WO2023201554A1 - 显示面板及显示装置 - Google Patents

显示面板及显示装置 Download PDF

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Publication number
WO2023201554A1
WO2023201554A1 PCT/CN2022/087809 CN2022087809W WO2023201554A1 WO 2023201554 A1 WO2023201554 A1 WO 2023201554A1 CN 2022087809 W CN2022087809 W CN 2022087809W WO 2023201554 A1 WO2023201554 A1 WO 2023201554A1
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WIPO (PCT)
Prior art keywords
data
display panel
line
display area
circuit
Prior art date
Application number
PCT/CN2022/087809
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English (en)
French (fr)
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WO2023201554A9 (zh
Inventor
马宏伟
何帆
董向丹
胡明
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to CN202280000784.0A priority Critical patent/CN117413309A/zh
Priority to PCT/CN2022/087809 priority patent/WO2023201554A1/zh
Publication of WO2023201554A1 publication Critical patent/WO2023201554A1/zh
Publication of WO2023201554A9 publication Critical patent/WO2023201554A9/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources

Definitions

  • the present disclosure relates to the field of display technology, and in particular, to a display panel and a display device.
  • a display panel includes a plurality of pixel driving circuits, a plurality of pads, a plurality of first data lines and at least one data lead.
  • the plurality of pixel driving circuits are arranged in the display area.
  • the plurality of pixel driving circuits form a plurality of circuit columns distributed along the first direction.
  • the circuit columns include at least two pixel driving circuits distributed along the second direction.
  • the second direction and The first direction crosses.
  • the plurality of pads are disposed in the non-display area and located on one side of the display area along the second direction.
  • a plurality of first data lines are disposed in the display area.
  • the first data lines extend along the second direction and are coupled to at least two pixel driving circuits in the circuit column.
  • the data lead is coupled to the first data line, the data lead extends from the display area to the non-display area, and is coupled to at least one pad.
  • the plurality of circuit columns form a plurality of circuit groups distributed along the first direction, the circuit group includes at least one circuit column, and the data leads are arranged between two adjacent circuit groups.
  • At least one data lead includes at least one first data lead, and a portion of the first data lead located in the display area is arranged on the same layer as the first data line.
  • At least one data lead includes at least one second data lead, and a portion of the second data lead located in the display area is arranged in a different layer from the first data line.
  • At least one data lead is a plurality of data leads, and the plurality of data leads further include at least one first data lead, and a portion of the first data lead located in the display area is arranged on the same layer as the first data line. In the thickness direction of the display panel, the first data lead and the second data lead do not overlap.
  • the display panel further includes a plurality of first signal lines.
  • a plurality of first signal lines are arranged in the display area, the first signal lines extend along a first direction, and the first signal lines include a plurality of first line segments and at least one second line segment.
  • the part of the second data lead located in the display area is arranged on the same layer as the first line segment, and is arranged between two adjacent first line segments. Two first line segments adjacent in the first direction are coupled through a second line segment, and the second line segment and the first line segment are arranged in different layers.
  • the display panel further includes at least one connection line disposed in the display area, and the connection line extends along the first direction.
  • the first data line is coupled to the data lead through the connection line, and the connection line is arranged on the same layer as the portion of the second data lead located in the display area.
  • the display panel further includes at least one connecting line. At least one connection line is provided in the display area, and the connection line extends along the first direction. The first data line is coupled to the data lead through the connecting line.
  • the display panel further includes a plurality of signal lines.
  • a plurality of signal lines are arranged in the display area, and the signal lines extend along the first direction.
  • the plurality of signal lines form a plurality of signal line groups distributed along the second direction, and one signal line group includes at least one signal line. At least part of the connecting line and the signal line are arranged on the same layer, and are arranged between two adjacent signal line groups.
  • the distance between every two adjacent signal line groups is approximately the same.
  • the display panel further includes a plurality of light-emitting devices, and the light-emitting devices are coupled to the pixel driving circuit.
  • the plurality of first data lines include a plurality of different-color data lines, and the different-color data lines are coupled to at least two light-emitting devices that emit different colors. Parts of all the data leads coupled to the plurality of data lines of different colors located in the display area are arranged on the same layer.
  • the display panel further includes at least one second data line extending from the display area to the non-display area along the second direction and coupled to at least one pad.
  • At least one data lead is a plurality of data leads, the plurality of data leads form a plurality of lead groups distributed along the first direction, and each data lead in the lead group is disposed between the same two circuit groups. . In the display area, among multiple lead wire groups, the distance between every two adjacent lead wire groups is approximately the same.
  • the display device includes: the display panel as described in any of the above embodiments.
  • the manufacturing method of the display panel includes forming a plurality of pixel driving circuits, a plurality of pads, a plurality of first data lines and at least one data lead on a substrate, and the plurality of pixel driving circuits form a plurality of pixel driving circuits distributed along a first direction.
  • the circuit column includes at least two pixel driving circuits distributed along the second direction, and the first direction and the second direction intersect.
  • the plurality of bonding pads are located on one side of the plurality of pixel driving circuits along the second direction.
  • the first data line extends along the second direction and is coupled to at least two pixel driving circuits in the circuit column.
  • the data leads extend along the second direction and are coupled to the first data line and at least one pad.
  • the plurality of circuit columns form a plurality of circuit groups distributed along the first direction.
  • the circuit groups include at least one circuit column.
  • the data leads are arranged on Between two adjacent circuit groups.
  • Figure 1 is a structural diagram of a display panel according to related technologies
  • Figure 2 is a structural diagram of a display device according to some embodiments.
  • Figures 3 and 4 are structural diagrams of display panels according to some embodiments.
  • Figure 5 is the equivalent circuit diagram of the pixel drive circuit
  • Figure 6 is a top view of multiple pixel driving circuits in a display panel according to some embodiments.
  • FIG. 7 to 9 are partial enlarged views of a display panel according to some embodiments.
  • Figure 10 is a partial enlarged view of area U2 in the display panel of the related art of Figure 1;
  • Figure 11 is a top view of a display panel according to some embodiments.
  • Figure 12 is a partial enlarged view of the display panel of Figure 11;
  • Figure 13 is a partial enlarged view of area U3 in the display panel of Figure 7;
  • Figure 14 is a partial enlarged view of area U4 in the display panel of Figure 8;
  • Figure 15 is a partial enlarged view of a display area of a display panel according to some embodiments.
  • first and second are used for descriptive purposes only and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Therefore, features defined as “first” and “second” may explicitly or implicitly include one or more of these features.
  • plural means two or more.
  • At least one of A, B and C has the same meaning as “at least one of A, B or C” and includes the following combinations of A, B and C: A only, B only, C only, A and B The combination of A and C, the combination of B and C, and the combination of A, B and C.
  • parallel includes absolutely parallel and approximately parallel, and the acceptable deviation range of approximately parallel may be, for example, a deviation within 5°;
  • perpendicular includes absolutely vertical and approximately vertical, and the acceptable deviation range of approximately vertical may also be, for example, Deviation within 5°.
  • equal includes absolute equality and approximate equality, wherein the difference between the two that may be equal within the acceptable deviation range of approximately equal is less than or equal to 5% of either one, for example.
  • Example embodiments are described herein with reference to cross-sectional illustrations and/or plan views that are idealized illustrations.
  • the thickness of layers and regions are exaggerated for clarity. Accordingly, variations from the shapes in the drawings due, for example, to manufacturing techniques and/or tolerances are contemplated.
  • example embodiments should not be construed as limited to the shapes of regions illustrated herein but are to include deviations in shapes that result from, for example, manufacturing. For example, an etched area shown as a rectangle will typically have curved features. Accordingly, the regions shown in the figures are schematic in nature and their shapes are not intended to illustrate the actual shapes of regions of the device and are not intended to limit the scope of the exemplary embodiments.
  • the display panel DP may have a display area AA', and the display panel DP may also have a display located on one side of the display area AA' (for example, located on one side of the display area AA' along the Y-axis negative direction).
  • Fan-out area FA', bending area BA' and binding area PA' can be arranged in sequence.
  • the fan-out area FA', the bending area BA' and the binding area PA' can be arranged in sequence.
  • the display panel DP may also include a plurality of data lines DB, a plurality of data leads DL, and a plurality of pads P.
  • a plurality of (for example, all) data lines DB are located in the display area AA'.
  • a data line DB (eg, each data line DB) may be configured to write data signals to the pixel driving circuit.
  • a plurality of pads P may be provided in the bonding area PA'.
  • a data line DB located in the display area AA' can be coupled to at least one pad P located in the bonding area PA' through a data lead.
  • a data lead DL (for example, each data lead DL) is coupled to a data line DB, and the data lead DL can also extend from the fan-out area FA' to the bending area BA' and the bonding area PA' , and is coupled to at least one (for example, one; another example, multiple) pads P disposed in the bonding area PA'.
  • a pad P (eg, each pad P) may be configured to be coupled with a data driving circuit (eg, a source driver). In this way, through one or more pads P, data leads DL, and data lines DB, electrical signals (eg, including data signals) output by the data driving circuit can be written into the pixel driving circuit.
  • the part of the display panel DP located in the bending area BA' can be bent, and then the part of the display panel DP located in the binding area PA' is bent to the back of the display panel DP, that is, the display panel DP faces the non-display surface. side.
  • the height h1 of the fan-out area FA' (for example, the size of the fan-out area FA' along the Y-axis direction) can affect the frame of the display panel DP (for example, the frame of one end of the display panel DP along the negative Y-axis direction).
  • the larger the size k1 and the height h1 of the fan-out area FA' the larger the size k1 of the lower frame of the display panel DP.
  • the size d1 of the bonding area PA' provided with multiple pads P along the first direction is smaller than the display provided with multiple data lines DB
  • the size of the area AA' along the first direction is d2. Therefore, in the fan-out area FA', the plurality of data leads DL may be arranged in a fan shape.
  • the frame size of the display panel DP can be reduced by reducing the number of data lines DB. Since the number of data lines DB is reduced, the number of oblique wirings in the fan-out area FA' can be reduced, thereby reducing the frame size of the display panel DP. However, reducing the number of data lines DB may result in a reduction in the number of light-emitting devices in the display panel DP, that is, a reduction in the resolution of the display panel DP. How to reduce the frame size of the display panel while ensuring the resolution of the display panel is currently an urgent problem that needs to be solved.
  • embodiments of the present disclosure provide a display panel, a manufacturing method thereof, and a display device.
  • FIG. 2 is a structural diagram of a display device according to some embodiments.
  • the display device 1 is a product with a function of displaying images (including static images or dynamic images, where the dynamic images may be videos).
  • the display device 1 can be: a monitor, a television, a billboard, a digital photo frame, a laser printer with a display function, a telephone, a mobile phone, a personal digital assistant (Personal Digital Assistant, PDA), a digital camera, a camcorder, a viewfinder Any of devices, navigators, vehicles, large-area walls, home appliances, information query equipment (such as business query equipment in e-government, banks, hospitals, electric power, etc.), monitors, etc.
  • PDA Personal Digital Assistant
  • the display device 1 includes a display panel 10 .
  • Display panel 10 may be configured to display images. The structure of the display panel 10 will be described in detail below.
  • the display device 1 may further include a driving control circuit 20 coupled to the display panel 10 .
  • the drive control circuit 20 is configured to provide an electrical signal to the display panel 10 , in response to which the display panel 10 may display an image.
  • the drive control circuit 20 may include a data drive circuit 210 (also known as a source driver IC).
  • the data drive circuit 210 is configured to provide a data drive signal (also known as a data signal) to the display panel 10 ).
  • the drive control circuit 20 may also include a timing control circuit 220 (which may also be called a timing controller, TCON for short) coupled to the data drive circuit 210.
  • a timing control circuit 220 (which may also be called a timing controller, TCON for short) coupled to the data drive circuit 210.
  • the drive control circuit 20 may further include a scan drive circuit 110 .
  • the scan driving circuit 110 may be integrated in the display panel 10 , or it can be said that the display panel 10 includes the scanning driving circuit 110 . Since the scan driver circuit 110 is provided in the display panel 10, the scan driver circuit 110 may also be called a GOA (Gate Driver on Array, a scan driver circuit provided on the array substrate).
  • GOA Gate Driver on Array
  • the timing control circuit 220 may be coupled to the data driving circuit 210 and may also be coupled to the scan driving circuit 110 .
  • the timing control circuit 220 may be configured to receive a display signal, which includes, for example, a power signal, a video image signal, a communication signal (such as a signal corresponding to the IIC communication protocol), and a mode control signal (such as a mode control signal corresponding to the test mode, or Mode control signal corresponding to normal display mode), etc.
  • the video image signal is, for example, MIPI (Mobile Industry Processor Interface, mobile industry processor interface) signal, LVDS (Low-Voltage Differential Signaling, low voltage differential signal) signal.
  • the video image signal may include: image data and timing control signals.
  • the image data includes, for example, pixel data of a plurality of sub-pixels, and the pixel data may be RGB data or the like.
  • the timing control signals include, for example, a data enable signal (Data Enable, which may be referred to as DE), a horizontal synchronization signal (Hsync, which may be referred to as HS), and a field synchronization signal (Vsync, which may be referred to as VS).
  • Data Enable which may be referred to as DE
  • Hsync horizontal synchronization signal
  • Vsync field synchronization signal
  • the timing control circuit 220 may also be configured to output a first control signal and image data to the data driving circuit 210 and a second control signal to the scan driving circuit 110 in response to the display signal.
  • the first control signal is configured to control the working timing of the data driving circuit 210
  • the second control signal is configured to control the working timing of the scan driving circuit 110 .
  • the data driving circuit 210 may be configured to convert the received image data into data signals for a plurality of light-emitting devices E (to be described below) in the display panel 10 and output the data signals according to the operating timing determined by the first control signal. to the pixel driving circuit D (to be described below) coupled to the corresponding light emitting device E.
  • the scan driving circuit 110 is configured to output scanning signals to the plurality of pixel driving circuits D according to the operating timing determined by the second control signal.
  • Some embodiments of the present disclosure also provide a display panel.
  • the display panel can be used as a display panel in the display device provided in any of the above embodiments.
  • the display panel can also be applied to other display devices, and the embodiments of the present disclosure are not limited thereto.
  • FIG. 3 and 4 are structural diagrams of display panels according to some embodiments. It should be noted that, for the sake of clarity of the drawing, FIG. 3 shows multiple pixel driving circuits, multiple light-emitting devices and multiple data lines in the display panel, while multiple data leads are omitted. Moreover, the specific structure of the non-display area is omitted in FIG. 3 . FIG. 4 shows multiple data lines and multiple data leads in the display panel, while multiple pixel driving circuits and multiple light-emitting devices are omitted.
  • the display panel 10 can be an OLED (Organic Light Emitting Diode, organic light-emitting diode) display panel, a QLED (Quantum Dot Light Emitting Diode, quantum dot light-emitting diode) display panel, or a micro-LED (including: MiniLED or MicroLED).
  • OLED Organic Light Emitting Diode, organic light-emitting diode
  • QLED Quantum Dot Light Emitting Diode, quantum dot light-emitting diode
  • micro-LED including: MiniLED or MicroLED.
  • LED is a type of light-emitting diode (LED) display panel.
  • the display panel 10 has a display area AA.
  • the portion of the display panel 10 located in the display area AA can display images.
  • the display panel 10 also has a non-display area SA.
  • the non-display area SA may be located on at least one side of the display area AA (for example, one side; another example, all around, including the upper and lower sides and the left and right sides).
  • the non-display area SA of the display panel 10 may include a binding area PA.
  • the non-display area SA of the display panel 10 may also include a fan-out area FA and a bending area BA.
  • the fan-out area FA, the bending area BA, and the binding area PA may be located on one side of the display area AA (for example, located on one side of the display area AA along the negative Y-axis direction). Moreover, the fan-out area FA, the bending area BA, and the binding area PA can be arranged in sequence. For example, the fan-out area FA, the bending area BA, and the binding area PA can be arranged in sequence along the negative direction of the Y-axis.
  • the display panel 10 may include a plurality of light emitting devices E.
  • a plurality of (eg, all) light emitting devices E may be disposed in the display area AA.
  • the light-emitting device E may emit light.
  • the light-emitting device E may emit one of red light, green light, blue light or white light.
  • the light-emitting device E may be one of an organic light-emitting diode OLED, a quantum dot light-emitting diode QLED, or a light-emitting diode LED.
  • the display panel 10 may further include a plurality of pixel driving circuits D.
  • a plurality of (for example, all) pixel driving circuits D are provided in the display area AA.
  • a pixel driving circuit D (eg, each pixel driving circuit D) may be coupled to a light emitting device E.
  • the pixel driving circuit D may be configured to respond to the received scanning signal and data signal (for example, the scanning signal output by the scanning driving circuit and the data signal output by the data driving circuit), to the light emitting device E coupled with the pixel driving circuit D.
  • An electrical signal (such as a driving voltage or a driving current) is provided to drive the light-emitting device E to emit light, so that the display panel 10 can display an image.
  • the pixel driving circuit D may include a plurality of transistors and at least one (for example, one; also, for example, a plurality of) capacitors.
  • the pixel driving circuit D may have a structure such as "2T1C", “6T1C”, “7T1C”, “6T2C” or "7T2C".
  • T represents a transistor, such as a thin film transistor.
  • the number in front of the “T” indicates the number of transistors.
  • “C” represents a capacitor, and the number in front of "C” represents the number of capacitors.
  • the structure, function and connection relationship of the components (such as transistors or capacitors) in the pixel driving circuit D can be similar to the pixel driving circuit D with a structure of 7T1C. Please refer to the following relevant information. illustrate.
  • all transistors in the pixel driving circuit D are LTPS (Low Temperature Poly-Silicon) transistors.
  • the material of the active layer of the LTPS transistor may include polysilicon.
  • one or more (for example, two) transistors in the pixel driving circuit D are oxide transistors, and the material of the active layer of the oxide transistor may include an oxide, such as IGZO (Indium Gallium Zinc Oxide). , indium gallium zinc oxide).
  • the pixel driving circuit D may also be called an LTPO (Low-Temperature Polycrystalline Oxide, low-temperature polycrystalline oxide) type pixel driving circuit.
  • FIG. 6 is a top view of multiple pixel driving circuits in a display panel according to some embodiments. It should be noted that only a plurality of conductor pattern layers are shown in FIG. 6 , and other film layers, such as active layers, are omitted.
  • the pixel driving circuit D may have a 7T1C structure, that is, the pixel driving circuit D may include 7 transistors, such as a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, and a fifth transistor T5. , a sixth transistor T6 and a seventh transistor T7.
  • the pixel driving circuit D may also include a capacitor C.
  • the working process of the pixel driving circuit D may include the following three stages:
  • the first transistor T1 in response to the first scan signal GA1, the first transistor T1 is turned on, thereby writing the first reset signal Vint1 into the gate of the third transistor T3. In this way, the gate of the third transistor T3 can be reset.
  • the second transistor T2, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 may all be turned off.
  • the fourth transistor T4 is turned on.
  • the second transistor T2 is turned on.
  • the data signal DA can be written into the gate of the third transistor T3, so that the gate voltage of the third transistor T3 can be V DA + V th , where V DA is the data signal DA.
  • the voltage of V th is the threshold voltage of the third transistor T3.
  • the first transistor T1, the fifth transistor T5, and the sixth transistor T6 may all be turned off.
  • the seventh transistor T7 may also be turned on in response to the fourth scan signal GA4, thereby writing the second reset signal Vint2 to the light emitting device E. In this way, the light emitting device E can be reset.
  • the gate of the fourth transistor T4 and the gate of the seventh transistor T7 can be connected in series with each other, so that in the second stage, both the fourth transistor T4 and the seventh transistor T7 can be turned on, and then in the second stage In the second stage, the data signal DA can be written into the gate of the third transistor T3, and the light-emitting device E can also be reset.
  • the above-mentioned step of writing the second reset signal Vint2 into the light-emitting device E may be performed in the first stage.
  • the gate of the first transistor T1 and the gate of the seventh transistor T7 can be connected in series with each other, so that in the first stage, both the first transistor T1 and the seventh transistor T7 can be turned on, and then in the first stage, the gate of the first transistor T1 and the seventh transistor T7 can be turned on. Both the third transistor T3 and the light emitting device E are reset.
  • the fifth transistor T5 in response to the fifth scan signal GA5, the fifth transistor T5 is turned on.
  • the power supply voltage signal VDD can be written into the first electrode (for example, the source electrode) of the third transistor T3, so that the voltage of the first electrode of the third transistor T3 is VDD.
  • the third transistor T3 can generate a driving current flowing through the first and second poles (for example, the drain) of the third transistor T3 in response to the voltage VDD on its first pole and the gate voltage V DA +V th .
  • the sixth transistor T6 in response to the sixth scan signal GA6, the sixth transistor T6 is turned on. Through the sixth transistor T6, the driving current generated by the third transistor T3 can flow into the light-emitting device E to drive the light-emitting device E to emit light.
  • the first transistor T1, the second transistor T2, the fourth transistor T4, and the seventh transistor T7 may all be turned off.
  • the display panel may include an active layer (not shown in the figures) and a plurality of conductor pattern layers, such as a first conductor pattern layer 160 and a second conductor pattern layer 170 .
  • the active layer and the plurality of conductor pattern layers may form one or more of the above-mentioned pixel driving circuits D.
  • the conductor pattern layer may also include one or more signal lines.
  • One signal line may be configured to write the above-mentioned electrical signals (such as data signal DA, first scan signal GA1, second scan signal GA2, third scan signal GA3, fourth scan signal GA4, fifth scan signal GA4, etc.) to the pixel driving circuit D.
  • the multiple electrical signals may be the same.
  • the first conductor pattern layer 160 may include a plurality of first data lines 141 .
  • the first data line 141 may be coupled with the fourth transistor T4 in the pixel driving circuit D.
  • the first data line 141 may be configured to write the data signal DA to the pixel driving circuit D.
  • the first conductor pattern layer 160 may further include a plurality of power supply voltage signal lines 161 .
  • the first power supply voltage signal line 161 may be coupled with the fifth transistor T5 in the pixel driving circuit D.
  • the first power supply voltage signal line 161 may be configured to write the power supply voltage signal VDD to the pixel driving circuit D.
  • the first conductor pattern layer 160 may further include one or more connection patterns CP.
  • connection pattern CP may be part of the pixel driving circuit D.
  • the connection pattern CP may be configured to couple two elements in the pixel driving circuit D (the elements in the pixel driving circuit D are, for example, transistors or capacitors).
  • the connection pattern CP may also be configured to couple the pixel driving circuit D to other elements other than the pixel driving circuit D, for example, to couple the pixel driving circuit D to the light emitting device E.
  • the second conductor pattern layer 170 may include a plurality of reset signal lines 171 .
  • the reset signal line 171 may be coupled with the seventh transistor T7 in the pixel driving circuit D.
  • the reset signal line 171 may be configured to write the second reset signal Vint2 to the pixel driving circuit D.
  • the second conductor pattern layer 170 may also include one or more connection patterns CP.
  • a pixel driving circuit D can be the smallest unit capable of realizing the above-mentioned functions, as shown in FIG. 6 .
  • the pixel driving circuit D is coupled to one or more signal lines.
  • a signal line can be in contact with the pixel driving circuit to realize mutual coupling between the two. Therefore, when the position of the pixel driving circuit D changes, the position of one or more signal lines coupled to the pixel driving circuit D will also change accordingly.
  • a part of a signal line can be configured to define the boundary of the pixel driving circuit D.
  • a position where a signal line and the pixel driving circuit contact each other can be configured to define the boundary of the pixel driving circuit.
  • a part of the first data line 141 coupled to the pixel driving circuit D1 may serve as the left boundary D1a of the pixel driving circuit D1 (for example, the boundary of the pixel driving circuit D1 along the negative direction of the X-axis).
  • a part of the first data line 141 coupled to the pixel driving circuit D2 may serve as the right boundary D2b of the pixel driving circuit D2 (for example, the boundary of the pixel driving circuit D2 along the positive direction of the X-axis).
  • a plurality of pixel driving circuits D may form a plurality of circuit columns 120 distributed along a first direction (eg, parallel to the X-axis direction).
  • a circuit column 120 (eg, each circuit column 120) includes at least two pixel driving circuits D distributed along a second direction (eg, parallel to the Y-axis direction).
  • a plurality of pixel driving circuits D may be distributed in an array.
  • the first direction and the second direction intersect, for example, the first direction is perpendicular to the second direction.
  • the first direction (eg, parallel to the X-axis direction) and the second direction (eg, parallel to the Y-axis direction) may be parallel to the extension direction of the display panel 10 .
  • the display panel 10 includes a plurality of pads 130 .
  • a plurality of pads 130 are provided in the non-display area SA.
  • a plurality (eg, all) of the pads 130 may be located on one side of the display area AA along the second direction (eg, parallel to the Y-axis direction).
  • the bonding area PA may be located on one side of the display area AA along the second direction, for example, on one side of the display area AA along the negative Y-axis direction, and multiple (eg, all) pads 130 may be located on the bonding area In PA.
  • a pad 130 may be configured to couple with a data drive control circuit (ie, a source driver).
  • a data drive control circuit ie, a source driver
  • the pad 130 may be coupled to the data driving control circuit through anisotropic conductive glue.
  • the display panel 10 further includes a plurality of first data lines 141 .
  • a plurality of (for example, all) first data lines 141 are provided in the display area AA.
  • a first data line 141 (eg, each first data line 141 ) extends along a second direction (eg, parallel to the Y-axis direction) and is coupled to at least two pixel driving circuits D in a circuit column 120 .
  • a first data line 141 may be coupled to two pixel driving circuits D in a circuit column 120 .
  • a first data line 141 may be coupled to all pixel driving circuits D in a circuit column 120 .
  • the display panel 10 further includes at least one (for example, one; also, for example, multiple) data leads 150 .
  • a data lead 150 (eg, each data lead 150) is coupled to a first data line 141.
  • a data lead 150 (eg, each data lead 150) extends from the display area AA to the non-display area SA.
  • the data lead 150 is coupled to at least one (eg, one; another example, multiple) pads 130 .
  • a first data line 141 can be coupled to at least one pad 130 through a data lead 150 .
  • a data lead 150 may include a first portion and a second portion coupled to each other, wherein the first portion is located in the display area AA.
  • the first part may be a straight line extending in the second direction.
  • the second part is located in the non-display area.
  • the second portion may be coupled to at least one pad 130 .
  • a pad 130 may be configured to couple with the data driving circuit.
  • a data lead 150 is coupled to at least one pad 130, the data lead 150 is also coupled to a first data line 141, and a first data line 141 drives at least two pixels in a circuit column 120.
  • Circuit coupling Based on this, at least two (eg, all) pixel driving circuits D in a circuit column 120 can be coupled to the data driving circuit through the first data line and the data lead, so that the data signal output by the data driving circuit can be written into the circuit. At least two (eg, all) pixels in column 120 drive circuit D.
  • the plurality of light-emitting devices E coupled to the at least two pixel driving circuits D can emit light, so that the display panel 10 can display images.
  • FIGS. 7 to 9 are partial enlarged views of a display panel according to some embodiments, showing the locations of data leads and pixel driving circuits. It should be noted that, for the sake of simplicity of the drawings, the light-emitting device and the specific structure of the pixel driving circuit are omitted in FIGS. 7 to 9 , and only the relative positions of the pixel driving circuit and the data leads are shown.
  • a plurality of circuit columns 120 form a plurality of circuit groups DG distributed along a first direction (eg, parallel to the X-axis direction).
  • a circuit group DG (eg, each circuit group DG) includes at least one (eg, one; another example, multiple) circuit columns 120 .
  • a data lead 150 is provided between two adjacent circuit groups DG. It can also be said that a data line 150 can be disposed between two adjacent pixel driving circuits D.
  • the two pixel driving circuits D respectively belong to two adjacent circuit groups DG. It should be noted that the adjacent position of two circuit groups DG may mean that there is no other circuit group DG between the two circuit groups DG. Similarly, two pixel driving circuits D being adjacently located may mean that there are no other pixel driving circuits D between the two pixel driving circuits D.
  • Embodiments of the present disclosure do not limit the number of data leads 150 provided between two adjacent circuit groups DG.
  • a data lead 150 is provided between two adjacent circuit groups DG.
  • a plurality of data leads 150 are provided between two adjacent circuit groups DG.
  • FIG. 10 is a partial enlarged view of area U2 in the related art display panel shown in FIG. 1 .
  • FIG. 7 to FIG. 9 show the structure of the area U1 in the display panel according to some embodiments.
  • Eight pixel driving circuits are provided in the area U1.
  • FIG. 8 shows the structure of area U2 in a display panel of the related art.
  • Eight pixel driving circuits are also provided in area U2.
  • a data lead 150 (for example, each data lead 150 ) is disposed between two adjacent circuit groups DG, in the area Under the premise that the size t1 of U1 along the first direction (for example, parallel to the X-axis direction) is the same as the size t2 of the area U2 along the first direction, in the display panel according to the embodiment of the present disclosure, a pixel driving circuit D (for example, The size r1 of each pixel driving circuit D) along the first direction may be smaller than the size r2 along the first direction of a pixel driving circuit D' in the related art.
  • the display panel provided according to the embodiment of the present disclosure, it is possible to reduce the size of the pixel driving circuit D in the first direction without increasing the size of the display panel and reducing the number of pixel driving circuits.
  • a certain space is set between two adjacent circuit groups DG, and this space can be used to set one or more data leads 150 .
  • one or more of the multiple conductor pattern layers also have a certain space at the corresponding position, and the data leads can be arranged at in corresponding spaces of the one or more conductor pattern layers.
  • at least one (for example, one; also, for example, multiple) data leads 150 can be provided in the display area AA.
  • a data lead 150 may be closer to the center line 10 c of the display panel 10 than the first data line 141 coupled to the data lead 150 .
  • the center line 10c is the center line of the display panel along the first direction (for example, parallel to the X-axis direction).
  • the oblique wiring in the fan-out area FA of the display panel 10 (for example, the second one of the data leads 150
  • the inclination angle o1 (for example, the angle between the extension direction of the oblique wiring and the negative direction of the Y-axis) of the part located in the fan-out area FA and whose extension direction is not parallel to the Y-axis) may be smaller than the fan-out area FA of the display panel DP
  • the inclination angle o2 of the oblique wiring in ' may be smaller than the fan-out area FA of the display panel DP.
  • the height h2 of the fan-out area FA in the display panel 10 can be smaller than the height h1 of the fan-out area FA' in the display panel DP, thereby making the size k2 of the frame of the display panel 10 (ie, the frame with the fan-out area) smaller than the display panel 10 .
  • the frame size k1 of the panel DP is determined on the above, in the display panel provided by the embodiment of the present disclosure, at least one (for example, one; also, for example, multiple) data leads 150 can be provided in the display area AA without reducing the number of pixel driving circuits. , the frame size of the display panel can be reduced without increasing the size of the display panel and without reducing the resolution of the display panel.
  • At least one (eg, one; another example, multiple) data leads 150 includes at least one (eg, one; another example, multiple) first data leads 151 .
  • the portion 151a of a first data lead 151 (for example, each first data lead 151) located in the display area AA (ie, the first portion of the first data lead 151) is arranged on the same layer as the first data line.
  • the data lead 150 is the first data lead 151 . It can also be said that the portion of the data lead 150 located in the display area AA is arranged on the same layer as the first data line.
  • the display panel includes a plurality of data lead lines 150 and the plurality of data lead lines 150 include a first data lead line 151 , one of the plurality of data lead lines 150 is the first data lead line 151 . It can also be said that the portion of one of the plurality of data leads 150 located in the display area AA is arranged on the same layer as the first data line.
  • the display panel includes a plurality of data lead lines 150 and the plurality of data lead lines 150 include a plurality of first data lead lines 151
  • a plurality of (for example, part of; another example, all of) the plurality of data lead lines 150 ) is the first data lead 151. It can also be said that each part of some or all of the data leads 150 located in the display area AA is arranged on the same layer as the first data line.
  • the portion 151 a of the first data lead 151 located in the display area AA and the first data line 141 are both located in the first conductor pattern layer 160 .
  • the first data line 141 is located in the display area AA and extends along the second direction. Furthermore, the portion 151a of the first data lead 151 located in the display area AA, that is, the first portion 151a of the first data lead 151, may also extend in the second direction. That is, the extending direction of the first portion 151a of the first data lead 151 and the first data line 141 may be the same. Therefore, the portion 151a of the first data lead 151 located in the display area AA can be arranged in the same layer as the first data line 141.
  • the display panel may include fewer pattern layers such that the thickness of the display panel It can be smaller, which is beneficial to the thinning of the display panel and the display device.
  • At least one (eg, one; another example, multiple) data leads 150 includes at least one (eg, one; another example, multiple) second data leads 152 .
  • the portion 152a of a second data lead 152 eg, each second data lead 152 located in the display area AA (ie, the first portion 152a of the second data lead 152) is arranged in a different layer from the first data line.
  • the data lead 150 is the second data lead 152 . It can also be said that the portion of the data lead 150 located in the display area AA is arranged in a different layer from the first data line.
  • the display panel includes a plurality of data lead lines 150 and the plurality of data lead lines 150 includes a second data lead line 152, one of the plurality of data lead lines 150 is the second data lead line 152. It can also be said that the portion of one of the plurality of data leads 150 located in the display area AA is arranged in a different layer from the first data line.
  • the display panel includes a plurality of data lead lines 150 and the plurality of data lead lines 150 include a plurality of second data lead lines 152
  • a plurality of (for example, part of; another example, all of) the plurality of data lead lines 150 ) is the second data lead 152. It can also be said that each part of some or all of the data leads 150 located in the display area AA is arranged in a different layer from the first data line.
  • the portion 152a of the second data lead 152 located in the display area AA is arranged in a different layer from the first data line, the influence of the second data lead 152 on the first data line 141 can be reduced, and the relationship between the two signal lines can be improved. Signal crosstalk problem.
  • the first data line 141 is located in the first conductor pattern layer 160 .
  • the portion 152 a of the second data lead 152 located in the display area AA is located in the second conductor pattern layer 170 .
  • the display panel can include fewer pattern layers, so that the thickness of the display panel can be smaller, which is beneficial to the thinning of the display panel and the display device.
  • the display panel includes a plurality of data leads 150 .
  • the plurality of data leads 150 includes at least one first data lead 151 .
  • the portion 151a of a first data lead 151 (for example, each first data lead 151) located in the display area AA is arranged on the same layer as the first data line.
  • the plurality of data leads 150 also includes at least one second data lead 152 .
  • the portion 152a of a second data lead 152 (for example, each second data lead 152) located in the display area AA is arranged in a different layer from the first data line.
  • the portion 151a of a first data lead 151 (eg, each first data lead 151) located in the display area AA and the portion 152a of a second data lead 152 located in the display area AA are arranged in different layers. In this way, under the premise that the distance between two adjacent circuit groups CG is constant, more data leads can be arranged in the corresponding spaces of the two conductor pattern layers.
  • a first data lead 151 for example, each first data lead 151 and a second data lead 152 are not in contact with each other. overlap. In this way, the signal crosstalk between the first data lead 151 and the second data lead 152 can be reduced, and the display effect of the display panel can be improved. It can be understood that since a first data lead 151 (for example, each first data lead 151) does not overlap with the second data lead 152, accordingly, the portion 151a of the first data lead 151 located in the display area AA and The portion 152a of the second data lead 152 located in the display area AA also does not overlap.
  • display panel 10 includes at least one data lead 150 including at least one second data lead 152 .
  • the display panel 10 also includes a plurality of first signal lines 171 .
  • a plurality of (for example, all) first signal lines 171 are provided in the display area.
  • the first signal line 171 may be coupled with the seventh transistor (T7 in FIG. 5) in the pixel driving circuit D.
  • the first signal line 171 may be configured to write the second reset signal to the pixel driving circuit D.
  • the first signal line 171 may also be called a reset signal line.
  • a first signal line 171 (for example, each first signal line 171) extends along a first direction (for example, parallel to the X-axis direction).
  • a first signal line 171 (for example, each first signal line 171) extends along the first direction and is coupled to a plurality of pixel driving circuits D distributed along the first direction.
  • FIG. 12 is a partial enlarged view of the display panel of FIG. 11 . It should be noted that, for the sake of clarity of the drawing, only the first signal line and the data lead line are shown in FIG. 12 , and other patterns are omitted.
  • a first signal line 171 (eg, each first signal line 171 ) includes a plurality of first line segments 171 a and at least one (eg, one; another example, multiple) second line segments 171 b.
  • the portion 152a of a second data lead (eg, each second data lead) located in the display area (ie, the first part of the second data lead) is arranged on the same layer as the first line segment 171a.
  • the portion 152a of the second data lead located in the display area and the first line segment 171a are both located in the second conductor pattern layer 170.
  • portion 152a of a second data lead (eg, each second data lead) located in the display area is disposed between two adjacent first line segments 171a. It should be noted that the adjacent position of two first line segments 171a may mean that there is no other first line segment 171a between the two first line segments 171a.
  • first line segments 171a that are adjacent in the first direction are coupled by a second line segment 171b, and the second line segment 171b is connected to the first Line segments 171a are arranged in different layers.
  • second line segment 171b and the first portion 152a of one or more second data leads located between the two first line segments 171a are arranged in different layers.
  • the first part 152a of the second data lead extending in the second direction may not contact the first signal line 171 extending in the first direction, and the second data lead may be located in the display area.
  • the portion 152a and the first line segment 171a of the first signal line 171 can be arranged on the same layer without being short-circuited to each other.
  • a first line segment 171a (eg, each first line segment 171a) and a first portion 152a of a second data lead (eg, each second data lead) may be included in the second conductor pattern layer 170
  • a second line segment 171b (eg, each second line segment 171b) may be included in the third conductor pattern layer 180.
  • the third conductor pattern layer 180 may be a conductor pattern layer.
  • the third conductor pattern layer 180 may include a plurality of signal lines, and may also include one or more connection patterns.
  • the third conductor pattern layer 180 may include a plurality of signal lines extending in a first direction (eg, parallel to the X-axis direction), and the signal lines may be configured to transmit a first scan signal (ie, the first scan signal in FIG. 5 signal GA1) or the third scanning signal (ie, the third scanning signal GA3 in Figure 5).
  • a first scan signal ie, the first scan signal in FIG. 5 signal GA1
  • the third scanning signal ie, the third scanning signal GA3 in Figure 5
  • the third conductor pattern layer 180, the second conductor pattern layer 170, and the first conductor pattern layer 160 may be disposed in sequence.
  • the plurality of pixel driving circuits D there are multiple arrangements possible in the display panel. In different arrangements, the number of data leads 150 between two adjacent circuit groups DG may be different. The arrangement of the plurality of pixel driving circuits D and the corresponding number of data leads 150 will be described in detail below.
  • FIG. 13 is a partial enlarged view of area U3 in the display panel of FIG. 7 .
  • FIG. 14 is a partial enlarged view of area U4 in the display panel of FIG. 8 .
  • the distance between two patterns arranged on the same layer needs to be considered.
  • the minimum distance between two patterns set on the same layer should be greater than or equal to a critical value. Too close a distance between two patterns on the same layer may cause signal crosstalk.
  • multiple patterns "set in the same layer” means that multiple patterns belong to the same pattern layer, that is, multiple patterns are formed through the same patterning process.
  • the patterning process refers to a process that can form multiple patterns at the same time.
  • the patterning process may be evaporation or printing.
  • the patterning process may include: first forming a thin film using a film forming process, and then patterning the thin film to form a pattern layer containing multiple patterns.
  • the patterning process may include: coating photoresist, exposure, development, etching and other processes.
  • multiple patterns may be at least partially connected or spaced apart from each other.
  • the plurality of patterns may have different thicknesses (eg, the size of the pattern along the thickness direction of the display panel).
  • the minimum allowable distance between two patterns arranged on the same layer and adjacent in position is recorded as W1, that is, the distance between two patterns arranged in the same layer and adjacent in position. Should be greater than or equal to W1. It should be noted that two adjacent patterns may mean that there are no other patterns between the two patterns in the same pattern layer.
  • the width of the first data lead 151 (for example, the size of the first data lead 151 along the width direction of the first data lead 151, the width direction of the first portion 151a of the first data lead 151 is perpendicular to its extension direction, the first data lead 151 is The width direction of the first portion 151a is, for example, parallel to the X-axis direction) and is denoted as W2.
  • the width of the first portion 152a of the second data lead (for example, the size of the first portion 152a of the second data lead along the width direction of the second data lead 152, the width direction of the second data lead 152 is perpendicular to its extension direction, the second data
  • the width direction of the lead 152 (for example, parallel to the X-axis direction) may be the same as the width of the first portion 151a of the first data lead.
  • the width of the first portion 152a of the second data lead may also be noted as W2.
  • a circuit group DG (eg, each circuit group DG) includes one circuit column 120 . There is a certain space between two adjacent circuit groups DG. It can also be said that there is a certain space between two adjacent circuit columns 120 . At least one (eg, one; eg, multiple) data leads 150 may be disposed in the space. It should be noted that two adjacent circuit columns may mean that there are no other circuit columns between the two circuit columns.
  • the minimum distance that allows one data lead to be provided between two adjacent circuit columns 120 is denoted as W3 (hereinafter, this distance is referred to as the first distance).
  • the minimum distance that allows one data lead 150 to be disposed between two adjacent circuit columns 120 may mean: on a conductor pattern layer including at least one data lead 150 (for example, one or more first data lines 150 ).
  • the first conductor pattern layer of the leads, or the second conductor pattern layer including one or more second data leads) respectively corresponds to the two adjacent circuit columns 120 and is opposite to the position of the data lead 150.
  • the minimum distance between two adjacent patterns are examples of the leads.
  • a pattern corresponding to a circuit column 120 may mean that the pattern is part of one or more pixel driving circuits D in the circuit column 120.
  • the pattern is configured to be a part of a pixel driving circuit D in the circuit column 120. Multiple components are coupled.
  • a pattern corresponding to a circuit column 120 may also mean that the pattern is coupled to one or more pixel driving circuits D in the circuit column 120 .
  • the pattern is configured to drive one or more pixel driving circuits D in the circuit column 120 .
  • An electrical signal is written into a pixel driving circuit D.
  • the pattern is a signal line, such as a first data line or a power supply voltage signal line.
  • the pattern is configured to couple one or more pixel driving circuits D in the circuit column 120 to other elements.
  • the pattern is configured to couple one pixel driving circuit D to the light-emitting device E.
  • a circuit group DG (eg, each circuit group DG) includes a plurality of circuit columns 120 .
  • a circuit group DG includes two circuit columns 120 .
  • a circuit group DG includes four circuit columns 120 .
  • a circuit group DG includes two In the case of circuit column 120, the distance between two adjacent circuit groups DG is 2W3 (hereinafter referred to as the second distance), and the second distance allows M1 (M1 ⁇ 2) data leads to be set. Of course, the actual number of settings is N1, N1 ⁇ M1.
  • the second distance may mean: between a conductor pattern layer including a plurality of data leads 150 (for example, a first conductor pattern layer including a plurality of first data leads arranged on the same layer, or a conductor pattern layer including a plurality of second data leads arranged on the same layer).
  • the distances between the two patterns corresponding to the two adjacent circuit columns 120 and the N data lead lines 150 are adjacent to each other.
  • the two adjacent circuit columns 120 refer to the two circuit columns 120 that respectively belong to the two adjacent circuit groups DG and are close to each other.
  • two data leads of the same layer can be set in the space of size 2W3.
  • One or more data leads may be arranged using the space of size W1. For example, more first data leads may be arranged in corresponding spaces of the first conductor pattern layer.
  • one or more second data leads may be disposed in corresponding spaces of the second conductor pattern layer. Based on the above, it can also be said that for an area corresponding to four circuit columns, when a circuit group DG includes two circuit columns 120 , more than four data leads can be provided in this area.
  • a circuit group DG includes four
  • the distance between two adjacent circuit groups DG is 4W3 (hereinafter referred to as the third distance)
  • M2 (M2 ⁇ 4) data leads to be set.
  • N2 ⁇ M2 the actual number of settings
  • the third distance may be similar to the second distance described above, and reference may be made to the relevant description above, which will not be described again here. Based on the above, 5 data leads on the same layer can be set up in a space of size 4W3.
  • W3 W2+2W1
  • One or more data leads may be arranged using the space with a size of 2W1-W2.
  • more first data leads may be arranged in corresponding spaces of the first conductor pattern layer.
  • one or more second data leads may be disposed in corresponding spaces of the second conductor pattern layer.
  • circuit group DG includes four circuit columns 120 , more than five circuit columns (for example, 6 circuit columns; another example, 7 circuit columns 120 ) can be provided in the region. bar) data lead 150.
  • circuit group DG includes more (for example, greater than or equal to 5) circuit columns 120, the size of the display panel along the first direction is constant and the size of the pixel driving circuit along the first direction is constant. Under this condition, more data leads can be provided between two adjacent circuit groups DG, that is, more data leads can be provided in the display panel.
  • the length q1 of the portion of the data lead 150 located in the display area AA first increases and then decreases.
  • a data lead 150 (for example, each data lead 150) is located in the part of the display area AA, that is, the length q1 of the first part of the protective gear 150 can be the length q1 of the first part along the second direction (for example, parallel to the Y-axis direction) size. In this way, the multiple data leads 150 are evenly distributed, which can improve the structural stability of the display panel.
  • the display panel further includes a plurality of light-emitting devices E, and one light-emitting device E is coupled to a pixel driving circuit D.
  • the plurality of first data lines 141 include a plurality of different-color data lines. It can also be said that a plurality of the first data lines 141 are different-color data lines.
  • a different-color data line (eg, each different-color data line) extends along a second direction (eg, parallel to the Y direction) and is coupled to at least two pixel driving circuits D in a circuit column 120 .
  • a different-color data line (for example, each different-color data line) is coupled to at least two light-emitting devices E that emit different colors.
  • All data leads 150 coupled to multiple (for example, all) data lines of different colors are arranged on the same layer.
  • all data leads 150 coupled to a plurality of (for example, all) different-color data lines are first data leads 151 and are included in the first conductor pattern layer 160 .
  • the difference in electrical load on the two data leads (for example, caused by the parasitic capacitance in the pixel drive circuit) can Smaller, so that the difference in the electrical signals output by the two data leads to the pixel driving circuit D can be smaller.
  • the display effect of the display panel can be improved.
  • the different-color data lines are coupled to at least two light-emitting devices E with different emitting colors, the frequency of changes in the electrical signals transmitted on the different-color data lines may be larger. Based on this, since all the data leads 150 coupled to multiple (for example, all) different-color data lines are arranged on the same layer, the display effect of the display panel can be further improved.
  • the display panel further includes at least one (eg, one; another example, multiple) second data lines 142 .
  • a second data line 142 (for example, each second data line 142) extends from the display area AA to the non-display area SA along a second direction (for example, parallel to the Y-axis direction), and is connected to at least one (for example, one; also such as , multiple) pads P are coupled.
  • a second data line 142 extends along the second direction from the display area AA to the fan-out area FA, the bending area BA and the bonding area PA, and is coupled to at least one pad P located in the bonding area PA.
  • the second data line 142 may be coupled to at least one pad P without connecting lines and data leads. Therefore, since the display includes at least one second data line 142, the structure of the display panel may be simpler, and the quality of the display panel may be improved. Rate.
  • the display panel includes a plurality of data leads 150 .
  • the plurality of data leads 150 form a plurality of lead groups LG distributed along a first direction (eg, parallel to the X-axis direction).
  • Each data lead 150 in a lead group LG (eg, each lead group LG) is disposed on the same two between circuit groups DG. It can also be said that a lead group LG is provided between two adjacent circuit groups DG.
  • the distance q1 between every two adjacent lead wire groups LG is approximately the same. It should be noted that the adjacent positions of two lead wire groups LG may mean that there are no other lead wire groups LG between the two lead wire groups LG.
  • the distance q1 between two adjacent lead groups LG may be the minimum distance between two data leads 150 that respectively belong to the two lead groups LG and are close to each other. Since the distance q1 between every two adjacent lead groups LG in the display area is approximately the same, the number of circuit columns 120 in each circuit group DG in the display panel can be the same.
  • the structure of the display panel can be relatively uniform.
  • the size of each of the plurality of circuit groups DG along the first direction (for example, parallel to the X-axis direction) may be approximately the same. In this way, the structure of the display panel may be relatively uniform and the structural stability of the display panel may be improved.
  • FIG. 15 is a partial enlarged view of a display area of a display panel according to some embodiments, showing the relative positions of connection lines, data leads and first signal lines. It should be noted that, for the sake of simplicity of the drawing, only a plurality of connection lines, a plurality of data leads and a plurality of first signal lines are shown in FIG. 15 , while other structures are omitted.
  • the display panel further includes at least one (for example, one; also, for example, multiple) connection lines 172 .
  • a connection line 172 (for example, each connection line 172) is disposed in the display area AA.
  • a connecting line 172 (eg, each connecting line 172) extends along a first direction (eg, parallel to the X-axis direction).
  • the first data line 141 is coupled to the data lead 150 through the connection line 172 .
  • a connection line 172 can be coupled to the first data line 141, and the connection line 172 can also be coupled to the first data lead 151 or the second data lead 152, so that through the connection line 172, a first The data lead 141 may be coupled to a first data lead 151 or a second data lead 152 .
  • the display panel further includes at least one connection line 172 , and the display panel further includes a plurality of signal lines, and the plurality of signal lines are disposed in the display area AA.
  • a signal line (for example, each signal line) extends along a first direction (for example, parallel to the X-axis direction).
  • one signal line (for example, each signal line) is the first signal line 171 .
  • the signal lines may also be other types of signal lines, and embodiments of the present disclosure are not limited to this, as long as the signal lines are arranged in the display area AA and extend along the first direction. In the following, description will be made taking the signal line as the first signal line as an example.
  • the plurality of signal lines form a plurality of signal line groups SG distributed along the second direction (for example, parallel to the Y-axis direction), and a signal line group SG includes at least one (for example, One; another example, multiple) signal lines.
  • a connection line 172 (for example, each connection line 172) is arranged on the same layer as at least a part (for example, part; another example, all) of the signal line, and is arranged between two adjacent signal line groups SG. It should be noted that the adjacent positions of two signal line groups SG may mean that there are no other signal line groups SG between the two signal line groups SG.
  • connection line 172 is arranged on the same layer as the first line segment 171a of the first signal line.
  • a connection line 172 is arranged on the same layer as the first line segment 171a of the first signal line.
  • the line segments 171a are all included in the second conductor pattern layer 170.
  • connection line 172 extends along the first direction, and a signal line also extends along the first direction, based on this, a connection line 172 can be disposed on the same layer as at least a part of a signal line, and can be disposed on two adjacent signal lines. between the line groups SG.
  • the display panel can include fewer pattern layers, so that the thickness of the display panel can be smaller, which is beneficial to the thinning of the display panel and the display device.
  • connection lines 172 can be provided in the display area AA without increasing the size of the display panel and reducing the number of pixel driving circuits D.
  • a signal line group SG (eg, each signal line group SG) includes a plurality of signal lines.
  • a signal line group SG includes two signal lines.
  • a signal line group SG (for example, each signal line group SG) includes one signal line. Similar to the data leads, in the case where a signal line group SG (for example, each signal line group SG) includes a plurality of signal lines, more connection lines may be provided in the display panel.
  • the distance q2 between every two adjacent signal line groups SG is approximately the same.
  • the distance q2 between two adjacent signal line groups SG may be the minimum distance between two adjacent signal lines that respectively belong to the two signal line groups SG and are adjacently located. Since the distance q2 between two adjacent signal line groups SG in the plurality of signal line groups SG is approximately the same, the structure of the display panel can be more uniform, which can improve the structural stability of the display panel.
  • Some embodiments of the present disclosure also provide a method of manufacturing a display panel. Through this method, the display panel provided in any of the above embodiments can be produced.
  • the manufacturing method of a display panel includes forming a plurality of pixel driving circuits, a plurality of bonding pads, a plurality of first data lines and at least one data lead on a substrate.
  • the plurality of pixel driving circuits form a plurality of circuit columns distributed along the first direction, and the circuit columns include at least two pixel driving circuits distributed along the second direction, and the first direction and the second direction intersect.
  • the plurality of bonding pads are located on one side of the plurality of pixel driving circuits along the second direction.
  • the first data line extends along the second direction and is coupled to at least two pixel driving circuits in the circuit column.
  • the data leads extend along the second direction and are coupled to the first data line and at least one pad.
  • the plurality of circuit columns form a plurality of circuit groups distributed along the first direction.
  • the circuit groups include at least one circuit column.
  • the data leads are arranged on Between two adjacent circuit groups.

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  • Liquid Crystal Display Device Control (AREA)

Abstract

一种显示面板(10)。显示面板(10)包括多个像素驱动电路(D)、多个焊盘(130)、多条第一数据线(141)以及至少一条数据引线(150)。多个像素驱动电路(D)设置在显示区(AA)中，多个像素驱动电路(D)形成沿第一方向分布的多个电路列(120)，电路列(120)包括沿第二方向分布的至少两个像素驱动电路(D)。多个焊盘(130)沿第二方向位于显示区(AA)的一侧。多条第一数据线(141)设置在显示区(AA)中，第一数据线(141)与电路列(120)中的至少两个像素驱动电路(D)耦接。数据引线(150)与第一数据线(141)耦接，且与至少一个焊盘(130)耦接。其中，多个电路列(120)形成沿第一方向分布的多个电路组(DG)，电路组(DG)包括至少一个电路列(120)，数据引线(150)设置在位置相邻的两个电路组(DG)之间。

Description

显示面板及显示装置 技术领域
本公开涉及显示技术领域，尤其涉及一种显示面板及显示装置。
背景技术
为了给用户带来更优的使用体验，全面屏、窄边框、高分辨率等将成为未来显示类产品，尤其是手机类产品的发展趋势。
发明内容
一方面，提供一种显示面板。所述显示面板包括多个像素驱动电路、多个焊盘、多条第一数据线以及至少一条数据引线。所述多个像素驱动电路设置在显示区中，多个像素驱动电路形成沿第一方向分布的多个电路列，电路列包括沿第二方向分布的至少两个像素驱动电路，第二方向和第一方向交叉。多个焊盘设置在非显示区中且沿第二方向位于显示区的一侧。多条第一数据线设置在显示区中，第一数据线沿第二方向延伸，且与电路列中的至少两个像素驱动电路耦接。数据引线与第一数据线耦接，数据引线从显示区延伸至非显示区，且与至少一个焊盘耦接。其中，多个电路列形成沿第一方向分布的多个电路组，电路组包括至少一个电路列，数据引线设置在位置相邻的两个电路组之间。
在一些实施例中，至少一条数据引线包括至少一条第一数据引线，第一数据引线中位于所述显示区的部分与第一数据线同层设置。
在一些实施例中，至少一条数据引线包括至少一条第二数据引线，第二数据引线中位于所述显示区的部分与所述第一数据线异层设置。
在一些实施例中，至少一条数据引线为多条数据引线，多条数据引线还包括至少一条第一数据引线，第一数据引线中位于显示区的部分与第一数据线同层设置。在显示面板的厚度方向上，第一数据引线与第二数据引线不交叠。
在一些实施例中，显示面板还包括多条第一信号线。多条第一信号线设置在显示区中，第一信号线沿第一方向延伸，第一信号线包括多个第一线段和至少一个第二线段。第二数据引线位于显示区的部分与第一线段同层设置，且设置在位置相邻的两个第一线段之间。在第一方向上位置相邻的两个第一线段通过第二线段耦接，第二线段与第一线段异层设置。
在一些实施例中，显示面板还包括至少一条连接线，设置在显示区中，连接线沿第一方向延伸。通过连接线，第一数据线与数据引线耦接，连接线 与第二数据引线位于显示区的部分同层设置。
在一些实施例中，显示面板还包括至少一条连接线。至少一条连接线设置在显示区中，连接线沿第一方向延伸。通过连接线，第一数据线与数据引线耦接。
在一些实施例中，显示面板还包括多条信号线。多条信号线设置在显示区中，信号线沿第一方向延伸。多条信号线形成沿第二方向分布的多个信号线组，一信号线组包括至少一条信号线。连接线与信号线的至少一部分同层设置，且设置在位置相邻的两个信号线组之间。
在一些实施例中，多个信号线组中，位置相邻的每两个信号线组之间的距离大致相同。
在一些实施例中，显示面板还包括多个发光器件，发光器件与像素驱动电路耦接。多条第一数据线包括多条异色数据线，异色数据线与至少两个发光颜色不同的发光器件耦接。与多条异色数据线耦接的所有数据引线的位于显示区的部分同层设置。
在一些实施例中，显示面板还包括至少一条第二数据线，第二数据线沿第二方向从显示区延伸至非显示区，且与至少一个焊盘耦接。
在一些实施例中，至少一条数据引线为多条数据引线，多条数据引线形成沿第一方向分布的多个引线组，引线组中的每条数据引线设置在相同的两个电路组之间。在显示区中，多个引线组中，位置相邻的每两个引线组之间的距离大致相同。
另一方面，提供一种显示装置。所述显示装置包括：如上述任一实施例所述的显示面板。
另一方面，提供一种显示面板的制作方法。所述显示面板的制作方法包括：在基底上形成多个像素驱动电路、多个焊盘、多条第一数据线以及至少一条数据引线，多个像素驱动电路形成沿第一方向分布的多个电路列，电路列包括沿第二方向分布的至少两个像素驱动电路，第一方向和第二方向交叉。多个焊盘沿第二方向位于多个像素驱动电路的一侧。第一数据线沿第二方向延伸，且与电路列中的至少两个像素驱动电路耦接。数据引线沿第二方向延伸，且与第一数据线和至少一个焊盘耦接，多个电路列形成沿第一方向分布的多个电路组，电路组包括至少一个电路列，数据引线设置在位置相邻的两个电路组之间。
附图说明
为了更清楚地说明本公开中的技术方案，下面将对本公开一些实施 例中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例的附图，对于本领域普通技术人员来讲，还可以根据这些附图获得其他的附图。此外，以下描述中的附图可以视作示意图，并非对本公开实施例所涉及的产品的实际尺寸、方法的实际流程、信号的实际时序等的限制。
图1为根据相关技术的显示面板的结构图；
图2为根据一些实施例的显示装置的结构图；
图3和图4为根据一些实施例的显示面板的结构图；
图5为像素驱动电路的等效电路图；
图6为根据一些实施例的显示面板中多个像素驱动电路的俯视图；
图7～图9为根据一些实施例的显示面板的局部放大图；
图10为图1的相关技术的显示面板中区域U2的局部放大图；
图11为根据一些实施例的显示面板的俯视图；
图12为图11的显示面板的局部放大图；
图13为图7的显示面板中区域U3的局部放大图；
图14为图8的显示面板中区域U4的局部放大图；
图15为根据一些实施例的显示面板的显示区的局部放大图。
具体实施方式
下面将结合附图，对本公开一些实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开所提供的实施例，本领域普通技术人员所获得的所有其他实施例，都属于本公开保护的范围。
除非上下文另有要求，否则，在整个说明书和权利要求书中，术语“包括(comprise)”及其其他形式例如第三人称单数形式“包括(comprises)”和现在分词形式“包括(comprising)”被解释为开放、包含的意思，即为“包含，但不限于”。在说明书的描述中，术语“一个实施例(one embodiment)”、“一些实施例(some embodiments)”、“示例性实施例(exemplary embodiments)”、“示例(example)”、“特定示例(specific example)”或“一些示例(some examples)”等旨在表明与该实施例或示例相关的特定特征、结构、材料或特性包括在本公开的至少一个实施例或示例中。上述术语的示意性表示不一定是指同一实施例或示例。此外，所述的特定特征、结构、材料或特点可以以任何适当方式包括在任何一个或多个实施例或示例中。
以下，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相 对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个该特征。在本公开实施例的描述中，除非另有说明，“多个”的含义是两个或两个以上。
在描述一些实施例时，可能使用了“耦接”和“连接”及其衍伸的表达。例如，描述一些实施例时可能使用了术语“连接”以表明两个或两个以上部件彼此间有直接物理接触或电接触。又如，描述一些实施例时可能使用了术语“耦接”以表明两个或两个以上部件有直接物理接触或电接触。然而，术语“耦接”或“通信耦合(communicatively coupled)”也可能指两个或两个以上部件彼此间并无直接接触，但仍彼此协作或相互作用。这里所公开的实施例并不必然限制于本文内容。
“A、B和C中的至少一个”与“A、B或C中的至少一个”具有相同含义，均包括以下A、B和C的组合：仅A，仅B，仅C，A和B的组合，A和C的组合，B和C的组合，及A、B和C的组合。
本文中“被配置为”的使用意味着开放和包容性的语言，其不排除适用于或被配置为执行额外任务或步骤的设备。
另外，“基于”的使用意味着开放和包容性，因为“基于”一个或多个所述条件或值的过程、步骤、计算或其他动作在实践中可以基于额外条件或超出所述的值。
如本文所使用的那样，“大致”或“近似”包括所阐述的值以及处于特定值的可接受偏差范围内的平均值，其中所述可接受偏差范围如由本领域普通技术人员考虑到正在讨论的测量以及与特定量的测量相关的误差(即，测量系统的局限性)所确定。
如本文所使用的那样，“平行”、“垂直”、“相等”包括所阐述的情况以及与所阐述的情况相近似的情况，该相近似的情况的范围处于可接受偏差范围内，其中所述可接受偏差范围如由本领域普通技术人员考虑到正在讨论的测量以及与特定量的测量相关的误差(即，测量系统的局限性)所确定。例如，“平行”包括绝对平行和近似平行，其中近似平行的可接受偏差范围例如可以是5°以内偏差；“垂直”包括绝对垂直和近似垂直，其中近似垂直的可接受偏差范围例如也可以是5°以内偏差。“相等”包括绝对相等和近似相等，其中近似相等的可接受偏差范围内例如可以是相等的两者之间的差值小于或等于其中任一者的5％。
应当理解的是，当层或元件被称为在另一层或基板上时，可以是该层或元件直接在另一层或基板上，或者也可以是该层或元件与另一层或基板之间 存在中间层。
本文参照作为理想化示例性附图的剖视图和/或平面图描述了示例性实施方式。在附图中，为了清楚，放大了层和区域的厚度。因此，可设想到由于例如制造技术和/或公差引起的相对于附图的形状的变动。因此，示例性实施方式不应解释为局限于本文示出的区域的形状，而是包括因例如制造而引起的形状偏差。例如，示为矩形的蚀刻区域通常将具有弯曲的特征。因此，附图中所示的区域本质上是示意性的，且它们的形状并非旨在示出设备的区域的实际形状，并且并非旨在限制示例性实施方式的范围。
参见图1，在相关技术中，显示面板DP可以具有显示区AA’，显示面板DP还可以具有位于显示区AA’的一侧(例如沿Y轴负方向位于显示区AA’的一侧)的扇出区FA’、弯折区BA’以及绑定区PA’。示例性地，扇出区FA’、弯折区BA’以及绑定区PA’可以依次设置。
显示面板DP还可以包括多条数据线DB，多条数据引线DL以及多个焊盘P。其中，多条(例如，所有)数据线DB位于显示区AA’中。一数据线DB(例如每条数据线DB)可以被配置为向像素驱动电路写入数据信号。多个焊盘P可以设置在绑定区PA’中。位于显示区AA’中的一数据线DB可以通过一数据引线，与位于绑定区PA’的至少一个焊盘P耦接。具体地，一数据引线DL(例如每条数据引线DL)与一条数据线DB耦接，并且，该数据引线DL还可以从扇出区FA’延伸至弯折区BA’和绑定区PA’，并与设置在绑定区PA’中的至少一个(例如，一个；又如，多个)焊盘P耦接。进一步地，一焊盘P(例如每个焊盘P)可以被配置为与数据驱动电路(例如源极驱动器)耦接。这样，通过一个或多个焊盘P、数据引线DL和数据线DB，数据驱动电路输出的电信号(例如包括数据信号)可以写入像素驱动电路。
继续参见图1，显示面板DP位于弯折区BA’的部分可以弯折，进而将显示面板DP位于绑定区PA’的部分弯折到显示面板DP的背部，即显示面板DP朝向非显示面的一侧。基于上述，扇出区FA’的高度h1(例如为扇出区FA’沿Y轴方向的尺寸)可以影响显示面板DP的边框(例如为显示面板DP的沿Y轴负方向一端的边框)的尺寸k1，扇出区FA’的高度h1越大，显示面板DP的下边框的尺寸k1越大。
对于扇出区FA’的高度而言，由于设置有多个焊盘P的绑定区PA’沿第一方向(例如平行于X轴方向)的尺寸d1小于设置有多条数据线DB的显示区AA’沿第一方向的尺寸d2，因此，在扇出区FA’中，多条数据引线DL可以呈扇形排布。这样，在扇出区FA’中，斜向走线(例如数据引线DL中沿与Y 轴不平行的方向延伸的部分)较多，尤其是显示面板DP下边框的转角CR’处，导致扇出区FA’的高度h1较大，进而导致显示面板DP的边框尺寸较大。
可以通过减少数据线DB的数量来减小显示面板DP的边框尺寸。由于数据线DB的数量减少，因此，在扇出区FA’中的斜向走线的数量可以减少，进而使得显示面板DP的边框尺寸减小。然而，减小数据线DB的数量可能导致显示面板DP中发光器件的数量减小，即，显示面板DP的分辨率减小。如何在保证显示面板的分辨率的前提下缩小显示面板的边框尺寸，是目前亟需解决的问题。
为了解决上述问题，本公开的实施例提供了一种显示面板及其制作方法，显示装置。
图2为根据一些实施例的显示装置的结构图。参见图2，显示装置1为具有图像(包括：静态图像或动态图像，其中，动态图像可以是视频)显示功能的产品。例如，显示装置1可以是：显示器，电视机，广告牌，数码相框，具有显示功能的激光打印机，电话，手机，个人数字助理(Personal Digital Assistant，PDA)，数码相机，便携式摄录机，取景器，导航仪，车辆，大面积墙壁，家电，信息查询设备(如电子政务、银行、医院、电力等部分的业务查询设备)，监视器等中的任一种。
显示装置1包括显示面板10。显示面板10可以被配置为显示图像。显示面板10的结构将在下文详细说明。显示装置1还可以包括与显示面板10耦接的驱动控制电路20。驱动控制电路20被配置为向显示面板10提供电信号，响应于该电信号，显示面板10可以显示图像。
继续参见图2，驱动控制电路20可以包括数据驱动电路210(也可以称为源极驱动器，Source Driver IC)，数据驱动电路210被配置为向显示面板10提供数据驱动信号(也称为数据信号)。
驱动控制电路20还可以包括与数据驱动电路210耦接的时序控制电路220(也可以称为时序控制器，Timing Controller，简称为TCON)。
在一些实施例中，驱动控制电路20还可以包括扫描驱动电路110。在另一些实施例中，扫描驱动电路110可以集成在显示面板10中，也可以说，显示面板10包括扫描驱动电路110。由于扫描驱动电路110设置在显示面板10中，因此，扫描驱动电路110也可以称为GOA(Gate Driver on Array，设置在阵列基板上的扫描驱动电路)。
时序控制电路220可以与数据驱动电路210耦接，还可以与扫描驱动电路110耦接。
时序控制电路220可以被配置为接收显示信号，显示信号例如包括电源信号、视频图像信号、通信信号(例如IIC通信协议对应的信号)、以及模式控制信号(例如测试模式对应的模式控制信号，或者正常显示模式对应的模式控制信号)等。其中，视频图像信号例如是MIPI(Mobile Industry Processor Interface，移动行业处理器接口)信号、LVDS(Low-Voltage Differential Signaling，低电压差分信号)信号。视频图像信号可以包括：图像数据和时序控制信号。图像数据例如包括多个子像素的像素数据，像素数据可以是RGB数据等。时序控制信号例如包括数据使能信号(Data Enable，可以简称为DE)、行同步信号(Hsync，可以简称为HS)、场同步信号(Vsync，可以简称为VS)。
时序控制电路220还可以被配置为响应于显示信号，向数据驱动电路210输出第一控制信号和图像数据，向扫描驱动电路110输出第二控制信号。其中，第一控制信号被配置为控制数据驱动电路210的工作时序，第二控制信号被配置为控制扫描驱动电路110的工作时序。
数据驱动电路210可以被配置为将接收到的图像数据转换成显示面板10中多个发光器件E(将在下文进行说明)的数据信号，并按照第一控制信号确定的工作时序将数据信号输出至与相应发光器件E耦接的像素驱动电路D(将在下文进行说明)。扫描驱动电路110被配置为按照第二控制信号确定的工作时序将扫描信号输出至多个像素驱动电路D。
本公开的一些实施例还提供了一种显示面板。该显示面板可以作为上述任一实施例提供的显示装置中的显示面板。当然，该显示面板还可以应用于其他显示装置中，本公开的实施例对此不作限制。
图3和图4为根据一些实施例的显示面板的结构图。需要说明的是，为了附图的清晰，图3中示出了显示面板中的多个像素驱动电路、多个发光器件和多条数据线，而省略了多条数据引线。并且，图3中省略了非显示区的具体结构。图4中示出了显示面板中的多条数据线和多条数据引线，而省略了多个像素驱动电路和多个发光器件。
参见图3和图4，显示面板10可以是OLED(Organic Light Emitting Diode，有机发光二极管)显示面板、QLED(Quantum Dot Light Emitting Diodes，量子点发光二极管)显示面板、微LED(包括：MiniLED或MicroLED，LED为发光二极管)显示面板中的一种。
继续参见图3和图4，显示面板10具有显示区AA。显示面板10位于显示区AA的部分可以显示图像。显示面板10还具有非显示区SA。非显示区 SA可以位于显示区AA的至少一侧(例如，一侧；又如，四周，即包括上下两侧和左右两侧)。参见图4，在一些实施例中，显示面板10的非显示区SA可以包括绑定区PA。显示面板10的非显示区SA还可以包括扇出区FA和弯折区BA。其中，扇出区FA、弯折区BA和绑定区PA可以位于显示区AA的一侧(例如沿Y轴负方向位于显示区AA的一侧)。并且，扇出区FA、弯折区BA以及绑定区PA可以依次设置，例如，扇出区FA、弯折区BA以及绑定区PA可以沿Y轴负方向依次设置。
参见图3，显示面板10可以包括多个发光器件E。多个(例如，所有)发光器件E可以设置在显示区AA中。发光器件E可以发射光线，例如，发光器件E可以发射红色光线、绿色光线、蓝色光线或白色光线中的一种。通过设置在显示区AA中的多个发光器件E发射光线，显示面板10位于显示区AA的部分可以显示图像。发光器件E可以是有机发光二极管OLED、量子点发光二极管QLED、发光二极管LED中的一种。
继续参见图3，显示面板10还可以包括多个像素驱动电路D。多个(例如，所有)像素驱动电路D设置在显示区AA中。一像素驱动电路D(例如每个像素驱动电路D)可以与一发光器件E耦接。像素驱动电路D可以被配置为响应于接收到的扫描信号和数据信号(例如扫描驱动电路输出的扫描信号和数据驱动电路输出的数据信号)，向与该像素驱动电路D耦接的发光器件E提供电信号(例如驱动电压或驱动电流)，以驱动该发光器件E发光，从而使得显示面板10可以显示图像。
像素驱动电路D可以包括多个晶体管和至少一个(例如，一个；又如，多个)电容器。例如，像素驱动电路D可以为“2T1C”、“6T1C”、“7T1C”、“6T2C”或“7T2C”等结构。此处，“T”表示晶体管，例如为薄膜晶体管。位于“T”前面的数字表示晶体管的数量。“C”表示电容器，位于“C”前面的数字表示电容器的数量。下面，将以像素驱动电路D为“7T1C”结构为例对像素驱动电路D进行说明。可以理解地，像素驱动电路D具有其他结构时，像素驱动电路D中的元件(例如晶体管或电容器)的结构、功能以及连接关系可以与结构为7T1C的像素驱动电路D类似，可以参照下文的相关说明。
在一些实施例中，像素驱动电路D中的所有晶体管均为LTPS(Low Temperature Poly-Silicon，低温多晶硅)晶体管。LTPS晶体管的有源层的材料可以包括多晶硅。在另一些实施例中，像素驱动电路D中的一个或多个(例如，两个)晶体管为氧化物晶体管，氧化物晶体管的有源层的材料可以包括 氧化物，例如IGZO(Indium Gallium Zinc Oxide，铟镓锌氧化物)。在像素驱动电路D包括至少一个LTPS晶体管以及至少一个氧化物晶体管的情况下，该像素驱动电路D也可以称为LTPO(Low-Temperature Polycrystalline Oxide，低温多晶氧化物)型像素驱动电路。
图5为像素驱动电路的等效电路图。图6为根据一些实施例的显示面板中多个像素驱动电路的俯视图。需要说明的是，图6中仅示出了多个导体图案层，而省略了其他膜层，例如省略了有源层。
参见图5，像素驱动电路D可以为7T1C结构，即，像素驱动电路D可以包括7个晶体管，例如第一晶体管T1、第二晶体管T2、第三晶体管T3、第四晶体管T4、第五晶体管T5、第六晶体管T6以及第七晶体管T7，像素驱动电路D还可以包括1个电容器C。
示例性地，像素驱动电路D的工作过程可以包括以下三个阶段：
在第一阶段中，响应于第一扫描信号GA1，第一晶体管T1导通，从而将第一复位信号Vint1写入第三晶体管T3的栅极。这样，可以将第三晶体管T3的栅极复位。此外，在第一阶段中，第二晶体管T2、第四晶体管T4、第五晶体管T5以及第六晶体管T6均可以截止。
在第二阶段中，响应于第二扫描信号GA2，第四晶体管T4导通。并且，响应于第三扫描信号GA3，第二晶体管T2导通。通过第四晶体管T4和第二晶体管T2，数据信号DA可以写入第三晶体管T3的栅极，使得第三晶体管T3的栅极电压可以为V DA+V th，其中，V DA为数据信号DA的电压，V th为第三晶体管T3的阈值电压。此外，在第二阶段中，第一晶体管T1、第五晶体管T5以及第六晶体管T6均可以截止。
在一些实施例中，在第二阶段中，第七晶体管T7也可以响应于第四扫描信号GA4而导通，从而将第二复位信号Vint2写入发光器件E。这样，可以将发光器件E复位。在一些可能的实现方式中，第四晶体管T4的栅极和第七晶体管T7的栅极可以相互串联，使得在第二阶段中，第四晶体管T4和第七晶体管T7均可以导通，进而在第二阶段中，可以将数据信号DA写入第三晶体管T3的栅极，还可以将发光器件E复位。在另一些实施例中，上述将第二复位信号Vint2写入发光器件E的步骤可以在第一阶段中进行。例如，第一晶体管T1的栅极和第七晶体管T7的栅极可以相互串联，使得在第一阶段中，第一晶体管T1和第七晶体管T7均可以导通，进而在第一阶段中，可以将第三晶体管T3和发光器件E均复位。
在第三阶段中，响应于第五扫描信号GA5，第五晶体管T5导通。通过第 五晶体管T5，电源电压信号VDD可以写入第三晶体管T3的第一极(例如源极)，使得第三晶体管T3的第一极的电压为VDD。第三晶体管T3响应于其第一极上的电压VDD以及栅极电压V DA+V th，可以产生流经第三晶体管T3的第一极和第二极(例如为漏极)的驱动电流。并且，响应于第六扫描信号GA6，第六晶体管T6导通。通过第六晶体管T6，第三晶体管T3产生的驱动电流可以流入发光器件E，以驱动发光器件E发光。此外，在第三阶段中，第一晶体管T1、第二晶体管T2、第四晶体管T4以及第七晶体管T7均可以截止。
参见图5和图6，显示面板可以包括有源层(图中未示出)和多个导体图案层，例如第一导体图案层160和第二导体图案层170。该有源层和多个导体图案层可以形成一个或多个上述像素驱动电路D。
此外，继续参见图5和图6，为了将上文所述的电信号写入像素驱动电路D，导体图案层还可以包括一条或多条信号线。一条信号线可以被配置为向像素驱动电路D写入上述电信号(例如数据信号DA、第一扫描信号GA1、第二扫描信号GA2、第三扫描信号GA3、第四扫描信号GA4、第五扫描信号GA5、第六扫描信号GA6、第一复位信号Vint1、第二复位信号Vint2和电源电压信号VDD)中的一种或多种。本领域技术人员可以理解，在一条信号线向像素驱动电路D写入多种电信号的情况下，该多种电信号可以是相同的。
继续参见图5和图6，示例性地，第一导体图案层160可以包括多条第一数据线141。第一数据线141可以与像素驱动电路D中的第四晶体管T4耦接。第一数据线141可以被配置为向像素驱动电路D写入数据信号DA。第一导体图案层160还可以包括多条电源电压信号线161。第一电源电压信号线161可以与像素驱动电路D中的第五晶体管T5耦接。第一电源电压信号线161可以被配置为向像素驱动电路D写入电源电压信号VDD。此外，第一导体图案层160还可以包括一种或多种连接图案CP。连接图案CP可以为像素驱动电路D的一部分。连接图案CP可以被配置为将像素驱动电路D中的两个元件(像素驱动电路D中的元件例如为晶体管或电容器)耦接。连接图案CP也可以被配置为将像素驱动电路D与像素驱动电路D以外的其他元件耦接，例如，将像素驱动电路D与发光器件E耦接。
又示例性地，继续参见图5和图6，第二导体图案层170可以包括多条复位信号线171。复位信号线171可以与像素驱动电路D中的第七晶体管T7耦接。复位信号线171可以被配置为向像素驱动电路D写入第二复位信号Vint2。此外，与第一导体图案层160类似地，第二导体图案层170也可以包括一种 或多种连接图案CP。
基于上述，一个像素驱动电路D可以为能够实现上文所述功能的最小单元，如图6所示的那样。参见图6，本领域技术人员可以理解，像素驱动电路D与一条或多条信号线耦接，例如，一信号线可以与像素驱动电路接触，以实现二者相互耦接。因此，像素驱动电路D的位置变化，与该像素驱动电路D耦接的一条或多条信号线的位置也将相应变化。基于此，一信号线的一部分可以被配置为界定像素驱动电路D的边界，例如，一信号线与像素驱动电路相互接触的位置可以被配置为界定像素驱动电路的边界。示例性地，与像素驱动电路D1耦接的第一数据线141的一部分可以作为像素驱动电路D1的左边界D1a(例如为像素驱动电路D1沿X轴负方向的边界)。又示例性地，与像素驱动电路D2耦接的第一数据线141的一部分可以作为像素驱动电路D2的右边界D2b(例如为像素驱动电路D2沿X轴正方向的边界)。
参见图3和图6，在显示面板10中，多个像素驱动电路D可以形成沿第一方向(例如平行于X轴方向)分布的多个电路列120。一电路列120(例如每个电路列120)包括沿第二方向(例如平行于Y轴方向)分布的至少两个像素驱动电路D。示例性地，在显示面板10中，多个像素驱动电路D可以呈阵列分布。需要说明的是，第一方向和第二方向交叉，例如，第一方向与第二方向垂直。第一方向(例如平行于X轴方向)和第二方向(例如平行于Y轴方向)可以平行于显示面板10的延展方向。
参见图4，显示面板10包括多个焊盘130。多个焊盘130设置在非显示区SA中。并且，多个(例如，所有)焊盘130可以沿第二方向(例如平行于Y轴方向)位于显示区AA的一侧。示例性地，绑定区PA可以沿第二方向位于显示区AA的一侧，例如沿Y轴负方向位于显示区AA的一侧，多个(例如，所有)焊盘130可以位于绑定区PA中。
一焊盘130(例如每个焊盘130)可以被配置为与数据驱动控制电路(即源极驱动器)耦接。示例性地，该焊盘130可以通过各向异性导电胶与数据驱动控制电路耦接。
参见图3和图4，显示面板10还包括多条第一数据线141。多条(例如，所有)第一数据线141设置在显示区AA中。一第一数据线141(例如每条第一数据线141)沿第二方向(例如平行于Y轴方向)延伸，且与一电路列120中的至少两个像素驱动电路D耦接。示例性地，一第一数据线141可以与一电路列120中的两个像素驱动电路D耦接。又示例性地，一第一数据线141可以与一电路列120中的所有像素驱动电路D耦接。
参见图4，显示面板10还包括至少一条(例如，一条；又如，多条)数据引线150。一数据引线150(例如每条数据引线150)与一第一数据线141耦接。一数据引线150(例如每条数据引线150)从显示区AA延伸至非显示区SA。并且，该数据引线150与至少一个(例如，一个；又如，多个)焊盘130耦接。这样，通过一条数据引线150，一第一数据线141可以与至少一个焊盘130耦接。示例性地，一数据引线150可以包括相互耦接的第一部分和第二部分，其中，第一部分位于显示区AA中。第一部分可以为沿第二方向延伸的直线。第二部分位于非显示区中。第二部分可以与至少一个焊盘130耦接。
参见图3和图4，并参照上文的说明，一焊盘130可以被配置为与数据驱动电路耦接。并且，一数据引线150与至少一个焊盘130耦接，该数据引线150还与一第一数据线141耦接，并且，一第一数据线141与一电路列120中的至少两个像素驱动电路耦接。基于此，一电路列120中的至少两个(例如，所有)像素驱动电路D可以通过第一数据线和数据引线与数据驱动电路耦接，使得数据驱动电路输出的数据信号可以写入该电路列120中的至少两个(例如，所有)像素驱动电路D。响应于该数据信号，与该至少两个像素驱动电路D耦接的多个发光器件E可以发光，使得显示面板10可以显示图像。
图7～图9为根据一些实施例的显示面板的局部放大图，示出了数据引线与像素驱动电路的位置。需要说明的是，为了附图的简洁，图7～图9中省略了发光器件，且省略了像素驱动电路的具体结构，仅示出了像素驱动电路与数据引线的相对位置。
参见图7～图9，在显示面板10中，多个电路列120形成沿第一方向(例如平行于X轴方向)分布的多个电路组DG。一电路组DG(例如每个电路组DG)包括至少一个(例如，一个；又如，多个)电路列120。并且，一数据引线150设置在位置相邻的两个电路组DG之间。也可以说，一数据线150可以设置在位置相邻的两个像素驱动电路D之间，这两个像素驱动电路D分别属于位置相邻的两个电路组DG。需要说明的是，两个电路组DG位置相邻可以意指这两个电路组DG之间没有其他电路组DG。类似地，两个像素驱动电路D位置相邻可以意指这两个像素驱动电路D之间没有其他像素驱动电路D。
本公开的实施例对位置相邻的两个电路组DG之间设置的数据引线150的数目不作限制。示例性地，位置相邻的两个电路组DG之间设置有一条数据引线150。又示例性地，位置相邻的两个电路组DG之间设置有多条数据引 线150。
图10为图1所示的相关技术的显示面板中区域U2的局部放大图。需要说明的是，图7～图9示出了根据一些实施例的显示面板中区域U1的结构，区域U1中设置有8个像素驱动电路。作为对比，图8示出了相关技术的显示面板中区域U2的结构，区域U2中也设置有8个像素驱动电路。
参见图7～图9，在本公开的实施例提供的显示面板中，由于一数据引线150(例如每条数据引线150)设置在位置相邻的两个电路组DG之间，因此，在区域U1沿第一方向(例如平行于X轴方向)的尺寸t1和区域U2沿第一方向的尺寸t2相同的前提下，在根据本公开的实施例的显示面板中，一像素驱动电路D(例如每个像素驱动电路D)沿第一方向的尺寸r1可以小于相关技术中一像素驱动电路D’沿第一方向的尺寸r2。这样，在根据本公开的实施例提供的显示面板中，在不增大显示面板尺寸且不减少像素驱动电路的数量的前提下，可以通过减小像素驱动电路D在第一方向上的尺寸的方式，在位置相邻的两个电路组DG之间设置一定的空间，该空间可以用以设置一条或多条数据引线150。可以理解地，由于位置相邻的两个电路组DG之间具有一定的空间，因此，多个导体图案层中的一个或多个在相应位置处也具有一定的空间，可以将数据引线设置在该一个或多个导体图案层的相应空间中。这样，在不增大显示面板尺寸且不减少像素驱动电路的数量的前提下，可以在显示区AA中设置至少一条(例如，一条；又如，多条)数据引线150。
进一步地，参见图1和图4，一数据引线150可以比与该数据引线150耦接的第一数据线141更靠近显示面板10的中线10c。中线10c为显示面板沿第一方向(例如平行于X轴方向)的中线。这样，在显示面板10的数据引线150的数量与显示面板DP的数据引线DL的数量相同的前提下，显示面板10的扇出区FA中的斜向走线(例如为数据引线150的第二部分位于扇出区FA且延伸方向与Y轴不平行的部分)的倾斜角度o1(例如为斜向走线的延伸方向与Y轴负方向的夹角)可以小于显示面板DP的扇出区FA’中的斜向走线的倾斜角度o2。这样，显示面板10中扇出区FA的高度h2可以小于显示面板DP中扇出区FA’的高度h1，进而使得显示面板10的边框(即设置有扇出区的边框)的尺寸k2小于显示面板DP的边框尺寸k1。基于上述，在本公开的实施例提供的显示面板中，在不减少像素驱动电路的数量的前提下，可以在显示区AA中设置至少一条(例如，一条；又如，多条)数据引线150，可以在不增大显示面板的尺寸且不减小显示面板的分辨率的前提下减小显示面板的边框尺寸。
参见图7～图9，在一些实施例中，至少一条(例如，一条；又如，多条)数据引线150包括至少一条(例如，一条；又如，多条)第一数据引线151。一第一数据引线151(例如每条第一数据引线151)中位于显示区AA的部分151a(即第一数据引线151的第一部分)与第一数据线同层设置。
示例性地，在显示面板包括一条数据引线150且数据引线150包括一条第一数据引线151的情况下，该数据引线150为第一数据引线151。也可以说，该数据引线150中位于显示区AA的部分与第一数据线同层设置。又示例性地，在显示面板包括多条数据引线150且多条数据引线150包括一条第一数据引线151的情况下，多条数据引线150中的一条为第一数据引线151。也可以说，多条数据引线150中的一条位于显示区AA的部分与第一数据线同层设置。又示例性地，在显示面板包括多条数据引线150且多条数据引线150包括多条第一数据引线151的情况下，多条数据引线150中的多条(例如，部分；又如，全部)为第一数据引线151。也可以说，部分或全部数据引线150中的每条位于显示区AA的部分与第一数据线同层设置。
参见图6～图9，在一些可能的实现方式中，第一数据引线151中位于显示区AA的部分151a和第一数据线141均位于第一导体图案层160中。
继续参见图6～图9，参照上文的说明，第一数据线141位于显示区AA中，且沿第二方向延伸。并且，第一数据引线151中位于显示区AA的部分151a，即第一数据引线151的第一部分151a，也可以沿第二方向延伸。即，第一数据引线151的第一部分151a与第一数据线141的延伸方向可以相同。因此，可以将第一数据引线151位于显示区AA的部分151a与第一数据线141同层设置，这样，相比于一条或多条第一数据引线151单独设置在其他图案层(例如显示面板中除了用以形成多个像素驱动电路的多个导体图案层以及包含一条或多条信号线的导体图案层以外的图案层)上，显示面板可以包括更少的图案层，使得显示面板的厚度可以较小，有利于显示面板和显示装置的轻薄化。
参见图7～图9，在一些实施例中，至少一条(例如，一条；又如，多条)数据引线150包括至少一条(例如，一条；又如，多条)第二数据引线152。一第二数据引线152(例如每条第二数据引线152)中位于显示区AA的部分152a(即第二数据引线152的第一部分152a)与第一数据线异层设置。
示例性地，在显示面板包括一条数据引线150且数据引线150包括一条第二数据引线152的情况下，该数据引线150为第二数据引线152。也可以说，该数据引线150中位于显示区AA的部分与第一数据线异层设置。又示例性 地，在显示面板包括多条数据引线150且多条数据引线150包括一条第二数据引线152的情况下，多条数据引线150中的一条为第二数据引线152。也可以说，多条数据引线150中的一条位于显示区AA的部分与第一数据线异层设置。又示例性地，在显示面板包括多条数据引线150且多条数据引线150包括多条第二数据引线152的情况下，多条数据引线150中的多条(例如，部分；又如，全部)为第二数据引线152。也可以说，部分或全部数据引线150中的每条位于显示区AA的部分与第一数据线异层设置。
由于第二数据引线152中位于显示区AA的部分152a与第一数据线异层设置，因此，可以减小第二数据引线152对第一数据线141的影响，可以改善两种信号线之间信号串扰的问题。
参见图6、图8和图9，在一些可能的实现方式中，第一数据线141位于第一导体图案层160中。第二数据引线152中位于显示区AA的部分152a位于第二导体图案层170中。这样，相比于一条或多条第二数据引线152单独设置在其他图案层(例如显示面板中除了用以形成多个像素驱动电路的多个导体图案层以及包含一条或多条信号线的导体图案层以外的图案层)上，显示面板可以包括更少的图案层，使得显示面板的厚度可以较小，有利于显示面板和显示装置的轻薄化。
参见图8和图9，在一些实施例中，显示面板包括多条数据引线150。多条数据引线150包括至少一条第一数据引线151。一第一数据引线151(例如每条第一数据引线151)中位于显示区AA的部分151a与第一数据线同层设置。多条数据引线150还包括至少一条第二数据引线152。一第二数据引线152(例如每条第二数据引线152)中位于显示区AA的部分152a与第一数据线异层设置。一第一数据引线151(例如每条第一数据引线151)中位于显示区AA的部分151a与一第二数据引线152中位于显示区AA的部分152a异层设置。这样，在位置相邻的两个电路组CG之间的距离一定的前提下，可以在两个导体图案层的相应空间中设置更多的数据引线。
进一步地，在一些可能的实现方式中，在显示面板的厚度方向(例如平行于Z轴方向)上，一第一数据引线151(例如每条第一数据引线151)与第二数据引线152不交叠。这样，可以减小第一数据引线151和第二数据引线152之间的信号串扰，可以提高显示面板的显示效果。可以理解地，由于一第一数据引线151(例如每条第一数据引线151)与第二数据引线152不交叠，因而相应地，该第一数据引线151中位于显示区AA的部分151a与第二数据引线152中位于显示区AA的部分152a也不交叠。
图11为根据一些实施例的显示面板的俯视图，示出了位于显示区中的多个像素驱动电路和多条数据引线。参见图11，在一些实施例中，显示面板10包括至少一条数据引线150，该至少一条数据引线150包括至少一条第二数据引线152。显示面板10还包括多条第一信号线171。多条(例如，所有)第一信号线171设置在显示区中。示例性地，第一信号线171可以与像素驱动电路D中的第七晶体管(图5中的T7)耦接。第一信号线171可以被配置为向像素驱动电路D写入第二复位信号。在此情况下，第一信号线171也可以称为复位信号线。一第一信号线171(例如每条第一信号线171)沿第一方向(例如平行于X轴方向)延伸。示例性地，一第一信号线171(例如每条第一信号线171)沿第一方向延伸，且与沿第一方向分布的多个像素驱动电路D耦接。
图12为图11的显示面板的局部放大图。需要说明的是，为了附图的清晰，图12中仅示出了第一信号线和数据引线，而省略了其他图案。
参见图12，一第一信号线171(例如每条第一信号线171)包括多个第一线段171a和至少一个(例如，一个；又如，多个)第二线段171b。其中，一第二数据引线(例如每条第二数据引线)位于显示区的部分152a(即第二数据引线的第一部分)与第一线段171a同层设置。示例性地，第二数据引线位于显示区的部分152a以及第一线段171a均位于第二导体图案层170中。并且，一第二数据引线(例如每条第二数据引线)位于显示区的部分152a设置在位置相邻的两个第一线段171a之间。需要说明的是，两个第一线段171a位置相邻可以意指：这两个第一线段171a之间没有其他第一线段171a。
继续参见图12，进一步地，在第一方向(例如平行于X轴方向)上位置相邻的两个第一线段171a通过第二线段171b耦接，并且，该第二线段171b与第一线段171a异层设置。也可以说，该第二线段171b与位于两个第一线段171a之间的一条或多条第二数据引线的第一部分152a异层设置。这样，沿第二方向(例如平行于Y轴方向)延伸的第二数据引线的第一部分152a与沿第一方向延伸的第一信号线171可以不接触，可以在第二数据引线位于显示区的部分152a与第一信号线171的第一线段171a不相互短接的前提下实现二者同层设置。
参见图11和图12，在一些可能的实现方式中，一第一线段171a(例如每个第一线段171a)和一第二数据引线(例如每条第二数据引线)的第一部分152a可以包含于第二导体图案层170中，而一第二线段171b(例如每个第二线段171b)可以包含于第三导体图案层180中。需要说明的是，第三导体 图案层180可以为一导体图案层。第三导体图案层180可以包括多条信号线，还可以包括一种或多种连接图案。例如，第三导体图案层180可以包括沿第一方向(例如平行于X轴方向)延伸的多条信号线，该信号线例如被配置为传输第一扫描信号(即图5中的第一扫描信号GA1)或第三扫描信号(即图5中的第三扫描信号GA3)。示例性地，沿显示面板的厚度方向(例如平行于Z轴方向)，第三导体图案层180、第二导体图案层170以及第一导体图案层160可以依次设置。
参见图7～图9，在显示面板10沿第一方向(例如平行于X轴方向)的尺寸一定，且像素驱动电路D沿第一方向的尺寸r1一定的前提下，多个像素驱动电路D在显示面板中可以具有多种排布方式。在不同的排布方式中，位置相邻的两个电路组DG之间的多条数据引线150的数量可以不同。下文将对多个像素驱动电路D的排布方式，以及相应的数据引线150的数量进行详细说明。
图13为图7的显示面板中区域U3的局部放大图。图14为图8的显示面板中区域U4的局部放大图。
首先需要说明的是，在显示面板的制作工艺中，例如数据引线的制作工艺中，需要考虑同层设置的两个图案之间的距离。同层设置的两个图案之间的最小距离应大于或等于一临界值。同层设置的两个图案之间的距离过近可能导致信号串扰的问题。并且，在显示面板的制作工艺中，考虑到制作工艺的精度，也要求同层设置的两个图案之间具有一定的距离，否则，由于存在工艺误差，可能导致同层设置的两个图案短接的问题。
需要说明的是，在本文中，多个图案“同层设置”指的是多个图案属于同一图案层，即多个图案通过同一构图工艺形成。其中，构图工艺是指能够同时形成多个图案的工艺。例如，该构图工艺可以是蒸镀或打印等。示例性地，构图工艺可以包括：先采用成膜工艺形成一薄膜，然后将该薄膜图案化形成包含多个图案的图案层。其中，图案化的过程可以包括：涂覆光刻胶、曝光、显影、刻蚀等工艺。需要说明的是，多个图案可以有至少部分连接，或者相互间隔。此外，多个图案可能具有不同厚度(例如为该图案沿显示面板厚度方向的尺寸)。
参见图13，为了方便说明，在本文中，将同层设置且位置相邻的两个图案之间的最小允许距离记为W1，即同层设置且位置相邻的两个图案之间的距离应大于或等于W1。需要说明的是，位置相邻的两个图案可以意指，同一图案层中，这两个图案之间没有其他图案。将第一数据引线151的宽度(例如 为第一数据引线151沿该第一数据引线151的宽度方向的尺寸，第一数据引线的第一部分151a的宽度方向垂直于其延伸方向，第一数据引线的第一部分151a的宽度方向例如平行于X轴方向)记为W2。第二数据引线的第一部分152a的宽度(例如为第二数据引线的第一部分152a沿该第二数据引线152的宽度方向的尺寸，第二数据引线152宽度方向垂直于其延伸方向，第二数据引线152的宽度方向例如平行于X轴方向)可以与第一数据引线的第一部分151a的宽度相同。可以将第二数据引线的第一部分152a的宽度也记为W2。
在一些实施例中，参见图7和图13，并参照上文的说明，一电路组DG(例如每个电路组DG)包括一个电路列120。位置相邻的两个电路组DG之间具有一定的空间，也可以说，位置相邻的两个电路列120之间具有一定的空间。至少一条(例如，一条；又如，多条)数据引线150可以设置在该空间中。需要说明的是，位置相邻的两个电路列可以意指，这两个电路列之间没有其他电路列。
将位置相邻的两个电路列120之间允许设置一条数据引线的最小距离记为W3(下文中将该距离称为第一距离)。为了在位置相邻的两个电路列120之间设置一条数据引线150，要求W3＝W2+2W1。需要说明的是，位置相邻的两个电路列120之间允许设置一条数据引线150的最小距离可以意指：在包含至少一条数据引线150的导体图案层(例如包含一条或多条第一数据引线的第一导体图案层，或者包含一条或多条第二数据引线的第二导体图案层)中，分别对应于位置相邻的两个电路列120的、且与该条数据引线150位置相邻的两个图案之间的最小距离。其中，一图案与一电路列120对应可以意指：该图案为该电路列120中一个或多个像素驱动电路D的一部分，例如该图案被配置为将该电路列中一像素驱动电路D中的多个元件耦接。一图案与一电路列120对应还可以意指：该图案与该电路列120中一个或多个像素驱动电路D耦接，示例性地，该图案被配置为向该电路列120中一个或多个像素驱动电路D中写入电信号，例如，该图案为一信号线，如第一数据线或电源电压信号线等。又示例性地，该图案被配置为将该电路列120中一个或多个像素驱动电路D与其他元件耦接，例如，该图案被配置为将一个像素驱动电路D与发光器件E耦接。
在另一些实施例中，参见图8、图9和图14，一电路组DG(例如每个电路组DG)包括多个电路列120。示例性地，参见图8和图14，一电路组DG包括两个电路列120。又示例性地，参见图9，一电路组DG包括四个电路列120。
将图8和图14与图7和图13对比，在显示面板沿第一方向的尺寸一定，且像素驱动电路D沿第一方向的尺寸r1一定的前提下，在一电路组DG包括两个电路列120的情况下，位置相邻的两个电路组DG之间的距离为2W3(下文中将该距离称为第二距离)，第二距离允许设置M1(M1≥2)条数据引线，当然实际设置的数量为N1，N1≤M1。其中，第二距离可以意指：在包含多条数据引线150的导体图案层(例如包含同层设置的多条第一数据引线的第一导体图案层，或者包含同层设置的多条第二数据引线的第二导体图案层)中，分别对应于位置相邻的两个电路列120的、且与N条数据引线150位置相邻的两个图案之间的距离。其中，位置相邻的两个电路列120是指分别属于该位置相邻的两个电路组DG且相互靠近的两个电路列120。
参照上文的说明，由于尺寸为W3的空间中可以设置一条数据引线，因此，尺寸为2W3的空间中可以设置同层设置的两条数据引线。例如，可以在第一导体图案层160的相应空间中设置两条第一数据引线151。由于W3＝W2+2W1，因此，在尺寸为2W3的空间中设置同层设置的两条数据引线后，剩余的空间尺寸可以为2W3-(2W2+3W1)＝2(W2+2W1)-(2W2+3W1)＝W1。可以利用该尺寸为W1的空间设置一条或多条数据引线，例如，可以在第一导体图案层的相应空间中设置更多的第一数据引线。又例如，可以在第二导体图案层的相应空间中设置一条或多条第二数据引线。基于上述，也可以说，对于4个电路列对应的区域而言，在一电路组DG包括两个电路列120的情况下，可以在该区域中设置多于4条数据引线。
类似地，将图9与图7和图13对比，在显示面板沿第一方向的尺寸一定，且像素驱动电路D沿第一方向的尺寸r1一定的前提下，在一电路组DG包括四个电路列120的情况下，位置相邻的两个电路组DG之间的距离为4W3(下文中将该距离称为第三距离)，第三距离允许设置M2(M2≥4)条数据引线，当然，实际设置的数量为N2，N2≤M2。其中，第三距离可以与上文所述的第二距离类似，可以参照上文的相关说明，在此不再赘述。基于上述，可以在尺寸为4W3的空间中设置同层设置的5条数据引线。由于W3＝W2+2W1，因此，在尺寸为4W3的空间中设置同层设置的5条数据引线后，还可以剩余的空间的尺寸为4W3-(5W2+6W1)＝4(W2+2W1)-(5W2+6W1)＝2W1-W2。可以利用该尺寸为2W1-W2的空间设置一条或多条数据引线，例如，可以在第一导体图案层的相应空间中设置更多的第一数据引线。又例如，可以在第二导体图案层的相应空间中设置一条或多条第二数据引线。也可以说，对于4个电路列对应的区域而言，在一电路组DG包括4个电路列120的情况下，可以 在该区域中设置多于5条(例如，6条；又如，7条)数据引线150。
可以理解地，在电路组DG包括更多(例如，大于或等于5)电路列120的情况下，在显示面板沿第一方向的尺寸一定，且像素驱动电路沿第一方向的尺寸一定的前提下，位置相邻的两个电路组DG之间可以设置更多条数据引线，即，显示面板中可以设置有更多数据引线。
参见图4，在一些实施例中，沿第一方向(例如平行于X轴方向)，数据引线150位于显示区AA的部分的长度q1先增大再减小。其中，一数据引线150(例如每条数据引线150)位于显示区AA的部分，即该护具阴险150的第一部分的长度q1可以为第一部分沿第二方向(例如平行于Y轴方向)的尺寸。这样，多条数据引线150的分布较为均匀，可以提高显示面板的结构稳定性。
参见图3、以及图7～图9，在一些实施例中，显示面板还包括多个发光器件E，一发光器件E与一像素驱动电路D耦接。多条第一数据线141包括多条异色数据线。也可以说，多条第一数据线141中的多条为异色数据线。一异色数据线(例如每条异色数据线)沿第二方向(例如平行于Y方向)延伸，且与一电路列120中的至少两个像素驱动电路D耦接。并且，一异色数据线(例如每条异色数据线)与至少两个发光颜色不同的发光器件E耦接。与多条(例如，所有)异色数据线耦接的所有数据引线150同层设置。示例性地，与多条(例如，所有)异色数据线耦接的所有数据引线150均为第一数据引线151，均包含于第一导体图案层160中。
在向两条数据引线写入相同电信号的前提下，当这两条数据引线同层设置时，这两条数据引线上的电负载的差异(例如由像素驱动电路中的寄生电容引起)可以较小，使得这两条数据引线向像素驱动电路D输出的电信号的差异可以较小。基于此，当多条(例如，所有)数据引线同层设置时，可以提高显示面板的显示效果。进一步地，由于异色数据线与至少两个发光颜色不同的发光器件E耦接，因此，异色数据线上传输的电信号的变化频率可能较大。基于此，由于与多条(例如，所有)异色数据线耦接的所有数据引线150同层设置，因此，可以进一步地提高显示面板的显示效果。
参见图3，在一些实施例中，显示面板还包括至少一条(例如，一条；又如，多条)第二数据线142。一第二数据线142(例如每条第二数据线142)沿第二方向(例如平行于Y轴方向)从显示区AA延伸至非显示区SA，且与至少一个(例如，一个；又如，多个)焊盘P耦接。例如，一第二数据线142沿第二方向从显示区AA延伸至扇出区FA、弯折区BA和绑定区PA，且与位 于绑定区PA中的至少一个焊盘P耦接。第二数据线142可以不通过连接线和数据引线而与至少一个焊盘P耦接，因此，由于显示包括至少一条第二数据线142，显示面板的结构可以较为简单，可以提高显示面板的良率。
参见图7～图9，在一些实施例中，显示面板包括多条数据引线150。多条数据引线150形成沿第一方向(例如平行于X轴方向)分布的多个引线组LG，一引线组LG(例如每个引线组LG)中的每条数据引线150设置在相同的两个电路组DG之间。也可以说，位置相邻的两个电路组DG之间设置有一个引线组LG。在显示区中，在多个引线组LG中，位置相邻的每两个引线组LG之间的距离q1大致相同。需要说明的是，两个引线组LG位置相邻可以意指，这两个引线组LG之间没有其他引线组LG。示例性地，在显示区中，位置相邻的两个引线组LG之间的距离q1可以为，分别属于这两个引线组LG且相互靠近的两条数据引线150之间的最小距离。由于在显示区中位置相邻的每两个引线组LG之间的距离q1大致相同，因此，显示面板中各个电路组DG中电路列120的数量可以相同。
由于在多个引线组LG中，位置相邻的每两个引线组LG之间的距离q1大致相同，因此，显示面板的结构可以较为均匀。示例性地，多个电路组DG中的每个沿第一方向(例如平行于X轴方向)的尺寸可以大致相同，这样，显示面板的结构可以较为均匀，可以提高显示面板的结构稳定性。
图15为根据一些实施例的显示面板的显示区的局部放大图，示出了连接线、数据引线和第一信号线的相对位置。需要说明的是，为了附图的简洁，图15中仅示出了多条连接线、多条数据引线和多条第一信号线，而省略了其他结构。
参见图4和图15，在一些实施例中，显示面板还包括至少一条(例如，一条；又如，多条)连接线172。一连接线172(例如每条连接线172)设置在显示区AA中。一连接线172(例如每条连接线172)沿第一方向(例如平行于X轴方向)延伸。通过连接线172，第一数据线141与数据引线150耦接。示例性地，一连接线172可以与第一数据线141耦接，该连接线172还可以与第一数据引线151或第二数据引线152耦接，这样，通过该连接线172，一第一数据引线141可以与一第一数据引线151或第二数据引线152耦接。
继续参见图4和图15，在一些实施例中，显示面板还包括至少一条连接线172，并且，显示面板还包括多条信号线，该多条信号线设置在显示区AA中。一信号线(例如每条信号线)沿第一方向(例如平行于X轴方向)延伸。示例性地，一信号线(例如每条信号线)为第一信号线171。当然，信号线也 可以是其他种类的信号线，本公开的实施例对此不作限制，只要该种信号线设置在显示区AA中且沿第一方向延伸即可。下文中，将以信号线为第一信号线为例加以说明。
进一步地，多条信号线(例如多条第一信号线171)形成沿第二方向(例如平行于Y轴方向)分布的多个信号线组SG，一信号线组SG包括至少一条(例如，一条；又如，多条)信号线。一连接线172(例如每条连接线172)与信号线的至少一部分(例如，部分；又如，全部)同层设置，且设置在位置相邻的两个信号线组SG之间。需要说明的是，两个信号线组SG位置相邻可以意指：这两个信号线组SG之间没有其他信号线组SG。示例性地，在信号线为第一信号线171的情况下，一连接线172与第一信号线的第一线段171a同层设置，例如，一连接线172与第一信号线的第一线段171a均包含于第二导体图案层170中。
由于一连接线172沿第一方向延伸，一信号线也沿第一方向延伸，基于此，一连接线172可以与一信号线的至少一部分同层设置，且设置在位置相邻的两个信号线组SG之间，这样，相比于一条或多条连接线172单独设置在其他图案层(例如显示面板中除了用以形成多个像素驱动电路的多个导体图案层以及包含一条或多条信号线的导体图案层以外的图案层)上，显示面板可以包括更少的图案层，使得显示面板的厚度可以较小，有利于显示面板和显示装置的轻薄化。此外，与数据引线类似地，可以通过减小像素驱动电路的至少一部分(例如，部分；又如，全部)沿第二方向(例如平行于Y轴方向)的尺寸，在位置相邻的两个信号线组SG之间设置一定的空间，该空间可以用以设置一条或多条连接线172。这样，在不增大显示面板尺寸且不减少像素驱动电路D的数量的前提下，可以在显示区AA中设置多条连接线172。
继续参见图15，在一些实施例中，一信号线组SG(例如每个信号线组SG)包括多条信号线，例如，一信号线组SG包括两条信号线。或者，在另一些实施例中，一信号线组SG(例如每个信号线组SG)包括一条信号线。与数据引线类似地，在一信号线组SG(例如每个信号线组SG)包括多条信号线的情况下，显示面板中可以设置有更多连接线。
继续参见图15，在一些实施例中，在多个信号线组SG中，位置相邻的每两个信号线组SG之间的距离q2大致相同。示例性地，位置相邻的两个信号线组SG之间的距离q2可以为，分别属于这两个信号线组SG且位置相邻的两条信号线之间的最小距离。由于在多个信号线组SG中，位置相邻的每两个信号线组SG之间的距离q2大致相同，因此，显示面板的结构可以较为均 匀，可以提高显示面板的结构稳定性。
本公开的一些实施例还提供了一种显示面板的制作方法。通过该方法，可以制作上述任一实施例提供的显示面板。显示面板的制作方法包括：在基底上形成多个像素驱动电路、多个焊盘、多条第一数据线以及至少一条数据引线。
其中，多个像素驱动电路形成沿第一方向分布的多个电路列，电路列包括沿第二方向分布的至少两个像素驱动电路，第一方向和第二方向交叉。多个焊盘沿第二方向位于多个像素驱动电路的一侧。第一数据线沿第二方向延伸，且与电路列中的至少两个像素驱动电路耦接。数据引线沿第二方向延伸，且与第一数据线和至少一个焊盘耦接，多个电路列形成沿第一方向分布的多个电路组，电路组包括至少一个电路列，数据引线设置在位置相邻的两个电路组之间。对于上述结构的具体说明可以参照上文的相关说明，在此不再赘述。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (13)

  1. 一种显示面板，具有显示区和非显示区，所述显示面板包括：
    多个像素驱动电路，设置在所述显示区中，所述多个像素驱动电路形成沿第一方向分布的多个电路列，所述电路列包括沿第二方向分布的至少两个像素驱动电路，所述第二方向和所述第一方向交叉；
    多个焊盘，设置在所述非显示区中且沿所述第二方向位于所述显示区的一侧；
    多条第一数据线，设置在所述显示区中，所述第一数据线沿所述第二方向延伸、且与所述电路列中的至少两个像素驱动电路耦接；
    至少一条数据引线，所述数据引线与所述第一数据线耦接，所述数据引线从所述显示区延伸至所述非显示区，且与至少一个焊盘耦接；
    其中，所述多个电路列形成沿所述第一方向分布的多个电路组，所述电路组包括至少一个电路列，所述数据引线设置在位置相邻的两个电路组之间。
  2. 根据权利要求1所述的显示面板，其中，
    所述至少一条数据引线包括至少一条第一数据引线，所述第一数据引线中位于所述显示区的部分与所述第一数据线同层设置。
  3. 根据权利要求1所述的显示面板，其中，
    所述至少一条数据引线包括至少一条第二数据引线，所述第二数据引线中位于所述显示区的部分与所述第一数据线异层设置。
  4. 根据权利要求3所述的显示面板，其中，
    所述至少一条数据引线为多条数据引线，所述多条数据引线还包括至少一条第一数据引线，所述第一数据引线中位于所述显示区的部分与所述第一数据线同层设置；
    在所述显示面板的厚度方向上，所述第一数据引线与所述第二数据引线不交叠。
  5. 根据权利要求3或4所述的显示面板，还包括：
    多条第一信号线，设置在所述显示区中，所述第一信号线沿所述第一方向延伸，所述第一信号线包括多个第一线段和至少一个第二线段；
    所述第二数据引线位于所述显示区的部分与所述第一线段同层设置，且 设置在位置相邻的两个第一线段之间；
    在第一方向上位置相邻的两个所述第一线段通过所述第二线段耦接，所述第二线段与所述第一线段异层设置。
  6. 根据权利要求5所述的显示面板，还包括：
    至少一条连接线，设置在所述显示区中，所述连接线沿所述第一方向延伸；
    通过所述连接线，所述第一数据线与所述数据引线耦接，所述连接线与所述第二数据引线位于所述显示区的部分同层设置。
  7. 根据权利要求1所述的显示面板，还包括：
    至少一条连接线，设置在所述显示区中，所述连接线沿所述第一方向延伸；
    通过所述连接线，所述第一数据线与所述数据引线耦接。
  8. 根据权利要求7所述的显示面板，还包括：
    多条信号线，设置在所述显示区中，所述信号线沿所述第一方向延伸；
    所述多条信号线形成沿所述第二方向分布的多个信号线组，一信号线组包括至少一条信号线；
    所述连接线与所述信号线的至少一部分同层设置，且设置在位置相邻的两个所述信号线组之间。
  9. 根据权利要求8所述的显示面板，其中，
    所述多个信号线组中，位置相邻的每两个信号线组之间的距离大致相同。
  10. 根据权利要求1所述的显示面板，还包括：
    多个发光器件，所述发光器件与所述像素驱动电路耦接；
    所述多条第一数据线包括多条异色数据线，所述异色数据线与至少两个发光颜色不同的发光器件耦接；
    与所述多条异色数据线耦接的所有数据引线位于所述显示区的部分同层设置。
  11. 根据权利要求1所述的显示面板，还包括：
    至少一条第二数据线，所述第二数据线沿所述第二方向从所述显示区延伸至所述非显示区，且与至少一个焊盘耦接。
  12. 根据权利要求1所述的显示面板，其中，
    所述至少一条数据引线为多条数据引线，所述多条数据引线形成沿所述第一方向分布的多个引线组，所述引线组中的每条数据引线设置在相同的两个电路组之间；
    在所述显示区中，所述多个引线组中，位置相邻的每两个引线组之间的距离大致相同。
  13. 一种显示装置，包括权利要求1～12任一项所述的显示面板。
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