WO2023199932A1 - 半導体装置および製造方法 - Google Patents

半導体装置および製造方法 Download PDF

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Publication number
WO2023199932A1
WO2023199932A1 PCT/JP2023/014827 JP2023014827W WO2023199932A1 WO 2023199932 A1 WO2023199932 A1 WO 2023199932A1 JP 2023014827 W JP2023014827 W JP 2023014827W WO 2023199932 A1 WO2023199932 A1 WO 2023199932A1
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Prior art keywords
region
section
trench
transistor
diode
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Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
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PCT/JP2023/014827
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English (en)
French (fr)
Japanese (ja)
Inventor
功 吉川
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Fuji Electric Co Ltd
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Fuji Electric Co Ltd
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Application filed by Fuji Electric Co Ltd filed Critical Fuji Electric Co Ltd
Priority to DE112023000205.3T priority Critical patent/DE112023000205T5/de
Priority to JP2024514977A priority patent/JP7726385B2/ja
Priority to CN202380013775.XA priority patent/CN117999657A/zh
Publication of WO2023199932A1 publication Critical patent/WO2023199932A1/ja
Priority to US18/611,728 priority patent/US20240234555A1/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
    • H10D12/411—Insulated-gate bipolar transistors [IGBT]
    • H10D12/441—Vertical IGBTs
    • H10D12/461—Vertical IGBTs having non-planar surfaces, e.g. having trenches, recesses or pillars in the surfaces of the emitter, base or collector regions
    • H10D12/481—Vertical IGBTs having non-planar surfaces, e.g. having trenches, recesses or pillars in the surfaces of the emitter, base or collector regions having gate structures on slanted surfaces, on vertical surfaces, or in grooves, e.g. trench gate IGBTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D8/00—Diodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D8/00—Diodes
    • H10D8/50—PIN diodes 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]

Definitions

  • the present invention relates to a semiconductor device and a manufacturing method.
  • RC-IGBTs reverse conduction IGBTs
  • a transistor section such as an IGBT (Insulated Gate Bipolar Transistor) and a diode section are provided on a single semiconductor substrate (for example, see Patent Documents 1 and 2).
  • Patent Documents 1 and 2 [Prior art documents] [Patent document] [Patent Document 1] JP2018-78230A [Patent Document 2] JP2015-135954A
  • the semiconductor device may include a semiconductor substrate that has an upper surface and a lower surface and is provided with a drift region of a first conductivity type.
  • the semiconductor device includes a collector region of a second conductivity type in contact with the lower surface of the semiconductor substrate, and an emitter region of a first conductivity type provided in contact with the upper surface of the semiconductor substrate and having a higher doping concentration than the drift region.
  • a transistor portion may be provided.
  • Any of the above semiconductor devices may include a diode portion having a first conductivity type cathode region in contact with the lower surface of the semiconductor substrate.
  • the avalanche breakdown voltage in the diode portion may be 0.7 times or more and less than 1 time the avalanche breakdown voltage in the transistor portion.
  • the cathode voltage at which the diode section reaches the negative resistance region may be higher than the collector voltage at which the transistor section reaches the negative resistance region.
  • the diode section and the transistor section may have a plurality of trench sections arranged at intervals along the arrangement direction on the upper surface of the semiconductor substrate.
  • At least some of the trench portions in the transistor portion may be arranged at a first interval in the arrangement direction. In any of the above semiconductor devices, at least some of the trench portions in the diode portion may be arranged at a second interval larger than the first interval in the arrangement direction.
  • any of the above semiconductor devices may include an intermediate region disposed between the diode section and the transistor section, provided with a plurality of the trench sections, and having at least one of the cathode region and the collector region.
  • the intermediate region may include a transistor side region.
  • the transistor side region may be in contact with the transistor portion, and one or more of the trench portions may be arranged at the first interval.
  • any of the above semiconductor devices may include an intermediate region disposed between the diode section and the transistor section, provided with a plurality of the trench sections, and having at least one of the cathode region and the collector region.
  • the intermediate region may include a transistor side region.
  • the transistor side region may be in contact with the transistor portion, and one or more of the trench portions may be arranged at intervals smaller than the first interval.
  • a boundary position between the cathode region and the collector region in the intermediate region may be located in the transistor side region.
  • the boundary position may be located below the trench portion closest to the diode portion among the one or more trench portions in the transistor side region.
  • the transistor side region may include the first trench portion and the second trench portion, the distance of which in the arrangement direction is the smallest in the intermediate region.
  • the boundary position may be located in a region from below the first trench part to below the second trench part.
  • the distance between the plurality of trench portions in the arrangement direction in the intermediate region may be larger as the distance is closer to the diode portion.
  • the second interval may be twice or more the first interval.
  • At least some of the trench portions in the transistor portion may have a first length in the depth direction of the semiconductor substrate. In any of the above semiconductor devices, at least some of the trench portions in the diode portion may have a second length larger than the first length in the depth direction.
  • any of the above semiconductor devices may include an intermediate region disposed between the diode section and the transistor section, provided with a plurality of the trench sections, and having the cathode region and the collector region.
  • the intermediate region may have a transistor side region in contact with the transistor section.
  • the transistor side region may have the trench portion having the first length.
  • any of the above semiconductor devices may include an intermediate region disposed between the diode section and the transistor section, provided with a plurality of the trench sections, and having the cathode region and the collector region.
  • the intermediate region may have a transistor side region in contact with the transistor section.
  • the transistor side region may have the trench portion having a length smaller than the first length.
  • a boundary position between the cathode region and the collector region in the intermediate region may be located in the transistor side region.
  • the length of the plurality of trench portions in the depth direction in the intermediate region may be larger as the trench portions are closer to the diode portion.
  • the transistor portion may have a first lower end region of the second conductivity type provided in contact with a lower end of at least one of the trench portions.
  • the lower end of at least one of the trench portions of the diode portion may not be in contact with the second conductivity type region.
  • the lower ends of all the trench portions of the diode portion do not need to be in contact with the second conductivity type region.
  • the diode portion may have a second lower end region of a first conductivity type that is provided in contact with a lower end of at least one of the trench portions and has a higher doping concentration than the drift region.
  • the lower end of at least one of the trench portions of the transistor portion may not be in contact with a first conductivity type region having a higher doping concentration than the drift region.
  • the transistor section may have a second conductivity type base region provided between the emitter region and the drift region.
  • the transistor section may include a first conductivity type storage region provided between the base region and the drift region and having a higher doping concentration than the drift region.
  • the doping concentration of the second lower end region may be lower than the doping concentration of the accumulation region.
  • the diode section may include a lifetime adjustment section that adjusts the lifetime of the carrier on the upper surface side of the semiconductor substrate.
  • a second aspect of the present invention provides a semiconductor device.
  • the semiconductor device may include a semiconductor substrate that has an upper surface and a lower surface and is provided with a drift region of a first conductivity type.
  • the semiconductor device includes a collector region of a second conductivity type in contact with the lower surface of the semiconductor substrate, and an emitter region of a first conductivity type provided in contact with the upper surface of the semiconductor substrate and having a higher doping concentration than the drift region.
  • a transistor portion may be provided. Any of the above semiconductor devices may include a diode portion having a first conductivity type cathode region in contact with the lower surface of the semiconductor substrate.
  • the diode section and the transistor section may have a plurality of trench sections arranged at intervals along the arrangement direction on the upper surface of the semiconductor substrate.
  • the transistor portion may include a first lower end region of the second conductivity type provided in contact with a lower end of at least one of the trench portions.
  • the lower end of at least one of the trench portions of the diode portion may not be in contact with the second conductivity type region.
  • a third aspect of the present invention provides a method for manufacturing a semiconductor device having a transistor section and a diode section on a semiconductor substrate.
  • a non-destructive maximum energy density at which the semiconductor device is not destroyed may be obtained by a non-clamp dielectric switching test.
  • a ratio of avalanche breakdown voltages of the diode portion and the transistor portion is set so that the non-destructive maximum energy density is greater than that of the first semiconductor device. It's fine.
  • the transistor section and the diode section in the second semiconductor device may be designed so as to satisfy the set avalanche breakdown voltage ratio.
  • the second semiconductor device may be manufactured based on the design.
  • FIG. 1 is a top view showing an example of a semiconductor device 100 according to one embodiment of the present invention.
  • 2 is an enlarged view of region D in FIG. 1.
  • FIG. 3 is a diagram showing an example of a cross section taken along line ee in FIG. 2.
  • FIG. 3 is an example of current density-voltage characteristics of a transistor section 70 and a diode section 80 according to a reference example.
  • 3 is an example of current density-voltage characteristics of a transistor section 70 and a diode section 80 according to an example.
  • FIG. 3 is a diagram showing an example of a cross section taken along line ee according to the embodiment.
  • FIG. 7 is a diagram showing another example of the ee cross section according to the embodiment.
  • FIG. 7 is a diagram showing another example of the ee cross section according to the embodiment.
  • FIG. 7 is a diagram showing another example of the ee cross section according to the embodiment.
  • FIG. 7 is a diagram showing another example of the ee cross section according to the embodiment.
  • FIG. 7 is a diagram showing another example of the ee cross section according to the embodiment.
  • FIG. 7 is a diagram showing another example of the ee cross section according to the embodiment.
  • FIG. 7 is a diagram showing another example of the ee cross section according to the embodiment.
  • FIG. 7 is a diagram showing another example of the ee cross section according to the embodiment.
  • FIG. 7 is a diagram showing another example of the ee cross section according to the embodiment.
  • FIG. 7 is a diagram showing another example of the ee cross section according to the embodiment.
  • FIG. 7 is a diagram showing another example of the ee cross section according to the embodiment.
  • FIG. 7 is a diagram showing another example of the ee cross section according to the embodiment.
  • 7 is a diagram showing the relationship between the trench spacing in the transistor section 70 and the diode section 80 and the avalanche breakdown voltage in the transistor section 70 and the diode section 80.
  • FIG. 7 is a diagram showing the relationship between the trench length in the transistor section 70 and the diode section 80 and the avalanche breakdown voltage in the transistor section 70 and the diode section 80.
  • FIG. 7 is a diagram showing the relationship between the trench spacing in the transistor section 70 and the diode section 80 and the avalanche breakdown voltage in the transistor section 70 and the diode section 80.
  • FIG. 7 is a diagram showing the relationship between the dose amount (or doping concentration) in the second lower end region 204 of the diode section 80 and the avalanche breakdown voltage of the diode section 80.
  • FIG. 3 is a diagram illustrating the non-destructive maximum energy density of the semiconductor device 100.
  • FIG. The relationship between the avalanche breakdown voltage Va_d and the non-destructive maximum energy density in the diode section 80 is shown.
  • 1 is a diagram illustrating an example of a method for manufacturing a semiconductor device 100.
  • one side in the direction parallel to the depth direction of the semiconductor substrate is referred to as "upper”, and the other side is referred to as “lower”.
  • one surface is referred to as the upper surface and the other surface is referred to as the lower surface.
  • the “up” and “down” directions are not limited to the gravitational direction or the direction in which the semiconductor device is mounted.
  • orthogonal coordinate axes of the X-axis, Y-axis, and Z-axis only specify the relative positions of the components and do not limit specific directions.
  • the Z axis does not limit the height direction relative to the ground.
  • the +Z-axis direction and the -Z-axis direction are directions opposite to each other.
  • the Z-axis direction is described without indicating positive or negative, it means a direction parallel to the +Z-axis and the -Z-axis.
  • orthogonal axes parallel to the top and bottom surfaces of the semiconductor substrate are referred to as the X axis and the Y axis. Further, the axis perpendicular to the upper and lower surfaces of the semiconductor substrate is defined as the Z axis.
  • the direction of the Z-axis may be referred to as the depth direction.
  • a direction parallel to the top and bottom surfaces of the semiconductor substrate, including the X-axis and Y-axis may be referred to as a horizontal direction.
  • the region from the center of the semiconductor substrate in the depth direction to the top surface of the semiconductor substrate is sometimes referred to as the top surface side.
  • the region from the center of the semiconductor substrate in the depth direction to the lower surface of the semiconductor substrate may be referred to as the lower surface side.
  • the conductivity type of the doped region doped with impurities is described as P type or N type.
  • an impurity may particularly mean either an N-type donor or a P-type acceptor, and may be referred to as a dopant.
  • doping means introducing a donor or an acceptor into a semiconductor substrate to make it a semiconductor exhibiting an N-type conductivity type or a semiconductor exhibiting a P-type conductivity type.
  • doping concentration refers to the donor concentration or acceptor concentration at thermal equilibrium.
  • the net doping concentration means the net concentration obtained by adding together the donor concentration, which is the positive ion concentration, and the acceptor concentration, which is the negative ion concentration, including charge polarity.
  • the donor concentration is N D and the acceptor concentration is N A
  • the net net doping concentration at any location is N D ⁇ NA .
  • the net doping concentration may be simply referred to as doping concentration.
  • the donor has the function of supplying electrons to the semiconductor.
  • the acceptor has the function of receiving electrons from the semiconductor.
  • Donors and acceptors are not limited to impurities themselves.
  • a VOH defect in which vacancies (V), oxygen (O), and hydrogen (H) are bonded together in a semiconductor functions as a donor that supplies electrons.
  • VOH defects may be referred to as hydrogen donors.
  • the hydrogen donor may be a donor to which at least a vacancy (V) and hydrogen (H) are bonded.
  • the semiconductor substrate herein has N-type bulk donors distributed throughout.
  • the bulk donor is a donor made from a dopant that is substantially uniformly contained in the ingot during manufacture of the ingot that is the source of the semiconductor substrate.
  • the bulk donor in this example is an element other than hydrogen.
  • Bulk donor dopants include, but are not limited to, phosphorus, antimony, arsenic, selenium or sulfur.
  • the bulk donor in this example is phosphorus.
  • Bulk donors are also included in the P-type region.
  • the semiconductor substrate may be a wafer cut from a semiconductor ingot, or may be a chip obtained by cutting the wafer into pieces.
  • the semiconductor ingot may be manufactured by any one of the Czochralski method (CZ method), the magnetic field Czochralski method (MCZ method), and the float zone method (FZ method).
  • the ingot in this example is manufactured by the MCZ method.
  • the oxygen concentration contained in the substrate manufactured by the MCZ method is 1 ⁇ 10 17 to 7 ⁇ 10 17 /cm 3 .
  • the oxygen concentration contained in the substrate manufactured by the FZ method is 1 ⁇ 10 15 to 5 ⁇ 10 16 /cm 3 .
  • Hydrogen donors tend to be generated more easily when the oxygen concentration is high.
  • the bulk donor concentration may be a chemical concentration of bulk donors distributed throughout the semiconductor substrate, and may be between 90% and 100% of the chemical concentration.
  • the semiconductor substrate may be a non-doped substrate that does not contain a dopant such as phosphorus.
  • the bulk donor concentration (D0) of the non-doped substrate is, for example, 1 ⁇ 10 10 /cm 3 or more and 5 ⁇ 10 12 /cm 3 or less.
  • the bulk donor concentration (D0) of the non-doped substrate is preferably 1 ⁇ 10 11 /cm 3 or more.
  • the bulk donor concentration (D0) of the non-doped substrate is preferably 5 ⁇ 10 12 /cm 3 or less.
  • each concentration in the present invention may be a value at room temperature. As an example of the value at room temperature, the value at 300K (Kelvin) (about 26.9°C) may be used.
  • the doping concentration when described as P+ type or N+ type, it means that the doping concentration is higher than P type or N type, and when described as P ⁇ type or N ⁇ type, it means that the doping concentration is higher than P type or N type. It means that the concentration is low. Further, in this specification, when it is described as P++ type or N++ type, it means that the doping concentration is higher than that of P+ type or N+ type.
  • the unit system in this specification is the SI unit system unless otherwise specified. Although the unit of length is sometimes expressed in cm, various calculations may be performed after converting to meters (m).
  • chemical concentration refers to the atomic density of impurities measured regardless of the state of electrical activation.
  • the chemical concentration can be measured, for example, by secondary ion mass spectrometry (SIMS).
  • the above-mentioned net doping concentration can be measured by voltage-capacitance measurement (CV method).
  • the carrier concentration measured by the spreading resistance measurement method (SR method) may be taken as the net doping concentration.
  • the carrier concentration measured by the CV method or the SR method may be a value in a thermal equilibrium state.
  • the donor concentration is sufficiently higher than the acceptor concentration, so the carrier concentration in this region may be taken as the donor concentration.
  • the carrier concentration in the region may be set as the acceptor concentration.
  • the doping concentration of the N-type region may be referred to as a donor concentration
  • the doping concentration of the P-type region may be referred to as an acceptor concentration.
  • the peak value may be taken as the donor, acceptor, or net doping concentration in the region.
  • the average value of the donor, acceptor, or net doping concentration in the region may be taken as the donor, acceptor, or net doping concentration.
  • atoms/cm 3 or /cm 3 is used to express the concentration per unit volume. This unit is used for donor or acceptor concentration or chemical concentration within a semiconductor substrate. The atoms notation may be omitted.
  • the carrier concentration measured by the SR method may be lower than the donor or acceptor concentration.
  • the carrier mobility of the semiconductor substrate may be lower than the value in the crystalline state. The decrease in carrier mobility occurs when carriers are scattered due to disorder of the crystal structure due to lattice defects or the like.
  • the concentration of the donor or acceptor calculated from the carrier concentration measured by the CV method or the SR method may be lower than the chemical concentration of the element representing the donor or acceptor.
  • the donor concentration of phosphorus or arsenic as a donor, or the acceptor concentration of boron (boron) as an acceptor is about 99% of these chemical concentrations.
  • the donor concentration of hydrogen, which serves as a donor in a silicon semiconductor is about 0.1% to 10% of the chemical concentration of hydrogen.
  • FIG. 1 is a top view showing an example of a semiconductor device 100 according to one embodiment of the present invention.
  • FIG. 1 the positions of each member projected onto the upper surface of the semiconductor substrate 10 are shown.
  • FIG. 1 only some members of the semiconductor device 100 are shown, and some members are omitted.
  • the semiconductor device 100 includes a semiconductor substrate 10.
  • the semiconductor substrate 10 is a substrate made of a semiconductor material.
  • the semiconductor substrate 10 is a silicon substrate.
  • the semiconductor substrate 10 has an edge 162 when viewed from above. In this specification, when simply referred to as a top view, it means viewed from the top surface side of the semiconductor substrate 10.
  • the semiconductor substrate 10 of this example has two sets of end sides 162 that face each other when viewed from above. In FIG. 1, the X and Y axes are parallel to either edge 162. Further, the Z axis is perpendicular to the top surface of the semiconductor substrate 10.
  • An active part 160 is provided on the semiconductor substrate 10.
  • the active portion 160 is a region where a main current flows in the depth direction between the upper surface and the lower surface of the semiconductor substrate 10 when the semiconductor device 100 operates.
  • An emitter electrode is provided above the active region 160, but is omitted in FIG.
  • the active portion 160 may refer to a region that overlaps with the emitter electrode when viewed from above. Furthermore, the region sandwiched between the active portions 160 in a top view may also be included in the active portions 160.
  • the active section 160 is provided with a transistor section 70 including a transistor element such as an IGBT (Insulated Gate Bipolar Transistor).
  • the active section 160 may further include a diode section 80 including a diode element such as a free-wheeling diode (FWD).
  • FWD free-wheeling diode
  • the transistor sections 70 and the diode sections 80 are alternately arranged along a predetermined arrangement direction (in this example, the X-axis direction) on the upper surface of the semiconductor substrate 10.
  • the semiconductor device 100 of this example is a reverse conduction type IGBT (RC-IGBT).
  • the region where the transistor section 70 is arranged is marked with the symbol "I"
  • the region where the diode section 80 is arranged is marked with the symbol "F”.
  • a direction perpendicular to the arrangement direction in a top view may be referred to as a stretching direction (Y-axis direction in FIG. 1).
  • the transistor section 70 and the diode section 80 may each have a length in the extending direction. In other words, the length of the transistor section 70 in the Y-axis direction is greater than the width in the X-axis direction. Similarly, the length of the diode section 80 in the Y-axis direction is greater than the width in the X-axis direction.
  • the extending direction of the transistor section 70 and the diode section 80 may be the same as the longitudinal direction of each trench section, which will be described later.
  • the diode section 80 has an N+ type cathode region in a region in contact with the lower surface of the semiconductor substrate 10.
  • the region provided with the cathode region is referred to as a diode section 80.
  • the diode section 80 is a region that overlaps with the cathode region when viewed from above.
  • a P+ type collector region may be provided on the lower surface of the semiconductor substrate 10 in a region other than the cathode region.
  • the diode section 80 may also include an extension region 81 in which the diode section 80 is extended in the Y-axis direction to a gate wiring to be described later.
  • a collector region is provided on the lower surface of the extension region 81.
  • the transistor section 70 has a P+ type collector region in a region in contact with the lower surface of the semiconductor substrate 10. Further, in the transistor section 70, a gate structure including an N-type emitter region, a P-type base region, a gate conductive portion, and a gate insulating film is periodically arranged on the upper surface side of the semiconductor substrate 10.
  • the semiconductor device 100 may have one or more pads above the semiconductor substrate 10.
  • the semiconductor device 100 of this example has a gate pad 164.
  • the semiconductor device 100 may have pads such as an anode pad, a cathode pad, and a current detection pad. Each pad is located near the edge 162.
  • the vicinity of the edge 162 refers to the area between the edge 162 and the emitter electrode in a top view.
  • each pad may be connected to an external circuit via wiring such as a wire.
  • a gate potential is applied to the gate pad 164.
  • the gate pad 164 is electrically connected to a conductive portion of the gate trench portion of the active portion 160 .
  • the semiconductor device 100 includes a gate wiring that connects the gate pad 164 and the gate trench portion. In FIG. 1, the gate wiring is hatched.
  • the gate wiring in this example includes an outer gate wiring 130 and an active side gate wiring 131.
  • the outer gate wiring 130 is arranged between the active region 160 and the edge 162 of the semiconductor substrate 10 when viewed from above.
  • the outer gate wiring 130 of this example surrounds the active region 160 when viewed from above.
  • the active portion 160 may be a region surrounded by the outer gate wiring 130 when viewed from above.
  • a well region is formed below the gate wiring.
  • the well region is a P-type region with a higher concentration than the base region described later, and is formed from the upper surface of the semiconductor substrate 10 to a position deeper than the base region.
  • the active region 160 may be a region surrounded by the well region in a top view.
  • the outer gate wiring 130 is connected to the gate pad 164.
  • the outer gate wiring 130 is arranged above the semiconductor substrate 10.
  • the outer gate wiring 130 may be a metal wiring containing aluminum or the like.
  • the active side gate wiring 131 is provided in the active part 160. By providing the active side gate wiring 131 in the active portion 160, variations in wiring length from the gate pad 164 can be reduced in each region of the semiconductor substrate 10.
  • the outer gate wiring 130 and the active side gate wiring 131 are connected to the gate trench portion of the active part 160.
  • the outer gate wiring 130 and the active side gate wiring 131 are arranged above the semiconductor substrate 10.
  • the outer gate wiring 130 and the active side gate wiring 131 may be wirings formed of a semiconductor such as polysilicon doped with impurities.
  • the active side gate wiring 131 may be connected to the outer peripheral gate wiring 130.
  • the active side gate wiring 131 in this example extends in the X-axis direction from one outer peripheral gate wiring 130 to the other outer peripheral gate wiring 130 sandwiching the active region 160 so as to cross the active region 160 at approximately the center in the Y-axis direction. It is provided.
  • the transistor sections 70 and the diode sections 80 may be arranged alternately in the X-axis direction in each divided region.
  • the semiconductor device 100 may include a temperature sensing section (not shown) that is a PN junction diode made of polysilicon or the like, and a current detection section (not shown) that simulates the operation of a transistor section provided in the active section 160. .
  • the semiconductor device 100 of this example includes an edge termination structure portion 90 between the active portion 160 and the end side 162 when viewed from above.
  • the edge termination structure section 90 of this example is arranged between the outer peripheral gate wiring 130 and the end side 162.
  • the edge termination structure 90 alleviates electric field concentration on the upper surface side of the semiconductor substrate 10.
  • the edge termination structure 90 may include at least one of a guard ring, a field plate, and a resurf provided in an annular manner surrounding the active portion 160.
  • FIG. 2 is an enlarged view of region D in FIG. 1.
  • Region D is a region including the transistor section 70, the diode section 80, and the active side gate wiring 131.
  • the semiconductor device 100 of this example includes a connection region 190 between the transistor section 70 and the diode section 80.
  • the semiconductor device 100 of this example includes a gate trench section 40, a dummy trench section 30, a well region 11, an emitter region 12, a base region 14, and a contact region 15 provided inside the upper surface side of a semiconductor substrate 10.
  • Each of the gate trench section 40 and the dummy trench section 30 is an example of a trench section.
  • the semiconductor device 100 of this example includes an emitter electrode 52 and an active side gate wiring 131 provided above the upper surface of the semiconductor substrate 10. Emitter electrode 52 and active side gate wiring 131 are provided separately from each other.
  • An interlayer insulating film is provided between the emitter electrode 52 and the active side gate wiring 131 and the upper surface of the semiconductor substrate 10, but is omitted in FIG. 2.
  • a contact hole 54 is provided in the interlayer insulating film of this example, penetrating the interlayer insulating film. In FIG. 2, each contact hole 54 is indicated by diagonal hatching.
  • the emitter electrode 52 is provided above the gate trench section 40, dummy trench section 30, well region 11, emitter region 12, base region 14, and contact region 15. Emitter electrode 52 contacts emitter region 12, contact region 15, and base region 14 on the upper surface of semiconductor substrate 10 through contact hole 54. Further, the emitter electrode 52 is connected to a dummy conductive portion within the dummy trench portion 30 through a contact hole provided in the interlayer insulating film. The emitter electrode 52 may be connected to the dummy conductive part of the dummy trench part 30 at the tip of the dummy trench part 30 in the Y-axis direction. The dummy conductive portion of the dummy trench portion 30 does not need to be connected to the emitter electrode 52 and the gate conductive portion, and may be controlled to a different potential from the potential of the emitter electrode 52 and the potential of the gate conductive portion.
  • the active side gate wiring 131 is connected to the gate trench portion 40 through a contact hole provided in the interlayer insulating film.
  • the active side gate wiring 131 may be connected to the gate conductive portion of the gate trench portion 40 at the tip portion 41 of the gate trench portion 40 in the Y-axis direction.
  • the active side gate wiring 131 is not connected to the dummy conductive part in the dummy trench part 30.
  • the emitter electrode 52 is formed of a material containing metal.
  • FIG. 2 shows a range where the emitter electrode 52 is provided.
  • the emitter electrode 52 is formed of aluminum or an aluminum-silicon alloy, such as a metal alloy such as AlSi or AlSiCu.
  • the emitter electrode 52 may include a barrier metal made of titanium, a titanium compound, or the like below a region made of aluminum or the like.
  • a plug may be formed by burying tungsten or the like in contact with the barrier metal and aluminum in the contact hole.
  • the well region 11 is provided to overlap the active side gate wiring 131.
  • the well region 11 is provided extending with a predetermined width even in a range that does not overlap with the active side gate wiring 131.
  • the well region 11 in this example is provided away from the end of the contact hole 54 in the Y-axis direction toward the active side gate wiring 131 side.
  • the well region 11 is a second conductivity type region having a higher doping concentration than the base region 14 .
  • the well region 11 may be formed from the upper surface of the semiconductor substrate 10 to a depth deeper than the lower end of the trench portion.
  • the base region 14 in this example is of P- type, and the well region 11 is of P+ type.
  • Each of the transistor section 70, the connection region 190, and the diode section 80 has a plurality of trench sections arranged in the arrangement direction.
  • the transistor section 70 of this example one or more gate trench sections 40 and one or more dummy trench sections 30 are alternately provided along the arrangement direction.
  • the connection region 190 of this example a plurality of dummy trench portions 30 are provided along the arrangement direction.
  • the diode section 80 of this example a plurality of dummy trench sections 30 are provided along the arrangement direction.
  • the gate trench portion 40 is not provided in the connection region 190 and the diode portion 80 in this example, the gate trench portion 40 may be provided in the connection region 190 and the diode portion 80.
  • the gate trench portion 40 of this example connects two straight portions 39 extending along the stretching direction perpendicular to the arrangement direction (a portion of the trench portion that is linear along the stretching direction) and the two straight portions 39.
  • the tip portion 41 may have a tip portion 41.
  • the stretching direction in FIG. 2 is the Y-axis direction.
  • At least a portion of the tip portion 41 be provided in a curved shape when viewed from above.
  • the dummy trench section 30 is provided between each straight portion 39 of the gate trench section 40.
  • One dummy trench section 30 may be provided between each straight portion 39, or a plurality of dummy trench sections 30 may be provided.
  • the dummy trench portion 30 may have a linear shape extending in the extending direction, and may have a linear portion 29 and a tip portion 31 similarly to the gate trench portion 40.
  • the semiconductor device 100 shown in FIG. 2 includes both a linear dummy trench section 30 that does not have a tip 31 and a dummy trench section 30 that has a tip 31.
  • the diffusion depth of the well region 11 may be deeper than the depths of the gate trench portion 40 and the dummy trench portion 30. Ends of the gate trench section 40 and the dummy trench section 30 in the Y-axis direction are provided in the well region 11 when viewed from above. That is, at the end of each trench portion in the Y-axis direction, the bottom portion of each trench portion in the depth direction is covered with the well region 11 . Thereby, electric field concentration at the bottom of each trench portion can be alleviated.
  • a mesa portion is provided between each trench portion in the arrangement direction.
  • the mesa portion refers to a region sandwiched between trench portions inside the semiconductor substrate 10.
  • the upper end of the mesa portion is the upper surface of the semiconductor substrate 10.
  • the depth position of the lower end of the mesa portion is the same as the depth position of the lower end of the trench portion.
  • the mesa portion of this example is provided on the upper surface of the semiconductor substrate 10 so as to extend in the extending direction (Y-axis direction) along the trench.
  • the transistor section 70 is provided with a mesa section 60
  • the diode section 80 is provided with a mesa section 61
  • the connection region 190 is provided with a mesa section 62.
  • a mesa portion it refers to mesa portion 60, mesa portion 61, and mesa portion 62, respectively.
  • a base region 14 is provided in each mesa portion. Among the base regions 14 exposed on the upper surface of the semiconductor substrate 10 in the mesa portion, a region disposed closest to the active side gate wiring 131 is defined as a base region 14-e. In FIG. 2, the base region 14-e is shown arranged at one end of each mesa in the extending direction, but the base region 14-e is also arranged at the other end of each mesa. has been done.
  • at least one of the emitter region 12 of the first conductivity type and the contact region 15 of the second conductivity type may be provided in a region sandwiched between the base regions 14-e when viewed from above.
  • Emitter region 12 in this example is of N+ type
  • contact region 15 is of P+ type.
  • Emitter region 12 and contact region 15 may be provided between base region 14 and the upper surface of semiconductor substrate 10 in the depth direction.
  • the mesa portion 60 of the transistor portion 70 has an emitter region 12 exposed on the upper surface of the semiconductor substrate 10. Emitter region 12 is provided in contact with gate trench portion 40 . A contact region 15 exposed on the upper surface of the semiconductor substrate 10 may be provided in the mesa portion 60 in contact with the gate trench portion 40 .
  • Each of the contact region 15 and emitter region 12 in the mesa portion 60 is provided from one trench portion to the other trench portion in the X-axis direction.
  • the contact regions 15 and emitter regions 12 of the mesa section 60 are arranged alternately along the extending direction (Y-axis direction) of the trench section.
  • the contact region 15 and emitter region 12 of the mesa portion 60 may be provided in a stripe shape along the extending direction (Y-axis direction) of the trench portion.
  • an emitter region 12 is provided in a region in contact with the trench portion, and a contact region 15 is provided in a region sandwiched between the emitter regions 12.
  • the emitter region 12 is not provided in the mesa portion 61 of the diode portion 80 and the mesa portion 62 of the connection region 190.
  • the base region 14 and the contact region 15 may be provided on the upper surfaces of the mesa portions 61 and 62.
  • a contact region 15 may be provided in a region between the base regions 14-e on the upper surface of the mesa portion 61 and the mesa portion 62 in contact with the respective base regions 14-e.
  • the base region 14 may be provided in a region sandwiched between the contact regions 15 on the upper surface of the mesa portion 61 .
  • the base region 14 may be arranged in the entire region sandwiched between the contact regions 15.
  • a contact hole 54 is provided above each mesa portion. Contact hole 54 is arranged in a region sandwiched between base regions 14-e. Contact hole 54 in this example is provided above each of contact region 15, base region 14, and emitter region 12. Contact hole 54 is not provided in a region corresponding to base region 14-e and well region 11.
  • the contact hole 54 may be arranged at the center of the mesa portion 60 in the arrangement direction (X-axis direction).
  • an N+ type cathode region 82 is provided in a region adjacent to the lower surface of the semiconductor substrate 10.
  • a P+ type collector region 22 may be provided in a region where the cathode region 82 is not provided.
  • a cathode region 82 may be provided in a region adjacent to the lower surface of the semiconductor substrate 10
  • a collector region 22 may be provided, or both the cathode region 82 and the collector region 22 may be provided.
  • Cathode region 82 and collector region 22 are provided between lower surface 23 of semiconductor substrate 10 and buffer region 20. In FIG. 2, the boundary between the cathode region 82 and the collector region 22 is shown by a dotted line.
  • the cathode region 82 is arranged apart from the well region 11 in the Y-axis direction. Thereby, the distance between the P-type region (well region 11), which has a relatively high doping concentration and is formed to a deep position, and the cathode region 82 can be secured, and the breakdown voltage can be improved.
  • the end of the cathode region 82 in the Y-axis direction is located farther from the well region 11 than the end of the contact hole 54 in the Y-axis direction.
  • the end of the cathode region 82 in the Y-axis direction may be arranged between the well region 11 and the contact hole 54.
  • FIG. 3 is a diagram showing an example of the ee cross section in FIG. 2.
  • FIG. 3 shows a structure according to a reference example.
  • the ee cross section is an XZ plane passing through the emitter region 12 and the cathode region 82.
  • the ee cross section includes the transistor section 70, the connection region 190, and the diode section 80.
  • the semiconductor device 100 of this example includes a semiconductor substrate 10, an interlayer insulating film 38, an emitter electrode 52, and a collector electrode 24 in the cross section.
  • the interlayer insulating film 38 is provided on the upper surface of the semiconductor substrate 10.
  • the interlayer insulating film 38 is a film including at least one layer of an insulating film such as silicate glass doped with impurities such as boron or phosphorus, a thermal oxide film, and other insulating films.
  • the contact hole 54 described in FIG. 2 is provided in the interlayer insulating film 38.
  • the emitter electrode 52 is provided above the interlayer insulating film 38. Emitter electrode 52 is in contact with upper surface 21 of semiconductor substrate 10 through contact hole 54 of interlayer insulating film 38 .
  • Collector electrode 24 is provided on lower surface 23 of semiconductor substrate 10 .
  • the emitter electrode 52 and the collector electrode 24 are made of a metal material such as aluminum.
  • the direction (Z-axis direction) connecting the emitter electrode 52 and the collector electrode 24 is referred to as the depth direction.
  • the semiconductor substrate 10 has an N-type or N-type drift region 18.
  • Drift region 18 is provided in each of transistor section 70, diode section 80, and connection region 190.
  • an N+ type emitter region 12 and a P ⁇ type base region 14 are provided in order from the upper surface 21 side of the semiconductor substrate 10.
  • a drift region 18 is provided below the base region 14 .
  • the mesa portion 60 may be provided with an N+ type storage region 16.
  • Accumulation region 16 is located between base region 14 and drift region 18 .
  • the emitter region 12 is exposed on the upper surface 21 of the semiconductor substrate 10 and is provided in contact with the gate trench portion 40.
  • the emitter region 12 may be in contact with the trench portions on both sides of the mesa portion 60.
  • Emitter region 12 has a higher doping concentration than drift region 18 .
  • a contact region 15 is provided in place of the emitter region 12.
  • the base region 14 is provided below the emitter region 12.
  • the base region 14 in this example is provided in contact with the emitter region 12.
  • the base region 14 may be in contact with the trench portions on both sides of the mesa portion 60.
  • the storage region 16 is provided below the base region 14.
  • the accumulation region 16 is an N+ type region having a higher doping concentration than the drift region 18. That is, the accumulation region 16 has a higher donor concentration than the drift region 18.
  • the carrier injection promotion effect IE effect
  • the storage region 16 may be provided so as to cover the entire lower surface of the base region 14 in each mesa portion 60.
  • a P ⁇ type base region 14 is provided in the mesa portion 61 of the diode portion 80 in contact with the upper surface 21 of the semiconductor substrate 10.
  • a drift region 18 is provided below the base region 14 .
  • the storage region 16 may be provided below the base region 14.
  • a contact region 15 may be provided on the upper surface 21 of the mesa portion 61 below the contact hole 54 .
  • a P- type base region 14 is provided in the mesa portion 62 of the connection region 190 in contact with the upper surface 21 of the semiconductor substrate 10.
  • a drift region 18 is provided below the base region 14 .
  • the storage region 16 may be provided below the base region 14.
  • a contact region 15 may be provided on the upper surface 21 of the mesa portion 62 below the contact hole 54 .
  • An N+ type buffer region 20 may be provided under the drift region 18 in each of the transistor section 70, diode section 80, and connection region 190.
  • the doping concentration of buffer region 20 is higher than the doping concentration of drift region 18 .
  • Buffer region 20 may have a concentration peak with a higher doping concentration than drift region 18 .
  • the doping concentration at the concentration peak refers to the doping concentration at the apex of the concentration peak.
  • the average value of the doping concentration in a region where the doping concentration distribution is substantially flat may be used as the doping concentration of the drift region 18, the average value of the doping concentration in a region where the doping concentration distribution is substantially flat may be used.
  • the buffer region 20 may have two or more concentration peaks in the depth direction (Z-axis direction) of the semiconductor substrate 10.
  • the concentration peak of the buffer region 20 may be provided at the same depth position as the chemical concentration peak of hydrogen (protons) or phosphorus, for example.
  • Buffer region 20 may function as a field stop layer that prevents a depletion layer spreading from the lower end of base region 14 from reaching P+ type collector region 22 and N+ type cathode region 82.
  • a P+ type collector region 22 is provided below the buffer region 20.
  • the acceptor concentration in collector region 22 is higher than the acceptor concentration in base region 14 .
  • Collector region 22 may contain the same acceptors as base region 14 or may contain different acceptors.
  • the acceptor in the collector region 22 is, for example, boron.
  • an N+ type cathode region 82 is provided below the buffer region 20.
  • a collector region 22 may be provided below the buffer region 20, and a cathode region 82 may be provided.
  • the collector region 22 is provided below all the mesa portions 62.
  • the donor concentration in the cathode region 82 is higher than that in the drift region 18.
  • the donor of cathode region 82 is, for example, hydrogen or phosphorus. Note that the elements serving as donors and acceptors in each region are not limited to the above-mentioned examples.
  • Collector region 22 and cathode region 82 are exposed on lower surface 23 of semiconductor substrate 10 and connected to collector electrode 24 .
  • Collector electrode 24 may be in contact with the entire lower surface 23 of semiconductor substrate 10 .
  • the emitter electrode 52 and the collector electrode 24 are formed of a metal material such as aluminum.
  • each trench portion is provided from the upper surface 21 of the semiconductor substrate 10, penetrating the base region 14, and reaching below the base region 14. In regions where at least one of emitter region 12, contact region 15 and storage region 16 is provided, each trench portion also passes through these doped regions.
  • the trench portion penetrating the doping region is not limited to manufacturing in the order in which the doping region is formed and then the trench portion is formed.
  • a structure in which a doping region is formed between the trench sections after the trench section is formed is also included in the structure in which the trench section penetrates the doping region.
  • the transistor section 70 is provided with the gate trench section 40 and the dummy trench section 30.
  • the dummy trench section 30 is provided in the diode section 80 and the connection region 190, and the gate trench section 40 is not provided.
  • the gate trench portion 40 includes a gate trench provided on the upper surface 21 of the semiconductor substrate 10, a gate insulating film 42, and a gate conductive portion 44.
  • the gate insulating film 42 is provided to cover the inner wall of the gate trench.
  • the gate insulating film 42 may be formed by oxidizing or nitriding the semiconductor on the inner wall of the gate trench.
  • the gate conductive portion 44 is provided inside the gate trench inside the gate insulating film 42 . That is, the gate insulating film 42 insulates the gate conductive portion 44 and the semiconductor substrate 10.
  • Gate conductive portion 44 is formed of a conductive material such as polysilicon.
  • the gate conductive portion 44 may be provided longer than the base region 14 in the depth direction.
  • the gate trench portion 40 in the cross section is covered with the interlayer insulating film 38 on the upper surface 21 of the semiconductor substrate 10 .
  • the gate conductive portion 44 is electrically connected to the gate wiring. When a predetermined gate voltage is applied to the gate conductive portion 44, a channel is formed by an electron inversion layer in the surface layer of the interface of the base region 14 that is in contact with the gate trench portion 40.
  • the dummy trench portion 30 may have the same structure as the gate trench portion 40 in the cross section.
  • the dummy trench section 30 includes a dummy trench provided on the upper surface 21 of the semiconductor substrate 10, a dummy insulating film 32, and a dummy conductive section 34.
  • the dummy conductive portion 34 is electrically connected to the emitter electrode 52.
  • the dummy insulating film 32 is provided to cover the inner wall of the dummy trench.
  • the dummy conductive portion 34 is provided inside the dummy trench and further inside the dummy insulating film 32 .
  • the dummy insulating film 32 insulates the dummy conductive portion 34 and the semiconductor substrate 10.
  • the dummy conductive part 34 may be formed of the same material as the gate conductive part 44.
  • the dummy conductive portion 34 is formed of a conductive material such as polysilicon.
  • the dummy conductive portion 34 may have the same length as the gate conductive portion 44 in the depth direction.
  • the gate trench portion 40 and dummy trench portion 30 of this example are covered with an interlayer insulating film 38 on the upper surface 21 of the semiconductor substrate 10.
  • the bottoms of the dummy trench section 30 and the gate trench section 40 may have a downwardly convex curved surface (curved in cross section).
  • the depth position of the lower end of the gate trench portion 40 is defined as Zt.
  • each trench portion that is, the width of each mesa portion
  • the depth of each trench portion in the Z-axis direction that is, the lower end position Zt
  • a P-type collector region 22 is provided on the lower surface 23 of the transistor section 70, and a PNP transistor composed of, for example, a base region 14, a drift region 18, and a collector region 22 is formed.
  • Avalanche breakdown voltage is the voltage at which avalanche breakdown first occurs at any point when the voltage between the collector electrode 24 and emitter electrode 52 is gradually increased and each voltage is applied for a sufficiently long time. Point. In other words, avalanche breakdown voltage refers to static breakdown voltage.
  • FIG. 4 is an example of current density-voltage characteristics of the transistor section 70 and the diode section 80 according to the reference example.
  • the collector voltage of the transistor section 70 reaches the avalanche breakdown voltage Va_t of the transistor section 70, avalanche breakdown occurs at a portion of the transistor section 70 where the breakdown voltage is low, and the collector current increases rapidly.
  • the cathode voltage of the diode section 80 reaches the avalanche breakdown voltage Va_d of the diode section 80, avalanche breakdown occurs in the diode section 80 and the cathode current increases rapidly.
  • the semiconductor device 100 is designed such that both the avalanche breakdown voltage Va_t of the transistor section 70 and the avalanche breakdown voltage Va_d of the diode section 80 are larger than the breakdown voltage specification value V0 of the semiconductor device 100.
  • the avalanche breakdown voltage Va_t of the transistor section 70 is the minimum voltage among the voltages at a portion where the collector voltage is approximately constant (flat) with respect to an increase in collector current in the current density-voltage characteristics shown in FIG. It can be defined as The current density-voltage characteristics may be measured in an ambient temperature environment of room temperature (25° C.).
  • the avalanche breakdown voltage Va_d of the diode section 80 may be defined as the minimum voltage among the voltages at a portion where the cathode voltage is approximately constant (flat) in the current density-voltage characteristics shown in FIG. "Substantially flat" means that, for example, the current fluctuates by a factor of 100 while the voltage fluctuates by 20 V or less.
  • the avalanche breakdown voltage Va_t of the transistor section 70 is defined as the portion where the waveform of the collector voltage is approximately constant (flat) with respect to an increase in the collector current in the current density-voltage characteristics shown in FIG. may be defined as the value of the collector voltage at a preset value of the collector current.
  • the avalanche withstand voltage Va_d of the diode section 80 is determined by a preset cathode current among the voltages at a portion where the cathode voltage is approximately constant (flat) with respect to an increase in cathode current in the current density-voltage characteristics shown in FIG. It may be defined as the value of the cathode voltage at the value of .
  • the collector voltage or cathode voltage when the collector current or cathode current is 1 ⁇ 10 ⁇ 3 (A/cm 2 ) may be taken as the avalanche breakdown voltage Va_t.
  • the preset collector current or cathode current value may be 1 ⁇ 10 ⁇ 4 (A/cm 2 ) or more, and 1 ⁇ 10 0 (A/cm 2 ) in the current density-voltage characteristics shown in FIG. It may be the following.
  • the voltage (Vn_t-Va_t) that can be raised from the voltage Va_t at which avalanche breakdown occurs to the voltage Vn_t that reaches the negative resistance region is about several volts, and the collector current that can be raised is also small. If the temperature of the semiconductor substrate 10 rises, the voltage Vn_t that reaches the negative resistance region may also rise, but in the transistor section 70, the voltage and current that can rise from avalanche breakdown to reach the negative resistance region are small. , the temperature of the semiconductor substrate 10 cannot be raised sufficiently and easily reaches the negative resistance region.
  • the voltage Vn_d at which the diode section 80 reaches the negative resistance region is the voltage at which the cathode voltage changes from increasing to decreasing when the cathode current of the diode section 80 increases.
  • the voltage Vn_d may be the maximum value of the cathode voltage in the characteristics shown in FIG.
  • the voltage Vn_t at which the transistor section 70 reaches the negative resistance region is the voltage at which the collector voltage (collector-emitter voltage) changes from increasing to decreasing when the collector current of the transistor section 70 increases.
  • the voltage Vn_t may be the maximum value of the collector voltage in the characteristics shown in FIG.
  • the avalanche breakdown voltage Va_t of the transistor section 70 is smaller than the avalanche breakdown voltage Va_d of the diode section 80. Therefore, the transistor section 70 undergoes avalanche breakdown first. When the transistor section 70 undergoes avalanche breakdown, it instantly reaches the negative resistance region, and the semiconductor device 100 is destroyed.
  • FIG. 5 is an example of current density-voltage characteristics of the transistor section 70 and diode section 80 according to the example.
  • the avalanche breakdown voltage Va_d in the diode section 80 of this example is smaller than the avalanche breakdown voltage Va_t in the transistor section 70. This allows avalanche breakdown to occur in the diode section 80 before the transistor section 70. Therefore, when avalanche breakdown occurs, it can be suppressed from instantaneously reaching the negative resistance region.
  • the avalanche breakdown voltage Va_d in the diode section 80 is 0.7 times or more and less than 1 time the avalanche breakdown voltage Va_t in the transistor section 70.
  • the avalanche breakdown voltage Va_d may be 0.98 times or less, 0.96 times or less, or 0.9 times or less of the avalanche breakdown voltage Va_t. If the avalanche breakdown voltage Va_d of the diode section 80 is made too small, the avalanche breakdown voltage of the semiconductor device 100 will become low.
  • the avalanche breakdown voltage Va_d may be 0.75 times or more, 0.8 times or more, or 0.85 times or more of the avalanche breakdown voltage Va_t.
  • the avalanche breakdown voltage Va_d of the diode section 80 is larger than the specification value of the avalanche breakdown voltage V0 of the semiconductor device 100.
  • the avalanche breakdown voltage Va_d may be larger than the average value of the specification value V 0 of the avalanche breakdown voltage and the avalanche breakdown voltage Va_t in the transistor section 70 .
  • the avalanche breakdown voltage Va_d of the diode section 80 can be adjusted by adjusting the interval in the X-axis direction of the trench sections of the diode section 80 (or the width of the mesa section 61 in the X-axis direction), the depth of the trench section of the diode section 80, and the like.
  • the voltage Vn_d at which the diode section 80 reaches the negative resistance region may be greater than or equal to the avalanche breakdown voltage Va_t of the transistor section 70 and may be greater than the avalanche breakdown voltage Va_t of the transistor section 70.
  • the voltage Vn_d at which the diode section 80 reaches the negative resistance region may be higher than the voltage Vn_t at which the transistor section 70 reaches the negative resistance region. This can prevent the transistor section 70 from reaching the negative resistance region first.
  • the voltage Vn_d at which the diode section 80 reaches the negative resistance region may be smaller than or the same as the voltage Vn_t at which the transistor section 70 reaches the negative resistance region.
  • the current density-voltage characteristics of the transistor section 70 and the diode section 80 may be calculated using general device simulation. Device simulation may be performed by solving Poisson's equation and the current continuity equation regarding electrons and holes under predetermined boundary conditions and initial conditions.
  • the current density-voltage characteristic of the transistor section 70 may be calculated by calculating the current density-voltage characteristic for a structure simulating only the transistor section 70. Alternatively, calculations may be performed in a structure simulating both the transistor section 70 and the diode section 80, and the current density-voltage characteristics regarding only the transistor section 70 may be extracted.
  • the current density-voltage characteristics of the diode section 80 may be calculated by calculating the current density-voltage characteristics for a structure simulating only the diode section 80. Alternatively, calculations may be performed using a structure that imitates both the transistor section 70 and the diode section 80, and the current density-voltage characteristics regarding only the diode section 80 may be extracted.
  • FIG. 6 is a diagram showing an example of the ee cross section according to the embodiment.
  • the spacing between the trench portions in the diode portion 80 is different from that in the reference example of FIG.
  • an intermediate area 200 may be provided in place of the connection area 190 in the reference example shown in FIG.
  • the intermediate region 200 and the connection region 190 have different trench portion intervals in the X-axis direction.
  • Other structures are similar to the examples described in FIGS. 1 to 3.
  • Intermediate region 200 is arranged between diode section 80 and transistor section 70 in the X-axis direction.
  • a plurality of trench portions are provided in the intermediate region 200.
  • a region including the mesa portion 60 provided with the emitter region 12 and a trench portion adjacent to the mesa portion 60 is defined as a transistor portion 70.
  • a collector region 22 is provided on the lower surface of the transistor section 70 .
  • a region including a mesa portion 61 in which the emitter region 12 is not provided and a trench portion adjacent to the mesa portion 61 is defined as a diode portion 80.
  • a cathode region 82 is provided on the lower surface of the diode section 80.
  • the spacing in the X-axis direction between the plurality of trench portions in the diode portion 80 is a constant value Xd.
  • the lengths of the plurality of trench portions in the diode portion 80 in the Z-axis direction are also constant (lower end depth position Zt).
  • the avalanche breakdown voltage Va_d in the diode section 80 is smaller than the avalanche breakdown voltage Va_t in the transistor section 70.
  • a region including a mesa portion 62 in which the emitter region 12 is not provided and a trench portion adjacent to the mesa portion 62 is defined as an intermediate region 200.
  • At least one of the collector region 22 and the cathode region 82 is provided on the lower surface 23 of the intermediate region 200 .
  • One of the collector region 22 and the cathode region 82 may be provided on the lower surface 23 of the intermediate region 200 from a position in contact with the transistor section 70 to a position in contact with the diode section 80 .
  • the collector region 22 may be provided in a region in contact with the transistor section 70, and the cathode region 82 may be provided in a region in contact with the diode section 80.
  • the boundary between the collector region 22 and the cathode region 82 is located in the intermediate region 200.
  • the boundary between the intermediate region 200 and the transistor section 70 is the center in the X-axis direction of the trench section closest to the diode section 80 (dummy trench section 30-1 in this example) among the trench sections in contact with the emitter region 12.
  • the trench portion of the intermediate region 200 has a different structure from the trench portion of the diode portion 80.
  • the trench portion of the intermediate region 200 is different from the trench portion of the diode portion 80 in at least one of the distance between adjacent trench portions and the depth of the trench portion.
  • the trench portion of the intermediate region 200 and the trench portion of the diode portion 80 may differ in the presence or absence of the first lower end region 202 (see FIG. 11) or the second lower end region 204 (see FIG. 13).
  • the boundary between the intermediate region 200 and the diode section 80 is the center in the X-axis direction of the boundary trench section (in this example, the dummy trench section 30-4) where the structure changes.
  • the avalanche breakdown voltage of the intermediate region 200 may be greater than the avalanche breakdown voltage of the diode section 80 and smaller than the avalanche breakdown voltage of the transistor section 70. In each example herein, the intermediate region 200 may not be provided. In this case, the transistor section 70 and the diode section 80 are provided in contact with each other.
  • Each of the diode section 80, the transistor section 70, and the intermediate region 200 has a plurality of trench sections arranged at intervals along the arrangement direction (X-axis direction) on the upper surface 21 of the semiconductor substrate 10.
  • At least some of the trench portions in the transistor section 70 are arranged at a first interval Xt in the X-axis direction.
  • the first interval Xt may be the largest interval among the intervals between the trench parts in the transistor section 70.
  • all the trench sections in the transistor section 70 are arranged at the first interval Xt.
  • At least some of the trench portions in the diode section 80 are arranged at a second interval Xd that is larger than the first interval Xt in the X-axis direction. In this example, all the trench sections of the diode section 80 are arranged at the second interval Xd.
  • the second interval Xd of the trench portions in the diode portion 80 is set so that the avalanche breakdown voltage Va_d in the diode portion 80 is less than 1 times and 70% or more of the avalanche breakdown voltage Va_t in the transistor portion 70.
  • the second interval Xd between the trench sections in the diode section 80 may be larger than the first interval Xt between the trench sections in the transistor section 70, and may be at least 1.2 times the first interval Xt, and may be at least twice the first interval Xt. It may be 3 times or more, and it may be 5 times or more.
  • the first spacing Xt is 2.5 ⁇ m or less
  • the second spacing Xd is 5 ⁇ m or more.
  • the second spacing Xd may be 50 ⁇ m or less, or 30 ⁇ m or less.
  • the intermediate region 200 has a plurality of trench portions.
  • the intermediate region 200 of this example has a plurality of dummy trench sections 30.
  • the dummy trench section 30-1 is arranged at the boundary between the transistor section 70 and the intermediate region 200.
  • the center of the dummy trench portion 30-1 in the X-axis direction is the boundary position between the transistor portion 70 and the intermediate region 200.
  • the dummy trench section 30-4 is arranged at the boundary between the diode section 80 and the intermediate region 200.
  • the center of the dummy trench section 30-4 in the X-axis direction is the boundary position between the diode section 80 and the intermediate region 200.
  • One or more dummy trench sections 30 may be arranged between dummy trench section 30-1 and dummy trench section 30-4, and other dummy trench sections 30 may not be arranged.
  • dummy trench sections 30-2 and 30-3 are arranged between dummy trench sections 30-1 and 30-4.
  • the intermediate region 200 has one or more mesa portions 62.
  • the mesa portion 62-1 is placed adjacent to the transistor portion 70, and the mesa portion 62-3 is placed adjacent to the diode portion 80.
  • One or more mesa parts 62 may be arranged between mesa part 62-1 and mesa part 62-3, and other mesa parts 62 may not be arranged.
  • mesa portion 62-2 is arranged between mesa portion 62-1 and mesa portion 62-3.
  • the trench interval monotonically increases as it approaches the diode section 80. That is, in the intermediate region 200 of this example, the mesa width increases monotonically from the mesa portion 62-1 to the mesa portion 62-3 as it approaches the diode portion 80.
  • the trench spacing is the distance between the center positions of adjacent trench portions in the X-axis direction.
  • the mesa width is the width of a region sandwiched between two adjacent trench portions in the X-axis direction.
  • Monotonically increasing trench spacing means that the trench spacing is increasing in at least one location and decreasing in the direction from dummy trench portion 30-1 to dummy trench portion 30-4. It means that there is no. That is, in the direction from dummy trench section 30-1 to dummy trench section 30-4, a region may be included where the trench spacing does not change.
  • the trench interval between the dummy trench portion 30-k and the dummy trench portion 30-k+1 is set to Xk.
  • k is an integer of 1 or more.
  • the dummy trench section 30-k+1 is arranged adjacent to the dummy trench section 30-k on the diode section 80 side.
  • the trench spacing Xk may monotonically increase as k increases.
  • the avalanche withstand voltage in one mesa portion 62 by monotonically increasing the trench interval Xk, the avalanche withstand voltage can be gradually changed in the X-axis direction. This can prevent electric field strength from concentrating in the intermediate region 200.
  • the intermediate region 200 has a transistor side region 201 in contact with the transistor section 70.
  • one or more trench portions are arranged at a first interval Xt that is the same as the trench interval in the transistor portion 70.
  • the trench spacing X1 is equal to the first spacing Xt.
  • the region from dummy trench portion 30-1 to dummy trench portion 30-2 is transistor side region 201.
  • a boundary position in the X-axis direction between the cathode region 82 and the collector region 22 in the intermediate region 200 may be located in the transistor side region 201 .
  • the trench spacing X3 at the location closest to the diode section 80 is larger than the trench spacing X1.
  • the trench spacing X3 is smaller than the second spacing Xd in the diode section 80.
  • the trench spacing may be increased at one location, or the trench spacing may be increased at multiple locations.
  • Xt X1 ⁇ X2 ⁇ X3 ⁇ Xd. That is, the trench spacing in the X-axis direction of the plurality of trench portions in the intermediate region 200 of this example is larger as the trench portion is closer to the diode portion 80.
  • the diode section 80 extends up to the dummy trench section 30-3.
  • FIG. 7 is a diagram showing another example of the ee cross section according to the embodiment.
  • the trench interval X1 in the transistor side region 201 is different from the example in FIG. 6 .
  • Other structures may be similar to the example of FIG.
  • the trench spacing X1 in the transistor side region 201 of this example is smaller than the first spacing Xt in the transistor section 70.
  • the transistor side region 201 has two trench portions, but may have more trench portions. Also in this case, each trench spacing Xk in the transistor side region 201 is smaller than the first spacing Xt.
  • the trench spacing Xk in the transistor side region 201 may be constant, or may monotonically increase toward the diode portion 80.
  • the trench interval X2 of the trench portions adjacent to the transistor side region 201 is larger than the trench interval X1 of the transistor side region 201.
  • the trench spacing X2 may be the same as the first spacing Xt, may be smaller than the first spacing Xt, or may be larger than the first spacing Xt.
  • the boundary position between the collector region 22 and the cathode region 82 in the X-axis direction may be located in a region from below the dummy trench section 30-1 to below the dummy trench section 30-2.
  • FIG. 8 is a diagram showing another example of the ee cross section according to the embodiment.
  • the configuration of the transistor side region 201 is different from the example in FIG. 6.
  • Other structures may be similar to the example of FIG.
  • the transistor side region 201 in this example includes three or more trench portions.
  • the transistor side region 201 extends from dummy trench portion 30-1 to dummy trench portion 30-4.
  • the trench intervals in this example, X1, X2, and X3
  • the boundary between the cathode region 82 and the collector region 22 is located below the dummy trench portion 30-4 closest to the diode portion 80 among the trench portions of the transistor side region 201.
  • FIG. 9 is a diagram showing another example of the ee cross section according to the embodiment.
  • the length of the trench portion of the diode portion 80 in the Z-axis direction is different from the examples described in FIGS. 3 to 8.
  • this example has an intermediate area 200 instead of the connection area 190 in the reference example shown in FIG.
  • the intermediate region 200 of this example is different from the examples described in FIGS. 6 to 8 in the length of the trench portion in the Z-axis direction.
  • Other structures in intermediate region 200 (for example, trench spacing Xk) may be similar to any of the examples described in FIGS. 6 to 8, and may be the same as connection region 190 described in FIG. 3.
  • At least some of the trench portions in the transistor section 70 are arranged with a first length Ztt in the Z-axis direction.
  • the first length Ztt may be the maximum length among the lengths of the trench portion in the transistor portion 70.
  • all trench sections in the transistor section 70 have the first length Ztt.
  • At least some of the trench portions in the diode portion 80 have a second length Ztd that is larger than the first length Ztt in the Z-axis direction. In this example, all trench sections of the diode section 80 have the second length Ztd.
  • the second length Ztd of the trench section in the diode section 80 is set so that the avalanche breakdown voltage Va_d in the diode section 80 is less than 1 times and 70% or more of the avalanche breakdown voltage Va_t in the transistor section 70. As explained in FIGS.
  • the avalanche breakdown voltage Va_d in the diode section 80 becomes the avalanche breakdown voltage Va_t in the transistor section 70.
  • the length of each trench portion and the trench spacing are set so that it is less than 1 times and 70% or more.
  • the second length Ztd may be 1.5 times or more, or twice or more, the first length Ztt. However, if the second length Ztd is made too large, the withstand voltage of the diode section 80 becomes too small, so the second length Ztd may be 5 times or less than the first length Ztt, and may be 4 times or less. There may be.
  • the intermediate region 200 has a plurality of trench portions.
  • the intermediate region 200 of this example has a plurality of dummy trench sections 30.
  • the dummy trench section 30-1 is arranged at the boundary between the transistor section 70 and the intermediate region 200
  • the dummy trench section 30-5 is arranged at the boundary between the diode section 80 and the intermediate region 200.
  • One or more dummy trench sections 30 may be arranged between dummy trench section 30-1 and dummy trench section 30-5, and other dummy trench sections 30 may not be arranged.
  • dummy trench sections 30-2, 30-3, and 30-4 are arranged between dummy trench sections 30-1 and 30-5.
  • the length of the trench portion in the Z-axis direction increases monotonically as it approaches the diode portion 80.
  • the term “the length of the trench portion increases monotonically” means that the length of the trench portion increases at least at one location in the direction from the dummy trench portion 30-1 to the dummy trench portion 30-5, and It means that there is no place where the length of is decreasing. That is, in the direction from the dummy trench section 30-1 to the dummy trench section 30-5, a region may be included in which the length of the trench section does not change.
  • the length of the dummy trench portion 30-k in the Z-axis direction is Ztk.
  • k is an integer of 1 or more.
  • the dummy trench section 30-k+1 is arranged adjacent to the dummy trench section 30-k on the diode section 80 side.
  • the length Ztk may increase monotonically as k increases. By monotonically increasing the trench length Ztk, the avalanche breakdown voltage can be gradually changed in the X-axis direction.
  • the intermediate region 200 has a transistor side region 201 in contact with the transistor section 70.
  • one or more trench portions are arranged with the same first length Ztt as the transistor portion 70.
  • trench lengths Zt1 and Zt2 are equal to the first length Ztt.
  • the region from dummy trench portion 30-1 to dummy trench portion 30-2 is transistor side region 201.
  • a boundary position in the X-axis direction between the cathode region 82 and the collector region 22 in the intermediate region 200 may be located in the transistor side region 201 .
  • trench length Zt4 at the location closest to the diode portion 80 is greater than the trench length Zt1.
  • Trench length Zt4 is smaller than second length Ztd in diode section 80.
  • the trench length may be increased at one location, or may be increased at multiple locations.
  • FIG. 10 is a diagram showing another example of the ee cross section according to the embodiment.
  • the trench length of any trench portion in the transistor side region 201 is different from the example in FIG. 9 .
  • Other structures may be similar to the example of FIG.
  • the trench length (Zt2 in FIG. 10) of any trench portion of the transistor side region 201 in this example is smaller than the first length Ztt in the transistor portion 70.
  • the trench length Zt2 of one dummy trench portion 30-2 in the transistor side region 201 is smaller than the first length Ztt.
  • the transistor side region 201 may include a plurality of dummy trench portions 30 having a trench length smaller than the first length Ztt. The trench lengths of these dummy trench sections 30 may be constant or may monotonically increase toward the diode section 80.
  • the trench length Zt3 of the trench portion adjacent to the transistor side region 201 is larger than the trench length Zt2.
  • the trench length Zt3 may be the same as the first spacing Xt or may be greater than the first spacing Xt.
  • the boundary position between the collector region 22 and the cathode region 82 in the X-axis direction may be located in a region from below the dummy trench section 30-1 to below the dummy trench section 30-2.
  • FIG. 11 is a diagram showing another example of the ee cross section according to the embodiment. This example differs from the examples described in FIGS. 3 to 10 in that a first lower end region 202 is provided in the transistor section 70 and the intermediate region 200. Similar to the example described in FIG. 3, the trench spacing Xt and trench length may be constant in the transistor section 70, the diode section 80, and the intermediate region 200. The transistor section 70, the diode section 80, and the intermediate region 200 may have trench spacings similar to the examples described in FIGS. 6 to 8, and trench lengths similar to the examples described in FIGS. 9 to 10. You may.
  • the transistor section 70 has a P-type first lower end region 202 provided in contact with the lower end 212 of at least one trench section.
  • the first lower end region 202 is provided so as to cover from the lower end 212 of the trench portion to a part of the side wall 213 of the trench portion.
  • the first lower end region 202 of the transistor section 70 in this example is in contact with the storage region 16.
  • the doping concentration of the first lower end region 202 may be lower or higher than the doping concentration of the base region 14.
  • the doping concentration of the first lower end region 202 may be lower than that of the collector region 22 and may be lower than that of the contact region 15.
  • the first lower end region 202 may be provided in all trench portions of the transistor portion 70.
  • the first lower end regions 202 provided at the lower end 212 of each trench portion may be separated from each other in the X-axis direction, as shown in FIG. 11, or may be connected to each other in the X-axis direction.
  • the first lower end region 202 is not provided at the lower end 212 of at least one trench section of the diode section 80.
  • the lower end 212 of the trench portion is not in contact with the P-type region.
  • the lower end 212 of the trench portion is in contact with the drift region 18 .
  • the first lower end region 202 may not be provided at the lower end 212 of all the trench portions of the diode portion 80.
  • the avalanche breakdown voltage of the transistor section 70 can be increased and the avalanche breakdown voltage of the diode section 80 can be relatively lowered.
  • the avalanche breakdown voltage of the diode section 80 can be adjusted to less than 1 times and 70% or more of the avalanche breakdown voltage of the transistor section 70.
  • the avalanche breakdown voltage of the transistor section 70 can be adjusted by adjusting the doping concentration of the first lower end region 202 and the like. Furthermore, among the adjustments of the trench spacing Xk as explained in FIGS. 6 to 8, the trench length adjustment as explained in FIGS.
  • the avalanche breakdown voltage of the diode section 80 may be adjusted to be less than 1 time and 70% or more of the avalanche breakdown voltage of the transistor section 70 by combining two or more of them.
  • a first lower end region 202 is provided in the trench portion of the intermediate region 200, except for the dummy trench portion 30-3 located at the boundary with the diode portion 80.
  • a first lower end region 202 is provided in contact with lower ends 212 of dummy trench portions 30-1 and 30-2.
  • the doping concentration of each first lower end region 202 of the intermediate region 200 is the same as the doping concentration of the first lower end region 202 of the transistor section 70 .
  • the doping concentration of the first lower end region 202 of the intermediate region 200 may monotonically decrease as it approaches the diode portion 80.
  • the boundary position between the collector region 22 and the cathode region 82 in the X-axis direction may be located in a region from below the dummy trench section 30-1 to below the dummy trench section 30-2.
  • FIG. 12 is a diagram showing another example of the ee cross section according to the embodiment.
  • the number of trench portions in the intermediate region 200 is different from the example in FIG. 11.
  • Other structures are similar to the example in FIG. 11.
  • the intermediate region 200 of this example has three or more trench portions in which the first lower end region 202 is provided.
  • the first lower end region 202 is provided in four dummy trench sections 30 from dummy trench section 30-1 to dummy trench section 30-4.
  • FIG. 13 is a diagram showing another example of the ee cross section according to the embodiment. This example differs from the examples described in FIGS. 3 to 12 in that a second lower end region 204 is provided in the diode section 80. Similar to the example described in FIG. 3, the trench spacing Xt and trench length may be constant in the transistor section 70, the diode section 80, and the intermediate region 200. The transistor section 70, the diode section 80, and the intermediate region 200 may have trench spacings similar to the examples described in FIGS. 6 to 8, and trench lengths similar to the examples described in FIGS. 9 to 10. You may. Furthermore, similar to the example described in FIGS. 11 and 12, a first lower end region 202 may be provided in the transistor section 70 and the intermediate region 200.
  • the diode section 80 has an N-type second lower end region 204 provided in contact with the lower end 212 of at least one trench section.
  • the second lower end region 204 is provided so as to cover from the lower end 212 of the trench portion to a part of the side wall 213 of the trench portion.
  • the lower end of the second lower end region 204 is arranged closer to the lower surface 23 than the lower end of the storage region 16 .
  • the doping concentration of the second lower end region 204 is higher than the doping concentration of the drift region 18 .
  • the doping concentration of the second lower end region 204 may be twice or more than the doping concentration of the drift region 18, may be five times or more, and may be ten times or more.
  • the doping concentration of the second lower end region 204 may be lower than the doping concentration of the accumulation region 16 .
  • the doping concentration of the second lower end region 204 may be lower than the doping concentration of the cathode region 82 .
  • the second lower end region 204 may be provided in half or more of the trench portions, the second lower end region 204 may be provided in 90% or more of the trench portions, and the second lower end region 204 may be provided in all the trench portions.
  • Two lower end regions 204 may be provided.
  • the second lower end regions 204 provided at the lower end 212 of each trench portion may be separated from each other in the X-axis direction, as shown in FIG. 13, or may be connected to each other in the X-axis direction.
  • the second lower end region 204 is not provided at the lower end 212 of at least one trench portion of the transistor section 70.
  • the lower end 212 of the trench portion is not in contact with an N-type region having a higher doping concentration than the drift region 18.
  • the lower end 212 of the trench portion is in contact with the drift region 18 .
  • the second lower end region 204 may not be provided at the lower end 212 of all the trench portions of the transistor section 70.
  • the second lower end region 204 is not provided at the lower end 212 of all the trench portions of the intermediate region 200 .
  • each second lower end region 204 may be uniform. In other examples, the doping concentrations of the plurality of second bottom regions 204 may be different from each other. As an example, the doping concentration of the second lower end region 204 at the center of the diode section 80 in the X-axis direction may be higher than the doping concentration of the second lower end region 204 at the end of the diode section 80 in the X-axis direction. This makes it easier to cause avalanche breakdown near the center of the diode section 80 away from the transistor section 70.
  • the boundary between the collector region 22 and the cathode region 82 is located closer to the transistor section 70 than the second lower end region 204 . Thereby, the P+ type collector region 22 and the N type second lower end region 204 can be arranged apart from each other, and movement of carriers between the collector region 22 and the second lower end region 204 can be suppressed.
  • the avalanche breakdown voltage of the diode section 80 can be adjusted to less than 1 times and 70% or more of the avalanche breakdown voltage of the transistor section 70.
  • the avalanche breakdown voltage of the transistor section 70 can be adjusted by adjusting the doping concentration of the second lower end region 204 and the like.
  • the trench spacing Xk is adjusted as explained in FIGS. 6 to 8, the trench length is adjusted as explained in FIGS. 9 to 10, the adjustment is made using the first lower end region 202 as explained in FIGS.
  • the avalanche breakdown voltage of the diode section 80 is adjusted to less than 1 times and 70% or more of the avalanche breakdown voltage of the transistor section 70 by combining two or more of the adjustments using the second lower end region 204 described in FIG. It's okay.
  • FIG. 14 is a diagram showing another example of the ee cross section according to the embodiment. This example differs from the examples described in FIGS. 3 to 13 in that a lifetime adjustment section 208 is provided in the diode section 80. Similar to the example described in FIG. 3, the trench spacing Xt and trench length may be constant in the transistor section 70, the diode section 80, and the intermediate region 200. The transistor section 70, the diode section 80, and the intermediate region 200 may have trench spacings similar to the examples described in FIGS. 6 to 8, and trench lengths similar to the examples described in FIGS. 9 to 10. You may. Similar to the example described in FIGS. 11 and 12, a first lower end region 202 may be provided in the transistor section 70 and the intermediate region 200. Similarly to the example described in FIG. 13, the diode section 80 may be provided with a second lower end region 204.
  • the lifetime adjustment section 208 is arranged below the lower end of the trench section on the upper surface 21 side of the semiconductor substrate 10.
  • the lifetime adjustment section 208 is a region where the carrier lifetime exhibits a minimum value in the depth direction of the semiconductor substrate 10. In a region where many lattice defects 206 remain, carriers are captured by the lattice defects 206, so that the lifetime of the carriers becomes short.
  • characteristics such as turn-off time of the semiconductor device 100 can be adjusted.
  • a charged particle beam such as a helium ion beam
  • the lifetime adjustment section 208 of this example is provided throughout the diode section 80 in the X-axis direction.
  • the lifetime adjustment section 208 may be provided extending over the entire intermediate region 200 in the X-axis direction.
  • the lifetime adjustment section 208 may be provided extending also to a part of the transistor section 70 in the X-axis direction.
  • the region where the lifetime adjustment section 208 is provided may have a carrier lifetime of less than 10% and 0.001% or more compared to the region where the lifetime adjustment section 208 is not provided.
  • the carrier lifetime in the lifetime adjustment section 208 is less than 10% and 0.001% or more.
  • the carrier lifetime in the lifetime adjustment section 208 may be 1% or less of the reference carrier lifetime, or may be 0.1% or less.
  • the carrier lifetime in the lifetime adjustment unit 208 may be 0.01% or more of the reference carrier lifetime.
  • the carrier lifetime in the drift region 18 is almost uniform. “Substantially uniform” refers to, for example, that the carrier lifetimes in the entire drift region 18 are distributed within a range of 100% or less and 10% or more with respect to the maximum value of the carrier lifetime in the drift region 18.
  • the carrier lifetime in the entire drift region 18 is distributed within a range of 100% or less and 50% or more with respect to the maximum value of the carrier lifetime in the drift region 18. Good too.
  • FIG. 15 is a diagram showing another example of the ee cross section according to the embodiment.
  • a lifetime adjustment section 208 is provided in the configuration shown in FIG.
  • a lifetime adjustment section 208 may be provided in the configuration shown in FIG.
  • FIG. 16 is a diagram showing another example of the ee cross section according to the embodiment.
  • a lifetime adjustment section 208 is provided in the configuration shown in FIG.
  • a lifetime adjustment section 208 may be provided in the configuration shown in FIG.
  • FIG. 17 is a diagram showing another example of the ee cross section according to the embodiment.
  • a lifetime adjustment section 208 is provided in the configuration shown in FIG.
  • FIG. 18 is a diagram showing the relationship between the trench spacing in the transistor section 70 and the diode section 80 and the avalanche breakdown voltage in the transistor section 70 and the diode section 80.
  • the measured values of each sample are shown as square plots and circle plots.
  • the avalanche breakdown voltage can be adjusted by adjusting the trench spacing.
  • the breakdown voltage of the transistor section 70 is 1425V.
  • the withstand voltage of the diode section 80 can be made smaller than 1425V.
  • the trench spacing in the diode section 80 may be 5.5 times or more, 6 times or more, or 10 times or more as large as the trench spacing in the transistor section 70.
  • FIG. 19 is a diagram showing the relationship between the trench length in the transistor section 70 and the diode section 80 and the avalanche breakdown voltage in the transistor section 70 and the diode section 80.
  • the measured values of each sample are shown as square plots and circle plots.
  • the avalanche breakdown voltage can be adjusted by adjusting the trench length. In this example, when the trench length in the transistor section 70 is 5 ⁇ m, the breakdown voltage of the transistor section 70 is 1425V.
  • the withstand voltage of the diode section 80 can be made smaller than 1425V.
  • the trench length of the diode section 80 may be 2.4 times or more, 3 times or more, or 5 times or more as long as the trench length of the transistor section 70.
  • FIG. 20 is a diagram showing the relationship between the trench spacing in the transistor section 70 and the diode section 80 and the avalanche breakdown voltage in the transistor section 70 and the diode section 80.
  • the diode section 80 of this example is the same as the diode section 80 of the example of FIG.
  • the transistor section 70 in the example of FIG. 18 does not have the first lower end region 202, but the transistor section 70 in this example does have the first lower end region 202.
  • the transistor section 70 of this example is the same as the transistor section 70 of the example of FIG. 18 except that the first lower end region 202 is provided.
  • FIGS. 18 and 20 by providing the first lower end region 202, the avalanche breakdown voltage of the transistor section 70 is increased. That is, by providing the first lower end region 202, the avalanche breakdown voltage can be adjusted.
  • FIG. 21 is a diagram showing the relationship between the dose amount (or doping concentration) in the second lower end region 204 of the diode section 80 and the avalanche breakdown voltage of the diode section 80.
  • the avalanche breakdown voltage in the case where the second lower end region 204 is not provided is shown by a square plot.
  • the dose amount of the second lower end region 204 is increased, the avalanche breakdown voltage is decreased. That is, by adjusting the dose of the second lower end region 204, the avalanche breakdown voltage can be adjusted.
  • FIG. 22 is a diagram illustrating the non-destructive maximum energy density of the semiconductor device 100.
  • the non-destructive maximum energy density is the energy that is applied just before the semiconductor device 100 is destroyed when the energy applied to the semiconductor device 100 is gradually increased in an unclamped dielectric switching test (UIS test). Refers to density.
  • the semiconductor device 100 When the semiconductor device 100 is transitioned from the on state to the off state at time t1, the current density of the main current flowing through the semiconductor device 100 gradually decreases, and the collector/emitter voltage of the semiconductor device 100 increases. As shown in the lower graph of FIG. 23, energy obtained by time-integrating the product (V ⁇ J) of the main current density and the collector/emitter voltage is applied to the semiconductor device 100.
  • the energy slightly smaller than the energy applied from time t1 to time t2 in the turn-off operation is the non-destructive maximum energy density.
  • the applied energy in the turn-off operation may be the non-destructive maximum energy density, or the applied energy in the turn-off operation may be subtracted by a predetermined margin to be the non-destructive maximum energy density, or the applied energy in the turn-off operation immediately before the turn-off operation may be the maximum non-destructive energy density.
  • the energy may be the maximum non-destructive energy density.
  • FIG. 23 shows the relationship between the avalanche breakdown voltage Va_d and the non-destructive maximum energy density in the diode section 80.
  • the horizontal axis in FIG. 23 indicates the avalanche breakdown voltage Va_d (ie, Va_d/Va_t) normalized by the avalanche breakdown voltage Va_t in the transistor section 70.
  • the semiconductor device 100 may have an avalanche breakdown voltage ratio of the diode section 80 and the transistor section 70 such that the maximum non-destructive energy density is greater than the reference value S0 .
  • the avalanche breakdown voltage Va_d of the diode section 80 is 70% or more and less than 100% of the avalanche breakdown voltage Va_t of the transistor section 70.
  • the semiconductor device 100 may have an avalanche breakdown voltage ratio of the diode section 80 and the transistor section 70 such that the maximum non-destructive energy density is 80% or more of the maximum value S max .
  • the semiconductor device 100 may have an avalanche breakdown voltage ratio of the diode section 80 and the transistor section 70 such that the maximum non-destructive energy density is 90% or more of the maximum value S max .
  • the semiconductor device 100 may have an avalanche breakdown voltage ratio of the diode section 80 and the transistor section 70 such that the non-destructive maximum energy density is equal to or greater than the intermediate value between the reference value S 0 and the maximum value S max .
  • the avalanche breakdown voltage Va_d of the diode section 80 may be 75% or more of the avalanche breakdown voltage Va_t of the transistor section 70, and may be 80% or more. In the semiconductor device 100, the avalanche breakdown voltage Va_d of the diode section 80 may be less than 100%, 95% or less, or 90% or less of the avalanche breakdown voltage Va_t of the transistor section 70.
  • FIG. 24 is a diagram illustrating an example of a method for manufacturing the semiconductor device 100.
  • the reference value S0 of the non-destructive maximum energy density explained in FIGS. 22 and 23 is obtained using one or more semiconductor devices.
  • a reference value S0 is obtained by an unclamped dielectric switching test.
  • One or more semiconductor devices used to obtain the reference value S 0 will be referred to as a first semiconductor device.
  • a setting step S304 as explained with reference to FIG. 23, the avalanche breakdown voltage ratios of the diode section 80 and the transistor section 70 are set so that the maximum non-destructive energy density is larger than the reference value S0 .
  • the structures of the diode section 80 and the transistor section 70 are designed so as to satisfy the avalanche breakdown voltage ratio set at S304.
  • the interval between the trench parts, the depth of the trench part, the arrangement of the first lower end region 202, the arrangement of the second lower end region 204, the arrangement of the lifetime adjustment section 208, etc. By adjusting , the avalanche breakdown voltage ratio of the diode section 80 and the transistor section 70 is adjusted.
  • the semiconductor device in which the avalanche breakdown voltage ratio of the diode section 80 and the transistor section 70 is adjusted is referred to as a second semiconductor device.
  • the semiconductor device 100 is manufactured based on the design in S306.
  • Semiconductor device 100 is a second semiconductor device. Thereby, the semiconductor device 100 can be manufactured.
  • the semiconductor device 100 has the avalanche breakdown voltage explained in FIG.

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Citations (4)

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JP2014175517A (ja) * 2013-03-11 2014-09-22 Mitsubishi Electric Corp 半導体装置およびその製造方法
JP2016139719A (ja) * 2015-01-28 2016-08-04 株式会社東芝 半導体装置
JP2016162855A (ja) * 2015-02-27 2016-09-05 株式会社日立製作所 半導体装置およびそれを用いた電力変換装置
JP2018078230A (ja) * 2016-11-11 2018-05-17 三菱電機株式会社 電力用半導体装置およびその製造方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2014175517A (ja) * 2013-03-11 2014-09-22 Mitsubishi Electric Corp 半導体装置およびその製造方法
JP2016139719A (ja) * 2015-01-28 2016-08-04 株式会社東芝 半導体装置
JP2016162855A (ja) * 2015-02-27 2016-09-05 株式会社日立製作所 半導体装置およびそれを用いた電力変換装置
JP2018078230A (ja) * 2016-11-11 2018-05-17 三菱電機株式会社 電力用半導体装置およびその製造方法

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