WO2023197507A1 - 视频数据处理方法、系统、装置及计算机可读存储介质 - Google Patents

视频数据处理方法、系统、装置及计算机可读存储介质 Download PDF

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WO2023197507A1
WO2023197507A1 PCT/CN2022/115726 CN2022115726W WO2023197507A1 WO 2023197507 A1 WO2023197507 A1 WO 2023197507A1 CN 2022115726 W CN2022115726 W CN 2022115726W WO 2023197507 A1 WO2023197507 A1 WO 2023197507A1
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video data
storage space
ram
compressed
ddr
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PCT/CN2022/115726
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English (en)
French (fr)
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张贞雷
李拓
满宏涛
刘同强
周玉龙
邹晓峰
王贤坤
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苏州浪潮智能科技有限公司
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Publication of WO2023197507A1 publication Critical patent/WO2023197507A1/zh

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/42—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation
    • H04N19/423—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation characterised by memory arrangements

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  • the present application relates to the field of video transmission, and in particular to a video data processing method, system, device and computer-readable storage medium.
  • the video graphics array module (VGA, Video Graphics Array) converts the initial video data transmitted from the host into RGB format video data.
  • the conversion module Perform color space conversion on RGB format video data to obtain YUV format video data.
  • the compression module follows the Block (block) ) sequence, read YUV format video data from the off-chip DDR, perform compression processing, and write the compressed video data to the off-chip DDR, and then the CPU (Central Processing Unit, central processing unit) runs
  • the network driver reads the command of compressed video data and sends it to the remote terminal for decoding and display through the network to realize remote monitoring and management.
  • a video data processing method, system, device and computer-readable storage medium are provided.
  • a video data processing method including: receiving a read signal, determining the storage space where the video data to be compressed corresponding to the read signal is located; in response to determining that the storage space is a DDR storage space, reading multiple Blocks from the DDR storage space video data, send the video data to be compressed in the video data to the compression module for compression processing, and store the video data in the video data of the multiple blocks except the video data to be compressed into the RAM storage space; in response to the determination
  • the storage space is a RAM storage space, and the video data to be compressed is read from the RAM storage space, and the video data to be compressed is sent to the compression module for compression processing.
  • a video data processing system including: a determination module, in response to receiving a read signal, to determine the storage space where the video data to be compressed corresponding to the read signal is located; a first processing module, in response to determining when the storage space is For the DDR storage space, read the video data of multiple blocks from the DDR storage space, send the video data to be compressed in the video data to the compression module for compression processing, and remove the video data of the multiple blocks to be compressed.
  • Video data other than the video data is stored in the RAM storage space; and a second processing module is configured to read the video data to be compressed from the RAM storage space in response to determining that the storage space is the RAM storage space, and send the video data to be compressed. Perform compression processing for the compression module.
  • a video data processing device includes a memory and one or more processors, the memory is used to store computer readable instructions; the one or more processors are used to implement the steps of the above video data processing method when executing the computer readable instructions.
  • a non-volatile computer-readable storage medium Computer-readable instructions are stored on the non-volatile computer-readable storage medium. When the computer-readable instructions are executed by a processor, the steps of the above video data processing method are implemented.
  • Figure 1 is a schematic process flow diagram of a video compression system in the prior art
  • Figure 2 is a schematic structural diagram of a video compression system according to one or more embodiments
  • Figure 3 is a flow chart of steps of a video data processing method according to one or more embodiments
  • Figure 4 is a schematic diagram of a Block according to one or more embodiments.
  • Figure 5 is a schematic structural diagram of a video data processing system according to one or more embodiments.
  • Figure 6 is a schematic structural diagram of a video data processing device according to one or more embodiments.
  • Figure 7 is a schematic structural diagram of a video data processing device according to one or more embodiments.
  • the core of this application is to provide a video data processing method, system, device and computer-readable storage medium, which can improve memory usage efficiency, reduce the occupation of DDR bus bandwidth by the video compression function, and achieve the purpose of improving system performance.
  • the video compression system can be implemented through a substrate management control chip.
  • the video compression system includes CPU 01, compression module 02, processing module 03 and on-chip RAM (Random Access Memory) 04.
  • the video data processing method provided in this embodiment can be implemented specifically through the processing module.
  • Figure 3 is a step flow chart of a video data processing method provided by this application.
  • the video data processing method includes:
  • S101 Receive the read signal and determine the storage space where the video data to be compressed corresponding to the read signal is located;
  • S102 In response to determining that the storage space is a DDR storage space, read the video data of multiple blocks from the DDR storage space, send the video data to be compressed in the video data to the compression module for compression processing, and save the video data of the multiple blocks.
  • the video data in the video data except the video data to be compressed is stored in the RAM storage space;
  • S103 In response to determining that the storage space is a RAM storage space, read the video data to be compressed from the RAM storage space, and send the video data to be compressed to the compression module for compression processing.
  • the video compression process whether it is H.264 format compression or JPEG (Joint Photographic Experts Group), is the product of the JPEG standard, which is formulated by the International Organization for Standardization (ISO) and is oriented to continuous tone still images.
  • ISO International Organization for Standardization
  • a compression standard format requires video data to be input in the form of blocks instead of rows. Therefore, the video data sent from the host needs to be stored in the storage space corresponding to the off-chip DDR first. Perform Block conversion.
  • the video data to be compressed in this step is actually a Block of video data.
  • the original video data is first converted into RGB format video data, and then through color space conversion, the RGB format video data is converted into YUV format video data, and finally , store the video data in YUV format into the storage space corresponding to DDR, that is, store the Y component in the video data into the memory space with Y_addr as the starting address in DDR, and store the U component in the video data into DDR.
  • U_addr is the memory space with the starting address.
  • Y_addr, U_addr, and V_addr are different according to different SoC systems (users can define them themselves).
  • the CPU assigns the above three addresses to the compression module so that the compression module outputs a read signal.
  • Block is explained under different compression configuration modes.
  • Each small box on the right side of Figure 4 represents an 8 ⁇ 8 pixel point on the left side.
  • Cb is the U component
  • Cr is the V component.
  • the compression configuration mode YUV420 the Y block represents the Y component of four 8 ⁇ 8 pixels
  • the Cb block represents the U component of one 8 ⁇ 8 block
  • the Cr block represents the V component of one 8 ⁇ 8 block.
  • the compression module must generate the address sequence for reading the 16 ⁇ 16 Y component, the address sequence for the 8 ⁇ 8 U component, and the address sequence for the 8 ⁇ 8 V component. .
  • the compression module For the current compression configuration mode of YUV422, the compression module should generate the address sequence for reading the 16 ⁇ 16 Y component, the address sequence for the 8 ⁇ 16 U component, and the address sequence for the 8 ⁇ 16 V component. For the current compression configuration mode of YUV444, the compression module must generate an address sequence for reading the 8 ⁇ 8 Y component, an address sequence for the 8 ⁇ 8 U component, and an address sequence for the 8 ⁇ 8 V component.
  • the reading strategy for reading YUV format video data from the DDR storage space each time is: reading the Y components of multiple Blocks, the U components of multiple Blocks, and the V components of multiple Blocks. , after passing the Y component of a block, the U component of a block and the V component of a block corresponding to the current read signal to the compression module in sequence, write the remaining Y component, U component and V component of the current read respectively. into the storage space corresponding to RAM. Based on this, after receiving the read signal output by the compression module, the processing module first determines the storage space where the video data to be compressed corresponding to the read signal is located.
  • the storage space where the video data to be compressed may be a DDR storage space or a RAM. of storage space.
  • the compression configuration mode is YUV420, taking the Y component as an example, assume that the Y components of three blocks are read from the DDR at a time, and the Y components of the block corresponding to the current read signal are passed to the compression module. The Y components of the two blocks under are stored in Y_RAM. Then the next time a read signal is received, the Y component of a block can be obtained directly from Y_RAM, that is, the data of three blocks is read by DDR at one time and two blocks are cached. Block will further increase the amount of data that can be read and written from DDR at one time, and increase the burst length of DDR, which also improves the efficiency of burst access and improves memory usage efficiency.
  • the video data processing method provided by this embodiment can read video data of multiple blocks at one time when performing a reading operation from the DDR storage space, which can increase the amount of data that can be read and written to the DDR at one time, and improves the suddenness of the data.
  • the efficiency of access is improved, thereby improving memory usage efficiency.
  • the RAM resources of the on-chip system are used to temporarily store the video data read from the DDR and not transmitted to the compression module, so that the next time a read signal is received, the video data to be compressed can be read directly from the RAM. , reducing the number of DDR reads, thereby greatly reducing the occupation of the DDR bus bandwidth by the video compression function, so that the DDR bus bandwidth can be used by other processes running on the CPU, thus achieving the purpose of improving system performance.
  • the video data processing method further includes: obtaining a compression configuration mode; determining the data to be stored in the YUV format video data based on the compression configuration mode; and storing the data to be stored in the DDR storage space.
  • the compression configuration mode is first obtained.
  • the data to be stored corresponding to each YUV component is also different.
  • the video data is first pre-selected and then stored in the DDR storage space. On the one hand, it reduces the storage of DDR. The space occupied, on the other hand, facilitates subsequent reading.
  • all Y components in all compression configuration modes are stored in the memory space with Y_addr as the starting address in DDR.
  • U component For the U component, all U components in YUV444 compression configuration mode are stored in the memory space with U_addr as the starting address in DDR; even rows (or even columns/odd rows/odd columns, the principle is 2 in YUV422 compression configuration mode
  • the U component (the Y component shares a U component) is stored in the memory space with U_addr as the starting address in DDR; even rows and even columns (or odd rows, odd columns, or even rows and odd columns) in YUV420 compression configuration mode , or odd-numbered rows, even-numbered columns, the principle is that four Y components share one U component) and the U component is stored in the memory space with U_addr as the starting address in DDR.
  • V component For the V component, all V components in the YUV444 compression configuration mode are stored in the memory space with V_addr as the starting address in the DDR; the even rows (even columns/odd rows/odd columns) in the YUV422 compression configuration mode are 2 Y components in principle Sharing a V component) the V component is stored in the memory space with V_addr as the starting address in DDR; even rows and even columns (or odd rows and odd columns, even rows and odd columns, odd rows and even columns in YUV420 compression configuration mode , the principle is that four Y components share one V component) and the V component is stored in the memory space with V_addr as the starting address in DDR.
  • the remaining data of U in the 0/16/32/48... rows of 0/16/32/48... rows is written into the 0th row of U_RAM, and the 2/18/34/50... rows of 2/
  • the U remaining data in columns 18/34/50 is written into row 1 of U_RAM, and the remaining U data in columns 4/20/36/52 at rows 4/20/36/52... is written into row 2 of U_RAM,...
  • the remaining data of U in columns 14/30/46/62... of rows 14/30/46/62... is written into row 7 of U_RAM;
  • the remaining data of V in row 0/16/32/48... of row 0/16/32/48... is written into row 0 of V_RAM, 2/18/34/50... of row 2/18/34/
  • the remaining data of V in column 50 is written into row 1 of V_RAM, and the remaining data in column 4/20/36/52 of row 4/20/36/52... is written into row 2 of V_RAM,... 14/30
  • the remaining data of V in columns 14/30/46/62 of rows /46/62... is written into row 7 of V_RAM.
  • the remaining data of Y in row 1,..., 15/31/47/63... is written into the 15th row of Y_RAM;
  • YUV444 mode write the Y remaining data of line 8m 5 +n 5 into the n 5th line of Y_RAM, write the remaining U data of line 8m 5 +n 5 into the n 5th line of U_RAM, and write the remaining U data of line 8m 5 +n 5 into the n 5th line of U_RAM.
  • the Y remaining data of rows 0/8/16/24... is written into row 0 of Y_RAM, and the remaining Y data of rows 1/9/17/25... is written into row 1 of Y_RAM,...
  • the remaining data of Y in rows 7/15/23/31... is written into row 7 of Y_RAM, and the remaining data in U in rows 0/8/16/24... is written into row 0 of U_RAM, 1/9/17/
  • the remaining U data of row 25... is written into the first row of U_RAM, the remaining U data of rows 7/15/23/31... is written into the 7th row of U_RAM, and the remaining data of row 0/8/16/24...
  • the remaining data of V is written into the 0th row of V_RAM, the remaining data of V in rows 1/9/17/25... is written into the 1st row of V_RAM,..., the remaining V data in rows 7/15/23/31... Data is written into line 7 of V_RAM.
  • the video data processing method further includes: obtaining a compression configuration mode; and determining the number of Blocks to read based on the compression configuration mode.
  • the compression configuration modes include YUV444, YUV422, and YUV420.
  • the number of Blocks corresponding to different compression configuration modules and the amount of data included in a Block are also different.
  • YUV420 mode two Blocks are first read ( 16 ⁇ 16), then read the U components of two Blocks (8 ⁇ 8), and the V components of two Blocks (8 ⁇ 8).
  • YUV422 mode first read the two Blocks (16 ⁇ 16) Y component, then read the U component of two Block (8 ⁇ 16), and the V component of two Block (8 ⁇ 16).
  • YUV444 mode first read the Y component of the two Block (8 ⁇ 8), Then read the U components of two Blocks (8 ⁇ 8) and the V components of two Blocks (8 ⁇ 8).
  • the video data processing method also includes: obtaining the RAM bit width; determining the number of Blocks to read based on the compression configuration mode.
  • the process includes: and determining the number of Blocks to read based on the compression configuration mode and the RAM bit width. number.
  • the number of blocks to be read can be determined based on the resources provided by the on-chip RAM.
  • Y_RAM is 256 bit, which means that the data of two blocks can be cached. Then the data of three blocks can be read at one time and two blocks can be cached. Block data.
  • the video data processing method further includes:
  • the process of determining the storage space where the video data to be compressed corresponding to the read signal is located includes: in response to receiving the read signal and the number of reads reaches a preset number of times, determining the storage space where the video data to be compressed corresponding to the read signal is located.
  • the storage space is a DDR storage space; and in response to receiving the read signal and the number of reads has not reached the preset number, it is determined that the storage space where the video data to be compressed corresponding to the read signal is located is the RAM storage space.
  • the processing module After the processing module reads the video data of multiple blocks in the DDR, it will store the video data that has not been transmitted to the compression module into the storage space corresponding to the RAM. After receiving the next trigger of the compression module, it will save the video data from the RAM. To read the corresponding Block, the processing module will record the number of times the corresponding Block is read from RAM. In response to receiving the read signal sent by the compression module, the currently recorded number of reads does not reach the preset number, and continues to read from RAM. Read the video data of the corresponding Block, and in response to the number of reads of the current record reaching the preset number, adopt the above-mentioned strategy of reading video data from the DDR.
  • the preset number of times can be determined based on the number of blocks read from DDR each time. For example, 3 blocks of video data can be read from DDR each time, then the preset number of times can be set to two. Assume that the first time After receiving the read signal sent by the compression module, it determines that the storage space where the video data to be compressed corresponding to the current read signal is located is the DDR storage space, reads 3 Blocks of data from the DDR, and then converts the data corresponding to the current read signal to The data of the block is transmitted to the compression module. The read signal sent by the compression module is received for the second time. At this time, the number of reads is 0 and has not reached the preset number.
  • the storage space where the video data to be compressed corresponding to the current read signal is located It is the RAM storage space.
  • the number of reads is 1, which has not reached the preset number.
  • Block data is sent to the compression module, and the number of reads is recorded as 2.
  • the number of reads is 2.
  • the preset number the number corresponding to the current read signal is determined.
  • the storage space where the video data to be compressed is the DDR storage space, then 3 more blocks of data are read from the DDR, and so on.
  • FIG. 5 is a schematic structural diagram of a video data processing system provided by this application.
  • the video data processing system includes a determination module 11, a first processing module 12 and a second processing module 13, wherein:
  • Determining module 11 configured to respond to receiving the read signal and determine the storage space where the video data to be compressed corresponding to the read signal is located;
  • the first processing module 12 is configured to respond to the determination module 11 determining that the storage space is a DDR storage space, read the video data of multiple blocks from the DDR storage space, and send the video data to be compressed in the video data to the compression module for compression. Process and store the video data except the video data to be compressed into the RAM storage space;
  • the second processing module 13 is configured to respond to the determination module 11 determining that the storage space is a RAM storage space, read the video data to be compressed from the RAM storage space, and send the video data to be compressed to the compression module for compression processing.
  • the video data processing system can read multiple blocks of video data at one time when performing a reading operation from the DDR storage space, which can increase the amount of data that can be read and written to the DDR at one time, and improves the suddenness of the data.
  • the efficiency of access is improved, thereby improving memory usage efficiency.
  • the RAM resources of the on-chip system are used to temporarily store the video data read from the DDR and not transmitted to the compression module, so that the next time a read signal is received, the video data to be compressed can be read directly from the RAM. , reducing the number of DDR reads, thereby greatly reducing the occupation of the DDR bus bandwidth by the video compression function, so that the DDR bus bandwidth can be used by other processes running on the CPU, thus achieving the purpose of improving system performance.
  • the video data processing system also includes a first acquisition module (not shown in the figure) and a first pre-processing module (not shown in the figure), wherein:
  • the first acquisition module is used to obtain the compression configuration mode
  • the first preprocessing module is used to determine the data to be stored in the video data in YUV format based on the compression configuration mode, and store the data to be stored in the DDR storage space.
  • the video data processing system also includes a second acquisition module (not shown in the figure) and a second pre-processing module (not shown in the figure), wherein:
  • the second acquisition module is used to obtain the compression configuration mode
  • the second preprocessing module is used to determine the number of blocks to read based on the compression configuration mode.
  • the video data processing system also includes a third acquisition module (not shown in the figure), wherein:
  • the third acquisition module is used to obtain the RAM bit width
  • the second preprocessing module is specifically used to determine the number of blocks to read based on the compression configuration mode and RAM bit width.
  • the compression configuration mode is any one of YUV420 compression configuration mode, YUV422 compression configuration mode, and YUV444 compression configuration mode.
  • the video data processing system also includes a recording module (not shown in the figure), wherein:
  • the recording module is used to record the number of times the video data to be compressed is read from the RAM storage space;
  • the process of determining the storage space where the video data to be compressed corresponding to the read signal is located includes:
  • the storage space where the video data to be compressed corresponding to the read signal is located is the DDR storage space
  • the storage space where the video data to be compressed corresponding to the read signal is located is the RAM storage space.
  • FIG. 6 is a schematic structural diagram of a video data processing device provided by the present application.
  • the video data processing device includes:
  • Memory 21 for storing computer readable instructions
  • One or more processors 22 are configured to implement the steps of the video data processing method described in any of the above embodiments when executing computer-readable instructions.
  • the memory 21 includes a non-volatile storage medium and an internal memory 21 .
  • the non-volatile storage medium stores an operating system and computer-readable instructions
  • the internal memory 21 provides an environment for the execution of the operating system and computer-readable instructions in the non-volatile storage medium.
  • the processor 22 executes the computer readable instructions stored in the memory 21, the following steps can be implemented: receiving a read signal, determining the storage space where the video data to be compressed corresponding to the read signal is located; responding to determining that the storage space is a DDR storage space , read the video data of multiple blocks from the DDR storage space, send the video data to be compressed in the video data to the compression module for compression processing, and save the video data of the multiple blocks except the video data to be compressed.
  • the video data is stored in the RAM storage space; in response to determining that the storage space is the RAM storage space, the video data to be compressed is read from the RAM storage space, and the video data to be compressed is sent to the compression module for compression processing.
  • the video data processing device can read the video data of multiple blocks at one time when performing a reading operation from the DDR storage space, which can increase the amount of data that can be read and written to the DDR at one time, and improves the suddenness of the data.
  • the efficiency of access is improved, thereby improving memory usage efficiency.
  • the RAM resources of the on-chip system are used to temporarily store the video data read from the DDR and not transmitted to the compression module, so that the next time a read signal is received, the video data to be compressed can be read directly from the RAM. , reducing the number of DDR reads, thereby greatly reducing the occupation of the DDR bus bandwidth by the video compression function, so that the DDR bus bandwidth can be used by other processes running on the CPU, thus achieving the purpose of improving system performance.
  • the processor 22 executes the computer subroutine stored in the memory 21, the following steps can be implemented: obtain the compression configuration mode; determine the data to be stored in the YUV format video data based on the compression configuration mode; and Store the data to be stored in the DDR storage space; the compression configuration mode is any one of YUV420 compression configuration mode, YUV422 compression configuration mode and YUV444 compression configuration mode.
  • the processor 22 executes the computer subroutine stored in the memory 21, the following steps can be implemented: obtain the compression configuration mode; and determine the number of Blocks to read based on the compression configuration mode; the compression configuration mode is Any one of YUV420 compression configuration mode, YUV422 compression configuration mode and YUV444 compression configuration mode.
  • the processor 22 executes the computer subroutine stored in the memory 21, the following steps can be implemented: obtain the RAM bit width; determine the number of Blocks to read based on the compression configuration mode and the RAM bit width. .
  • the processor 22 executes the computer subroutine stored in the memory 21, the following steps can be implemented: recording the number of times the video data to be compressed is read from the RAM storage space; in response to receiving the read Get the signal, and the number of reads reaches the preset number, and determine that the storage space where the video data to be compressed corresponding to the read signal is located is the DDR storage space; in response to receiving the read signal, and the number of reads does not reach the preset number, determine The storage space where the video data to be compressed corresponding to the read signal is located is the RAM storage space.
  • FIG. 7 is a structural diagram of another video data processing device provided by an embodiment of the present application.
  • the video data processing device also includes:
  • VGA module 23 used to convert the initial video data sent by the host into video data in RGB format
  • Conversion module 24 used to convert video data in RGB format into video data in YUV format
  • the compression module 25 is used to send read signals, receive video data to be compressed, and compress the video data to be compressed;
  • RAM 26 is used to store video data in YUV format read by the processor 22 from the DDR storage space.
  • the present application also provides a non-volatile computer-readable storage medium.
  • the non-volatile computer-readable storage medium stores computer-readable instructions.
  • the computer-readable instructions are implemented when executed by a processor. The steps of the video data processing method described in any of the above embodiments.
  • the non-volatile computer-readable storage medium can include: U disk, mobile hard disk, read-only memory (Read-Only Memory, ROM), random access memory (Random Access Memory, RAM), magnetic disk or optical disk and other media that can store program code.
  • Computer readable instructions are stored on the non-volatile storage medium.
  • the following steps are implemented: receiving a read signal, determining the storage space where the video data to be compressed corresponding to the read signal is located; responding In order to determine that the storage space is a DDR storage space, read the video data of multiple blocks from the DDR storage space, send the video data to be compressed in the video data to the compression module for compression processing, and store the video data of the multiple blocks
  • the video data except the video data to be compressed is stored in the RAM storage space; in response to determining that the storage space is the RAM storage space, the video data to be compressed is read from the RAM storage space, and the video data to be compressed is sent to the compression module for compression. deal with.
  • reading the video data of multiple blocks at one time can increase the amount of data read and written to the DDR at one time, improve the efficiency of burst access, and thereby improve the memory Usage efficiency.
  • the RAM resources of the on-chip system are used to temporarily store the video data read from the DDR and not transmitted to the compression module, so that the next time a read signal is received, the video data to be compressed can be read directly from the RAM. , reducing the number of DDR reads, thereby greatly reducing the occupation of the DDR bus bandwidth by the video compression function, so that the DDR bus bandwidth can be used by other processes running on the CPU, thus achieving the purpose of improving system performance.
  • the following steps can be implemented: obtain the compression configuration mode; determine the video in YUV format based on the compression configuration mode The data to be stored in the data; and the data to be stored is stored in the DDR storage space; the compression configuration mode is any one of YUV420 compression configuration mode, YUV422 compression configuration mode and YUV444 compression configuration mode.
  • the following steps can be implemented: obtaining the compression configuration mode; and determining the read value of the Block based on the compression configuration mode. Take the number; the compression configuration mode is any one of YUV420 compression configuration mode, YUV422 compression configuration mode and YUV444 compression configuration mode.
  • the following steps can be implemented: obtaining the RAM bit width; and based on the compression configuration mode and RAM bit width Determine the number of blocks to read.
  • the following steps can be implemented: recording the reading of the video data to be compressed from the RAM storage space. fetch times; in response to receiving the read signal, and the number of reads reaches the preset number of times, it is determined that the storage space where the video data to be compressed corresponding to the read signal is located is the DDR storage space; in response to receiving the read signal, and reading If the number of times does not reach the preset number, it is determined that the storage space where the video data to be compressed corresponding to the read signal is located is the RAM storage space.

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Abstract

本申请公开了一种视频数据处理方法、系统、装置及计算机可读存储介质，涉及视频传输领域，该视频数据处理方法包括：当接收到读取信号，确定读取信号对应的待压缩视频数据所在的存储空间；响应于确定存储空间为DDR存储空间，从DDR存储空间中读取多个Block的视频数据，将视频数据中的待压缩视频数据发送给压缩模块进行压缩处理，并将除待压缩视频数据外的视频数据存储到RAM存储空间；响应于确定存储空间为RAM存储空间，从RAM存储空间中读取待压缩视频数据，并将待压缩视频数据发送给压缩模块进行压缩处理。本申请能够提高内存使用效率，降低视频压缩功能对DDR总线带宽的占用，达到了提高系统性能的目的。

Description

视频数据处理方法、系统、装置及计算机可读存储介质
相关申请的交叉引用
本申请要求于2022年04月11日提交中国专利局，申请号为202210371374.9，申请名称为“视频数据处理方法、系统、装置及计算机可读存储介质”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及视频传输领域，特别涉及一种视频数据处理方法、系统、装置及计算机可读存储介质。
背景技术
传统的基板管理控制芯片中，视频压缩系统的处理流程参照图1所示，视频图形阵列模块(VGA，Video Graphics Array)将主机端传递来的初始视频数据转换为RGB格式的视频数据，转换模块对RGB格式的视频数据进行色彩空间转换，得到YUV格式的视频数据，将YUV格式的视频数据写到片外的DDR(Double Data Rate，双倍速率)的存储空间中，压缩模块按照Block(块)的顺序，从片外的DDR中读取YUV格式的视频数据，进行压缩处理，并将压缩处理后的视频数据写到片外的DDR中，然后CPU(Central Processing Unit，中央处理器)运行的网络驱动读取压缩视频数据的命令，通过网络发送至远程端解码显示，实现远程监控管理。
发明人意识到，传统方案中，将视频数据写到片外的DDR上的原因有以下两个，其一是避免后级模块处理不及时，而主机端的视频数据又一直不断的产生，因此要写到DDR中进行缓存，其二是因为视频压缩的过程，要求数据以Block的形式进行输入，而不是按行进行输入，因此要在压缩前进行Block转换，故要求先对YUV数据进行缓存。传统方案存在YUV数据要先写到片外的DDR，再多次从片外的DDR中读回到片内的过程，因此对DDR总线的占用率很高，并且在读DDR的时候都是短包读取，对DDR的使用效率很低，严重影响系统中其他的应用对DDR的访问，从而降低了整个系统的性能。
因此，如何提供一种解决上述技术问题的方案是本领域技术人员目前需要解决的问题。
发明内容
根据本申请公开的各种实施例，提供一种视频数据处理方法、系统、装置及计算机可读存储介质。
一种视频数据处理方法，包括：接收到读取信号，确定读取信号对应的待压缩视频数据所在的存储空间；响应于确定存储空间为DDR存储空间，从DDR存储空间中读取多个Block的视频数据，将视频数据中的待压缩视频数据发送给压缩模块进行压缩处理，并将所述多个Block的视频数据中除待压缩视频数据外的视频数据存储到RAM存储空间；响应于确定存储空间为RAM存储空间，从RAM存储空间中读取待压缩视频数据，并将待压缩视频数据发送给压缩模块进行压缩处理。
一种视频数据处理系统，包括：确定模块，用于响应于接收到读取信号，确定读取信号对应的待压缩视频数据所在的存储空间；第一处理模块，用于响应于确定当存储空间为DDR存储空间，从DDR存储空间中读取多个Block的视频数据，将视频数据中的待压缩视频数据发送给压缩模块进行压缩处理，并将所述多个Block的视频数据中除待压缩视频数据外的视频数据存储到RAM存储空间；及第二处理模块，用于响应于确定当存储空间为RAM存储空间，从RAM存储空间中读取待压缩视频数据，并将待压缩视频数据发送给压缩模块进行压缩处理。
一种视频数据处理装置，包括存储器以及一个或多个处理器，该存储器用于存储计算机可读指令；该一个或多个处理器用于执行计算机可读指令时实现上述视频数据处理方法的步骤。
一种非易失性计算机可读存储介质，该非易失性计算机可读存储介质上存储有计算机可读指令，该计算机可读指令被处理器执行时实现上述视频数据处理方法的步骤。
本申请的一个或多个实施例的细节在下面的附图和描述中提出。本申请的其它特征和优点将从说明书、附图以及权利要求书变得明显。
附图说明
为了更清楚地说明本申请实施例，下面将对实施例中所需要使用的附图做简单的介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为现有技术中的一种视频压缩系统的处理流程示意图；
图2为根据一个或多个实施例中视频压缩系统的结构示意图；
图3为根据一个或多个实施例中视频数据处理方法的步骤流程图；
图4为根据一个或多个实施例中Block的示意图；
图5为根据一个或多个实施例中视频数据处理系统的结构示意图；
图6为根据一个或多个实施例中视频数据处理装置的结构示意图；
图7为根据一个或多个实施例中视频数据处理装置的结构示意图。
具体实施方式
本申请的核心是提供一种视频数据处理方法、系统、装置及计算机可读存储介质，能够提高内存使用效率，降低视频压缩功能对DDR总线带宽的占用，达到了提高系统性能的目的。
为使本申请实施例的目的、技术方案和优点更加清楚，下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
为便于理解本申请所提出的一种视频数据处理方法，对于该视频数据处理方法所适用的视频压缩系统进行说明，该视频压缩系统可以通过基板管理控制芯片实现，参照图2所示，该视频压缩系统包括CPU 01、压缩模块02、处理模块03及片上的RAM(Random Access Memory，随机存取存储器)04，本实施例所提供的视频数据处理方法具体可以通过处理模块实现，请参照图3，图3为本申请所提供的一种视频数据处理方法的步骤流程图，该视频数据处理方法包括：
S101：接收到读取信号，确定读取信号对应的待压缩视频数据所在的存储空间；
S102：响应于确定存储空间为DDR存储空间，从DDR存储空间中读取多个Block的视频数据，将视频数据中的待压缩视频数据发送给压缩模块进行压缩处理，并将该多个Block的视频数据中除待压缩视频数据外的视频数据存储到RAM存储空间；
S103：响应于确定存储空间为RAM存储空间，从RAM存储空间中读取待压缩视频数据，并将待压缩视频数据发送给压缩模块进行压缩处理。
首先需要说明的是，视频压缩过程，无论是H.264格式的压缩还是JPEG(Joint Photographic Experts Group，是JPEG标准的产物，该标准由国际标准化组织(ISO)制 订，是面向连续色调静止图像的一种压缩标准)格式的压缩，都要求视频数据以Block的形式进行输入，而不是按行输入，因此，需要先把主机端发送过来的视频数据存储到片外的DDR对应的存储空间中，进行Block转换，本步骤中的待压缩视频数据实际上为一个Block的视频数据。
可以理解的是，接收到主机端发送的原始视频数据后，首先将原始视频数据转换为RGB格式的视频数据，再经过色彩空间转换，将RGB格式的视频数据转换为YUV格式的视频数据，最后，将YUV格式的视频数据分别存储到DDR对应的存储空间中，即将视频数据中的Y分量存储到DDR中以Y_addr为起始地址的内存空间，将视频数据中的U分量存储到DDR中以U_addr为起始地址的内存空间，将视频数据中的V分量存储到DDR中以V_addr为起始地址的内存空间，其中Y_addr，U_addr，V_addr根据不同的SoC系统而不同(用户可以自己定义)，同时CPU将上述三个地址分配给压缩模块，以便压缩模块输出读取信号。
具体的，参照图4所示，在不同压缩配置模式下对Block进行说明，图4中右侧每一个小方框表示左侧中8×8像素点，Cb就是U分量，Cr就是V分量，以压缩配置模式为YUV420为例进行说明，Y块表示4个8×8像素点的Y分量，Cb块表示1个8×8块的U分量，Cr块表示1个8×8块的V分量，也就是说，对于当前的压缩配置模式为YUV420的情况，压缩模块要产生读16×16的Y分量的地址顺序，8×8的U分量的地址顺序，8×8的V分量的地址顺序。对于当前的压缩配置模式为YUV422的情况，压缩模块要产生读16×16的Y分量的地址顺序，8×16的U分量的地址顺序，8×16的V分量的地址顺序。对于当前的压缩配置模式为YUV444的情况，压缩模块要产生读8×8的Y分量的地址顺序，8×8的U分量的地址顺序，8×8的V分量的地址顺序。
具体的，本实施例中每次从DDR的存储空间读取YUV格式的视频数据的读取策略为：分别读取多个Block的Y分量、多个Block的U分量以及多个Block的V分量，将当前读取信号对应的一个Block的Y分量，一个Block的U分量和一个Block的V分量依次传递给压缩模块后，将当前次读取的剩余的Y分量、U分量和V分量分别写入RAM对应的存储空间中。基于此，当接收到压缩模块输出的读取信号后，处理模块首先确定读取信号对应的待压缩视频数据所在存储空间，待压缩视频数据所在存储空间可能为DDR的存储空间，也可能为RAM的存储空间。如果确定是DDR的存储空间，则执行上述从DDR存储空间中读取视频数据的步骤，如果确定是RAM的存储空间，则从RAM中将当前读取信号对应的一个Block的Y分量，一个Block的U分量和一个Block的V分量依次传递给压缩模块。
举例说明，比如在压缩配置模式为YUV420时，以Y分量为例，假设一次从DDR中读取3个Block的Y分量，将与当前读取信号对应的Block的Y分量传递给压缩模块，剩下的两个Block的Y分量存储到Y_RAM中，那么下一次接收到读取信号时，可以直接从Y_RAM中获取一个Block的Y分量，即一次读DDR读取3个Block的数据，缓存两个Block，将进一步提高读DDR一次读写的数据量，提高读DDR的突发长度，也就提高了突发访问的效率，提高了内存使用效率。
可见，本实施例所提供的一种视频数据处理方法，从DDR存储空间中执行读取操作时，一次读取多个Block的视频数据，可以提高对DDR一次读写的数据量，提高了突发访问的效率，从而提高内存使用效率。同时，利用片上系统的RAM资源，对从DDR中读取的、未传输给压缩模块的视频数据进行暂存，以便下一次接收到读取信号时，可以直接从RAM中读取待压缩视频数据，减少读DDR的次数，从而极大的降低了视频压缩功能对DDR总线带宽的占用，使DDR的总线带宽可以给CPU上运行的其他进程使用，进而达到了提高系统性能的目的。
在上述实施例的基础上：
作为一种可选的实施例，该视频数据处理方法还包括：获取压缩配置模式；基于压缩配置模式确定YUV格式的视频数据中的待存储数据；及将待存储数据存储到DDR存储空间中。
具体的，首先获取压缩配置模式，不同的压缩配置模式，YUV各分量对应的待存储数据也是不同的，先对视频数据进行预选择，再存储至DDR的存储空间，一方面减少对DDR的存储空间的占用，另一方面便于后续读取。
具体的，下面对不同压缩配置模式下的视频数据存储到DDR的方案进行详细说明。
对于Y分量，所有压缩配置模式下的所有的Y分量存储到DDR中以Y_addr为起始地址的内存空间。
对于U分量，YUV444压缩配置模式下的所有U分量存储到DDR中以U_addr为起始地址的内存空间；YUV422压缩配置模式下的偶数行(或偶数列/奇数行/奇数列，原则是2个Y分量共用一个U分量)的U分量存储到DDR中以U_addr为起始地址的内存空间；YUV420压缩配置模式下的偶数行且偶数列(或者是奇数行、奇数列，或者偶数行、奇数列，或者奇数行、偶数列，其原则是4个Y分量共用一个U分量)的U分量存储到DDR中以U_addr为起始地址的内存空间。
对于V分量，YUV444压缩配置模式下的所有V分量存储到DDR中以V_addr为起 始地址的内存空间；YUV422压缩配置模式下的偶数行(偶数列/奇数行/奇数列原则是2个Y分量共用一个V分量)的V分量存储到DDR中以V_addr为起始地址的内存空间；YUV420压缩配置模式下的偶数行且偶数列(或者是奇数行奇数列，偶数行奇数列，奇数行偶数列，其原则是4个Y分量共用一个V分量)的V分量存储到DDR中以V_addr为起始地址的内存空间。
相应的，将每次读取DDR后Y分量、U分量和V分量的剩余数据存储到RAM的存储空间的过程如下：
将剩余的Y数据写入Y_RAM，注意，YUV420模式下，将第16m 1+n 1行的Y剩余数据写进Y_RAM的第n 1行，其中，m 1＝0,1,2,3,...，n 1＝0,1,2，3,...,15，即第0/16/32/48……行的Y剩余数据写进Y_RAM的第0行，第1/17/33/49……行的Y剩余数据写进Y_RAM的第1行……第15/31/47/63……行的Y剩余数据写进Y_RAM的第15行。
UV分量保留偶数行偶数列的情况下，将第16m 2+2n 2行的第16m 2+2n 2列的U剩余数据写进U_RAM的第n 2行，第16m 2+2n 2行的第16m 2+2n 2列的V剩余数据写进V_RAM的第n 2行，其中，m 2＝0,1,2,3,...，n 2＝0,1,2，3,...,7。
具体地，0/16/32/48……行的0/16/32/48……列的U剩余数据写进U_RAM的第0行，第2/18/34/50……行的2/18/34/50列的U剩余数据写进U_RAM的第1行，4/20/36/52……行的4/20/36/52列的U剩余数据写进U_RAM的第2行，……14/30/46/62……行的14/30/46/62列的U剩余数据写进U_RAM的第7行；
0/16/32/48……行的0/16/32/48……列的V剩余数据写进V_RAM的第0行，2/18/34/50……行的2/18/34/50列的V剩余数据写进V_RAM的第1行，4/20/36/52……行的4/20/36/52列的V剩余数据写进V_RAM的第2行，……14/30/46/62……行的14/30/46/62列的V剩余数据写进V_RAM的第7行。
YUV422模式下，将第16m 3+n 3行的Y剩余数据写进Y_RAM的第n 3行，其中，m 3＝0,1,2,3,..，n 3＝0,1,2，3,...,15，即0/16/32/48……行的Y剩余数据写进Y_RAM的第0行，1/17/33/49……行的Y剩余数据写进Y_RAM的第1行，……，15/31/47/63……行的Y剩余数据写进Y_RAM的第15行；
UV分量保留偶数列情况下，将第16m 4+n 4行的第2k 1列的U剩余数据写进U_RAM的第n 4行，将第16m 4+n 4行的第2k 1列的V剩余数据写进V_RAM的第n 4行，其中，m 4＝0,1,2,3,..，n 4＝0,1,2,3,...,15，k 1＝0,1,2,3,...,7，具体地：
0/16/32/48……行的第0/2/4/6…14列的U剩余数据写进U_RAM的第0行，1/17/33/49……行的第0/2/4/6…14列的U剩余数据写进U_RAM的第1行，……， 15/31/47/63……行的第0/2/4/6…14列的U剩余数据写进U_RAM的第15行；
0/16/32/48……行的第0/2/4/6…14列的V剩余数据写进V_RAM的第0行，1/17/33/49……行的第0/2/4/6…14列的V剩余数据写进V_RAM的第1行，……15/31/47/63……行的第0/2/4/6…14列的V剩余数据写进V_RAM的第15行。
YUV444模式下，将第8m 5+n 5行的Y剩余数据写进Y_RAM的第n 5行，将第8m 5+n 5行的U剩余数据写进U_RAM的第n 5行，将第8m 5+n 5行的V剩余数据写进V_RAM的第n 5行，其中，m 5＝0,1,2,3,...，n 5＝0,1,2,3,...,7。
具体地，0/8/16/24……行的Y剩余数据写进Y_RAM的第0行，1/9/17/25……行的Y剩余数据写进Y_RAM的第1行，……，7/15/23/31……行的Y剩余数据写进Y_RAM的第7行，0/8/16/24……行的U剩余数据写进U_RAM的第0行，1/9/17/25……行的U剩余数据写进U_RAM的第1行，……7/15/23/31……行的U剩余数据写进U_RAM的第7行，0/8/16/24……行的V剩余数据写进V_RAM的第0行，1/9/17/25……行的V剩余数据写进V_RAM的第1行，……，7/15/23/31……行的V剩余数据写进V_RAM的第7行。
作为一种可选的实施例，该视频数据处理方法还包括：获取压缩配置模式；及基于压缩配置模式确定Block的读取个数。
具体的，参照上文，压缩配置模式包括YUV444、YUV422、YUV420，不同的压缩配置模块对应的Block个数及一个Block包括的数据量也不同，比如，YUV420模式下，首先读取两个Block(16×16)的Y分量，再读取两个Block(8×8)的U分量，两个Block(8×8)的V分量，YUV422模式下，首先读取两个Block(16×16)的Y分量，再读取两个Block(8×16)的U分量，两个Block(8×16)的V分量，YUV444模式下，首先读取两个Block(8×8)的Y分量，再读取两个Block(8×8)的U分量，两个Block(8×8)的V分量。
作为一种可选的实施例，该视频数据处理方法还包括：获取RAM位宽；基于压缩配置模式确定Block的读取个数过程包括：及基于压缩配置模式和RAM位宽确定Block的读取个数。
具体的，可以根据片上的RAM可提供的资源确定Block的读取个数，比如Y_RAM为256bit，即可以缓存两个Block的数据，那么则可以一次读取3个Block的数据，并缓存两个Block的数据。
作为一种可选的实施例，将除待压缩视频数据外的视频数据存储到RAM存储空间之后，该视频数据处理方法还包括：
记录从RAM存储空间中读取待压缩视频数据的读取次数；
相应的，确定读取信号对应的待压缩视频数据所在的存储空间的过程包括：响应于接收到读取信号，且读取次数达到预设次数，判定读取信号对应的待压缩视频数据所在的存储空间为DDR存储空间；及响应于接收到读取信号，且读取次数未达到预设次数，判定读取信号对应的待压缩视频数据所在的存储空间为RAM存储空间。
具体的，处理模块在DDR中读取多个Block的视频数据之后，会将未传输给压缩模块的视频数据存储到RAM对应的存储空间里，在接收到压缩模块下一次触发后，会从RAM读取对应的Block，处理模块会记录从RAM读取对应的Block的次数，响应于在接收到压缩模块发送的读取信号时，当前记录的读取次数未达到预设次数，继续从RAM中读取对应的Block的视频数据，响应于当前记录的读取次数达到预设次数，采取上述从DDR读取视频数据的策略。
其中，预设次数可以根据上述每次从DDR中读Block的个数确定，比如每次可从DDR中读取3个Block的视频数据，那么预设次数可以设置为两次，假设第一次接收到压缩模块发送的读取信号，判定当前读取信号对应的待压缩视频数据所在的存储空间为DDR存储空间，从DDR中读取3个Block的数据，然后将与当前读取信号对应的Block的数据传输给压缩模块，第二次接收到压缩模块发送的读取信号，此时读取次数为0，未达到预设次数，判定当前读取信号对应的待压缩视频数据所在的存储空间为RAM存储空间，从RAM的存储空间中读取与当前读取信号对应的Block的数据发送给压缩模块，并记录读取次数为1，在第三次接收到压缩模块发送的读取信号，此时读取次数为1，未达到预设次数，判定当前读取信号对应的待压缩视频数据所在的存储空间为RAM存储空间，仍从RAM的存储空间中读取与当前读取信号对应的Block的数据发送给压缩模块，并记录读取次数为2，在第四次接收到压缩模块发送的读取信号，此时读取次数为2，达到预设次数，判定当前读取信号对应的待压缩视频数据所在的存储空间为DDR存储空间，则从DDR中再读取3个Block的数据，以此类推。
请参照图5，图5为本申请所提供的一种视频数据处理系统的结构示意图，该视频数据处理系统包括确定模块11、第一处理模块12以及第二处理模块13，其中：
确定模块11，用于响应于接收到读取信号，确定读取信号对应的待压缩视频数据所在的存储空间；
第一处理模块12，用于响应于确定模块11确定存储空间为DDR存储空间，从DDR存储空间中读取多个Block的视频数据，将视频数据中的待压缩视频数据发送给压缩模块 进行压缩处理，并将除待压缩视频数据外的视频数据存储到RAM存储空间；
第二处理模块13，用于响应于确定模块11确定存储空间为RAM存储空间，从RAM存储空间中读取待压缩视频数据，并将待压缩视频数据发送给压缩模块进行压缩处理。
可见，本实施例所提供的一种视频数据处理系统，从DDR存储空间中执行读取操作时，一次读取多个Block的视频数据，可以提高对DDR一次读写的数据量，提高了突发访问的效率，从而提高内存使用效率。同时，利用片上系统的RAM资源，对从DDR中读取的、未传输给压缩模块的视频数据进行暂存，以便下一次接收到读取信号时，可以直接从RAM中读取待压缩视频数据，减少读DDR的次数，从而极大的降低了视频压缩功能对DDR总线带宽的占用，使DDR的总线带宽可以给CPU上运行的其他进程使用，进而达到了提高系统性能的目的。
作为一种可选的实施例，该视频数据处理系统还包括第一获取模块(图中未示出)和第一预处理模块(图中未示出)，其中：
第一获取模块，用于获取压缩配置模式；
第一预处理模块，用于基于压缩配置模式确定YUV格式的视频数据中的待存储数据，将待存储数据存储到DDR存储空间中。
作为一种可选的实施例，该视频数据处理系统还包括第二获取模块(图中未示出)和第二预处理模块(图中未示出)，其中：
第二获取模块，用于获取压缩配置模式；
第二预处理模块，用于基于压缩配置模式确定Block的读取个数。
作为一种可选的实施例，该视频数据处理系统还包括第三获取模块(图中未示出)，其中：
第三获取模块，用于获取RAM位宽；
第二预处理模块具体用于基于压缩配置模式和RAM位宽确定Block的读取个数。
作为一种可选的实施例，压缩配置模式为YUV420压缩配置模式、YUV422压缩配置模式及YUV444压缩配置模式中的任意一种。
作为一种可选的实施例，该视频数据处理系统还包括记录模块(图中未示出)，其中：
记录模块，用于记录从RAM存储空间中读取待压缩视频数据的读取次数；
相应的，确定读取信号对应的待压缩视频数据所在的存储空间的过程包括：
响应于接收到读取信号，且读取次数达到预设次数，判定读取信号对应的待压缩视 频数据所在的存储空间为DDR存储空间；
响应于接收到读取信号，且读取次数未达到预设次数，判定读取信号对应的待压缩视频数据所在的存储空间为RAM存储空间。
另一方面，请参照图6，图6为本申请所提供的一种视频数据处理装置的结构示意图，该视频数据处理装置包括：
存储器21，用于存储计算机可读指令；及
一个或者多个处理器22，用于执行计算机可读指令时实现如上文任意一个实施例所描述的视频数据处理方法的步骤。
具体的，存储器21包括非易失性存储介质、内存储器21。该非易失性存储介质存储有操作系统和计算机可读指令，该内存储器21为非易失性存储介质中的操作系统和计算机可读指令的运行提供环境。处理器22执行存储器21中保存的计算机可读指令时，可以实现以下步骤：接收到读取信号，确定读取信号对应的待压缩视频数据所在的存储空间；响应于确定存储空间为DDR存储空间，从DDR存储空间中读取多个Block的视频数据，将视频数据中的待压缩视频数据发送给压缩模块进行压缩处理，并将所述多个Block的视频数据中除待压缩视频数据外的视频数据存储到RAM存储空间；响应于确定存储空间为RAM存储空间，从RAM存储空间中读取待压缩视频数据，并将待压缩视频数据发送给压缩模块进行压缩处理。
可见，本实施例所提供的一种视频数据处理装置，从DDR存储空间中执行读取操作时，一次读取多个Block的视频数据，可以提高对DDR一次读写的数据量，提高了突发访问的效率，从而提高内存使用效率。同时，利用片上系统的RAM资源，对从DDR中读取的、未传输给压缩模块的视频数据进行暂存，以便下一次接收到读取信号时，可以直接从RAM中读取待压缩视频数据，减少读DDR的次数，从而极大的降低了视频压缩功能对DDR总线带宽的占用，使DDR的总线带宽可以给CPU上运行的其他进程使用，进而达到了提高系统性能的目的。
作为一种可选的实施例，处理器22执行存储器21中保存的计算机子程序时，可以实现以下步骤：获取压缩配置模式；基于压缩配置模式确定YUV格式的视频数据中的待存储数据；及将待存储数据存储到DDR存储空间中；压缩配置模式为YUV420压缩配置模式、YUV422压缩配置模式及YUV444压缩配置模式中的任意一种。
作为一种可选的实施例，处理器22执行存储器21中保存的计算机子程序时，可以实现以下步骤：获取压缩配置模式；及基于压缩配置模式确定Block的读取个数；压缩配 置模式为YUV420压缩配置模式、YUV422压缩配置模式及YUV444压缩配置模式中的任意一种。
作为一种可选的实施例，处理器22执行存储器21中保存的计算机子程序时，可以实现以下步骤：获取RAM位宽；基及于压缩配置模式和RAM位宽确定Block的读取个数。
作为一种可选的实施例，处理器22执行存储器21中保存的计算机子程序时，可以实现以下步骤：记录从RAM存储空间中读取待压缩视频数据的读取次数；响应于接收到读取信号，且读取次数达到预设次数，判定读取信号对应的待压缩视频数据所在的存储空间为DDR存储空间；响应于接收到读取信号，且读取次数未达到预设次数，判定读取信号对应的待压缩视频数据所在的存储空间为RAM存储空间。
在上述实施例的基础上，作为优选实施方式，参见图7，图7为本申请实施例提供的另一种视频数据处理装置的结构图，该视频数据处理装置还包括：
VGA模块23，用于将主机发送的初始视频数据转换为RGB格式的视频数据；
转换模块24，用于将RGB格式的视频数据转换为YUV格式的视频数据；
压缩模块25，用于发送读取信号，还用于接收待压缩视频数据，对待压缩视频数据进行压缩；及
RAM 26，用于存储处理器22从DDR存储空间中读取的YUV格式的视频数据。
另一方面，本申请还提供了一种非易失性计算机可读存储介质，该非易失性计算机可读存储介质上存储有计算机可读指令，该计算机可读指令被处理器执行时实现如上文任意一个实施例所描述的视频数据处理方法的步骤。
具体的，该非易失性计算机可读存储介质可以包括：U盘、移动硬盘、只读存储器(Read-Only Memory，ROM)、随机存取存储器(Random Access Memory，RAM)、磁碟或者光盘等各种可以存储程序代码的介质。该非易失性存储介质上存储有计算机可读指令，计算机可读指令被处理器执行时实现以下步骤：接收到读取信号，确定读取信号对应的待压缩视频数据所在的存储空间；响应于确定存储空间为DDR存储空间，从DDR存储空间中读取多个Block的视频数据，将视频数据中的待压缩视频数据发送给压缩模块进行压缩处理，并将所述多个Block的视频数据中除待压缩视频数据外的视频数据存储到RAM存储空间；响应于确定存储空间为RAM存储空间，从RAM存储空间中读取待压缩视频数据，并将待压缩视频数据发送给压缩模块进行压缩处理。
可见，本实施例中，从DDR存储空间中执行读取操作时，一次读取多个Block的视 频数据，可以提高对DDR一次读写的数据量，提高了突发访问的效率，从而提高内存使用效率。同时，利用片上系统的RAM资源，对从DDR中读取的、未传输给压缩模块的视频数据进行暂存，以便下一次接收到读取信号时，可以直接从RAM中读取待压缩视频数据，减少读DDR的次数，从而极大的降低了视频压缩功能对DDR总线带宽的占用，使DDR的总线带宽可以给CPU上运行的其他进程使用，进而达到了提高系统性能的目的。
作为一种可选的实施例，非易失性计算机可读存储介质中存储的计算机子程序被处理器执行时，具体可以实现以下步骤：获取压缩配置模式；基于压缩配置模式确定YUV格式的视频数据中的待存储数据；及将待存储数据存储到DDR存储空间中；压缩配置模式为YUV420压缩配置模式、YUV422压缩配置模式及YUV444压缩配置模式中的任意一种。
作为一种可选的实施例，非易失性计算机可读存储介质中存储的计算机子程序被处理器执行时，具体可以实现以下步骤：获取压缩配置模式；及基于压缩配置模式确定Block的读取个数；压缩配置模式为YUV420压缩配置模式、YUV422压缩配置模式及YUV444压缩配置模式中的任意一种。
作为一种可选的实施例，非易失性计算机可读存储介质中存储的计算机子程序被处理器执行时，具体可以实现以下步骤：获取RAM位宽；及基于压缩配置模式和RAM位宽确定Block的读取个数。
作为一种可选的实施例，非易失性计算机可读存储介质中存储的计算机子程序被处理器执行时，具体可以实现以下步骤：记录从RAM存储空间中读取待压缩视频数据的读取次数；响应于接收到读取信号，且读取次数达到预设次数，判定读取信号对应的待压缩视频数据所在的存储空间为DDR存储空间；响应于接收到读取信号，且读取次数未达到预设次数，判定读取信号对应的待压缩视频数据所在的存储空间为RAM存储空间。
还需要说明的是，在本说明书中，诸如第一和第二等之类的关系术语仅仅用来将一个实体或者操作与另一个实体或操作区分开来，而不一定要求或者暗示这些实体或操作之间存在任何这种实际的关系或者顺序。而且，术语“包括”、“包含”或者其任何其他变体意在涵盖非排他性的包含，从而使得包括一系列要素的过程、方法、物品或者设备不仅包括那些要素，而且还包括没有明确列出的其他要素，或者是还包括为这种过程、方法、物品或者设备所固有的要素。在没有更多限制的状况下，由语句“包括一个……”限定的要素，并不排除在包括要素的过程、方法、物品或者设备中还存在另外的相同要 素。
对所公开的实施例的上述说明，使本领域专业技术人员能够实现或使用本申请。对这些实施例的多种修改对本领域的专业技术人员来说将是显而易见的，本文中所定义的一般原理可以在不脱离本申请的精神或范围的情况下，在其他实施例中实现。因此，本申请将不会被限制于本文所示的这些实施例，而是要符合与本文所公开的原理和新颖特点相一致的最宽的范围。

Claims (20)

  1. 一种视频数据处理方法，其特征在于，包括：
    接收到读取信号，确定所述读取信号对应的待压缩视频数据所在的存储空间；
    响应于确定所述存储空间为DDR存储空间，从所述DDR存储空间中读取多个Block的视频数据，将所述视频数据中的所述待压缩视频数据发送给压缩模块进行压缩处理，并将所述多个Block的视频数据中除所述待压缩视频数据外的视频数据存储到RAM存储空间；及
    响应于确定所述存储空间为所述RAM存储空间，从所述RAM存储空间中读取所述待压缩视频数据，并将所述待压缩视频数据发送给所述压缩模块进行压缩处理。
  2. 根据权利要求1所述的视频数据处理方法，其特征在于，所述待压缩视频数据为一个Block的视频数据。
  3. 根据权利要求1或2所述的视频数据处理方法，其特征在于，还包括：
    获取压缩配置模式；
    基于所述压缩配置模式确定YUV格式的视频数据中的待存储数据；及
    将所述待存储数据存储到所述DDR存储空间中。
  4. 根据权利要求3所述的视频数据处理方法，其特征在于，所述压缩配置模式为YUV420压缩配置模式，所述将所述待存储数据存储到所述DDR存储空间中，包括：
    将所述待存储数据的Y分量存储到DDR中以Y_addr为起始地址的内存空间；
    将所述待存储数据的偶数行且偶数列、奇数行且奇数列、偶数行且奇数列、或者奇数行且偶数列的U分量存储到DDR中以U_addr为起始地址的内存空间；及
    将所述待存储数据的对于偶数行且偶数列、奇数行且奇数列、偶数行且奇数列、或者奇数行且偶数列的V分量存储到DDR中以V_addr为起始地址的内存空间。
  5. 根据权利要求4所述的视频数据处理方法，其特征在于，所述将所述多个Block的视频数据中除所述待压缩视频数据外的视频数据存储到RAM存储空间，包括：
    将第16m 1+n 1行的Y剩余数据写进Y_RAM的第n 1行；
    将第16m 2+2n 2行的第16m 2+2n 2列的U剩余数据写进U_RAM的第n 2行；及
    将第16m 2+2n 2行的第16m 2+2n 2列的V剩余数据写进V_RAM的第n 2行；
    其中，m 1＝0,1,2,3,...，n 1＝0,1,2，3,...,15，m 2＝0,1,2,3,...，n 2＝0,1,2，3,...,7。
  6. 根据权利要求3所述的视频数据处理方法，其特征在于，所述压缩配置模式为 YUV422压缩配置模式，所述将所述待存储数据存储到所述DDR存储空间中，包括：
    将所述待存储数据的Y分量存储到DDR中以Y_addr为起始地址的内存空间；
    将所述待存储数据的偶数行、偶数列、奇数行或者奇数列的U分量存储到DDR中以U_addr为起始地址的内存空间；及
    将所述待存储数据的对于偶数行、偶数列、奇数行或者奇数列的V分量存储到DDR中以V_addr为起始地址的内存空间。
  7. 根据权利要求6所述的视频数据处理方法，其特征在于，所述将所述多个Block的视频数据中除所述待压缩视频数据外的视频数据存储到RAM存储空间，包括：
    将第16m 3+n 3行的Y剩余数据写进Y_RAM的第n 3行；
    将第16m 4+n 4行的第2k 1列的U剩余数据写进U_RAM的第n 4行；及
    将第16m 4+n 4行的第2k 1列的V剩余数据写进V_RAM的第n 4行；
    其中，m 3＝0,1,2,，n 3＝0,1,2，3,...,15，m 4＝0,1,2,3,...，n 4＝0,1,2,3,...,15，k 1＝0,1,2,3,...,7。
  8. 根据权利要求3所述的视频数据处理方法，其特征在于，所述压缩配置模式为YUV444压缩配置模式，所述将所述待存储数据存储到所述DDR存储空间中，包括：
    将所述待存储数据的Y分量存储到DDR中以Y_addr为起始地址的内存空间；
    将所述待存储数据的U分量存储到DDR中以U_addr为起始地址的内存空间；及
    将所述待存储数据的对于V分量存储到DDR中以V_addr为起始地址的内存空间。
  9. 根据权利要求8所述的视频数据处理方法，其特征在于，所述将所述多个Block的视频数据中除所述待压缩视频数据外的视频数据存储到RAM存储空间，包括：
    将第8m 5+n 5行的Y剩余数据写进Y_RAM的第n 5行；
    将第8m 5+n 5行的U剩余数据写进U_RAM的第n 5行；及
    将第8m 5+n 5行的V剩余数据写进V_RAM的第n 5行；
    其中，m 5＝0,1,2,3,...，n 5＝0,1,2,3,...,7。
  10. 根据权利要求1至9任意一项所述的视频数据处理方法，其特征在于，还包括：
    获取压缩配置模式；及
    基于所述压缩配置模式确定所述Block的读取个数。
  11. 根据权利要求10所述的视频数据处理方法，其特征在于，还包括：
    获取RAM位宽；及
    所述基于所述压缩配置模式确定所述Block的读取个数过程包括：
    基于所述压缩配置模式和所述RAM位宽确定所述Block的读取个数。
  12. 根据权利要求11所述的视频数据处理方法，其特征在于，所述基于所述压缩配置模式和所述RAM位宽确定所述Block的读取个数，包括：
    根据所述压缩配置模式和片上的RAM可提供的资源确定所述Block的读取个数。
  13. 根据权利要求10至14任意一项所述的视频数据处理方法，其特征在于，所述压缩配置模式为YUV420压缩配置模式、YUV422压缩配置模式及YUV444压缩配置模式中的任意一种。
  14. 根据权利要求1至13任意一项所述的视频数据处理方法，其特征在于，所述将除所述待压缩视频数据外的所述视频数据存储到RAM存储空间之后，该视频数据处理方法还包括：
    记录从所述RAM存储空间中读取所述待压缩视频数据的读取次数；
    所述确定所述读取信号对应的待压缩视频数据所在的存储空间，包括：
    响应于接收到读取信号，且所述读取次数达到预设次数，判定所述读取信号对应的待压缩视频数据所在的存储空间为所述DDR存储空间；及
    响应于接收到所述读取信号，且所述读取次数未达到所述预设次数，判定所述读取信号对应的待压缩视频数据所在的存储空间为所述RAM存储空间。
  15. 根据权利要求14所述的视频数据处理方法，其特征在于，所述方法还包括：
    根据从所述DDR存储空间中读取的视频数据的Block的个数确定。
  16. 一种视频数据处理系统，其特征在于，包括：
    确定模块，用于响应于接收到读取信号，确定所述读取信号对应的待压缩视频数据所在的存储空间；
    第一处理模块，用于响应于确定所述存储空间为DDR存储空间，从所述DDR存储空间中读取多个Block的视频数据，将所述视频数据中的所述待压缩视频数据发送给压缩模块进行压缩处理，并将所述多个Block的视频数据中除所述待压缩视频数据外的所述视频数据存储到RAM存储空间；及
    第二处理模块，用于响应于确定所述存储空间为所述RAM存储空间，从所述RAM存储空间中读取所述待压缩视频数据，并将所述待压缩视频数据发送给所述压缩模块进行压缩处理。
  17. 根据权利要求16所述的视频数据处理系统，其特征在于，所述系统还包括：
    记录模块，用于记录从RAM存储空间中读取待压缩视频数据的读取次数；及
    所述确定读取信号对应的待压缩视频数据所在的存储空间，包括：
    当接收到读取信号，且读取次数达到预设次数，判定读取信号对应的待压缩视频数据所在的存储空间为DDR存储空间；及
    当接收到读取信号，且读取次数未达到预设次数，判定读取信号对应的待压缩视频数据所在的存储空间为RAM存储空间。
  18. 一种视频数据处理装置，其特征在于，包括：
    存储器，用于存储计算机可读指令；及
    一个或多个处理器，用于执行所述计算机可读指令时实现如权利要求1至15任意一项所述的视频数据处理方法的步骤。
  19. 根据权利要求18所述的视频数据处理装置，其特征在于，该视频数据处理装置还包括：
    VGA模块，用于将主机发送的初始视频数据转换为RGB格式的视频数据；
    转换模块，用于将所述RGB格式的视频数据转换为YUV格式的视频数据；及
    压缩模块，用于发送读取信号，还用于接收待压缩视频数据，对所述待压缩视频数据进行压缩；
    RAM，用于存储所述处理器从DDR存储空间中读取的所述YUV格式的视频数据。
  20. 一种非易失性计算机可读存储介质，其特征在于，所述计算机可读存储介质上存储有计算机可读指令，所述计算机可读指令被处理器执行时实现如权利要求1-15任意一项所述的视频数据处理方法的步骤。
PCT/CN2022/115726 2022-04-11 2022-08-30 视频数据处理方法、系统、装置及计算机可读存储介质 WO2023197507A1 (zh)

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