WO2021248936A1 - 一种视频存储方法、装置、soc系统、介质 - Google Patents

一种视频存储方法、装置、soc系统、介质 Download PDF

Info

Publication number
WO2021248936A1
WO2021248936A1 PCT/CN2021/077020 CN2021077020W WO2021248936A1 WO 2021248936 A1 WO2021248936 A1 WO 2021248936A1 CN 2021077020 W CN2021077020 W CN 2021077020W WO 2021248936 A1 WO2021248936 A1 WO 2021248936A1
Authority
WO
WIPO (PCT)
Prior art keywords
stored
video data
video
storage space
application request
Prior art date
Application number
PCT/CN2021/077020
Other languages
English (en)
French (fr)
Inventor
张贞雷
刘同强
周玉龙
童元满
Original Assignee
浪潮(北京)电子信息产业有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 浪潮(北京)电子信息产业有限公司 filed Critical 浪潮(北京)电子信息产业有限公司
Priority to US18/008,381 priority Critical patent/US20230199143A1/en
Publication of WO2021248936A1 publication Critical patent/WO2021248936A1/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00—Details of television systems
    • H04N5/76—Television signal recording
    • H04N5/765—Interface circuits between an apparatus for recording and another apparatus
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00—Details of television systems
    • H04N5/76—Television signal recording
    • H04N5/907—Television signal recording using static stores, e.g. storage tubes or semiconductor memories
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
    • G06F15/7807—System on chip, i.e. computer system on a single chip; System in package, i.e. computer system on one or more chips in a single package
    • G06F15/781—On-chip cache; Off-chip memory
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/0604—Improving or facilitating administration, e.g. storage management
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0638—Organizing or formatting or addressing of data
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
    • G06F3/0671—In-line storage system
    • G06F3/0673—Single storage device
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N9/00—Details of colour television systems
    • H04N9/64—Circuits for processing colour signals
    • H04N9/67—Circuits for processing colour signals for matrixing
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Definitions

  • This application relates to the field of data storage technology, in particular to a video storage method, device, SOC system, and medium.
  • the corresponding off-chip DDR Double Data Rate, double-rate synchronous dynamic random access memory
  • DDR Double Data Rate, double-rate synchronous dynamic random access memory
  • Such storage space cannot be released when the SOC system closes the video function.
  • the video storage space on the SOC system needs to be used for different resolution scenarios.
  • the maximum resolution (such as 1920x1024) needs to be met, so generally a relatively large storage space will be allocated.
  • the resolution of the video to be stored is small, such as 640x480, a large part of the DDR space will be wasted, resulting in a waste of storage resources.
  • the purpose of this application is to provide a video storage method, device, SOC system, and medium, which can avoid the waste of storage resources on the SOC system and ensure the normal operation of the SOC system's functions.
  • the specific plan is as follows:
  • this application discloses a video storage method applied to an SOC system, including:
  • the to-be-stored video data corresponding to the to-be-stored video information is stored in the address space corresponding to the storage space application request in the target DDR.
  • the sending a storage space application request to the target DDR according to the video information to be stored and the target DDR occupancy information includes:
  • the video data to be stored is source video data
  • the video data to be stored is compressed video data
  • the sending a storage space application request to the target DDR includes:
  • a storage space application request is sent to the target DDR through the local CPU, wherein the storage space size requested in the storage space application request is based on the resolution of the video data to be stored Rate and frame number are determined;
  • the storing the to-be-stored video data corresponding to the to-be-stored video information in the address space corresponding to the storage space application request in the target DDR includes:
  • the video data to be stored is stored in the address space corresponding to the start address through the local source video data writing control module.
  • the sending a storage space application request to the target DDR includes:
  • a storage space application request is sent to the target DDR through the local CPU, wherein the storage space size requested in the storage space application request is based on the size of the video data to be stored The resolution, the number of frames of the video data to be stored, and the compression mode configuration are determined;
  • the storing the to-be-stored video data corresponding to the to-be-stored video information in the address space corresponding to the storage space application request in the target DDR includes:
  • the video data to be stored is stored in the address space corresponding to the start address through the local compressed video data writing control module.
  • the method before the sending a storage space application request to the target DDR through the local CPU, the method further includes:
  • the method before storing the to-be-stored video data in the address space corresponding to the start address through the local source video data writing control module, the method further includes:
  • the color space conversion of the video data to be stored is performed by the local color space conversion module to obtain the video data to be stored after conversion.
  • the video storage method further includes:
  • Stop requesting storage space from the target DDR, so that the target DDR can be called locally to support the running application.
  • this application discloses a video storage device applied to an SOC system, including:
  • the request sending module is configured to send a storage space application request to the target DDR according to the video information to be stored and the target DDR occupancy information;
  • An information receiving module configured to receive a storage space allocation response sent by the target DDR according to the storage space application request
  • the data storage module is configured to store the to-be-stored video data corresponding to the to-be-stored video information in the address space corresponding to the storage space application request in the target DDR.
  • this application discloses a SOC system, including:
  • the memory is used to store a computer program
  • the processor is configured to execute the computer program to implement the video storage method disclosed above.
  • this application discloses a computer-readable storage medium for storing a computer program, wherein the computer program is executed by a processor to implement the video storage method disclosed above.
  • this application first sends a storage space application request to the target DDR according to the video information to be stored and the target DDR occupancy information, and receives the storage space allocation response sent by the target DDR according to the storage space application request, and then transfers all
  • the to-be-stored video data corresponding to the to-be-stored video information is stored in the address space corresponding to the storage space application request in the target DDR.
  • the storage resources on the SOC system can be used to support the operation of other functions to ensure the normal operation of other functions on the system and improve the performance of the SOC system.
  • FIG. 1 is a flowchart of a video storage method disclosed in this application.
  • FIG. 2 is a block diagram of a video storage disclosed in this application.
  • FIG. 3 is a flowchart of a specific video storage method disclosed in this application.
  • FIG. 4 is a schematic diagram of a compressed mode configuration disclosed in this application.
  • FIG. 5 is a schematic diagram of the structure of a video storage device disclosed in this application.
  • FIG. 6 is a schematic diagram of the structure of a SOC system disclosed in this application.
  • this application proposes a video storage method, which can avoid the waste of storage resources on the SOC system and ensure the normal operation of the SOC system's functions.
  • an embodiment of the present application discloses a video storage method, which is applied to an SOC system, and the method includes:
  • Step S11 Send a storage space application request to the target DDR according to the video information to be stored and the target DDR occupancy information.
  • the target DDR is locally corresponding and can be used to write the local data to be stored DDR
  • the video information to be stored includes the resolution and the number of frames of the video to be stored
  • the video information to be stored includes the video data to be stored.
  • the storage space application request may include the start address of the storage space to be applied for locally, the resolution of the video to be stored, and the number of frames, where the start address may be determined according to the target DDR occupancy information.
  • Step S12 Receive a storage space allocation response sent by the target DDR according to the storage space application request.
  • the target DDR After sending the storage space application request, if the storage space corresponding to the storage space application request is allocated successfully, the target DDR will return a corresponding response, so the target DDR needs to be received locally according to the storage space application request The storage space allocation response sent. If the allocation is unsuccessful, you need to apply for a new address space.
  • Step S13 Store the to-be-stored video data corresponding to the to-be-stored video information in the address space corresponding to the storage space application request in the target DDR.
  • the to-be-stored video data corresponding to the to-be-stored video information can be stored in the address space corresponding to the storage space application request in the target DDR.
  • this application first sends a storage space application request to the target DDR according to the video information to be stored and the target DDR occupancy information, and receives the storage space allocation response sent by the target DDR according to the storage space application request, and then transfers all
  • the to-be-stored video data corresponding to the to-be-stored video information is stored in the address space corresponding to the storage space application request in the target DDR.
  • the storage resources on the SOC system can be used to support the operation of other functions to ensure the normal operation of other functions on the system and improve the performance of the SOC system.
  • the embodiment of the application discloses a specific video storage block diagram, including: graphics card, color space conversion module, DDR, source video data writing space module, compressed video data writing control module, address generation module , Compressed IP (that is, IP core, Intellectual Property core, intellectual property core) and CPU, and may also include a resolution detection module.
  • graphics card color space conversion module, DDR, source video data writing space module, compressed video data writing control module, address generation module , Compressed IP (that is, IP core, Intellectual Property core, intellectual property core) and CPU, and may also include a resolution detection module.
  • an embodiment of the present application discloses a specific video storage method, which is applied to an SOC system, and the method includes:
  • Step S21 When the video data to be stored is the source video data, a storage space application request is sent to the target DDR through the local CPU, wherein the storage space size requested in the storage space application request is based on the video to be stored The resolution of the data and the number of frames are determined.
  • a storage space application request may be sent to the target DDR first. That is, the local CPU sends a storage space application request to the target DDR. Specifically, a storage space application request is sent to the target DDR through corresponding software running on the local CPU.
  • a storage space application request is sent to the target DDR through the local CPU, where the storage space size requested in the storage space application request is based on the The resolution and the number of frames of the video data to be stored are determined, and the starting address of the requested storage space can be determined according to the occupancy of the target DDR.
  • Step S22 Receive a storage space allocation response sent by the target DDR according to the storage space application request through the local CPU.
  • the storage space allocation response sent by the target DDR according to the storage space application request needs to be received through the local CPU.
  • Step S23 Send the start address corresponding to the storage space application request, the number of frames of the to-be-stored video data, and the resolution of the to-be-stored video data to the local source video data writing control module through the local CPU.
  • the local CPU After receiving the storage space allocation response sent by the target DDR according to the storage space application request, the local CPU first sends relevant information to the local source video data writing control module, so that the local source video data writing control module receives Write the video data to be stored into the target DDR.
  • FIFOs First Input First Output
  • WR_ADDR_FIFO, WR_FRAME_NUM_FIFO, RSL_FIFO respectively store the starting address, the number of frames stored, and the resolution.
  • the local source video data is written into the control module to read WR_ADDR_FIFO, WR_FRAME_NUM_FIFO, RSL_FIFO in turn to get a set of storage space address information.
  • the first register WR_ADDR is the DDR to be written
  • the first address and the second register WR_FRAME_NUM are the number of frames to be written in the DDR space with WR_ADDR as the starting address
  • the third register RSL is the resolution information.
  • Step S24 Store the to-be-stored video data in the address space corresponding to the start address through the local source video data writing control module.
  • the local source video data writing control module After the local source video data writing control module obtains the starting address, resolution, and frame number, the local source video data writing control module can store the to-be-stored video data to the corresponding starting address In the address space.
  • the method further includes: performing color space conversion on the to-be-stored video data through a local color space conversion module to obtain the converted-to-be-stored video data. Convert the RGB data into YUV data and send it to the local source video data to be written into the control module.
  • the RGB color mode is a color standard in the industry. It obtains a variety of colors by changing the three color channels of red (R), green (G), and blue (B) and superimposing them with each other. , Is one of the most widely used color systems.
  • YUV is a color coding method, Y stands for brightness, U stands for chroma, and V stands for density.
  • the local source video data write control module reads the information in the three registers WR_ADDR, WR_FRAME_NUM, and RSL to obtain a set of storage space address information, and stores the corresponding video data to be stored in the address space, for example,
  • the read address information of a set of storage space is that the value of the WR_ADDR register is 0x1000_0000, and the value of WR_FRAME_NUM is 2, that is, 2 frames of image information should be written in the space with 0x1000_000 as the starting address on the DDR.
  • the resolution is used to calculate the number of frames written to the target DDR video.
  • the local CPU may again issue a storage space application request to the target DDR according to the video information to be stored that needs to be stored next and the occupancy of the target DDR. Until the source video data to be stored is stored or the target DDR storage space is insufficient.
  • the local CPU Before sending the storage space request request to the target DDR through the local CPU, it further includes: reading the resolution of the video data to be stored from the local graphics card through the local CPU; or, through the local CPU from the local resolution detection module Read the resolution of the video data to be stored. Specifically, if there is a register in the graphics card that stores the resolution corresponding to the video data to be stored, the local CPU can directly read the resolution corresponding to the video data to be stored from the graphics card, and there is no need to distinguish at this time. Rate detection module, the process at this time is shown by the dotted line in Figure 2. If there is no register in the graphics card that stores the resolution corresponding to the video data to be stored, the graphics card source video control information needs to be input to the resolution detection module.
  • the source video control information includes line and field synchronization control information such as Hs, Vs, etc., For resolution detection.
  • the video data to be stored is compressed video data
  • a storage space application request is sent to the target DDR through the local CPU, wherein the storage space size requested in the storage space application request is based on the to-be-stored
  • the resolution of the video data, the number of frames of the video data to be stored, and the compression mode configuration are determined. Specifically, for source video data with the same number of frames and the same resolution, because the compression mode configuration is different, the size of the storage space required for the compressed video data is also different, for example, for the same number of frames and the same resolution
  • the storage space required for compressed video data configured in the YUV420 compression mode is smaller than that of the compressed video data configured in the YUV444 compression mode.
  • each Y corresponds to a set of UV components, where Y represents brightness, U represents chroma, and V represents Concentration, so for the YUV420 compression mode configuration, a part of the UV component will be discarded.
  • the start address corresponding to the storage space application request and the frame number of the video data to be stored are sent to the local compressed video data writing control module through the local CPU; the local compressed video data writing control module is used to send the waiting
  • the storage video data is stored in the address space corresponding to the start address.
  • the storage space address information is also continuously issued, so the local compressed video data can be written into the control module.
  • the local compressed video data write control module reads WR_ADDR_FIFO, WR_FRAME_NUM_FIFO in turn, and then a set of storage space information can be obtained.
  • the two registers WR_FRAME_NUM are the number of video image frames to be written in the DDR space with WR_ADDR as the starting address.
  • a set of storage space address information can be read first, and then the corresponding compressed video data can be stored under this set of storage space address information, for example, the read A set of storage space address information is: the value of the WR_ADDR register is 0x7000_0000, the value of WR_FRAME_NUM is 3, that is, 3 frames of compressed images are to be written in the storage space with the starting address of 0x7000_000.
  • the module should use the frame header and end information carried by the compressed image to calculate the number of image frames that have been written. When the third frame end 0xFFD9 is detected, the writing is stopped.
  • the local CPU may again issue a storage space application request to the target DDR according to the video information to be stored that needs to be stored next and the occupancy of the target DDR. Until the source video data to be stored is stored or the target DDR storage space is insufficient.
  • the method further includes: reading the source video data from the target DDR, and compressing the source video data.
  • the address generation module generates the source video data reading address
  • the compression IP reads the source video data from the target DDR according to the source video data reading address, and compresses the compressed video data. Input to the local compressed video data writing control module.
  • the process of generating the source video data reading address by the address generating module includes: generating the source video data reading address using the obtained source video data storage storage space address information, resolution, and compression mode configuration. Specifically, three FIFOs are set up inside the address generation module: WR_ADDR_FIFO, WR_FRAME_NUM_FIFO, RSL_FIFO, which store the starting address, the number of stored frames, and the resolution respectively. Read 3 queues in sequence to get a set of information, after getting the start address of a frame of image, according to the compression mode configuration, generate the source video data reading address.
  • the compressed mode configuration includes two kinds of YUV420 and YUV444 shown in Figure 4.
  • YUV420 reads 16 ⁇ 16 Y first, then reads 8 ⁇ 8 U, then reads 8 ⁇ 8 V, and then Start repeating the steps of reading 16 ⁇ 16 Y.
  • YUV444 first reads 8 ⁇ 8 Y, then reads 8 ⁇ 8 U, then reads 8 ⁇ 8 V, and then starts to repeat reading 8. ⁇ 8 steps of Y. Only the start address of the first frame can be read in WR_ADDR_FIFO. If the current address stores multiple consecutive frames, the start address of the second and subsequent frames must be calculated in this module according to the resolution to generate the source video Data read address.
  • Step S25 If the video function closing instruction is received, the local video function is closed.
  • Step S26 Stop requesting storage space from the target DDR, so as to locally call the target DDR to support the application program that is in the running state.
  • an embodiment of the present application discloses a video storage device, which is applied to an SOC system, and includes:
  • the request sending module 11 is configured to send a storage space application request to the target DDR according to the video information to be stored and the occupancy information of the target DDR;
  • the information receiving module 12 is configured to receive a storage space allocation response sent by the target DDR according to the storage space application request;
  • the data storage module 13 is configured to store the to-be-stored video data corresponding to the to-be-stored video information in the address space corresponding to the storage space application request in the target DDR.
  • this application first sends a storage space application request to the target DDR according to the video information to be stored and the target DDR occupancy information, and receives the storage space allocation response sent by the target DDR according to the storage space application request, and then transfers all
  • the to-be-stored video data corresponding to the to-be-stored video information is stored in the address space corresponding to the storage space application request in the target DDR.
  • the storage resources on the SOC system can be used to support the operation of other functions to ensure the normal operation of other functions on the system and improve the performance of the SOC system.
  • an embodiment of the present application also discloses an SOC system, including: a processor 21 and a memory 22.
  • the memory 22 is used to store a computer program; the processor 21 is used to execute the computer program to implement the video storage method disclosed in the foregoing embodiments.
  • an embodiment of the present application also discloses a computer-readable storage medium for storing a computer program, wherein the computer program is executed by a processor to implement the video storage method disclosed in any of the foregoing embodiments.
  • the steps of the method or algorithm described in combination with the embodiments disclosed herein can be directly implemented by hardware, a software module executed by a processor, or a combination of the two.
  • the software module can be placed in random access memory (RAM), internal memory, read-only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disks, removable disks, CD-ROMs, or all areas in the technical field. Any other known storage media.

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Human Computer Interaction (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Television Signal Processing For Recording (AREA)

Abstract

一种视频存储方法、装置、SOC系统、介质，该方法包括：根据待存储视频信息和目标DDR占用信息，向目标DDR发送存储空间申请请求（S11）；接收目标DDR根据存储空间申请请求发送的存储空间分配响应（S12）；将待存储视频信息对应的待存储视频数据存储到目标DDR中与存储空间申请请求对应的地址空间下（S13）。本申请可以避免存储空间的浪费，且在不需要进行视频存储时，SOC系统上的存储资源可以用于支持其他功能的运行。

Description

一种视频存储方法、装置、SOC系统、介质
本申请要求于2020年06月12日提交中国专利局、申请号为202010540164.9、发明名称为“一种视频存储方法、装置、SOC系统、介质”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及数据存储技术领域，特别涉及一种视频存储方法、装置、SOC系统、介质。
背景技术
传统的集成视频压缩功能的SOC(System on Chip，片上系统)系统中，会预先在对应的片外DDR(Double Data Rate，双倍速率同步动态随机存储器)中分配地址连续的空间来存储源视频数据或压缩后视频数据，这样的存储空间在SOC系统关闭视频功能时，是无法释放的，这对于内存资源紧张的SOC系统而言，会影响SOC系统功能的运行。此外SOC系统上的视频存储空间需要用于不同的分辨率场景，为保险起见需要满足最大分辨率(如1920x1024)需求，所以一般会分配比较大的存储空间，但是如果在SOC系统的应用中，待存储视频的分辨率较小，如640x480，则该部分DDR空间中会有很大一部分被浪费掉，造成存储资源的浪费。
发明内容
有鉴于此，本申请的目的在于提供一种视频存储方法、装置、SOC系统、介质，能够避免SOC系统上的存储资源浪费，且保证SOC系统功能的正常运行。其具体方案如下：
第一方面，本申请公开了一种视频存储方法，应用于SOC系统，包括：
根据待存储视频信息和目标DDR占用信息，向所述目标DDR发送存储空间申请请求；
接收所述目标DDR根据所述存储空间申请请求发送的存储空间分配响应；
将所述待存储视频信息对应的待存储视频数据存储到所述目标DDR中与所述存储空间申请请求对应的地址空间下。
可选地，所述根据待存储视频信息和目标DDR占用信息，向所述目标DDR发送存储空间申请请求，包括：
当所述待存储视频数据为源视频数据时，根据所述待存储视频的分辨率、所述待存储视频的帧数以及目标DDR占用信息，向所述目标DDR发送存储空间申请请求；
当所述待存储视频数据为压缩后视频数据时，根据所述待存储视频的分辨率、所述待存储视频的帧数、压缩模式配置以及目标DDR占用信息，向所述目标DDR发送存储空间申请请求。
可选地，所述向所述目标DDR发送存储空间申请请求，包括：
当所述待存储视频数据为源视频数据时，通过本地CPU向所述目标DDR发送存储空间申请请求，其中，所述存储空间申请请求中申请的存储空间大小根据所述待存储视频数据的分辨率和帧数确定；
相应地，所述将所述待存储视频信息对应的待存储视频数据存储到所述目标DDR中与所述存储空间申请请求对应的地址空间下，包括：
通过本地CPU将与所述存储空间申请请求对应的起始地址、所述待存储视频数据的帧数以及所述待存储视频数据的分辨率发送到本地源视频数据写入控制模块；
通过本地源视频数据写入控制模块将所述待存储视频数据存储到所述起始地址对应的地址空间中。
可选地，所述向所述目标DDR发送存储空间申请请求，包括：
当所述待存储视频数据为压缩后视频数据时，通过本地CPU向所述目标DDR发送存储空间申请请求，其中，所述存储空间申请请求中申请的存储空间大小根据所述待存储视频数据的分辨率、所述待存储视频数据的帧数以及压缩模式配置确定；
相应地，所述将所述待存储视频信息对应的待存储视频数据存储到所述目标DDR中与所述存储空间申请请求对应的地址空间下，包括：
通过本地CPU将与所述存储空间申请请求对应的起始地址、所述待存 储视频数据的帧数发送到本地压缩视频数据写入控制模块；
通过本地压缩视频数据写入控制模块将所述待存储视频数据存储到所述起始地址对应的地址空间中。
可选地，所述通过本地CPU向所述目标DDR发送存储空间申请请求之前，还包括：
通过本地CPU从本地显卡中读取所述待存储视频数据的分辨率；
或，通过本地CPU从本地分辨率检测模块中读取所述待存储视频数据的分辨率。
可选地，所述通过本地源视频数据写入控制模块将所述待存储视频数据存储到所述起始地址对应的地址空间中之前，还包括：
通过本地色彩空间转换模块对所述待存储视频数据进行色彩空间转换，得到转换后待存储视频数据。
可选地，所述视频存储方法，还包括：
若接收到视频功能关闭指令，则关闭本地视频功能；
停止向所述目标DDR申请存储空间，以便本地调用所述目标DDR以支持正处于运行状态的应用程序。
第二方面，本申请公开了一种视频存储装置，应用于SOC系统，包括：
请求发送模块，用于根据待存储视频信息和目标DDR占用信息，向所述目标DDR发送存储空间申请请求；
信息接收模块，用于接收所述目标DDR根据所述存储空间申请请求发送的存储空间分配响应；
数据存储模块，用于将所述待存储视频信息对应的待存储视频数据存储到所述目标DDR中与所述存储空间申请请求对应的地址空间下。
第三方面，本申请公开了一种SOC系统，包括：
存储器和处理器；
其中，所述存储器，用于存储计算机程序；
所述处理器，用于执行所述计算机程序，以实现前述公开的视频存储方法。
第四方面，本申请公开了一种计算机可读存储介质，用于保存计算机 程序，其中，所述计算机程序被处理器执行时实现前述公开的视频存储方法。
可见，本申请先根据待存储视频信息和目标DDR占用信息，向所述目标DDR发送存储空间申请请求，并接收所述目标DDR根据所述存储空间申请请求发送的存储空间分配响应，然后将所述待存储视频信息对应的待存储视频数据存储到所述目标DDR中与所述存储空间申请请求对应的地址空间下。本申请中在视频存储的过程中，先根据待存储视频信息以及待写入DDR的占用情况进行存储空间的申请，再将待存储视频存储到申请的空间中，这样可以避免存储空间的浪费，且在不需要进行视频存储时，SOC系统上的存储资源便可以用于支持其他功能的运行，以保证系统上其他功能的正常运行，且提高了SOC系统的性能。
附图说明
为了更清楚地说明本申请实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据提供的附图获得其他的附图。
图1为本申请公开的一种视频存储方法流程图；
图2为本申请公开的一种视频存储框图；
图3为本申请公开的一种具体的视频存储方法流程图；
图4为本申请公开的一种压缩模式配置示意图；
图5为本申请公开的一种视频存储装置结构示意图；
图6为本申请公开的一种SOC系统结构示意图。
具体实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没 有做出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
目前，集成视频压缩功能的SOC系统中，会预先在对应的片外DDR中分配地址连续的空间来存储源视频数据或压缩后视频数据，这样预先进行存储空间的分配会导致视频数据存储失去灵活性，造成存储资源的浪费以及影响SOC系统功能的正常运行等。有鉴于此，本申请提出了一种视频存储方法，能够避免SOC系统上的存储资源浪费，且保证SOC系统功能的正常运行。
参见图1所示，本申请实施例公开了一种视频存储方法，应用于SOC系统，该方法包括：
步骤S11：根据待存储视频信息和目标DDR占用信息，向所述目标DDR发送存储空间申请请求。
在具体的实施过程中，需要先根据待存储视频信息和目标DDR占用信息向所述目标DDR发送存储空间申请请求，其中，所述目标DDR为本地对应的、可用于写入本地待存储数据的DDR，在待存储视频数据为源视频数据时，所述待存储视频信息包括待存储视频的分辨率、帧数，在待存储视频数据为压缩后视频数据时，所述待存储视频信息包括待存储视频的分辨率、帧数、压缩模式配置。所述存储空间申请请求中可以包括本地要申请的存储空间的起始地址、待存储视频的分辨率以及帧数，其中，所述起始地址可以根据所述目标DDR占用信息确定。
步骤S12：接收所述目标DDR根据所述存储空间申请请求发送的存储空间分配响应。
在发送所述存储空间申请请求之后，如果所述存储空间申请请求对应的存储空间分配成功，则所述目标DDR会返回相应的响应，所以本地需要接收所述目标DDR根据所述存储空间申请请求发送的存储空间分配响应。如果分配不成功，则需要申请新的地址空间。
步骤S13：将所述待存储视频信息对应的待存储视频数据存储到所述目标DDR中与所述存储空间申请请求对应的地址空间下。
在接收到所述存储空间分配响应之后，便可以将所述待存储视频信息 对应的待存储视频数据存储到所述目标DDR中与所述存储空间申请请求对应的地址空间下。
可见，本申请先根据待存储视频信息和目标DDR占用信息，向所述目标DDR发送存储空间申请请求，并接收所述目标DDR根据所述存储空间申请请求发送的存储空间分配响应，然后将所述待存储视频信息对应的待存储视频数据存储到所述目标DDR中与所述存储空间申请请求对应的地址空间下。本申请中在视频存储的过程中，先根据待存储视频信息以及待写入DDR的占用情况进行存储空间的申请，再将待存储视频存储到申请的空间中，这样可以避免存储空间的浪费，且在不需要进行视频存储时，SOC系统上的存储资源便可以用于支持其他功能的运行，以保证系统上其他功能的正常运行，且提高了SOC系统的性能。
参见图2所示，本申请实施例公开了一种具体的视频存储框图，包括：显卡、色彩空间转换模块、DDR、源视频数据写入空间模块、压缩视频数据写入控制模块、地址产生模块、压缩IP(也即IP核，Intellectual Property core，知识产权核)以及CPU，还可以包括分辨率检测模块。
结合图2所示的框架对本申请提供的视频存储方法进行说明。参见图3所示，本申请实施例公开了一种具体的视频存储方法，应用于SOC系统，该方法包括：
步骤S21：当所述待存储视频数据为源视频数据时，通过本地CPU向所述目标DDR发送存储空间申请请求，其中，所述存储空间申请请求中申请的存储空间大小根据所述待存储视频数据的分辨率和帧数确定。
在具体的实施过程中，可以先向所述目标DDR发送存储空间申请请求。也就是通过本地CPU向所述目标DDR发送存储空间申请请求。具体的是通过本地CPU上运行的相应软件向所述目标DDR发送存储空间申请请求。
在具体的实施过程中，当所述待存储视频数据为源视频数据时，通过本地CPU向所述目标DDR发送存储空间申请请求，其中，所述存储空间申请请求中申请的存储空间大小根据所述待存储视频数据的分辨率和帧数确定，申请的存储空间的起始地址可以根据所述目标DDR占用情况确定。
步骤S22：通过本地CPU接收所述目标DDR根据所述存储空间申请请求发送的存储空间分配响应。
可以理解的是，在发送所述存储空间申请请求之后，还需要通过本地CPU接收所述目标DDR根据所述存储空间申请请求发送的存储空间分配响应。
步骤S23：通过本地CPU将与所述存储空间申请请求对应的起始地址、所述待存储视频数据的帧数以及所述待存储视频数据的分辨率发送到本地源视频数据写入控制模块。
在接收所述目标DDR根据所述存储空间申请请求发送的存储空间分配响应之后，本地CPU先将相关信息发送给本地源视频数据写入控制模块，以便本地源视频数据写入控制模块根据接收到的相关信息将待存储视频数据写入到目标DDR中。
在具体的实施过程中，因为视频是连续输出的，存储空间地址信息也是连续下发的，故可在本地源视频数据写入控制模块中设置3个FIFO(First Input First Output，先入先出队列)：WR_ADDR_FIFO、WR_FRAME_NUM_FIFO、RSL_FIFO，分别存储起始地址、存储的帧数、分辨率。然后本地源视频数据写入控制模块依次读WR_ADDR_FIFO、WR_FRAME_NUM_FIFO、RSL_FIFO，便可得到一组存储空间地址信息，若用寄存器WR_ADDR,WR_FRAME_NUM，RSL表示，则第一个寄存器WR_ADDR为要写入的DDR的首地址，第二个寄存器WR_FRAME_NUM为以WR_ADDR为起始地址的DDR空间中，要写入的帧数，第三个寄存器RSL为分辨率信息。
步骤S24：通过本地源视频数据写入控制模块将所述待存储视频数据存储到所述起始地址对应的地址空间中。
在本地源视频数据写入控制模块得到所述起始地址、分辨率以及帧数之后，便可以通过本地源视频数据写入控制模块将所述待存储视频数据存储到所述起始地址对应的地址空间中。
在将源视频数据存储到所述目标DDR之前，还包括：通过本地色彩空间转换模块对所述待存储视频数据进行色彩空间转换，得到转换后待存 储视频数据。将RGB数据转换成YUV数据并发送到本地源视频数据写入控制模块中。RGB色彩模式是工业界的一种颜色标准，是通过对红(R)、绿(G)、蓝(B)三个颜色通道的变化以及它们相互之间的叠加来得到各式各样的颜色的，是目前运用最广的颜色系统之一。YUV是一种颜色编码方法，Y表示亮度，U表示色度,V表示浓度。
具体的，通过本地源视频数据写入控制模块读取WR_ADDR,WR_FRAME_NUM，RSL三个寄存器中的信息，得到一组存储空间地址信息，将对应的待存储视频数据存储到该地址空间下，例如，读取的一组存储空间地址信息为WR_ADDR寄存器的值为0x1000_0000，WR_FRAME_NUM的值为2，即要在DDR上以0x1000_000为起始地址的空间中写入2帧的图像信息。所述分辨率用于计算写入目标DDR视频的帧数，比如以640x480分辨率为例，在本地源视频数据写入控制模块对写入目标DDR的数据进行计数wr_cnt，当wr_cnt＝640x480x2时，表示写入了两帧的源视频数据。在这两帧视频存储结束之后，本地CPU又可以根据接下来需要存储的待存储视频信息以及目标DDR占用情况向所述目标DDR再次发出存储空间申请请求。直到待存储源视频数据存储完毕或目标DDR存储空间不足。
这样可以根据DDR空间的使用情况，灵活的进行存储空间申请，然后下发空间地址至本地源视频数据写入控制模块，以供数据存储使用，可以最大限度的提高DDR使用效率。同时可以在SOC系统关闭视频功能时，不申请DDR空间，将全部的DDR空间用于SOC其他的功能，提升了SOC系统的性能。
在通过本地CPU向所述目标DDR发送存储空间申请请求之前，还包括：通过本地CPU从本地显卡中读取所述待存储视频数据的分辨率；或，通过本地CPU从本地分辨率检测模块中读取所述待存储视频数据的分辨率。具体的，就是如果显卡中有寄存器存储了待存储视频数据对应的分辨率，则本地CPU可以直接从所述显卡中读取到所述待存储视频数据对应的分辨率，此时便不需要分辨率检测模块，此时过程如图2中虚线所示。如果所述显卡中没有寄存器存储了待存储视频数据对应的分辨率，需要将显 卡源视频控制信息输入到分辨率检测模块，所述源视频控制信息包括Hs、Vs等行、场同步控制信息，以进行分辨率检测。
相应的，当所述待存储视频数据为压缩后视频数据时，通过本地CPU向所述目标DDR发送存储空间申请请求，其中，所述存储空间申请请求中申请的存储空间大小根据所述待存储视频数据的分辨率、所述待存储视频数据的帧数以及压缩模式配置确定。具体的，对于相同帧数以及相同分辨率的源视频数据来说，由于压缩模式配置不相同，压缩后视频数据所需要的存储空间大小也不相同，例如，对相同帧数以及相同分辨率的源视频数据来说，采用YUV420压缩模式配置的压缩后视频数据所需要的存储空间比采用YUV444压缩模式配置的压缩后视频数据所需要的存储空间小。因为对于YUV420压缩模式配置来说是每4个Y共用一组UV分量，对于YUV444压缩模式配置来说是每1个Y对应一组UV分量，其中，Y表示亮度，U表示色度,V表示浓度，所以对于YUV420压缩模式配置来说会舍弃一部分UV分量。
通过本地CPU将与所述存储空间申请请求对应的起始地址、所述待存储视频数据的帧数发送到本地压缩视频数据写入控制模块；通过本地压缩视频数据写入控制模块将所述待存储视频数据存储到所述起始地址对应的地址空间中。
在具体的实施过程中，因为视频是连续输出的，存储空间地址信息也是连续下发的，故可以在本地压缩视频数据写入控制模块内部有2个FIFO：WR_ADDR_FIFO、WR_FRAME_NUM_FIFO，分别存储起始地址、存储的帧数。然后本地压缩视频数据写入控制模块依次读WR_ADDR_FIFO、WR_FRAME_NUM_FIFO，便可以得到一组存储空间信息，若用寄存器WR_ADDR,WR_FRAME_NUL表示，则第一个寄存器WR_ADDR为要写入的DDR的起始地址，第二个寄存器WR_FRAME_NUM为以WR_ADDR为起始地址的DDR空间中要写入的视频图像帧数。
在将所述压缩后视频数据存储到目标DDR的过程中，可以先读取出一组存储空间地址信息，再将对应的压缩后视频数据存储到这组存储空间地址信息下，例如读取的一组存储空间地址信息为：WR_ADDR寄存器的 值为0x7000_0000，WR_FRAME_NUM的值为3，即要在以0x7000_000为起始地址的存储空间中，写入3帧的压缩图像。在压缩图像下写入的过程中，该模块要利用压缩图像携带的帧头帧尾信息，计算已写入的图像帧数，比如JPEG格式一帧图像的帧头为0xFFD8，帧尾为0xFFD9，则检测到第三个帧尾0xFFD9时，停止写入。在这3帧视频存储结束之后，本地CPU又可以根据接下来需要存储的待存储视频信息以及目标DDR占用情况向所述目标DDR再次发出存储空间申请请求。直到待存储源视频数据存储完毕或目标DDR存储空间不足。
在将压缩后视频数据存储到目标DDR之前，还包括：从目标DDR中读取出源视频数据，并对所述源视频数据进行压缩。具体的，就是地址产生模块生成源视频数据读取地址，再由压缩IP根据所述源视频数据读取地址从所述目标DDR中读取出源视频数据，并进行压缩，将压缩后视频数据输入到所述本地压缩视频数据写入控制模块。
地址产生模块生成源视频数据读取地址的过程，包括：利用获取到的源视频数据存储的存储空间地址信息、分辨率以及压缩模式配置生成源视频数据读取地址。具体的，在地址产生模块内部设置3个FIFO：WR_ADDR_FIFO、WR_FRAME_NUM_FIFO、RSL_FIFO，分别存储起始地址、存储的帧数、分辨率。依次读取3个队列得到一组信息，在得到一帧图像的起始地址后，根据压缩模式配置，生成源视频数据读取地址。其中，压缩模式配置包括图4所示的YUV420以及YUV444两种，YUV420就是先读取16×16的Y，在再读取8×8的U，然后再读取8×8的V，然后再开始重复读取16×16的Y的步骤，YUV444就是先读取8×8的Y，在再读取8×8的U，然后再读取8×8的V，然后再开始重复读取8×8的Y的步骤。WR_ADDR_FIFO中只能读到第一帧的起始地址，如果当前地址存放的连续的多帧，则第2及以后帧的起始地址，要根据分辨率在该模块中进行计算，以生成源视频数据读取地址。例如：第2帧的起始地址为WR_ADDR+RSL_L*RSL_W，其中，RSL_L、RSL_W分别是分辨率的行和列信息，比如RSL_L＝640，RSL_W＝480。
步骤S25：若接收到视频功能关闭指令，则关闭本地视频功能。
在实际应用中，如果接收到视频功能关闭指令，则关闭本地视频功能。
步骤S26：停止向所述目标DDR申请存储空间，以便本地调用所述目标DDR以支持正处于运行状态的应用程序。
在关闭所述本地视频功能之后，便可以停止向所述目标DDR申请存储空间，以便本地调用所述目标DDR以支持正处于运行状态的应用程序。以保证本地运行的其他功能正常，提高SOC系统的性能。
参见图5所示，本申请实施例公开了一种视频存储装置，应用于SOC系统，包括：
请求发送模块11，用于根据待存储视频信息和目标DDR占用信息，向所述目标DDR发送存储空间申请请求；
信息接收模块12，用于接收所述目标DDR根据所述存储空间申请请求发送的存储空间分配响应；
数据存储模块13，用于将所述待存储视频信息对应的待存储视频数据存储到所述目标DDR中与所述存储空间申请请求对应的地址空间下。
可见，本申请先根据待存储视频信息和目标DDR占用信息，向所述目标DDR发送存储空间申请请求，并接收所述目标DDR根据所述存储空间申请请求发送的存储空间分配响应，然后将所述待存储视频信息对应的待存储视频数据存储到所述目标DDR中与所述存储空间申请请求对应的地址空间下。本申请中在视频存储的过程中，先根据待存储视频信息以及待写入DDR的占用情况进行存储空间的申请，再将待存储视频存储到申请的空间中，这样可以避免存储空间的浪费，且在不需要进行视频存储时，SOC系统上的存储资源便可以用于支持其他功能的运行，以保证系统上其他功能的正常运行，且提高了SOC系统的性能。
进一步的，参见图6所示，本申请实施例还公开了一种SOC系统，包括：处理器21和存储器22。
其中，所述存储器22，用于存储计算机程序；所述处理器21，用于执行所述计算机程序，以实现前述实施例中公开的视频存储方法。
其中，关于上述视频存储方法的具体过程可以参考前述实施例中公开的相应内容，在此不再进行赘述。
进一步的，本申请实施例还公开了一种计算机可读存储介质，用于保存计算机程序，其中，所述计算机程序被处理器执行时实现前述任一实施例中公开的视频存储方法。
其中，关于上述视频存储方法的具体过程可以参考前述实施例中公开的相应内容，在此不再进行赘述。
本说明书中各个实施例采用递进的方式描述，每个实施例重点说明的都是与其它实施例的不同之处，各个实施例之间相同或相似部分互相参见即可。对于实施例公开的装置而言，由于其与实施例公开的方法相对应，所以描述的比较简单，相关之处参见方法部分说明即可。
结合本文中所公开的实施例描述的方法或算法的步骤可以直接用硬件、处理器执行的软件模块，或者二者的结合来实施。软件模块可以置于随机存储器(RAM)、内存、只读存储器(ROM)、电可编程ROM、电可擦除可编程ROM、寄存器、硬盘、可移动磁盘、CD-ROM、或技术领域内所公知的任意其它形式的存储介质中。
最后，还需要说明的是，在本文中，诸如第一和第二之类的关系术语仅仅用来将一个实体或者操作与另一个实体或者操作区分开来，而不一定要求或者暗示这些实体或操作之间存在任何这种实际的关系或者顺序。而且，术语“包括”、“包含”或者其任何其他变体意在涵盖非排他性的包含，从而使得一系列包含其他要素的过程、方法、物品或者设备不仅包括那些要素，而且还包括没有明确列出的其他要素，或者是还包括为这种过程、方法、物品或者设备所固有的要素。在没有更多限制的情况下，由语句“包括一个……”限定的要素，并不排除在包括所述要素的过程、方法、物品或者设备中还存在另外的相同要素。
以上对本申请所提供的一种视频存储方法、装置、SOC系统、介质进行了详细介绍，本文中应用了具体个例对本申请的原理及实施方式进行了 阐述，以上实施例的说明只是用于帮助理解本申请的方法及其核心思想；同时，对于本领域的一般技术人员，依据本申请的思想，在具体实施方式及应用范围上均会有改变之处，综上所述，本说明书内容不应理解为对本申请的限制。

Claims (10)

  1. 一种视频存储方法，其特征在于，应用于SOC系统，包括：
    根据待存储视频信息和目标DDR占用信息，向所述目标DDR发送存储空间申请请求；
    接收所述目标DDR根据所述存储空间申请请求发送的存储空间分配响应；
    将所述待存储视频信息对应的待存储视频数据存储到所述目标DDR中与所述存储空间申请请求对应的地址空间下。
  2. 根据权利要求1所述的视频存储方法，其特征在于，所述根据待存储视频信息和目标DDR占用信息，向所述目标DDR发送存储空间申请请求，包括：
    当所述待存储视频数据为源视频数据时，根据所述待存储视频的分辨率、所述待存储视频的帧数以及目标DDR占用信息，向所述目标DDR发送存储空间申请请求；
    当所述待存储视频数据为压缩后视频数据时，根据所述待存储视频的分辨率、所述待存储视频的帧数、压缩模式配置以及目标DDR占用信息，向所述目标DDR发送存储空间申请请求。
  3. 根据权利要求2所述的视频存储方法，其特征在于，所述向所述目标DDR发送存储空间申请请求，包括：
    当所述待存储视频数据为源视频数据时，通过本地CPU向所述目标DDR发送存储空间申请请求，其中，所述存储空间申请请求中申请的存储空间大小根据所述待存储视频数据的分辨率和帧数确定；
    相应地，所述将所述待存储视频信息对应的待存储视频数据存储到所述目标DDR中与所述存储空间申请请求对应的地址空间下，包括：
    通过本地CPU将与所述存储空间申请请求对应的起始地址、所述待存储视频数据的帧数以及所述待存储视频数据的分辨率发送到本地源视频数据写入控制模块；
    通过本地源视频数据写入控制模块将所述待存储视频数据存储到所述起始地址对应的地址空间中。
  4. 根据权利要求2所述的视频存储方法，其特征在于，所述向所述目标DDR发送存储空间申请请求，包括：
    当所述待存储视频数据为压缩后视频数据时，通过本地CPU向所述目标DDR发送存储空间申请请求，其中，所述存储空间申请请求中申请的存储空间大小根据所述待存储视频数据的分辨率、所述待存储视频数据的帧数以及压缩模式配置确定；
    相应地，所述将所述待存储视频信息对应的待存储视频数据存储到所述目标DDR中与所述存储空间申请请求对应的地址空间下，包括：
    通过本地CPU将与所述存储空间申请请求对应的起始地址、所述待存储视频数据的帧数发送到本地压缩视频数据写入控制模块；
    通过本地压缩视频数据写入控制模块将所述待存储视频数据存储到所述起始地址对应的地址空间中。
  5. 根据权利要求3所述的视频存储方法，其特征在于，所述通过本地CPU向所述目标DDR发送存储空间申请请求之前，还包括：
    通过本地CPU从本地显卡中读取所述待存储视频数据的分辨率；
    或，通过本地CPU从本地分辨率检测模块中读取所述待存储视频数据的分辨率。
  6. 根据权利要求3所述的视频存储方法，其特征在于，所述通过本地源视频数据写入控制模块将所述待存储视频数据存储到所述起始地址对应的地址空间中之前，还包括：
    通过本地色彩空间转换模块对所述待存储视频数据进行色彩空间转换，得到转换后待存储视频数据。
  7. 根据权利要求1至6任一项所述的视频存储方法，其特征在于，还包括：
    若接收到视频功能关闭指令，则关闭本地视频功能；
    停止向所述目标DDR申请存储空间，以便本地调用所述目标DDR以支持正处于运行状态的应用程序。
  8. 一种视频存储装置，其特征在于，应用于SOC系统，包括：
    请求发送模块，用于根据待存储视频信息和目标DDR占用信息，向 所述目标DDR发送存储空间申请请求；
    信息接收模块，用于接收所述目标DDR根据所述存储空间申请请求发送的存储空间分配响应；
    数据存储模块，用于将所述待存储视频信息对应的待存储视频数据存储到所述目标DDR中与所述存储空间申请请求对应的地址空间下。
  9. 一种SOC系统，其特征在于，包括：
    存储器和处理器；
    其中，所述存储器，用于存储计算机程序；
    所述处理器，用于执行所述计算机程序，以实现权利要求1至7任一项所述的视频存储方法。
  10. 一种计算机可读存储介质，其特征在于，用于保存计算机程序，其中，所述计算机程序被处理器执行时实现如权利要求1至7任一项所述的视频存储方法。
PCT/CN2021/077020 2020-06-12 2021-02-20 一种视频存储方法、装置、soc系统、介质 WO2021248936A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US18/008,381 US20230199143A1 (en) 2020-06-12 2021-02-20 Video storage method and apparatus, and soc system and medium

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202010540164.9A CN111741246B (zh) 2020-06-12 2020-06-12 一种视频存储方法、装置、soc系统、介质
CN202010540164.9 2020-06-12

Publications (1)

Publication Number Publication Date
WO2021248936A1 true WO2021248936A1 (zh) 2021-12-16

Family

ID=72649162

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2021/077020 WO2021248936A1 (zh) 2020-06-12 2021-02-20 一种视频存储方法、装置、soc系统、介质

Country Status (3)

Country Link
US (1) US20230199143A1 (zh)
CN (1) CN111741246B (zh)
WO (1) WO2021248936A1 (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115297094A (zh) * 2022-10-08 2022-11-04 苏州浪潮智能科技有限公司 视频传输控制方法、装置、设备及计算机可读存储介质

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111741246B (zh) * 2020-06-12 2022-07-05 浪潮(北京)电子信息产业有限公司 一种视频存储方法、装置、soc系统、介质
CN113328998B (zh) * 2021-05-14 2023-02-21 维沃移动通信有限公司 影像数据传输的方法和电子设备
CN115190175B (zh) * 2022-07-18 2023-07-14 浪潮(北京)电子信息产业有限公司 连接处理方法、系统、电子设备、服务器及可读存储介质
CN117082281B (zh) * 2023-10-17 2024-02-23 苏州元脑智能科技有限公司 音视频数据同步处理方法、系统、设备及介质

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101241469A (zh) * 2007-02-05 2008-08-13 力博特公司 一种在嵌入式系统中存储、读取数据的方法及装置
US20120113150A1 (en) * 2010-11-04 2012-05-10 Electronics And Telecommunications Research Institute Multimedia communication apparatus and processing method for group media communication
CN103136105A (zh) * 2011-11-28 2013-06-05 广东新岸线计算机系统芯片有限公司 一种内存管理方法、嵌入式系统和视频数据处理系统
CN105245912A (zh) * 2015-10-21 2016-01-13 东方网力科技股份有限公司 一种缓存视频数据及读取视频数据的方法及装置
CN110555890A (zh) * 2018-05-30 2019-12-10 珠海全志科技股份有限公司 一种内存管理方法及系统
CN111741246A (zh) * 2020-06-12 2020-10-02 浪潮(北京)电子信息产业有限公司 一种视频存储方法、装置、soc系统、介质

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4435251B2 (ja) * 2008-08-29 2010-03-17 株式会社東芝 映像表示装置、映像再生装置、映像表示方法および映像再生方法
US9019291B2 (en) * 2013-02-25 2015-04-28 Apple Inc. Multiple quality of service (QoS) thresholds or clock gating thresholds based on memory stress level
US20170255565A1 (en) * 2016-03-02 2017-09-07 Intel Corporation Method and apparatus for providing a contiguously addressable memory region by remapping an address space

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101241469A (zh) * 2007-02-05 2008-08-13 力博特公司 一种在嵌入式系统中存储、读取数据的方法及装置
US20120113150A1 (en) * 2010-11-04 2012-05-10 Electronics And Telecommunications Research Institute Multimedia communication apparatus and processing method for group media communication
CN103136105A (zh) * 2011-11-28 2013-06-05 广东新岸线计算机系统芯片有限公司 一种内存管理方法、嵌入式系统和视频数据处理系统
CN105245912A (zh) * 2015-10-21 2016-01-13 东方网力科技股份有限公司 一种缓存视频数据及读取视频数据的方法及装置
CN110555890A (zh) * 2018-05-30 2019-12-10 珠海全志科技股份有限公司 一种内存管理方法及系统
CN111741246A (zh) * 2020-06-12 2020-10-02 浪潮(北京)电子信息产业有限公司 一种视频存储方法、装置、soc系统、介质

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115297094A (zh) * 2022-10-08 2022-11-04 苏州浪潮智能科技有限公司 视频传输控制方法、装置、设备及计算机可读存储介质
CN115297094B (zh) * 2022-10-08 2023-02-28 苏州浪潮智能科技有限公司 视频传输控制方法、装置、设备及计算机可读存储介质

Also Published As

Publication number Publication date
CN111741246A (zh) 2020-10-02
US20230199143A1 (en) 2023-06-22
CN111741246B (zh) 2022-07-05

Similar Documents

Publication Publication Date Title
WO2021248936A1 (zh) 一种视频存储方法、装置、soc系统、介质
US9538087B2 (en) Image processing device with multiple image signal processors and image processing method
WO2016011886A1 (zh) 对图像进行解码的方法及装置
TWI524176B (zh) 用於顯示功率管理之方法及裝置
US9244648B2 (en) Multi-processor video processing system and video image synchronous transmission and display method therein
TW200427312A (en) Method and apparatus for pattern RAM sharing color LUT
CN114501024B (zh) 一种视频压缩系统、方法、计算机可读存储介质及服务器
WO2024016520A1 (zh) 一种视频压缩方法、系统、设备及计算机非易失性可读存储介质
WO2023197507A1 (zh) 视频数据处理方法、系统、装置及计算机可读存储介质
CN111683251A (zh) 一种视频数据存储方法、装置和计算机可读存储介质
CN115209145A (zh) 一种视频压缩方法、系统、装置及可读存储介质
WO2024074012A1 (zh) 视频传输控制方法、装置、设备及非易失性可读存储介质
TWI230013B (en) System and method for processing memory with YCbCr 4:2:0 planar video data format
WO2023045168A1 (zh) 一种图像处理方法、装置及相关组件
CN111193916B (zh) 运算方法
CN108563519B (zh) 基于gpgpu中的2d桌面块拷贝填充操作的实现
US7103702B2 (en) Memory device
CN102572207A (zh) 一种适于jpeg图像的颜色空间转换方法
JPH0447376A (ja) 情報処理装置および情報処理方法
Gong et al. Design of high-speed real-time sensor image processing based on FPGA and DDR3
JP3238692B2 (ja) ソフトウェア／ハードウェア複合方式を用いたデータ処理装置及び方法
CN114554126B (zh) 一种基板管理控制芯片、视频数据传输方法及服务器
US20110026603A1 (en) Method and apparatus of using system memory for 3d comb filtering for video decoding
CN103680402A (zh) 一种基于leon3软核cpu的异步全彩led显示控制系统
JP2001236191A (ja) 印刷装置及び該印刷装置を備えた画像処理装置

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 21822338

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 21822338

Country of ref document: EP

Kind code of ref document: A1