WO2023197399A1 - 一种存储器的测试方法、装置及存储器系统 - Google Patents

一种存储器的测试方法、装置及存储器系统 Download PDF

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Publication number
WO2023197399A1
WO2023197399A1 PCT/CN2022/093270 CN2022093270W WO2023197399A1 WO 2023197399 A1 WO2023197399 A1 WO 2023197399A1 CN 2022093270 W CN2022093270 W CN 2022093270W WO 2023197399 A1 WO2023197399 A1 WO 2023197399A1
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write
memory
storage unit
data
noise
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French (fr)
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周坤
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Changxin Memory Technologies Inc
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Changxin Memory Technologies Inc
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/50—Marginal testing, e.g. race, voltage or current testing
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/50—Marginal testing, e.g. race, voltage or current testing
    • G11C2029/5004—Voltage

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  • the present disclosure relates to the field of semiconductor technology, and in particular, to a memory testing method, device and memory system.
  • DRAM Dynamic Random Access Memory
  • embodiments of the present disclosure provide a memory testing method, device and memory system to solve at least one problem existing in the prior art.
  • an embodiment of the present disclosure provides a memory testing method, which method includes:
  • the write operation includes writing test data into the storage unit
  • the noise in the noisy environment includes at least one of the following: power supply voltage noise, write recovery time noise, and memory cell leakage noise.
  • performing write operations and read operations on the memory unit in a noisy environment includes:
  • performing write operations and read operations on the memory unit in a noisy environment includes:
  • performing write operations and read operations on the memory unit in a noisy environment includes:
  • Adjust the waiting time between the write operation and the read operation from a third duration to a fourth duration; the third duration is less than the fourth duration;
  • performing a write operation on the storage unit includes:
  • a second writing operation is performed on the storage unit, and the test data in the preset data structure is written into the storage unit.
  • the write recovery time corresponding to the second write operation is less than the write recovery time corresponding to the first write operation.
  • the background data is first data;
  • the test data in the preset data structure includes first data and second data, and the storage unit corresponding to the second data is target storage. unit.
  • the memory is a dynamic random access memory.
  • an embodiment of the present disclosure provides a memory testing device, which includes:
  • a data processing module configured to perform write operations and read operations on the storage unit in a noisy environment; the write operation includes writing test data into the storage unit;
  • a comparison module configured to compare the read result obtained by performing the read operation with the test data to obtain the signal margin test result of the memory unit under the influence of noise
  • the noise in the noisy environment includes at least one of the following: power supply voltage noise, write recovery time noise, and memory cell leakage noise.
  • the device further includes:
  • a voltage adjustment module configured to adjust the power supply voltage from a first voltage to a second voltage; the first voltage is greater than the second voltage;
  • the data processing module is specifically configured to perform write operations and read operations on the memory unit in the power supply voltage noise environment.
  • the device further includes:
  • a write recovery time adjustment module configured to adjust the write recovery time from a first duration to a second duration; the first duration is greater than the second duration;
  • the data processing module is specifically configured to perform write operations and read operations on the storage unit in the write recovery time noise environment.
  • the device further includes:
  • a waiting time adjustment module configured to adjust the waiting time between the write operation and the read operation from a third duration to a fourth duration; the third duration is less than the fourth duration;
  • the data processing module is specifically configured to perform writing operations and reading operations on the storage unit in the leakage noise environment of the storage unit.
  • the data processing module includes:
  • a first writing module configured to perform a first writing operation on the storage module and write background data into the storage unit
  • the second writing module is configured to perform a second writing operation on the storage unit according to the preset data structure, and write the test data in the preset data structure into the storage unit.
  • the write recovery time of the second write operation is less than the write recovery time of the first write operation.
  • the background data is first data;
  • the test data in the preset data structure includes first data and second data, and the storage unit corresponding to the second data is target storage. unit.
  • an embodiment of the present disclosure provides a memory system, including: a controller and a plurality of memories coupled to the controller; wherein,
  • the controller is configured to execute the memory testing method described in the first aspect.
  • a memory testing method includes: performing a write operation and a read operation on a memory unit in a noisy environment; the write operation includes writing test data into the storage unit; compare the read result obtained by performing the read operation with the test data to obtain the signal margin test result of the storage unit under the influence of noise; the noise in the noisy environment Including at least one of the following: power supply voltage noise, write recovery time noise, memory cell leakage noise.
  • the present disclosure can effectively improve the test coverage by performing signal margin testing on memory cells in noisy environments such as power supply voltage noise, write recovery time noise, memory cell leakage noise, etc., making it easier to detect memory cells with potential insufficient signal margin defects. are detected, improving the accuracy of memory performance evaluation.
  • Figure 1 is a schematic structural diagram of a memory cell array in a memory provided by an embodiment of the present disclosure
  • Figure 2 is a schematic diagram of the composition and structure of memory cells in a memory cell array provided by an embodiment of the present disclosure
  • Figure 3 is a schematic diagram of a circuit structure during a reading operation according to an embodiment of the present disclosure
  • Figure 4 is a timing diagram of a read operation according to an embodiment of the present disclosure.
  • Figure 5 is a schematic flow chart of the implementation of a memory testing method provided by an embodiment of the present disclosure
  • Figure 6 is a curve of the number of failed bits changing with write recovery time in a noisy environment of write recovery time provided by an embodiment of the present disclosure
  • Figure 7 is a curve of the number of failed bits changing with the waiting time between write operations and read operations in a memory cell leakage noise environment provided by an embodiment of the present disclosure
  • Figures 8a-8c show three different preset data structures provided by embodiments of the present disclosure.
  • Figure 9 is a test flow chart of a memory provided by a specific example of an embodiment of the present disclosure.
  • Figure 10 is a schematic structural diagram of a memory testing device provided by an embodiment of the present disclosure.
  • FIG. 11 is a schematic structural diagram of a memory system provided by an embodiment of the present disclosure.
  • spatial relational terms such as “under”, “under”, “under”, “under”, “on”, “above”, etc., are used here It may be used for convenience of description to describe the relationship of one element or feature to other elements or features shown in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, then elements or features described as “below” or “under” or “beneath” other elements or features would then be oriented “above” the other elements or features. Thus, the exemplary terms “below” and “under” may include both upper and lower orientations. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially descriptive terms used herein interpreted accordingly.
  • the storage device involved in the embodiment of the present disclosure may include a dynamic random access memory (Dynamic Random Access Memory, DRAM), which is particularly suitable for double data rate synchronous dynamic random access memory using DDR4 memory specifications and DDR5 memory specifications.
  • DRAM Dynamic Random Access Memory
  • Low-power double data rate synchronous dynamic random access memory with LPDDR5 memory specification is particularly suitable for double data rate synchronous dynamic random access memory using DDR4 memory specifications and DDR5 memory specifications.
  • LPDDR5 memory specification Low-power double data rate synchronous dynamic random access memory with LPDDR5 memory specification.
  • FIG. 1 is a schematic structural diagram of a memory cell array in a memory provided by an embodiment of the present disclosure.
  • the memory cell array includes a plurality of word lines (WL shown in FIG. 1), a plurality of bit line pairs (BL/BLB shown in FIG. 1), a plurality of memory cells (shown as " ⁇ " in Figure 1), and a plurality of sense amplifiers (shown as "SA” in Figure 1) connected to the bit line pairs.
  • WL word lines
  • BL/BLB shown in FIG. 1 bit line pairs
  • SA sense amplifiers
  • FIG. 1 is a column select signal (CSL) that controls bit line activation
  • WE write enable signal
  • LIO multiple local input and output lines
  • FIG. 2 is a schematic structural diagram of a memory cell in a memory cell array according to an embodiment of the present disclosure.
  • each memory cell in DRAM usually includes a capacitor (Storage Capacitor, SC) and a transistor (Access Transistor, AT).
  • the gate of the transistor AT is connected to the word line WL, the drain is connected to the bit line, and the source pole is connected to the capacitor SC.
  • the voltage signal on the word line WL can control the opening or closing of the transistor AT, and then read the data information stored in the capacitor SC through the bit line BL, or write the data information into the capacitor SC through the bit line BL for storage.
  • Figure 3 is a schematic diagram of the circuit structure during the reading operation
  • Figure 4 is a timing diagram of the reading operation.
  • the sense amplifier 100 includes four transistors, namely a first transistor 101 , a second transistor 102 , a third transistor 103 and a fourth transistor 104 , wherein both the first transistor 101 and the third transistor 103 are PMOS. (Positive channel Metal Oxide Semiconductor, P-type metal oxide semiconductor) transistor, the second transistor 102 and the fourth transistor 104 are both NMOS (Negative channel Metal Oxide Semiconductor, N-type metal oxide semiconductor) transistors.
  • the gate of the first transistor 101 is connected to the reference bit line BLB, and the drain and source of the first transistor 101 are connected to the bit line BL and the P-type sense amplifier control signal (Sense-Amplifier P-Fet Control, SAP) respectively;
  • the first The gate of the third transistor 103 is connected to the bit line BL, and the drain and source of the third transistor 103 are connected to the reference bit line BLB and SAP respectively;
  • the gate of the second transistor 102 is connected to the reference bit line BLB, and the second transistor 102
  • the drain and source of are connected to the bit line BL and the N-type sense amplifier control signal (Sense-Amplifier N-Fet Control, SAN) respectively;
  • the gate of the fourth transistor 104 is connected to the bit line BL, and the gate of the fourth transistor 104 The drain and source are connected to the reference bit lines BLB and SAN respectively.
  • the precharge part 120 includes a fifth transistor 105 , a sixth transistor 106 and a seventh transistor 107 .
  • the drain and source of the fifth transistor 105 are respectively connected to the bit line BL and the bit line precharge voltage VBLP (Voltage of Bit Line Precharge), and the drain and source of the sixth transistor 106 are respectively connected to the reference bit line BLB.
  • VBLP Voltage of Bit Line Precharge
  • the drain and source of the seventh transistor 107 are respectively connected to the bit line BL and the reference bit line BLB, the gate of the fifth transistor 105, the gate of the sixth transistor 106 and the seventh transistor 107
  • the gates are connected to the precharge signal line, and the precharge signal line is connected to the Voltage Equalizer (VEQ), so that when the precharge signal line is turned on, the bit line BL and the reference bit line BLB are charged in place.
  • VEQ Voltage Equalizer
  • the voltage applied on one plate of the capacitor SC in the storage unit 110 is always half of the power voltage V CC , that is, V CC /2.
  • V CC power voltage
  • the amount of charge stored in the capacitor SC is +Vcc/2C, where C is the capacitance of the capacitor SC; when the data information stored in the capacitor SC is "0", the voltage on the other substrate is 0, so The amount of charge stored in capacitor SC is -Vcc/2C.
  • FIG 4 is a timing diagram of a read operation, in which the horizontal axis represents time and the vertical axis represents signal level.
  • a read operation includes four stages: Precharge stage Q1, Charge Sharing stage Q2, Sensing stage Q3 and Restore stage Q4.
  • the precharge phase Q1 see Figure 3 and Figure 4, after the precharge command (PRE), WL is turned off, and the sense amplifier is turned off after a period of time.
  • the precharge phase Q1 After the precharge phase Q1, the voltages on BL and BLB have stabilized at Vref.
  • the precharge signal line is closed, and the WL signal is controlled after the activation command (Row-Active Command, ACT) and a fixed time T1 delay. Turn on WL, turn on the transistor AT in the memory unit 110, and the positive charge stored in the capacitor will flow to BL, and then the voltage of BL will be raised to Vref+, and then the sensing stage Q3 will be entered.
  • the fourth transistor 104 Since the voltage of BL is pulled up to Vref+ during the acquisition phase Q2, the fourth transistor 104 will be more conductive than the second transistor 102, and the first transistor 101 will be more conductive than the third transistor 103.
  • the voltage on SAN will be set to a logic 0 voltage
  • the voltage on the SAP will be set to a logic 1 voltage, that is, the high level V CC .
  • the fourth transistor 104 Since the fourth transistor 104 will be more conductive than the second transistor 102, the voltage on the BLB will be pulled to the logic 0 voltage by the SAN faster, which is Gnd (representing the ground voltage, which can also be recorded as Vss). In the same way, The voltage on BL will also be pulled to the logic 1 voltage by SAP faster. Then the first transistor 101 and the fourth transistor 104 enter the on state, and the third transistor 103 and the second transistor 102 enter the off state. Finally, the voltages of both BL and BLB enter a stable state, correctly presenting the information stored in the
  • BL is at a stable logic 1 voltage V CC , and at this time BL will charge the capacitor. After a certain amount of time, the capacitor's charge is restored to its state before the read operation.
  • the column selection transistor 141 is turned on by controlling the column selection signal CSL.
  • the information stored in the capacitor SC is output from the sense amplifier to the local input and output line LIO, and the outside world can read the specific information.
  • Write Part of the process of the write operation (Write) is the same as the read operation.
  • the write recovery stage Q5 the write enable transistor (not shown in the figure) is turned on by controlling the write enable signal WE.
  • BL will be pulled to the logic 1 level
  • BLB will be pulled to the logic 0 level.
  • the transistor AT connected to the capacitor SC can be turned off by controlling WL, and the operation of writing 1 is completed.
  • C BL is the equivalent capacitance generated by BL
  • C SC is the capacitance of capacitor SC.
  • FIG. 5 is a schematic flowchart of the implementation of a memory testing method provided by an embodiment of the present disclosure. As shown in Figure 5, the memory testing method includes the following steps:
  • Step 501 Perform write operations and read operations on the storage unit in a noisy environment; the write operation includes writing test data into the storage unit; the noise in the noisy environment includes at least one of the following: power supply voltage noise , write recovery time noise, memory cell leakage noise.
  • performing a write operation and a read operation on a memory cell in a noisy environment includes: adjusting a power supply voltage from a first voltage to a second voltage; the first voltage being greater than the second voltage; Write operations and read operations are performed on the memory cell in the power supply voltage noise environment.
  • the reduction of the power supply voltage of the memory will directly lead to the reduction of the power supply voltage V CC of the memory unit, and the theoretical signal margin SM of the memory unit is positively related to V CC . Therefore, in the signal margin test, The impact of power supply voltage noise on the signal margin of the memory cell can be simulated by reducing the power supply voltage of the memory, thereby making it easier to detect memory cells with potential insufficient signal margin defects.
  • the first voltage is the power supply voltage of DRAM specified in the JEDEC standard, and the second voltage is lower than the first voltage.
  • the second voltage can be 1.62V; when the first voltage When the voltage is 1.1V, the second voltage can be 0.99V.
  • performing write operations and read operations on the memory unit in a noisy environment includes: adjusting the write recovery time from a first duration to a second duration; the first duration is greater than the second duration; Write operations and read operations are performed on the memory cell in the write recovery time noise environment.
  • the write recovery time (Time of Write Recovery, tWR) is the time period between the generation of the write enable signal WE and the generation of the precharge command PRE. If the write recovery time is too short, the next precharge operation may be started before the previous write operation is completed. That is, WL is turned off before the voltage on the capacitor SC reaches +Vcc. This situation will also have a negative impact on the memory cell. Actual signal margin is affected. Therefore, in the signal margin test, the write recovery time noise can be simulated by shortening the write recovery time to simulate the impact of the write recovery time noise on the signal margin of the memory cell, thereby making the memory cell with potential insufficient signal margin defects more reliable. hardly detected.
  • the testing method further includes: determining the second duration.
  • the process of determining the second duration may be to perform write and read tests of the same test data on the storage unit under different write recovery times, and calculate the number of failed bits in each write and read test. Count, FBC).
  • the different write recovery times in the determination process are multiple write recovery times obtained by decreasing from the first duration, and the first duration may be the write recovery time of DRAM specified in the JEDEC standard.
  • the change curve of the number of failed bits FBC with the write recovery time tWR obtained by writing and reading tests in a noisy environment is shown in Figure 6.
  • the corresponding time t1 is the second duration, which is also the shortest write recovery time for the storage unit to correctly write data. Setting the write recovery time to the shortest write recovery time t1 that allows the storage unit to correctly write data can minimize the actual signal margin of the storage unit and improve the coverage of the signal margin test.
  • the number of failed bits FBC in the memory can be determined by counting the number of memory cells in which written data and read data are different, or can be determined in other ways, which is not limited in the embodiments of the present disclosure.
  • the preset allowable failure number FBC* can be set according to the actual situation.
  • the preset allowable failure number is set to any number from one thousandth to one ten thousandth of the total number of storage units. This embodiment of the present disclosure does not specifically limit this. .
  • performing a write operation and a read operation on a memory unit in a noisy environment includes: adjusting a waiting time between the write operation and the read operation from a third duration to a fourth duration. ; The third duration is less than the fourth duration; performing write operations and read operations on the storage unit in the leakage noise environment of the storage unit.
  • the memory cell will leak electricity.
  • the waiting time increases, the amount of charge stored on the capacitor gradually decreases, and the actual signal margin of the memory cell also gradually decreases.
  • the leakage reaches a certain level, the amount of charge stored on the capacitor is not enough to correctly identify the data, resulting in data loss. Therefore, the memory cell leakage noise in the actual situation can be simulated by increasing the waiting time between the write operation and the read operation, and the write operation and read operation are performed on the memory cell in the memory cell leakage noise environment.
  • the testing method further includes determining the fourth duration.
  • the process of determining the fourth duration may be to turn off the self-refresh function of the memory, perform writing and reading tests of the same test data on the storage unit under different waiting times, and calculate the failure bit in each writing and reading test.
  • the amount of yuan The change curve of the number of failed bits in the memory FBC with the waiting time in the memory cell leakage noise environment obtained through writing and reading tests is shown in Figure 7. As the waiting time increases, when the number of failed bits in the memory changes When the quantity FBC reaches the preset allowed failure quantity FBC*, the corresponding time t2 is the fourth duration, which is also the maximum data retention time of the storage unit.
  • the storage unit can fully leak electricity after the waiting time and still maintain the accuracy of the stored data, thereby creating the noise of leakage of the storage unit. environment, making it easier to detect memory cells with potential insufficient signal margin defects and improving the coverage of signal margin testing.
  • performing a write operation on a storage unit includes: performing a first write operation on the storage unit, writing background data into the storage unit; and writing the storage unit according to a preset data structure.
  • a second writing operation is performed to write the test data in the preset data structure into the storage unit.
  • the write recovery time corresponding to the second write operation is less than the write recovery time corresponding to the first write operation.
  • the write recovery time corresponding to the second write operation is the fourth duration.
  • the background data is first data; the test data in the preset data structure includes first data and second data, and the storage unit corresponding to the second data is a target storage unit.
  • the second data when the first data is 0, the second data is 1, and the storage unit corresponding to 1 is the target storage unit; when the first data is 1, the second data is 0, and the storage unit corresponding to 0 is the target storage unit. unit.
  • the preset data structure may be a checkerboard pattern with 1 and 0 alternately arranged (two preset data as shown in Figure 8a structure), a stripe pattern in which 1 and 0 are arranged alternately in rows (two preset data structures as shown in Figure 8b), a pattern in which the data on one BL is 0 (eight preset data structures as shown in Figure 8c data structure) or other patterns composed of arbitrary arrangements of 0s and 1s.
  • Each preset data structure includes test data corresponding to 8 word lines. Combined with the writing method of 8 word lines apart, this can maximize the test coverage.
  • the second write operation and the read operation are in burst length (Burst Length, BL) units.
  • the second write operation may be an X-FAST write operation.
  • the X-FAST write operation is a write operation mode in the X direction (row direction), that is, for the bit lines connected to the same bit line. All word lines, write a burst length of data on each word line in turn.
  • the read operation can be an X-FAST read operation.
  • the X-FAST read operation is an X-direction (row direction) read operation mode, that is, for all word lines connected to the same bit line, each word line is read in sequence. data in the storage unit.
  • the second write operation may be a Y-FAST write operation.
  • the Y-FAST write operation is a write operation mode in the Y direction (column direction), that is, before each write operation is performed, Turn on a word line, and after sequentially writing all the memory cells corresponding to this word line in units of burst length, close this word line; then turn on the next word line and sequentially write all the corresponding memory cells on this word line. storage unit.
  • the read operation can be a Y-FAST read operation.
  • the Y-FAST read operation is a Y-direction (column direction) read operation mode, that is, before each read operation is performed, a word line is opened, with a burst length of After the unit sequentially reads all the memory cells corresponding to this word line, it turns off this word line; then it turns on the next word line and sequentially reads all the memory cells corresponding to this word line.
  • the burst length refers to the number of memory cells involved when adjacent memory cells in the same word line continuously read/write data.
  • the burst length supported by DDR4 is 8 or 4 (that is, BL8 or BL4).
  • the bit width of DDR4 is 16 bit, 8 ⁇ 16bit data or 4 ⁇ 16bit data can be read/written at a time; the burst length supported by LPDDR4
  • the transmission length is 32 or 16 (i.e. BL32 or BL16).
  • the bit width of LPDDR4 is 16bit, 32 ⁇ 16bit data or 16 ⁇ 16bit data can be read/written each time.
  • Step 502 Compare the read result obtained by performing the read operation with the test data to obtain the signal margin test result of the memory unit under the influence of noise.
  • the signal margin test result of the memory unit when the read result obtained by performing the read operation on the memory unit is inconsistent with the test data, the signal margin test result of the memory unit is failed; when the read result obtained by performing the read operation on the memory unit When the result is consistent with the test data, the signal margin test result of the memory unit is passed.
  • the power supply voltage noise, write recovery time noise and memory cell leakage noise in actual situations are simulated by adjusting the power supply voltage, adjusting the write recovery time and adjusting the waiting time between the write operation and the read operation respectively. , so that memory cells with potential insufficient signal margin defects can be more easily detected during the test process, improving the coverage of signal margin testing.
  • this disclosure provides a specific example.
  • Figure 9 is a test flow chart of a memory provided by a specific example of an embodiment of the present disclosure. As shown in Figure 9, the test process includes the following steps:
  • Step 901 Set the noise environment
  • setting the noise environment includes: setting power supply voltage noise, setting write recovery time noise, and/or setting memory cell leakage noise.
  • Setting the power supply voltage noise includes reducing the power supply voltage to simulate the power supply voltage noise, here, the power supply voltage can be reduced to 1.62V or 0.99V;
  • setting the write recovery time noise includes reducing the write recovery time to simulate the write recovery time noise, here, write The recovery time can be reduced to the shortest write recovery time t1 that allows the storage unit to correctly write data;
  • setting the storage unit leakage noise includes increasing the waiting time between write operations and read operations to simulate the storage unit leakage noise, here, the waiting time It can be increased to the maximum data retention time t2 of the storage unit.
  • Step 902 Perform the first writing operation and write background data
  • the background data is written into all memory units by performing a first write operation on the memory units.
  • Step 903 Perform the second writing operation and write the test data according to the preset data structure
  • multiple different preset data structures are provided; for each of the multiple different preset data structures, test data is written to the storage unit sequentially through the second write operation. enter.
  • the first preset data structure is used in the first loop
  • the second preset data structure is used in the second loop, and so on, until all the preset data structures have been traversed, and so on through multiple different presets
  • the data structure can realize traversal of all storage units.
  • a second write operation is performed on the storage unit according to the preset data structure, and the test data in the preset data structure is written into the target storage unit.
  • the storage unit corresponding to 0 in the preset data structure is the target storage unit.
  • the write recovery time of the second write operation is the shortest write recovery time t1 that allows the storage unit to correctly write data.
  • the second write operation is an X-FAST write operation or a Y-FAST write operation, and the burst length is 8 bits, 16 bits or 32 bits.
  • Step 904 Perform the reading operation after the waiting time
  • the waiting time is the maximum data retention time t2 of the storage unit.
  • the read operation is an X-FAST read operation or a Y-FAST read operation.
  • Step 905 Compare the reading results and test data
  • the signal margin test result of the target memory cell can be obtained by comparing the read result and the test data. Switch to the next preset data structure and continue to execute step 903; if the preset data structure at this time is the last preset data structure, exit this test.
  • all storage units in the memory can be used as target storage units to complete a signal margin test. For example, when the preset data structure in the first cycle is the first preset data structure shown in Figure 8a, in the second cycle the preset data structure is changed to the second preset data structure shown in Figure 8a.
  • Step 906 Output the test results.
  • the signal margin test result of the target memory unit obtained by comparing the read result and the test data is output.
  • FIG. 10 is a schematic structural diagram of a memory testing device provided by an embodiment of the present disclosure. As shown in Figure 10, the memory Test device 1000 includes:
  • the data processing module 1001 is configured to perform write operations and read operations on the storage unit in a noisy environment; the write operation includes writing test data into the storage unit;
  • the comparison module 1002 is configured to compare the read result obtained by performing the read operation with the test data to obtain the signal margin test result of the memory unit under the influence of noise;
  • the noise in the noisy environment includes at least one of the following: power supply voltage noise, write recovery time noise, and memory cell leakage noise.
  • the device further includes:
  • the voltage adjustment module 1003 is configured to adjust the power supply voltage from a first voltage to a second voltage; the first voltage is greater than the second voltage;
  • the data processing module 1001 is specifically configured to perform write operations and read operations on the memory unit in the power supply voltage noise environment.
  • the device further includes:
  • the write recovery time adjustment module 1004 is configured to adjust the write recovery time from a first duration to a second duration; the first duration is greater than the second duration;
  • the data processing module 1001 is specifically configured to perform write operations and read operations on the storage unit in the write recovery time noise environment.
  • the device further includes:
  • the waiting time adjustment module 1005 is configured to adjust the waiting time between the write operation and the read operation from a third duration to a fourth duration; the third duration is less than the fourth duration;
  • the data processing module 1001 is specifically configured to perform write operations and read operations on the memory unit in the leakage noise environment of the memory unit.
  • the data processing module 1001 includes:
  • a first writing module (not shown in the figure) configured to perform a first writing operation on the storage module and write background data into the storage unit;
  • the second writing module (not shown in the figure) is configured to perform a second writing operation on the storage unit according to the preset data structure, and write the test data in the preset data structure into the storage unit. middle.
  • the write recovery time of the second write operation is less than the write recovery time of the first write operation.
  • the background data is first data; the test data in the preset data structure includes first data and second data, and the storage unit corresponding to the second data is a target storage unit.
  • An embodiment of the present disclosure also provides a memory system.
  • the memory system provided by the embodiment of the present disclosure includes a controller 1101 and a plurality of memories 1102 coupled to the controller; wherein,
  • the controller 1101 is configured to perform the aforementioned memory testing method.
  • the storage device is dynamic random access memory.
  • the memory of the dynamic random access memory complies with DDR2 memory specifications.
  • the memory of the dynamic random access memory complies with DDR3 memory specifications.
  • the memory of the dynamic random access memory complies with DDR4 memory specifications.
  • the memory of the dynamic random access memory complies with DDR5 memory specifications.
  • the memory of the dynamic random access memory complies with LPDDR4 memory specifications.
  • the memory of the dynamic random access memory complies with LPDDR5 memory specifications.
  • the present disclosure can effectively improve the test coverage by performing signal margin testing on memory cells in noisy environments such as power supply voltage noise, write recovery time noise, memory cell leakage noise, etc., making it easier to detect memory cells with potential insufficient signal margin defects. are detected, improving the accuracy of memory performance evaluation.

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  • For Increasing The Reliability Of Semiconductor Memories (AREA)

Abstract

公开了一种存储器的测试方法、装置及存储器系统，方法包括：在噪声环境下对存储单元执行写入操作和读取操作；写入操作包括将测试数据写入存储单元中（501）；将执行读取操作得到的读取结果和测试数据进行比较，得到存储单元在噪声影响下的信号裕度测试结果（502）；噪声环境中的噪声至少包括以下之一：电源电压噪声、写恢复时间噪声、存储单元漏电噪声。

Description

一种存储器的测试方法、装置及存储器系统
相关的交叉引用
本公开基于申请号为202210374029.0、申请日为2022年04月11日、发明名称为“一种存储器的测试方法、装置及存储器系统”的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此引入本公开作为参考。
技术领域
本公开涉及半导体技术领域，尤其涉及一种存储器的测试方法、装置及存储器系统。
背景技术
动态随机存取存储器(Dynamic Random Access Memory，DRAM)是当代计算机系统中不可或缺的组成部件，由许多阵列排布的存储单元组成。
在DRAM中，存储单元自身以及相邻存储单元之间存在着多种噪声。这些噪声会消耗存储单元的信号裕度，导致存储单元产生由于信号裕度不足造成的失效。
因此，在测试过程中准确地检测出存在潜在信号裕度不足缺陷的存储单元，对于DRAM的性能评估具有重要意义。
发明内容
有鉴于此，本公开实施例为解决现有技术中存在的至少一个问题而提供一种存储器的测试方法、装置及存储器系统。
为达到上述目的，本公开实施例的技术方案是这样实现的：
第一方面，本公开实施例提供一种存储器的测试方法，所述方法包括：
在噪声环境下对存储单元执行写入操作和读取操作；所述写入操作包括将测试数据写入所述存储单元中；
将执行所述读取操作得到的读取结果和所述测试数据进行比较，得到所述存储单元在噪声影响下的信号裕度测试结果；
所述噪声环境中的噪声至少包括以下之一：电源电压噪声、写恢复时间噪声、存储单元漏电噪声。
在一种可选的实施方式中，所述在噪声环境下对存储单元执行写入操作和读取操作，包括：
将电源电压从第一电压调整为第二电压；所述第一电压大于所述第二 电压；
在所述电源电压噪声环境下对存储单元执行写入操作和读取操作。
在一种可选的实施方式中，所述在噪声环境下对存储单元执行写入操作和读取操作，包括：
将写恢复时间从第一时长调整为第二时长；所述第一时长大于所述第二时长；
在所述写恢复时间噪声环境下对存储单元执行写入操作和读取操作。
在一种可选的实施方式中，所述在噪声环境下对存储单元执行写入操作和读取操作，包括：
将所述写入操作和所述读取操作之间的等待时间从第三时长调整为第四时长；所述第三时长小于所述第四时长；
在所述存储单元漏电噪声环境下对存储单元执行写入操作和读取操作。
在一种可选的实施方式中，所述对存储单元执行写入操作，包括：
对所述存储单元执行第一写入操作，将背景数据写入所述存储单元中；
按照预设数据结构，对所述存储单元执行第二写入操作，将所述预设数据结构中的测试数据写入所述存储单元中。
在一种可选的实施方式中，所述第二写入操作对应的写恢复时间小于所述第一写入操作对应的写恢复时间。
在一种可选的实施方式中，所述背景数据为第一数据；所述预设数据结构中的测试数据包括第一数据和第二数据，所述第二数据对应的存储单元为目标存储单元。
在一种可选的实施方式中，所述存储器为动态随机存取存储器。
第二方面，本公开实施例提供一种存储器测试装置，所述装置包括：
数据处理模块，配置为在噪声环境下对所述存储单元执行写入操作和读取操作；所述写入操作包括将测试数据写入所述存储单元中；
比较模块，配置为将执行所述读取操作得到的读取结果和所述测试数据进行比较，得到所述存储单元在噪声影响下的信号裕度测试结果；
所述噪声环境中的噪声至少包括以下之一：电源电压噪声、写恢复时间噪声、存储单元漏电噪声。
在一种可选的实施方式中，所述装置还包括：
电压调整模块，配置为将电源电压从第一电压调整为第二电压；所述第一电压大于所述第二电压；
所述数据处理模块，具体配置为在所述电源电压噪声环境下对所述存储单元执行写入操作和读取操作。
在一种可选的实施方式中，所述装置还包括：
写恢复时间调整模块，配置为将写恢复时间从第一时长调整为第二时长；所述第一时长大于所述第二时长；
所述数据处理模块，具体配置为在所述写恢复时间噪声环境下对所述 存储单元执行写入操作和读取操作。
在一种可选的实施方式中，所述装置还包括：
等待时间调整模块，配置为将所述写入操作和所述读取操作之间的等待时间从第三时长调整为第四时长；所述第三时长小于所述第四时长；
所述数据处理模块，具体配置为在所述存储单元漏电噪声环境下对所述存储单元执行写入操作和读取操作。
在一种可选的实施方式中，所述数据处理模块包括：
第一写入模块，配置为对所述存储模块执行第一写入操作，将背景数据写入所述存储单元中；
第二写入模块，配置为按照预设数据结构，对所述存储单元执行第二写入操作，将所述预设数据结构中的测试数据写入所述存储单元中。
在一种可选的实施方式中，所述第二写入操作的写恢复时间小于所述第一写入操作的写恢复时间。
在一种可选的实施方式中，所述背景数据为第一数据；所述预设数据结构中的测试数据包括第一数据和第二数据，所述第二数据对应的存储单元为目标存储单元。
第三方面，本公开实施例提供一种存储器系统，包括：控制器以及多个耦合至所述控制器的存储器；其中，
所述控制器，被配置为执行第一方面所述的存储器测试方法。
在本公开所提供的技术方案中，提供了一种存储器的测试方法，所述方法包括：在噪声环境下对存储单元执行写入操作和读取操作；所述写入操作包括将测试数据写入所述存储单元中；将执行所述读取操作得到的读取结果和所述测试数据进行比较，得到所述存储单元在噪声影响下的信号裕度测试结果；所述噪声环境中的噪声至少包括以下之一：电源电压噪声、写恢复时间噪声、存储单元漏电噪声。本公开通过在电源电压噪声、写恢复时间噪声、存储单元漏电噪声等噪声环境中对存储单元进行信号裕度测试，能有效提高测试覆盖率，使得存在潜在信号裕度不足缺陷的存储单元更容易被检测出来，提高了存储器性能评估的准确性。
附图说明
图1为本公开实施例提供的存储器中存储单元阵列的组成结构示意图；
图2为本公开实施例提供的存储单元阵列中存储单元的组成结构示意图；
图3为本公开实施例提供读取操作时的电路结构示意图；
图4为本公开实施例提供读取操作的时序图；
图5为本公开实施例提供的存储器的测试方法的实现流程示意图；
图6为本公开实施例提供的写恢复时间噪声环境下失效位元的数量随写恢复时间的变化曲线；
图7为本公开实施例提供的存储单元漏电噪声环境下失效位元的数量随写入操作和读取操作之间的等待时间的变化曲线；
图8a-8c为本公开实施例提供的三种不同的预设数据结构；
图9为本公开实施例一具体示例提供的存储器的测试流程图；
图10为本公开实施例提供的存储器的测试装置的组成结构示意图；
图11为本公开实施例提供的存储器系统的组成结构示意图。
具体实施方式
下面将参照附图更详细地描述本公开公开的示例性实施方式。虽然附图中显示了本公开的示例性实施方式，然而应当理解，可以以各种形式实现本公开，而不应被这里阐述的具体实施方式所限制。相反，提供这些实施方式是为了能够更透彻地理解本公开，并且能够将本公开公开的范围完整的传达给本领域的技术人员。
在下文的描述中，给出了大量具体的细节以便提供对本公开更为彻底的理解。然而，对于本领域技术人员而言显而易见的是，本公开可以无需一个或多个这些细节而得以实施。在其他的例子中，为了避免与本公开发生混淆，对于本领域公知的一些技术特征未进行描述；即，这里不描述实际实施例的全部特征，不详细描述公知的功能和结构。
在附图中，为了清楚，层、区、元件的尺寸以及其相对尺寸可能被夸大。自始至终相同附图标记表示相同的元件。
应当明白，空间关系术语例如“在……下”、“在……下面”、“下面的”、“在……之下”、“在……之上”、“上面的”等，在这里可为了方便描述而被使用从而描述图中所示的一个元件或特征与其它元件或特征的关系。应当明白，除了图中所示的取向以外，空间关系术语意图还包括使用和操作中的器件的不同取向。例如，如果附图中的器件翻转，然后，描述为“在其它元件下面”或“在其之下”或“在其下”元件或特征将取向为在其它元件或特征“上”。因此，示例性术语“在……下面”和“在……下”可包括上和下两个取向。器件可以另外地取向(旋转90度或其它取向)并且在此使用的空间描述术语相应地被解释。
在此使用的术语的目的仅在于描述具体实施例并且不作为本公开的限制。在此使用时，单数形式的“一”、“一个”和“所述/该”也意图包括复数形式，除非上下文清楚指出另外的方式。还应明白术语“组成”和/或“包括”，当在该说明书中使用时，确定所述特征、整数、步骤、操作、元件和/或部件的存在，但不排除一个或更多其它的特征、整数、步骤、操作、元件、部件和/或组的存在或添加。在此使用时，术语“和/或”包括相关所列项目的任何及所有组合。
附图中所示的方框图仅仅是功能实体，不一定必须与物理上独立的实体相对应。即，可以采用软件形式来实现这些功能实体，或在一个或多个 软件硬化的模块中实现这些功能实体或功能实体的一部分，或在不同网络和/或处理器装置和/或微控制器装置中实现这些功能实体。
本公开实施例中涉及的存储装置可以包括动态随机存取存储器(Dynamic Random Access Memory，DRAM)，尤其适应用于采用DDR4内存规格、DDR5内存规格的双倍数据速率同步动态随机存取存储器和采用LPDDR5内存规格的低功耗双倍数据速率同步动态随机存取存储器。需要说明的是，本公开实施例并不限于DRAM，但在后续的介绍中，为了描述清楚，仅以DRAM为例进行说明。
图1为本公开实施例提供的存储器中存储单元阵列的组成结构示意图。如图1所示，在DRAM中，存储单元阵列典型地以行和列布置，使得特定的存储单元可以通过指定其阵列的行和列来寻址。存储单元阵列包括多条字线(图1中示出的WL)、多个位线对(图1中示出的BL/BLB)、多个位于所述字线和位线的交叉位置处的存储单元(图1中示出的“■”)，以及多个连接到所述位线对的感应放大器(图1中示出的“SA”)。图1中还示出了控制位线激活的列选择信号(CSL)，控制写驱动器的写使能信号(WE)和多条本地输入输出线(图1中示出的LIO)。
图2为本公开实施例提供的存储单元阵列中存储单元的组成结构示意图。如图2所示，DRAM中的每个存储单元通常包括电容器(Storage Capacitor，SC)和晶体管(Access Transistor，AT)，晶体管AT的栅极与字线WL相连，漏极与位线相连，源极与电容器SC相连。字线WL上的电压信号能够控制晶体管AT的打开或关闭，进而通过位线BL读取存储在电容器SC中的数据信息，或者通过位线BL将数据信息写入到电容器SC中进行存储。
下面先结合图3和图4对存储单元的数据读取过程进行说明，其中，图3为读取操作时的电路结构示意图，图4为读取操作的时序图。
如图3所示，感应放大器100包括四个晶体管，分别为第一晶体管101、第二晶体管102、第三晶体管103和第四晶体管104，其中，第一晶体管101和第三晶体管103均为PMOS(Positive channel Metal Oxide Semiconductor，P型金属氧化物半导体)晶体管，第二晶体管102和第四晶体管104均为NMOS(Negative channel Metal Oxide Semiconductor，N型金属氧化物半导体)晶体管。第一晶体管101的栅极连接至参考位线BLB，第一晶体管101的漏极和源极分别与位线BL和P型感应放大器控制信号(Sense-Amplifier P-Fet Control，SAP)连接；第三晶体管103的栅极连接至位线BL，第三晶体管103的漏极和源极分别与参考位线BLB和SAP连接；第二晶体管102的栅极连接至参考位线BLB，第二晶体管102的漏极和源极分别与位线BL和N型感应放大器控制信号(Sense-Amplifier N-Fet Control，SAN)连接；第四晶体管104的栅极连接至位线BL，第四晶体管104的的漏极和源极分别与参考位线BLB和SAN连接。
预充电部分120包括第五晶体管105、第六晶体管106和第七晶体管107。其中，第五晶体管105的漏极和源极分别连接于位线BL和位线预充电压VBLP(Voltage of Bit Line Precharge)，第六晶体管106的漏极和源极分别连接于参考位线BLB和位线预充电压VBLP，第七晶体管107的漏极和源极分别连接于位线BL和参考位线BLB，第五晶体管105的栅极、第六晶体管106的栅极和第七晶体管107的栅极都连接于预充信号线，且预充信号线连接的是电压均衡器(Voltage Equalizer，VEQ)，从而在预充信号线导通时，使位线BL和参考位线BLB充电到位线预充电压VBLP。
存储单元110中电容器SC的一个极板上施加的电压始终为电源电压V CC的一半，即为V CC/2，当电容器SC存储的数据信息为“1”时，另一个极板上的电压为V CC，此时电容器SC所存储的电荷量为+Vcc/2C，其中C为电容器SC的电容；当电容器SC存储的数据信息为“0”时，另一个基板上的电压为0，此时电容器SC所存储的电荷量为-Vcc/2C。下面以对一个存储单元110执行数据信息“1”的写入操作和读取操作为例进行描述。
图4为读取操作的时序图，图中横轴表示时间，纵轴表示信号电平。如图4所示，一个读取操作(Read)包括四个阶段：预充电(Precharge)阶段Q1、电荷共享(Charge Sharing)阶段Q2、感测(Sensing)阶段Q3和恢复(Restore)阶段Q4。
在预充电阶段Q1，参见图3和图4，在预充电指令(PRE)后，WL关断，一段时间后感应放大器关断，通过控制预充信号，让第五晶体管105、第六晶体管106、第七晶体管107处于导通状态，将位线BL和参考位线BLB上的电压稳定在Vref上，Vref＝V CC/2＝VBLP。
经过预充电阶段Q1，BL和BLB上的电压已经稳定在Vref，在获取阶段Q2，预充信号线关闭，在激活指令(Row-Active Command，ACT)和一固定时间T1延迟后通过控制WL信号开启WL，将存储单元110中的晶体管AT导通，电容器中存储正电荷会流向BL，继而将BL的电压拉升到Vref+，然后进入感测阶段Q3。
由于在获取阶段Q2，BL的电压被拉升到Vref+，第四晶体管104会比第二晶体管102更具导通性，第一晶体管101则会比第三晶体管103更具导通性。在感测阶段Q3，SAN上的电压会被设定为逻辑0的电压，SAP的电压则会被设定为逻辑1的电压，即高电平V CC。由于第四晶体管104会比第二晶体管102更具导通性，BLB上的电压会更快被SAN拉到逻辑0电压，即为Gnd(表示接地电压，也可以记为Vss)，同理，BL上的电压也会更快被SAP拉到逻辑1电压。接着第一晶体管101和第四晶体管104进入导通状态，第三晶体管103和第二晶体管102进入截止状态。最后，BL和BLB的电压都进入稳定状态，正确的呈现了电容器所存储的信息。
在完成感测阶段Q3的操作后，在恢复阶段Q4，BL处于稳定的逻辑1电压V CC，此时BL会对电容器进行充电。经过特定的时长后，电容器的电 荷就可以恢复到读取操作前的状态。执行读指令RD，通过控制列选择信号CSL使列选择晶体管141导通，电容器SC所存储的信息被从感应放大器输出到本地输入输出线LIO，外界就可以读取到具体的信息。
写入操作(Write)的部分过程与读取操作是一样的，除了包括预充电阶段Q1、电荷共享阶段Q2、感测阶段Q3和恢复阶段Q4，还包括写恢复(Write Recovery)阶段Q5。在写恢复阶段Q5，通过控制写使能信号WE，使写使能晶体管(图中未示出)导通。此时，BL会被拉到逻辑1电平，BLB则会被拉到逻辑0电平。经过特定的时间后，当电容器SC被充电到1的状态时，就可以通过控制WL，将连接电容器SC的晶体管AT截止，完成写入1的操作。
理论情况下，在读取操作的过程中，BL上的电压从Vref被拉升至逻辑1电压，在此过程中BL上产生的电压变化即为存储单元的理论信号裕度(Signal Margin，SM)，如公式(1)所示：
Figure PCTCN2022093270-appb-000001
其中，C BL是BL产生的等效电容，C SC为电容器SC的电容。
随着半导体存储技术的发展，存储器的生产工艺越来越成熟，半导体存储器朝着更小尺度和更大集成的方向发展。半导体存储器的生产过程中，因生产工艺的高要求和高精度，往往会存在一定数量的缺陷产品。对于缺陷产品，有些缺陷暴露较明显，能够在测试阶段检测出来进而进行修复或丢弃；但对于有些缺陷，在测试阶段往往不能检测出来，只有在之后的反复擦除与写入中才会显露出来。在存储器生产工艺流程中，因工艺的偏差、环境、设备等因素的影响，存储单元可能存在潜在信号裕度不足缺陷；此类缺陷在存储器的测试阶段很难被检测出来，只有在之后的使用中，因循环的读取和写入呈现出来，并造成数据读取错误。
因此，如何能够及时检测出存储单元的潜在信号裕度不足缺陷成为了亟待解决的问题，并且对于DRAM的性能评估具有重要意义。
对此，本公开提出了以下实施方式。
本公开实施例提出了一种存储器的测试方法。图5为本公开实施例提供的存储器的测试方法的实现流程示意图。如图5所示，存储器的测试方法包括以下步骤：
步骤501：在噪声环境下对存储单元执行写入操作和读取操作；所述写入操作包括将测试数据写入存储单元中；所述噪声环境中的噪声至少包括以下之一：电源电压噪声、写恢复时间噪声、存储单元漏电噪声。
在一些实施例中，在噪声环境下对存储单元执行写入操作和读取操作，包括：将电源电压从第一电压调整为第二电压；所述第一电压大于所述第二电压；在所述电源电压噪声环境下对存储单元执行写入操作和读取操作。
在本公开实施例中，存储器的电源电压的降低会直接导致存储单元的 电源电压V CC的降低，而存储单元的理论信号裕度SM与V CC成正相关，因此，在信号裕度测试中，可以通过降低存储器的电源电压来模拟电源电压噪声对存储单元信号裕度的影响，从而使得存在潜在信号裕度不足缺陷的存储单元更容易被检测出来。
在一具体示例中，第一电压为JEDEC标准中规定的DRAM的电源电压，第二电压低于第一电压，如当第一电压为1.80V时，第二电压可以为1.62V；当第一电压为1.1V时，第二电压可以为0.99V。
在一些实施例中，在噪声环境下对存储单元执行写入操作和读取操作，包括：将写恢复时间从第一时长调整为第二时长；所述第一时长大于所述第二时长；在所述写恢复时间噪声环境下对存储单元执行写入操作和读取操作。
这里，写恢复时间(Time of Write Recovery，tWR)为写使能信号WE产生到预充电指令PRE产生之间的时间段。如果写恢复时间太短，可能会导致前一次写入操作未完成就开始下一次预充电操作，即电容器SC上的电压未达到+Vcc时WL就已关断，这种情况也会对存储单元的实际信号裕度造成影响。因此，在信号裕度测试中，可以通过缩短写恢复时间来模拟写恢复时间噪声，以模拟写恢复时间噪声对存储单元信号裕度的影响，从而使得存在潜在信号裕度不足缺陷的存储单元更容易被检测出来。
在一些实施例中，测试方法还包括：确定所述第二时长。确定所述第二时长的过程可以为在不同写恢复时间下对存储单元执行相同测试数据的写入和读取测试，并计算每次写入和读取测试中失效位元的数量(Failure Bit Count，FBC)。这里，确定过程中的不同写恢复时间为从第一时长递减得到的多个写恢复时间，第一时长可以为JEDEC标准中规定的DRAM的写恢复时间。通过写入和读取测试得到的写恢复时间噪声环境下失效位元的数量FBC随写恢复时间tWR的变化曲线如图6所示，随着写恢复时间的减小，当存储器中失效位元的数量FBC达到预设允许失效数量FBC*时，对应的时间t1即为第二时长，也是使存储单元正确写入数据的最短写恢复时间。将写恢复时间设置为使存储单元正确写入数据的最短写恢复时间t1，可以最大限度地减小存储单元的实际信号裕度，提高信号裕度测试的覆盖率。
这里，存储器中失效位元的数量FBC可以通过统计写入的数据和读取的数据不同的存储单元的数量来确定，也可以通过其他方式确定，本公开实施例对此不作限定。预设允许失效数量FBC*可以根据实际情况设置，例如，将预设允许失效数量设置为存储单元总数的千分之一至万分之一中的任意数，本公开实施例对此不作特殊限定。
在一些实施例中，在噪声环境下对存储单元执行写入操作和读取操作，包括：将所述写入操作和所述读取操作之间的等待时间从第三时长调整为第四时长；所述第三时长小于所述第四时长；在所述存储单元漏电噪声环 境下对存储单元执行写入操作和读取操作。
在实际情况中，在写入操作完成以后，存储单元会产生漏电的现象，随着等待时间的增加，电容器上存储的电荷数量逐渐减小，存储单元的实际信号裕度也逐渐减小。当漏电达到一定程度时，电容器上存储的电荷数量不足以正确的判别数据，就会造成数据的丢失。因此，可以通过增加写入操作和读取操作之间的等待时间，来模拟实际情况中的存储单元漏电噪声，并在存储单元漏电噪声环境下对存储单元执行写入操作和读取操作。
在一些实施例中，测试方法还包括：确定所述第四时长。确定所述第四时长的过程可以为关闭存储器的自刷新功能，在不同等待时间下对存储单元进行相同测试数据的写入和读取测试，并计算每次写入和读取测试中失效位元的数量。通过写入和读取测试得到的在存储单元漏电噪声环境下存储器中失效位元的数量FBC随等待时间的变化曲线如图7所示，随着等待时间的增加，当存储器中失效位元的数量FBC达到预设允许失效数量FBC*时，对应的时间t2即为第四时长，也是存储单元的最长数据保持时间。这里，通过将第四时长设置为存储单元的最长数据保持时间t2，可以使存储单元在经过等待时间后充分漏电并仍能保持所存储数据的准确性，从而可以制造出存储单元漏电的噪声环境，使得存在潜在信号裕度不足缺陷的存储单元更容易被检测出来，提高信号裕度测试的覆盖率。
在一些实施例中，对存储单元执行写入操作，包括：对所述存储单元执行第一写入操作，将背景数据写入所述存储单元中；按照预设数据结构，对所述存储单元执行第二写入操作，将所述预设数据结构中的测试数据写入所述存储单元中。
在一些实施例中，所述第二写入操作对应的写恢复时间小于所述第一写入操作对应的写恢复时间。这里，第二写入操作对应的写恢复时间即为第四时长。
在一些实施例中，所述背景数据为第一数据；所述预设数据结构中的测试数据包括第一数据和第二数据，所述第二数据对应的存储单元为目标存储单元。
这里，当第一数据为0时，第二数据为1，与1对应的存储单元为目标存储单元；当第一数据为1时，第二数据为0，与0对应的存储单元为目标存储单元。
在本公开实施例中，当第一数据为1，第二数据为0时，预设数据结构可以为具有1和0交替排布的棋盘状图案(如图8a所示的两个预设数据结构)、1和0按行交替排布的条纹图案(如图8b所示的两个预设数据结构)、其中一条BL上的数据为0的图案(如图8c所示的八个预设数据结构)或者其他由0和1任意排布组成的图案。在以上预设数据结构中，存储0的目标存储单元周围存在存储1的存储单元，可以加剧目标存储单元的漏电，从而进一步模拟存储单元漏电噪声。以图8c所示的预设数据结构为例进行 说明，可以通过提供如图8c所示的8个不同的预设数据结构，每个预设数据结构中包括8条字线对应的测试数据，结合间隔8条字线的写入方式，如此能最大限度地提高测试覆盖率。
在一些实施例中，第二写入操作和读取操作以突发长度(Burst Length，BL)为单位。在一具体的示例中，第二写入操作可以为X-FAST写入操作，X-FAST写入操作为一种X方向(行方向)的写入操作方式，即针对连接于同一位线的所有字线，依次在每条字线上写入一个突发长度的数据。读取操作可以为X-FAST读操作，X-FAST读操作为一种X方向(行方向)的读取操作方式，即针对连接于同一位线的所有字线，依次读取每条字线上的存储单元中的数据。在另一具体示例中，第二写入操作可以为Y-FAST写操作，Y-FAST写操作为一种Y方向(列方向)的写入操作方式，即在每次执行写入操作之前，开启一条字线，以突发长度为单位顺序写完这条字线上对应的所有存储单元后，关闭这条字线；然后再开启下一条字线顺序写完这条字线上对应的所有的存储单元。读取操作可以为Y-FAST读操作，Y-FAST读操作为一种Y方向(列方向)的读取操作方式，即在每一次执行读操作之前，开启一条字线，以突发长度为单位顺序读完这条字线上对应的所有存储单元后，关闭这条字线；然后再开启下一条字线顺序读完这条字线上对应的所有存储单元。
这里，突发长度是指在同一条字线中相邻的存储单元连续进行数据读取/写入时所涉及到的存储单元的数量。例如，DDR4支持的突发长度为8或4(即BL8或BL4)，当DDR4的位宽为16bit时，每一次可以读取/写入8×16bit数据或者4×16bit数据；LPDDR4支持的突发长度为32或16(即BL32或BL16)，当LPDDR4的位宽为16bit时，每一次可以读取/写入32×16bit数据或者16×16bit数据。
步骤502：将执行所述读取操作得到的读取结果和所述测试数据进行比较，得到所述存储单元在噪声影响下的信号裕度测试结果。
在本公开实施例中，当对存储单元执行读取操作得到的读取结果与测试数据不一致时，该存储单元的信号裕度测试结果为失败；当对存储单元执行读取操作得到的读取结果与测试数据一致时，该存储单元的信号裕度测试结果为通过。
在本公开实施例中，分别通过调节电源电压、调节写恢复时间和调节写入操作和读取操作之间的等待时间来模拟实际情况中的电源电压噪声、写恢复时间噪声和存储单元漏电噪声，从而使存在潜在信号裕度不足缺陷的存储单元在测试过程中能够被更容易地检测出来，提高了信号裕度测试的覆盖率。
为了进一步将上述存储器测试方法应用于实际的存储器信号裕度测试，本公开提供一具体示例。
图9为本公开实施例一具体示例提供的存储器的测试流程图，如图9 所示，测试流程包括以下步骤：
步骤901：设置噪声环境；
在本公开实施例中，设置噪声环境包括：设置电源电压噪声、设置写恢复时间噪声和/或设置存储单元漏电噪声。设置电源电压噪声包括减小电源电压以模拟电源电压噪声，这里，电源电压可以减小为1.62V或0.99V；设置写恢复时间噪声包括减小写恢复时间以模拟写恢复时间噪声，这里，写恢复时间可以减小为使存储单元正确写入数据的最短写恢复时间t1；设置存储单元漏电噪声包括增加写入操作和读取操作之间的等待时间以模拟存储单元漏电噪声，这里，等待时间可以增加为存储单元的最长数据保持时间t2。如此，通过设置噪声环境，可以使存在潜在信号裕度不足缺陷的存储单元在测试过程中更容易被检测出来，提高了信号裕度测试的覆盖率。
步骤902：执行第一写入操作，写入背景数据；
在本公开实施例中，通过对存储单元执行第一写入操作以将背景数据写入所有存储单元中。
步骤903：执行第二写入操作，按照预设数据结构写入测试数据；
在本公开实施例中，提供多个不同的预设数据结构；对于多个不同的预设数据结构中的每个预设数据结构，通过第二写入操作依次对存储单元进行测试数据的写入。第一次循环时采用第一个预设数据结构，第二次循环时采用第二个预设数据结构，以此类推，直到所有预设数据结构均被遍历，如此通过多个不同的预设数据结构即可实现所有存储单元的遍历。
在本公开实施例中，按照预设数据结构对存储单元执行第二写入操作，将预设数据结构中的测试数据写入目标存储单元。
这里，当背景数据为1时，与预设数据结构中的0对应的存储单元为目标存储单元。
在本公开实施例中，第二写入操作的写恢复时间为使存储单元正确写入数据的最短写恢复时间t1。第二写入操作为X-FAST写操作或Y-FAST写操作，突发长度为8位、16位或32位。
步骤904：经过等待时间后执行读取操作；
这里，等待时间为存储单元的最长数据保持时间t2。读取操作为X-FAST读操作或Y-FAST读操作。
步骤905：比较读取结果和测试数据；
在本公开实施例中，比较读取结果和测试数据可以得到目标存储单元的信号裕度测试结果。切换下一预设数据结构，继续执行步骤903；若此时的预设数据结构为最后一个预设数据结构，则退出本次测试。这里，通过使用多个预设数据结构可以使存储器中的所有存储单元都能作为目标存储单元完成一次信号裕度测试。例如，当第一次循环中的预设数据结构为图8a所示的第一个预设数据结构时，在第二次循环时将预设数据结构改变为图8a所示的第二个预设数据结构；当第一次循环中的预设数据结构为图8b 所示的第一个预设数据结构时，在第二次循环时将预设数据结构改变为图8b所示的第二个预设数据结构；当第一次循环中的预设数据结构为图8c所示的第一个预设数据结构时，在第二次循环时将预设数据结构改变为图8c所示的第二个预设数据结构，以此类推，直到图8c所示的所有预设数据结构均被遍历。如此，可以使存储器中的所有存储单元都能作为目标存储单元完成一次信号裕度测试，即可以实现存储单元的遍历。
步骤906：输出测试结果。
在本公开实施例中，将读取结果和测试数据进行比较得到的目标存储单元的信号裕度测试结果进行输出。
基于前述存储器的测试方法相同的技术构思，本公开实施例提供一种存储器的测试装置，图10为本公开实施例提供的一种存储器的测试装置的结构示意图，如图10所示，存储器的测试装置1000包括：
数据处理模块1001，配置为在噪声环境下对所述存储单元执行写入操作和读取操作；所述写入操作包括将测试数据写入所述存储单元中；
比较模块1002，配置为将执行所述读取操作得到的读取结果和所述测试数据进行比较，得到所述存储单元在噪声影响下的信号裕度测试结果；
所述噪声环境中的噪声至少包括以下之一：电源电压噪声、写恢复时间噪声、存储单元漏电噪声。
在一些实施例中，所述装置还包括：
电压调整模块1003，配置为将电源电压从第一电压调整为第二电压；所述第一电压大于所述第二电压；
所述数据处理模块1001，具体配置为在所述电源电压噪声环境下对所述存储单元执行写入操作和读取操作。
在一些实施例中，所述装置还包括：
写恢复时间调整模块1004，配置为将写恢复时间从第一时长调整为第二时长；所述第一时长大于所述第二时长；
所述数据处理模块1001，具体配置为在所述写恢复时间噪声环境下对所述存储单元执行写入操作和读取操作。
在一些实施例中，所述装置还包括：
等待时间调整模块1005，配置为将所述写入操作和所述读取操作之间的等待时间从第三时长调整为第四时长；所述第三时长小于所述第四时长；
所述数据处理模块1001，具体配置为在所述存储单元漏电噪声环境下对所述存储单元执行写入操作和读取操作。
在一些实施例中，所述数据处理模块1001包括：
第一写入模块(图中未示出)，配置为对所述存储模块执行第一写入操作，将背景数据写入所述存储单元中；
第二写入模块(图中未示出)，配置为按照预设数据结构，对所述存储单元执行第二写入操作，将所述预设数据结构中的测试数据写入所述存 储单元中。
在一些实施例中，所述第二写入操作的写恢复时间小于所述第一写入操作的写恢复时间。
在一些实施例中，所述背景数据为第一数据；所述预设数据结构中的测试数据包括第一数据和第二数据，所述第二数据对应的存储单元为目标存储单元。
本公开实施例还提供一种存储器系统，如图11所示，本公开实施例提供的存储器系统包括控制器1101以及多个耦合至所述控制器的存储器1102；其中，
控制器1101，被配置为执前述存储器测试方法。
在一些实施例中，所述存储装置为动态随机存取存储器。
在一些实施例中，所述动态随机存取存储器的内存符合DDR2内存规格。
在一些实施例中，所述动态随机存取存储器的内存符合DDR3内存规格。
在一些实施例中，所述动态随机存取存储器的内存符合DDR4内存规格。
在一些实施例中，所述动态随机存取存储器的内存符合DDR5内存规格。
在一些实施例中，所述动态随机存取存储器的内存符合LPDDR4内存规格。
在一些实施例中，所述动态随机存取存储器的内存符合LPDDR5内存规格。
本公开所提供的几个方法实施例中所揭露的方法，在不冲突的情况下可以任意组合，得到新的方法实施例。
本公开所提供的几个装置实施例中所揭露的特征，在不冲突的情况下可以任意组合，得到新的装置实施例。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。
工业实用性
本公开通过在电源电压噪声、写恢复时间噪声、存储单元漏电噪声等噪声环境中对存储单元进行信号裕度测试，能有效提高测试覆盖率，使得存在潜在信号裕度不足缺陷的存储单元更容易被检测出来，提高了存储器性能评估的准确性。

Claims (16)

  1. 一种存储器测试方法，所述方法包括：
    在噪声环境下对存储单元执行写入操作和读取操作；所述写入操作包括将测试数据写入所述存储单元中；
    将执行所述读取操作得到的读取结果和所述测试数据进行比较，得到所述存储单元在噪声影响下的信号裕度测试结果；
    所述噪声环境中的噪声至少包括以下之一：电源电压噪声、写恢复时间噪声、存储单元漏电噪声。
  2. 根据权利要求1所述的存储器测试方法，其中，所述在噪声环境下对存储单元执行写入操作和读取操作，包括：
    将电源电压从第一电压调整为第二电压；所述第一电压大于所述第二电压；
    在所述电源电压噪声环境下对存储单元执行写入操作和读取操作。
  3. 根据权利要求1所述的存储器测试方法，其中，所述在噪声环境下对存储单元执行写入操作和读取操作，包括：
    将写恢复时间从第一时长调整为第二时长；所述第一时长大于所述第二时长；
    在所述写恢复时间噪声环境下对存储单元执行写入操作和读取操作。
  4. 根据权利要求1所述的存储器测试方法，其中，所述在噪声环境下对存储单元执行写入操作和读取操作，包括：
    将所述写入操作和所述读取操作之间的等待时间从第三时长调整为第四时长；所述第三时长小于所述第四时长；
    在所述存储单元漏电噪声环境下对存储单元执行写入操作和读取操作。
  5. 根据权利要求1所述的存储器测试方法，其中，所述对存储单元执行写入操作，包括：
    对所述存储单元执行第一写入操作，将背景数据写入所述存储单元中；
    按照预设数据结构，对所述存储单元执行第二写入操作，将所述预设数据结构中的测试数据写入所述存储单元中。
  6. 根据权利要求5所述的存储器测试方法，其中，所述第二写入操作对应的写恢复时间小于所述第一写入操作对应的写恢复时间。
  7. 根据权利要求5所述的存储器测试方法，其中，所述背景数据为第一数据；所述预设数据结构中的测试数据包括第一数据和第二数据，所述第二数据对应的存储单元为目标存储单元。
  8. 根据权利要求1-7中任一项所述的存储器测试方法，其中，所述存储器为动态随机存取存储器。
  9. 一种存储器测试装置，所述装置包括：
    数据处理模块，配置为在噪声环境下对所述存储单元执行写入操作和读取操作；所述写入操作包括将测试数据写入所述存储单元中；
    比较模块，配置为将执行所述读取操作得到的读取结果和所述测试数据进行比较，得到所述存储单元在噪声影响下的信号裕度测试结果；
    所述噪声环境中的噪声至少包括以下之一：电源电压噪声、写恢复时间噪声、存储单元漏电噪声。
  10. 根据权利要求9所述的存储器测试装置，其中，所述装置还包括：
    电压调整模块，配置为将电源电压从第一电压调整为第二电压；所述第一电压大于所述第二电压；
    所述数据处理模块，具体配置为在所述电源电压噪声环境下对所述存储单元执行写入操作和读取操作。
  11. 根据权利要求9所述的存储器测试装置，其中，所述装置还包括：
    写恢复时间调整模块，配置为将写恢复时间从第一时长调整为第二时长；所述第一时长大于所述第二时长；
    所述数据处理模块，具体配置为在所述写恢复时间噪声环境下对所述存储单元执行写入操作和读取操作。
  12. 根据权利要求9所述的存储器测试装置，其中，所述装置还包括：
    等待时间调整模块，配置为将所述写入操作和所述读取操作之间的等待时间从第三时长调整为第四时长；所述第三时长小于所述第四时长；
    所述数据处理模块，具体配置为在所述存储单元漏电噪声环境下对所述存储单元执行写入操作和读取操作。
  13. 根据权利要求9所述的存储器测试装置，其中，所述数据处理模块包括：
    第一写入模块，配置为对所述存储模块执行第一写入操作，将背景数据写入所述存储单元中；
    第二写入模块，配置为按照预设数据结构，对所述存储单元执行第二写入操作，将所述预设数据结构中的测试数据写入所述存储单元中。
  14. 根据权利要求13所述的存储器测试装置，其中，所述第二写入操作的写恢复时间小于所述第一写入操作的写恢复时间。
  15. 根据权利要求13所述的存储器测试装置，其中，所述背景数据为第一数据；所述预设数据结构中的测试数据包括第一数据和第二数据，所述第二数据对应的存储单元为目标存储单元。
  16. 一种存储器系统，包括控制器以及多个耦合至所述控制器的存储器；其中，
    所述控制器，被配置为执行权利要求1至8任一项所述的方法。
PCT/CN2022/093270 2022-04-11 2022-05-17 一种存储器的测试方法、装置及存储器系统 Ceased WO2023197399A1 (zh)

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Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20010014922A1 (en) * 2000-02-14 2001-08-16 Mitsubishi Denki Kabushiki Kaisha Interface circuit device for performing data sampling at optimum strobe timing
CN101916593A (zh) * 2010-07-15 2010-12-15 凌阳科技股份有限公司 一种内存测试系统
JP2011060392A (ja) * 2009-09-11 2011-03-24 Nec Corp 半導体記憶装置の試験方法
CN110021333A (zh) * 2017-11-23 2019-07-16 三星电子株式会社 存储器装置和存储器系统
CN110322910A (zh) * 2018-03-28 2019-10-11 英特尔公司 基于自适应校准的存储器预设调节
CN112885401A (zh) * 2021-03-25 2021-06-01 长鑫存储技术有限公司 存储单元信号裕度确定方法及装置、存储介质及电子设备
CN114072749A (zh) * 2019-07-02 2022-02-18 微软技术许可有限责任公司 动态调节器件工作电压
CN114283870A (zh) * 2022-01-14 2022-04-05 长鑫存储技术有限公司 测试方法、装置、计算机设备及存储介质

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20010014922A1 (en) * 2000-02-14 2001-08-16 Mitsubishi Denki Kabushiki Kaisha Interface circuit device for performing data sampling at optimum strobe timing
JP2011060392A (ja) * 2009-09-11 2011-03-24 Nec Corp 半導体記憶装置の試験方法
CN101916593A (zh) * 2010-07-15 2010-12-15 凌阳科技股份有限公司 一种内存测试系统
CN110021333A (zh) * 2017-11-23 2019-07-16 三星电子株式会社 存储器装置和存储器系统
CN110322910A (zh) * 2018-03-28 2019-10-11 英特尔公司 基于自适应校准的存储器预设调节
CN114072749A (zh) * 2019-07-02 2022-02-18 微软技术许可有限责任公司 动态调节器件工作电压
CN112885401A (zh) * 2021-03-25 2021-06-01 长鑫存储技术有限公司 存储单元信号裕度确定方法及装置、存储介质及电子设备
CN114283870A (zh) * 2022-01-14 2022-04-05 长鑫存储技术有限公司 测试方法、装置、计算机设备及存储介质

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