WO2023195598A1

WO2023195598A1 - Apparatus for suppressing current distortion and circulation current of parallel three-phase two-level inverter and operating method of apparatus

Info

Publication number: WO2023195598A1
Application number: PCT/KR2022/020039
Authority: WO
Inventors: 박용순; 최승보
Original assignee: 광주과학기술원
Priority date: 2022-04-04
Filing date: 2022-12-09
Publication date: 2023-10-12
Also published as: KR20230142990A

Abstract

The present disclosure relates to a method for controlling a second inverter, the method comprising the steps of: receiving a three-phase command voltage of a first inverter, which is generated by a control device; acquiring a three-phase compensation voltage on the basis of a three-phase zero-phase current of the second inverter; acquiring a three-phase command voltage of the second inverter on the basis of the three-phase command voltage of the first inverter and the three-phase compensation voltage; and operating the second inverter on the basis of the three-phase command voltage of the second inverter.

Description

Current distortion and circulating current suppression device and method of operation of parallel 3-phase 2-level inverter

The present disclosure relates to a device for suppressing current distortion and circulating current of a three-phase, two-level inverter connected in parallel. More specifically, it relates to a device that controls a second inverter by receiving a minimum control signal from the first inverter.

As the capacity of solar and wind energy increases, multiple inverters are connected in parallel to deliver large amounts of power, rather than using a single inverter module. The biggest problem with the parallel operation method of inverters is that a circulating current is generated in the parallel inverters due to the difference in output voltage produced by each inverter. If the PWM signals are different due to sensing errors caused by each current and voltage sensor, filter parameter tolerance, and carrier asynchronization (reference patent [1]), the inverter output voltage between parallel inverter modules may vary. A difference occurs, which causes a circulating current to circulate between parallel inverter modules. To suppress circulating current, there is a method of physically blocking the circulating current by insulating parallel inverter modules. In addition, a method of reducing the size of the circulating current using a coupling inductor has been introduced, but both of the previous methods involve adding hardware, which increases the system cost. Therefore, there are ways to solve the problem through software methods. Among them, a master-slave method has been disclosed in which the PWM signal generated by the master inverter module is shared with the slave inverter modules in order to match the inverter output voltages of parallel inverter modules. However, due to the turn-on, turn-off of each phase of the inverter module, and the nonlinearity of the inverter due to parasitic capacitors, the inverter output voltages produced by parallel inverter modules have differences. This causes a circulating current to circulate between parallel inverter modules, and distortion of the inverter output current occurs in the slave module inverter that receives the PWM signal. To solve this problem, in the conventional inverter parallel operation method, a method has been disclosed to reduce the circulating current by using a zero-phase controller in the slave module, or to solve the problem by measuring the output current of all inverters and configuring a controller. However, when configuring a zero-phase controller, the zero-phase circulating current can be reduced, but the distortion of the slave's inverter output current due to the difference in inverter nonlinearity cannot be resolved. If a current controller is implemented by sensing the output current of all inverters, the data required to communicate between master and slave increases because the output current of all inverters must be known. Therefore, a correction method is needed that can prevent distortion of output current between circulating current and inverter, increase energy conversion efficiency delivered to the system, and reduce communication burden.

The control method of the second inverter for suppressing the circulating current of the second inverter connected in parallel with the first inverter according to an embodiment of the present disclosure includes the three-phase command voltage of the first inverter generated by the control device of the first inverter. receiving, obtaining a three-phase compensation voltage based on the three-phase zero phase current of the second inverter, and obtaining a three-phase command voltage of the second inverter based on the three-phase command voltage and the three-phase compensation voltage of the first inverter. It includes the step of obtaining, and the step of operating the second inverter based on the three-phase command voltage of the second inverter.

The step of acquiring the three-phase compensation voltage of the control method according to an embodiment of the present disclosure includes obtaining a three-phase target current signal, measuring the three-phase current of the second inverter, and measuring the three-phase current of the second inverter. Obtaining a three-phase zero-phase current of the second inverter based on the three-phase zero-phase current of the second inverter, obtaining a three-phase estimated current of the first inverter based on the three-phase zero-phase current of the second inverter and the three-phase target current signal, Obtaining a three-phase error current for the second inverter based on the phase estimate current and the three-phase current of the second inverter, and obtaining a three-phase compensation voltage based on the three-phase error current for the second inverter. Includes.

The step of acquiring the 3-phase estimated current of the first inverter in the control method according to an embodiment of the present disclosure is to subtract the 3-phase zero phase current of the second inverter from the 3-phase target current signal to obtain the 3-phase estimated current of the first inverter. Includes acquisition steps.

The step of acquiring the 3-phase error current for the second inverter in the control method according to an embodiment of the present disclosure is to subtract the 3-phase estimated current of the first inverter from the 3-phase current of the second inverter to obtain 3-phase error current for the second inverter. and obtaining phase error current.

The step of acquiring the three-phase compensation voltage of the control method according to an embodiment of the present disclosure is performed according to the equation below,

is the three-phase compensation voltage,

is the proportional gain,

is the integral gain,

is the command current for the three-phase error current for the second inverter, s is the Laplace operator and 1/s means the integrator,

is the three-phase error current for the second inverter.

The step of acquiring the three-phase command voltage of the second inverter in the control method according to an embodiment of the present disclosure includes obtaining the three-phase command voltage of the second inverter by adding the three-phase command voltage of the first inverter to the three-phase compensation voltage. Includes steps.

The step of acquiring the three-phase zero phase current of the second inverter in the control method according to an embodiment of the present disclosure includes the measured current of phase A of the second inverter, the measured current of phase B of the second inverter, and the measured current of phase B of the second inverter. It includes obtaining the average of the currents of phase C as the three-phase zero phase current of the second inverter.

The step of acquiring the three-phase estimated current of the first inverter in the control method according to an embodiment of the present disclosure includes measuring the three-phase zero phase current using a sensor included in the second inverter.

The step of acquiring the three-phase estimated current of the first inverter in the control method according to an embodiment of the present disclosure includes the step of obtaining a predetermined three-phase zero phase current, and the magnitude of the three-phase zero phase current is greater than or equal to zero. .

A control device for the second inverter for suppressing the circulating current of the second inverter connected in parallel with the first inverter according to an embodiment of the present disclosure. The control device of the second inverter includes a processor and a memory, and the processor receives the three-phase command voltage of the first inverter generated by the control device of the first inverter based on instructions stored in the memory, and Obtain a three-phase compensation voltage based on the three-phase zero-phase current, obtain a three-phase command voltage of the second inverter based on the three-phase command voltage and three-phase compensation voltage of the first inverter, and obtain a three-phase command of the second inverter. The second inverter is operated based on the voltage.

The control device of the second inverter according to an embodiment of the present disclosure includes a processor acquiring a three-phase target current signal based on an instruction stored in a memory, measuring the three-phase current of the second inverter, and controlling the three-phase current of the second inverter. Obtain the three-phase zero phase current of the second inverter based on the phase current, obtain the three-phase estimated current of the first inverter based on the three-phase zero phase current of the second inverter and the three-phase target current signal, and obtain the three-phase estimated current of the first inverter. A three-phase error current for the second inverter is obtained based on the three-phase estimated current and the three-phase current of the second inverter, and a three-phase compensation voltage is obtained based on the three-phase error current for the second inverter.

A computer-readable recording medium on which a control method program of a second inverter for suppressing circulating current of a second inverter connected in parallel with the first inverter according to an embodiment of the present disclosure is recorded, comprising: a control device for the first inverter; Receiving the three-phase command voltage of the first inverter generated by, obtaining a three-phase compensation voltage based on the three-phase zero phase current of the second inverter, the three-phase command voltage and the three-phase compensation voltage of the first inverter It includes obtaining a three-phase command voltage of the second inverter based on and operating the second inverter based on the three-phase command voltage of the second inverter.

The method for suppressing current distortion and circulating current in a three-phase, two-level inverter parallel operation system of the present invention is to eliminate physical differences caused by delays caused by differences in the nonlinear turn-on, turn-off, and parasitic capacitance of the inverter. It has a corrective effect.

This has the effect of reducing the communication burden by correcting the non-linear difference in the inverter without separate communication for current information between master and slave.

As the circulating current between parallel inverter modules decreases, the efficiency of the entire parallel operation system can be increased.

It is possible to provide efficient operation of each inverter module by suppressing current distortion of the slave inverter module that occurs due to differences in nonlinearity of the inverter modules.

By correcting nonlinear differences without adding additional hardware, it can be used in industrial fields that require parallel operation of inverters, such as grid-connected inverters, renewable energy generation, and large-capacity motor drives.

1 is a diagram showing a conventional method of controlling inverters connected in parallel.

Figure 2 shows a circuit diagram of a control device in one embodiment of the present disclosure.

FIG. 3 is a diagram for explaining why circulating current occurs in the master inverter and slave inverter according to an embodiment of the present disclosure.

FIG. 4 is a diagram for explaining why circulating current occurs in the master inverter and slave inverter according to an embodiment of the present disclosure.

FIG. 5 is a diagram to explain why circulating current occurs in the master inverter and slave inverter according to an embodiment of the present disclosure.

Figure 6

This is a diagram showing the process of deriving .

Figure 7 discloses the hardware configuration of a control device according to an embodiment of the present disclosure.

Figure 8 is a flowchart showing the operation of a control device according to an embodiment of the present disclosure.

Figure 9 is a flowchart showing the operation of a control device according to an embodiment of the present disclosure.

Figure 10 is a waveform diagram showing the effect of a control device according to an embodiment of the present disclosure.

11 is a waveform diagram showing the effect of a control device according to an embodiment of the present disclosure.

Figure 12 is a waveform diagram showing the effect of the control device according to an embodiment of the present disclosure.

Advantages and features of the disclosed embodiments and methods for achieving them will become clear by referring to the embodiments described below in conjunction with the accompanying drawings. However, the present disclosure is not limited to the embodiments disclosed below and may be implemented in various different forms. The present embodiments are merely provided to ensure that the present disclosure is complete and to those skilled in the art to which the present disclosure pertains. It is only provided to fully inform the user of the scope of the invention.

Terms used in this specification will be briefly described, and the disclosed embodiments will be described in detail.

The terms used in this specification are general terms that are currently widely used as much as possible while considering the function in the present disclosure, but this may vary depending on the intention or precedent of a technician working in the related field, the emergence of new technology, etc. In addition, in certain cases, there are terms arbitrarily selected by the applicant, and in this case, the meaning will be described in detail in the description of the relevant invention. Therefore, the terms used in this disclosure should be defined based on the meaning of the term and the overall content of this disclosure, rather than simply the name of the term.

In this specification, singular expressions include plural expressions, unless the context clearly specifies the singular. Additionally, plural expressions include singular expressions, unless the context clearly specifies plural expressions.

When it is said that a part "includes" a certain element throughout the specification, this means that, unless specifically stated to the contrary, it does not exclude other elements but may further include other elements.

Additionally, the term “unit” used in the specification refers to a software or hardware component, and the “unit” performs certain roles. However, “wealth” is not limited to software or hardware. The “copy” may be configured to reside on an addressable storage medium and may be configured to run on one or more processors. Thus, as an example, “part” refers to software components, such as object-oriented software components, class components, and task components, processes, functions, properties, procedures, Includes subroutines, segments of program code, drivers, firmware, microcode, circuits, data, databases, data structures, tables, arrays, and variables. The functionality provided within the components and “parts” may be combined into smaller numbers of components and “parts” or may be further separated into additional components and “parts”.

According to one embodiment of the present disclosure, “unit” may be implemented with a processor and memory. The term “processor” should be interpreted broadly to include general purpose processors, central processing units (CPUs), microprocessors, digital signal processors (DSPs), controllers, microcontrollers, state machines, etc. In some contexts, “processor” may refer to an application-specific integrated circuit (ASIC), programmable logic device (PLD), field programmable gate array (FPGA), etc. The term “processor” refers to a combination of processing devices, for example, a combination of a DSP and a microprocessor, a combination of a plurality of microprocessors, a combination of one or more microprocessors in combination with a DSP core, or any other such combination of configurations. It may also refer to

The term “memory” should be interpreted broadly to include any electronic component capable of storing electronic information. The terms memory include random access memory (RAM), read-only memory (ROM), non-volatile random access memory (NVRAM), programmable read-only memory (PROM), erasable-programmable read-only memory (EPROM), electrical may refer to various types of processor-readable media, such as erasable PROM (EEPROM), flash memory, magnetic or optical data storage, registers, etc. A memory is said to be in electronic communication with a processor if the processor can read information from and/or write information to the memory. The memory integrated into the processor is in electronic communication with the processor.

Below, with reference to the attached drawings, embodiments will be described in detail so that those skilled in the art can easily implement them. In order to clearly explain the present disclosure in the drawings, parts unrelated to the description are omitted.

According to the prior art, the current was measured for each phase, and after dq-axis coordinate transformation, a controller was configured for the sum of the currents and the difference between the currents to create each PWM signal. In FIG. 1, Inverter #1 represents the first inverter or master inverter. Additionally, Inverter #2 represents the second inverter or slave inverter. In the case of Figure 1, the slave inverter could be controlled only by knowing information about the output current of the master inverter. In other words, when the size of communication data between the slave inverter and the master inverter is large, when there is a communication delay due to the distance between the master inverter and the slave inverter, and when it is difficult to immediately respond to signal changes and control of the slave inverter becomes difficult. There was. The purpose of the slave inverter control method according to the present disclosure is to allow the slave inverter to be controlled normally while significantly reducing the amount of communication data between the master inverter and the slave inverter control device. More specifically, the present disclosure describes a control method for preventing circulating current from occurring between the master inverter and the slave inverter by controlling the slave inverter while reducing the amount of communication data.

Hereinafter, the configuration of a circuit according to an embodiment of the present disclosure will be described, and the reason why circulating current occurs between the master inverter and the slave inverter that are identically implemented with the same device will be explained. Additionally, a process in which the control method according to an embodiment of the present disclosure prevents circulating current while reducing the amount of communication data between the control unit of the master inverter and the slave inverter will be described.

3 to 5 are diagrams to explain why circulating current occurs in the master inverter and slave inverter according to an embodiment of the present disclosure.

Figure 2 shows a parallel operation system of a three-phase, two-level inverter according to an embodiment of the present disclosure. In the present disclosure, the master inverter is the same as the first inverter 220. Additionally, in the present disclosure, the slave inverter is the same as the second inverter 240. Additionally, Inverter #1 in FIG. 2 represents the first inverter or master inverter. Additionally, Inverter #2 in FIG. 2 represents a second inverter or slave inverter.

If the IGBT (Insulated Gate Bipolar Transistor), which is a switching element included in the first inverter 220 and the second inverter 240, is ideal, no current circulating or current distortion occurs within the parallel inverter module. However, problems occur in the parallel operation system due to differences in time delay due to turn-on, turn-off, and parasitic capacitors for each inverter phase.

Taking phase A as an example, one switching cycle (

), an ideal PWM signal can be created as shown in Figure 3.

In Figure 3

Is

It may be a PWM signal created by .

may be the A-phase command voltage of the first inverter 220 derived by block 210 of FIG. 2. The A-phase command voltage of the first inverter 220 may be included in the three-phase command voltage of the first inverter. The control device of the first inverter is

Compare to triangle wave

A signal like this can be obtained.

If is the PWM signal of the positive switch 221 of phase A,

may be a PWM signal of the A-phase cathode switch 222.

Is

It may be complementary to The positive and negative switches can be IGBTs.

In Figure 3

and

If all are 'ON', there is a possibility of a short circuit in the DC power supply unit 230, so the control device of the first inverter 220 is

and

In dead-time,

) can be applied. The PWM signal of the first inverter with dead time applied is

and

It can be. Depending on hardware characteristics and operating conditions, the switch signal within the dead time section is

and

may vary from the intended signal change.

Figure 4 shows the voltage around the inverter when the first inverter is assumed to be ideal and there is a non-linear element in the second inverter. When such a non-linear element occurs, a voltage difference occurs between one phase of the first inverter and one phase of the second inverter, and a circulating current may occur due to the voltage difference.

Figure 4(A) shows a case where the direction of the current flowing through the switch of the first inverter is positive. When the direction of the current flowing through the switch of the first inverter is positive, the direction of the current flowing through the switch of the second inverter may also be positive. Figure 4(B) shows a case where the direction of the current flowing through the switch of the first inverter is negative. When the direction of the current flowing through the switch of the first inverter is negative, the direction of the current flowing through the switch of the second inverter may also be negative.

In Figure 4

represents the output voltage of the first inverter 220. Since the first inverter 220 was assumed to be ideal,

can have a perfect square wave. The output voltage of the first inverter 220 may refer to the voltage between point A1 and point N in FIG. 2.

represents the output voltage of the second inverter 240. The output voltage of the second inverter 240 may refer to the voltage between point A2 and point N in FIG. 2. Since the output voltage of the second inverter 240 is not ideal, a delay may occur.

means the turn-on delay of the A-phase positive switch 241 of the second inverter 240.

means the turn-on delay of the A-phase cathode switch 242 of the second inverter 240.

means the turn-off delay of the A-phase positive switch 241 of the second inverter 240.

means the turn-off delay of the A-phase cathode switch 242 of the second inverter 240.

means the delay caused by the parasitic capacitor of the A-phase switches 241 and 242 of the second inverter 240.

According to an embodiment of the present disclosure in (A) of FIG. 4, the output voltage of the second inverter 240 may be the same as the waveform 411. In addition, according to another embodiment of the present disclosure in (A) of FIG. 4, the output voltage of the second inverter 240 may be the same as the waveform 421.

According to an embodiment of the present disclosure in (A) of FIG. 4, when the output voltage of the second inverter 240 is the same as the waveform 411, the output voltage of the first inverter 220 and the second inverter 240 The difference in output voltage (

) may be the same as waveform 412. In addition, according to another embodiment of the present disclosure in Figure 4 (A), when the output voltage of the second inverter 240 is the same as the waveform 421, the output voltage of the first inverter 220 and the second inverter ( 240) difference in output voltage (

) may be the same as waveform 422. The difference between the output voltage of the first inverter 220 and the output voltage of the second inverter 240 (

), a circulating current may be generated between the first inverter 220 and the second inverter 240.

Likewise, according to an embodiment of the present disclosure in Figure 4 (B), when the output voltage of the second inverter 240 is the same as the waveform 431, the output voltage of the first inverter 220 and the second inverter ( 240) difference in output voltage (

) may be the same as waveform 432. In addition, according to another embodiment of the present disclosure in Figure 4 (B), when the output voltage of the second inverter 240 is the same as the waveform 441, the output voltage of the first inverter 220 and the second inverter ( 240) difference in output voltage (

) may be the same as waveform 442. The difference between the output voltage of the first inverter 220 and the output voltage of the second inverter 240 (

Figure 4 focuses on phase A, but since the same description can be applied to phases B and C, overlapping descriptions will be omitted. As explained in FIG. 4, if it is assumed that the first inverter is ideal and the second inverter includes non-linear elements, the inverter output voltages of the first inverter and the second inverter are (A) in FIG. It may appear as in (B) in 4. Due to the non-linear elements of the inverter, a difference occurs in the inverter output voltage depending on the current direction of the second inverter every switching cycle, and this can be expressed as

Equations

1 and 2 in FIG. 5. Referring to FIG. 5, the output voltage of the first inverter 220 can be expressed as follows.

(Equation 1)

Additionally, referring to FIG. 5, the output voltage of the second inverter 240 can be expressed as follows.

(Equation 2)

In Equation 2

is the voltage caused by the nonlinearity delay of the switch according to the direction of the output current of the A-phase inverter of the second inverter 240, which is

,

All delays caused by can be included.

Figure 6 shows that in Equation 2

This is a diagram showing the process of deriving .

can be expressed as equation (610) in FIG. 6. Figure 6 is explained focusing on phase A, but since the same description can be applied to phases B and C, overlapping descriptions will be omitted.

The voltage that causes a circulating current from point (A1, B1, or C1) of the first inverter 220 in FIG. 2 to point (A2, B2, or C2) through point (A, B, or C) is generated.

If expressed as an equation, it can be as follows.

(Equation 3)

In equation 3

(where x= a, b, or c)

(However, x= a, b, or c).

According to another embodiment of the present disclosure,

Expressed as a formula, it can be as follows.

(Equation 3-1)

As already explained, the first inverter 220 is assumed to be ideal, but in reality, the first inverter 220 has nonlinearity, so Equation 3 can be modified as Equation 3-1 to reflect this. In Equation 3-1

(where x = a, b, or c) may be a voltage caused by a non-linear delay of the switch according to the direction of the inverter output current of the first inverter 220.

(where x= a, b, or c)

(However, x = a, b, or c) can be determined in the same way as in FIG. 6.

The control device of the second inverter of the present disclosure is

(However, x=a, b, or c, y=1 or 2) may include a control method to eliminate the difference. That is, the control device of the second inverter of the present disclosure may include a control method for removing residual circulation. The control method is explained below.

The control device 700 may include a processor 710 and a memory 720. The processor 710 may execute instructions stored in the memory 720. The control device 700 may control the second inverter 240 based on commands stored in the memory 720. The control device 700 may be implemented as hardware or software. The control device 700 may be implemented with only hardware to perform the corresponding function. However, it is not limited to this, and the control device 700 may be implemented with a general-purpose processor 710, and the general-purpose processor 710 of the control device 700 may be implemented to execute a program stored in the memory 720. The control device of the first inverter may include the same configuration as the control device 700 of the second inverter. The control device 700 of the first inverter and the second inverter may include a communication unit. The control device of the first inverter and the control device 700 of the second inverter can communicate wired or wirelessly. For example, the control device 700 of the second inverter may receive the three-phase command voltage of the first inverter 220 from the control device of the first inverter. However, it is not limited to this, and one control device can control both the first inverter and the second inverter. In this disclosure, simply referring to the control device 700 may refer to the control device of the second inverter.

Referring to FIG. 2, the second inverter 240 may be connected in parallel with the first inverter 220. For example, the first inverter 220 may be a master inverter, and the second inverter 240 may be a slave inverter. Master inverter and slave inverter can be determined by the administrator. The master inverter can be controlled independently without receiving control signals from the slave inverter. The slave inverter can be controlled by receiving a control signal from the master inverter. The control device 700 of the second inverter 240 may perform the following control method to suppress circulating current between the second inverter 240 and the first inverter 220.

Referring to FIGS. 2, 7, and 8 together, the control device 700 of the second inverter 240 controls the three-phase command voltage (

) may be performed (step 810). More specifically, the control device 700 of the second inverter 240 controls the three-phase command voltage of the first inverter 220 generated by the control block 210 (

) may be performed (step 810). The control device of the first inverter 220 can generate a three-phase command voltage. For example, the three-phase command voltage of the first inverter 220 may be generated by the block 210. The three-phase command voltage of the first inverter 220 is

,

,and

may include.

is the command voltage of phase A,

is the command voltage of phase B,

may be the command voltage of phase C. The control device of the first inverter 220 may generate a pulse wave by comparing the three-phase command voltage of the first inverter 220 with a triangle wave, and transmit the pulse wave to the switch (IGBT; Insulated Gate) of the first inverter 220. Bipolar Transistor). Additionally, the control device of the first inverter 220 may transmit the three-phase command voltage of the first inverter 220 to the control device 700 of the second inverter 240. The control device 700 of the second inverter 240 may receive the three-phase command voltage of the first inverter 220.

The control device 700 controls the three-phase zero phase current of the second inverter (

) A step 820 of acquiring a three-phase compensation voltage can be performed. The control device 700 may perform the following steps to obtain the three-phase zero phase current of the second inverter. The control device 700 obtains the average of the measured current in phase A of the second inverter, the measured current in phase B of the second inverter, and the measured current in phase C of the second inverter as the three-phase zero phase current of the second inverter. You can follow the steps. More specifically, the three-phase zero phase current of the second inverter (

) can be obtained by the following equation.

(Equation 4)

In Equation 4

may be the current flowing from point A2 to point A.

may be the current flowing from point B2 to point B.

may be the current flowing from point C2 to point C. The control device 700 of the second inverter controls the three-phase zero phase current (700) of the second inverter without the need for communication with the control device of the first inverter.

) can be obtained. The control device 700 measures the current using a sensor included in the second inverter 240 and determines the three-phase zero phase current (

) can be obtained. In addition, the control device 700 controls the three-phase zero phase current (

) can be obtained. 3-phase zero current (

) may have a value set by the user. The control device of the first inverter or the control device 700 of the second inverter controls three-phase zero phase current (

) can be input from the user. Pre-stored three-phase zero current (

) can have a value greater than or equal to 0. Pre-stored three-phase zero current (

) may be smaller than the target current signal or the three-phase target current signal in the dq coordinate system. Accordingly, the size of communication data of the first inverter 220 to the second inverter 240 can be reduced, and control errors of the second inverter 240 due to communication delay can be reduced. Step 820 will be described in detail with reference to FIG. 9.

The three-phase compensation voltage may be configured to obtain the three-phase command voltage of the second inverter 240 by compensating for the three-phase command voltage of the first inverter 220.

The control device 700 controls the three-phase command voltage of the first inverter (

,

,and

) and three-phase compensation voltage (

,

) Based on the three-phase command voltage of the second inverter (

,

,and

) can be performed (step 830). The control device 700 may further perform the following steps to perform the step 830 of acquiring the three-phase command voltage of the second inverter. The control device 700 uses a three-phase compensation voltage (

,

) to the three-phase command voltage of the first inverter (

,

,and

) is added to obtain the three-phase command voltage of the second inverter (

,

,and

) can be performed.

Additionally, step 840 of operating the second inverter based on the three-phase command voltage of the second inverter may be performed. More specifically, the control device 700 of the second inverter 240 controls the three-phase command voltage of the second inverter 240 (

,

,and

) can be compared with a triangle wave to generate a pulse PWM signal, and the PWM signal can be input to the positive and negative switches included in the second inverter 240.

More specifically, FIG. 9 is a flowchart specifying step 820 of FIG. 8. The step 820 of acquiring a three-phase compensation voltage may further include the following processes.

The control device 700 may perform step 910 of acquiring a three-phase target current signal. The three-phase target current signal may refer to the current supplied to the load 250 by the first inverter 220 or the second inverter 240. For example, the three-phase target current signal obtained by the control device 700 of the second inverter 240 is

,

, and

may include. The three-phase target current signal may be a predetermined value. The three-phase target current signal can be set by the manager of the control device 700.

The control device 700 of the second inverter 240 may perform control using the dq coordinate system. That is, the target current signal in the predetermined dq coordinate system is

and

It may be the same as

may be the d-axis component of the target current signal. also,

may be the q-axis component of the target current signal. The control device 700 of the second inverter 240 may convert the target current signal in the dq coordinate system into a three-phase target current signal.

The control device of the first inverter 220 and the control device of the second inverter 240 may share the target current signal in the d-q coordinate system. The control device of the first inverter 220 and the control device of the second inverter 240 may communicate using a target current signal in the d-q coordinate system. The control device of the first inverter 220 and the control device of the second inverter 240 may transmit and receive a target current signal in the d-q coordinate system. In addition, the control device of the first inverter 220 and the control device of the second inverter 240 perform a step 910 of converting the target current signal in the d-q coordinate system into a three-phase target current signal to obtain the three-phase target current signal. It can be done. For the target current signal in the d-q coordinate system, the d-axis and q-axis components can be expressed as DC components. Therefore, when communicating using a target current signal in the d-q coordinate system, the control device of the first inverter 220 and the control device of the second inverter 240 can transmit and receive a constant value regardless of the communication period. However, since three phases are changing alternating current components, when the control device of the first inverter 220 and the control device of the second inverter 240 exchange a three-phase target current signal, the three-phase target current signal affects the communication cycle. This may cause problems. Therefore, the control device of the first inverter 220 and the control device of the second inverter 240 of the present disclosure can stably operate the system by transmitting and receiving the target current signal in the d-q coordinate system.

For example, a three-phase target current signal (

,

, and

) is the target current signal (

and

) can be derived from

(Equation 5)

here

can be as follows:

(Equation 6)

here

May be the phase of the grid voltage obtained through a PLL (Phase-Locked Loop).

The control device 700 controls the three-phase current of the second inverter (

,

) can be performed (920). The control device 700 uses the sensor included in the second inverter 240 to control the flow from point A2 to point A.

obtains and flows from point B2 to point B.

obtains and flows from point C2 to point C.

can be obtained.

The control device 700 of the second inverter 240 may perform step 930 of measuring the three-phase zero phase current of the second inverter. The control device 700 controls the three-phase current of the second inverter measured in step 920 (

,

) based on the three-phase zero-phase current (

) can be obtained. The control device 700 measures the measured current of phase A of the second inverter (

), the measured current of phase B of the second inverter (

), and the measured current of phase C of the second inverter (

) is the average of the three-phase zero phase current of the second inverter (

), you can perform the acquisition steps. More specifically, the control device 700 controls the three-phase zero phase current (

) can be obtained.

The control device 700 of the second inverter 240 controls the three-phase zero phase current of the second inverter (

) and the target current signal in the dq coordinate system (

and

) Based on the three-phase estimated current of the first inverter (

) can be performed (940). In addition, the control device 700 of the second inverter 240 controls the three-phase zero phase current of the second inverter (

) and three-phase target current signal (

,

, and

) Based on the three-phase estimated current of the first inverter (

) can be performed (940). More specifically, the control device 700 of the second inverter 240 controls the three-phase estimated current of the first inverter (

), you can perform the following process to obtain: The control device 700 receives a three-phase target current signal (

,

, and

), the three-phase zero phase current of the second inverter 240 (

) is subtracted to obtain the three-phase estimated current of the first inverter (

) can be performed. More specifically, the control device 700 controls the A-phase target current signal (

), the three-phase zero phase current of the second inverter 240 (

) is subtracted to obtain the estimated current of phase A of the first inverter (

) can be performed. In addition, the control device 700 provides a B-phase target current signal (

), the three-phase zero phase current of the second inverter 240 (

) is subtracted to obtain the estimated phase B current of the first inverter (

) can be performed. In addition, the control device 700 provides a C-phase target current signal (

), the three-phase zero phase current of the second inverter 240 (

) is subtracted to obtain the estimated C phase current of the first inverter (

) can be performed. However, it is not limited to this, and the control device 700 controls the three-phase zero phase current (

) to the three-phase target current signal (

,

, and

) can also be performed.

The three-phase zero current of the second inverter 240 (

) is estimated to also flow to the first inverter 240. This is because the three-phase zero phase current of the second inverter 240 (

) is assumed to be a circulating current flowing in the first inverter 220 and the second inverter 240. The first inverter 220 and the second inverter 240 provide a three-phase target current signal (

,

, and

) must be provided to the load 250, but the three-phase zero phase current (

) is measured, so the three-phase zero phase current (

It can be assumed that a current subtracted by ) is flowing. Because the three-phase zero current (

) is a circular current, so it will flow from point A2 to A and then to A1. That is, the three-phase zero phase current measured in the second inverter (

) is the three-phase target current signal of the second inverter 240 (

,

, and

) is added to the three-phase target current signal of the first inverter 220 (

,

, and

) can be deducted. Based on this estimate, the control device 700 calculates the three-phase estimated current of the first inverter (

) can be obtained.

According to the present disclosure, as can be seen in step 940, the control device 700 of the second inverter controls the three-phase estimated current of the first inverter (

), so there is no need to receive three-phase current from the control device of the first inverter. Accordingly, data transmission and reception between the control device 700 of the second inverter and the control device of the first inverter can be minimized. Additionally, the control signal for the second inverter 240 may not have an error due to communication delay, and the control device 700 of the second inverter can quickly generate the control signal for the second inverter 240. .

The control device 700 of the second inverter 240 controls the three-phase estimated current of the first inverter (

) and the three-phase current of the second inverter (

,

) based on the three-phase error current for the second inverter (

,

) can be performed (950). More specifically, the control device 700 may perform the following steps to perform the step 950 of acquiring the three-phase error current for the second inverter. The control device 700 controls the three-phase current of the second inverter (

,

), the three-phase estimated current of the first inverter 220 (

) is subtracted to obtain the three-phase error current for the second inverter (

,

) can be performed. However, it is not limited to this, and the control device 700 calculates the three-phase estimated current of the first inverter 220 (

), the three-phase current of the second inverter (

,

) can also be performed.

If steps 910 to 950 of FIG. 9 are summarized in an equation, the three-phase error current for the second inverter (

,

) can be expressed as follows.

(Equation 7)

is the d-axis current command of the inverter.

is the inverter’s q-axis current command,

is the zero phase current of the second inverter 240. here

may be the same as Equation 6. According to Equation 7, the control device 700 of the second inverter 240 does not require separate reception of the output current of the first inverter 220, and the burden of communication can be reduced.

The control device 700 controls the three-phase error current for the second inverter 240 (

,

) Based on the three-phase compensation voltage (

(however, x=a, b, or c)) may be performed in step 960. The control device 700 uses a three-phase compensation voltage (

,

), the following steps can be further performed for the step 960 of obtaining. When creating a delta current controller for Equation 3, each phase can be expressed as a PI controller as shown in Equation 8. That is, step 960 can be performed according to Equation 8 below.

(Equation 8)

here

is the three-phase compensation voltage,

is a predetermined proportional gain,

is a predetermined integral gain,

is the command current for the three-phase error current for the second inverter, s is the Laplace operator,

may be a three-phase error current for the second inverter. 1/s may refer to the integrator.

Command current for the three-phase error current for the second inverter (

) may be a command current for the three-phase error current for the first inverter. Additionally, the command current for the three-phase error current for the second inverter may be 0. This is because the target current can be reached only when the 3-phase error current is reduced to 0.

In other words, Equation 8 can be as follows.

As described above, the control device 700 of the second inverter 240 receives the three-phase command voltage (

,

,and

), there is no need to receive any other signals. Therefore, the amount of data transmitted and received between the first inverter 220 and the second inverter 240 may not be large. Therefore, delay due to communication can be minimized. Additionally, by estimating the current of the first inverter, the zero phase current can be dramatically reduced and heat generation can be reduced.

10 is a waveform diagram showing the effect of a control device according to an embodiment of the present disclosure.

FIG. 10A shows current distortion and zero-phase current occurring in the second inverter 240 due to nonlinearity between the first inverter 220 and the second inverter 240. In (A) of Figure 10

is the A-phase current included in the three-phase current of the second inverter,

is the B-phase current included in the three-phase current of the second inverter,

represents the C-phase current included in the three-phase current of the second inverter.

represents the three-phase zero phase current of the second inverter. Additionally, in Figure 10 (A)

is the A-phase current included in the three-phase current of the first inverter,

is the B-phase current included in the three-phase current of the first inverter,

represents the C-phase current included in the three-phase current of the first inverter.

represents the three-phase zero phase current of the first inverter. Referring to Figure 10 (A)

Is

It can be confirmed that it is the reverse image of . Additionally, the three-phase zero phase current of the first inverter (

) and the three-phase zero phase current of the second inverter (

), it can be confirmed that there is distortion in the three-phase current of the first inverter and the three-phase current of the second inverter.

Figure 10(B) shows removal of the zero-sequence current using the prior art. According to Figure 10(b), the prior art removes the zero-sequence current circulating in parallel inverters, but the zero-sequence current in the second inverter 240 is removed. It does not eliminate current distortion.

FIG. 10C shows the results of the control device 700 of the present disclosure suppressing zero phase current and current distortion of the second inverter 240 according to FIGS. 2, 8, and 9.

Figure 11 (A) shows the case where there is no compensation voltage. Referring to (A) of FIG. 11, it can be seen that there is a difference between the rising time and falling time of the inverter output voltage due to the difference in nonlinearity.

Figure 11 (B) shows a case of using a zero-phase current controller according to the prior art. Referring to (B) in FIG. 11, it can be seen that the difference in the inverter output voltage increases at rising time and falling time because the compensation voltage is added to all phases rather than calculating the compensation voltage for each phase. .

Figure 11 (C) shows a case of using the compensation voltage according to the present disclosure. Referring to (C) of FIG. 11, since the control device 700 of the present disclosure calculates and adds the compensation voltage for each phase, the difference between the inverter output voltage at rising time and falling time is (A) of FIG. 11 and FIG. It can be seen that there is an improvement compared to 11(B).

When there is no compensation voltage as shown in (A) of FIG. 12, it can be seen that the degree of distortion of the current varies depending on the direction of the output current of the first inverter 220 and the second inverter 240.

Figure 12 (B) shows a waveform according to the control device 700 of the present disclosure. According to the control device 700 of the present disclosure, a three-phase compensation voltage (

,

) can be seen to be different for each phase. 3-phase compensation voltage (

,

) is determined separately for each phase by equation (8). According to the control device 700 of the present disclosure, it can be confirmed that the distortion of the inverter output current is reduced and there is no difference between the inverter output currents.

So far, we have looked at various embodiments. Those skilled in the art to which this disclosure pertains will understand that the present invention can be implemented in a modified form without departing from the essential characteristics of the present invention. Therefore, the disclosed embodiments should be considered from an illustrative rather than a restrictive perspective. The scope of the present invention is indicated in the claims rather than the foregoing description, and all differences within the equivalent scope should be construed as being included in the present invention.

Meanwhile, the above-described embodiments of the present invention can be written as a program that can be executed on a computer, and can be implemented in a general-purpose digital computer that operates the program using a computer-readable recording medium. The computer-readable recording media includes storage media such as magnetic storage media (eg, ROM, floppy disk, hard disk, etc.) and optical read media (eg, CD-ROM, DVD, etc.).

Claims

In the control method of the second inverter for suppressing the circulating current of the second inverter connected in parallel with the first inverter,

Receiving a three-phase command voltage of the first inverter generated by a control device of the first inverter;

Obtaining a three-phase compensation voltage based on the three-phase zero phase current of the second inverter;

Obtaining a three-phase command voltage of the second inverter based on the three-phase command voltage of the first inverter and the three-phase compensation voltage; and

A control method of a second inverter comprising operating the second inverter based on a three-phase command voltage of the second inverter.
According to claim 1,

The step of obtaining the three-phase compensation voltage is,

Obtaining a three-phase target current signal;

measuring three-phase current of the second inverter;

Obtaining a three-phase zero phase current of the second inverter based on the three-phase current of the second inverter;

Obtaining a three-phase estimated current of the first inverter based on the three-phase zero phase current and the three-phase target current signal of the second inverter;

Obtaining a three-phase error current for the second inverter based on the estimated three-phase current of the first inverter and the three-phase current of the second inverter; and

A control method comprising obtaining a three-phase compensation voltage based on the three-phase error current for the second inverter.
According to claim 2,

The step of acquiring the three-phase estimated current of the first inverter is:

A control method comprising obtaining a three-phase estimated current of the first inverter by subtracting the three-phase zero phase current of the second inverter from the three-phase target current signal.
According to claim 2,

The step of acquiring the three-phase error current for the second inverter is:

A control method comprising obtaining the three-phase error current for the second inverter by subtracting the estimated three-phase current of the first inverter from the three-phase current of the second inverter.
According to claim 2,

The step of obtaining the three-phase compensation voltage is,

It is performed according to the formula below,

is the three-phase compensation voltage,
is the proportional gain,
is the integral gain,
is the command current for the three-phase error current for the second inverter, s is the Laplace operator, and 1/s means the integrator,
A method of controlling the three-phase error current for the second inverter.
According to claim 1,

The step of acquiring the three-phase command voltage of the second inverter is:

A control method comprising adding a three-phase command voltage of the first inverter to the three-phase compensation voltage to obtain a three-phase command voltage of the second inverter.
According to claim 1,

The step of acquiring the three-phase zero phase current of the second inverter is:

Obtaining the average of the measured current of phase A of the second inverter, the measured current of phase B of the second inverter, and the measured current of phase C of the second inverter as the three-phase zero phase current of the second inverter. Control methods including:
According to claim 3,

The step of acquiring the three-phase estimated current of the first inverter is,

A control method comprising measuring the three-phase zero phase current using a sensor included in the second inverter.
According to claim 3,

The step of acquiring the three-phase estimated current of the first inverter is,

Comprising the step of obtaining the predetermined three-phase zero phase current,

A control method in which the magnitude of the three-phase zero phase current is greater than or equal to 0.
In the control device of the second inverter for suppressing the circulating current of the second inverter connected in parallel with the first inverter,

The control device of the second inverter includes a processor and memory,

Based on the instructions stored in the memory, the processor

Receiving a three-phase command voltage of the first inverter generated by a control device of the first inverter,

Obtaining a three-phase compensation voltage based on the three-phase zero phase current of the second inverter,

Obtaining a three-phase command voltage of the second inverter based on the three-phase command voltage of the first inverter and the three-phase compensation voltage,

A control device for a second inverter that operates the second inverter based on a three-phase command voltage of the second inverter.
According to claim 10,

Based on the instructions stored in the memory, the processor

Obtain a three-phase target current signal,

Measure the three-phase current of the second inverter,

Obtaining a three-phase zero phase current of the second inverter based on the three-phase current of the second inverter,

Obtaining a three-phase estimated current of the first inverter based on the three-phase zero phase current and the three-phase target current signal of the second inverter,

Obtaining a three-phase error current for the second inverter based on the estimated three-phase current of the first inverter and the three-phase current of the second inverter,

A control device for a second inverter that obtains a three-phase compensation voltage based on the three-phase error current for the second inverter.
A computer-readable recording medium on which a control method program of the second inverter for suppressing circulating current of the second inverter connected in parallel with the first inverter is recorded,

Receiving a three-phase command voltage of the first inverter generated by a control device of the first inverter;

Obtaining a three-phase compensation voltage based on the three-phase zero phase current of the second inverter;

Obtaining a three-phase command voltage of the second inverter based on the three-phase command voltage of the first inverter and the three-phase compensation voltage; and

A computer-readable recording medium recording a control method program comprising operating the second inverter based on a three-phase command voltage of the second inverter.