WO2022164095A1 - Method and apparatus for signal processing - Google Patents

Method and apparatus for signal processing Download PDF

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WO2022164095A1
WO2022164095A1 PCT/KR2022/000679 KR2022000679W WO2022164095A1 WO 2022164095 A1 WO2022164095 A1 WO 2022164095A1 KR 2022000679 W KR2022000679 W KR 2022000679W WO 2022164095 A1 WO2022164095 A1 WO 2022164095A1
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time delay
signal
denotes
fractional time
fractional
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Jia Yan
Meiling Zhang
Shaomin ZHANG
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Samsung Electronics Co., Ltd.
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    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/32—Modifications of amplifiers to reduce non-linear distortion
    • H03F1/3241—Modifications of amplifiers to reduce non-linear distortion using predistortion circuits
    • H03F1/3258—Modifications of amplifiers to reduce non-linear distortion using predistortion circuits based on polynomial terms
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
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    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
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    • G06F7/498—Computations with decimal numbers radix 12 or 20. using counter-type accumulators
    • G06F7/4981—Adding; Subtracting
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    • G06F—ELECTRIC DIGITAL DATA PROCESSING
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    • G06F17/10—Complex mathematical operations
    • G06F17/16—Matrix or vector computation, e.g. matrix-matrix or matrix-vector multiplication, matrix factorization
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    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/189—High frequency amplifiers, e.g. radio frequency amplifiers
    • H03F3/19—High frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only
    • H03F3/195—High frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only in integrated circuits
    • H—ELECTRICITY
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    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
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    • H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
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    • H04L25/03343—Arrangements at the transmitter end
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
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    • H03F2200/451—Indexing scheme relating to amplifiers the amplifier being a radio frequency amplifier

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Abstract

The application provides a signal processing system, a signal processing method and an electronic apparatus, which can improve the identification precision of a non-linear system. A signal processing system comprises: a fractional time delay generation unit, used for performing time delay processing on an input signal of the signal processing system to generate a fractional time delay signal; an integer time delay unit, used for performing time delay processing on the fractional time delay signal to generate an integer time delay processed signal; and a model processing unit, used for processing the integer time delay processed signal according to a mathematical model of the signal processing system to obtain an output signal of the signal processing system.

Description

METHOD AND APPARATUS FOR SIGNAL PROCESSING
The application relates to the technical field of signal processing, in particular to a signal processing system, a signal processing method and an electronic apparatus.
To meet the demand for wireless data traffic having increased since deployment of 4th generation (4G) communication systems, efforts have been made to develop an improved 5th generation (5G) or pre-5G communication system. The 5G or pre-5G communication system is also called a ‘beyond 4G network’ or a ‘post long term evolution (LTE) system’. The 5G communication system is considered to be implemented in higher frequency (mmWave) bands, e.g., 60 giga-Hertz (GHz) bands, so as to accomplish higher data rates. To decrease propagation loss of the radio waves and increase the transmission distance, beamforming, massive multiple-input multiple-output (MIMO), full dimensional MIMO (FD-MIMO), array antenna, analog beamforming, and large scale antenna techniques are discussed with respect to 5G communication systems. In addition, in 5G communication systems, development for system network improvement is under way based on advanced small cells, cloud radio access networks (RANs), ultra-dense networks, device-to-device (D2D) communication, wireless backhaul, moving network, cooperative communication, coordinated multi-points (CoMP), reception-end interference cancellation and the like. In the 5G system, hybrid frequency shift keying (FSK) and Feher's quadrature amplitude modulation (FQAM) and sliding window superposition coding (SWSC) as an advanced coding modulation (ACM), and filter bank multi carrier (FBMC), non-orthogonal multiple access (NOMA), and sparse code multiple access (SCMA) as an advanced access technology have been developed.
The Internet, which is a human centered connectivity network where humans generate and consume information, is now evolving to the Internet of things (IoT) where distributed entities, such as things, exchange and process information without human intervention. The Internet of everything (IoE), which is a combination of the IoT technology and the big data processing technology through connection with a cloud server, has emerged. As technology elements, such as technologies connectivity network where humans generate and consume information, is now evolving to the Internet of things (IoT) where the cloud server has IoT implementation, a sensor network, a machine-to-machine (M2M) communication, machine type communication (MTC), and so forth have been recently researched. Such an IoT environment may provide intelligent Internet technology services that create a new value to human life by collecting and analyzing data generated among connected things. IoT may be applied to a variety of fields including smart home, smart building, smart city, smart car or connected cars, smart grid, health care, smart appliances and advanced medical services through convergence and combination between existing information technology (IT) and various industrial applications.
In line with this, various attempts have been made to apply 5G communication systems to IoT networks. For example, technologies such as a sensor network, MTC, and M2M communication may be implemented by beamforming, MIMO, and array antennas. Application of a cloud RAN as the above-described big data processing technology may also be considered to be as an example of convergence between the 5G technology and the IoT technology.
The application provides method and apparatus for signal processing.
Figures 1A and 1B show schematic diagrams of an application scenario according to some embodiments of the present application;
Figure 2 shows a schematic diagram of a signal processing system according to some embodiments of the present application;
Figure 3A shows a schematic diagram of a signal processing system according to some embodiments of the present application;
Figure 3B shows a schematic diagram of a signal processing system according to some embodiments of the present application;
Figure 3C shows a schematic diagram of a signal processing system according to some embodiments of the present application;
Figure 4 shows a schematic diagram of a signal processing system according to some embodiments of the present application;
Figure 5 shows a flow diagram of a generation method 500 of a non-linear model according to some embodiments of the present application;
Figure 6 shows a flow diagram of a generation method 600 of a non-linear model according to some embodiments of the present application;
Figure 7 shows a flow diagram of a signal processing method 700 according to some embodiments of the present application;
Figure 8 shows a flow diagram of a method 800 of generating an output signal according to some embodiments of the present application;
Figure 9 shows a schematic diagram of a base station according to some embodiments of the present application; and
Figure 10 shows a schematic diagram of an electronic apparatus according to some embodiments of the present application.
Figure 11 illustrates an apparatus according to embodiments of the present disclosure.
The application provides a signal processing system, a signal processing method and an electronic apparatus, which can improve the identification precision of a non-linear system.
According to one aspect of the present application, there is provided a signal processing system comprising:
a fractional time delay generation unit, used for performing time delay processing on an input signal of the signal processing system to generate a fractional time delay signal;
an integer time delay unit, used for performing time delay processing on the fractional time delay signal to generate an integer time delay processed signal; and
a model processing unit, used for processing the integer time delay processed signal according to a mathematical model of the signal processing system to obtain an output signal of the signal processing system.
In some embodiments, the mathematical model of the signal processing system is a generalized memory polynomial;
the fractional time delay generation unit is used for generating a first fractional time delay signal and a second fractional time delay signal;
the integer time delay unit comprises a first integer time delay module and a second integer time delay module, wherein the first integer time delay module is used for performing time delay processing on the first fractional time delay signal to output a first integer time delay signal, and the second integer time delay module is used for performing time delay processing on the second fractional time delay signal to output a second integer time delay signal; and
the model processing unit is used for processing the first integer time delay signal and the second integer time delay signal according to the generalized memory polynomial to obtain the output signal of the signal processing system.
In some embodiments, the mathematical model of the signal processing system is a generalized memory polynomial with fractional time delay:
Figure PCTKR2022000679-appb-img-000001
, wherein n denotes a sequence number of a sampling point of an input signal, x(n) is the input signal, i, j are integer time delays,
Figure PCTKR2022000679-appb-img-000002
is a non-linear function base,
Figure PCTKR2022000679-appb-img-000003
denotes a fractional time delay corresponding to tap n-i,
Figure PCTKR2022000679-appb-img-000004
denotes a fractional time delay corresponding to tap n-j, p denotes a number of non-linear bases,
Figure PCTKR2022000679-appb-img-000005
denotes a coefficient of the input signal, and y(n) denotes the output signal;
the fractional time delay generation unit is used for generating a first fractional time delay signal
Figure PCTKR2022000679-appb-img-000006
corresponding to
Figure PCTKR2022000679-appb-img-000007
and a second fractional time delay signal
Figure PCTKR2022000679-appb-img-000008
corresponding to
Figure PCTKR2022000679-appb-img-000009
;
the first integer time delay module is used for performing time delay processing on the first fractional time delay signal
Figure PCTKR2022000679-appb-img-000010
to output the second integer time delay signal
Figure PCTKR2022000679-appb-img-000011
, and the second integer time delay module is used for performing time delay processing on the second fractional time delay signal
Figure PCTKR2022000679-appb-img-000012
to output the second integer time delay signal
Figure PCTKR2022000679-appb-img-000013
; and
the model processing unit comprises a non-linear function lookup table, a multiplier and an accumulator,
wherein the non-linear function lookup table is used for generating
Figure PCTKR2022000679-appb-img-000014
according to
Figure PCTKR2022000679-appb-img-000015
and
Figure PCTKR2022000679-appb-img-000016
;
the multiplier is used for generating a product of
Figure PCTKR2022000679-appb-img-000017
and
Figure PCTKR2022000679-appb-img-000018
; and
the accumulator is user for generating, the output signal y(n) of the signal processing according to a product of
Figure PCTKR2022000679-appb-img-000019
and
Figure PCTKR2022000679-appb-img-000020
.
In some embodiments, the signal processing system further comprises a processor used for determining
Figure PCTKR2022000679-appb-img-000021
,
Figure PCTKR2022000679-appb-img-000022
, and
Figure PCTKR2022000679-appb-img-000023
in the generalized memory polynomial with fractional time delay.
In some embodiments, the signal processing system further comprises a signal distribution unit used for inputtingthe first fractional time delay signal
Figure PCTKR2022000679-appb-img-000024
generated by the fractional time delay generation unit into the first integer time delay module and inputting the second fractional time delay signal
Figure PCTKR2022000679-appb-img-000025
into the second integer time delay module.
In some embodiments, ranges of values of the
Figure PCTKR2022000679-appb-img-000026
and the
Figure PCTKR2022000679-appb-img-000027
are predetermined discrete sets, and the processor determines
Figure PCTKR2022000679-appb-img-000028
,
Figure PCTKR2022000679-appb-img-000029
, and
Figure PCTKR2022000679-appb-img-000030
in the generalized memory polynomial with fractional time delay in such a manner that:
matrix A is initialized as an empty matrix, set
Figure PCTKR2022000679-appb-img-000031
is initialized as an empty set, and parameter
Figure PCTKR2022000679-appb-img-000032
is initialized as y, wherein y denotes a target signal;
regarding each group of values for （i，j）,
Figure PCTKR2022000679-appb-img-000033
is determined such that
Figure PCTKR2022000679-appb-img-000034
is largest, wherein
Figure PCTKR2022000679-appb-img-000035
is a non-linear base of the generalized memory polynomial with fractional time delay, wherein
Figure PCTKR2022000679-appb-img-000036
,
wherein denotes a conjugate matrix of matrix
Figure PCTKR2022000679-appb-img-000037
, and
Figure PCTKR2022000679-appb-img-000038
denotes a group of values for
Figure PCTKR2022000679-appb-img-000039
;
matrix A is updated according to
Figure PCTKR2022000679-appb-img-000040
, and
Figure PCTKR2022000679-appb-img-000041
denotes an augmented matrix;
Figure PCTKR2022000679-appb-img-000042
is updated according to
Figure PCTKR2022000679-appb-img-000043
, wherein pinv(A) denotes a pseudo inverse matrix of the matrix A;
Figure PCTKR2022000679-appb-img-000044
is added to set
Figure PCTKR2022000679-appb-img-000045
; and
a product of pinv(A) and y is used as
Figure PCTKR2022000679-appb-img-000046
.
In some embodiments, ranges of values of the
Figure PCTKR2022000679-appb-img-000047
and the
Figure PCTKR2022000679-appb-img-000048
are predetermined continuous intervals, and the processor determines
Figure PCTKR2022000679-appb-img-000049
,
Figure PCTKR2022000679-appb-img-000050
, and
Figure PCTKR2022000679-appb-img-000051
in the generalized memory polynomial with fractional time delay in such a manner that:
Figure PCTKR2022000679-appb-img-000052
is initialized as 0 and
Figure PCTKR2022000679-appb-img-000053
is initialized as 0; and
regarding each group of values for （i，j）, following operations are performed until
Figure PCTKR2022000679-appb-img-000054
is less than a predetermined threshold, the following operations including that
a value of
Figure PCTKR2022000679-appb-img-000055
is determined according to
Figure PCTKR2022000679-appb-img-000056
, wherein
Figure PCTKR2022000679-appb-img-000057
denotes a pseudo inverse matrix of
Figure PCTKR2022000679-appb-img-000058
,
Figure PCTKR2022000679-appb-img-000059
wherein
Figure PCTKR2022000679-appb-img-000060
denotes a coefficient of a fractional time delay filter;
perturbation quantity
Figure PCTKR2022000679-appb-img-000061
is determined according to
Figure PCTKR2022000679-appb-img-000062
, wherein the perturbation quantity
Figure PCTKR2022000679-appb-img-000063
is a perturbation to
Figure PCTKR2022000679-appb-img-000064
when a value of
Figure PCTKR2022000679-appb-img-000065
is taken as
Figure PCTKR2022000679-appb-img-000066
, wherein
Figure PCTKR2022000679-appb-img-000067
Figure PCTKR2022000679-appb-img-000068
Figure PCTKR2022000679-appb-img-000069
wherein
Figure PCTKR2022000679-appb-img-000070
denotes a derivative of
Figure PCTKR2022000679-appb-img-000071
at
Figure PCTKR2022000679-appb-img-000072
with respect to
Figure PCTKR2022000679-appb-img-000073
,
Figure PCTKR2022000679-appb-img-000074
is determined according to the following formula:
Figure PCTKR2022000679-appb-img-000075
; and
Figure PCTKR2022000679-appb-img-000076
and
Figure PCTKR2022000679-appb-img-000077
are updated by means of
Figure PCTKR2022000679-appb-img-000078
Figure PCTKR2022000679-appb-img-000079
According to an aspect of the present application, there is provided a generation method of a non-linear model, wherein the non-linear model is a generalized memory polynomial with fractional time delay:
Figure PCTKR2022000679-appb-img-000080
, wherein n denotes a sequence number of a sampling point of an input signal, x(n) is the input signal, i, j are integer time delays,
Figure PCTKR2022000679-appb-img-000081
is a non-linear function base,
Figure PCTKR2022000679-appb-img-000082
denotes a fractional time delay corresponding to tap n-i,
Figure PCTKR2022000679-appb-img-000083
denotes a fractional time delay corresponding to tap n-j, p denotes a number of non-linear bases,
Figure PCTKR2022000679-appb-img-000084
denotes a coefficient of the input signal, and y(n) denotes the output signal, and ranges of values of
Figure PCTKR2022000679-appb-img-000085
and
Figure PCTKR2022000679-appb-img-000086
are predetermined discrete sets; and the generation method comprises that
matrix A is initialized as an empty matrix, set
Figure PCTKR2022000679-appb-img-000087
is initialized as an empty set, and parameter
Figure PCTKR2022000679-appb-img-000088
is initialized as y, wherein y denotes a target signal;
regarding each group of values for （i，j）,
Figure PCTKR2022000679-appb-img-000089
is determined such that
Figure PCTKR2022000679-appb-img-000090
is largest, wherein
Figure PCTKR2022000679-appb-img-000091
is a non-linear base of the generalized memory polynomial with fractional time delay, wherein
Figure PCTKR2022000679-appb-img-000092
,
wherein denotes a conjugate matrix of matrix
Figure PCTKR2022000679-appb-img-000093
, and
Figure PCTKR2022000679-appb-img-000094
denotes a group of values for
Figure PCTKR2022000679-appb-img-000095
;
matrix A is updated according to
Figure PCTKR2022000679-appb-img-000096
, and
Figure PCTKR2022000679-appb-img-000097
denotes an augmented matrix;
Figure PCTKR2022000679-appb-img-000098
is updated according to
Figure PCTKR2022000679-appb-img-000099
, wherein pinv(A) denotes a pseudo inverse matrix of the matrix A;
Figure PCTKR2022000679-appb-img-000100
is added to set
Figure PCTKR2022000679-appb-img-000101
; and
a product of pinv(A) and y is used as
Figure PCTKR2022000679-appb-img-000102
.
According to an aspect of the present application, there is provided a generation method of a non-linear model, wherein the non-linear model is a generalized memory polynomial with fractional time delay:
Figure PCTKR2022000679-appb-img-000103
wherein n denotes a sequence number of a sampling point of an input signal, x(n) is the input signal, i, j are integer time delays,
Figure PCTKR2022000679-appb-img-000104
is a non-linear function base,
Figure PCTKR2022000679-appb-img-000105
denotes a fractional time delay corresponding to tap n-i,
Figure PCTKR2022000679-appb-img-000106
denotes a fractional time delay corresponding to tap n-j, p denotes a number of non-linear bases,
Figure PCTKR2022000679-appb-img-000107
denotes a coefficient of the input signal, and y(n) denotes the output signal, and ranges of values of
Figure PCTKR2022000679-appb-img-000108
and
Figure PCTKR2022000679-appb-img-000109
are predetermined continuous intervals; and the generation method comprises that
Figure PCTKR2022000679-appb-img-000110
is initialized as 0 and
Figure PCTKR2022000679-appb-img-000111
is initialized as 0; and
regarding each group of values for （i，j）, following operations are performed until
Figure PCTKR2022000679-appb-img-000112
is less than a predetermined threshold, the following operations including that
a value of
Figure PCTKR2022000679-appb-img-000113
is determined according to
Figure PCTKR2022000679-appb-img-000114
, wherein
Figure PCTKR2022000679-appb-img-000115
denotes a pseudo inverse matrix of
Figure PCTKR2022000679-appb-img-000116
,
Figure PCTKR2022000679-appb-img-000117
wherein
Figure PCTKR2022000679-appb-img-000118
denotes a coefficient of a fractional time delay filter;
perturbation quantity
Figure PCTKR2022000679-appb-img-000119
is determined according to
Figure PCTKR2022000679-appb-img-000120
, wherein the perturbation quantity
Figure PCTKR2022000679-appb-img-000121
is a perturbation to
Figure PCTKR2022000679-appb-img-000122
when a value of
Figure PCTKR2022000679-appb-img-000123
is taken as
Figure PCTKR2022000679-appb-img-000124
, wherein
Figure PCTKR2022000679-appb-img-000125
Figure PCTKR2022000679-appb-img-000126
Figure PCTKR2022000679-appb-img-000127
wherein
Figure PCTKR2022000679-appb-img-000128
denotes a derivative of
Figure PCTKR2022000679-appb-img-000129
at
Figure PCTKR2022000679-appb-img-000130
with respect to
Figure PCTKR2022000679-appb-img-000131
,
Figure PCTKR2022000679-appb-img-000132
is determined according to the following formula:
Figure PCTKR2022000679-appb-img-000133
; and
Figure PCTKR2022000679-appb-img-000134
and
Figure PCTKR2022000679-appb-img-000135
are updated by means of
Figure PCTKR2022000679-appb-img-000136
Figure PCTKR2022000679-appb-img-000137
According to an aspect of the present application, there is provided a signal processing method, comprising:
performing time delay processing on an input signal of the signal processing system to generate a fractional time delay signal;
performing time delay processing on the fractional time delay signal to generate an integer time delay processed signal; and
processing the integer time delay processed signal according to a mathematical model of the signal processing system, to obtain an output signal of the signal processing system.
According to an aspect of the present application, there is provided an electronic apparatus, comprising:
a memory; and
a processor for performing the generation method of a non-linear model or a signal processing method according to an embodiment of the present application.
According to an aspect of the present application, there is provided a storage medium storing a program comprising instructions, wherein the instructions, when executed by an electronic apparatus, cause the electronic apparatus to perform the generation method of a non-linear model or a signal processing method according to an embodiment of the present application.
According to an aspect of the present application, there is provided a base station, comprising:
the signal processing system according to the present application; and
a power amplifier unit.
In summary, according to the signal processing system provided by the embodiment of the present application, the fractional time delay signal can be generated by the fractional time delay generation unit on the premise of not increasing the sampling rate, and the output signal is generated on the basis of the mathematical model of the signal processing system, so that the identification precision is improved, and the increase of power consumption caused by the increase of the sampling rate is avoided.
For the purposes, technical solutions, and advantages of this application to become more fully apparent, further details of the application are provided with reference to the accompanying drawings and embodiments.
In the application scenarios of automation control, base station communication and audio signal processing, the identification of non-linear system can be realized by discrete signal sampling. With the increase of system bandwidth and the improvement of identification precision, identification solutions of non-linear system usually increase the sampling frequency to obtain better time resolution and improve the identification precision.
However, increasing the sampling frequency increases the amount of computation and thus hardware power consumption.
Therefore, on the premise of not increasing hardware power consumption, how to improve identification precision is a technical problem to be solved.
Figures 1A and 1B show schematic diagrams of an application scenario according to some embodiments of the present application.
As shown in figures 1A and 1B, an application scenario shows a non-linear system 110 and a signal processing system 120. Here, the signal processing system 120 may be at an input or output of the non-linear system 110. Here, the non-linear system 110 may be, for example, a non-linear device in a scene of automation control, digital audio processing, base station communication, etc. For example, the non-linear system 110 is a power amplifier unit in a base station, but is not limited thereto.
As shown in figure 1A, in a scenario where the signal processing system 120 is at the input of the non-linear system 110, the input signal may first be pre-distorted by the signal processing system 120, resulting in a pre-distorted signal. The pre-distorted signal enters the non-linear system 110. The non-linear system 110 may output a signal. The signal processing system 120 may compensate for non-linearities of the non-linear system 110 to suppress distortion by the non-linear system 110.
As shown in figure 1B, in a scenario where the signal processing system 120 is at the output of the non-linear system 110, the signal processing system 120 may process the output signal of the non-linear system 110, i.e., use the output signal of the non-linear system 110 as an input signal to the signal processing system 120 to post-process the output signal of the non-linear system 110 to suppress non-linear distortion of the output signal of the non-linear system 110. For example, the non-linear system 110 is an audio signal processing system. Signal processing system 120 may process the output signal to cancel echoes in the audio signal.
Figure 2 shows a schematic diagram of a signal processing system according to some embodiments of the present application. The signal processing system 120 may be implemented as an FPGA or ASIC hardware module.
As shown in figure 2, the signal processing system 120 may include a fractional time delay generation unit 121, an integer time delay unit 122, and a model processing unit 123.
The fractional time delay generation unit 121 is used for performing time delay processing on an input signal of the signal processing system to generate a fractional time delay signal.
The integer time delay unit 122 is used for performing time delay processing on the fractional time delay signal to generate an integer time delay processed signal.
The model processing unit 123 is used for processing the integer time delay processed signal according to a mathematical model of the signal processing system to obtain an output signal of the signal processing system.
In summary, according to the signal processing system provided by the embodiment of the present application, the fractional time delay signal can be generated by the fractional time delay generation unit on the premise of not increasing the sampling rate, and the output signal is generated on the basis of the mathematical model of the signal processing system, so that the identification precision is improved, and the increase of power consumption caused by the increase of the sampling rate is avoided.
Figure 3A shows a schematic diagram of a signal processing system according to some embodiments of the present application.
Here, the mathematical model of the signal processing system is a generalized memory polynomial. The fractional time delay generation unit 121 is used for generating a first fractional time delay signal and a second fractional time delay signal.
The integer time delay unit 122 comprises a first integer time delay module 124 and a second integer time delay module 125. The first integer time delay module 124 is used for performing time delay processing on the first fractional time delay signal to output a first integer time delay signal, and the second integer time delay module 125 is used for performing time delay processing on the second fractional time delay signal to output a second integer time delay signal.
The model processing unit 123 is used for processing the first integer time delay signal and the second integer time delay signal according to the generalized memory polynomial to obtain the output signal of the signal processing system. In summary, according to the signal processing system provided by the embodiment of the application, the first fractional time delay signal and the second fractional time delay signal can be generated by the fractional time delay generation unit on the premise of not increasing the sampling rate, and the output signal is generated on the basis of the mathematical model of the generalized memory polynomial of the signal processing system, which is beneficial to improving the identification precision and avoiding the increase of power consumption caused by increasing the sampling rate. Figure 3B shows a schematic diagram of a signal processing system according to some embodiments of the present application.
As shown in figure 3B, the signal processing system 120 may include a fractional time delay generation unit 121, an integer time delay unit 122, and a model processing unit 123. The integer time delay unit 122 may include a first integer time delay module 124 and a second integer time delay module 125. The model processing unit 123 includes a non-linear function lookup table 126, a multiplier 127 and an accumulator 128.
The mathematical model of the signal processing system 120 is a generalized memory polynomial (GMP) with fractional time delay:
Figure PCTKR2022000679-appb-img-000138
, wherein n denotes a sequence number of a sampling point of an input signal,
Figure PCTKR2022000679-appb-img-000139
is the input signal, i, j are integer time delays,
Figure PCTKR2022000679-appb-img-000140
is a non-linear function base,
Figure PCTKR2022000679-appb-img-000141
denotes a fractional time delay corresponding to tap n-i,
Figure PCTKR2022000679-appb-img-000142
denotes a fractional time delay corresponding to tap n-j, p denotes a number of non-linear bases,
Figure PCTKR2022000679-appb-img-000143
denotes a coefficient of the input signal, and
Figure PCTKR2022000679-appb-img-000144
denotes the output signal of the signal processing system.
The fractional time delay generation unit 121 is used for generating a first fractional time delay signal
Figure PCTKR2022000679-appb-img-000145
corresponding to
Figure PCTKR2022000679-appb-img-000146
and a second fractional time delay signal
Figure PCTKR2022000679-appb-img-000147
corresponding to
Figure PCTKR2022000679-appb-img-000148
.
The first integer time delay module 124 is used for performing time delay processing on the first fractional time delay signal
Figure PCTKR2022000679-appb-img-000149
to output the first integer time delay signal
Figure PCTKR2022000679-appb-img-000150
. The second integer time delay module 125 is used for performing time delay processing on the second fractional time delay signal
Figure PCTKR2022000679-appb-img-000151
to output the second integer time delay signal
Figure PCTKR2022000679-appb-img-000152
.
The non-linear function lookup table 126 is used for generating
Figure PCTKR2022000679-appb-img-000153
according to
Figure PCTKR2022000679-appb-img-000154
and
Figure PCTKR2022000679-appb-img-000155
.
The multiplier 127 is used for generating a product of
Figure PCTKR2022000679-appb-img-000156
and
Figure PCTKR2022000679-appb-img-000157
.
It should be noted that for each group of values for （i，j）, the signal processing system 120 is configured with one corresponding branch for outputting a product of
Figure PCTKR2022000679-appb-img-000158
,
Figure PCTKR2022000679-appb-img-000159
and
Figure PCTKR2022000679-appb-img-000160
. Each branch includes a first integer time delay module 124, a second integer time delay module 125, a non-linear function lookup table 126, and a multiplier 127.
The accumulator 128 is used for generating the output signal
Figure PCTKR2022000679-appb-img-000161
of the signal processing system according to a product of
Figure PCTKR2022000679-appb-img-000162
and
Figure PCTKR2022000679-appb-img-000163
. Here, the accumulator 128 may accumulate the product of
Figure PCTKR2022000679-appb-img-000164
,
Figure PCTKR2022000679-appb-img-000165
and
Figure PCTKR2022000679-appb-img-000166
corresponding to each group of values for （i，j） to obtain the output signal
Figure PCTKR2022000679-appb-img-000167
.
In summary, according to the signal processing system provided by the embodiment of the present application, the fractional time delay signal can be generated by the fractional time delay generation unit on the premise of not increasing the sampling rate, and the output signal is generated on the basis of the mathematical model of the generalized memory polynomial with fractional time delay, so that the identification precision is improved, and the increase of power consumption caused by the increase of the sampling rate is avoided.
Figure 3C shows a schematic diagram of a signal processing system 120 according to some embodiments of the present application.
As shown in figure 3C, the signal processing system 120 may include a fractional time delay generation unit 121, an integer time delay unit 122, a model processing unit 123, and a signal distribution unit 129. The integer time delay unit 122 may include a first integer time delay module 124 and a second integer time delay module 125. The model processing unit 123 includes a non-linear function lookup table 126, a multiplier 127 and an accumulator 128.
The signal distribution unit 129 is used for inputting the fractional time delay signal
Figure PCTKR2022000679-appb-img-000168
generated by the fractional time delay generation unit 121 into the first integer time delay module 124 and inputting the fractional time delay signal
Figure PCTKR2022000679-appb-img-000169
into the second integer time delay module 125.
In some embodiments, the time delay characteristics of the non-linear system 110 are relatively stable, and embodiments of the present application may generate parameters in the mathematical model of the signal processing system off-line. For example, embodiments of the present application may determine the parameters
Figure PCTKR2022000679-appb-img-000170
,
Figure PCTKR2022000679-appb-img-000171
, and
Figure PCTKR2022000679-appb-img-000172
in a generalized memory polynomial with fractional time delay in an electronic apparatus. Here, the electronic apparatus may be, for example, a desktop computer, a notebook computer, or a cloud computer.
In some embodiments, the parameters of the signal processing system 120 need to be adjusted during operation of the non-linear system 110. In order to determine the parameters of the signal processing system 120 during operation of the non-linear system 110, embodiments of the present application may calculate the parameters through the structure of figure 4.
Figure 4 shows a schematic diagram of a signal processing system 120 according to some embodiments of the present application.
As shown in figure 4, the signal processing system 120 may include a fractional time delay generation unit 121, an integer time delay unit 122, a model processing unit 123, a signal distribution unit 129, and a processor 130. The integer time delay unit 122 may include a first integer time delay module 124 and a second integer time delay module 125. The model processing unit 123 includes a non-linear function lookup table 126, a multiplier 127 and an accumulator 128.
The signal distribution unit 129 is used for inputting the fractional time delay signal
Figure PCTKR2022000679-appb-img-000173
generated by the fractional time delay generation unit 121 into the first integer time delay module 124 and inputting the fractional time delay signal
Figure PCTKR2022000679-appb-img-000174
into the second integer time delay module 125.
The processor 130 is used for determining
Figure PCTKR2022000679-appb-img-000175
,
Figure PCTKR2022000679-appb-img-000176
, and
Figure PCTKR2022000679-appb-img-000177
in the generalized memory polynomial with fractional time delay.
For example, figure 5 shows a flow diagram of a generation method 500 of a non-linear model according to some embodiments of the present application. The method 500 may be performed, for example, in an electronic apparatus or in the processor 130. The non-linear model is a generalized memory polynomial with fractional time delay:
Figure PCTKR2022000679-appb-img-000178
, wherein n denotes a sequence number of a sampling point of an input signal,
Figure PCTKR2022000679-appb-img-000179
is the input signal, i, j are integer time delays,
Figure PCTKR2022000679-appb-img-000180
is a non-linear function base,
Figure PCTKR2022000679-appb-img-000181
denotes a fractional time delay corresponding to tap n-i,
Figure PCTKR2022000679-appb-img-000182
denotes a fractional time delay corresponding to tap n-j, p denotes a number of non-linear bases,
Figure PCTKR2022000679-appb-img-000183
denotes a coefficient of the input signal, and y(n) denotes the output signal. Ranges of values of
Figure PCTKR2022000679-appb-img-000184
and
Figure PCTKR2022000679-appb-img-000185
are predetermined discrete sets. Here, ranges of values of
Figure PCTKR2022000679-appb-img-000186
and
Figure PCTKR2022000679-appb-img-000187
are, for example,
Figure PCTKR2022000679-appb-img-000188
.
As shown in figure 5, in step S501, matrix A is initialized as an empty matrix, set
Figure PCTKR2022000679-appb-img-000189
is initialized as an empty set, and parameter
Figure PCTKR2022000679-appb-img-000190
is initialized as y, wherein y denotes a target signal. The target signal is for example a sampling signal.
Regarding each group of values for （i，j）, the method 500 can perform steps S502-S505.
In step S502,
Figure PCTKR2022000679-appb-img-000191
is determined such that
Figure PCTKR2022000679-appb-img-000192
is largest, wherein
Figure PCTKR2022000679-appb-img-000193
is a non-linear base of the generalized memory polynomial with fractional time delay, wherein
Figure PCTKR2022000679-appb-img-000194
,
wherein in matrix
Figure PCTKR2022000679-appb-img-000195
, a previous action of
Figure PCTKR2022000679-appb-img-000196
is
Figure PCTKR2022000679-appb-img-000197
,
and a next action is
Figure PCTKR2022000679-appb-img-000198
.
Figure PCTKR2022000679-appb-img-000199
denotes a conjugate matrix of matrix A
Figure PCTKR2022000679-appb-img-000200
, and
Figure PCTKR2022000679-appb-img-000201
denotes a group of values for (
Figure PCTKR2022000679-appb-img-000202
).
In step S503, matrix A is updated according to
Figure PCTKR2022000679-appb-img-000203
, and
Figure PCTKR2022000679-appb-img-000204
denotes an augmented matrix.
In step S504,
Figure PCTKR2022000679-appb-img-000205
is updated according to
Figure PCTKR2022000679-appb-img-000206
, wherein pinv(A) denotes a pseudo inverse matrix of the matrix A.
In step S505,
Figure PCTKR2022000679-appb-img-000207
is added to set
Figure PCTKR2022000679-appb-img-000208
.
Here, regarding each group of values for （i，j）, in an embodiment of the present application, after
Figure PCTKR2022000679-appb-img-000209
is determined in step S502,
Figure PCTKR2022000679-appb-img-000210
is added to matrix A in step S503, which means that matrix A is updated to an augmented matrix added with
Figure PCTKR2022000679-appb-img-000211
. In addition, in the embodiment of the present application, y_res is updated in step S504, and a group of values for
Figure PCTKR2022000679-appb-img-000212
is added to set
Figure PCTKR2022000679-appb-img-000213
.
On such basis, the method 500 can perform step S506, and a product of (A) and y is used as
Figure PCTKR2022000679-appb-img-000214
.
In summary, the method 500 can determine parameters in the non-linear model for scenarios where
Figure PCTKR2022000679-appb-img-000215
and
Figure PCTKR2022000679-appb-img-000216
are discrete values.
Figure 6 shows a flow diagram of a generation method 500 for a non-linear model according to some embodiments of the present application. The method 500 may be performed, for example, in an electronic apparatus or in the processor 130.
The non-linear model is a generalized memory polynomial with fractional time delay:
Figure PCTKR2022000679-appb-img-000217
, wherein n denotes a sequence number of a sampling point of an input signal, x(n) is the input signal, i, j are integer time delays,
Figure PCTKR2022000679-appb-img-000218
is a non-linear function base,
Figure PCTKR2022000679-appb-img-000219
denotes a fractional time delay corresponding to tap n-i,
Figure PCTKR2022000679-appb-img-000220
denotes a fractional time delay corresponding to tap n-j, p denotes a number of non-linear bases,
Figure PCTKR2022000679-appb-img-000221
denotes a coefficient of the input signal, and y(n) denotes the output signal. Ranges of values of
Figure PCTKR2022000679-appb-img-000222
and
Figure PCTKR2022000679-appb-img-000223
are predetermined continuous intervals, for example [0, 1].
In step S601,
Figure PCTKR2022000679-appb-img-000224
is initialized as 0 and
Figure PCTKR2022000679-appb-img-000225
is initialized as 0.
Regarding each group of values for （i，j）, steps S602-S604 are performed repeatedly in the method 600 until
Figure PCTKR2022000679-appb-img-000226
is less than a predetermined threshold. Here, the predetermined threshold value is determined according to the specific application scenario, e.g. 0.1.
In step S602, a value of α_ijp is determined according to
Figure PCTKR2022000679-appb-img-000227
, wherein
Figure PCTKR2022000679-appb-img-000228
denotes a pseudo inverse matrix of
Figure PCTKR2022000679-appb-img-000229
,
Figure PCTKR2022000679-appb-img-000230
wherein i in each row
Figure PCTKR2022000679-appb-img-000231
in
Figure PCTKR2022000679-appb-img-000232
ranges from 1 to p, and n in each column changes.
For example, a previous column of elements for the row where
Figure PCTKR2022000679-appb-img-000233
locates is
Figure PCTKR2022000679-appb-img-000234
.
A previous row of elements for the column where
Figure PCTKR2022000679-appb-img-000235
locates is
Figure PCTKR2022000679-appb-img-000236
.
Figure PCTKR2022000679-appb-img-000237
denotes a coefficient of a fractional time delay filter, which for example can be expressed as a Lagrangian difference polynomial.
In step S603, perturbation quantity
Figure PCTKR2022000679-appb-img-000238
is determined according to
Figure PCTKR2022000679-appb-img-000239
, wherein the perturbation quantity
Figure PCTKR2022000679-appb-img-000240
is a perturbation to
Figure PCTKR2022000679-appb-img-000241
when a value of
Figure PCTKR2022000679-appb-img-000242
is taken as
Figure PCTKR2022000679-appb-img-000243
, wherein
Figure PCTKR2022000679-appb-img-000244
Figure PCTKR2022000679-appb-img-000245
Figure PCTKR2022000679-appb-img-000246
wherein
Figure PCTKR2022000679-appb-img-000247
denotes a derivative of
Figure PCTKR2022000679-appb-img-000248
at
Figure PCTKR2022000679-appb-img-000249
with respect to
Figure PCTKR2022000679-appb-img-000250
, and
Figure PCTKR2022000679-appb-img-000251
is determined according to the following formula:
Figure PCTKR2022000679-appb-img-000252
; and
In step S604,
Figure PCTKR2022000679-appb-img-000253
and
Figure PCTKR2022000679-appb-img-000254
are updated by means of
Figure PCTKR2022000679-appb-img-000255
Figure PCTKR2022000679-appb-img-000256
In summary, the method 600 can determine parameters in the non-linear model for scenarios where
Figure PCTKR2022000679-appb-img-000257
and
Figure PCTKR2022000679-appb-img-000258
are continuous values.
Figure 7 shows a flow diagram of a signal processing method 700 according to some embodiments of the present application. The signal processing method 700 may be performed, for example, in the signal processing system 120 or in an electronic apparatus.
As shown in figure 7, in step S701, time delay processing is performed on an input signal of the signal processing system to generate a fractional time delay signal.
In step S702, time delay processing is performed on the fractional time delay signal to generate an integer time delay processed signal.
In step S703, the integer time delay processed signal is processed according to a mathematical model of the signal processing system, to obtain an output signal of the signal processing system.
In summary, according to the signal processing method provided by the embodiment of the invention, the fractional time delay signal can be generated on the premise of not increasing the sampling rate, and the output signal is generated on the basis of the mathematical model of the signal processing system, so that the identification precision is improved, and the increase of power consumption caused by the increase of the sampling rate is avoided.
In some embodiments, the mathematical model of the signal processing system is a generalized memory polynomial. Step S701 may generate a first fractional time delay signal and a second fractional time delay signal. Step S702 may perform a time delay processing on the first fractional time delay signal to output a first integer time delay signal and perform a time delay processing on the second fractional time delay signal to output a second integer time delay signal. Step S703 processes the first integer time delay signal and the second integer time delay signal according to the generalized memory polynomial to obtain an output signal of the signal processing system. Therefore, according to the signal processing method provided by the embodiment of the invention, the first fractional time delay signal and the second fractional time delay signal are generated on the premise of not increasing the sampling rate, and the output signal is generated on the basis of the mathematical model of the generalized memory polynomial of the signal processing system, so that the identification precision is improved, and the increase of power consumption caused by the increase of the sampling rate is avoided.
In some embodiments, the mathematical model of the signal processing system 120 is a generalized memory polynomial of fractional time delay:
Figure PCTKR2022000679-appb-img-000259
,
wherein n denotes a sequence number of a sampling point of an input signal, x(n) is the input signal, i, j are integer time delays,
Figure PCTKR2022000679-appb-img-000260
is a non-linear function base,
Figure PCTKR2022000679-appb-img-000261
denotes a fractional time delay corresponding to tap n-i,
Figure PCTKR2022000679-appb-img-000262
denotes a fractional time delay corresponding to tap n-j, p denotes a number of non-linear bases,
Figure PCTKR2022000679-appb-img-000263
denotes a coefficient of the input signal, and y(n) denotes the output signal.
In step S701, a first fractional time delay signal
Figure PCTKR2022000679-appb-img-000264
corresponding to
Figure PCTKR2022000679-appb-img-000265
and a second fractional time delay signal
Figure PCTKR2022000679-appb-img-000266
corresponding to
Figure PCTKR2022000679-appb-img-000267
can be generated.
In step S702, time delay processing can be performed on the first fractional time delay signal
Figure PCTKR2022000679-appb-img-000268
to output the first integer time delay signal
Figure PCTKR2022000679-appb-img-000269
, and time delay processing can be performed on the second fractional time delay signal
Figure PCTKR2022000679-appb-img-000270
to output the second integer time delay signal
Figure PCTKR2022000679-appb-img-000271
.
Step S703 can be implemented as the method 800.
As shown in figure 8, in step S801,
Figure PCTKR2022000679-appb-img-000272
is generated according to
Figure PCTKR2022000679-appb-img-000273
and
Figure PCTKR2022000679-appb-img-000274
.
In step S802, a product of
Figure PCTKR2022000679-appb-img-000275
and
Figure PCTKR2022000679-appb-img-000276
is generated.
In step S803, the output signal y(n) of the signal processing system is generated according to the product of
Figure PCTKR2022000679-appb-img-000277
and
Figure PCTKR2022000679-appb-img-000278
.
In summary, according to the method 800 of the embodiments of the present application, the first fractional time delay signal and the second fractional time delay signal are generated on the premise of not increasing the sampling rate, and the output signal is generated on the basis of the mathematical model of the generalized memory polynomial with the fractional time delay, so that the identification precision is improved, and the increase of power consumption caused by the increase of the sampling rate is avoided.
Figure 9 shows a schematic diagram of a base station according to some embodiments of the present application.
As shown in figure 9, the base station includes a signal processing system 120 and a power amplifier unit 140.
The signal processing system 120 is at the input of a power amplifier unit 140. The signal processing system 120 may perform a pre-distortion process to obtain a pre-distorted signal. The pre-distorted signal enters the power amplifier unit 140. The power amplifier unit 140 may output an amplified signal. The signal processing system 120 may compensate for the non-linearity of the power amplifier unit 140 in order to suppress distortion of the power amplifier unit 140.
Figure 10 shows a schematic diagram of an electronic apparatus according to some embodiments of the present application. As shown in figure 10, the electronic apparatus includes one or more processors (CPU) 1002, a communication module 1004, a memory 1006, a user interface 1010, and a communication bus 1008 for interconnecting these components.
The processor 1002 can receive and transmit data through the communication module 1004 to enable network communication and/or local communication.
The user interface 1010 includes one or more output devices 1012 that include one or more speakers and one or more screens. The user interface 1010 also includes one or more input devices 1014. The user interface 1010 may be, for example but not limited to, a button.
The memory 1006 may be a high speed random access memory, such as DRAM, SRAM, DDR RAM, or other random access solid state memory device; or non-volatile memory, such as one or more magnetic disk storage devices, optical disk storage devices, flash memory devices, or other non-volatile solid state storage devices.
The memory 1006 stores a set of instructions executable by the processor 1002, including:
an operating system 1016 including programs for processing various basic system services and for performing hardware-related tasks;
an application 1018, includes various programs for implementing the solutions described above. Such a program can implement the processing flow in the embodiments described above, which may include, for example, a generation method of a non-linear model or a signal processing method.
Figure 11 illustrates an apparatus according to embodiments of the present disclosure.
Referring to the figure 11, the apparatus 1100 may include a processor 1110, a transceiver 1120 and a memory 1130. However, all of the illustrated components are not essential. The apparatus 1100 may be implemented by more or less components than those illustrated in figure 11. In addition, the processor 1110 and the transceiver 1120 and the memory 1130 may be implemented as a single chip according to another embodiment.
The aforementioned components will now be described in detail.
The processor 1110 may include one or more processors or other processing devices that control the proposed function, process, and/or method. Operation of the apparatus 1100 may be implemented by the processor 1110.
The transceiver 1120 may include a RF transmitter for up-converting and amplifying a transmitted signal, and a RF receiver for down-converting a frequency of a received signal. However, according to another embodiment, the transceiver 1120 may be implemented by more or less components than those illustrated in components.
The transceiver 1120 may be connected to the processor 1110 and transmit and/or receive a signal. The signal may include control information and data. In addition, the transceiver 1120 may receive the signal through a wireless channel and output the signal to the processor 1110. The transceiver 1120 may transmit a signal output from the processor 1110 through the wireless channel.
The memory 1130 may store the control information or the data included in a signal obtained by the apparatus 1100. The memory 1130 may be connected to the processor 1110 and store at least one instruction or a protocol or a parameter for the proposed function, process, and/or method. The memory 1130 may include read-only memory (ROM) and/or random access memory (RAM) and/or hard disk and/or CD-ROM and/or DVD and/or other storage devices.
In addition, each embodiment of the present application may be implemented by a data processing program executed by a data processing apparatus such as a computer. Obviously, the data processing program constitutes the application. In addition, the data processing program, which is usually stored in a storage medium, is executed by directly reading the program out of the storage medium or by installing or copying the program into a storage device (such as a hard disk and/or a memory) of the data processing apparatus. Thus, such a storage medium also constitutes the application. The storage medium may use any type of recording means, such as a paper storage medium (e.g., paper tape, etc.), a magnetic storage medium (e.g., floppy disk, hard disk, flash memory, etc.), an optical storage medium (e.g., CD-ROM, etc.), a magneto-optical storage medium (e.g., MO, etc.), etc.
The present application therefore also discloses a non-volatile storage medium in which a program is stored. The program includes instructions which, when executed by a processor, cause an electronic apparatus to perform the generation method of a non-linear model or the signal processing method according to the present application.
In addition, the method steps described herein may be implemented in hardware, such as logic gates, switches, application specific integrated circuits (ASICs), programmable logic controllers, embedded microcontrollers, and the like, in addition to data processing programs. Thus, such hardware that may implement the signal processing methods of embodiments of the present application may also constitute the present application.
While the foregoing is directed to the preferred embodiments of the application, it is not intended to limit the invention, but on the contrary, the intention is to cover any of the modifications, equivalents, and improvements within the scopes of protection of the present application.

Claims (14)

  1. An apparatus for signal processing, the apparatus comprising:
    a memory;
    a transceiver; and
    a processor coupled with the memory and the transceiver and configured to:
    perform time delay processing on an input signal of the signal processing system to generate a fractional time delay signal,
    perform time delay processing on the fractional time delay signal to generate an integer time delay processed signal, and
    process the integer time delay processed signal according to a mathematical model of the signal processing to obtain an output signal of the signal processing.
  2. The apparatus of claim 1,
    wherein the mathematical model of the signal processing is a generalized memory polynomial,
    wherein the fractional time delay signal comprises a first fractional time delay signal and a second fractional time delay signal, and
    wherein the integer time delay processed signal comprises a first integer time delay signal and a second integer time delay signal.
  3. The apparatus of claim 2,
    wherein the mathematical model of the signal processing is the generalized memory polynomial with fractional time delay:
    Figure PCTKR2022000679-appb-img-000279
    ,
    wherein:
    n denotes a sequence number of a sampling point of an input signal,
    x(n) is the input signal,
    i, j are integer time delays,
    Figure PCTKR2022000679-appb-img-000280
    is a non-linear function base,
    Figure PCTKR2022000679-appb-img-000281
    denotes a fractional time delay corresponding to tap n-i,
    Figure PCTKR2022000679-appb-img-000282
    denotes a fractional time delay corresponding to tap n-j,
    p denotes a number of non-linear bases,
    Figure PCTKR2022000679-appb-img-000283
    denotes a coefficient of the input signal, and
    y(n) denotes the output signal;
    wherein the first fractional time delay signal is
    Figure PCTKR2022000679-appb-img-000284
    corresponding to
    Figure PCTKR2022000679-appb-img-000285
    and the second fractional time delay signal is
    Figure PCTKR2022000679-appb-img-000286
    corresponding to
    Figure PCTKR2022000679-appb-img-000287
    ;
    wherein the first integer time delay signal is
    Figure PCTKR2022000679-appb-img-000288
    , and the second integer time delay is
    Figure PCTKR2022000679-appb-img-000289
    ; and
    wherein the processor further configured to:
    generate, by using a non-linear function lookup table,
    Figure PCTKR2022000679-appb-img-000290
    according to
    Figure PCTKR2022000679-appb-img-000291
    and
    Figure PCTKR2022000679-appb-img-000292
    ;
    generate, by using a multiplier, a product of
    Figure PCTKR2022000679-appb-img-000293
    and
    Figure PCTKR2022000679-appb-img-000294
    ; and
    generate, by using an accumulator, the output signal y(n) of the signal processing according to a product of
    Figure PCTKR2022000679-appb-img-000295
    and
    Figure PCTKR2022000679-appb-img-000296
    .
  4. The apparatus of claim 3,
    wherein the processor further configured to determine
    Figure PCTKR2022000679-appb-img-000297
    ,
    Figure PCTKR2022000679-appb-img-000298
    , and
    Figure PCTKR2022000679-appb-img-000299
    in the generalized memory polynomial with fractional time delay.
  5. The apparatus of claim 3,
    wherein the processor further configured to distribute the first fractional time delay signal
    Figure PCTKR2022000679-appb-img-000300
    to generate the first integer time delay signal and the second fractional time delay signal
    Figure PCTKR2022000679-appb-img-000301
    to generate the second integer time delay signal.
  6. The apparatus of claim 4,
    wherein ranges of values of the
    Figure PCTKR2022000679-appb-img-000302
    and the
    Figure PCTKR2022000679-appb-img-000303
    are predetermined discrete sets, and the processor determines
    Figure PCTKR2022000679-appb-img-000304
    ,
    Figure PCTKR2022000679-appb-img-000305
    , and
    Figure PCTKR2022000679-appb-img-000306
    in the generalized memory polynomial with fractional time delay in such a manner that:
    matrix A is initialized as an empty matrix, set
    Figure PCTKR2022000679-appb-img-000307
    is initialized as an empty set, and parameter
    Figure PCTKR2022000679-appb-img-000308
    is initialized as y, wherein y denotes a target signal;
    regarding each group of values for （i，j）,
    Figure PCTKR2022000679-appb-img-000309
    is determined such that
    Figure PCTKR2022000679-appb-img-000310
    is largest, wherein
    Figure PCTKR2022000679-appb-img-000311
    is a non-linear base of the generalized memory polynomial with fractional time delay, wherein
    Figure PCTKR2022000679-appb-img-000312
    ,
    wherein denotes a conjugate matrix of matrix
    Figure PCTKR2022000679-appb-img-000313
    , and
    Figure PCTKR2022000679-appb-img-000314
    denotes a group of values for
    Figure PCTKR2022000679-appb-img-000315
    ;
    matrix A is updated according to
    Figure PCTKR2022000679-appb-img-000316
    , and
    Figure PCTKR2022000679-appb-img-000317
    denotes an augmented matrix;
    Figure PCTKR2022000679-appb-img-000318
    is updated according to
    Figure PCTKR2022000679-appb-img-000319
    , wherein pinv(A) denotes a pseudo inverse matrix of the matrix A;
    Figure PCTKR2022000679-appb-img-000320
    is added to set
    Figure PCTKR2022000679-appb-img-000321
    ; and
    a product of pinv(A) and y is used as
    Figure PCTKR2022000679-appb-img-000322
    .
  7. The apparatus of claim 4,
    wherein ranges of values of the
    Figure PCTKR2022000679-appb-img-000323
    and the
    Figure PCTKR2022000679-appb-img-000324
    are predetermined continuous intervals, and the processor determines
    Figure PCTKR2022000679-appb-img-000325
    ,
    Figure PCTKR2022000679-appb-img-000326
    , and
    Figure PCTKR2022000679-appb-img-000327
    in the generalized memory polynomial with fractional time delay in such a manner that:
    Figure PCTKR2022000679-appb-img-000328
    is initialized as 0 and
    Figure PCTKR2022000679-appb-img-000329
    is initialized as 0; and
    regarding each group of values for （i，j）, following operations are performed until
    Figure PCTKR2022000679-appb-img-000330
    is less than a predetermined threshold, the following operations including that
    a value of
    Figure PCTKR2022000679-appb-img-000331
    is determined according to
    Figure PCTKR2022000679-appb-img-000332
    , wherein
    Figure PCTKR2022000679-appb-img-000333
    denotes a pseudo inverse matrix of
    Figure PCTKR2022000679-appb-img-000334
    ,
    Figure PCTKR2022000679-appb-img-000335
    wherein
    Figure PCTKR2022000679-appb-img-000336
    denotes a coefficient of a fractional time delay filter;
    perturbation quantity
    Figure PCTKR2022000679-appb-img-000337
    is determined according to
    Figure PCTKR2022000679-appb-img-000338
    , wherein the perturbation quantity
    Figure PCTKR2022000679-appb-img-000339
    is a perturbation to
    Figure PCTKR2022000679-appb-img-000340
    when a value of
    Figure PCTKR2022000679-appb-img-000341
    is taken as
    Figure PCTKR2022000679-appb-img-000342
    , wherein
    Figure PCTKR2022000679-appb-img-000343
    Figure PCTKR2022000679-appb-img-000344
    Figure PCTKR2022000679-appb-img-000345
    wherein
    Figure PCTKR2022000679-appb-img-000346
    denotes a derivative of
    Figure PCTKR2022000679-appb-img-000347
    at
    Figure PCTKR2022000679-appb-img-000348
    with respect to
    Figure PCTKR2022000679-appb-img-000349
    ,
    Figure PCTKR2022000679-appb-img-000350
    is determined according to the following formula:
    Figure PCTKR2022000679-appb-img-000351
    ; and
    Figure PCTKR2022000679-appb-img-000352
    and
    Figure PCTKR2022000679-appb-img-000353
    are updated by means of
    Figure PCTKR2022000679-appb-img-000354
    Figure PCTKR2022000679-appb-img-000355
  8. A method for signal processing performed by an apparatus, the method comprising:
    performing time delay processing on an input signal of the signal processing system to generate a fractional time delay signal;
    performing time delay processing on the fractional time delay signal to generate an integer time delay processed signal; and
    processing the integer time delay processed signal according to a mathematical model of the signal processing to obtain an output signal of the signal processing.
  9. The method of claim 8,
    wherein the mathematical model of the signal processing is a generalized memory polynomial,
    wherein the fractional time delay signal comprises a first fractional time delay signal and a second fractional time delay signal, and
    wherein the integer time delay processed signal comprises a first integer time delay signal and a second integer time delay signal.
  10. The method of claim 9
    wherein the mathematical model of the signal processing is the generalized memory polynomial with fractional time delay:
    Figure PCTKR2022000679-appb-img-000356
    ,
    wherein:
    n denotes a sequence number of a sampling point of an input signal,
    x(n) is the input signal,
    i, j are integer time delays,
    Figure PCTKR2022000679-appb-img-000357
    is a non-linear function base,
    Figure PCTKR2022000679-appb-img-000358
    denotes a fractional time delay corresponding to tap n-i,
    Figure PCTKR2022000679-appb-img-000359
    denotes a fractional time delay corresponding to tap n-j,
    p denotes a number of non-linear bases,
    Figure PCTKR2022000679-appb-img-000360
    denotes a coefficient of the input signal, and
    y(n) denotes the output signal;
    wherein the first fractional time delay signal is
    Figure PCTKR2022000679-appb-img-000361
    corresponding to
    Figure PCTKR2022000679-appb-img-000362
    and the second fractional time delay signal is
    Figure PCTKR2022000679-appb-img-000363
    corresponding to
    Figure PCTKR2022000679-appb-img-000364
    ;
    wherein the first integer time delay signal is
    Figure PCTKR2022000679-appb-img-000365
    , and the second integer time delay is
    Figure PCTKR2022000679-appb-img-000366
    ; and
    wherein the method further comprising:
    generating, by using a non-linear function lookup table,
    Figure PCTKR2022000679-appb-img-000367
    according to
    Figure PCTKR2022000679-appb-img-000368
    and
    Figure PCTKR2022000679-appb-img-000369
    ;
    generating, by using a multiplier, a product of
    Figure PCTKR2022000679-appb-img-000370
    and
    Figure PCTKR2022000679-appb-img-000371
    ; and
    generating, by using an accumulator, the output signal y(n) of the signal processing according to a product of
    Figure PCTKR2022000679-appb-img-000372
    and
    Figure PCTKR2022000679-appb-img-000373
    .
  11. The method of claim 10, the method further comprising:
    determining
    Figure PCTKR2022000679-appb-img-000374
    ,
    Figure PCTKR2022000679-appb-img-000375
    , and
    Figure PCTKR2022000679-appb-img-000376
    in the generalized memory polynomial with fractional time delay.
  12. The method of claim 10, the method further comprising:
    distributing the first fractional time delay signal
    Figure PCTKR2022000679-appb-img-000377
    to generate the first integer time delay signal and the second fractional time delay signal
    Figure PCTKR2022000679-appb-img-000378
    to generate the second integer time delay signal.
  13. The method of claim 11
    wherein ranges of the
    Figure PCTKR2022000679-appb-img-000379
    and the
    Figure PCTKR2022000679-appb-img-000380
    are predetermined discrete sets, and the
    Figure PCTKR2022000679-appb-img-000381
    ,
    Figure PCTKR2022000679-appb-img-000382
    , and
    Figure PCTKR2022000679-appb-img-000383
    are determined in the generalized memory polynomial with fractional time delay in such a manner that:
    matrix A is initialized as an empty matrix, set
    Figure PCTKR2022000679-appb-img-000384
    is initialized as an empty set, and parameter
    Figure PCTKR2022000679-appb-img-000385
    is initialized as y, wherein y denotes a target signal;
    regarding each group of values for （i，j）,
    Figure PCTKR2022000679-appb-img-000386
    is determined such that
    Figure PCTKR2022000679-appb-img-000387
    is largest, wherein
    Figure PCTKR2022000679-appb-img-000388
    is a non-linear base of the generalized memory polynomial with fractional time delay, wherein
    Figure PCTKR2022000679-appb-img-000389
    ,
    wherein denotes a conjugate matrix of matrix
    Figure PCTKR2022000679-appb-img-000390
    , and
    Figure PCTKR2022000679-appb-img-000391
    denotes a group of values for
    Figure PCTKR2022000679-appb-img-000392
    ;
    matrix A is updated according to
    Figure PCTKR2022000679-appb-img-000393
    , and
    Figure PCTKR2022000679-appb-img-000394
    denotes an augmented matrix;
    Figure PCTKR2022000679-appb-img-000395
    is updated according to
    Figure PCTKR2022000679-appb-img-000396
    , wherein pinv(A) denotes a pseudo inverse matrix of the matrix A;
    Figure PCTKR2022000679-appb-img-000397
    is added to set
    Figure PCTKR2022000679-appb-img-000398
    ; and
    a product of pinv(A) and y is used as
    Figure PCTKR2022000679-appb-img-000399
    .
  14. The the method of claim 11,
    wherein ranges of values of the
    Figure PCTKR2022000679-appb-img-000400
    and the
    Figure PCTKR2022000679-appb-img-000401
    are predetermined continuous intervals, and the
    Figure PCTKR2022000679-appb-img-000402
    ,
    Figure PCTKR2022000679-appb-img-000403
    , and
    Figure PCTKR2022000679-appb-img-000404
    are determined in the generalized memory polynomial with fractional time delay in such a manner that:
    Figure PCTKR2022000679-appb-img-000405
    is initialized as 0 and
    Figure PCTKR2022000679-appb-img-000406
    is initialized as 0; and
    regarding each group of values for （i，j）, following operations are performed until
    Figure PCTKR2022000679-appb-img-000407
    is less than a predetermined threshold, the following operations including that
    a value of
    Figure PCTKR2022000679-appb-img-000408
    is determined according to
    Figure PCTKR2022000679-appb-img-000409
    , wherein
    Figure PCTKR2022000679-appb-img-000410
    denotes a pseudo inverse matrix of
    Figure PCTKR2022000679-appb-img-000411
    ,
    Figure PCTKR2022000679-appb-img-000412
    wherein
    Figure PCTKR2022000679-appb-img-000413
    denotes a coefficient of a fractional time delay filter;
    perturbation quantity
    Figure PCTKR2022000679-appb-img-000414
    is determined according to
    Figure PCTKR2022000679-appb-img-000415
    , wherein the perturbation quantity
    Figure PCTKR2022000679-appb-img-000416
    is a perturbation to
    Figure PCTKR2022000679-appb-img-000417
    when a value of
    Figure PCTKR2022000679-appb-img-000418
    is taken as
    Figure PCTKR2022000679-appb-img-000419
    , wherein
    Figure PCTKR2022000679-appb-img-000420
    Figure PCTKR2022000679-appb-img-000421
    Figure PCTKR2022000679-appb-img-000422
    wherein
    Figure PCTKR2022000679-appb-img-000423
    denotes a derivative of
    Figure PCTKR2022000679-appb-img-000424
    at
    Figure PCTKR2022000679-appb-img-000425
    with respect to
    Figure PCTKR2022000679-appb-img-000426
    ,
    Figure PCTKR2022000679-appb-img-000427
    is determined according to the following formula:
    Figure PCTKR2022000679-appb-img-000428
    ; and
    Figure PCTKR2022000679-appb-img-000429
    and
    Figure PCTKR2022000679-appb-img-000430
    are updated by means of
    Figure PCTKR2022000679-appb-img-000431
    Figure PCTKR2022000679-appb-img-000432
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