WO2023189153A1 - Method for manufacturing optical semiconductor package - Google Patents

Method for manufacturing optical semiconductor package Download PDF

Info

Publication number
WO2023189153A1
WO2023189153A1 PCT/JP2023/007678 JP2023007678W WO2023189153A1 WO 2023189153 A1 WO2023189153 A1 WO 2023189153A1 JP 2023007678 W JP2023007678 W JP 2023007678W WO 2023189153 A1 WO2023189153 A1 WO 2023189153A1
Authority
WO
WIPO (PCT)
Prior art keywords
light receiving
metal
receiving element
wiring
substrate
Prior art date
Application number
PCT/JP2023/007678
Other languages
French (fr)
Japanese (ja)
Inventor
竜大 小松
勝 森下
信吾 島井
陽祐 諏訪
Nao INOUE (井上 直)
Original Assignee
浜松ホトニクス株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 浜松ホトニクス株式会社 filed Critical 浜松ホトニクス株式会社
Publication of WO2023189153A1 publication Critical patent/WO2023189153A1/en

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/12Mountings, e.g. non-detachable insulating substrates
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144Devices controlled by radiation
    • H01L27/146Imager structures
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04NPICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70SSIS architectures; Circuits associated therewith

Definitions

  • the present disclosure relates to a method for manufacturing an optical semiconductor package.
  • Patent Document 1 discloses a method for manufacturing a semiconductor package including a light receiving element.
  • a connection wiring including a columnar electrode is formed on a glass substrate, and a light receiving element (a silicon substrate provided with a photoelectric conversion device region (light receiving part)) is formed on the connection wiring.
  • a first sealing film (underfill) made of resin is filled between the light receiving element and the glass substrate, and then the entire upper surface of the glass substrate is further covered with a second sealing film made of resin.
  • the above manufacturing method since the light-receiving section is covered with the first sealing film, there is a risk that the light-receiving sensitivity may decrease. In addition, since the interface between the first sealing film and the second sealing film is in contact with the connection wiring, the thermal expansion coefficient difference between the first sealing film and the second sealing film, etc. Stress is concentrated on the connection wiring, and there is a risk that the connection wiring may be damaged. As described above, the above manufacturing method has room for improvement in terms of reliability of the semiconductor package.
  • An object of the present disclosure is to provide a method for manufacturing an optical semiconductor package that can improve reliability.
  • a method for manufacturing an optical semiconductor package includes a light receiving element having a first surface provided with a light receiving portion and an electrode terminal electrically connected to the light receiving portion, and a first end of a columnar metal member.
  • the second surface of the light receiving element and the first surface of the metal member are formed by polishing or grinding the resin part from the side opposite to the second surface of the light receiving element, which is opposite to the first surface of the light receiving element.
  • the light receiving element in the first step, is temporarily bonded to the substrate so that no gap is formed between the substrate and the light receiving element.
  • the second step it is possible to prevent the resin from flowing between the light receiving element and the substrate, that is, to prevent the resin portion from being formed at a position facing the light receiving portion.
  • the resin portion in the first step, it is possible to avoid a decrease in light-receiving sensitivity due to the light-receiving part being covered with the resin part.
  • by temporarily bonding the light receiving element and the metal member to the substrate it is possible to stably and accurately perform the second step in a state in which each member is stably fixed.
  • an optical semiconductor package can be manufactured with high reliability.
  • the first step includes positioning and supporting the metal member with the first end exposed by the support member, and positioning the substrate with respect to the first end of the metal member supported by the support member.
  • the step of temporarily joining the first end portion to the substrate by bringing the temporary joining surfaces into contact may be included.
  • the metal member can be temporarily bonded to the substrate by a relatively simple operation of bringing the temporary bonding surface of the substrate into contact with the metal member positioned and supported by the support member.
  • the support member may include a plate-like member in which a through hole having a width larger than the width of the metal member is formed, and a support substrate on which the second end portion is placed and supported, and the metal member may be inserted into and positioned through the through hole of the plate-shaped member and supported by the support substrate, and in a state where the metal member is supported by the support member, the first end portion is supported with respect to the plate-shaped member. It may protrude on the side opposite to the substrate side.
  • the metal member is supported by the support member in a state where the first end of the metal member protrudes beyond the plate-like member, when the temporary bonding surface of the substrate is brought into contact with the first end, , it is possible to prevent the temporarily bonded surface of the substrate from coming into contact with the plate member. That is, it is possible to accurately prevent the temporarily bonded surface of the substrate from sticking to the plate-like member.
  • the metal member may include a shaft portion including the second end portion and a flange portion including the first end portion and formed wider than the shaft portion, and the supporting member may have a width wider than the shaft portion.
  • the metal member may be a plate-like member in which a through hole having a width smaller than the width of the flange portion is formed. may be supported by the support member by coming into contact with the peripheral edge of the through hole of the support member. According to the above configuration, it is possible to support the flange portion by hooking it onto the peripheral edge of the through hole of the plate-shaped member. That is, since a support substrate for supporting the second end is not required, the support member can be simplified. Further, by providing the flange portion, the posture (verticality) of the metal member erected on the substrate can be more stabilized.
  • the first wiring layer may be formed such that the width of the portion of the first metal wiring connected to the second end is larger than the width of the second end of the metal member. According to the above configuration, it is possible to absorb the positional shift of the metal member that may occur in the second step (resin portion forming step). That is, by increasing the wiring width of the first metal wiring, even if the position of the metal member is slightly shifted in the second step, the first metal wiring and the metal member (second end) can be brought into contact more reliably. be able to.
  • the first wiring layer may be formed such that the width of the portion of the first metal wiring connected to the second end is smaller than the width of the second end of the metal member.
  • the first metal wiring can be formed without being influenced by the size (width) of the metal member. For example, if the width of the first metal wiring is made larger than the width of the metal member when the width of the metal member (second end portion) is relatively large, the first metal wiring may be connected to other wiring provided in the first wiring layer. A problem may arise in that it is easy to interfere with the According to the above configuration, occurrence of such a problem can be avoided.
  • the second wiring layer may be formed such that the wiring width of the portion of the second metal wiring connected to the first end is larger than the width of the first end of the metal member.
  • the second wiring layer may be formed such that the wiring width of the portion of the second metal wiring connected to the first end is smaller than the width of the first end of the metal member.
  • the second metal wiring can be formed without being influenced by the size (width) of the metal member. For example, when the width of the metal member (first end portion) is relatively large, if the width of the second metal wiring is made larger than the width of the metal member, the second metal wiring may be connected to other wiring provided in the second wiring layer. A problem may arise in that it is easy to interfere with the According to the above configuration, occurrence of such a problem can be avoided.
  • the fifth step may be performed at least after the third step. Further, the fourth step may be performed after the third step, and the fifth step may be performed after the fourth step. According to the above configuration, by keeping the substrate attached in the third step (or the third step and the fourth step), the third step (or the third step and the fourth step) is performed with the support stability of each member increased. 3 and 4) can be performed with high reliability.
  • the light receiving element may have a light receiving surface on the first surface. According to the above configuration, an optical semiconductor package in which the surface of the front-illuminated light receiving element is the first surface can be manufactured with high reliability.
  • a method for manufacturing an optical semiconductor package includes a first step of forming, on a substrate, a first wiring layer that includes a first metal wiring and is provided with an opening that exposes the substrate; 1.
  • the resin part covers the light receiving part by filling the internal space between the light receiving element and the substrate in the fifth step, but the resin part is not detected by the light receiving part. Since the resin part has transparency to light, a decrease in light-receiving sensitivity caused by the resin part covering the light-receiving part is suppressed. Furthermore, in the fifth step, a resin portion is formed by a single resin material, filling the internal space between the light receiving element and the substrate and covering each member (the light receiving element, the metal member, and the first wiring layer). can be formed. This reduces reliability due to the coexistence of two types of resin parts (for example, two resin parts formed from different materials or at different times) (for example, due to differences in thermal expansion coefficients between the two resin parts). (damage to metal wiring due to stress caused by stress, etc.) can be avoided. As described above, according to the above manufacturing method, an optical semiconductor package can be manufactured with high reliability.
  • the eighth step may be performed at least after the sixth step. Further, the seventh step may be performed after the sixth step, and the eighth step may be performed after the seventh step. According to the above configuration, by keeping the substrate attached in the sixth step (or the sixth step and the seventh step), the sixth step (or the sixth step and the seventh step) is performed with the support stability of each member increased. 6 and 7) can be performed with high reliability.
  • the light receiving element may have a light receiving surface on the first surface. According to the above configuration, an optical semiconductor package in which the surface of the front-illuminated light receiving element is the first surface can be manufactured with high reliability.
  • FIG. 1 is a cross-sectional view of the optical semiconductor package of the first embodiment.
  • FIG. 2 is a diagram showing an example of the manufacturing process of the optical semiconductor package of FIG. 1.
  • FIG. 3 is a diagram showing an example of the manufacturing process of the optical semiconductor package of FIG. 1.
  • FIG. 4 is a diagram showing an example of the manufacturing process of the optical semiconductor package of FIG. 1.
  • FIG. 5 is a diagram showing an example of the manufacturing process of the optical semiconductor package of FIG. 1.
  • FIG. 6 is a diagram showing an example of the manufacturing process of the optical semiconductor package of FIG. 1.
  • FIG. 7 is a diagram showing an example of the manufacturing process of the optical semiconductor package of FIG. 1.
  • FIG. 8 is a cross-sectional view of the optical semiconductor package of the second embodiment.
  • FIG. 9 is a diagram showing an example of the manufacturing process of the optical semiconductor package of FIG. 8.
  • FIG. 10 is a diagram showing an example of the manufacturing process of the optical semiconductor package of FIG. 8.
  • FIG. 11 is a diagram showing an example of the manufacturing process of the optical semiconductor package of FIG. 8.
  • FIG. 12 is a cross-sectional view of the optical semiconductor package of the third embodiment.
  • FIG. 13 is a diagram showing an example of the manufacturing process of the optical semiconductor package of FIG. 12.
  • FIG. 14 is a diagram showing an example of the manufacturing process of the optical semiconductor package of FIG. 12.
  • FIG. 15 is a diagram showing an example of the manufacturing process of the optical semiconductor package of FIG. 12.
  • FIG. 16 is a diagram showing a modification of the method for manufacturing the optical semiconductor package shown in FIG.
  • the optical semiconductor package 1A of the first embodiment includes a light receiving element 2, a mold resin 3 (resin part), a wiring layer 4 (first wiring layer), and a wiring layer 5 (second wiring layer). wiring layer) and a metal pillar 6 (metal member).
  • the optical semiconductor package 1A is a type of FOWLP (Fan Out Wafer Level Package)/FOPLP (Fan Out Panel Level Package).
  • the light receiving element 2 is a semiconductor chip having a light receiving section 21, and is formed into a rectangular plate shape.
  • the light receiving element 2 has a first surface 2a and a second surface 2b.
  • the direction in which the first surface 2a and the second surface 2b face each other is expressed as the Z-axis direction
  • the direction along one side of the light-receiving element 2 when viewed from the Z-axis direction is expressed as the X-axis direction.
  • the direction along the other side (the side perpendicular to the above-mentioned one side) of the light receiving element 2 when viewed from the Z-axis direction is expressed as the Y-axis direction.
  • a light receiving section 21 and a plurality of (two in this embodiment) electrode terminals 22 electrically connected to the light receiving section 21 are provided on the first surface 2a.
  • one light receiving section 21 is provided at approximately the center of the first surface 2a when viewed from the Z-axis direction, but a plurality of light receiving sections 21 are provided on the first surface 2a.
  • the plurality of light receiving sections 21 may be arranged one-dimensionally or two-dimensionally, for example, when viewed from the Z-axis direction.
  • the light receiving section 21 is arranged at a position along the first surface. That is, the light receiving element 2 has a light receiving surface on the first surface 2a.
  • the portion of the first surface 2a that faces the light receiving section 21 functions as a light receiving surface.
  • the light receiving section 21 is embedded in the light receiving element 2 so that the light incident surface (the surface on the first surface 2a side) of the light receiving section 21 is substantially flush with the first surface 2a.
  • the light receiving section 21 include a Si photodiode (SiPD), a Si avalanche photodiode (SiAPD), and a Si-MPPC (Multi-Pixel Photon Counter).
  • the two electrode terminals 22 are provided so as to protrude above the first surface 2a.
  • An insulating layer 23 is provided on the first surface 2a.
  • the insulating layer 23 is provided so as to surround a plurality of (two in this embodiment) electrode terminals 22 provided on the first surface 2a. Openings 23a are formed in the insulating layer 23 to expose each electrode terminal 22.
  • the insulating layer 23 may be formed of an inorganic film such as silicon dioxide (SiO 2 ) or silicon nitride (Si 3 N 4 ), or an organic film such as polyimide.
  • the mold resin 3 seals the side surface of the light receiving element 2 so as to surround the light receiving element 2 when viewed from the Z-axis direction.
  • the mold resin 3 also covers the metal pillar 6.
  • the mold resin 3 may be made of, for example, epoxy resin.
  • the mold resin 3 has an end surface 3a formed flush with the surface of the insulating layer 23, and an end surface 3b formed flush with the second surface 2b of the light receiving element 2.
  • the wiring layer 4 is provided on the second surface 2b side of the light receiving element 2, on the second surface 2b of the light receiving element 2, and on the end surface 3b of the molded resin 3 continuous with the second surface 2b.
  • the wiring layer 4 is a rewiring layer including an insulating layer 41 and a metal wiring 42 (first metal wiring).
  • the insulating layer 41 may be formed of, for example, an inorganic film such as silicon dioxide (SiO 2 ) or silicon nitride (Si 3 N 4 ), or an organic film such as polyimide.
  • the metal wiring 42 is, for example, a copper (Cu) wiring.
  • An opening 41a is provided in a portion of the insulating layer 41 that overlaps with the metal pillar 6 in the Z-axis direction.
  • a metal wiring 42 electrically connected to the end 6b (second end) of the metal pillar 6 on the wiring layer 4 side is provided in the opening 41a.
  • the width of the opening 41a is made larger than the width of the end portion 6b of the metal pillar 6.
  • the wiring width w11 of the portion of the metal wiring 42 connected to the end 6b is larger than the width w12 of the end 6b of the metal pillar 6.
  • a plated portion 43 is provided at the outer end of the metal wiring 42 (the end located on the opposite side from the metal pillar 6 in the Z-axis direction).
  • the plated portion 43 is a portion that is bonded to a printed circuit board or the like using, for example, solder.
  • the plated portion 43 is, for example, two-layer plating of nickel and gold (Ni/Au plating).
  • the wiring layer 5 is provided on the side opposite to the side where the wiring layer 4 is located with respect to the light receiving element 2 and the mold resin 3. That is, the wiring layer 5 is provided on the insulating layer 23 and on the end surface 3a of the molded resin 3 on the first surface 2a side of the light receiving element 2.
  • the wiring layer 5 is a rewiring layer including an insulating layer 51 and a metal wiring 52 (second metal wiring).
  • the insulating layer 51 may be formed of, for example, an inorganic film such as silicon dioxide (SiO 2 ) or silicon nitride (Si 3 N 4 ), or an organic film such as polyimide.
  • the metal wiring 52 is, for example, a copper (Cu) wiring.
  • An opening 51a is provided in a portion of the insulating layer 51 that overlaps with the metal pillar 6 in the Z-axis direction.
  • a metal wiring 52 electrically connected to the end 6a (first end) of the metal pillar 6 on the wiring layer 5 side is provided in the opening 51a.
  • the width of the opening 51a is made larger than the width of the end portion 6a of the metal pillar 6.
  • the wiring width w21 of the portion of the metal wiring 52 connected to the end 6a is larger than the width w22 of the end 6a of the metal pillar 6.
  • An opening 51b is provided in a portion of the insulating layer 51 that overlaps with the light receiving section 21 in the Z-axis direction. That is, the insulating layer 51 is formed so as not to cover the light receiving section 21 in the Z-axis direction.
  • the metal wiring 52 electrically connects the end 6a of the metal pillar 6 and the electrode terminal 22 of the light receiving element 2. That is, the light receiving element 2 (electrode terminal 22) is electrically connected to the plating portion 43 via the metal wiring 52, the metal pillar 6, and the metal wiring 42.
  • the metal pillar 6 is a metal member formed into a columnar shape.
  • the metal pillar 6 is made of copper, for example.
  • the metal pillar 6 is, for example, a so-called copper pillar or a copper post.
  • two electrode terminals 22, two metal wirings 52, two metal pillars 6, and two metal wirings 42 are provided. More specifically, a set of electrode terminals 22, metal wiring 52, metal pillar 6, and metal wiring 42, which are electrically connected to each other, is arranged on each side of the light receiving section 21 when viewed from the Y-axis direction. It is provided. Note that when a plurality of light receiving sections 21 are provided as described above, the number of electrode terminals 22 (that is, the number of the above-mentioned groups) may vary depending on the number of light receiving sections 21.
  • the optical semiconductor package 1A is manufactured by a CoW (Chip on Wafer) method or a CoP (Chip on Panel) method.
  • the light receiving element 2 and the end portion 6a of the metal pillar 6 are connected to a temporary bonding surface 50a (for example, a surface coated with adhesive for temporary bonding) of a substrate 50 that is a temporary bonding member. are temporarily joined (first step). That is, the light receiving element 2 and the metal pillar 6 are temporarily bonded to the substrate 50 in such a manner that they can be removed later.
  • the light receiving element 2 is temporarily bonded to the substrate 50 such that the first surface 2a faces the substrate 50.
  • the insulating layer 23 provided on the first surface 2a of the light receiving element 2 is temporarily bonded to the substrate 50.
  • the substrate 50 is, for example, a silicon wafer, a glass wafer, a SUS carrier, or the like.
  • a plurality of unit regions corresponding to one optical semiconductor package 1A are formed in a grid (two-dimensional shape). 2 to 7 represent the state of one unit area in each manufacturing process.
  • a support member 100 is used that positions each metal pillar 6 with the ends 6a of a plurality (number of unit areas x number of metal pillars included in each unit area) of the metal pillars 6 exposed.
  • the step of temporarily joining the metal pillar 6 to the substrate 50 in the first step is a step of positioning and supporting the metal pillar 6 with the end portion 6a of the metal pillar 6 exposed using the support member 100.
  • the metal pillar 6 can be temporarily bonded to the substrate 50 by a relatively simple operation of bringing the temporary bonding surface 50a of the substrate 50 into contact with the metal pillar 6 positioned and supported by the support member 100. can.
  • the metal pillar 6 is positioned and supported by the support member 100 with the end 6a of the metal pillar 6 exposed.
  • the support member 100 includes a plate-like member 101 in which a through hole 101a having a width larger than the width of the metal pillar 6 is formed, and a support substrate 102 on which the end portion 6b of the metal pillar 6 is placed and supported. It has . Note that the size of the through hole 101a is adjusted to a size that allows the metal pillar 6 to be inserted therein and allows the lateral positional deviation of the metal pillar 6 to be kept within an allowable error range.
  • Each metal pillar 6 is inserted into the through hole 101a of the plate member 101 and positioned, and is supported by the support substrate 102.
  • the end portion 6a protrudes from the plate member 101 on the side opposite to the support substrate 102 side.
  • the plate-like member 101 and the support substrate 102 may be formed separately as shown in FIG. 3, or may be formed integrally. Further, a space (gap) may be provided between the plate member 101 and the support substrate 102 as shown in FIG. 3, or such a space may not be provided.
  • the temporary bonding surface 50a of the substrate 50 is brought into contact with the end 6a of the metal pillar 6 supported by the support member 100.
  • the end portion 6a of the metal pillar 6 is temporarily bonded to the temporary bonding surface 50a of the substrate 50.
  • the temporary bonding surface 50a of the substrate 50 is attached to the end 6a.
  • the temporary bonding surface 50a of the substrate 50 can be prevented from coming into contact with the plate member 101. That is, it is possible to accurately prevent the temporary bonding surface 50a of the substrate 50 from sticking to the plate member 101.
  • a metal pillar 6A having a flange portion 62 may be used instead of the metal pillar 6.
  • the metal pillar 6A has a shaft portion 61 including an end portion 6b, and a flange portion 62 including the end portion 6a and formed wider than the shaft portion 61.
  • the flange portion 62 is a portion extending outward in a direction perpendicular to the axial direction of the shaft portion 61 at the end portion 6a.
  • the shape of the flange portion 62 when viewed from the axial direction is, for example, circular.
  • the through hole 101a of the plate member 101 is set to have a width larger than the width of the shaft portion 61 and smaller than the width of the flange portion 62.
  • the shaft portion 61 is inserted into the through hole 101a, and the inner surface 62a of the flange portion 62 on the end 6b side abuts the peripheral edge of the through hole 101a of the plate member 101, so that the metal pillar 6A is inserted into the plate member 101. Supported.
  • the end 6a of the metal pillar 6A can be temporarily joined to the substrate 50 by bringing the temporary joining surface 50a of the substrate 50 into contact with the end 6a of the metal pillar 6A.
  • the flange portion 62 can be supported by being hooked onto the peripheral edge of the through hole 101a of the plate member 101, so the support substrate 102 for supporting the end portion 6b is not required.
  • the support member 100 can be simplified. Further, by providing the flange portion 62, the posture (verticality) of the metal pillar 6A erected on the substrate 50 can be more stabilized.
  • the method for forming the metal pillars 6 on the substrate 50 is not limited to the above method.
  • the metal pillar 6 may be formed on the substrate 50 by transferring the metal pillar 6 to a designated position on the substrate 50 using a transfer device configured to be able to transfer the metal pillar 6.
  • the metal pillars 6 can be placed at any position on the substrate 50 with high precision.
  • semiconductor pre-processes seed layer formation, photolithography, electrolytic Cu plating, resist removal, seed layer etching, etc.
  • a metal pillar 6 may be formed on the surface.
  • the above method also allows the pattern (position and shape) of the metal pillars 6 to be controlled with high precision.
  • a metal pad is formed on the substrate 50, wire bonding is performed so that a wire extending vertically is formed on the metal pad, and the wire bonded on the metal pad is cut to an appropriate length.
  • a metal pillar 6 (that is, a structure combining a metal pad and a wire) may be formed by this method.
  • a wire (metal pillar 6) having an arbitrary diameter and length can be formed by adjusting the bonding conditions (parameters).
  • a mold resin 3 is formed on the substrate 50 to cover the light receiving elements 2 and metal pillars 6 arranged in each unit area (second step). Focusing on one unit area, the mold resin 3 covers the second surface 2b and side surfaces of the light receiving element 2, and also covers the entire portion of each metal pillar 6 except for the end portion 6a (end portion 6b and side surface). It is formed like this.
  • the mold resin 3 is polished or ground from the side facing the second surface 2b of the light-receiving element 2 (i.e., the end surface 3b side), so that the light-receiving element 2 is polished.
  • the second surface 2b and the end portion 6b of the metal pillar 6 are exposed (third step).
  • “Polishing or grinding” includes cases in which only one of polishing and grinding is performed, as well as cases in which both polishing and grinding are performed.
  • the end surface 3b of the molded resin 3 and the second surface 2b of the light-receiving element 2 may also be polished or ground.
  • the end portion 6b of the metal pillar 6 may also be polished or ground.
  • the process of polishing or grinding the end portion 6b at once may be continued.
  • the light receiving element 2 is made thinner, and the second surface 2b of the light receiving element 2 and the end portion 6b of the metal pillar 6 are exposed to the outside.
  • the second surface 2b of the light receiving element 2, the end portion 6b of the metal pillar 6, and the end surface 3b of the molded resin 3 become substantially flush with each other.
  • the wiring layer 4 is formed on the second surface 2b of the light receiving element 2 and on the end surface 3b of the molded resin 3 that is continuous with the second surface 2b.
  • an insulating layer 41 and metal wiring 42 are formed on the second surface 2b of the light receiving element 2, the end 6b of the metal pillar 6, and the end surface 3b of the molded resin 3.
  • the structure shown in (A) is obtained.
  • the wiring layer 4 is formed so that the wiring width of the portion of the metal wiring 42 connected to the end portion 6b is larger than the width of the end portion 6b. More specifically, the width of the opening 41a of the insulating layer 41 is formed to be larger than the width of the end 6b of the metal pillar 6. As a result, the wiring width w11 (see FIG. 1) of the portion of the metal wiring 42 connected to the end 6b is formed larger than the width w12 (see FIG.
  • the wiring layer 4 may be formed such that the wiring width of the portion of the metal wiring 42 connected to the end 6b is smaller than the width of the end 6b of the metal pillar 6 ( (See second embodiment described later).
  • the metal wiring 42 can be formed without being affected by the size (width) of the metal pillar 6.
  • the width of the metal wiring 42 is made larger than the width of the metal pillar 6 when the width of the metal pillar 6 (end portion 6b) is relatively large, the metal wiring 42 will interfere with other wiring provided in the wiring layer 4. The problem may arise that it becomes easier to do so. According to the above configuration, occurrence of such a problem can be avoided.
  • the substrate 50 is separated from the light receiving element 2, metal pillar 6, and mold resin 3 (fifth step). Further, the processing surface (the surface to be processed) changes from the surface on the second surface 2b side of the light receiving element 2 to the surface on the first surface 2a side of the light receiving element 2 (that is, the surface exposed after the substrate 50 is separated). will be changed to
  • the wiring layer 5 is formed on the side opposite to the side where the wiring layer 4 is located with respect to the light receiving element 2 and the mold resin 3 (sixth step).
  • the insulating layer 51 and the metal wiring 52 are formed on the portion of the insulating layer 23 that does not overlap with the light receiving section 21, the end portion 6a of the metal pillar 6, and the end surface 3a of the molded resin 3. Further, by performing electroless plating on the outer end portion of the metal wiring 42, a plated portion 43 is formed on the surface of the outer end portion.
  • the structure shown in (A) is obtained.
  • the wiring layer 5 is formed so that the wiring width of the portion of the metal wiring 52 connected to the end portion 6a is larger than the width of the end portion 6a. More specifically, the width of the opening 51a of the insulating layer 51 is larger than the width of the end 6a of the metal pillar 6. As a result, the wiring width w21 (see FIG. 1) of the portion of the metal wiring 52 connected to the end 6a is formed larger than the width w22 (see FIG. 1) of the end 6a of the metal pillar 6.
  • the metal wiring 52 and the metal pillar 6 can be easily connected. Contact can be made more reliably.
  • the wiring layer 5 may be formed such that the wiring width of the portion of the metal wiring 52 connected to the end 6a is smaller than the width of the end 6a of the metal pillar 6 ( (See second embodiment described later).
  • the metal wiring 52 can be formed without being affected by the size (width) of the metal pillar 6.
  • the width of the metal wiring 52 is made larger than the width of the metal pillar 6 when the width of the metal pillar 6 (end portion 6a) is relatively large, the metal wiring 52 will interfere with other wiring provided in the wiring layer 5. The problem may arise that it becomes easier to do so. According to the above configuration, occurrence of such a problem can be avoided.
  • the light receiving element 2 is temporarily bonded to the substrate 50 so that no gap is formed between the substrate 50 and the light receiving element 2.
  • the second step it is possible to prevent the mold resin 3 from flowing between the light receiving element 2 and the substrate 50, that is, from forming the mold resin 3 at a position facing the light receiving section 21.
  • the mold resin 3 it is possible to avoid a decrease in light receiving sensitivity due to the light receiving section 21 being covered with the mold resin 3.
  • by temporarily bonding the light receiving element 2 and the metal pillar 6 to the substrate 50 it becomes possible to carry out the second step stably and accurately with each member being stably fixed.
  • the optical semiconductor package 1A can be manufactured with high reliability.
  • the light receiving element 2 has a light receiving surface on the first surface 2a. According to the above configuration, the optical semiconductor package 1A in which the surface of the front-illuminated light receiving element 2 is the first surface 2a can be manufactured with high reliability.
  • the following effects are also achieved.
  • the light receiving element is placed apart from the glass substrate using bump connection as in the method disclosed in Patent Document 1
  • the light receiving element is placed with respect to the glass substrate due to variations in the amount of bumps.
  • optical axis misalignment may occur, resulting in a decrease in uniformity.
  • the method for manufacturing the optical semiconductor package 1A described above since the light receiving element 2 (insulating layer 23) is brought into close contact with the substrate 50, the light receiving element 2 is prevented from being arranged at an angle with respect to the substrate 50. This can avoid the problems mentioned above.
  • voids may occur in the underfill sealed between the glass substrate and the light receiving element, and special processing may be required to eliminate the voids.
  • the method for manufacturing the optical semiconductor package 1A described above since no underfill is formed at a position facing the light receiving element 2 (light receiving section 21), the above problem can also be avoided.
  • Optical components such as glass, a bandpass filter, and a lens may be attached to a position on the insulating layer 23 facing the light receiving section 21 .
  • the step of attaching such an optical component may be performed, for example, after the step of forming the wiring layer 5 (sixth step).
  • the optical components described above may be attached to the light receiving element 2 in advance before the manufacturing process of this embodiment is performed.
  • the step of separating (peeling) the substrate 50 from the light receiving element 2, etc. (fifth step) may be performed at any timing between the completion of the second step and the start of the sixth step. good.
  • substrate 50 may be removed immediately after the second step is completed.
  • the fifth step may be performed at least after the third step.
  • the fourth step may be performed after the third step
  • the fifth step may be performed after the fourth step.
  • the third step (or The advantage is that the third step and the fourth step) can be carried out with high reliability.
  • the light receiving section 21 since the light receiving section 21 is exposed to the outside through the insulating layer 23, by attaching the substrate 50, the light receiving section 21 can be properly protected from external impact etc. in each process. can be protected.
  • a substrate for example, the substrate 50
  • a temporary bonding member may be attached on the wiring layer 4 in order to improve the support stability of each member.
  • the optical semiconductor package 1B of the second embodiment is different from the optical semiconductor package 1A in that a transparent mold resin 3B is provided instead of the mold resin 3. Further, in the optical semiconductor package 1B, the end portion 6a of the metal pillar 6 (metal member) is located at a higher position than the upper surface of the insulating layer 23 (the surface opposite to the first surface 2a side), and the end portion 6a of the metal pillar 6 (metal member) It is also different from the optical semiconductor package 1A in that it further includes a metal pillar 7 that connects the electrode terminal 22 to the end 52b on the side opposite to the side connected to the portion 6a.
  • the parts of the optical semiconductor package 1B that are different from the optical semiconductor package 1A will be described, and the description of the parts of the optical semiconductor package 1B that are similar to the optical semiconductor package 1A will be omitted.
  • the mold resin 3B is made of a material that is transparent to the light (wavelength) to be detected by the light receiving section 21.
  • the mold resin 3B may be made of, for example, transparent epoxy resin.
  • the mold resin 3B is provided not only on the side surface of the light-receiving element 2 but also on the portion facing the first surface 2a of the light-receiving element 2 (that is, the area on the insulating layer 23), and is provided on the metal pillar 6 and the metal pillar 7. covers the entire side of the
  • the mold resin 3B is also provided inside the opening 51b of the wiring layer 5. That is, the end surface 3a of the molded resin 3B opposite to the end surface 3b (the end surface formed flush with the second surface 2b) is formed flush with the outer surface of the wiring layer 5 (insulating layer 51).
  • the wiring layer 5 (first wiring layer) is separated from the insulating layer 23 in the Z-axis direction. For this reason, a metal pillar 7 is provided for electrically connecting the metal wiring 52 (first metal wiring) and the electrode terminal 22.
  • the metal wiring 52 has an end portion 52a (first end portion) located outside in the X-axis direction (a portion that does not overlap with the light-receiving element 2), and an end portion 52a (first end portion) located inside in the X-axis direction (a portion that does not overlap with the light-receiving element 2). and an end portion 52b (a second end portion) disposed at a portion overlapping with the first end portion.
  • the end 52a is connected to the end 6a of the metal pillar 6.
  • the end 52b is connected to the end 7a of the metal pillar 7 (the end on the opposite side to the electrode terminal 22 side).
  • the optical semiconductor package 1B does not necessarily need to include the columnar metal pillar 7.
  • the end portion 52b and the electrode terminal 22 may be connected via a conductive bump. That is, the end portion 52b and the electrode terminal 22 may be electrically connected by some kind of conductive member.
  • the molded resin 3B can be introduced into the internal space S (see (B) in FIG. 9) in the fifth step described later. It is sufficient that a gap of 1 is formed between the insulating layer 23 and the insulating layer 51.
  • FIGS. 9 to 11 Method for manufacturing optical semiconductor package
  • the optical semiconductor package 1B is manufactured by a CoW method or a CoP method.
  • 9 to 11 show the state of one unit area in each manufacturing process. The following description focuses on only one unit area.
  • the wiring layer 5 provided with an opening 51b that exposes the substrate 50 is formed on the substrate 50, which is a temporary bonding member (first step).
  • the wiring layer 5 includes an insulating layer 51 and metal wiring 52.
  • the opening 51b is provided in the insulating layer 51.
  • a semiconductor process seed layer formation, photolithography, electrolytic plating, etc.
  • the width of the opening 51a of the insulating layer 51 is smaller than the width of the end 6a of the metal pillar 6, and as a result, the width of the opening 51a of the insulating layer 51 is smaller than the width of the end 6a of the metal wiring 52.
  • the wiring width is formed smaller than the width of the end portion 6a of the metal pillar 6.
  • the width of the portion of the metal wiring 52 connected to the end 6a may be formed to be larger than the width of the end 6a of the metal pillar 6.
  • a metal pillar 6 is formed which is connected to the end portion 52a of the metal wiring 52 and protrudes from the wiring layer 5 to the side opposite to the substrate 50 side. process).
  • the metal pillar 6 is formed, for example, by plating, solder bump forming, or the like.
  • the metal pillar 6 has an end 6a connected to the end 52a, and an end 6b opposite to the end 6a.
  • the light receiving element 2 is prepared (third step). Subsequently, an end 52b of the metal wiring 52 different from the end 52a and the electrode terminal 22 are electrically connected via the metal pillar 7, and the light receiving part 21 is arranged at a position facing the opening 51b.
  • the light receiving element 2 is arranged so that an internal space S is formed between the substrate 50 and the light receiving element 2 (fourth step).
  • the metal pillar 7 has an end 7a connected to the end 52b, and an end 7b opposite to the end 7a. Note that, as described above, the metal pillar 7 may be any conductive member, and may be a conductive bump formed by bump-bonding the end portion 7b and the electrode terminal 22, for example.
  • the upper surface of the insulating layer 51 (the surface opposite to the substrate 50 side) and the lower surface of the insulating layer 23 (the surface facing the substrate 50) are separated, and the gap between the insulating layer 51 and the insulating layer 23 is There is a gap. That is, the internal space S communicates with the outside via the gap. In other words, the interior space S is not a closed space cut off from the outside.
  • mold resin 3B is formed (fifth step).
  • the mold resin 3B is made of a material that is transparent to the light to be detected by the light receiving section 21, and covers the light receiving element 2, the metal pillars 6, 7, and the wiring layer 5, and also covers the internal space. S (see FIG. 9B).
  • the mold resin 3B is polished or ground from the side facing the second surface 2b of the light-receiving element 2 (that is, the end surface 3b side), so that the light-receiving element 2 is polished.
  • the second surface 2b and the end portion 6b of the metal pillar 6 are exposed (sixth step).
  • the second surface 2b of the light receiving element 2 may be polished or ground together with the end surface 3b of the molded resin 3B.
  • the end portion 6b of the metal pillar 6 may also be polished or ground.
  • the second surface 2b of the light receiving element 2 or the end 6b of the metal pillar 6 in each unit area is exposed by polishing or grinding the end surface 3b of the molded resin 3B
  • the end surface 3b and the second surface 2b of the molded resin 3B are further exposed.
  • the process of polishing or grinding the end portion 6b at once may be continued.
  • the second surface 2b of the light receiving element 2 and the end portion 6b of the metal pillar 6 are exposed to the outside.
  • the second surface 2b of the light receiving element 2, the end portion 6b of the metal pillar 6, and the end surface 3b of the molded resin 3B become substantially flush with each other.
  • a wiring layer 4 is formed on the second surface 2b of the light receiving element 2 and on the end surface 3b of the molded resin 3B that is continuous with the second surface 2b ( 7th step).
  • an insulating layer 41 and metal wiring 42 are formed on the second surface 2b of the light receiving element 2, the end 6b of the metal pillar 6, and the end surface 3b of the molded resin 3B.
  • a plated portion 43 is formed on the surface of the outer end portion.
  • the width of the opening 41a of the insulating layer 41 is smaller than the width of the end 6b of the metal pillar 6, and as a result, the width of the portion of the metal wiring 42 connected to the end 6b is smaller.
  • the wiring width is formed smaller than the width of the end portion 6b of the metal pillar 6.
  • the wiring width of the portion of the metal wiring 42 connected to the end 6b may be formed to be larger than the width of the end 6b of the metal pillar 6.
  • the substrate 50 is separated from the wiring layer 5 and the mold resin 3B (eighth step). Subsequently, dicing is performed along the boundary line L between the unit areas. Thereby, a plurality of individualized optical semiconductor packages 1B are obtained.
  • the mold resin 3B is filled into the internal space S between the light receiving element 2 and the substrate 50, so that the mold resin 3B covers the light receiving part 21. Since 3B has transparency to the light to be detected by the light receiving section 21, a decrease in light receiving sensitivity caused by the mold resin 3B covering the light receiving section 21 is suppressed. Furthermore, in the fifth step, the internal space S between the light receiving element 2 and the substrate 50 is filled with a single resin material, and each member (the light receiving element 2, the metal pillars 6, 7, and the wiring layer 5) is filled with a single resin material. ) can be formed to cover the mold resin 3B.
  • the optical semiconductor package 1B can be manufactured with high reliability.
  • the light receiving element 2 has a light receiving surface on the first surface 2a. According to the above configuration, the optical semiconductor package 1B in which the surface of the front-illuminated light receiving element 2 is the first surface 2a can be manufactured with high reliability.
  • the void-free mold resin 3B can be formed all at once without using any special equipment.
  • the step of separating (peeling) the substrate 50 from the wiring layer 5 and the like may be performed at any timing after the fifth step is completed.
  • substrate 50 may be removed immediately after completing the fifth step.
  • the eighth step may be performed at least after the sixth step.
  • the seventh step may be performed after the sixth step, and the eighth step may be performed after the seventh step.
  • the optical semiconductor package 1C of the third embodiment is different from the optical semiconductor package 1A in that it includes a wiring layer 5C instead of the wiring layer 5.
  • the parts of the optical semiconductor package 1C that are different from the optical semiconductor package 1A will be described, and the description of the parts of the optical semiconductor package 1C that are similar to the optical semiconductor package 1A will be omitted.
  • the wiring layer 5C is different from the wiring layer 5 of the optical semiconductor package 1A in that it has an insulating layer 51C instead of the insulating layer 51.
  • the insulating layer 51C is different from the insulating layer 51 in that it is formed of a transparent resin insulating film and does not have an opening 51b.
  • the insulating layer 51C is made of a material that is transparent to the light that the light receiving section 21 detects.
  • the insulating layer 51C may be formed of, for example, transparent epoxy resin, transparent polyimide resin, or the like.
  • optical semiconductor package 1C (Method for manufacturing optical semiconductor package) An example of the manufacturing process of the optical semiconductor package 1C will be described with reference to FIGS. 13 to 15.
  • the optical semiconductor package 1C is manufactured by a CoW method or a CoP method. 13 to 15 show the state of one unit area in each manufacturing process. The following description focuses on only one unit area.
  • the method for manufacturing the optical semiconductor package 1C is as follows: a first step of preparing a light receiving element 2 having a first surface 2a provided with a light receiving section 21 and an electrode terminal 22 electrically connected to the light receiving section 21; a second step of forming, on the substrate 50, a wiring layer 5C including an insulating layer 51C and a metal wiring 52 that is transparent to light to be detected by the light receiving section 21; a third step of forming a metal member (metal pillar 6) connected to the end portion 52a of the metal wiring 52 and protruding from the wiring layer 5C to the side opposite to the substrate 50 side; a fourth step of arranging the light receiving element 2 on the wiring layer 5C so that the end 52b of the metal wiring 52 and the electrode terminal 22 are electrically connected; a fifth step of forming a resin part (molding resin 3) covering the light receiving element 2, the metal pillar 6, and the wiring layer 5C; a sixth step of exposing the second surface 2b of the light receiving element 2 and the
  • the light receiving element 2 (see (B) in FIG. 13) is prepared (first step).
  • a wiring layer 5C is formed on the substrate 50, which is a temporary bonding member (second step).
  • the wiring layer 5C includes the insulating layer 51C and the metal wiring 52.
  • the wiring layer 5C shown in FIG. It will be done.
  • the width of the opening 51a of the insulating layer 51C is formed to be larger than the width of the end 6a of the metal pillar 6, and as a result, the width of the portion of the metal wiring 52 connected to the end 6a is The wiring width is formed to be larger than the width of the end portion 6a of the metal pillar 6.
  • the wiring width of the portion of the metal wiring 52 connected to the end 6a may be formed smaller than the width of the end 6a of the metal pillar 6.
  • a metal pillar 6 is formed which is connected to the end 52a of the metal wiring 52 and protrudes from the wiring layer 5C to the side opposite to the substrate 50 side. process).
  • the metal pillar 6 is formed, for example, by plating, solder bump forming, or the like.
  • the light receiving element 2 is placed on the wiring layer 5C so that the end 52b of the metal wiring 52 and the electrode terminal 22 are electrically connected ( 4th step).
  • the end portion 52b and the electrode terminal 22 are connected, for example, by bump bonding.
  • the insulating layer 51C and the insulating layer 23 are brought into contact with each other, and no gap is formed between the insulating layer 51C and the insulating layer 23.
  • the end portion 52b and the electrode terminal 22 may be connected by hybrid bonding using copper and an insulating film.
  • mold resin 3 is formed (fifth step).
  • the mold resin 3 is formed to cover the light receiving element 2, the metal pillar 6, and the wiring layer 5C.
  • the mold resin 3 is polished or ground from the side facing the second surface 2b of the light-receiving element 2 (i.e., the end surface 3b side), so that the light-receiving element 2 is polished or ground.
  • the second surface 2b and the end portion 6b of the metal pillar 6 are exposed (sixth step).
  • the end surface 3b of the molded resin 3 and the second surface 2b of the light-receiving element 2 may also be polished or ground.
  • the end portion 6b of the metal pillar 6 may also be polished or ground.
  • a wiring layer 4 is formed on the second surface 2b of the light receiving element 2 and on the end surface 3b of the molded resin 3 that is continuous with the second surface 2b. 7th step).
  • an insulating layer 41 and metal wiring 42 are formed on the second surface 2b of the light receiving element 2, the end 6b of the metal pillar 6, and the end surface 3b of the molded resin 3.
  • a plated portion 43 is formed on the surface of the outer end portion.
  • the width of the opening 41a of the insulating layer 41 is formed to be larger than the width of the end 6b of the metal pillar 6, and as a result, the width of the portion of the metal wiring 42 connected to the end 6b is The wiring width is formed to be larger than the width of the end portion 6b of the metal pillar 6.
  • the wiring width of the portion of the metal wiring 42 connected to the end 6b may be formed smaller than the width of the end 6b of the metal pillar 6.
  • the substrate 50 is separated from the wiring layer 5 and the mold resin 3 (eighth step). Subsequently, dicing is performed along the boundary line L between the unit areas. Thereby, a plurality of individualized optical semiconductor packages 1C are obtained.
  • the optical semiconductor package 1C can be manufactured by the steps of forming the wiring layer 4 on the back surface side (second surface 2b side) of the light receiving element 2.
  • substrate 50 from the wiring layer 5 etc. may be performed at arbitrary timing after the 5th process is completed. For example, substrate 50 may be removed immediately after completing the fifth step.
  • the sixth and seventh steps there is an advantage that the sixth and seventh steps can be carried out with high reliability while increasing the support stability of each member. It will be done.
  • a wiring layer 5 including an insulating layer 51 and a metal wiring 52 and provided with an opening 51b for exposing the substrate 50 is placed on a substrate.
  • a wiring layer 5 including an insulating layer 51 and a metal wiring 52 and provided with an opening 51b for exposing the substrate 50 is placed on a substrate.
  • the fourth step of the method for manufacturing the optical semiconductor package 1C described above is performed at a position where the end portion 52b of the metal wiring 52 and the electrode terminal 22 are electrically connected, and the light receiving portion 21 faces the opening portion 51b.
  • "4th step” in which the light receiving element 2 is arranged on the wiring layer 5 so that a closed space S1 is formed between the substrate 50 and the light receiving element 2.
  • the structure shown in FIG. 16(B) is obtained instead of the structure shown in FIG. 13(B).
  • the closed space S1 is a sealed space surrounded by the substrate 50, the insulating layer 23, and the insulating layer 51.
  • the mold resin 3 is formed to cover the light receiving element 2, the metal pillar 6, and the wiring layer 5, and the mold resin 3 is not filled in the closed space S1.
  • the present disclosure is not limited to the above embodiments.
  • the materials and shapes of each structure are not limited to the materials and shapes described above, but various materials and shapes can be employed.
  • some of the configurations in one embodiment or modification example described above can be arbitrarily applied to the configurations in other embodiments or modification examples.
  • the substrate 50 can be suitably used as a temporary bonding member, but the temporary bonding member may be a member other than the substrate.
  • a sheet member for example, a very thin sheet-like member
  • a manufacturing method using a CoW method or a CoP method is exemplified, but methods other than the above may be adopted.
  • the dicing step in the above embodiment can be omitted.
  • 1A, 1B, 1C... Optical semiconductor package 2... Light receiving element, 2a... First surface, 2b... Second surface, 3, 3B... Mold resin (resin part), 4... Wiring layer (first wiring layer, second wiring layer), 5... wiring layer (first wiring layer, second wiring layer), 6, 6A... metal pillar (metal member), 6a... end (first end), 6b... end (second end) part), 21... Light receiving part, 22... Electrode terminal, 42... Metal wiring (first metal wiring, second metal wiring), 50... Substrate, 51b... Opening, 52... Metal wiring (first metal wiring, second metal wiring) metal wiring), 61... shaft portion, 62... flange portion, 62a... inner surface, 100... support member, 101... plate member, 101a... through hole, 102... support substrate.

Abstract

This method for manufacturing an optical semiconductor package comprises: a first step for temporarily bonding a light reception element and a first end of a metal pillar to a substrate; a second step for forming on the substrate a mold resin covering the light reception element and the metal pillar; a third step for polishing or grinding the mold resin from the side facing a second surface of the light reception element, to expose the second surface of the light reception element and a second end of the metal pillar; a fourth step for forming a first wiring layer on the second surface of the light reception element and on an end surface of the mold resin; a fifth step for separating the substrate from the light reception element, the metal pillar, and the mold resin; and a sixth step for, after the fifth step, forming a second wiring layer on the side, with respect to the light reception element and the mold resin, opposite to the side on which the first wiring layer is positioned.

Description

光半導体パッケージの製造方法Manufacturing method of optical semiconductor package
 本開示は、光半導体パッケージの製造方法に関する。 The present disclosure relates to a method for manufacturing an optical semiconductor package.
 特許文献1には、受光素子を含む半導体パッケージの製造方法が開示されている。特許文献1に開示された製造方法においては、ガラス基板上に柱状電極を含む接続用配線が形成され、接続用配線上に受光素子(光電変換デバイス領域(受光部)が設けられたシリコン基板)が搭載され、受光素子とガラス基板との間に樹脂からなる第1封止膜(アンダーフィル)が充填された後に、さらにガラス基板の上面全体が樹脂からなる第2封止膜で覆われる。 Patent Document 1 discloses a method for manufacturing a semiconductor package including a light receiving element. In the manufacturing method disclosed in Patent Document 1, a connection wiring including a columnar electrode is formed on a glass substrate, and a light receiving element (a silicon substrate provided with a photoelectric conversion device region (light receiving part)) is formed on the connection wiring. is mounted and a first sealing film (underfill) made of resin is filled between the light receiving element and the glass substrate, and then the entire upper surface of the glass substrate is further covered with a second sealing film made of resin.
特許第4126389号公報Patent No. 4126389
 上記製造方法では、第1封止膜によって受光部が覆われてしまうため、受光感度が低下するおそれがある。また、第1封止膜と第2封止膜との界面が接続用配線に接触しているため、第1封止膜と第2封止膜との間の熱膨張係数差等に起因する応力が接続用配線に集中し、接続用配線が損傷するおそれがある。このように、上記製造方法には、半導体パッケージの信頼性の観点において、改善の余地がある。 In the above manufacturing method, since the light-receiving section is covered with the first sealing film, there is a risk that the light-receiving sensitivity may decrease. In addition, since the interface between the first sealing film and the second sealing film is in contact with the connection wiring, the thermal expansion coefficient difference between the first sealing film and the second sealing film, etc. Stress is concentrated on the connection wiring, and there is a risk that the connection wiring may be damaged. As described above, the above manufacturing method has room for improvement in terms of reliability of the semiconductor package.
 本開示は、信頼性の向上を図ることができる光半導体パッケージの製造方法を提供することを目的とする。 An object of the present disclosure is to provide a method for manufacturing an optical semiconductor package that can improve reliability.
 本開示の一側面に係る光半導体パッケージの製造方法は、受光部及び受光部と電気的に接続された電極端子が設けられた第1面を有する受光素子と、柱状の金属部材の第1端部と、を基板に仮接合する第1工程であって、第1面が基板に対向するように受光素子を基板に仮接合する第1工程と、受光素子及び金属部材を覆う樹脂部を基板上に形成する第2工程と、受光素子の第1面とは反対側の第2面に対向する側から樹脂部を研磨又は研削することにより、受光素子の第2面と金属部材の第1端部とは反対側の第2端部とを露出させる第3工程と、受光素子の第2面上、及び第2面と連続する樹脂部の端面上に、第2端部と電気的に接続される第1金属配線を含む第1配線層を形成する第4工程と、受光素子、金属部材、及び樹脂部から基板を分離する第5工程と、第5工程よりも後に、受光素子及び樹脂部に対して第1配線層が位置する側とは反対側に、第1端部と電極端子とを電気的に接続する第2金属配線を含む第2配線層を形成する第6工程と、を含む。 A method for manufacturing an optical semiconductor package according to one aspect of the present disclosure includes a light receiving element having a first surface provided with a light receiving portion and an electrode terminal electrically connected to the light receiving portion, and a first end of a columnar metal member. A first step of temporarily bonding the light-receiving element to the substrate such that the first surface faces the substrate; and a first step of temporarily bonding the light-receiving element and the metal member to the substrate; The second surface of the light receiving element and the first surface of the metal member are formed by polishing or grinding the resin part from the side opposite to the second surface of the light receiving element, which is opposite to the first surface of the light receiving element. A third step of exposing the second end opposite to the end, and electrically exposing the second end on the second surface of the light receiving element and on the end surface of the resin part continuous with the second surface. A fourth step of forming a first wiring layer including the first metal wiring to be connected; a fifth step of separating the substrate from the light receiving element, the metal member, and the resin part; and after the fifth step, the light receiving element and a sixth step of forming a second wiring layer including a second metal wiring electrically connecting the first end portion and the electrode terminal on a side opposite to the side where the first wiring layer is located with respect to the resin part; ,including.
 上記製造方法では、第1工程において、基板と受光素子との間に隙間が形成されないように、受光素子が基板に仮接合される。これにより、第2工程において、受光素子と基板との間に樹脂が流れ込むこと、すなわち、受光部に対向する位置に樹脂部が形成されることを防止することができる。その結果、受光部が樹脂部に覆われることに起因する受光感度の低下を回避することができる。また、受光素子及び金属部材が基板に仮接合されることによって各部材が安定的に固定された状態で、第2工程を安定的且つ精度良く実施することが可能となる。以上により、上記製造方法によれば、光半導体パッケージを信頼性高く製造することができる。 In the above manufacturing method, in the first step, the light receiving element is temporarily bonded to the substrate so that no gap is formed between the substrate and the light receiving element. Thereby, in the second step, it is possible to prevent the resin from flowing between the light receiving element and the substrate, that is, to prevent the resin portion from being formed at a position facing the light receiving portion. As a result, it is possible to avoid a decrease in light-receiving sensitivity due to the light-receiving part being covered with the resin part. Further, by temporarily bonding the light receiving element and the metal member to the substrate, it is possible to stably and accurately perform the second step in a state in which each member is stably fixed. As described above, according to the above manufacturing method, an optical semiconductor package can be manufactured with high reliability.
 第1工程は、支持部材によって、第1端部を露出させた状態で金属部材を位置決めすると共に支持する工程と、支持部材に支持されている金属部材の第1端部に対して、基板の仮接合面を接触させることにより、基板に第1端部を仮接合する工程と、を含んでもよい。上記構成によれば、支持部材によって位置決め及び支持された状態の金属部材に基板の仮接合面を接触させる比較的簡易な操作によって、基板に金属部材を仮接合することができる。 The first step includes positioning and supporting the metal member with the first end exposed by the support member, and positioning the substrate with respect to the first end of the metal member supported by the support member. The step of temporarily joining the first end portion to the substrate by bringing the temporary joining surfaces into contact may be included. According to the above configuration, the metal member can be temporarily bonded to the substrate by a relatively simple operation of bringing the temporary bonding surface of the substrate into contact with the metal member positioned and supported by the support member.
 支持部材は、金属部材の幅よりも大きい幅を有する貫通孔が形成された板状部材と、第2端部が載置及び支持される支持基板と、を有してもよく、金属部材は、板状部材の貫通孔に挿通されて位置決めされると共に、支持基板に支持されてもよく、金属部材が支持部材に支持された状態において、第1端部は、板状部材に対して支持基板側とは反対側に突出していてもよい。上記構成によれば、金属部材の第1端部が板状部材よりも突出した状態で、金属部材が支持部材によって支持されるため、基板の仮接合面を第1端部に接触させる際に、基板の仮接合面が板状部材に接触することを防止することができる。すなわち、基板の仮接合面が板状部材に貼り付いてしまうことを的確に防止することができる。 The support member may include a plate-like member in which a through hole having a width larger than the width of the metal member is formed, and a support substrate on which the second end portion is placed and supported, and the metal member may be inserted into and positioned through the through hole of the plate-shaped member and supported by the support substrate, and in a state where the metal member is supported by the support member, the first end portion is supported with respect to the plate-shaped member. It may protrude on the side opposite to the substrate side. According to the above configuration, since the metal member is supported by the support member in a state where the first end of the metal member protrudes beyond the plate-like member, when the temporary bonding surface of the substrate is brought into contact with the first end, , it is possible to prevent the temporarily bonded surface of the substrate from coming into contact with the plate member. That is, it is possible to accurately prevent the temporarily bonded surface of the substrate from sticking to the plate-like member.
 金属部材は、第2端部を含む軸部と、第1端部を含み且つ軸部よりも幅広に形成されたフランジ部と、を有してもよく、支持部材は、軸部の幅よりも大きくフランジ部の幅よりも小さい幅を有する貫通孔が形成された板状部材であってもよく、金属部材は、軸部が貫通孔に挿通され、フランジ部の第2端部側の内面が支持部材の貫通孔の周縁部に当接することによって、支持部材に支持されてもよい。上記構成によれば、フランジ部を板状部材の貫通孔の周縁部に引っかけて支持することが可能となる。すなわち、第2端部を支持するための支持基板が不要となるため、支持部材を簡素化することができる。また、フランジ部を設けることにより、基板上に立設される金属部材の姿勢(垂直性)をより安定化させることができる。 The metal member may include a shaft portion including the second end portion and a flange portion including the first end portion and formed wider than the shaft portion, and the supporting member may have a width wider than the shaft portion. The metal member may be a plate-like member in which a through hole having a width smaller than the width of the flange portion is formed. may be supported by the support member by coming into contact with the peripheral edge of the through hole of the support member. According to the above configuration, it is possible to support the flange portion by hooking it onto the peripheral edge of the through hole of the plate-shaped member. That is, since a support substrate for supporting the second end is not required, the support member can be simplified. Further, by providing the flange portion, the posture (verticality) of the metal member erected on the substrate can be more stabilized.
 第4工程において、第1金属配線における第2端部に接続される部分の配線幅が金属部材の第2端部の幅よりも大きくなるように、第1配線層を形成してもよい。上記構成によれば、第2工程(樹脂部形成工程)において生じ得る金属部材の位置ずれを吸収することができる。すなわち、第1金属配線の配線幅を大きくすることにより、第2工程において金属部材の位置が多少ずれたとしても、第1金属配線と金属部材(第2端部)とをより確実に接触させることができる。 In the fourth step, the first wiring layer may be formed such that the width of the portion of the first metal wiring connected to the second end is larger than the width of the second end of the metal member. According to the above configuration, it is possible to absorb the positional shift of the metal member that may occur in the second step (resin portion forming step). That is, by increasing the wiring width of the first metal wiring, even if the position of the metal member is slightly shifted in the second step, the first metal wiring and the metal member (second end) can be brought into contact more reliably. be able to.
 第4工程において、第1金属配線における第2端部に接続される部分の配線幅が金属部材の第2端部の幅よりも小さくなるように、第1配線層を形成してもよい。上記構成によれば、金属部材の大きさ(幅)の影響を受けずに、第1金属配線を形成することができる。例えば、金属部材(第2端部)の幅が比較的大きい場合に第1金属配線の幅を金属部材の幅よりもさらに大きくすると、第1金属配線が第1配線層に設けられる他の配線と干渉し易くなるという問題が生じ得る。上記構成によれば、このような問題の発生を回避することができる。 In the fourth step, the first wiring layer may be formed such that the width of the portion of the first metal wiring connected to the second end is smaller than the width of the second end of the metal member. According to the above configuration, the first metal wiring can be formed without being influenced by the size (width) of the metal member. For example, if the width of the first metal wiring is made larger than the width of the metal member when the width of the metal member (second end portion) is relatively large, the first metal wiring may be connected to other wiring provided in the first wiring layer. A problem may arise in that it is easy to interfere with the According to the above configuration, occurrence of such a problem can be avoided.
 第6工程において、第2金属配線における第1端部に接続される部分の配線幅が金属部材の第1端部の幅よりも大きくなるように、第2配線層を形成してもよい。上記構成によれば、第2工程(樹脂部形成工程)において生じ得る金属部材の位置ずれを吸収することができる。すなわち、第2金属配線の配線幅を大きくすることにより、第2工程において金属部材の位置が多少ずれたとしても、第2金属配線と金属部材(第1端部)とをより確実に接触させることができる。 In the sixth step, the second wiring layer may be formed such that the wiring width of the portion of the second metal wiring connected to the first end is larger than the width of the first end of the metal member. According to the above configuration, it is possible to absorb the positional shift of the metal member that may occur in the second step (resin portion forming step). That is, by increasing the wiring width of the second metal wiring, even if the position of the metal member is slightly shifted in the second step, the second metal wiring and the metal member (first end) can be brought into contact more reliably. be able to.
 第6工程において、第2金属配線における第1端部に接続される部分の配線幅が金属部材の第1端部の幅よりも小さくなるように、第2配線層を形成してもよい。上記構成によれば、金属部材の大きさ(幅)の影響を受けずに、第2金属配線を形成することができる。例えば、金属部材(第1端部)の幅が比較的大きい場合に第2金属配線の幅を金属部材の幅よりもさらに大きくすると、第2金属配線が第2配線層に設けられる他の配線と干渉し易くなるという問題が生じ得る。上記構成によれば、このような問題の発生を回避することができる。 In the sixth step, the second wiring layer may be formed such that the wiring width of the portion of the second metal wiring connected to the first end is smaller than the width of the first end of the metal member. According to the above configuration, the second metal wiring can be formed without being influenced by the size (width) of the metal member. For example, when the width of the metal member (first end portion) is relatively large, if the width of the second metal wiring is made larger than the width of the metal member, the second metal wiring may be connected to other wiring provided in the second wiring layer. A problem may arise in that it is easy to interfere with the According to the above configuration, occurrence of such a problem can be avoided.
 第5工程は、少なくとも第3工程よりも後に実施されてもよい。また、第4工程は、第3工程の後に実施されてもよく、第5工程は、第4工程の後に実施されてもよい。上記構成によれば、基板を第3工程(或いは、第3工程及び第4工程)においても取り付けた状態にすることによって、各部材の支持安定性を高めた状態で第3工程(或いは、第3工程及び第4工程)を信頼性高く実施することができる。 The fifth step may be performed at least after the third step. Further, the fourth step may be performed after the third step, and the fifth step may be performed after the fourth step. According to the above configuration, by keeping the substrate attached in the third step (or the third step and the fourth step), the third step (or the third step and the fourth step) is performed with the support stability of each member increased. 3 and 4) can be performed with high reliability.
 受光素子は、第1面に受光面を有してもよい。上記構成によれば、表面入射型の受光素子の表面が第1面である光半導体パッケージを信頼性高く製造することができる。 The light receiving element may have a light receiving surface on the first surface. According to the above configuration, an optical semiconductor package in which the surface of the front-illuminated light receiving element is the first surface can be manufactured with high reliability.
 本開示の他の側面に係る光半導体パッケージの製造方法は、基板上に、第1金属配線を含むと共に基板を露出させる開口部が設けられた第1配線層を形成する第1工程と、第1金属配線の第1端部に接続され、第1配線層から基板側とは反対側に突出する金属部材を形成する第2工程と、受光部及び受光部と電気的に接続された電極端子が設けられた第1面を有する受光素子を準備する第3工程と、第1端部とは異なる第1金属配線の第2端部と電極端子とが電気的に接続され、且つ、受光部が開口部に対向する位置に配置されて基板と受光素子との間に内部空間が形成されるように、受光素子を配置する第4工程と、受光素子、金属部材、及び第1配線層を覆うと共に内部空間に充填され、受光部の検出対象となる光に対する透明性を有する樹脂部を形成する第5工程と、受光素子の第1面とは反対側の第2面に対向する側から樹脂部を研磨又は研削することにより、第2面と金属部材の第1金属配線に接続される側とは反対側の端部とを露出させる第6工程と、受光素子の第2面上、及び第2面と連続する樹脂部の端面上に、金属部材の端部と電気的に接続される第2金属配線を含む第2配線層を形成する第7工程と、第1配線層及び樹脂部から基板を分離する第8工程と、を含む。 A method for manufacturing an optical semiconductor package according to another aspect of the present disclosure includes a first step of forming, on a substrate, a first wiring layer that includes a first metal wiring and is provided with an opening that exposes the substrate; 1. A second step of forming a metal member connected to the first end of the metal wiring and protruding from the first wiring layer to the side opposite to the substrate side, and a light receiving section and an electrode terminal electrically connected to the light receiving section. A third step of preparing a light-receiving element having a first surface provided with a fourth step of arranging the light receiving element such that the light receiving element is disposed at a position facing the opening and an internal space is formed between the substrate and the light receiving element; and the light receiving element, the metal member, and the first wiring layer are arranged. a fifth step of forming a resin part that covers and fills the internal space and is transparent to the light to be detected by the light receiving element, and from the side facing the second surface opposite to the first surface of the light receiving element; a sixth step of exposing the second surface and the end of the metal member on the side opposite to the side connected to the first metal wiring by polishing or grinding the resin part; and on the second surface of the light receiving element; and a seventh step of forming a second wiring layer including a second metal wiring electrically connected to the end of the metal member on the end surface of the resin part continuous with the second surface, and the first wiring layer and the resin. and an eighth step of separating the substrate from the part.
 上記製造方法では、第5工程において樹脂部が受光素子と基板との間の内部空間に充填されることにより、樹脂部が受光部を覆うことになるが、樹脂部は受光部の検出対象となる光に対する透明性を有するため、樹脂部が受光部を覆うことに起因する受光感度の低下が抑制される。さらに、第5工程において、単一の樹脂材料によって一括で、受光素子と基板との間の内部空間に充填され且つ各部材(受光素子、金属部材、及び第1配線層)を覆う樹脂部を形成することができる。これにより、2種類の樹脂部(例えば、互いに異なる材料又は異なるタイミングで形成される2つの樹脂部)が混在することに起因する信頼性の低下(例えば、2つの樹脂部の熱膨張係数差等に起因する応力による金属配線の損傷等)を回避することができる。以上により、上記製造方法によれば、光半導体パッケージを信頼性高く製造することができる。 In the above manufacturing method, the resin part covers the light receiving part by filling the internal space between the light receiving element and the substrate in the fifth step, but the resin part is not detected by the light receiving part. Since the resin part has transparency to light, a decrease in light-receiving sensitivity caused by the resin part covering the light-receiving part is suppressed. Furthermore, in the fifth step, a resin portion is formed by a single resin material, filling the internal space between the light receiving element and the substrate and covering each member (the light receiving element, the metal member, and the first wiring layer). can be formed. This reduces reliability due to the coexistence of two types of resin parts (for example, two resin parts formed from different materials or at different times) (for example, due to differences in thermal expansion coefficients between the two resin parts). (damage to metal wiring due to stress caused by stress, etc.) can be avoided. As described above, according to the above manufacturing method, an optical semiconductor package can be manufactured with high reliability.
 第8工程は、少なくとも第6工程よりも後に実施されてもよい。また、第7工程は、第6工程の後に実施されてもよく、第8工程は、第7工程の後に実施されてもよい。上記構成によれば、基板を第6工程(或いは、第6工程及び第7工程)においても取り付けた状態にすることによって、各部材の支持安定性を高めた状態で第6工程(或いは、第6工程及び第7工程)を信頼性高く実施することができる。 The eighth step may be performed at least after the sixth step. Further, the seventh step may be performed after the sixth step, and the eighth step may be performed after the seventh step. According to the above configuration, by keeping the substrate attached in the sixth step (or the sixth step and the seventh step), the sixth step (or the sixth step and the seventh step) is performed with the support stability of each member increased. 6 and 7) can be performed with high reliability.
 受光素子は、第1面に受光面を有してもよい。上記構成によれば、表面入射型の受光素子の表面が第1面である光半導体パッケージを信頼性高く製造することができる。 The light receiving element may have a light receiving surface on the first surface. According to the above configuration, an optical semiconductor package in which the surface of the front-illuminated light receiving element is the first surface can be manufactured with high reliability.
 本開示によれば、信頼性の向上を図ることができる光半導体パッケージの製造方法を提供することができる。 According to the present disclosure, it is possible to provide a method for manufacturing an optical semiconductor package that can improve reliability.
図1は、第1実施形態の光半導体パッケージの断面図である。FIG. 1 is a cross-sectional view of the optical semiconductor package of the first embodiment. 図2は、図1の光半導体パッケージの製造工程の一例を示す図である。FIG. 2 is a diagram showing an example of the manufacturing process of the optical semiconductor package of FIG. 1. 図3は、図1の光半導体パッケージの製造工程の一例を示す図である。FIG. 3 is a diagram showing an example of the manufacturing process of the optical semiconductor package of FIG. 1. 図4は、図1の光半導体パッケージの製造工程の一例を示す図である。FIG. 4 is a diagram showing an example of the manufacturing process of the optical semiconductor package of FIG. 1. 図5は、図1の光半導体パッケージの製造工程の一例を示す図である。FIG. 5 is a diagram showing an example of the manufacturing process of the optical semiconductor package of FIG. 1. 図6は、図1の光半導体パッケージの製造工程の一例を示す図である。FIG. 6 is a diagram showing an example of the manufacturing process of the optical semiconductor package of FIG. 1. 図7は、図1の光半導体パッケージの製造工程の一例を示す図である。FIG. 7 is a diagram showing an example of the manufacturing process of the optical semiconductor package of FIG. 1. 図8は、第2実施形態の光半導体パッケージの断面図である。FIG. 8 is a cross-sectional view of the optical semiconductor package of the second embodiment. 図9は、図8の光半導体パッケージの製造工程の一例を示す図である。FIG. 9 is a diagram showing an example of the manufacturing process of the optical semiconductor package of FIG. 8. 図10は、図8の光半導体パッケージの製造工程の一例を示す図である。FIG. 10 is a diagram showing an example of the manufacturing process of the optical semiconductor package of FIG. 8. 図11は、図8の光半導体パッケージの製造工程の一例を示す図である。FIG. 11 is a diagram showing an example of the manufacturing process of the optical semiconductor package of FIG. 8. 図12は、第3実施形態の光半導体パッケージの断面図である。FIG. 12 is a cross-sectional view of the optical semiconductor package of the third embodiment. 図13は、図12の光半導体パッケージの製造工程の一例を示す図である。FIG. 13 is a diagram showing an example of the manufacturing process of the optical semiconductor package of FIG. 12. 図14は、図12の光半導体パッケージの製造工程の一例を示す図である。FIG. 14 is a diagram showing an example of the manufacturing process of the optical semiconductor package of FIG. 12. 図15は、図12の光半導体パッケージの製造工程の一例を示す図である。FIG. 15 is a diagram showing an example of the manufacturing process of the optical semiconductor package of FIG. 12. 図16は、図1の光半導体パッケージの製造方法の変形例を示す図である。FIG. 16 is a diagram showing a modification of the method for manufacturing the optical semiconductor package shown in FIG.
 以下、本開示の実施形態について図面を参照しながら説明する。各図において同一又は相当の部分には同一の符号を付し、重複する説明を省略する。なお、図面においては、実施形態に係る特徴部分を分かり易く説明するために誇張している部分がある。このため、図面の寸法比率は、実際の寸法比率とは異なっている場合がある。 Hereinafter, embodiments of the present disclosure will be described with reference to the drawings. In each figure, the same or corresponding parts are denoted by the same reference numerals, and redundant explanations will be omitted. Note that in the drawings, some portions are exaggerated in order to clearly explain characteristic portions of the embodiments. Therefore, the dimensional ratios in the drawings may differ from the actual dimensional ratios.
[第1実施形態]
(光半導体パッケージの構造)
 図1に示されるように、第1実施形態の光半導体パッケージ1Aは、受光素子2と、モールド樹脂3(樹脂部)と、配線層4(第1配線層)と、配線層5(第2配線層)と、金属ピラー6(金属部材)と、を有している。光半導体パッケージ1Aは、FOWLP(Fan Out Wafer Level Package)/FOPLP(Fan Out Panel Level Package)の一種である。
[First embodiment]
(Structure of optical semiconductor package)
As shown in FIG. 1, the optical semiconductor package 1A of the first embodiment includes a light receiving element 2, a mold resin 3 (resin part), a wiring layer 4 (first wiring layer), and a wiring layer 5 (second wiring layer). wiring layer) and a metal pillar 6 (metal member). The optical semiconductor package 1A is a type of FOWLP (Fan Out Wafer Level Package)/FOPLP (Fan Out Panel Level Package).
 受光素子2は、受光部21を有する半導体チップであり、矩形板状に形成されている。受光素子2は、第1面2aと、第2面2bと、を有している。図1においては、第1面2aと第2面2bとが対向する対向方向をZ軸方向と表し、Z軸方向から見た場合の受光素子2の一の辺に沿った方向をX軸方向と表し、Z軸方向から見た場合の受光素子2の他の辺(上記一の辺に垂直な辺)に沿った方向をY軸方向と表している。 The light receiving element 2 is a semiconductor chip having a light receiving section 21, and is formed into a rectangular plate shape. The light receiving element 2 has a first surface 2a and a second surface 2b. In FIG. 1, the direction in which the first surface 2a and the second surface 2b face each other is expressed as the Z-axis direction, and the direction along one side of the light-receiving element 2 when viewed from the Z-axis direction is expressed as the X-axis direction. The direction along the other side (the side perpendicular to the above-mentioned one side) of the light receiving element 2 when viewed from the Z-axis direction is expressed as the Y-axis direction.
 第1面2aには、受光部21と、受光部21と電気的に接続された複数(本実施形態では2つ)の電極端子22と、が設けられている。本実施形態では一例として、Z軸方向から見た場合の第1面2aの略中央部に1つの受光部21が設けられているが、複数の受光部21が第1面2aに設けられてもよい。この場合、複数の受光部21は、例えば、Z軸方向から見た場合に、一次元又は二次元に配列され得る。受光部21は、第1面に沿った位置に配置されている。すなわち、受光素子2は、第1面2aに受光面を有している。より具体的には、第1面2aのうち受光部21に対向する部分が受光面として機能する。図1の例では、受光部21は、受光部21の光入射面(第1面2a側の面)が第1面2aと略面一となるように、受光素子2に埋設されている。受光部21の例としては、Siフォトダイオード(SiPD)、Siアバランシェ・フォトダイオード(SiAPD)、Si-MPPC(Multi-Pixel Photon Counter)等が挙げられる。2つの電極端子22は、第1面2a上に突出するように設けられている。 A light receiving section 21 and a plurality of (two in this embodiment) electrode terminals 22 electrically connected to the light receiving section 21 are provided on the first surface 2a. In this embodiment, as an example, one light receiving section 21 is provided at approximately the center of the first surface 2a when viewed from the Z-axis direction, but a plurality of light receiving sections 21 are provided on the first surface 2a. Good too. In this case, the plurality of light receiving sections 21 may be arranged one-dimensionally or two-dimensionally, for example, when viewed from the Z-axis direction. The light receiving section 21 is arranged at a position along the first surface. That is, the light receiving element 2 has a light receiving surface on the first surface 2a. More specifically, the portion of the first surface 2a that faces the light receiving section 21 functions as a light receiving surface. In the example of FIG. 1, the light receiving section 21 is embedded in the light receiving element 2 so that the light incident surface (the surface on the first surface 2a side) of the light receiving section 21 is substantially flush with the first surface 2a. Examples of the light receiving section 21 include a Si photodiode (SiPD), a Si avalanche photodiode (SiAPD), and a Si-MPPC (Multi-Pixel Photon Counter). The two electrode terminals 22 are provided so as to protrude above the first surface 2a.
 第1面2a上には、絶縁層23が設けられている。絶縁層23は、第1面2a上に設けられた複数(本実施形態では2つ)の電極端子22を囲むように設けられている。絶縁層23には、各電極端子22を露出させるための開口23aが形成されている。絶縁層23は、例えば二酸化ケイ素(SiO)、窒化ケイ素(Si)等の無機膜、或いはポリイミド等の有機膜によって形成され得る。 An insulating layer 23 is provided on the first surface 2a. The insulating layer 23 is provided so as to surround a plurality of (two in this embodiment) electrode terminals 22 provided on the first surface 2a. Openings 23a are formed in the insulating layer 23 to expose each electrode terminal 22. The insulating layer 23 may be formed of an inorganic film such as silicon dioxide (SiO 2 ) or silicon nitride (Si 3 N 4 ), or an organic film such as polyimide.
 モールド樹脂3は、Z軸方向から見た場合に受光素子2を包囲するように、受光素子2の側面を封止している。モールド樹脂3は、金属ピラー6も覆っている。モールド樹脂3は、例えばエポキシ樹脂等によって形成され得る。モールド樹脂3は、絶縁層23の表面と面一に形成された端面3aと、受光素子2の第2面2bと面一に形成された端面3bと、を有している。 The mold resin 3 seals the side surface of the light receiving element 2 so as to surround the light receiving element 2 when viewed from the Z-axis direction. The mold resin 3 also covers the metal pillar 6. The mold resin 3 may be made of, for example, epoxy resin. The mold resin 3 has an end surface 3a formed flush with the surface of the insulating layer 23, and an end surface 3b formed flush with the second surface 2b of the light receiving element 2.
 配線層4は、受光素子2の第2面2b側において、受光素子2の第2面2b上、及び第2面2bと連続するモールド樹脂3の端面3b上に設けられている。配線層4は、絶縁層41と、金属配線42(第1金属配線)と、を含んで構成される再配線層である。絶縁層41は、例えば二酸化ケイ素(SiO)、窒化ケイ素(Si)等の無機膜、或いはポリイミド等の有機膜によって形成され得る。金属配線42は、例えば銅(Cu)配線である。 The wiring layer 4 is provided on the second surface 2b side of the light receiving element 2, on the second surface 2b of the light receiving element 2, and on the end surface 3b of the molded resin 3 continuous with the second surface 2b. The wiring layer 4 is a rewiring layer including an insulating layer 41 and a metal wiring 42 (first metal wiring). The insulating layer 41 may be formed of, for example, an inorganic film such as silicon dioxide (SiO 2 ) or silicon nitride (Si 3 N 4 ), or an organic film such as polyimide. The metal wiring 42 is, for example, a copper (Cu) wiring.
 絶縁層41のうちZ軸方向において金属ピラー6と重なる部分には、開口41aが設けられている。開口41a内には、金属ピラー6の配線層4側の端部6b(第2端部)と電気的に接続される金属配線42が設けられている。開口41aの幅は、金属ピラー6の端部6bの幅よりも大きくされている。これにより、金属配線42における端部6bに接続される部分の配線幅w11が金属ピラー6の端部6bの幅w12よりも大きくなっている。 An opening 41a is provided in a portion of the insulating layer 41 that overlaps with the metal pillar 6 in the Z-axis direction. A metal wiring 42 electrically connected to the end 6b (second end) of the metal pillar 6 on the wiring layer 4 side is provided in the opening 41a. The width of the opening 41a is made larger than the width of the end portion 6b of the metal pillar 6. As a result, the wiring width w11 of the portion of the metal wiring 42 connected to the end 6b is larger than the width w12 of the end 6b of the metal pillar 6.
 金属配線42の外側端部(Z軸方向において金属ピラー6とは反対側に位置する端部)には、めっき部43が設けられている。めっき部43は、例えば半田等によってプリント基板等に接合される部分である。めっき部43は、例えばニッケル及び金の二層めっき(Ni/Auめっき)である。 A plated portion 43 is provided at the outer end of the metal wiring 42 (the end located on the opposite side from the metal pillar 6 in the Z-axis direction). The plated portion 43 is a portion that is bonded to a printed circuit board or the like using, for example, solder. The plated portion 43 is, for example, two-layer plating of nickel and gold (Ni/Au plating).
 配線層5は、受光素子2及びモールド樹脂3に対して配線層4が位置する側とは反対側に設けられている。すなわち、配線層5は、受光素子2の第1面2a側において、絶縁層23上及びモールド樹脂3の端面3a上に設けられている。配線層5は、絶縁層51と、金属配線52(第2金属配線)と、を含んで構成される再配線層である。絶縁層51は、例えば二酸化ケイ素(SiO)、窒化ケイ素(Si)等の無機膜、或いはポリイミド等の有機膜によって形成され得る。金属配線52は、例えば銅(Cu)配線である。 The wiring layer 5 is provided on the side opposite to the side where the wiring layer 4 is located with respect to the light receiving element 2 and the mold resin 3. That is, the wiring layer 5 is provided on the insulating layer 23 and on the end surface 3a of the molded resin 3 on the first surface 2a side of the light receiving element 2. The wiring layer 5 is a rewiring layer including an insulating layer 51 and a metal wiring 52 (second metal wiring). The insulating layer 51 may be formed of, for example, an inorganic film such as silicon dioxide (SiO 2 ) or silicon nitride (Si 3 N 4 ), or an organic film such as polyimide. The metal wiring 52 is, for example, a copper (Cu) wiring.
 絶縁層51のうちZ軸方向において金属ピラー6と重なる部分には、開口51aが設けられている。開口51a内には、金属ピラー6の配線層5側の端部6a(第1端部)と電気的に接続される金属配線52が設けられている。開口51aの幅は、金属ピラー6の端部6aの幅よりも大きくされている。これにより、金属配線52における端部6aに接続される部分の配線幅w21が金属ピラー6の端部6aの幅w22よりも大きくなっている。 An opening 51a is provided in a portion of the insulating layer 51 that overlaps with the metal pillar 6 in the Z-axis direction. A metal wiring 52 electrically connected to the end 6a (first end) of the metal pillar 6 on the wiring layer 5 side is provided in the opening 51a. The width of the opening 51a is made larger than the width of the end portion 6a of the metal pillar 6. As a result, the wiring width w21 of the portion of the metal wiring 52 connected to the end 6a is larger than the width w22 of the end 6a of the metal pillar 6.
 絶縁層51のうちZ軸方向において受光部21と重なる部分には、開口部51bが設けられている。すなわち、絶縁層51は、Z軸方向において受光部21を覆わないように形成されている。 An opening 51b is provided in a portion of the insulating layer 51 that overlaps with the light receiving section 21 in the Z-axis direction. That is, the insulating layer 51 is formed so as not to cover the light receiving section 21 in the Z-axis direction.
 金属配線52は、金属ピラー6の端部6aと受光素子2の電極端子22とを電気的に接続している。すなわち、受光素子2(電極端子22)は、金属配線52、金属ピラー6、及び金属配線42を介して、めっき部43と電気的に接続されている。 The metal wiring 52 electrically connects the end 6a of the metal pillar 6 and the electrode terminal 22 of the light receiving element 2. That is, the light receiving element 2 (electrode terminal 22) is electrically connected to the plating portion 43 via the metal wiring 52, the metal pillar 6, and the metal wiring 42.
 金属ピラー6は、柱状に形成された金属部材である。金属ピラー6は、例えば銅によって形成されている。金属ピラー6は、例えば、いわゆる銅ピラー又は銅ポストである。 The metal pillar 6 is a metal member formed into a columnar shape. The metal pillar 6 is made of copper, for example. The metal pillar 6 is, for example, a so-called copper pillar or a copper post.
 本実施形態では、電極端子22、金属配線52、金属ピラー6、及び金属配線42は、それぞれ2つずつ設けられている。より具体的には、互いに電気的に接続された電極端子22、金属配線52、金属ピラー6、及び金属配線42の組は、Y軸方向から見た場合において、受光部21の両側の各々に設けられている。なお、上述したように複数の受光部21が設けられる場合には、受光部21の数に応じて電極端子22の数(すなわち、上記の組の数)が変動してもよい。 In this embodiment, two electrode terminals 22, two metal wirings 52, two metal pillars 6, and two metal wirings 42 are provided. More specifically, a set of electrode terminals 22, metal wiring 52, metal pillar 6, and metal wiring 42, which are electrically connected to each other, is arranged on each side of the light receiving section 21 when viewed from the Y-axis direction. It is provided. Note that when a plurality of light receiving sections 21 are provided as described above, the number of electrode terminals 22 (that is, the number of the above-mentioned groups) may vary depending on the number of light receiving sections 21.
(光半導体パッケージの製造方法)
 図2~図7を参照して、光半導体パッケージ1Aの製造工程の一例について説明する。本実施形態では、光半導体パッケージ1Aは、CoW(Chip on Wafer)方式又はCoP(Chip on Panel)方式によって製造される。
(Method for manufacturing optical semiconductor package)
An example of the manufacturing process of the optical semiconductor package 1A will be described with reference to FIGS. 2 to 7. In this embodiment, the optical semiconductor package 1A is manufactured by a CoW (Chip on Wafer) method or a CoP (Chip on Panel) method.
 まず、図2に示されるように、受光素子2と金属ピラー6の端部6aとが、仮接合部材である基板50の仮接合面50a(例えば仮接合用の接着剤が塗布された面)に仮接合される(第1工程)。すなわち、受光素子2及び金属ピラー6は、後で取り外すことが可能な態様で、一時的に基板50に接合される。受光素子2は、第1面2aが基板50に対向するように基板50に仮接合される。本実施形態では、受光素子2の第1面2a上に設けられた絶縁層23が、基板50に仮接合される。 First, as shown in FIG. 2, the light receiving element 2 and the end portion 6a of the metal pillar 6 are connected to a temporary bonding surface 50a (for example, a surface coated with adhesive for temporary bonding) of a substrate 50 that is a temporary bonding member. are temporarily joined (first step). That is, the light receiving element 2 and the metal pillar 6 are temporarily bonded to the substrate 50 in such a manner that they can be removed later. The light receiving element 2 is temporarily bonded to the substrate 50 such that the first surface 2a faces the substrate 50. In this embodiment, the insulating layer 23 provided on the first surface 2a of the light receiving element 2 is temporarily bonded to the substrate 50.
 基板50は、例えばシリコンウェハ、ガラスウェハ、SUSキャリア等である。基板上には、1つの光半導体パッケージ1Aに対応する単位領域が、格子状(二次元状)に複数並んで形成される。図2~図7は、各製造工程における1つの単位領域の状態を表している。 The substrate 50 is, for example, a silicon wafer, a glass wafer, a SUS carrier, or the like. On the substrate, a plurality of unit regions corresponding to one optical semiconductor package 1A are formed in a grid (two-dimensional shape). 2 to 7 represent the state of one unit area in each manufacturing process.
 図3を参照して、基板50に金属ピラー6を仮接合する方法の一例について説明する。この例では、複数(単位領域数×各単位領域に含まれる金属ピラー数)の金属ピラー6の端部6aを露出させた状態で各金属ピラー6を位置決めする支持部材100が用いられる。具体的には、第1工程において基板50に金属ピラー6を仮接合する工程は、支持部材100によって、金属ピラー6の端部6aを露出させた状態で金属ピラー6を位置決めすると共に支持する工程と、支持部材100に支持されている金属ピラー6の端部6aに対して、基板50の仮接合面50aを接触させることにより、基板50に金属ピラー6の端部6aを仮接合する工程と、を含む。上記構成によれば、支持部材100によって位置決め及び支持された状態の金属ピラー6に基板50の仮接合面50aを接触させる比較的簡易な操作によって、基板50に金属ピラー6を仮接合することができる。 An example of a method for temporarily bonding the metal pillar 6 to the substrate 50 will be described with reference to FIG. 3. In this example, a support member 100 is used that positions each metal pillar 6 with the ends 6a of a plurality (number of unit areas x number of metal pillars included in each unit area) of the metal pillars 6 exposed. Specifically, the step of temporarily joining the metal pillar 6 to the substrate 50 in the first step is a step of positioning and supporting the metal pillar 6 with the end portion 6a of the metal pillar 6 exposed using the support member 100. and a step of temporarily joining the end portion 6a of the metal pillar 6 to the substrate 50 by bringing the temporary joining surface 50a of the substrate 50 into contact with the end portion 6a of the metal pillar 6 supported by the support member 100. ,including. According to the above configuration, the metal pillar 6 can be temporarily bonded to the substrate 50 by a relatively simple operation of bringing the temporary bonding surface 50a of the substrate 50 into contact with the metal pillar 6 positioned and supported by the support member 100. can.
 まず、図3の(A)に示されるように、支持部材100によって、金属ピラー6の端部6aを露出させた状態で、金属ピラー6が位置決めされると共に支持される。この例では、支持部材100は、金属ピラー6の幅よりも大きい幅を有する貫通孔101aが形成された板状部材101と、金属ピラー6の端部6bが載置及び支持される支持基板102と、を有している。なお、貫通孔101aの大きさは、金属ピラー6を挿入可能であり、且つ、金属ピラー6の横方向の位置ずれを許容誤差範囲内に収めることが可能な大きさに調整されている。各金属ピラー6は、板状部材101の貫通孔101aに挿通されて位置決めされると共に、支持基板102に支持される。金属ピラー6が支持部材100に支持された状態において、端部6aは、板状部材101に対して支持基板102側とは反対側に突出している。なお、板状部材101と支持基板102とは、図3に示されるように別体として形成されてもよいし、一体的に形成されてもよい。また、板状部材101と支持基板102との間には、図3に示されるようにスペース(隙間)が設けられてもよいし、このようなスペースが設けられなくてもよい。 First, as shown in FIG. 3A, the metal pillar 6 is positioned and supported by the support member 100 with the end 6a of the metal pillar 6 exposed. In this example, the support member 100 includes a plate-like member 101 in which a through hole 101a having a width larger than the width of the metal pillar 6 is formed, and a support substrate 102 on which the end portion 6b of the metal pillar 6 is placed and supported. It has . Note that the size of the through hole 101a is adjusted to a size that allows the metal pillar 6 to be inserted therein and allows the lateral positional deviation of the metal pillar 6 to be kept within an allowable error range. Each metal pillar 6 is inserted into the through hole 101a of the plate member 101 and positioned, and is supported by the support substrate 102. When the metal pillar 6 is supported by the support member 100, the end portion 6a protrudes from the plate member 101 on the side opposite to the support substrate 102 side. Note that the plate-like member 101 and the support substrate 102 may be formed separately as shown in FIG. 3, or may be formed integrally. Further, a space (gap) may be provided between the plate member 101 and the support substrate 102 as shown in FIG. 3, or such a space may not be provided.
 続いて、図3の(B)に示されるように、支持部材100に支持されている金属ピラー6の端部6aに対して、基板50の仮接合面50aが接触させられる。これにより、図3の(C)に示されるように、基板50の仮接合面50aに金属ピラー6の端部6aが仮接合される。 Subsequently, as shown in FIG. 3B, the temporary bonding surface 50a of the substrate 50 is brought into contact with the end 6a of the metal pillar 6 supported by the support member 100. Thereby, as shown in FIG. 3C, the end portion 6a of the metal pillar 6 is temporarily bonded to the temporary bonding surface 50a of the substrate 50.
 上記構成によれば、金属ピラー6の端部6aが板状部材101よりも突出した状態で、金属ピラー6が支持部材100によって支持されるため、基板50の仮接合面50aを端部6aに接触させる際に、基板50の仮接合面50aが板状部材101に接触することを防止することができる。すなわち、基板50の仮接合面50aが板状部材101に貼り付いてしまうことを的確に防止することができる。 According to the above configuration, since the metal pillar 6 is supported by the support member 100 with the end 6a of the metal pillar 6 protruding beyond the plate member 101, the temporary bonding surface 50a of the substrate 50 is attached to the end 6a. When making contact, the temporary bonding surface 50a of the substrate 50 can be prevented from coming into contact with the plate member 101. That is, it is possible to accurately prevent the temporary bonding surface 50a of the substrate 50 from sticking to the plate member 101.
 ここで、図4に示されるように、金属ピラー6の代わりにフランジ部62を有する金属ピラー6Aが用いられてもよい。金属ピラー6Aは、端部6bを含む軸部61と、端部6aを含み且つ軸部61よりも幅広に形成されたフランジ部62と、を有する。フランジ部62は、端部6aにおいて、軸部61の軸方向に直交する方向に外側に延在する部分である。軸方向から見たフランジ部62の形状は、例えば円形状である。板状部材101の貫通孔101aは、軸部61の幅よりも大きくフランジ部62の幅よりも小さい幅を有するように設定されている。金属ピラー6Aは、軸部61が貫通孔101aに挿通され、フランジ部62の端部6b側の内面62aが板状部材101の貫通孔101aの周縁部に当接することによって、板状部材101に支持される。この状態で、金属ピラー6Aの端部6aに対して、基板50の仮接合面50aを接触させることにより、基板50に金属ピラー6Aの端部6aを仮接合することができる。上記構成によれば、フランジ部62を板状部材101の貫通孔101aの周縁部に引っかけて支持することが可能となるため、端部6bを支持するための支持基板102が不要となる。その結果、支持部材100を簡素化することができる。また、フランジ部62を設けることにより、基板50上に立設される金属ピラー6Aの姿勢(垂直性)をより安定化させることができる。 Here, as shown in FIG. 4, a metal pillar 6A having a flange portion 62 may be used instead of the metal pillar 6. The metal pillar 6A has a shaft portion 61 including an end portion 6b, and a flange portion 62 including the end portion 6a and formed wider than the shaft portion 61. The flange portion 62 is a portion extending outward in a direction perpendicular to the axial direction of the shaft portion 61 at the end portion 6a. The shape of the flange portion 62 when viewed from the axial direction is, for example, circular. The through hole 101a of the plate member 101 is set to have a width larger than the width of the shaft portion 61 and smaller than the width of the flange portion 62. In the metal pillar 6A, the shaft portion 61 is inserted into the through hole 101a, and the inner surface 62a of the flange portion 62 on the end 6b side abuts the peripheral edge of the through hole 101a of the plate member 101, so that the metal pillar 6A is inserted into the plate member 101. Supported. In this state, the end 6a of the metal pillar 6A can be temporarily joined to the substrate 50 by bringing the temporary joining surface 50a of the substrate 50 into contact with the end 6a of the metal pillar 6A. According to the above configuration, the flange portion 62 can be supported by being hooked onto the peripheral edge of the through hole 101a of the plate member 101, so the support substrate 102 for supporting the end portion 6b is not required. As a result, the support member 100 can be simplified. Further, by providing the flange portion 62, the posture (verticality) of the metal pillar 6A erected on the substrate 50 can be more stabilized.
 ただし、基板50に金属ピラー6を形成する方法は、上記に限られない。例えば、金属ピラー6を移載可能に構成された移載装置によって金属ピラー6を基板50上の指定位置に移載することにより、基板50上に金属ピラー6を形成してもよい。上記方法によれば、移載装置を制御することにより、基板50上の任意の位置に精度良く金属ピラー6を配置することができる。また、基板50上に金属パターン(金属ピラー6)を形成するための半導体前工程(シード層形成、フォトリソグラフィ、電解Cuめっき、レジスト除去、シード層エッチング等)を実施することにより、基板50上に金属ピラー6を形成してもよい。上記方法によっても、金属ピラー6のパターン(位置及び形状)を高精度に制御することができる。或いは、基板50上に金属パッドを形成し、当該金属パッド上に垂直に延びるワイヤが形成されるようにワイヤボンディングを実施し、金属パッド上に接合されたワイヤを適当な長さで切断することにより、金属ピラー6(すなわち、金属パッドとワイヤとを合わせた構造)を形成してもよい。上記方法によれば、ボンディング条件(パラメータ)を調整することにより、任意の径及び長さのワイヤ(金属ピラー6)を形成することができる。 However, the method for forming the metal pillars 6 on the substrate 50 is not limited to the above method. For example, the metal pillar 6 may be formed on the substrate 50 by transferring the metal pillar 6 to a designated position on the substrate 50 using a transfer device configured to be able to transfer the metal pillar 6. According to the above method, by controlling the transfer device, the metal pillars 6 can be placed at any position on the substrate 50 with high precision. In addition, by performing semiconductor pre-processes (seed layer formation, photolithography, electrolytic Cu plating, resist removal, seed layer etching, etc.) for forming a metal pattern (metal pillar 6) on the substrate 50, A metal pillar 6 may be formed on the surface. The above method also allows the pattern (position and shape) of the metal pillars 6 to be controlled with high precision. Alternatively, a metal pad is formed on the substrate 50, wire bonding is performed so that a wire extending vertically is formed on the metal pad, and the wire bonded on the metal pad is cut to an appropriate length. A metal pillar 6 (that is, a structure combining a metal pad and a wire) may be formed by this method. According to the above method, a wire (metal pillar 6) having an arbitrary diameter and length can be formed by adjusting the bonding conditions (parameters).
 続いて、図5の(A)に示されるように、各単位領域に配置された受光素子2及び金属ピラー6を覆うモールド樹脂3が、基板50上に形成される(第2工程)。1つの単位領域に着目すると、モールド樹脂3は、受光素子2の第2面2bと側面とを覆うと共に、各金属ピラー6の端部6aを除く部分(端部6b及び側面)の全体を覆うように形成される。 Subsequently, as shown in FIG. 5A, a mold resin 3 is formed on the substrate 50 to cover the light receiving elements 2 and metal pillars 6 arranged in each unit area (second step). Focusing on one unit area, the mold resin 3 covers the second surface 2b and side surfaces of the light receiving element 2, and also covers the entire portion of each metal pillar 6 except for the end portion 6a (end portion 6b and side surface). It is formed like this.
 続いて、図5の(B)に示されるように、受光素子2の第2面2bに対向する側(すなわち、端面3b側)からモールド樹脂3を研磨又は研削することにより、受光素子2の第2面2bと金属ピラー6の端部6bとが露出させられる(第3工程)。「研磨又は研削」とは、研磨及び研削のいずれか一方のみを実施する場合を含むと共に、研磨及び研削の両方を実施する場合を含む。このとき、各単位領域において、モールド樹脂3の端面3bと共に、受光素子2の第2面2bも併せて研磨又は研削されてもよい。同様に、金属ピラー6の端部6bも研磨又は研削されてもよい。つまり、モールド樹脂3の端面3bの研磨又は研削によって各単位領域の受光素子2の第2面2b又は金属ピラー6の端部6bが露出した後、さらにモールド樹脂3の端面3bと第2面2b又は端部6bとを一括で研磨又は研削する処理が継続されてもよい。その結果、図5の(B)に示されるように、受光素子2が薄型化されると共に、受光素子2の第2面2b及び金属ピラー6の端部6bが外部に露出した状態となる。以上の処理により、受光素子2の第2面2b、金属ピラー6の端部6b、及びモールド樹脂3の端面3bは、略面一となる。 Subsequently, as shown in FIG. 5B, the mold resin 3 is polished or ground from the side facing the second surface 2b of the light-receiving element 2 (i.e., the end surface 3b side), so that the light-receiving element 2 is polished. The second surface 2b and the end portion 6b of the metal pillar 6 are exposed (third step). "Polishing or grinding" includes cases in which only one of polishing and grinding is performed, as well as cases in which both polishing and grinding are performed. At this time, in each unit area, the end surface 3b of the molded resin 3 and the second surface 2b of the light-receiving element 2 may also be polished or ground. Similarly, the end portion 6b of the metal pillar 6 may also be polished or ground. That is, after the second surface 2b of the light receiving element 2 or the end 6b of the metal pillar 6 in each unit area is exposed by polishing or grinding the end surface 3b of the molded resin 3, the end surface 3b and the second surface 2b of the molded resin 3 are further exposed. Alternatively, the process of polishing or grinding the end portion 6b at once may be continued. As a result, as shown in FIG. 5B, the light receiving element 2 is made thinner, and the second surface 2b of the light receiving element 2 and the end portion 6b of the metal pillar 6 are exposed to the outside. Through the above processing, the second surface 2b of the light receiving element 2, the end portion 6b of the metal pillar 6, and the end surface 3b of the molded resin 3 become substantially flush with each other.
 続いて、図6の(A)に示されるように、受光素子2の第2面2b上、及び第2面2bと連続するモールド樹脂3の端面3b上に、配線層4が形成される。本実施形態では、受光素子2の第2面2b、金属ピラー6の端部6b、及びモールド樹脂3の端面3b上に、絶縁層41及び金属配線42が形成される。 Subsequently, as shown in FIG. 6A, the wiring layer 4 is formed on the second surface 2b of the light receiving element 2 and on the end surface 3b of the molded resin 3 that is continuous with the second surface 2b. In this embodiment, an insulating layer 41 and metal wiring 42 are formed on the second surface 2b of the light receiving element 2, the end 6b of the metal pillar 6, and the end surface 3b of the molded resin 3.
 例えば、図5の(B)に示される状態から、絶縁層41のパターニング及び金属配線42のパターン形成を半導体プロセス(シード層形成、フォトリソグラフィ、電解めっき等)を用いて行うことにより、図6の(A)に示される構造が得られる。配線層4は、金属配線42における端部6bに接続される部分の配線幅が端部6bの幅よりも大きくなるように形成される。より具体的には、絶縁層41の開口41aの幅は、金属ピラー6の端部6bの幅よりも大きく形成される。これにより、金属配線42における端部6bに接続される部分の配線幅w11(図1参照)が金属ピラー6の端部6bの幅w12(図1参照)よりも大きく形成される。上記構成によれば、第2工程(モールド樹脂3を形成する工程)において生じ得る金属ピラー6の位置ずれを吸収することができる。すなわち、金属配線42の配線幅を大きくすることにより、第2工程におけるモールド樹脂3の流入によって金属ピラー6の位置が多少ずれたとしても、金属配線42と金属ピラー6(端部6b)とをより確実に接触させることができる。 For example, by patterning the insulating layer 41 and forming the pattern of the metal wiring 42 from the state shown in FIG. 5B using a semiconductor process (seed layer formation, photolithography, electrolytic plating, etc.), The structure shown in (A) is obtained. The wiring layer 4 is formed so that the wiring width of the portion of the metal wiring 42 connected to the end portion 6b is larger than the width of the end portion 6b. More specifically, the width of the opening 41a of the insulating layer 41 is formed to be larger than the width of the end 6b of the metal pillar 6. As a result, the wiring width w11 (see FIG. 1) of the portion of the metal wiring 42 connected to the end 6b is formed larger than the width w12 (see FIG. 1) of the end 6b of the metal pillar 6. According to the above configuration, it is possible to absorb the positional shift of the metal pillar 6 that may occur in the second step (the step of forming the molded resin 3). That is, by increasing the wiring width of the metal wiring 42, even if the position of the metal pillar 6 is slightly shifted due to the inflow of the molded resin 3 in the second step, the metal wiring 42 and the metal pillar 6 (end portion 6b) can be easily connected. Contact can be made more reliably.
 なお、上記とは逆に、金属配線42における端部6bに接続される部分の配線幅が金属ピラー6の端部6bの幅よりも小さくなるように、配線層4が形成されてもよい(後述する第2実施形態参照)。この場合、金属ピラー6の大きさ(幅)の影響を受けずに、金属配線42を形成することができる。例えば、金属ピラー6(端部6b)の幅が比較的大きい場合に金属配線42の幅を金属ピラー6の幅よりもさらに大きくすると、金属配線42が配線層4に設けられる他の配線と干渉し易くなるという問題が生じ得る。上記構成によれば、このような問題の発生を回避することができる。 Note that, contrary to the above, the wiring layer 4 may be formed such that the wiring width of the portion of the metal wiring 42 connected to the end 6b is smaller than the width of the end 6b of the metal pillar 6 ( (See second embodiment described later). In this case, the metal wiring 42 can be formed without being affected by the size (width) of the metal pillar 6. For example, if the width of the metal wiring 42 is made larger than the width of the metal pillar 6 when the width of the metal pillar 6 (end portion 6b) is relatively large, the metal wiring 42 will interfere with other wiring provided in the wiring layer 4. The problem may arise that it becomes easier to do so. According to the above configuration, occurrence of such a problem can be avoided.
 続いて、図6の(B)に示されるように、受光素子2、金属ピラー6、及びモールド樹脂3から基板50が分離される(第5工程)。また、加工面(加工対象の面)が、受光素子2の第2面2b側の面から、受光素子2の第1面2a側の面(すなわち、基板50が分離された後に露出する面)に変更される。 Subsequently, as shown in FIG. 6(B), the substrate 50 is separated from the light receiving element 2, metal pillar 6, and mold resin 3 (fifth step). Further, the processing surface (the surface to be processed) changes from the surface on the second surface 2b side of the light receiving element 2 to the surface on the first surface 2a side of the light receiving element 2 (that is, the surface exposed after the substrate 50 is separated). will be changed to
 続いて、上記のように基板50が受光素子2、金属ピラー6、及びモールド樹脂3から分離された後(すなわち、第5工程よりも後)に、図7の(A)に示されるように、受光素子2及びモールド樹脂3に対して配線層4が位置する側とは反対側に、配線層5が形成される(第6工程)。本実施形態では、絶縁層23のうち受光部21と重ならない部分、金属ピラー6の端部6a、及びモールド樹脂3の端面3a上に、絶縁層51及び金属配線52が形成される。また、金属配線42の外側端部に対する無電解めっきが行われることにより、上記外側端部の表面にめっき部43が形成される。 Subsequently, after the substrate 50 is separated from the light receiving element 2, metal pillar 6, and mold resin 3 as described above (that is, after the fifth step), as shown in FIG. 7(A), , the wiring layer 5 is formed on the side opposite to the side where the wiring layer 4 is located with respect to the light receiving element 2 and the mold resin 3 (sixth step). In this embodiment, the insulating layer 51 and the metal wiring 52 are formed on the portion of the insulating layer 23 that does not overlap with the light receiving section 21, the end portion 6a of the metal pillar 6, and the end surface 3a of the molded resin 3. Further, by performing electroless plating on the outer end portion of the metal wiring 42, a plated portion 43 is formed on the surface of the outer end portion.
 例えば、図6の(B)に示される状態から、絶縁層51のパターニング及び金属配線52のパターン形成を半導体プロセス(シード層形成、フォトリソグラフィ、電解めっき等)を用いて行うことにより、図7の(A)に示される構造が得られる。配線層5は、金属配線52における端部6aに接続される部分の配線幅が端部6aの幅よりも大きくなるように形成される。より具体的には、絶縁層51の開口51aの幅は、金属ピラー6の端部6aの幅よりも大きく形成される。これにより、金属配線52における端部6aに接続される部分の配線幅w21(図1参照)が金属ピラー6の端部6aの幅w22(図1参照)よりも大きく形成される。上記構成によれば、第2工程(モールド樹脂3を形成する工程)において生じ得る金属ピラー6の位置ずれを吸収することができる。すなわち、金属配線52の配線幅を大きくすることにより、第2工程におけるモールド樹脂3の流入によって金属ピラー6の位置が多少ずれたとしても、金属配線52と金属ピラー6(端部6a)とをより確実に接触させることができる。 For example, by patterning the insulating layer 51 and forming the pattern of the metal wiring 52 from the state shown in FIG. 6(B) using a semiconductor process (seed layer formation, photolithography, electrolytic plating, etc.), The structure shown in (A) is obtained. The wiring layer 5 is formed so that the wiring width of the portion of the metal wiring 52 connected to the end portion 6a is larger than the width of the end portion 6a. More specifically, the width of the opening 51a of the insulating layer 51 is larger than the width of the end 6a of the metal pillar 6. As a result, the wiring width w21 (see FIG. 1) of the portion of the metal wiring 52 connected to the end 6a is formed larger than the width w22 (see FIG. 1) of the end 6a of the metal pillar 6. According to the above configuration, it is possible to absorb the positional shift of the metal pillar 6 that may occur in the second step (the step of forming the molded resin 3). That is, by increasing the wiring width of the metal wiring 52, even if the position of the metal pillar 6 is slightly shifted due to the inflow of the molded resin 3 in the second step, the metal wiring 52 and the metal pillar 6 (end portion 6a) can be easily connected. Contact can be made more reliably.
 なお、上記とは逆に、金属配線52における端部6aに接続される部分の配線幅が金属ピラー6の端部6aの幅よりも小さくなるように、配線層5が形成されてもよい(後述する第2実施形態参照)。この場合、金属ピラー6の大きさ(幅)の影響を受けずに、金属配線52を形成することができる。例えば、金属ピラー6(端部6a)の幅が比較的大きい場合に金属配線52の幅を金属ピラー6の幅よりもさらに大きくすると、金属配線52が配線層5に設けられる他の配線と干渉し易くなるという問題が生じ得る。上記構成によれば、このような問題の発生を回避することができる。 Note that, contrary to the above, the wiring layer 5 may be formed such that the wiring width of the portion of the metal wiring 52 connected to the end 6a is smaller than the width of the end 6a of the metal pillar 6 ( (See second embodiment described later). In this case, the metal wiring 52 can be formed without being affected by the size (width) of the metal pillar 6. For example, if the width of the metal wiring 52 is made larger than the width of the metal pillar 6 when the width of the metal pillar 6 (end portion 6a) is relatively large, the metal wiring 52 will interfere with other wiring provided in the wiring layer 5. The problem may arise that it becomes easier to do so. According to the above configuration, occurrence of such a problem can be avoided.
 続いて、図7の(B)に示されるように、単位領域間の境界線Lに沿ってダイシングが行われる。これにより、個片化された複数の光半導体パッケージ1Aが得られる。 Subsequently, as shown in FIG. 7(B), dicing is performed along the boundary line L between the unit areas. Thereby, a plurality of individualized optical semiconductor packages 1A are obtained.
(作用効果)
 上記の光半導体パッケージ1Aの製造方法では、第1工程において、基板50と受光素子2との間に隙間が形成されないように、受光素子2が基板50に仮接合される。これにより、第2工程において、受光素子2と基板50との間にモールド樹脂3が流れ込むこと、すなわち、受光部21に対向する位置にモールド樹脂3が形成されることを防止することができる。その結果、受光部21がモールド樹脂3に覆われることに起因する受光感度の低下を回避することができる。また、受光素子2及び金属ピラー6が基板50に仮接合されることによって各部材が安定的に固定された状態で、第2工程を安定的且つ精度良く実施することが可能となる。より具体的には、モールド樹脂3の硬化時におけるパッケージの反りの発生を抑制できる。以上により、上記製造方法によれば、光半導体パッケージ1Aを信頼性高く製造することができる。また、受光素子2は、第1面2aに受光面を有している。上記構成によれば、表面入射型の受光素子2の表面が第1面2aである光半導体パッケージ1Aを信頼性高く製造することができる。
(effect)
In the method for manufacturing the optical semiconductor package 1A described above, in the first step, the light receiving element 2 is temporarily bonded to the substrate 50 so that no gap is formed between the substrate 50 and the light receiving element 2. Thereby, in the second step, it is possible to prevent the mold resin 3 from flowing between the light receiving element 2 and the substrate 50, that is, from forming the mold resin 3 at a position facing the light receiving section 21. As a result, it is possible to avoid a decrease in light receiving sensitivity due to the light receiving section 21 being covered with the mold resin 3. Further, by temporarily bonding the light receiving element 2 and the metal pillar 6 to the substrate 50, it becomes possible to carry out the second step stably and accurately with each member being stably fixed. More specifically, it is possible to suppress the occurrence of warping of the package when the mold resin 3 is cured. As described above, according to the above manufacturing method, the optical semiconductor package 1A can be manufactured with high reliability. Further, the light receiving element 2 has a light receiving surface on the first surface 2a. According to the above configuration, the optical semiconductor package 1A in which the surface of the front-illuminated light receiving element 2 is the first surface 2a can be manufactured with high reliability.
 また、上記の光半導体パッケージ1Aの製造方法によれば、以下の効果も奏される。すなわち、特許文献1に開示された手法のように、バンプ接続を用いてガラス基板から受光素子を離間させて配置する場合には、バンプ量のばらつきに起因してガラス基板に対して受光素子が傾いてしまい、光軸ずれが生じる結果、ユニフォミティが低下するおそれがある。一方、上記の光半導体パッケージ1Aの製造方法によれば、基板50に対して受光素子2(絶縁層23)を密着させるため、受光素子2が基板50に対して傾いて配置されることを防止でき、上記のような問題の発生を回避できる。 Furthermore, according to the method for manufacturing the optical semiconductor package 1A described above, the following effects are also achieved. In other words, when the light receiving element is placed apart from the glass substrate using bump connection as in the method disclosed in Patent Document 1, the light receiving element is placed with respect to the glass substrate due to variations in the amount of bumps. As a result of the tilting, optical axis misalignment may occur, resulting in a decrease in uniformity. On the other hand, according to the method for manufacturing the optical semiconductor package 1A described above, since the light receiving element 2 (insulating layer 23) is brought into close contact with the substrate 50, the light receiving element 2 is prevented from being arranged at an angle with respect to the substrate 50. This can avoid the problems mentioned above.
 また、特許文献1に開示された手法では、ガラス基板と受光素子との間にアンダーフィルを封入するためにある程度受光素子をガラス基板から離して配置する必要がある。この場合、受光素子がパッケージの奥に位置することにより、ガラス基板に形成された配線層が受光部の視野を遮る構造になってしまい、受光素子のアクティブエリアが狭くなってしまう。上記の光半導体パッケージ1Aの製造方法によれば、このような問題の発生も回避できる。 Furthermore, in the method disclosed in Patent Document 1, in order to seal an underfill between the glass substrate and the light receiving element, it is necessary to arrange the light receiving element at a certain distance from the glass substrate. In this case, since the light receiving element is located at the back of the package, the wiring layer formed on the glass substrate has a structure that blocks the field of view of the light receiving part, and the active area of the light receiving element becomes narrow. According to the method for manufacturing the optical semiconductor package 1A described above, the occurrence of such problems can also be avoided.
 また、特許文献1に開示された手法では、ガラス基板と受光素子との間に封入したアンダーフィル内にボイドが生じたり、当該ボイドを無くすための特殊な処理を行ったりする必要が生じる場合があるが、上記の光半導体パッケージ1Aの製造方法によれば、受光素子2(受光部21)に対向する位置にアンダーフィルが形成されないため、上記のような問題の発生も回避できる。 Furthermore, with the method disclosed in Patent Document 1, voids may occur in the underfill sealed between the glass substrate and the light receiving element, and special processing may be required to eliminate the voids. However, according to the method for manufacturing the optical semiconductor package 1A described above, since no underfill is formed at a position facing the light receiving element 2 (light receiving section 21), the above problem can also be avoided.
(変形例)
 絶縁層23上における受光部21と対向する位置には、ガラス、バンドパスフィルタ、レンズ等の光学部品が取り付けられてもよい。このような光学部品を取り付ける工程は、例えば、配線層5を形成する工程(第6工程)の後に実施されてもよい。或いは、上述した光学部品は、本実施形態の製造工程が実行される前に予め受光素子2に取り付けられていてもよい。また、基板50を受光素子2等から分離(剥離)する工程(第5工程)は、第2工程が完了してから第6工程が開始されるまでの間の任意のタイミングで実施されればよい。例えば、基板50は、第2工程の完了後に直ちに除去されてもよい。或いは、第5工程は、少なくとも第3工程よりも後に実施されてもよい。例えば、第4工程は、第3工程の後に実施されてもよく、第5工程は、第4工程の後に実施されてもよい。上記構成によれば、基板50を第3工程(或いは、第3工程及び第4工程)においても取り付けた状態にすることによって、各部材の支持安定性を高めた状態で第3工程(或いは、第3工程及び第4工程)を信頼性高く実施できるという利点が得られる。特に、本実施形態では、受光部21が絶縁層23を介して外部に露出しているため、基板50を取り付けた状態にすることにより、各工程において受光部21を外部からの衝撃等から適切に保護することができる。また、第6工程を実施する際に、各部材の支持安定性を高めるために、仮接合部材としての基板(例えば基板50)を配線層4上に取り付けてもよい。
(Modified example)
Optical components such as glass, a bandpass filter, and a lens may be attached to a position on the insulating layer 23 facing the light receiving section 21 . The step of attaching such an optical component may be performed, for example, after the step of forming the wiring layer 5 (sixth step). Alternatively, the optical components described above may be attached to the light receiving element 2 in advance before the manufacturing process of this embodiment is performed. Further, the step of separating (peeling) the substrate 50 from the light receiving element 2, etc. (fifth step) may be performed at any timing between the completion of the second step and the start of the sixth step. good. For example, substrate 50 may be removed immediately after the second step is completed. Alternatively, the fifth step may be performed at least after the third step. For example, the fourth step may be performed after the third step, and the fifth step may be performed after the fourth step. According to the above configuration, by keeping the substrate 50 attached also in the third step (or the third step and the fourth step), the third step (or The advantage is that the third step and the fourth step) can be carried out with high reliability. In particular, in this embodiment, since the light receiving section 21 is exposed to the outside through the insulating layer 23, by attaching the substrate 50, the light receiving section 21 can be properly protected from external impact etc. in each process. can be protected. Further, when carrying out the sixth step, a substrate (for example, the substrate 50) as a temporary bonding member may be attached on the wiring layer 4 in order to improve the support stability of each member.
[第2実施形態]
(光半導体パッケージの構造)
 図8に示されるように、第2実施形態の光半導体パッケージ1Bは、モールド樹脂3の代わりに透明なモールド樹脂3Bを備える点において、光半導体パッケージ1Aと相違している。また、光半導体パッケージ1Bは、金属ピラー6(金属部材)の端部6aが絶縁層23の上面(第1面2a側とは反対側の面)よりも高い位置にあり、金属配線52における端部6aと接続される側とは反対側の端部52bと電極端子22とを接続する金属ピラー7を更に備える点においても、光半導体パッケージ1Aと相違している。以下、光半導体パッケージ1Bの構成のうち光半導体パッケージ1Aと異なる部分について説明し、光半導体パッケージ1Bの構成のうち光半導体パッケージ1Aと同様の部分についての説明を省略する。
[Second embodiment]
(Structure of optical semiconductor package)
As shown in FIG. 8, the optical semiconductor package 1B of the second embodiment is different from the optical semiconductor package 1A in that a transparent mold resin 3B is provided instead of the mold resin 3. Further, in the optical semiconductor package 1B, the end portion 6a of the metal pillar 6 (metal member) is located at a higher position than the upper surface of the insulating layer 23 (the surface opposite to the first surface 2a side), and the end portion 6a of the metal pillar 6 (metal member) It is also different from the optical semiconductor package 1A in that it further includes a metal pillar 7 that connects the electrode terminal 22 to the end 52b on the side opposite to the side connected to the portion 6a. Hereinafter, the parts of the optical semiconductor package 1B that are different from the optical semiconductor package 1A will be described, and the description of the parts of the optical semiconductor package 1B that are similar to the optical semiconductor package 1A will be omitted.
 モールド樹脂3Bは、受光部21の検出対象となる光(波長)に対する透明性を有する材料によって形成されている。モールド樹脂3Bは、例えば、透明エポキシ樹脂等によって形成され得る。モールド樹脂3Bは、受光素子2の側面だけでなく、受光素子2の第1面2aに対向する部分(すなわち、絶縁層23上の領域)にも設けられており、金属ピラー6及び金属ピラー7の側面全体を覆っている。モールド樹脂3Bは、配線層5の開口部51bの内側にも設けられている。すなわち、モールド樹脂3Bの端面3b(第2面2bと面一に形成された端面)とは反対側の端面3aは、配線層5(絶縁層51)の外面と面一に形成されている。 The mold resin 3B is made of a material that is transparent to the light (wavelength) to be detected by the light receiving section 21. The mold resin 3B may be made of, for example, transparent epoxy resin. The mold resin 3B is provided not only on the side surface of the light-receiving element 2 but also on the portion facing the first surface 2a of the light-receiving element 2 (that is, the area on the insulating layer 23), and is provided on the metal pillar 6 and the metal pillar 7. covers the entire side of the The mold resin 3B is also provided inside the opening 51b of the wiring layer 5. That is, the end surface 3a of the molded resin 3B opposite to the end surface 3b (the end surface formed flush with the second surface 2b) is formed flush with the outer surface of the wiring layer 5 (insulating layer 51).
 光半導体パッケージ1Bにおいては、配線層5(第1配線層)は、Z軸方向において、絶縁層23と離間している。このため、金属配線52(第1金属配線)と電極端子22とを電気的に接続するための金属ピラー7が設けられている。光半導体パッケージ1Bにおいては、金属配線52は、X軸方向において外側(受光素子2と重ならない部分)に配置される端部52a(第1端部)と、X軸方向において内側(受光素子2と重なる部分)に配置される端部52b(第2端部)と、を有している。端部52aは、金属ピラー6の端部6aに接続されている。端部52bは、金属ピラー7の端部7a(電極端子22側とは反対側の端部)に接続されている。なお、光半導体パッケージ1Bは、必ずしも柱状の金属ピラー7を備える必要はない。例えば、端部52bと電極端子22とは、導電性バンプを介して接続されてもよい。すなわち、端部52bと電極端子22とは、何らかの導電性部材によって電気的に接続されていればよい。また、当該導電性部材が端部52bと電極端子22との間に配置されることによって、後述する第5工程においてモールド樹脂3Bを内部空間S(図9の(B)参照)に導入するための隙間が、絶縁層23と絶縁層51との間に形成されればよい。 In the optical semiconductor package 1B, the wiring layer 5 (first wiring layer) is separated from the insulating layer 23 in the Z-axis direction. For this reason, a metal pillar 7 is provided for electrically connecting the metal wiring 52 (first metal wiring) and the electrode terminal 22. In the optical semiconductor package 1B, the metal wiring 52 has an end portion 52a (first end portion) located outside in the X-axis direction (a portion that does not overlap with the light-receiving element 2), and an end portion 52a (first end portion) located inside in the X-axis direction (a portion that does not overlap with the light-receiving element 2). and an end portion 52b (a second end portion) disposed at a portion overlapping with the first end portion. The end 52a is connected to the end 6a of the metal pillar 6. The end 52b is connected to the end 7a of the metal pillar 7 (the end on the opposite side to the electrode terminal 22 side). Note that the optical semiconductor package 1B does not necessarily need to include the columnar metal pillar 7. For example, the end portion 52b and the electrode terminal 22 may be connected via a conductive bump. That is, the end portion 52b and the electrode terminal 22 may be electrically connected by some kind of conductive member. Furthermore, by disposing the conductive member between the end portion 52b and the electrode terminal 22, the molded resin 3B can be introduced into the internal space S (see (B) in FIG. 9) in the fifth step described later. It is sufficient that a gap of 1 is formed between the insulating layer 23 and the insulating layer 51.
(光半導体パッケージの製造方法)
 図9~図11を参照して、光半導体パッケージ1Bの製造工程の一例について説明する。本実施形態では、光半導体パッケージ1Bは、CoW方式又はCoP方式によって製造される。図9~図11は、各製造工程における1つの単位領域の状態を示している。以下では、1つの単位領域のみに着目して説明を行う。
(Method for manufacturing optical semiconductor package)
An example of the manufacturing process of the optical semiconductor package 1B will be described with reference to FIGS. 9 to 11. In this embodiment, the optical semiconductor package 1B is manufactured by a CoW method or a CoP method. 9 to 11 show the state of one unit area in each manufacturing process. The following description focuses on only one unit area.
 まず、図9の(A)に示されるように、仮接合部材である基板50上に、基板50を露出させる開口部51bが設けられた配線層5が形成される(第1工程)。配線層5は、絶縁層51と金属配線52とを有している。開口部51bは、絶縁層51に設けられている。例えば、絶縁層51のパターニング及び金属配線52のパターン形成を半導体プロセス(シード層形成、フォトリソグラフィ、電解めっき等)を用いて行うことにより、図9の(A)に示される配線層5が得られる。なお、本実施形態では、絶縁層51の開口51aの幅は、金属ピラー6の端部6aの幅よりも小さく形成されており、その結果、金属配線52における端部6aに接続される部分の配線幅が金属ピラー6の端部6aの幅よりも小さく形成されている。ただし、第1実施形態と同様に、金属配線52における端部6aに接続される部分の配線幅は、金属ピラー6の端部6aの幅よりも大きく形成されてもよい。 First, as shown in FIG. 9A, the wiring layer 5 provided with an opening 51b that exposes the substrate 50 is formed on the substrate 50, which is a temporary bonding member (first step). The wiring layer 5 includes an insulating layer 51 and metal wiring 52. The opening 51b is provided in the insulating layer 51. For example, by patterning the insulating layer 51 and forming the pattern of the metal wiring 52 using a semiconductor process (seed layer formation, photolithography, electrolytic plating, etc.), the wiring layer 5 shown in FIG. It will be done. In this embodiment, the width of the opening 51a of the insulating layer 51 is smaller than the width of the end 6a of the metal pillar 6, and as a result, the width of the opening 51a of the insulating layer 51 is smaller than the width of the end 6a of the metal wiring 52. The wiring width is formed smaller than the width of the end portion 6a of the metal pillar 6. However, similarly to the first embodiment, the width of the portion of the metal wiring 52 connected to the end 6a may be formed to be larger than the width of the end 6a of the metal pillar 6.
 続いて、図9の(A)に示されるように、金属配線52の端部52aに接続され、配線層5から基板50側とは反対側に突出する金属ピラー6が形成される(第2工程)。金属ピラー6は、例えば、めっき処理、はんだバンプ形成処理等によって形成される。金属ピラー6は、端部52aに接続される端部6aと、端部6aとは反対側の端部6bと、を有している。 Subsequently, as shown in FIG. 9A, a metal pillar 6 is formed which is connected to the end portion 52a of the metal wiring 52 and protrudes from the wiring layer 5 to the side opposite to the substrate 50 side. process). The metal pillar 6 is formed, for example, by plating, solder bump forming, or the like. The metal pillar 6 has an end 6a connected to the end 52a, and an end 6b opposite to the end 6a.
 続いて、図9の(B)に示されるように、受光素子2が準備される(第3工程)。続いて、端部52aとは異なる金属配線52の端部52bと電極端子22とが金属ピラー7を介して電気的に接続され、且つ、受光部21が開口部51bに対向する位置に配置されて基板50と受光素子2との間に内部空間Sが形成されるように、受光素子2が配置される(第4工程)。金属ピラー7は、端部52bに接続される端部7aと、端部7aとは反対側の端部7bと、を有している。なお、上述した通り、金属ピラー7は、何らかの導電性部材であればよく、例えば端部7bと電極端子22とをバンプ接合することによって形成される導電性バンプであってもよい。ここで、絶縁層51の上面(基板50側とは反対側の面)と絶縁層23の下面(基板50に対向する面)とは離間しており、絶縁層51と絶縁層23との間には、隙間が存在する。すなわち、内部空間Sは、当該隙間を介して、外部と連通している。言い換えれば、内部空間Sは、外部から遮断された閉空間とはされていない。 Subsequently, as shown in FIG. 9(B), the light receiving element 2 is prepared (third step). Subsequently, an end 52b of the metal wiring 52 different from the end 52a and the electrode terminal 22 are electrically connected via the metal pillar 7, and the light receiving part 21 is arranged at a position facing the opening 51b. The light receiving element 2 is arranged so that an internal space S is formed between the substrate 50 and the light receiving element 2 (fourth step). The metal pillar 7 has an end 7a connected to the end 52b, and an end 7b opposite to the end 7a. Note that, as described above, the metal pillar 7 may be any conductive member, and may be a conductive bump formed by bump-bonding the end portion 7b and the electrode terminal 22, for example. Here, the upper surface of the insulating layer 51 (the surface opposite to the substrate 50 side) and the lower surface of the insulating layer 23 (the surface facing the substrate 50) are separated, and the gap between the insulating layer 51 and the insulating layer 23 is There is a gap. That is, the internal space S communicates with the outside via the gap. In other words, the interior space S is not a closed space cut off from the outside.
 続いて、図10の(A)に示されるように、モールド樹脂3Bが形成される(第5工程)。モールド樹脂3Bは、上述したように、受光部21の検出対象となる光に対する透明性を有する材料によって形成されており、受光素子2、金属ピラー6,7、及び配線層5を覆うと共に内部空間S(図9の(B)参照)に充填される。 Subsequently, as shown in FIG. 10(A), mold resin 3B is formed (fifth step). As described above, the mold resin 3B is made of a material that is transparent to the light to be detected by the light receiving section 21, and covers the light receiving element 2, the metal pillars 6, 7, and the wiring layer 5, and also covers the internal space. S (see FIG. 9B).
 続いて、図10の(B)に示されるように、受光素子2の第2面2bに対向する側(すなわち、端面3b側)からモールド樹脂3Bを研磨又は研削することにより、受光素子2の第2面2bと金属ピラー6の端部6bとが露出させられる(第6工程)。このとき、各単位領域において、モールド樹脂3Bの端面3bと共に、受光素子2の第2面2bも併せて研磨又は研削されてもよい。同様に、金属ピラー6の端部6bも研磨又は研削されてもよい。つまり、モールド樹脂3Bの端面3bの研磨又は研削によって各単位領域の受光素子2の第2面2b又は金属ピラー6の端部6bが露出した後、さらにモールド樹脂3Bの端面3bと第2面2b又は端部6bとを一括で研磨又は研削する処理が継続されてもよい。その結果、図10の(B)に示されるように、受光素子2の第2面2b及び金属ピラー6の端部6bが外部に露出した状態となる。以上の処理により、受光素子2の第2面2b、金属ピラー6の端部6b、及びモールド樹脂3Bの端面3bは、略面一となる。 Subsequently, as shown in FIG. 10(B), the mold resin 3B is polished or ground from the side facing the second surface 2b of the light-receiving element 2 (that is, the end surface 3b side), so that the light-receiving element 2 is polished. The second surface 2b and the end portion 6b of the metal pillar 6 are exposed (sixth step). At this time, in each unit area, the second surface 2b of the light receiving element 2 may be polished or ground together with the end surface 3b of the molded resin 3B. Similarly, the end portion 6b of the metal pillar 6 may also be polished or ground. That is, after the second surface 2b of the light receiving element 2 or the end 6b of the metal pillar 6 in each unit area is exposed by polishing or grinding the end surface 3b of the molded resin 3B, the end surface 3b and the second surface 2b of the molded resin 3B are further exposed. Alternatively, the process of polishing or grinding the end portion 6b at once may be continued. As a result, as shown in FIG. 10(B), the second surface 2b of the light receiving element 2 and the end portion 6b of the metal pillar 6 are exposed to the outside. Through the above processing, the second surface 2b of the light receiving element 2, the end portion 6b of the metal pillar 6, and the end surface 3b of the molded resin 3B become substantially flush with each other.
 続いて、図11の(A)に示されるように、受光素子2の第2面2b上、及び第2面2bと連続するモールド樹脂3Bの端面3b上に、配線層4が形成される(第7工程)。本実施形態では、受光素子2の第2面2b、金属ピラー6の端部6b、及びモールド樹脂3Bの端面3b上に、絶縁層41及び金属配線42(第2金属配線)が形成される。また、金属配線42の外側端部に対する無電解めっきが行われることにより、上記外側端部の表面にめっき部43が形成される。 Subsequently, as shown in FIG. 11A, a wiring layer 4 is formed on the second surface 2b of the light receiving element 2 and on the end surface 3b of the molded resin 3B that is continuous with the second surface 2b ( 7th step). In this embodiment, an insulating layer 41 and metal wiring 42 (second metal wiring) are formed on the second surface 2b of the light receiving element 2, the end 6b of the metal pillar 6, and the end surface 3b of the molded resin 3B. Further, by performing electroless plating on the outer end portion of the metal wiring 42, a plated portion 43 is formed on the surface of the outer end portion.
 例えば、図10の(B)に示される状態から、絶縁層41のパターニング及び金属配線42のパターン形成を半導体プロセス(シード層形成、フォトリソグラフィ、電解めっき等)を用いて行うことにより、図11の(A)に示される構造が得られる。なお、本実施形態では、絶縁層41の開口41aの幅は、金属ピラー6の端部6bの幅よりも小さく形成されており、その結果、金属配線42における端部6bに接続される部分の配線幅が金属ピラー6の端部6bの幅よりも小さく形成されている。ただし、第1実施形態と同様に、金属配線42における端部6bに接続される部分の配線幅は、金属ピラー6の端部6bの幅よりも大きく形成されてもよい。 For example, from the state shown in FIG. 10B, by patterning the insulating layer 41 and forming the pattern of the metal wiring 42 using a semiconductor process (seed layer formation, photolithography, electrolytic plating, etc.), The structure shown in (A) is obtained. In this embodiment, the width of the opening 41a of the insulating layer 41 is smaller than the width of the end 6b of the metal pillar 6, and as a result, the width of the portion of the metal wiring 42 connected to the end 6b is smaller. The wiring width is formed smaller than the width of the end portion 6b of the metal pillar 6. However, similarly to the first embodiment, the wiring width of the portion of the metal wiring 42 connected to the end 6b may be formed to be larger than the width of the end 6b of the metal pillar 6.
 続いて、図11の(B)に示されるように、配線層5及びモールド樹脂3Bから基板50が分離される(第8工程)。続いて、単位領域間の境界線Lに沿ってダイシングが行われる。これにより、個片化された複数の光半導体パッケージ1Bが得られる。 Subsequently, as shown in FIG. 11(B), the substrate 50 is separated from the wiring layer 5 and the mold resin 3B (eighth step). Subsequently, dicing is performed along the boundary line L between the unit areas. Thereby, a plurality of individualized optical semiconductor packages 1B are obtained.
(作用効果)
 光半導体パッケージ1Bでは、第5工程においてモールド樹脂3Bが受光素子2と基板50との間の内部空間Sに充填されることにより、モールド樹脂3Bが受光部21を覆うことになるが、モールド樹脂3Bは受光部21の検出対象となる光に対する透明性を有するため、モールド樹脂3Bが受光部21を覆うことに起因する受光感度の低下が抑制される。さらに、第5工程において、単一の樹脂材料によって一括で、受光素子2と基板50との間の内部空間Sに充填され且つ各部材(受光素子2、金属ピラー6,7、及び配線層5)を覆うモールド樹脂3Bを形成することができる。これにより、2種類の樹脂部(例えば、互いに異なる材料又は異なるタイミングで形成される2つの樹脂部)が混在することに起因する信頼性の低下(例えば、2つの樹脂部の熱膨張係数差等に起因する応力による金属配線の損傷等)を回避することができる。以上により、上記製造方法によれば、光半導体パッケージ1Bを信頼性高く製造することができる。また、受光素子2は、第1面2aに受光面を有している。上記構成によれば、表面入射型の受光素子2の表面が第1面2aである光半導体パッケージ1Bを信頼性高く製造することができる。
(effect)
In the optical semiconductor package 1B, in the fifth step, the mold resin 3B is filled into the internal space S between the light receiving element 2 and the substrate 50, so that the mold resin 3B covers the light receiving part 21. Since 3B has transparency to the light to be detected by the light receiving section 21, a decrease in light receiving sensitivity caused by the mold resin 3B covering the light receiving section 21 is suppressed. Furthermore, in the fifth step, the internal space S between the light receiving element 2 and the substrate 50 is filled with a single resin material, and each member (the light receiving element 2, the metal pillars 6, 7, and the wiring layer 5) is filled with a single resin material. ) can be formed to cover the mold resin 3B. This reduces reliability due to the coexistence of two types of resin parts (for example, two resin parts formed from different materials or at different times) (for example, due to differences in thermal expansion coefficients between the two resin parts). (damage to metal wiring due to stress caused by stress, etc.) can be avoided. As described above, according to the above manufacturing method, the optical semiconductor package 1B can be manufactured with high reliability. Further, the light receiving element 2 has a light receiving surface on the first surface 2a. According to the above configuration, the optical semiconductor package 1B in which the surface of the front-illuminated light receiving element 2 is the first surface 2a can be manufactured with high reliability.
 また、上記の光半導体パッケージ1Bの製造方法では、減圧下において第5工程を実施することにより、特殊な装置を利用することなく、ボイドのないモールド樹脂3Bを一括で形成することができる。 Furthermore, in the method for manufacturing the optical semiconductor package 1B described above, by carrying out the fifth step under reduced pressure, the void-free mold resin 3B can be formed all at once without using any special equipment.
(変形例)
 基板50を配線層5等から分離(剥離)する工程(第8工程)は、第5工程が完了した後の任意のタイミングで実施されればよい。例えば、基板50は、第5工程の完了後に直ちに除去されてもよい。或いは、第8工程は、少なくとも第6工程よりも後に実施されてもよい。例えば、第7工程は、第6工程の後に実施されてもよく、第8工程は、第7工程の後に実施されてもよい。上記構成によれば、基板50を第6工程(或いは、第6工程及び第7工程)においても取り付けた状態にすることによって、各部材の支持安定性を高めた状態で第6工程及び第7工程を信頼性高く実施できるという利点が得られる。
(Modified example)
The step of separating (peeling) the substrate 50 from the wiring layer 5 and the like (eighth step) may be performed at any timing after the fifth step is completed. For example, substrate 50 may be removed immediately after completing the fifth step. Alternatively, the eighth step may be performed at least after the sixth step. For example, the seventh step may be performed after the sixth step, and the eighth step may be performed after the seventh step. According to the above configuration, by keeping the substrate 50 attached in the sixth step (or the sixth step and the seventh step), the sixth step and the seventh step are carried out in a state where the support stability of each member is increased. The advantage is that the process can be performed reliably.
[第3実施形態]
(光半導体パッケージの構造)
 図12に示されるように、第3実施形態の光半導体パッケージ1Cは、配線層5の代わりに配線層5Cを備える点において、光半導体パッケージ1Aと相違している。以下、光半導体パッケージ1Cの構成のうち光半導体パッケージ1Aと異なる部分について説明し、光半導体パッケージ1Cの構成のうち光半導体パッケージ1Aと同様の部分についての説明を省略する。
[Third embodiment]
(Structure of optical semiconductor package)
As shown in FIG. 12, the optical semiconductor package 1C of the third embodiment is different from the optical semiconductor package 1A in that it includes a wiring layer 5C instead of the wiring layer 5. Hereinafter, the parts of the optical semiconductor package 1C that are different from the optical semiconductor package 1A will be described, and the description of the parts of the optical semiconductor package 1C that are similar to the optical semiconductor package 1A will be omitted.
 配線層5Cは、絶縁層51の代わりに絶縁層51Cを有する点において、光半導体パッケージ1Aの配線層5と相違している。絶縁層51Cは、透明な樹脂絶縁膜によって形成されると共に開口部51bが設けられていない点において、絶縁層51と相違している。絶縁層51Cは、受光部21の検出対象となる光に対する透明性を有する材料によって形成されている。絶縁層51Cは、例えば、透明エポキシ樹脂、透明ポリイミド樹脂等によって形成され得る。 The wiring layer 5C is different from the wiring layer 5 of the optical semiconductor package 1A in that it has an insulating layer 51C instead of the insulating layer 51. The insulating layer 51C is different from the insulating layer 51 in that it is formed of a transparent resin insulating film and does not have an opening 51b. The insulating layer 51C is made of a material that is transparent to the light that the light receiving section 21 detects. The insulating layer 51C may be formed of, for example, transparent epoxy resin, transparent polyimide resin, or the like.
(光半導体パッケージの製造方法)
 図13~図15を参照して、光半導体パッケージ1Cの製造工程の一例について説明する。本実施形態では、光半導体パッケージ1Cは、CoW方式又はCoP方式によって製造される。図13~図15は、各製造工程における1つの単位領域の状態を示している。以下では、1つの単位領域のみに着目して説明を行う。
(Method for manufacturing optical semiconductor package)
An example of the manufacturing process of the optical semiconductor package 1C will be described with reference to FIGS. 13 to 15. In this embodiment, the optical semiconductor package 1C is manufactured by a CoW method or a CoP method. 13 to 15 show the state of one unit area in each manufacturing process. The following description focuses on only one unit area.
 本実施形態に係る光半導体パッケージ1Cの製造方法は、
 受光部21及び受光部21と電気的に接続された電極端子22が設けられた第1面2aを有する受光素子2を準備する第1工程と、
 受光部21の検出対象となる光に対する透明性を有する絶縁層51Cと金属配線52とを含む配線層5Cを基板50上に形成する第2工程と、
 金属配線52の端部52aに接続され、配線層5Cから基板50側とは反対側に突出する金属部材(金属ピラー6)を形成する第3工程と、
 金属配線52の端部52bと電極端子22とが電気的に接続されるように、受光素子2を配線層5C上に配置する第4工程と、
 受光素子2、金属ピラー6、及び配線層5Cを覆う樹脂部(モールド樹脂3)を形成する第5工程と、
 受光素子2の第2面2bに対向する側からモールド樹脂3を研磨又は研削することにより、受光素子2の第2面2bと金属ピラー6の端部6bとを露出させる第6工程と、
 受光素子2の第2面2b上、及び第2面2bと連続するモールド樹脂3の端面3b上に、金属ピラー6の端部6bと電気的に接続される金属配線42を含む配線層4を形成する第7工程と、
 配線層5C及びモールド樹脂3から基板50を分離する第8工程と、を含む。
The method for manufacturing the optical semiconductor package 1C according to this embodiment is as follows:
a first step of preparing a light receiving element 2 having a first surface 2a provided with a light receiving section 21 and an electrode terminal 22 electrically connected to the light receiving section 21;
a second step of forming, on the substrate 50, a wiring layer 5C including an insulating layer 51C and a metal wiring 52 that is transparent to light to be detected by the light receiving section 21;
a third step of forming a metal member (metal pillar 6) connected to the end portion 52a of the metal wiring 52 and protruding from the wiring layer 5C to the side opposite to the substrate 50 side;
a fourth step of arranging the light receiving element 2 on the wiring layer 5C so that the end 52b of the metal wiring 52 and the electrode terminal 22 are electrically connected;
a fifth step of forming a resin part (molding resin 3) covering the light receiving element 2, the metal pillar 6, and the wiring layer 5C;
a sixth step of exposing the second surface 2b of the light receiving element 2 and the end portion 6b of the metal pillar 6 by polishing or grinding the mold resin 3 from the side facing the second surface 2b of the light receiving element 2;
On the second surface 2b of the light receiving element 2 and on the end surface 3b of the molded resin 3 continuous with the second surface 2b, a wiring layer 4 including a metal wiring 42 electrically connected to the end 6b of the metal pillar 6 is provided. a seventh step of forming;
An eighth step of separating the substrate 50 from the wiring layer 5C and the mold resin 3 is included.
 まず、受光素子2(図13の(B)参照)が準備される(第1工程)。続いて、図13の(A)に示されるように、仮接合部材である基板50上に、配線層5Cが形成される(第2工程)。上述したように、配線層5Cは、絶縁層51Cと金属配線52とを有している。例えば、絶縁層51Cのパターニング及び金属配線52のパターン形成を半導体プロセス(シード層形成、フォトリソグラフィ、電解めっき等)を用いて行うことにより、図13の(A)に示される配線層5Cが得られる。なお、本実施形態では、絶縁層51Cの開口51aの幅は、金属ピラー6の端部6aの幅よりも大きく形成されており、その結果、金属配線52における端部6aに接続される部分の配線幅が金属ピラー6の端部6aの幅よりも大きく形成されている。ただし、第2実施形態と同様に、金属配線52における端部6aに接続される部分の配線幅は、金属ピラー6の端部6aの幅よりも小さく形成されてもよい。 First, the light receiving element 2 (see (B) in FIG. 13) is prepared (first step). Subsequently, as shown in FIG. 13A, a wiring layer 5C is formed on the substrate 50, which is a temporary bonding member (second step). As described above, the wiring layer 5C includes the insulating layer 51C and the metal wiring 52. For example, by patterning the insulating layer 51C and patterning the metal wiring 52 using a semiconductor process (seed layer formation, photolithography, electrolytic plating, etc.), the wiring layer 5C shown in FIG. It will be done. Note that in this embodiment, the width of the opening 51a of the insulating layer 51C is formed to be larger than the width of the end 6a of the metal pillar 6, and as a result, the width of the portion of the metal wiring 52 connected to the end 6a is The wiring width is formed to be larger than the width of the end portion 6a of the metal pillar 6. However, similarly to the second embodiment, the wiring width of the portion of the metal wiring 52 connected to the end 6a may be formed smaller than the width of the end 6a of the metal pillar 6.
 続いて、図13の(A)に示されるように、金属配線52の端部52aに接続され、配線層5Cから基板50側とは反対側に突出する金属ピラー6が形成される(第3工程)。金属ピラー6は、例えば、めっき処理、はんだバンプ形成処理等によって形成される。 Subsequently, as shown in FIG. 13A, a metal pillar 6 is formed which is connected to the end 52a of the metal wiring 52 and protrudes from the wiring layer 5C to the side opposite to the substrate 50 side. process). The metal pillar 6 is formed, for example, by plating, solder bump forming, or the like.
 続いて、図13の(B)に示されるように、金属配線52の端部52bと電極端子22とが電気的に接続されるように、受光素子2が配線層5C上に配置される(第4工程)。端部52bと電極端子22とは、例えば、バンプ接合によって接続される。これにより、絶縁層51Cと絶縁層23とは、互いに当接した状態となり、絶縁層51Cと絶縁層23との間に隙間は形成されない。なお、端部52bと電極端子22とは、銅及び絶縁膜を用いたハイブリッド接合によって接続されてもよい。 Subsequently, as shown in FIG. 13(B), the light receiving element 2 is placed on the wiring layer 5C so that the end 52b of the metal wiring 52 and the electrode terminal 22 are electrically connected ( 4th step). The end portion 52b and the electrode terminal 22 are connected, for example, by bump bonding. As a result, the insulating layer 51C and the insulating layer 23 are brought into contact with each other, and no gap is formed between the insulating layer 51C and the insulating layer 23. Note that the end portion 52b and the electrode terminal 22 may be connected by hybrid bonding using copper and an insulating film.
 続いて、図14の(A)に示されるように、モールド樹脂3が形成される(第5工程)。モールド樹脂3は、受光素子2、金属ピラー6、及び配線層5Cを覆うように形成される。 Subsequently, as shown in FIG. 14(A), mold resin 3 is formed (fifth step). The mold resin 3 is formed to cover the light receiving element 2, the metal pillar 6, and the wiring layer 5C.
 続いて、図14の(B)に示されるように、受光素子2の第2面2bに対向する側(すなわち、端面3b側)からモールド樹脂3を研磨又は研削することにより、受光素子2の第2面2bと金属ピラー6の端部6bとが露出させられる(第6工程)。このとき、各単位領域において、モールド樹脂3の端面3bと共に、受光素子2の第2面2bも併せて研磨又は研削されてもよい。同様に、金属ピラー6の端部6bも研磨又は研削されてもよい。つまり、モールド樹脂3の端面3bの研磨又は研削によって各単位領域の受光素子2の第2面2b又は金属ピラー6の端部6bが露出した後、さらにモールド樹脂3の端面3bと第2面2b又は端部6bとを一括で研磨又は研削する処理が継続されてもよい。その結果、図14の(B)に示されるように、受光素子2の第2面2b及び金属ピラー6の端部6bが外部に露出した状態となる。以上の処理により、受光素子2の第2面2b、金属ピラー6の端部6b、及びモールド樹脂3の端面3bは、略面一となる。 Subsequently, as shown in FIG. 14(B), the mold resin 3 is polished or ground from the side facing the second surface 2b of the light-receiving element 2 (i.e., the end surface 3b side), so that the light-receiving element 2 is polished or ground. The second surface 2b and the end portion 6b of the metal pillar 6 are exposed (sixth step). At this time, in each unit area, the end surface 3b of the molded resin 3 and the second surface 2b of the light-receiving element 2 may also be polished or ground. Similarly, the end portion 6b of the metal pillar 6 may also be polished or ground. That is, after the second surface 2b of the light receiving element 2 or the end 6b of the metal pillar 6 in each unit area is exposed by polishing or grinding the end surface 3b of the molded resin 3, the end surface 3b and the second surface 2b of the molded resin 3 are further exposed. Alternatively, the process of polishing or grinding the end portion 6b at once may be continued. As a result, as shown in FIG. 14(B), the second surface 2b of the light receiving element 2 and the end portion 6b of the metal pillar 6 are exposed to the outside. Through the above processing, the second surface 2b of the light receiving element 2, the end portion 6b of the metal pillar 6, and the end surface 3b of the molded resin 3 become substantially flush with each other.
 続いて、図15の(A)に示されるように、受光素子2の第2面2b上、及び第2面2bと連続するモールド樹脂3の端面3b上に、配線層4が形成される(第7工程)。本実施形態では、受光素子2の第2面2b、金属ピラー6の端部6b、及びモールド樹脂3の端面3b上に、絶縁層41及び金属配線42が形成される。また、金属配線42の外側端部に対する無電解めっきが行われることにより、上記外側端部の表面にめっき部43が形成される。 Subsequently, as shown in FIG. 15A, a wiring layer 4 is formed on the second surface 2b of the light receiving element 2 and on the end surface 3b of the molded resin 3 that is continuous with the second surface 2b. 7th step). In this embodiment, an insulating layer 41 and metal wiring 42 are formed on the second surface 2b of the light receiving element 2, the end 6b of the metal pillar 6, and the end surface 3b of the molded resin 3. Further, by performing electroless plating on the outer end portion of the metal wiring 42, a plated portion 43 is formed on the surface of the outer end portion.
 例えば、図14の(B)に示される状態から、絶縁層41のパターニング及び金属配線42のパターン形成を半導体プロセス(シード層形成、フォトリソグラフィ、電解めっき等)を用いて行うことにより、図15の(A)に示される構造が得られる。なお、本実施形態では、絶縁層41の開口41aの幅は、金属ピラー6の端部6bの幅よりも大きく形成されており、その結果、金属配線42における端部6bに接続される部分の配線幅が金属ピラー6の端部6bの幅よりも大きく形成されている。ただし、第2実施形態と同様に、金属配線42における端部6bに接続される部分の配線幅は、金属ピラー6の端部6bの幅よりも小さく形成されてもよい。 For example, from the state shown in FIG. 14B, by patterning the insulating layer 41 and forming the pattern of the metal wiring 42 using a semiconductor process (seed layer formation, photolithography, electrolytic plating, etc.), The structure shown in (A) is obtained. Note that in this embodiment, the width of the opening 41a of the insulating layer 41 is formed to be larger than the width of the end 6b of the metal pillar 6, and as a result, the width of the portion of the metal wiring 42 connected to the end 6b is The wiring width is formed to be larger than the width of the end portion 6b of the metal pillar 6. However, similarly to the second embodiment, the wiring width of the portion of the metal wiring 42 connected to the end 6b may be formed smaller than the width of the end 6b of the metal pillar 6.
 続いて、図15の(B)に示されるように、配線層5及びモールド樹脂3から基板50が分離される(第8工程)。続いて、単位領域間の境界線Lに沿ってダイシングが行われる。これにより、個片化された複数の光半導体パッケージ1Cが得られる。 Subsequently, as shown in FIG. 15(B), the substrate 50 is separated from the wiring layer 5 and the mold resin 3 (eighth step). Subsequently, dicing is performed along the boundary line L between the unit areas. Thereby, a plurality of individualized optical semiconductor packages 1C are obtained.
 上記のような製造方法によれば、受光素子2の表面側(第1面2a側)の配線層5を先に作製した後に、受光素子2の搭載(チップマウント)、樹脂モールド(モールド樹脂3の形成)、及び受光素子2の裏面側(第2面2b側)の配線層4の作製を行う手順によって、光半導体パッケージ1Cを製造することができる。なお、上記製造方法においても、基板50を配線層5等から分離(剥離)する工程(第8工程)は、第5工程が完了した後の任意のタイミングで実施されればよい。例えば、基板50は、第5工程の完了後に直ちに除去されてもよい。ただし、基板50を第6工程及び第7工程においても取り付けた状態にすることによって、各部材の支持安定性を高めた状態で第6工程及び第7工程を信頼性高く実施できるという利点が得られる。 According to the above manufacturing method, after the wiring layer 5 on the front surface side (first surface 2a side) of the light receiving element 2 is produced first, mounting of the light receiving element 2 (chip mount), resin molding (molding resin 3 The optical semiconductor package 1C can be manufactured by the steps of forming the wiring layer 4 on the back surface side (second surface 2b side) of the light receiving element 2. In addition, also in the said manufacturing method, the process (8th process) of separating (peeling) the board|substrate 50 from the wiring layer 5 etc. may be performed at arbitrary timing after the 5th process is completed. For example, substrate 50 may be removed immediately after completing the fifth step. However, by keeping the substrate 50 attached in the sixth and seventh steps, there is an advantage that the sixth and seventh steps can be carried out with high reliability while increasing the support stability of each member. It will be done.
 上記の光半導体パッケージ1Cの製造方法において、「配線層5C」及び「絶縁層51C」を「配線層5」及び「絶縁層51」に置き換えると共に、図13に示した工程を図16に示す工程に置き換えることにより、光半導体パッケージ1Aと同様の構造を有する光半導体パッケージを製造することができる。 In the method for manufacturing the optical semiconductor package 1C described above, "wiring layer 5C" and "insulating layer 51C" are replaced with "wiring layer 5" and "insulating layer 51", and the process shown in FIG. 13 is replaced with the process shown in FIG. 16. By replacing it with , it is possible to manufacture an optical semiconductor package having the same structure as the optical semiconductor package 1A.
 より具体的には、上記の光半導体パッケージ1Cの製造方法の第2工程は、「絶縁層51と金属配線52とを含むと共に基板50を露出させる開口部51bが設けられた配線層5を基板50上に形成する第2工程」に置き換えられる。これにより、第3工程が完了した時点において、図13の(A)に示される構造の代わりに、図16の(A)に示される構造が得られる。 More specifically, in the second step of the method for manufacturing the optical semiconductor package 1C described above, "a wiring layer 5 including an insulating layer 51 and a metal wiring 52 and provided with an opening 51b for exposing the substrate 50 is placed on a substrate. "Second step of forming on 50". As a result, when the third step is completed, the structure shown in FIG. 16A is obtained instead of the structure shown in FIG. 13A.
 また、上記の光半導体パッケージ1Cの製造方法の第4工程は、「金属配線52の端部52bと電極端子22とが電気的に接続され、且つ、受光部21が開口部51bに対向する位置に配置されて基板50と受光素子2との間に閉空間S1が形成されるように、受光素子2を配線層5上に配置する第4工程」に置き換えられる。これにより、第4工程が完了した時点において、図13の(B)に示される構造の代わりに、図16の(B)に示される構造が得られる。ここで、閉空間S1は、基板50と絶縁層23と絶縁層51とに包囲された密閉空間とされる。このため、第5工程において、モールド樹脂3は、受光素子2、金属ピラー6、及び配線層5を覆うように形成され、閉空間S1にはモールド樹脂3は充填されない。その結果、後続の第6工程~第8工程及びダイシングが完了した時点において、図1に示した光半導体パッケージ1Aと同様の構造を有する光半導体パッケージが得られる。 Further, the fourth step of the method for manufacturing the optical semiconductor package 1C described above is performed at a position where the end portion 52b of the metal wiring 52 and the electrode terminal 22 are electrically connected, and the light receiving portion 21 faces the opening portion 51b. "4th step" in which the light receiving element 2 is arranged on the wiring layer 5 so that a closed space S1 is formed between the substrate 50 and the light receiving element 2. As a result, when the fourth step is completed, the structure shown in FIG. 16(B) is obtained instead of the structure shown in FIG. 13(B). Here, the closed space S1 is a sealed space surrounded by the substrate 50, the insulating layer 23, and the insulating layer 51. Therefore, in the fifth step, the mold resin 3 is formed to cover the light receiving element 2, the metal pillar 6, and the wiring layer 5, and the mold resin 3 is not filled in the closed space S1. As a result, when the subsequent sixth to eighth steps and dicing are completed, an optical semiconductor package having the same structure as the optical semiconductor package 1A shown in FIG. 1 is obtained.
 以上、本開示のいくつかの実施形態について説明したが、本開示は、上記実施形態に限られない。各構成の材料及び形状には、上述した材料及び形状に限らず、様々な材料及び形状を採用することができる。また、上述した一の実施形態又は変形例における一部の構成は、他の実施形態又は変形例における構成に任意に適用することができる。例えば、上記実施形態で示したように、基板50を仮接合部材として好適に用いることが可能であるが、仮接合部材は、基板以外の部材であってもよい。例えば、シート部材(例えば、シート状の非常に薄い部材)が仮接合部材として用いられてもよい。また、上記実施形態では、CoW方式又はCoP方式による製造方法を例示したが、上記以外の方式が採用されてもよい。例えば、チップ単位で光半導体パッケージが製造される場合、上記実施形態におけるダイシング工程は省略され得る。 Although several embodiments of the present disclosure have been described above, the present disclosure is not limited to the above embodiments. The materials and shapes of each structure are not limited to the materials and shapes described above, but various materials and shapes can be employed. Furthermore, some of the configurations in one embodiment or modification example described above can be arbitrarily applied to the configurations in other embodiments or modification examples. For example, as shown in the above embodiment, the substrate 50 can be suitably used as a temporary bonding member, but the temporary bonding member may be a member other than the substrate. For example, a sheet member (for example, a very thin sheet-like member) may be used as the temporary joining member. Further, in the above embodiments, a manufacturing method using a CoW method or a CoP method is exemplified, but methods other than the above may be adopted. For example, when an optical semiconductor package is manufactured on a chip-by-chip basis, the dicing step in the above embodiment can be omitted.
 1A,1B,1C…光半導体パッケージ、2…受光素子、2a…第1面、2b…第2面、3,3B…モールド樹脂(樹脂部)、4…配線層(第1配線層、第2配線層)、5…配線層(第1配線層、第2配線層)、6,6A…金属ピラー(金属部材)、6a…端部(第1端部)、6b…端部(第2端部)、21…受光部、22…電極端子、42…金属配線(第1金属配線、第2金属配線)、50…基板、51b…開口部、52…金属配線(第1金属配線、第2金属配線)、61…軸部、62…フランジ部、62a…内面、100…支持部材、101…板状部材、101a…貫通孔、102…支持基板。 1A, 1B, 1C... Optical semiconductor package, 2... Light receiving element, 2a... First surface, 2b... Second surface, 3, 3B... Mold resin (resin part), 4... Wiring layer (first wiring layer, second wiring layer), 5... wiring layer (first wiring layer, second wiring layer), 6, 6A... metal pillar (metal member), 6a... end (first end), 6b... end (second end) part), 21... Light receiving part, 22... Electrode terminal, 42... Metal wiring (first metal wiring, second metal wiring), 50... Substrate, 51b... Opening, 52... Metal wiring (first metal wiring, second metal wiring) metal wiring), 61... shaft portion, 62... flange portion, 62a... inner surface, 100... support member, 101... plate member, 101a... through hole, 102... support substrate.

Claims (15)

  1.  受光部及び前記受光部と電気的に接続された電極端子が設けられた第1面を有する受光素子と、柱状の金属部材の第1端部と、を基板に仮接合する第1工程であって、前記第1面が前記基板に対向するように前記受光素子を前記基板に仮接合する前記第1工程と、
     前記受光素子及び前記金属部材を覆う樹脂部を前記基板上に形成する第2工程と、
     前記受光素子の前記第1面とは反対側の第2面に対向する側から前記樹脂部を研磨又は研削することにより、前記受光素子の前記第2面と前記金属部材の前記第1端部とは反対側の第2端部とを露出させる第3工程と、
     前記受光素子の前記第2面上、及び前記第2面と連続する前記樹脂部の端面上に、前記第2端部と電気的に接続される第1金属配線を含む第1配線層を形成する第4工程と、
     前記受光素子、前記金属部材、及び前記樹脂部から前記基板を分離する第5工程と、
     前記第5工程よりも後に、前記受光素子及び前記樹脂部に対して前記第1配線層が位置する側とは反対側に、前記第1端部と前記電極端子とを電気的に接続する第2金属配線を含む第2配線層を形成する第6工程と、を含む、
     光半導体パッケージの製造方法。
    A first step of temporarily bonding a light receiving element having a first surface provided with a light receiving part and an electrode terminal electrically connected to the light receiving part, and a first end of a columnar metal member to a substrate. the first step of temporarily bonding the light receiving element to the substrate so that the first surface faces the substrate;
    a second step of forming a resin part on the substrate to cover the light receiving element and the metal member;
    The second surface of the light receiving element and the first end of the metal member are polished or ground by polishing or grinding the resin portion from the side opposite to the second surface of the light receiving element opposite to the first surface. a third step of exposing the second end on the opposite side;
    A first wiring layer including a first metal wiring electrically connected to the second end is formed on the second surface of the light receiving element and on an end surface of the resin part that is continuous with the second surface. A fourth step of
    a fifth step of separating the substrate from the light receiving element, the metal member, and the resin part;
    After the fifth step, a step of electrically connecting the first end portion and the electrode terminal on a side opposite to the side where the first wiring layer is located with respect to the light receiving element and the resin portion. a sixth step of forming a second wiring layer including two metal wirings;
    A method for manufacturing an optical semiconductor package.
  2.  前記第1工程は、
      支持部材によって、前記第1端部を露出させた状態で前記金属部材を位置決めすると共に支持する工程と、
      前記支持部材に支持されている前記金属部材の前記第1端部に対して、前記基板の仮接合面を接触させることにより、前記基板に前記第1端部を仮接合する工程と、を含む、
     請求項1に記載の光半導体パッケージの製造方法。
    The first step is
    positioning and supporting the metal member with the first end exposed by a support member;
    Temporarily bonding the first end to the substrate by bringing a temporary bonding surface of the substrate into contact with the first end of the metal member supported by the support member. ,
    A method for manufacturing an optical semiconductor package according to claim 1.
  3.  前記支持部材は、
      前記金属部材の幅よりも大きい幅を有する貫通孔が形成された板状部材と、
      前記第2端部が載置及び支持される支持基板と、を有し、
     前記金属部材は、前記板状部材の前記貫通孔に挿通されて位置決めされると共に、前記支持基板に支持され、
     前記金属部材が前記支持部材に支持された状態において、前記第1端部は、前記板状部材に対して前記支持基板側とは反対側に突出している、
     請求項2に記載の光半導体パッケージの製造方法。
    The support member is
    a plate-like member in which a through hole having a width larger than the width of the metal member is formed;
    a support substrate on which the second end portion is placed and supported;
    The metal member is inserted into and positioned through the through hole of the plate member, and is supported by the support substrate,
    In a state in which the metal member is supported by the support member, the first end protrudes from the plate-shaped member on a side opposite to the support substrate side.
    The method for manufacturing an optical semiconductor package according to claim 2.
  4.  前記金属部材は、前記第2端部を含む軸部と、前記第1端部を含み且つ前記軸部よりも幅広に形成されたフランジ部と、を有し、
     前記支持部材は、前記軸部の幅よりも大きく前記フランジ部の幅よりも小さい幅を有する貫通孔が形成された板状部材であり、
     前記金属部材は、前記軸部が前記貫通孔に挿通され、前記フランジ部の前記第2端部側の内面が前記支持部材の前記貫通孔の周縁部に当接することによって、前記支持部材に支持される、
     請求項2に記載の光半導体パッケージの製造方法。
    The metal member has a shaft portion including the second end portion, and a flange portion including the first end portion and formed wider than the shaft portion,
    The support member is a plate-like member in which a through hole is formed having a width larger than the width of the shaft portion and smaller than the width of the flange portion,
    The metal member is supported by the support member by having the shaft portion inserted into the through hole and the inner surface of the flange portion on the second end side coming into contact with the peripheral edge of the through hole of the support member. be done,
    The method for manufacturing an optical semiconductor package according to claim 2.
  5.  前記第4工程において、前記第1金属配線における前記第2端部に接続される部分の配線幅が前記金属部材の前記第2端部の幅よりも大きくなるように、前記第1配線層を形成する、
     請求項1~4のいずれか一項に記載の光半導体パッケージの製造方法。
    In the fourth step, the first wiring layer is formed such that a wiring width of a portion of the first metal wiring connected to the second end is larger than a width of the second end of the metal member. Form,
    A method for manufacturing an optical semiconductor package according to any one of claims 1 to 4.
  6.  前記第4工程において、前記第1金属配線における前記第2端部に接続される部分の配線幅が前記金属部材の前記第2端部の幅よりも小さくなるように、前記第1配線層を形成する、
     請求項1~4のいずれか一項に記載の光半導体パッケージの製造方法。
    In the fourth step, the first wiring layer is formed such that a wiring width of a portion of the first metal wiring connected to the second end is smaller than a width of the second end of the metal member. Form,
    A method for manufacturing an optical semiconductor package according to any one of claims 1 to 4.
  7.  前記第6工程において、前記第2金属配線における前記第1端部に接続される部分の配線幅が前記金属部材の前記第1端部の幅よりも大きくなるように、前記第2配線層を形成する、
     請求項1~6のいずれか一項に記載の光半導体パッケージの製造方法。
    In the sixth step, the second wiring layer is formed such that a wiring width of a portion of the second metal wiring connected to the first end is larger than a width of the first end of the metal member. Form,
    A method for manufacturing an optical semiconductor package according to any one of claims 1 to 6.
  8.  前記第6工程において、前記第2金属配線における前記第1端部に接続される部分の配線幅が前記金属部材の前記第1端部の幅よりも小さくなるように、前記第2配線層を形成する、
     請求項1~6のいずれか一項に記載の光半導体パッケージの製造方法。
    In the sixth step, the second wiring layer is formed such that a wiring width of a portion of the second metal wiring connected to the first end is smaller than a width of the first end of the metal member. Form,
    A method for manufacturing an optical semiconductor package according to any one of claims 1 to 6.
  9.  前記第5工程は、少なくとも前記第3工程よりも後に実施される、
     請求項1~8のいずれか一項に記載の光半導体パッケージの製造方法。
    The fifth step is performed at least after the third step,
    A method for manufacturing an optical semiconductor package according to any one of claims 1 to 8.
  10.  前記第4工程は、前記第3工程の後に実施され、
     前記第5工程は、前記第4工程の後に実施される、
     請求項9に記載の光半導体パッケージの製造方法。
    The fourth step is performed after the third step,
    The fifth step is performed after the fourth step,
    The method for manufacturing an optical semiconductor package according to claim 9.
  11.  前記受光素子は、前記第1面に受光面を有する、
     請求項1~10のいずれか一項に記載の光半導体パッケージの製造方法。
    The light receiving element has a light receiving surface on the first surface.
    A method for manufacturing an optical semiconductor package according to any one of claims 1 to 10.
  12.  基板上に、第1金属配線を含むと共に前記基板を露出させる開口部が設けられた第1配線層を形成する第1工程と、
     前記第1金属配線の第1端部に接続され、前記第1配線層から前記基板側とは反対側に突出する金属部材を形成する第2工程と、
     受光部及び前記受光部と電気的に接続された電極端子が設けられた第1面を有する受光素子を準備する第3工程と、
     前記第1端部とは異なる前記第1金属配線の第2端部と前記電極端子とが電気的に接続され、且つ、前記受光部が前記開口部に対向する位置に配置されて前記基板と前記受光素子との間に内部空間が形成されるように、前記受光素子を配置する第4工程と、
     前記受光素子、前記金属部材、及び前記第1配線層を覆うと共に前記内部空間に充填され、前記受光部の検出対象となる光に対する透明性を有する樹脂部を形成する第5工程と、
     前記受光素子の前記第1面とは反対側の第2面に対向する側から前記樹脂部を研磨又は研削することにより、前記第2面と前記金属部材の前記第1金属配線に接続される側とは反対側の端部とを露出させる第6工程と、
     前記受光素子の前記第2面上、及び前記第2面と連続する前記樹脂部の端面上に、前記金属部材の前記端部と電気的に接続される第2金属配線を含む第2配線層を形成する第7工程と、
     前記第1配線層及び前記樹脂部から前記基板を分離する第8工程と、を含む、
     光半導体パッケージの製造方法。
    a first step of forming a first wiring layer on the substrate that includes a first metal wiring and is provided with an opening that exposes the substrate;
    a second step of forming a metal member connected to the first end of the first metal wiring and protruding from the first wiring layer to a side opposite to the substrate;
    a third step of preparing a light receiving element having a first surface provided with a light receiving portion and an electrode terminal electrically connected to the light receiving portion;
    A second end of the first metal wiring, which is different from the first end, is electrically connected to the electrode terminal, and the light receiving section is disposed at a position facing the opening, and is connected to the substrate. a fourth step of arranging the light receiving element so that an internal space is formed between the light receiving element;
    a fifth step of forming a resin part that covers the light receiving element, the metal member, and the first wiring layer, fills the internal space, and has transparency to light to be detected by the light receiving part;
    By polishing or grinding the resin portion from a side opposite to a second surface of the light receiving element opposite to the first surface, the second surface is connected to the first metal wiring of the metal member. a sixth step of exposing the end opposite to the side;
    a second wiring layer including a second metal wiring electrically connected to the end of the metal member on the second surface of the light receiving element and on an end surface of the resin part continuous with the second surface; a seventh step of forming;
    an eighth step of separating the substrate from the first wiring layer and the resin part;
    A method for manufacturing an optical semiconductor package.
  13.  前記第8工程は、少なくとも前記第6工程よりも後に実施される、
     請求項12に記載の光半導体パッケージの製造方法。
    The eighth step is performed at least after the sixth step,
    The method for manufacturing an optical semiconductor package according to claim 12.
  14.  前記第7工程は、前記第6工程の後に実施され、
     前記第8工程は、前記第7工程の後に実施される、
     請求項12に記載の光半導体パッケージの製造方法。
    The seventh step is performed after the sixth step,
    The eighth step is performed after the seventh step,
    The method for manufacturing an optical semiconductor package according to claim 12.
  15.  前記受光素子は、前記第1面に受光面を有する、
     請求項12~14のいずれか一項に記載の光半導体パッケージの製造方法。
    The light receiving element has a light receiving surface on the first surface.
    The method for manufacturing an optical semiconductor package according to any one of claims 12 to 14.
PCT/JP2023/007678 2022-03-30 2023-03-01 Method for manufacturing optical semiconductor package WO2023189153A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2022-055178 2022-03-30
JP2022055178A JP2023147595A (en) 2022-03-30 2022-03-30 Method for manufacturing optical semiconductor package

Publications (1)

Publication Number Publication Date
WO2023189153A1 true WO2023189153A1 (en) 2023-10-05

Family

ID=88201135

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2023/007678 WO2023189153A1 (en) 2022-03-30 2023-03-01 Method for manufacturing optical semiconductor package

Country Status (3)

Country Link
JP (1) JP2023147595A (en)
TW (1) TW202343818A (en)
WO (1) WO2023189153A1 (en)

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001339011A (en) * 2000-03-24 2001-12-07 Shinko Electric Ind Co Ltd Semiconductor device and its manufacturing method
JP2004111792A (en) * 2002-09-20 2004-04-08 Casio Comput Co Ltd Semiconductor package and its manufacturing method
JP2006128625A (en) * 2004-09-30 2006-05-18 Oki Electric Ind Co Ltd Semiconductor device and its manufacturing method
JP2006147835A (en) * 2004-11-19 2006-06-08 Casio Comput Co Ltd Semiconductor device
JP2016134577A (en) * 2015-01-22 2016-07-25 日本放送協会 Solid state image pickup element manufacturing method

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001339011A (en) * 2000-03-24 2001-12-07 Shinko Electric Ind Co Ltd Semiconductor device and its manufacturing method
JP2004111792A (en) * 2002-09-20 2004-04-08 Casio Comput Co Ltd Semiconductor package and its manufacturing method
JP2006128625A (en) * 2004-09-30 2006-05-18 Oki Electric Ind Co Ltd Semiconductor device and its manufacturing method
JP2006147835A (en) * 2004-11-19 2006-06-08 Casio Comput Co Ltd Semiconductor device
JP2016134577A (en) * 2015-01-22 2016-07-25 日本放送協会 Solid state image pickup element manufacturing method

Also Published As

Publication number Publication date
JP2023147595A (en) 2023-10-13
TW202343818A (en) 2023-11-01

Similar Documents

Publication Publication Date Title
US6930327B2 (en) Solid-state imaging device and method of manufacturing the same
EP1662564B1 (en) Semiconductor package and manufacturing method thereof
US8716109B2 (en) Chip package and fabrication method thereof
KR101173698B1 (en) Semiconductor chip manufacturing method, semiconductor chip, semiconductor device manufacturing method, and semiconductor device
US7265916B2 (en) Module for optical devices, and manufacturing method of module for optical devices
US6940141B2 (en) Flip-chip image sensor packages and methods of fabrication
US7534656B2 (en) Image sensor device and method of manufacturing the same
US7169645B2 (en) Methods of fabrication of package assemblies for optically interactive electronic devices
US20100053407A1 (en) Wafer level compliant packages for rear-face illuminated solid state image sensors
JP2012094882A (en) Manufacturing method for wafer-level image sensor module
KR20080074773A (en) Image sensor package with die receiving opening and method of the same
JP2000323614A (en) Image sensor.ball grid array.package and manufacture thereof
KR20160090972A (en) Image sensor package and fabrication method thereof
US20090267209A1 (en) Semiconductor device
WO2023189153A1 (en) Method for manufacturing optical semiconductor package
US7205095B1 (en) Apparatus and method for packaging image sensing semiconductor chips
US7459376B2 (en) Dissociated fabrication of packages and chips of integrated circuits
WO2023112409A1 (en) Optical semiconductor package and method for producing optical semiconductor package
CN219642829U (en) Semiconductor packaging structure
KR20050120359A (en) Package for semiconductor image pickup device and fabricating method thereof

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 23779183

Country of ref document: EP

Kind code of ref document: A1