TW202343818A - Method for manufacturing optical semiconductor package - Google Patents

Method for manufacturing optical semiconductor package Download PDF

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Publication number
TW202343818A
TW202343818A TW112108480A TW112108480A TW202343818A TW 202343818 A TW202343818 A TW 202343818A TW 112108480 A TW112108480 A TW 112108480A TW 112108480 A TW112108480 A TW 112108480A TW 202343818 A TW202343818 A TW 202343818A
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Taiwan
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light
metal
wiring
receiving element
mentioned
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TW112108480A
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Chinese (zh)
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小松竜大
森下勝
井上直
島井信吾
諏訪陽祐
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日商濱松赫德尼古斯股份有限公司
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Publication of TW202343818A publication Critical patent/TW202343818A/en

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/12Mountings, e.g. non-detachable insulating substrates
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144Devices controlled by radiation
    • H01L27/146Imager structures
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04NPICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70SSIS architectures; Circuits associated therewith

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Electromagnetism (AREA)
  • Signal Processing (AREA)
  • Multimedia (AREA)
  • Light Receiving Elements (AREA)
  • Solid State Image Pick-Up Elements (AREA)
  • Transforming Light Signals Into Electric Signals (AREA)

Abstract

This method for manufacturing an optical semiconductor package comprises: a first step for temporarily bonding a light reception element and a first end of a metal pillar to a substrate; a second step for forming on the substrate a mold resin covering the light reception element and the metal pillar; a third step for polishing or grinding the mold resin from the side facing a second surface of the light reception element, to expose the second surface of the light reception element and a second end of the metal pillar; a fourth step for forming a first wiring layer on the second surface of the light reception element and on an end surface of the mold resin; a fifth step for separating the substrate from the light reception element, the metal pillar, and the mold resin; and a sixth step for, after the fifth step, forming a second wiring layer on the side, with respect to the light reception element and the mold resin, opposite to the side on which the first wiring layer is positioned.

Description

光半導體封裝之製造方法Manufacturing method of optical semiconductor packaging

本發明係關於一種光半導體封裝之製造方法。The present invention relates to a manufacturing method of optical semiconductor packaging.

專利文獻1中揭示出包含受光元件之半導體封裝之製造方法。專利文獻1中揭示之製造方法中,於玻璃基板上形成包含柱狀電極之連接用配線,於連接用配線上搭載受光元件(設有光電轉換器件區域(受光部)之矽基板),於受光元件與玻璃基板之間填充包含樹脂之第1密封膜(底部填充膠)之後,進而利用包含樹脂之第2密封膜覆蓋玻璃基板之整個上表面。 先前技術文獻 專利文獻 Patent Document 1 discloses a method for manufacturing a semiconductor package including a light-receiving element. In the manufacturing method disclosed in Patent Document 1, connection wiring including columnar electrodes is formed on a glass substrate, a light-receiving element (a silicon substrate provided with a photoelectric conversion device region (light-receiving part)) is mounted on the connection wiring, and a light-receiving element is mounted on the glass substrate. After the first sealing film (underfill) containing resin is filled between the component and the glass substrate, the entire upper surface of the glass substrate is covered with the second sealing film containing resin. Prior technical literature patent documents

專利文獻1:日本專利第4126389號公報Patent Document 1: Japanese Patent No. 4126389

[發明所欲解決之問題][Problem to be solved by the invention]

上述製造方法中,由於受光部被第1密封膜覆蓋,故而有受光感度降低之虞。又,由於第1密封膜與第2密封膜之界面接觸於連接用配線,故而有因第1密封膜與第2密封膜之間之熱膨脹係數差等引起之應力集中於連接用配線,連接用配線受到損傷之虞。如此,就半導體封裝之可靠性之觀點而言,上述製造方法有改善之餘地。In the above-mentioned manufacturing method, since the light-receiving part is covered with the first sealing film, there is a risk that the light-receiving sensitivity may decrease. In addition, since the interface between the first sealing film and the second sealing film is in contact with the connecting wiring, stress due to a difference in thermal expansion coefficient between the first sealing film and the second sealing film is concentrated on the connecting wiring. The wiring may be damaged. Thus, from the viewpoint of reliability of semiconductor packaging, the above-mentioned manufacturing method has room for improvement.

本發明之目的在於提供一種能夠謀求提高可靠性之光半導體封裝之製造方法。 [解決問題之技術手段] An object of the present invention is to provide a method for manufacturing an optical semiconductor package that can improve reliability. [Technical means to solve problems]

本發明之一態樣之光半導體封裝之製造方法包括:第1步驟,其係將具有設有受光部及與受光部電性連接之電極端子之第1面之受光元件、與柱狀之金屬構件之第1端部暫時接合於基板,且以第1面與基板對向之方式將受光元件暫時接合於基板;第2步驟,其係將覆蓋受光元件及金屬構件之樹脂部形成於基板上;第3步驟,其係藉由從與受光元件之第1面之相反側之第2面對向之側研磨或研削樹脂部,而使受光元件之第2面及金屬構件之第1端部之相反側之第2端部露出;第4步驟,其係於受光元件之第2面上、及與第2面連續之樹脂部之端面上,形成包含與第2端部電性連接之第1金屬配線之第1配線層;第5步驟,其係將基板從受光元件、金屬構件、及樹脂部分離;及第6步驟,其係於第5步驟之後,相對於受光元件及樹脂部在與第1配線層所在之側相反之側,形成包含將第1端部與電極端子電性連接之第2金屬配線之第2配線層。A method for manufacturing an optical semiconductor package according to one aspect of the present invention includes: a first step, which is to combine a light-receiving element with a first surface provided with a light-receiving part and an electrode terminal electrically connected to the light-receiving part, and a columnar metal The first end of the member is temporarily bonded to the substrate, and the light-receiving element is temporarily bonded to the substrate with the first surface facing the substrate; the second step is to form a resin portion covering the light-receiving element and the metal member on the substrate ; The third step is to grind or grind the resin portion from the side facing the second surface opposite to the first surface of the light-receiving element, so that the second surface of the light-receiving element and the first end of the metal member The second end portion on the opposite side is exposed; the fourth step is to form a third end portion electrically connected to the second end portion on the second surface of the light-receiving element and the end surface of the resin portion continuous with the second surface. 1. The first wiring layer of the metal wiring; the fifth step, which is to separate the substrate from the light-receiving element, the metal member, and the resin part; and the sixth step, which is to separate the light-receiving element and the resin part after the fifth step. A second wiring layer including a second metal wiring electrically connecting the first end portion and the electrode terminal is formed on the side opposite to the side where the first wiring layer is located.

上述製造方法中,於第1步驟中,以基板與受光元件之間未形成間隙之方式將受光元件暫時接合於基板。藉此,於第2步驟中,能夠防止樹脂流入至受光元件與基板之間,即於與受光部對向之位置形成樹脂部。結果,能夠避免因受光部被樹脂部覆蓋導致之受光感度之降低。又,在藉由受光元件及金屬構件被暫時接合於基板而各構件穩定地固定之狀態下,能夠穩定且高精度地實施第2步驟。藉由以上,根據上述製造方法,能夠可靠性較高地製造光半導體封裝。In the above manufacturing method, in the first step, the light-receiving element is temporarily bonded to the substrate so that no gap is formed between the substrate and the light-receiving element. Thereby, in the second step, the resin can be prevented from flowing between the light-receiving element and the substrate, that is, the resin portion can be formed at a position facing the light-receiving portion. As a result, it is possible to avoid a decrease in the light receiving sensitivity caused by the light receiving portion being covered with the resin portion. Furthermore, in a state where the light-receiving element and the metal member are temporarily bonded to the substrate and each member is stably fixed, the second step can be performed stably and with high accuracy. As described above, according to the above-mentioned manufacturing method, the optical semiconductor package can be manufactured with high reliability.

第1步驟可包括以下步驟:藉由支持構件,以使第1端部露出之狀態將金屬構件定位並予以支持;及藉由使基板之暫時接合面接觸於被支持在支持構件之金屬構件之第1端部,而將第1端部暫時接合於基板。根據上述構成,藉由使基板之暫時接合面接觸於由支持構件定位及支持之狀態之金屬構件的相對較為簡單之操作,能夠將金屬構件暫時接合於基板。The first step may include the following steps: positioning and supporting the metal member with the first end exposed by the support member; and contacting the temporary joint surface of the substrate with the metal member supported by the support member. The first end portion is temporarily joined to the substrate. According to the above configuration, the metal member can be temporarily joined to the substrate by a relatively simple operation of bringing the temporary joining surface of the substrate into contact with the metal member that is positioned and supported by the supporting member.

支持構件可具有形成有寬度較金屬構件之寬度大之貫通孔之板狀構件、及供載置及支持第2端部之支持基板,金屬構件可插通於板狀構件之貫通孔而定位,並且支持於支持基板,在金屬構件支持於支持構件之狀態下,第1端部可相對於板狀構件而朝與支持基板側相反之側突出。根據上述構成,以金屬構件之第1端部較板狀構件更突出之狀態由支持構件支持金屬構件,因此於使基板之暫時接合面接觸於第1端部時,能夠防止基板之暫時接合面接觸於板狀構件。即,能夠確切地防止基板之暫時接合面貼附於板狀構件。The support member may have a plate-shaped member formed with a through-hole wider than the width of the metal member, and a support base plate for placing and supporting the second end. The metal member may be inserted into the through-hole of the plate-shaped member and positioned. In addition, it is supported on the support base plate, and in a state where the metal member is supported on the support member, the first end can protrude toward the side opposite to the support base plate side with respect to the plate-shaped member. According to the above configuration, the metal member is supported by the supporting member in a state where the first end of the metal member protrudes further than the plate-shaped member. Therefore, when the temporary joining surface of the substrate comes into contact with the first end, it is possible to prevent the temporary joining surface of the substrate from being in contact with the plate-like member. That is, it is possible to reliably prevent the temporary bonding surface of the substrate from adhering to the plate-shaped member.

金屬構件可具有包含第2端部之軸部、及包含第1端部且較軸部更寬幅地形成之凸緣部,支持構件可為形成有寬度大於軸部之寬度且小於凸緣部之寬度之貫通孔之板狀構件,金屬構件可藉由軸部插通於貫通孔且凸緣部之第2端部側之內表面抵接於支持構件之貫通孔之周緣部,而支持於支持構件。根據上述構成,能夠將凸緣部掛在板狀構件之貫通孔之周緣部而支持於此。即,不需要用以支持第2端部之支持基板,因此能夠簡化支持構件。又,藉由設置凸緣部,能夠使豎立設置於基板上之金屬構件之姿勢(垂直性)更穩定。The metal member may have a shaft part including the second end part, and a flange part including the first end part and formed wider than the shaft part, and the support member may be formed with a width larger than the width of the shaft part and smaller than the flange part. For a plate-shaped member with a through-hole of a width, the metal member can be supported by having the shaft inserted into the through-hole and the inner surface of the second end side of the flange being in contact with the peripheral edge of the through-hole of the supporting member. Support components. According to the above configuration, the flange portion can be hung on the peripheral portion of the through hole of the plate-shaped member and supported there. That is, since a support substrate for supporting the second end portion is not required, the support member can be simplified. Furthermore, by providing the flange portion, the posture (verticality) of the metal member erected on the substrate can be further stabilized.

於第4步驟中,可以第1金屬配線中之連接於第2端部之部分之配線寬度大於金屬構件之第2端部之寬度之方式形成第1配線層。根據上述構成,能夠吸收第2步驟(樹脂部形成步驟)中可能會產生之金屬構件之位置偏移。即,藉由增大第1金屬配線之配線寬度,即便於第2步驟中金屬構件之位置有些許偏移,亦能夠使第1金屬配線與金屬構件(第2端部)確實地接觸。In the fourth step, the first wiring layer may be formed such that the wiring width of the portion of the first metal wiring connected to the second end is larger than the width of the second end of the metal member. According to the above structure, it is possible to absorb the positional deviation of the metal member that may occur in the second step (resin portion forming step). That is, by increasing the wiring width of the first metal wiring, even if the position of the metal member is slightly shifted in the second step, the first metal wiring and the metal member (second end portion) can be brought into reliable contact.

於第4步驟中,可以第1金屬配線中之連接於第2端部之部分之配線寬度小於金屬構件之第2端部之寬度之方式形成第1配線層。根據上述構成,能夠不受金屬構件之大小(寬度)之影響地形成第1金屬配線。例如於金屬構件(第2端部)之寬度相對較大之情形時,若使第1金屬配線之寬度較金屬構件之寬度更大,則可能會產生第1金屬配線容易與設置於第1配線層之其他配線相干涉之問題。根據上述構成,能夠避免產生此種問題。In the fourth step, the first wiring layer may be formed such that the wiring width of the portion of the first metal wiring connected to the second end is smaller than the width of the second end of the metal member. According to the above configuration, the first metal wiring can be formed without being affected by the size (width) of the metal member. For example, when the width of the metal member (the second end portion) is relatively large, if the width of the first metal wiring is made larger than the width of the metal member, the first metal wiring may be easily disposed on the first wiring. The problem of interference with other wiring on the layer. According to the above-described configuration, such problems can be avoided.

於第6步驟中,可以第2金屬配線中之連接於第1端部之部分之配線寬度大於金屬構件之第1端部之寬度之方式形成第2配線層。根據上述構成,能夠吸收第2步驟(樹脂部形成步驟)中可能會產生之金屬構件之位置偏移。即,藉由增大第2金屬配線之配線寬度,即便於第2步驟中金屬構件之位置有些許偏移,亦能夠使第2金屬配線與金屬構件(第1端部)更確實地接觸。In the sixth step, the second wiring layer may be formed such that the wiring width of the portion of the second metal wiring connected to the first end is larger than the width of the first end of the metal member. According to the above structure, it is possible to absorb the positional deviation of the metal member that may occur in the second step (resin portion forming step). That is, by increasing the wiring width of the second metal wiring, even if the position of the metal member is slightly shifted in the second step, the second metal wiring can be brought into contact with the metal member (first end portion) more reliably.

於第6步驟中,可以第2金屬配線中之連接於第1端部之部分之配線寬度小於金屬構件之第1端部之寬度之方式形成第2配線層。根據上述構成,不受金屬構件之大小(寬度)之影響地形成第2金屬配線。例如於金屬構件(第1端部)之寬度相對較大之情形時,若使第2金屬配線之寬度較金屬構件之寬度更大,則可能會產生第2金屬配線容易與設置於第2配線層之其他配線相干涉之問題。根據上述構成,能夠避免產生此種問題。In the sixth step, the second wiring layer may be formed such that the wiring width of the portion of the second metal wiring connected to the first end is smaller than the width of the first end of the metal member. According to the above configuration, the second metal wiring is formed without being affected by the size (width) of the metal member. For example, when the width of the metal member (the first end) is relatively large, if the width of the second metal wiring is made larger than the width of the metal member, the second metal wiring may be easily disposed on the second wiring. The problem of interference with other wiring on the layer. According to the above-described configuration, such problems can be avoided.

第5步驟可至少於第3步驟之後實施。又,第4步驟可於第3步驟之後實施,第5步驟可於第4步驟之後實施。根據上述構成,藉由使基板於第3步驟(或者,第3步驟及第4步驟)中亦為安裝狀態,能夠於提高各構件之支持穩定性之狀態下高可靠性地實施第3步驟(或者,第3步驟及第4步驟)。Step 5 may be implemented at least after step 3. In addition, the fourth step can be implemented after the third step, and the fifth step can be implemented after the fourth step. According to the above configuration, by placing the substrate in the mounted state also in the third step (or the third step and the fourth step), the third step (3) can be performed with high reliability while improving the support stability of each member. Or, steps 3 and 4).

受光元件可於第1面具有受光面。根據上述構成,能夠可靠性較高地製造表面入射型之受光元件之表面為第1面之光半導體封裝。The light-receiving element may have a light-receiving surface on the first surface. According to the above structure, an optical semiconductor package in which the surface of the surface-incidence type light-receiving element is the first surface can be manufactured with high reliability.

本發明之另一態樣之光半導體封裝之製造方法包括:第1步驟,其係於基板上形成包含第1金屬配線且設有使基板露出之開口部之第1配線層;第2步驟,其係形成金屬構件,該金屬構件連接於第1金屬配線之第1端部,從第1配線層朝與基板側相反之側突出;第3步驟,其係準備受光元件,該受光元件具有設有受光部及與受光部電性連接之電極端子之第1面;第4步驟,其係以不同於第1端部之第1金屬配線之第2端部與電極端子電性連接,且受光部配置於與開口部對向之位置而於基板與受光元件之間形成有內部空間之方式配置受光元件;第5步驟,其係形成樹脂部,該樹脂部覆蓋受光元件、金屬構件、及第1配線層並且填充至內部空間,具有對於成為受光部之檢測對象之光之透明性;第6步驟,其係藉由從與受光元件之第1面之相反側之第2面對向之側研磨或研削樹脂部,而使第2面及金屬構件之連接於第1金屬配線之側之相反側之端部露出;第7步驟,其係於受光元件之第2面上、及與第2面連續之樹脂部之端面上,形成包含與金屬構件之端部電性連接之第2金屬配線之第2配線層;及第8步驟,其係將基板從第1配線層及樹脂部分離。A method of manufacturing an optical semiconductor package according to another aspect of the present invention includes: a first step, which is to form a first wiring layer on a substrate that includes a first metal wiring and is provided with an opening for exposing the substrate; a second step, In this step, a metal member is formed, which is connected to the first end of the first metal wiring and protrudes from the first wiring layer toward the side opposite to the substrate side; in the third step, a light-receiving element is prepared, and the light-receiving element has a device There is a light-receiving part and a first surface of an electrode terminal electrically connected to the light-receiving part; in the fourth step, a second end of a first metal wiring different from the first end is electrically connected to the electrode terminal and receives light The light-receiving element is arranged in a position opposite to the opening and an internal space is formed between the substrate and the light-receiving element; the fifth step is to form a resin part that covers the light-receiving element, the metal member, and the third 1. The wiring layer is filled into the internal space and has transparency with respect to the light that becomes the detection target of the light-receiving part; the 6th step is to pass the second surface from the side opposite to the first surface of the light-receiving element. Grind or grind the resin part to expose the second surface and the end of the metal member on the opposite side to the side connected to the first metal wiring; in the seventh step, it is connected to the second surface of the light-receiving element and the second surface of the light-receiving element. On the end surface of the continuous resin part, a second wiring layer including a second metal wiring electrically connected to the end of the metal member is formed; and the eighth step is to separate the substrate from the first wiring layer and the resin part.

上述製造方法中,在第5步驟中藉由將樹脂部填充至受光元件與基板之間之內部空間而樹脂部覆蓋受光部,但由於樹脂部具有對於成為受光部之檢測對象之光之透明性,故而能抑制因樹脂部覆蓋受光部導致之受光感度之降低。進而,於第5步驟中,能夠藉由單一之樹脂材料一次性形成填充至受光元件與基板之間之內部空間且覆蓋各構件(受光元件、金屬構件、及第1配線層)之樹脂部。藉此,能夠避免因2種樹脂部(例如,由互不相同之材料形成或於不同時點形成之2個樹脂部)混合存在而導致之可靠性降低(例如,因2個樹脂部之熱膨脹係數差等引起之應力導致的金屬配線之損傷等)。藉由以上,根據上述製造方法,能夠可靠性較高地製造光半導體封裝。In the above-mentioned manufacturing method, in the fifth step, the resin part covers the light-receiving part by filling the internal space between the light-receiving element and the substrate. However, the resin part has transparency to the light that is the detection target of the light-receiving part. , therefore it is possible to suppress the decrease in light receiving sensitivity caused by the resin part covering the light receiving part. Furthermore, in the fifth step, the resin portion that fills the internal space between the light-receiving element and the substrate and covers each member (the light-receiving element, the metal member, and the first wiring layer) can be formed at once from a single resin material. Thereby, it is possible to avoid a decrease in reliability caused by the mixing of two types of resin parts (for example, two resin parts formed of different materials or formed at different points in time) (for example, due to the thermal expansion coefficient of the two resin parts). Damage to metal wiring caused by stress caused by differences, etc.). As described above, according to the above-mentioned manufacturing method, the optical semiconductor package can be manufactured with high reliability.

第8步驟可至少於第6步驟之後實施。又,第7步驟可於第6步驟之後實施,第8步驟可於第7步驟之後實施。根據上述構成,藉由使基板於第6步驟(或者,第6步驟及第7步驟)中亦為安裝狀態,能夠於提高各構件之支持穩定性之狀態下高可靠性地實施第6步驟(或者,第6步驟及第7步驟)。Step 8 may be implemented at least after step 6. In addition, step 7 can be implemented after step 6, and step 8 can be implemented after step 7. According to the above configuration, by placing the substrate in the mounted state also in the sixth step (or the sixth step and the seventh step), the sixth step (6) can be performed with high reliability while improving the support stability of each member. Or, steps 6 and 7).

受光元件可於第1面具有受光面。根據上述構成,能夠可靠性較高地製造表面入射型之受光元件之表面為第1面之光半導體封裝。 [發明之效果] The light-receiving element may have a light-receiving surface on the first surface. According to the above structure, an optical semiconductor package in which the surface of the surface-incidence type light-receiving element is the first surface can be manufactured with high reliability. [Effects of the invention]

根據本發明,可提供能夠謀求提高可靠性之光半導體封裝之製造方法。According to the present invention, a method for manufacturing an optical semiconductor package capable of improving reliability can be provided.

以下,參照附圖對本發明之實施方式進行說明。各圖中對相同或相當之部分標註相同符號,並省略重複說明。再者,於附圖中,存在為了便於理解地說明實施方式之特徵部分而加以放大之部分。因此,附圖之尺寸比率有時與實際之尺寸比率不同。Hereinafter, embodiments of the present invention will be described with reference to the drawings. In each figure, the same or equivalent parts are marked with the same symbols, and repeated explanations are omitted. In addition, in the drawings, there are some parts that are enlarged in order to explain the characteristic parts of the embodiment for easy understanding. Therefore, the dimensional ratios in the drawings may differ from the actual dimensional ratios.

[第1實施方式] (光半導體封裝之構造) 如圖1所示,第1實施方式之光半導體封裝1A具有受光元件2、塑模樹脂3(樹脂部)、配線層4(第1配線層)、配線層5(第2配線層)、及金屬柱6(金屬構件)。光半導體封裝1A係FOWLP(Fan Out Wafer Level Package,扇出型晶圓級封裝)/FOPLP(Fan Out Panel Level Package,扇出型面板級封裝)之一種。 [First Embodiment] (Structure of optical semiconductor package) As shown in FIG. 1 , the optical semiconductor package 1A of the first embodiment includes a light-receiving element 2, a mold resin 3 (resin part), a wiring layer 4 (a first wiring layer), a wiring layer 5 (a second wiring layer), and Metal pillar 6 (metal member). Optical semiconductor package 1A is one of FOWLP (Fan Out Wafer Level Package)/FOPLP (Fan Out Panel Level Package).

受光元件2係具有受光部21之半導體晶片,形成為矩形板狀。受光元件2具有第1面2a、及第2面2b。於圖1中,將第1面2a與第2面2b對向之對向方向表示為Z軸方向,將從Z軸方向觀察時沿著受光元件2之一邊之方向表示為X軸方向,將從Z軸方向觀察時沿著受光元件2之另一邊(與上述一邊垂直之邊)之方向表示為Y軸方向。The light-receiving element 2 is a semiconductor chip having a light-receiving portion 21 and is formed in a rectangular plate shape. The light-receiving element 2 has a first surface 2a and a second surface 2b. In FIG. 1 , the opposing direction between the first surface 2 a and the second surface 2 b is represented as the Z-axis direction, the direction along one side of the light-receiving element 2 when viewed from the Z-axis direction is represented as the X-axis direction, and The direction along the other side of the light-receiving element 2 (the side perpendicular to the above-mentioned side) when viewed from the Z-axis direction is represented as the Y-axis direction.

於第1面2a,設有受光部21、及與受光部21電性連接之複數個(本實施方式中為2個)電極端子22。本實施方式中,作為一例,於從Z軸方向觀察時之第1面2a之大致中央部設有1個受光部21,但亦可於第1面2a設有複數個受光部21。於該情形時,複數個受光部21例如於從Z軸方向觀察之情形時,可一維或二維排列。受光部21配置於沿著第1面之位置。即,受光元件2於第1面2a具有受光面。更具體而言,第1面2a中之與受光部21對向之部分作為受光面發揮功能。圖1之例中,受光部21係以受光部21之光入射面(第1面2a側之面)與第1面2a為大致同一平面之方式埋設於受光元件2中。作為受光部21之例,可列舉Si光電二極體(SiPD)、Si雪崩光電二極體(SiAPD)、Si-MPPC(Multi-Pixel Photon Counter,多像素光子計數器)等。2個電極端子22於第1面2a上以突出之方式設置。The first surface 2a is provided with a light-receiving part 21 and a plurality of (two in this embodiment) electrode terminals 22 electrically connected to the light-receiving part 21. In this embodiment, as an example, one light receiving part 21 is provided at substantially the center of the first surface 2a when viewed from the Z-axis direction, but a plurality of light receiving parts 21 may be provided on the first surface 2a. In this case, the plurality of light receiving portions 21 may be arranged one-dimensionally or two-dimensionally when viewed from the Z-axis direction. The light-receiving part 21 is arrange|positioned along the 1st surface. That is, the light-receiving element 2 has a light-receiving surface on the first surface 2a. More specifically, a portion of the first surface 2 a facing the light receiving portion 21 functions as a light receiving surface. In the example of FIG. 1 , the light-receiving part 21 is embedded in the light-receiving element 2 so that the light incident surface of the light-receiving part 21 (surface on the first surface 2 a side) and the first surface 2 a are substantially the same plane. Examples of the light receiving portion 21 include Si photodiodes (SiPD), Si avalanche photodiodes (SiAPD), Si-MPPC (Multi-Pixel Photon Counter, multi-pixel photon counter), and the like. Two electrode terminals 22 are provided in a protruding manner on the first surface 2a.

於第1面2a上設有絕緣層23。絕緣層23以包圍設置於第1面2a上之複數個(本實施方式中為2個)電極端子22之方式設置。於絕緣層23形成有用以使各電極端子22露出之開口23a。絕緣層23可由例如二氧化矽(SiO 2)、氮化矽(Si 3N 4)等之無機膜、或者聚醯亞胺等之有機膜形成。 An insulating layer 23 is provided on the first surface 2a. The insulating layer 23 is provided to surround a plurality of (two in this embodiment) electrode terminals 22 provided on the first surface 2a. The insulating layer 23 is formed with an opening 23 a for exposing each electrode terminal 22 . The insulating layer 23 may be formed of an inorganic film such as silicon dioxide (SiO 2 ) or silicon nitride (Si 3 N 4 ), or an organic film such as polyimide.

於從Z軸方向觀察之情形時,塑模樹脂3係以包圍受光元件2之方式將受光元件2之側面密封。塑模樹脂3亦覆蓋金屬柱6。塑模樹脂3可由例如環氧樹脂等形成。塑模樹脂3具有與絕緣層23之表面形成為同一平面之端面3a、及與受光元件2之第2面2b形成為同一平面之端面3b。When viewed from the Z-axis direction, the molding resin 3 seals the side surfaces of the light-receiving element 2 so as to surround the light-receiving element 2 . The molding resin 3 also covers the metal pillar 6 . The mold resin 3 may be formed of, for example, epoxy resin or the like. The mold resin 3 has an end surface 3 a formed in the same plane as the surface of the insulating layer 23 , and an end surface 3 b formed in the same plane as the second surface 2 b of the light receiving element 2 .

配線層4在受光元件2之第2面2b側,設置於受光元件2之第2面2b上、及與第2面2b連續之塑模樹脂3之端面3b上。配線層4係包含絕緣層41、及金屬配線42(第1金屬配線)而構成之再配線層。絕緣層41可由例如二氧化矽(SiO 2)、氮化矽(Si 3N 4)等之無機膜、或者聚醯亞胺等之有機膜形成。金屬配線42例如為銅(Cu)配線。 The wiring layer 4 is provided on the second surface 2b side of the light-receiving element 2 and on the end surface 3b of the molding resin 3 that is continuous with the second surface 2b. The wiring layer 4 is a rewiring layer including an insulating layer 41 and a metal wiring 42 (first metal wiring). The insulating layer 41 may be formed of an inorganic film such as silicon dioxide (SiO 2 ) or silicon nitride (Si 3 N 4 ), or an organic film such as polyimide. The metal wiring 42 is, for example, copper (Cu) wiring.

於絕緣層41中之在Z軸方向上與金屬柱6重疊之部分設有開口41a。於開口41a內設有與金屬柱6之配線層4側之端部6b(第2端部)電性連接之金屬配線42。開口41a之寬度被設定為大於金屬柱6之端部6b之寬度。藉此,金屬配線42中之連接於端部6b之部分之配線寬度w11,大於金屬柱6之端部6b之寬度w12。An opening 41 a is provided in a portion of the insulating layer 41 that overlaps the metal pillar 6 in the Z-axis direction. A metal wiring 42 electrically connected to the end 6b (second end) of the metal pillar 6 on the wiring layer 4 side is provided in the opening 41a. The width of the opening 41a is set larger than the width of the end portion 6b of the metal pillar 6. Thereby, the wiring width w11 of the portion of the metal wiring 42 connected to the end portion 6 b is larger than the width w12 of the end portion 6 b of the metal pillar 6 .

於金屬配線42之外側端部(在Z軸方向上位於與金屬柱6相反之側之端部)設有鍍覆部43。鍍覆部43例如為藉由焊料等而接合於印刷基板等之部分。鍍覆部43例如為鎳及金之雙層鍍層(Ni/Au鍍層)。A plated portion 43 is provided at the outer end of the metal wiring 42 (the end located on the opposite side to the metal pillar 6 in the Z-axis direction). The plated portion 43 is a portion joined to a printed circuit board or the like by solder or the like, for example. The plated portion 43 is, for example, a double-layer plating of nickel and gold (Ni/Au plating).

配線層5相對於受光元件2及塑模樹脂3而設置在與配線層4所在之側相反之側。即,配線層5在受光元件2之第1面2a側,設置於絕緣層23上及塑模樹脂3之端面3a上。配線層5係包含絕緣層51、及金屬配線52(第2金屬配線)而構成之再配線層。絕緣層51可由例如二氧化矽(SiO 2)、氮化矽(Si 3N 4)等之無機膜、或者聚醯亞胺等之有機膜形成。金屬配線52例如為銅(Cu)配線。 The wiring layer 5 is provided on the side opposite to the side where the wiring layer 4 is located with respect to the light receiving element 2 and the mold resin 3 . That is, the wiring layer 5 is provided on the insulating layer 23 and the end surface 3a of the molding resin 3 on the first surface 2a side of the light receiving element 2. The wiring layer 5 is a rewiring layer including an insulating layer 51 and a metal wiring 52 (second metal wiring). The insulating layer 51 may be formed of an inorganic film such as silicon dioxide (SiO 2 ) or silicon nitride (Si 3 N 4 ), or an organic film such as polyimide. The metal wiring 52 is, for example, copper (Cu) wiring.

在絕緣層51中之於Z軸方向上與金屬柱6重疊之部分設有開口51a。於開口51a內設有與金屬柱6之配線層5側之端部6a(第1端部)電性連接之金屬配線52。開口51a之寬度被設定為大於金屬柱6之端部6a之寬度。藉此,金屬配線52中之連接於端部6a之部分之配線寬度w21,大於金屬柱6之端部6a之寬度w22。An opening 51 a is provided in a portion of the insulating layer 51 that overlaps the metal pillar 6 in the Z-axis direction. A metal wiring 52 electrically connected to the end 6 a (first end) of the metal pillar 6 on the wiring layer 5 side is provided in the opening 51 a. The width of the opening 51a is set larger than the width of the end portion 6a of the metal pillar 6. Thereby, the wiring width w21 of the portion of the metal wiring 52 connected to the end portion 6a is larger than the width w22 of the end portion 6a of the metal pillar 6 .

在絕緣層51中之於Z軸方向上與受光部21重疊之部分設有開口部51b。即,絕緣層51以於Z軸方向上不覆蓋受光部21之方式形成。An opening 51 b is provided in a portion of the insulating layer 51 that overlaps the light receiving portion 21 in the Z-axis direction. That is, the insulating layer 51 is formed so as not to cover the light receiving portion 21 in the Z-axis direction.

金屬配線52將金屬柱6之端部6a與受光元件2之電極端子22電性連接。即,受光元件2(電極端子22)經由金屬配線52、金屬柱6、及金屬配線42而與鍍覆部43電性連接。The metal wiring 52 electrically connects the end portion 6 a of the metal pillar 6 and the electrode terminal 22 of the light-receiving element 2 . That is, the light-receiving element 2 (electrode terminal 22) is electrically connected to the plated portion 43 via the metal wiring 52, the metal pillar 6, and the metal wiring 42.

金屬柱6係形成為柱狀之金屬構件。金屬柱6由例如銅形成。金屬柱6例如為所謂的銅柱或銅桿。The metal pillar 6 is a metal member formed into a columnar shape. The metal pillar 6 is formed of copper, for example. The metal pillar 6 is, for example, a so-called copper pillar or copper rod.

本實施方式中,電極端子22、金屬配線52、金屬柱6、及金屬配線42分別各設有2個。更具體而言,於從Y軸方向觀察之情形時,相互電性連接之電極端子22、金屬配線52、金屬柱6、及金屬配線42之組分別設置於受光部21之兩側。再者,於如上所述般設有複數個受光部21之情形時,電極端子22之數量(即,上述組之數量)可根據受光部21之數量而變動。In this embodiment, two electrode terminals 22 , metal wirings 52 , metal posts 6 , and metal wirings 42 are provided each. More specifically, when viewed from the Y-axis direction, a group of electrode terminals 22 , metal wires 52 , metal posts 6 , and metal wires 42 that are electrically connected to each other are respectively provided on both sides of the light receiving portion 21 . Furthermore, when a plurality of light receiving portions 21 are provided as described above, the number of electrode terminals 22 (that is, the number of the groups) can be changed according to the number of light receiving portions 21 .

(光半導體封裝之製造方法) 參照圖2至圖7對光半導體封裝1A之製造步驟之一例進行說明。本實施方式中,光半導體封裝1A藉由CoW(Chip on Wafer,晶圓上晶片)方式或CoP(Chip on Panel,面板上晶片)方式而製造。 (Manufacturing method of optical semiconductor package) An example of the manufacturing steps of the optical semiconductor package 1A will be described with reference to FIGS. 2 to 7 . In this embodiment, the optical semiconductor package 1A is manufactured by the CoW (Chip on Wafer, chip on wafer) method or the CoP (Chip on Panel, chip on panel) method.

首先,如圖2所示,受光元件2與金屬柱6之端部6a暫時接合於作為暫時接合構件之基板50之暫時接合面50a(例如塗佈有暫時接合用之接著劑之面)(第1步驟)。即,受光元件2及金屬柱6以之後能夠拆卸之態樣暫時接合於基板50。受光元件2以第1面2a與基板50對向之方式暫時接合於基板50。本實施方式中,設置於受光元件2之第1面2a上之絕緣層23暫時接合於基板50。First, as shown in FIG. 2 , the end portion 6 a of the light-receiving element 2 and the metal pillar 6 is temporarily joined to the temporary joining surface 50 a of the substrate 50 as a temporary joining member (for example, the surface coated with an adhesive for temporary joining) (Sec. 1 step). That is, the light-receiving element 2 and the metal pillar 6 are temporarily bonded to the substrate 50 in a manner that they can be detached later. The light-receiving element 2 is temporarily bonded to the substrate 50 so that the first surface 2 a faces the substrate 50 . In this embodiment, the insulating layer 23 provided on the first surface 2 a of the light-receiving element 2 is temporarily bonded to the substrate 50 .

基板50例如為矽晶圓、玻璃晶圓、SUS載具等。於基板上,與1個光半導體封裝1A對應之單位區域以格子狀(二維狀)排列形成有複數個。圖2至圖7表示各製造步驟中之1個單位區域之狀態。The substrate 50 is, for example, a silicon wafer, a glass wafer, a SUS carrier, or the like. On the substrate, a plurality of unit areas corresponding to one optical semiconductor package 1A are arranged in a grid shape (two-dimensional shape). 2 to 7 show the state of one unit area in each manufacturing step.

參照圖3,對將金屬柱6暫時接合於基板50之方法之一例進行說明。此例中,使用支持構件100,該支持構件100以使複數個(單位區域數×各單位區域中所含之金屬柱數)金屬柱6之端部6a露出之狀態將各金屬柱6定位。具體而言,第1步驟中將金屬柱6暫時接合於基板50之步驟包括以下步驟:藉由支持構件100,以使金屬柱6之端部6a露出之狀態將金屬柱6定位並予以支持;及藉由使基板50之暫時接合面50a接觸於支持在支持構件100之金屬柱6之端部6a,而將金屬柱6之端部6a暫時接合於基板50。根據上述構成,藉由使基板50之暫時接合面50a接觸於由支持構件100定位及支持之狀態之金屬柱6的相對較為簡單之操作,能夠將金屬柱6暫時接合於基板50。Referring to FIG. 3 , an example of a method of temporarily joining the metal pillar 6 to the substrate 50 will be described. In this example, a support member 100 is used that positions each metal pillar 6 in a state in which the end portion 6 a of a plurality of (number of unit areas × number of metal pillars included in each unit area) metal pillars 6 is exposed. Specifically, the step of temporarily joining the metal pillar 6 to the substrate 50 in the first step includes the following steps: positioning and supporting the metal pillar 6 with the end 6a of the metal pillar 6 exposed by the supporting member 100; And by bringing the temporary joint surface 50a of the substrate 50 into contact with the end 6a of the metal column 6 supported on the support member 100, the end 6a of the metal column 6 is temporarily joined to the substrate 50. According to the above configuration, the metal pillar 6 can be temporarily bonded to the substrate 50 by a relatively simple operation of bringing the temporary bonding surface 50 a of the substrate 50 into contact with the metal pillar 6 that is positioned and supported by the support member 100 .

首先,如圖3之(A)所示,藉由支持構件100而以使金屬柱6之端部6a露出之狀態定位且支持金屬柱6。此例中,支持構件100具有形成有寬度大於金屬柱6之寬度之貫通孔101a之板狀構件101、及供載置及支持金屬柱6之端部6b之支持基板102。再者,貫通孔101a之大小被調整為以下之大小:能夠插入金屬柱6,且能夠將金屬柱6之橫向之位置偏移收斂在容許誤差範圍內。各金屬柱6插通於板狀構件101之貫通孔101a而被定位,並且支持於支持基板102。在金屬柱6支持於支持構件100之狀態下,端部6a相對於板狀構件101而朝與支持基板102側相反之側突出。再者,板狀構件101與支持基板102既可如圖3所示分開地形成,亦可一體地形成。又,於板狀構件101與支持基板102之間,既可如圖3所示設有空間(間隙),亦可不設置此種空間。First, as shown in FIG. 3(A) , the metal pillar 6 is positioned and supported by the support member 100 in a state in which the end portion 6 a of the metal pillar 6 is exposed. In this example, the support member 100 has a plate-shaped member 101 formed with a through hole 101 a wider than the width of the metal pillar 6 , and a support substrate 102 for placing and supporting the end portion 6 b of the metal pillar 6 . Furthermore, the size of the through hole 101a is adjusted to a size that can insert the metal pillar 6 and keep the lateral positional deviation of the metal pillar 6 within an allowable error range. Each metal pillar 6 is inserted into the through hole 101 a of the plate-shaped member 101 to be positioned, and is supported by the support substrate 102 . In a state where the metal pillar 6 is supported by the support member 100, the end portion 6a protrudes toward the side opposite to the support substrate 102 side with respect to the plate-shaped member 101. In addition, the plate-shaped member 101 and the support substrate 102 may be formed separately as shown in FIG. 3 , or may be formed integrally. In addition, as shown in FIG. 3 , a space (gap) may be provided between the plate-shaped member 101 and the supporting substrate 102 , or such a space may not be provided.

繼而,如圖3之(B)所示,基板50之暫時接合面50a接觸於支持在支持構件100之金屬柱6之端部6a。藉此,如圖3之(C)所示,金屬柱6之端部6a暫時接合於基板50之暫時接合面50a。Then, as shown in FIG. 3(B) , the temporary joint surface 50a of the substrate 50 comes into contact with the end portion 6a of the metal pillar 6 supported on the supporting member 100. Thereby, as shown in FIG. 3(C) , the end portion 6a of the metal pillar 6 is temporarily joined to the temporary joining surface 50a of the substrate 50.

根據上述構成,以金屬柱6之端部6a較板狀構件101更突出之狀態由支持構件100支持金屬柱6,因此,於使基板50之暫時接合面50a接觸於端部6a時,能夠防止基板50之暫時接合面50a接觸於板狀構件101。即,能夠確切地防止基板50之暫時接合面50a貼附於板狀構件101。According to the above configuration, the metal pillar 6 is supported by the support member 100 in a state where the end portion 6a of the metal pillar 6 protrudes further than the plate-shaped member 101. Therefore, when the temporary joint surface 50a of the substrate 50 is brought into contact with the end portion 6a, it is possible to prevent The temporary bonding surface 50a of the substrate 50 is in contact with the plate-shaped member 101. That is, it is possible to reliably prevent the temporary bonding surface 50 a of the substrate 50 from adhering to the plate-shaped member 101 .

此處,亦可如圖4所示,代替金屬柱6而使用具有凸緣部62之金屬柱6A。金屬柱6A具有包含端部6b之軸部61、及包含端部6a且較軸部61更寬幅地形成之凸緣部62。凸緣部62係在端部6a沿著與軸部61之軸方向正交之方向朝外側延伸之部分。從軸方向觀察之凸緣部62之形狀例如為圓形狀。板狀構件101之貫通孔101a被設定為具有較軸部61之寬度大且較凸緣部62之寬度小的寬度。金屬柱6A藉由軸部61插通於貫通孔101a且凸緣部62之端部6b側之內表面62a抵接於板狀構件101之貫通孔101a之周緣部,而支持於板狀構件101。於該狀態下,藉由使基板50之暫時接合面50a接觸於金屬柱6A之端部6a,能夠將金屬柱6A之端部6a暫時接合於基板50。根據上述構成,能夠將凸緣部62掛在板狀構件101之貫通孔101a之周緣部而支持於此,因此,無需用以支持端部6b之支持基板102。結果,能夠簡化支持構件100。又,藉由設置凸緣部62,能夠使豎立設置於基板50上之金屬柱6A之姿勢(垂直性)更穩定。Here, as shown in FIG. 4 , a metal pillar 6A having a flange portion 62 may be used instead of the metal pillar 6 . The metal pillar 6A has a shaft part 61 including the end part 6b, and a flange part 62 including the end part 6a and formed wider than the shaft part 61. The flange portion 62 is a portion of the end portion 6 a extending outward in a direction orthogonal to the axial direction of the shaft portion 61 . The shape of the flange portion 62 viewed from the axial direction is, for example, a circular shape. The through hole 101 a of the plate-shaped member 101 is set to have a width larger than the width of the shaft portion 61 and smaller than the width of the flange portion 62 . The metal pillar 6A is supported on the plate-shaped member 101 by inserting the shaft portion 61 into the through-hole 101a and having the inner surface 62a of the end portion 6b side of the flange portion 62 in contact with the peripheral edge of the through-hole 101a of the plate-shaped member 101. . In this state, by bringing the temporary bonding surface 50a of the substrate 50 into contact with the end portion 6a of the metal pillar 6A, the end portion 6a of the metal pillar 6A can be temporarily bonded to the substrate 50. According to the above configuration, the flange portion 62 can be hung on the peripheral portion of the through hole 101a of the plate-shaped member 101 and supported there. Therefore, the support substrate 102 for supporting the end portion 6b is unnecessary. As a result, the support member 100 can be simplified. In addition, by providing the flange portion 62, the posture (verticality) of the metal pillar 6A erected on the substrate 50 can be further stabilized.

但,於基板50形成金屬柱6之方法並不限於上述。例如,可藉由利用以能夠移載金屬柱6之方式構成之移載裝置將金屬柱6移載至基板50上之指定位置,而於基板50上形成金屬柱6。根據上述方法,藉由控制移載裝置,能夠於基板50上之任意位置高精度地配置金屬柱6。又,亦可藉由實施用以於基板50上形成金屬圖案(金屬柱6)之半導體前步驟(晶種層形成、光微影、電解鍍Cu、抗蝕劑去除、晶種層蝕刻等),而於基板50上形成金屬柱6。藉由上述方法,亦能夠高精度地控制金屬柱6之圖案(位置及形狀)。或者,可藉由在基板50上形成金屬墊,以於該金屬墊上形成垂直地延伸之金屬線之方式實施打線接合,並將接合於金屬墊上之金屬線按適當之長度切斷,而形成金屬柱6(即,金屬墊與金屬線之組合構造)。根據上述方法,能夠藉由調整接合條件(參數)而形成任意直徑及長度之金屬線(金屬柱6)。However, the method of forming the metal pillars 6 on the substrate 50 is not limited to the above. For example, the metal pillars 6 can be formed on the substrate 50 by transferring the metal pillars 6 to a designated position on the substrate 50 using a transfer device configured to be able to transfer the metal pillars 6 . According to the above method, by controlling the transfer device, the metal pillar 6 can be placed at any position on the substrate 50 with high precision. Alternatively, the pre-semiconductor steps (seed layer formation, photolithography, electrolytic Cu plating, resist removal, seed layer etching, etc.) for forming the metal pattern (metal pillar 6) on the substrate 50 can also be performed. , and the metal pillars 6 are formed on the substrate 50 . Through the above method, the pattern (position and shape) of the metal pillar 6 can also be controlled with high precision. Alternatively, wire bonding can be performed by forming a metal pad on the substrate 50, forming a vertically extending metal line on the metal pad, and cutting the metal line bonded to the metal pad to an appropriate length to form a metal Pillar 6 (that is, the combined structure of metal pads and metal wires). According to the above method, a metal wire (metal pillar 6) of any diameter and length can be formed by adjusting the bonding conditions (parameters).

繼而,如圖5之(A)所示,將覆蓋配置在各單位區域之受光元件2及金屬柱6之塑模樹脂3形成於基板50上(第2步驟)。著眼於1個單位區域,塑模樹脂3係以覆蓋受光元件2之第2面2b及側面,且覆蓋各金屬柱6之除端部6a以外之部分(端部6b及側面)之整體之方式形成。Next, as shown in FIG. 5(A) , the molding resin 3 covering the light-receiving element 2 and the metal pillar 6 arranged in each unit area is formed on the substrate 50 (second step). Focusing on one unit area, the molding resin 3 covers the second surface 2b and side surfaces of the light-receiving element 2 and covers the entire portion of each metal pillar 6 except the end portion 6a (the end portion 6b and the side surface). form.

繼而,如圖5之(B)所示,藉由從與受光元件2之第2面2b對向之側(即,端面3b側)研磨或研削塑模樹脂3,而使受光元件2之第2面2b與金屬柱6之端部6b露出(第3步驟)。所謂「研磨或研削」,包括僅實施研磨及研削中之一者之情形,並且亦包括實施研磨及研削之兩者之情形。此時,於各單位區域中,受光元件2之第2面2b亦可與塑模樹脂3之端面3b一起被研磨或研削。同樣,金屬柱6之端部6b亦可被研磨或研削。亦即,可藉由塑模樹脂3之端面3b之研磨或研削而使各單位區域之受光元件2之第2面2b或金屬柱6之端部6b露出之後,進而繼續進行將塑模樹脂3之端面3b與第2面2b或端部6b一起進行研磨或研削之處理。結果,如圖5之(B)所示成為以下狀態:受光元件2薄型化,並且受光元件2之第2面2b及金屬柱6之端部6b露出於外部。藉由以上之處理,受光元件2之第2面2b、金屬柱6之端部6b、及塑模樹脂3之端面3b成為大致同一平面。Next, as shown in FIG. 5(B) , by grinding or grinding the molding resin 3 from the side opposite to the second surface 2b of the light-receiving element 2 (that is, the end surface 3b side), the second surface of the light-receiving element 2 is The surface 2b and the end 6b of the metal pillar 6 are exposed (step 3). The term "grinding or grinding" includes situations where only one of grinding and grinding is performed, and also includes situations where both grinding and grinding are performed. At this time, in each unit area, the second surface 2b of the light-receiving element 2 may also be ground or ground together with the end surface 3b of the molding resin 3. Similarly, the end 6b of the metal pillar 6 can also be ground or ground. That is, after the second surface 2b of the light-receiving element 2 or the end 6b of the metal pillar 6 in each unit area is exposed by grinding or grinding the end surface 3b of the molding resin 3, the molding resin 3 can be continued to be exposed. The end surface 3b is ground or ground together with the second surface 2b or the end 6b. As a result, as shown in FIG. 5(B) , the light-receiving element 2 is reduced in thickness, and the second surface 2 b of the light-receiving element 2 and the end portion 6 b of the metal pillar 6 are exposed to the outside. Through the above processing, the second surface 2b of the light-receiving element 2, the end portion 6b of the metal pillar 6, and the end surface 3b of the molding resin 3 become substantially the same plane.

繼而,如圖6之(A)所示,於受光元件2之第2面2b上、及與第2面2b連續之塑模樹脂3之端面3b上形成配線層4。本實施方式中,於受光元件2之第2面2b、金屬柱6之端部6b、及塑模樹脂3之端面3b上形成絕緣層41及金屬配線42。Then, as shown in FIG. 6(A) , the wiring layer 4 is formed on the second surface 2b of the light-receiving element 2 and on the end surface 3b of the molding resin 3 that is continuous with the second surface 2b. In this embodiment, the insulating layer 41 and the metal wiring 42 are formed on the second surface 2b of the light-receiving element 2, the end portion 6b of the metal pillar 6, and the end surface 3b of the molding resin 3.

例如,從圖5之(B)所示之狀態,藉由採用半導體製程(晶種層形成、光微影、電解鍍覆等)進行絕緣層41之圖案化及金屬配線42之圖案形成,可獲得圖6之(A)所示之構造。配線層4以金屬配線42中之連接於端部6b之部分之配線寬度大於端部6b之寬度之方式形成。更具體而言,絕緣層41之開口41a之寬度形成得大於金屬柱6之端部6b之寬度。藉此,金屬配線42中之連接於端部6b之部分之配線寬度w11(參照圖1)形成得大於金屬柱6之端部6b之寬度w12(參照圖1)。根據上述構成,能夠吸收第2步驟(形成塑模樹脂3之步驟)中可能會產生之金屬柱6之位置偏移。即,藉由增大金屬配線42之配線寬度,即便因第2步驟中之塑模樹脂3之流入而使金屬柱6之位置有些許偏移,亦能夠使金屬配線42與金屬柱6(端部6b)更確實地接觸。For example, from the state shown in FIG. 5(B) , by using a semiconductor process (seed layer formation, photolithography, electrolytic plating, etc.) to pattern the insulating layer 41 and pattern the metal wiring 42, it is possible to The structure shown in (A) of Figure 6 is obtained. The wiring layer 4 is formed such that the wiring width of the portion of the metal wiring 42 connected to the end portion 6 b is larger than the width of the end portion 6 b. More specifically, the width of the opening 41 a of the insulating layer 41 is formed larger than the width of the end portion 6 b of the metal pillar 6 . Thereby, the wiring width w11 (see FIG. 1 ) of the portion of the metal wiring 42 connected to the end 6 b is formed larger than the width w12 (see FIG. 1 ) of the end 6 b of the metal pillar 6 . According to the above structure, the positional deviation of the metal pillar 6 that may occur in the second step (the step of forming the mold resin 3) can be absorbed. That is, by increasing the wiring width of the metal wiring 42, even if the position of the metal pillar 6 is slightly shifted due to the inflow of the molding resin 3 in the second step, the metal wiring 42 can be aligned with the metal pillar 6 (end Part 6b) for more reliable contact.

再者,亦可與上述相反地,以金屬配線42中之連接於端部6b之部分之配線寬度小於金屬柱6之端部6b之寬度之方式形成配線層4(參照下述第2實施方式)。於該情形時,能夠不受金屬柱6之大小(寬度)之影響地形成金屬配線42。例如於金屬柱6(端部6b)之寬度相對較大之情形時,若使金屬配線42之寬度較金屬柱6之寬度更大,則可能會產生金屬配線42容易與設置於配線層4之其他配線相干涉之問題。根據上述構成,能夠避免產生此種問題。Furthermore, contrary to the above, the wiring layer 4 may be formed such that the wiring width of the portion of the metal wiring 42 connected to the end portion 6b is smaller than the width of the end portion 6b of the metal pillar 6 (refer to the second embodiment below). ). In this case, the metal wiring 42 can be formed without being affected by the size (width) of the metal pillar 6 . For example, when the width of the metal pillar 6 (end portion 6b) is relatively large, if the width of the metal wiring 42 is made larger than the width of the metal pillar 6, the metal wiring 42 may easily interfere with the wiring layer 4. Other wiring interference problems. According to the above-described configuration, such problems can be avoided.

繼而,如圖6之(B)所示,將基板50從受光元件2、金屬柱6、及塑模樹脂3分離(第5步驟)。又,將加工面(加工對象之面)從受光元件2之第2面2b側之面變更為受光元件2之第1面2a側之面(即,基板50分離後露出之面)。Next, as shown in FIG. 6(B) , the substrate 50 is separated from the light-receiving element 2, the metal pillar 6, and the molding resin 3 (the fifth step). Furthermore, the processing surface (surface to be processed) is changed from the surface on the second surface 2b side of the light-receiving element 2 to the surface on the first surface 2a side of the light-receiving element 2 (that is, the surface exposed after the substrate 50 is separated).

繼而,於如上所述般將基板50從受光元件2、金屬柱6、及塑模樹脂3分離之後(即,第5步驟之後),如圖7之(A)所示,相對於受光元件2及塑模樹脂3在與配線層4所在之側相反之側形成配線層5(第6步驟)。本實施方式中,於絕緣層23中之不與受光部21重疊之部分、金屬柱6之端部6a、及塑模樹脂3之端面3a上形成絕緣層51及金屬配線52。又,藉由對金屬配線42之外側端部進行無電解鍍覆,而於上述外側端部之表面形成鍍覆部43。Next, after the substrate 50 is separated from the light-receiving element 2, the metal pillar 6, and the molding resin 3 as described above (that is, after the fifth step), as shown in (A) of FIG. 7, relative to the light-receiving element 2 And the mold resin 3 forms the wiring layer 5 on the side opposite to the side where the wiring layer 4 is located (step 6). In this embodiment, the insulating layer 51 and the metal wiring 52 are formed on the portion of the insulating layer 23 that does not overlap the light receiving portion 21 , the end portion 6 a of the metal pillar 6 , and the end surface 3 a of the molding resin 3 . Furthermore, electroless plating is performed on the outer end portion of the metal wiring 42 to form a plated portion 43 on the surface of the outer end portion.

例如,從圖6之(B)所示之狀態,藉由採用半導體製程(晶種層形成、光微影、電解鍍覆等)進行絕緣層51之圖案化及金屬配線52之圖案形成,可獲得圖7之(A)所示之構造。配線層5以金屬配線52中之連接於端部6a之部分之配線寬度大於端部6a之寬度之方式形成。更具體而言,絕緣層51之開口51a之寬度形成得大於金屬柱6之端部6a之寬度。藉此,金屬配線52中之連接於端部6a之部分之配線寬度w21(參照圖1)形成得大於金屬柱6之端部6a之寬度w22(參照圖1)。根據上述構成,能夠吸收第2步驟(形成塑模樹脂3之步驟)中可能會產生之金屬柱6之位置偏移。即,藉由增大金屬配線52之配線寬度,即便因第2步驟中之塑模樹脂3之流入而使金屬柱6之位置有些許偏移,亦能夠使金屬配線52與金屬柱6(端部6a)更確實地接觸。For example, from the state shown in FIG. 6(B) , by using a semiconductor process (seed layer formation, photolithography, electrolytic plating, etc.) to pattern the insulating layer 51 and pattern the metal wiring 52, it is possible to The structure shown in (A) of Figure 7 is obtained. The wiring layer 5 is formed such that the wiring width of the portion of the metal wiring 52 connected to the end portion 6a is larger than the width of the end portion 6a. More specifically, the width of the opening 51 a of the insulating layer 51 is formed larger than the width of the end portion 6 a of the metal pillar 6 . Thereby, the wiring width w21 (see FIG. 1 ) of the portion of the metal wiring 52 connected to the end 6 a is formed larger than the width w22 (see FIG. 1 ) of the end 6 a of the metal pillar 6 . According to the above structure, the positional deviation of the metal pillar 6 that may occur in the second step (the step of forming the mold resin 3) can be absorbed. That is, by increasing the wiring width of the metal wiring 52, even if the position of the metal pillar 6 is slightly shifted due to the inflow of the molding resin 3 in the second step, the metal wiring 52 can be aligned with the metal pillar 6 (end Part 6a) contacts more reliably.

再者,亦可與上述相反地,以金屬配線52中之連接於端部6a之部分之配線寬度小於金屬柱6之端部6a之寬度之方式,形成配線層5(參照下述第2實施方式)。於該情形時,能夠不受金屬柱6之大小(寬度)之影響地形成金屬配線52。例如於金屬柱6(端部6a)之寬度相對較大之情形時,若使金屬配線52之寬度較金屬柱6之寬度更大,則可能會產生金屬配線52容易與設置於配線層5之其他配線相干涉之問題。根據上述構成,能夠避免產生此種問題。Furthermore, contrary to the above, the wiring layer 5 may be formed such that the wiring width of the portion of the metal wiring 52 connected to the end portion 6a is smaller than the width of the end portion 6a of the metal pillar 6 (refer to the second embodiment below). Way). In this case, the metal wiring 52 can be formed without being affected by the size (width) of the metal pillar 6 . For example, when the width of the metal pillar 6 (end portion 6 a ) is relatively large, if the width of the metal wiring 52 is made larger than the width of the metal pillar 6 , the metal wiring 52 may easily interfere with the wiring layer 5 . Other wiring interference problems. According to the above-described configuration, such problems can be avoided.

繼而,如圖7之(B)所示,沿著單位區域間之邊界線L進行切割。藉此,可獲得單片化之複數個光半導體封裝1A。Next, as shown in FIG. 7(B) , cutting is performed along the boundary line L between the unit areas. Thereby, a plurality of single-chip optical semiconductor packages 1A can be obtained.

(作用效果) 上述之光半導體封裝1A之製造方法中,於第1步驟中,以於基板50與受光元件2之間未形成間隙之方式將受光元件2暫時接合於基板50。藉此,於第2步驟中,能夠防止塑模樹脂3流入至受光元件2與基板50之間,即,於與受光部21對向之位置形成塑模樹脂3。結果,能夠避免因受光部21被塑模樹脂3覆蓋導致之受光感度之降低。又,在藉由將受光元件2及金屬柱6暫時接合於基板50而各構件穩定地固定之狀態下,能夠穩定地且高精度地實施第2步驟。更具體而言,能夠抑制塑模樹脂3之硬化時產生封裝之翹曲。藉由以上,根據上述製造方法,能夠可靠性較高地製造光半導體封裝1A。又,受光元件2於第1面2a具有受光面。根據上述構成,能夠可靠性較高地製造入射型之受光元件2之表面為第1面2a之光半導體封裝1A。 (Effect) In the above-mentioned manufacturing method of the optical semiconductor package 1A, in the first step, the light-receiving element 2 is temporarily bonded to the substrate 50 so that no gap is formed between the substrate 50 and the light-receiving element 2 . Thereby, in the second step, the mold resin 3 can be prevented from flowing between the light receiving element 2 and the substrate 50 , that is, the mold resin 3 can be formed at a position facing the light receiving portion 21 . As a result, it is possible to avoid a decrease in the light receiving sensitivity caused by the light receiving portion 21 being covered with the mold resin 3 . Furthermore, by temporarily joining the light-receiving element 2 and the metal pillar 6 to the substrate 50, and in a state where each component is stably fixed, the second step can be performed stably and with high accuracy. More specifically, it is possible to suppress package warpage that occurs when the mold resin 3 is cured. As described above, according to the above-mentioned manufacturing method, the optical semiconductor package 1A can be manufactured with high reliability. Furthermore, the light-receiving element 2 has a light-receiving surface on the first surface 2a. According to the above structure, the optical semiconductor package 1A in which the surface of the incident-type light-receiving element 2 is the first surface 2a can be manufactured with high reliability.

又,根據上述之光半導體封裝1A之製造方法,亦發揮出以下之效果。即,如專利文獻1所揭示之方法,於使用凸塊連接使受光元件與玻璃基板相隔配置之情形時,因凸塊量之不均會導致受光元件相對於玻璃基板傾斜,從而產生光軸偏移,結果有均勻度降低之虞。另一方面,根據上述之光半導體封裝1A之製造方法,由於使受光元件2(絕緣層23)密接於基板50,故而能夠防止受光元件2相對於基板50傾斜配置,從而能夠避免產生如上所述之問題。In addition, according to the above-mentioned manufacturing method of the optical semiconductor package 1A, the following effects are also exhibited. That is, as in the method disclosed in Patent Document 1, when the light-receiving element and the glass substrate are arranged apart from each other using bump connections, the uneven amount of bumps will cause the light-receiving element to tilt relative to the glass substrate, thereby causing optical axis deviation. If moved, the uniformity may be reduced. On the other hand, according to the above-mentioned manufacturing method of the optical semiconductor package 1A, since the light-receiving element 2 (insulating layer 23) is in close contact with the substrate 50, it is possible to prevent the light-receiving element 2 from being arranged obliquely with respect to the substrate 50, thereby avoiding the above-mentioned occurrence. problem.

又,專利文獻1所揭示之方法中,為了於玻璃基板與受光元件之間封入底部填充膠,必須使受光元件與玻璃基板以某種程度隔開配置。於該情形時,因受光元件位於封裝之裏側而成為形成於玻璃基板之配線層遮住受光部之視野之構造,受光元件之工作區變窄。根據上述之光半導體封裝1A之製造方法,亦能夠避免產生此種問題。Furthermore, in the method disclosed in Patent Document 1, in order to seal the underfill between the glass substrate and the light-receiving element, the light-receiving element and the glass substrate must be arranged with a certain distance between them. In this case, since the light-receiving element is located on the back side of the package, the wiring layer formed on the glass substrate blocks the view of the light-receiving part, and the working area of the light-receiving element is narrowed. According to the above-mentioned manufacturing method of the optical semiconductor package 1A, this problem can also be avoided.

又,專利文獻1所揭示之方法中,存在封入至玻璃基板與受光元件之間之底部填充膠內產生孔隙,需要進行用以消除該孔隙之特殊處理之情形,但根據上述之光半導體封裝1A之製造方法,由於在與受光元件2(受光部21)對向之位置未形成底部填充膠,故而亦能夠避免產生如上所述之問題。In addition, in the method disclosed in Patent Document 1, there are cases where pores are generated in the underfill sealed between the glass substrate and the light-receiving element, and special processing to eliminate the pores is required. However, according to the above-mentioned optical semiconductor package 1A In this manufacturing method, since the underfill is not formed at the position facing the light-receiving element 2 (light-receiving part 21), the above-mentioned problems can also be avoided.

(變化例) 可於絕緣層23上之與受光部21對向之位置,安裝玻璃、帶通濾波器、透鏡等光學零件。安裝此種光學零件之步驟可於例如形成配線層5之步驟(第6步驟)之後實施。或者,上述光學零件亦可在執行本實施方式之製造步驟之前預先安裝於受光元件2。又,將基板50從受光元件2等分離(剝離)之步驟(第5步驟),只要於第2步驟完成後至第6步驟開始為止之期間之任意時點實施即可。例如,基板50可於第2步驟完成後直接去除。或者,第5步驟亦可至少於第3步驟之後實施。例如,第4步驟可於第3步驟之後實施,第5步驟可於第4步驟之後實施。根據上述構成,藉由使基板50於第3步驟(或者,第3步驟及第4步驟)中亦為安裝狀態,可獲得能夠在提高各構件之支持穩定性之狀態下高可靠性地實施第3步驟(或者,第3步驟及第4步驟)之優點。尤其是,本實施方式中,由於受光部21經由絕緣層23露出於外部,故而藉由使基板50為安裝狀態,能夠於各步驟中恰當地保護受光部21使其免受來自外部之衝擊等之影響。又,於實施第6步驟時,為了提高各構件之支持穩定性,可將作為暫時接合構件之基板(例如基板50)安裝於配線層4上。 (Example of variation) Optical components such as glass, bandpass filters, and lenses can be installed on the insulating layer 23 at a position facing the light receiving portion 21 . The step of mounting such optical components may be performed, for example, after the step of forming the wiring layer 5 (step 6). Alternatively, the above-mentioned optical components may also be pre-installed on the light-receiving element 2 before performing the manufacturing steps of this embodiment. In addition, the step of separating (peeling off) the substrate 50 from the light-receiving element 2 and the like (the fifth step) may be performed at any point between the completion of the second step and the start of the sixth step. For example, the substrate 50 can be directly removed after the second step is completed. Alternatively, the fifth step may be implemented at least after the third step. For example, step 4 can be implemented after step 3, and step 5 can be implemented after step 4. According to the above configuration, by placing the substrate 50 in the mounted state also in the third step (or the third step and the fourth step), it is possible to perform the third step with high reliability while improving the support stability of each member. Advantages of the 3 steps (or, steps 3 and 4). In particular, in this embodiment, since the light-receiving part 21 is exposed to the outside through the insulating layer 23, by placing the substrate 50 in the mounted state, the light-receiving part 21 can be appropriately protected from external impacts in each step. the influence. In addition, when performing the sixth step, in order to improve the support stability of each component, a substrate (for example, the substrate 50 ) as a temporary joining member may be mounted on the wiring layer 4 .

[第2實施方式] (光半導體封裝之構造) 如圖8所示,第2實施方式之光半導體封裝1B在具備透明之塑模樹脂3B而代替塑模樹脂3之點上,與光半導體封裝1A不同。又,光半導體封裝1B在金屬柱6(金屬構件)之端部6a位於較絕緣層23之上表面(與第1面2a側相反之側之面)高之位置,且進而具備將金屬配線52中之與端部6a連接之側之相反側之端部52b和電極端子22連接之金屬柱7的點上,亦與光半導體封裝1A不同。以下,對光半導體封裝1B之構成中之與光半導體封裝1A不同之部分進行說明,並省略光半導體封裝1B之構成中之與光半導體封裝1A相同之部分之相關說明。 [Second Embodiment] (Structure of optical semiconductor package) As shown in FIG. 8 , the optical semiconductor package 1B of the second embodiment is different from the optical semiconductor package 1A in that it includes a transparent mold resin 3B instead of the mold resin 3 . In addition, the optical semiconductor package 1B has the end portion 6a of the metal pillar 6 (metal member) located at a position higher than the upper surface of the insulating layer 23 (the surface opposite to the first surface 2a side), and further has the metal wiring 52 The end portion 52b on the opposite side to the side connected to the end portion 6a and the metal pillar 7 connected to the electrode terminal 22 are also different from the optical semiconductor package 1A. Hereinafter, the parts of the structure of the optical semiconductor package 1B that are different from the optical semiconductor package 1A will be described, and the description of the parts of the structure of the optical semiconductor package 1B that are the same as the optical semiconductor package 1A will be omitted.

塑模樹脂3B由具有對於成為受光部21之檢測對象之光(波長)之透明性的材料形成。塑模樹脂3B可由例如透明環氧樹脂等形成。塑模樹脂3B不僅設置於受光元件2之側面,亦設置於與受光元件2之第1面2a對向之部分(即,絕緣層23上之區域),且覆蓋金屬柱6及金屬柱7之整個側面。塑模樹脂3B還設置於配線層5之開口部51b之內側。即,塑模樹脂3B之端面3b(與第2面2b形成為同一平面之端面)之相反側之端面3a與配線層5(絕緣層51)之外表面形成為同一平面。The mold resin 3B is made of a material that has transparency with respect to the light (wavelength) to be detected by the light receiving unit 21 . The mold resin 3B may be formed of, for example, transparent epoxy resin or the like. The molding resin 3B is not only provided on the side of the light-receiving element 2, but also on the portion facing the first surface 2a of the light-receiving element 2 (that is, the area on the insulating layer 23), and covers the metal pillars 6 and 7. The entire side. The mold resin 3B is also provided inside the opening 51b of the wiring layer 5 . That is, the end surface 3a on the opposite side to the end surface 3b (the end surface formed in the same plane as the second surface 2b) of the molding resin 3B is formed in the same plane as the outer surface of the wiring layer 5 (insulating layer 51).

於光半導體封裝1B中,配線層5(第1配線層)於Z軸方向上與絕緣層23隔開。因此,設有用以將金屬配線52(第1金屬配線)與電極端子22電性連接之金屬柱7。於光半導體封裝1B中,金屬配線52具有在X軸方向上配置於外側(不與受光元件2重疊之部分)之端部52a(第1端部)、及在X軸方向上配置於內側(與受光元件2重疊之部分)之端部52b(第2端部)。端部52a連接於金屬柱6之端部6a。端部52b連接於金屬柱7之端部7a(與電極端子22側相反之側之端部)。再者,光半導體封裝1B未必需要具備柱狀之金屬柱7。例如,端部52b與電極端子22可經由導電性凸塊而連接。即,端部52b與電極端子22藉由某些導電性構件電性連接即可。又,藉由該導電性構件配置於端部52b與電極端子22之間,而於絕緣層23與絕緣層51之間形成用以在下述第5步驟中將塑模樹脂3B導入至內部空間S(參照圖9之(B))之間隙即可。In the optical semiconductor package 1B, the wiring layer 5 (first wiring layer) is separated from the insulating layer 23 in the Z-axis direction. Therefore, the metal pillar 7 for electrically connecting the metal wiring 52 (first metal wiring) and the electrode terminal 22 is provided. In the optical semiconductor package 1B, the metal wiring 52 has an end portion 52a (first end portion) disposed on the outside in the X-axis direction (a portion that does not overlap with the light-receiving element 2), and an end portion 52a (1st end portion) disposed on the inside in the X-axis direction. The end portion 52b (the second end portion) of the portion overlapping the light-receiving element 2). The end portion 52a is connected to the end portion 6a of the metal pillar 6 . The end portion 52b is connected to the end portion 7a of the metal pillar 7 (the end portion on the opposite side to the electrode terminal 22 side). Furthermore, the optical semiconductor package 1B does not necessarily need to have columnar metal pillars 7 . For example, the end portion 52b and the electrode terminal 22 may be connected via a conductive bump. That is, the end portion 52b and the electrode terminal 22 only need to be electrically connected through some conductive member. In addition, the conductive member is disposed between the end portion 52b and the electrode terminal 22 to form between the insulating layer 23 and the insulating layer 51 for introducing the molding resin 3B into the internal space S in the fifth step described below. (Refer to (B) of Figure 9).

(光半導體封裝之製造方法) 參照圖9至圖11對光半導體封裝1B之製造步驟之一例進行說明。本實施方式中,光半導體封裝1B係藉由CoW方式或CoP方式製造。圖9至圖11表示各製造步驟中之1個單位區域之狀態。以下,僅著眼於1個單位區域進行說明。 (Manufacturing method of optical semiconductor package) An example of the manufacturing steps of the optical semiconductor package 1B will be described with reference to FIGS. 9 to 11 . In this embodiment, the optical semiconductor package 1B is manufactured by the CoW method or the CoP method. Figures 9 to 11 show the state of one unit area in each manufacturing step. The following description focuses on only one unit area.

首先,如圖9之(A)所示,於作為暫時接合構件之基板50上,形成設有使基板50露出之開口部51b之配線層5(第1步驟)。配線層5具有絕緣層51及金屬配線52。開口部51b設置於絕緣層51。例如,藉由採用半導體製程(晶種層形成、光微影、電解鍍覆等)進行絕緣層51之圖案化及金屬配線52之圖案形成,可獲得圖9之(A)所示之配線層5。再者,本實施方式中,絕緣層51之開口51a之寬度形成得小於金屬柱6之端部6a之寬度,結果,金屬配線52中之連接於端部6a之部分之配線寬度形成得小於金屬柱6之端部6a之寬度。但,亦可與第1實施方式相同,金屬配線52中之連接於端部6a之部分之配線寬度形成得大於金屬柱6之端部6a之寬度。First, as shown in FIG. 9(A) , the wiring layer 5 provided with the opening 51b for exposing the substrate 50 is formed on the substrate 50 as a temporary bonding member (first step). The wiring layer 5 has an insulating layer 51 and metal wiring 52 . The opening 51b is provided in the insulating layer 51 . For example, by using a semiconductor process (seed layer formation, photolithography, electrolytic plating, etc.) to pattern the insulating layer 51 and pattern the metal wiring 52, the wiring layer shown in FIG. 9(A) can be obtained. 5. Furthermore, in this embodiment, the width of the opening 51a of the insulating layer 51 is formed smaller than the width of the end portion 6a of the metal pillar 6. As a result, the wiring width of the portion of the metal wiring 52 connected to the end portion 6a is formed smaller than the width of the metal wiring 52. The width of the end 6a of the column 6. However, like the first embodiment, the wiring width of the portion of the metal wiring 52 connected to the end portion 6 a may be formed larger than the width of the end portion 6 a of the metal pillar 6 .

繼而,如圖9之(A)所示,形成連接於金屬配線52之端部52a且從配線層5朝與基板50側相反之側突出之金屬柱6(第2步驟)。金屬柱6藉由例如鍍覆處理、焊料凸塊形成處理等而形成。金屬柱6具有連接於端部52a之端部6a、及與端部6a相反之側之端部6b。Next, as shown in FIG. 9(A) , the metal pillar 6 is connected to the end portion 52a of the metal wiring 52 and protrudes from the wiring layer 5 toward the side opposite to the substrate 50 side (second step). The metal pillar 6 is formed by, for example, plating processing, solder bump forming processing, or the like. The metal pillar 6 has an end portion 6a connected to the end portion 52a, and an end portion 6b on the opposite side to the end portion 6a.

繼而,如圖9之(B)所示,準備受光元件2(第3步驟)。繼而,以與端部52a不同之金屬配線52之端部52b與電極端子22經由金屬柱7電性連接,且受光部21配置於與開口部51b對向之位置而於基板50與受光元件2之間形成內部空間S之方式,配置受光元件2(第4步驟)。金屬柱7具有連接於端部52b之端部7a、及與端部7a相反之側之端部7b。再者,如上所述,金屬柱7只要為某些導電性構件即可,例如可為藉由將端部7b與電極端子22進行凸塊接合而形成之導電性凸塊。此處,絕緣層51之上表面(與基板50側相反之側之面)與絕緣層23之下表面(與基板50對向之面)隔開,絕緣層51與絕緣層23之間存在間隙。即,內部空間S經由該間隙而與外部連通。換言之,內部空間S未被設為與外部隔斷之封閉空間。Next, as shown in FIG. 9(B) , the light-receiving element 2 is prepared (third step). Then, the end portion 52b of the metal wiring 52 that is different from the end portion 52a is electrically connected to the electrode terminal 22 through the metal pillar 7, and the light-receiving portion 21 is disposed at a position facing the opening 51b between the substrate 50 and the light-receiving element 2 Arrange the light-receiving element 2 so that an internal space S is formed between them (step 4). The metal pillar 7 has an end portion 7a connected to the end portion 52b, and an end portion 7b on the opposite side to the end portion 7a. Furthermore, as mentioned above, the metal pillar 7 only needs to be some conductive member. For example, it may be a conductive bump formed by bump bonding the end portion 7 b and the electrode terminal 22 . Here, the upper surface of the insulating layer 51 (the surface opposite to the side of the substrate 50) is separated from the lower surface of the insulating layer 23 (the surface facing the substrate 50), and there is a gap between the insulating layer 51 and the insulating layer 23. . That is, the internal space S communicates with the outside via this gap. In other words, the internal space S is not set as a closed space separated from the outside.

繼而,如圖10之(A)所示,形成塑模樹脂3B(第5步驟)。塑模樹脂3B如上所述係由具有對於成為受光部21之檢測對象之光之透明性的材料形成,覆蓋受光元件2、金屬柱6,7、及配線層5並且填充至內部空間S(參照圖9之(B))。Next, as shown in FIG. 10(A) , mold resin 3B is formed (fifth step). As mentioned above, the molding resin 3B is formed of a material having transparency to the light to be detected by the light-receiving part 21 , covers the light-receiving element 2 , the metal pillars 6 and 7 , and the wiring layer 5 and fills the internal space S (see Figure 9(B)).

繼而,如圖10之(B)所示,藉由從與受光元件2之第2面2b對向之側(即,端面3b側)研磨或研削塑模樹脂3B,而使受光元件2之第2面2b與金屬柱6之端部6b露出(第6步驟)。此時,於各單位區域中,受光元件2之第2面2b亦可與塑模樹脂3B之端面3b一起被研磨或研削。同樣,金屬柱6之端部6b亦可被研磨或研削。亦即,可藉由塑模樹脂3B之端面3b之研磨或研削而使各單位區域之受光元件2之第2面2b或金屬柱6之端部6b露出之後,進而繼續進行將塑模樹脂3B之端面3b與第2面2b或端部6b一起進行研磨或研削之處理。結果,如圖10之(B)所示,成為受光元件2之第2面2b及金屬柱6之端部6b露出於外部之狀態。藉由以上之處理,受光元件2之第2面2b、金屬柱6之端部6b、及塑模樹脂3B之端面3b成為大致同一平面。Next, as shown in FIG. 10(B) , by grinding or grinding the molding resin 3B from the side opposite to the second surface 2b of the light-receiving element 2 (that is, the end surface 3b side), the second surface of the light-receiving element 2 is The surface 2b and the end 6b of the metal pillar 6 are exposed (step 6). At this time, in each unit area, the second surface 2b of the light-receiving element 2 may also be ground or ground together with the end surface 3b of the molding resin 3B. Similarly, the end 6b of the metal pillar 6 can also be ground or ground. That is, after the second surface 2b of the light-receiving element 2 or the end 6b of the metal pillar 6 in each unit area is exposed by grinding or grinding the end surface 3b of the molding resin 3B, the molding resin 3B can be further exposed. The end surface 3b is ground or ground together with the second surface 2b or the end 6b. As a result, as shown in FIG. 10(B) , the second surface 2b of the light-receiving element 2 and the end portion 6b of the metal pillar 6 are exposed to the outside. Through the above processing, the second surface 2b of the light-receiving element 2, the end portion 6b of the metal pillar 6, and the end surface 3b of the molding resin 3B become substantially the same plane.

繼而,如圖11之(A)所示,於受光元件2之第2面2b上、及與第2面2b連續之塑模樹脂3B之端面3b上形成配線層4(第7步驟)。本實施方式中,於受光元件2之第2面2b、金屬柱6之端部6b、及塑模樹脂3B之端面3b上,形成絕緣層41及金屬配線42(第2金屬配線)。又,藉由對金屬配線42之外側端部進行無電解鍍覆,而於上述外側端部之表面形成鍍覆部43。Next, as shown in FIG. 11(A) , the wiring layer 4 is formed on the second surface 2b of the light-receiving element 2 and the end surface 3b of the mold resin 3B that is continuous with the second surface 2b (step 7). In this embodiment, an insulating layer 41 and a metal wiring 42 (second metal wiring) are formed on the second surface 2b of the light-receiving element 2, the end 6b of the metal pillar 6, and the end surface 3b of the molding resin 3B. Furthermore, electroless plating is performed on the outer end portion of the metal wiring 42 to form a plated portion 43 on the surface of the outer end portion.

例如,從圖10之(B)所示之狀態,藉由採用半導體製程(晶種層形成、光微影、電解鍍覆等)進行絕緣層41之圖案化及金屬配線42之圖案形成,可獲得圖11之(A)所示之構造。再者,本實施方式中,絕緣層41之開口41a之寬度形成得小於金屬柱6之端部6b之寬度,結果,金屬配線42中之連接於端部6b之部分之配線寬度形成得小於金屬柱6之端部6b之寬度。但,亦可與第1實施方式相同,金屬配線42中之連接於端部6b之部分之配線寬度形成得大於金屬柱6之端部6b之寬度。For example, from the state shown in FIG. 10(B) , by using a semiconductor process (seed layer formation, photolithography, electrolytic plating, etc.) to pattern the insulating layer 41 and pattern the metal wiring 42, it is possible to The structure shown in (A) of Fig. 11 is obtained. Furthermore, in this embodiment, the width of the opening 41a of the insulating layer 41 is formed smaller than the width of the end portion 6b of the metal pillar 6. As a result, the wiring width of the portion of the metal wiring 42 connected to the end portion 6b is formed smaller than the width of the metal wiring 42. The width of the end 6b of the column 6. However, like the first embodiment, the wiring width of the portion of the metal wiring 42 connected to the end portion 6 b may be formed larger than the width of the end portion 6 b of the metal pillar 6 .

繼而,如圖11之(B)所示,將基板50從配線層5及塑模樹脂3B分離(第8步驟)。繼而,沿著單位區域間之邊界線L進行切割。藉此,可獲得單片化之複數個光半導體封裝1B。Next, as shown in FIG. 11(B) , the substrate 50 is separated from the wiring layer 5 and the mold resin 3B (eighth step). Then, cutting is performed along the boundary line L between the unit areas. Thereby, a plurality of monolithic optical semiconductor packages 1B can be obtained.

(作用效果) 光半導體封裝1B中,藉由在第5步驟中將塑模樹脂3B填充至受光元件2與基板50之間之內部空間S,而塑模樹脂3B覆蓋受光部21,但由於塑模樹脂3B具有對於成為受光部21之檢測對象之光之透明性,故而能抑制因塑模樹脂3B覆蓋受光部21導致之受光感度之降低。進而,於第5步驟中,能夠藉由單一之樹脂材料一次性形成填充至受光元件2與基板50之間之內部空間S且覆蓋各構件(受光元件2、金屬柱6,7、及配線層5)之塑模樹脂3B。藉此,能夠避免因2種樹脂部(例如,以互不相同之材料形成或於不同時點形成之2個樹脂部)混合存在導致之可靠性降低(例如,因2個樹脂部之熱膨脹係數差等引起之應力導致的金屬配線之損傷等)。藉由以上,根據上述製造方法,能夠可靠性較高地製造光半導體封裝1B。又,受光元件2於第1面2a具有受光面。根據上述構成,能夠可靠性較高地製造表面入射型之受光元件2之表面為第1面2a之光半導體封裝1B。 (Effect) In the optical semiconductor package 1B, by filling the internal space S between the light-receiving element 2 and the substrate 50 with the molding resin 3B in the fifth step, the molding resin 3B covers the light-receiving part 21. However, since the molding resin 3B has Since the light receiving part 21 is transparent to the light to be detected, it is possible to suppress a decrease in the light receiving sensitivity due to the mold resin 3B covering the light receiving part 21 . Furthermore, in the fifth step, a single resin material can be used to fill the internal space S between the light-receiving element 2 and the substrate 50 and cover each component (the light-receiving element 2, the metal pillars 6, 7, and the wiring layer) at one time. 5) Molding resin 3B. Thereby, it is possible to avoid a decrease in reliability caused by the mixing of two types of resin parts (for example, two resin parts formed of different materials or formed at different points in time) (for example, due to a difference in thermal expansion coefficient of the two resin parts). Damage to metal wiring caused by stress, etc.). As described above, according to the above-mentioned manufacturing method, the optical semiconductor package 1B can be manufactured with high reliability. Furthermore, the light-receiving element 2 has a light-receiving surface on the first surface 2a. According to the above structure, the optical semiconductor package 1B in which the surface of the surface-illuminated light-receiving element 2 is the first surface 2a can be manufactured with high reliability.

又,上述之光半導體封裝1B之製造方法中,藉由在減壓下實施第5步驟,能夠在不利用特殊裝置之情況下,一起形成無孔隙之塑模樹脂3B。Furthermore, in the above-mentioned manufacturing method of the optical semiconductor package 1B, by performing the fifth step under reduced pressure, the void-free mold resin 3B can be formed together without using a special device.

(變化例) 將基板50從配線層5等分離(剝離)之步驟(第8步驟),只要於第5步驟完成後之任意時點實施即可。例如,基板50可於第5步驟完成後直接去除。或者,第8步驟可至少於第6步驟之後實施。例如,第7步驟可於第6步驟之後實施,第8步驟可於第7步驟之後實施。根據上述構成,藉由使基板50於第6步驟(或者,第6步驟及第7步驟)中亦為安裝狀態,可獲得在提高各構件之支持穩定性之狀態下高可靠性地實施第6步驟及第7步驟之優點。 (Example of variation) The step (eighth step) of separating (peeling off) the substrate 50 from the wiring layer 5 and the like can be performed at any time after the fifth step is completed. For example, the substrate 50 can be directly removed after the fifth step is completed. Alternatively, step 8 may be performed at least after step 6. For example, step 7 can be implemented after step 6, and step 8 can be implemented after step 7. According to the above structure, by placing the substrate 50 in the mounted state also in the sixth step (or the sixth step and the seventh step), it is possible to implement the sixth step with high reliability while improving the support stability of each member. Steps and advantages of Step 7.

[第3實施方式] (光半導體封裝之構造) 如圖12所示,第3實施方式之光半導體封裝1C在具備配線層5C而代替配線層5之點上,與光半導體封裝1A不同。以下,對光半導體封裝1C之構成中之與光半導體封裝1A不同之部分進行說明,並省略光半導體封裝1C之構成中之與光半導體封裝1A相同之部分之說明。 [Third Embodiment] (Structure of optical semiconductor package) As shown in FIG. 12 , the optical semiconductor package 1C of the third embodiment is different from the optical semiconductor package 1A in that it includes a wiring layer 5C instead of the wiring layer 5 . Hereinafter, the parts of the structure of the optical semiconductor package 1C that are different from the optical semiconductor package 1A will be described, and the description of the parts of the structure of the optical semiconductor package 1C that are the same as the optical semiconductor package 1A will be omitted.

配線層5C在具有絕緣層51C而代替絕緣層51之點上,與光半導體封裝1A之配線層5不同。絕緣層51C在由透明之樹脂絕緣膜形成且未設有開口部51b之點上,與絕緣層51不同。絕緣層51C由具有對於成為受光部21之檢測對象之光之透明性的材料形成。絕緣層51C可由例如透明環氧樹脂、透明聚醯亞胺樹脂等形成。The wiring layer 5C is different from the wiring layer 5 of the optical semiconductor package 1A in that it has an insulating layer 51C instead of the insulating layer 51 . The insulating layer 51C is different from the insulating layer 51 in that it is formed of a transparent resin insulating film and is not provided with the opening 51b. The insulating layer 51C is formed of a material that is transparent to the light to be detected by the light receiving unit 21 . The insulating layer 51C may be formed of, for example, transparent epoxy resin, transparent polyimide resin, or the like.

(光半導體封裝之製造方法) 參照圖13至圖15對光半導體封裝1C之製造步驟之一例進行說明。本實施方式中,光半導體封裝1C藉由CoW方式或CoP方式而製造。圖13至圖15表示各製造步驟中之1個單位區域之狀態。以下,僅著眼於1個單位區域進行說明。 (Manufacturing method of optical semiconductor package) An example of the manufacturing steps of the optical semiconductor package 1C will be described with reference to FIGS. 13 to 15 . In this embodiment, the optical semiconductor package 1C is manufactured by the CoW method or the CoP method. Figures 13 to 15 show the state of one unit area in each manufacturing step. The following description focuses on only one unit area.

本實施方式之光半導體封裝1C之製造方法包括: 第1步驟,其係準備受光元件2,該受光元件2具有設有受光部21及與受光部21電性連接之電極端子22之第1面2a; 第2步驟,其係將配線層5C形成於基板50上,該配線層5C包含具有對於成為受光部21之檢測對象之光之透明性之絕緣層51C及金屬配線52; 第3步驟,其係形成金屬構件(金屬柱6),該金屬構件(金屬柱6)連接於金屬配線52之端部52a,從配線層5C朝與基板50側相反之側突出; 第4步驟,其係以金屬配線52之端部52b與電極端子22電性連接之方式,將受光元件2配置於配線層5C上; 第5步驟,其係形成覆蓋受光元件2、金屬柱6、及配線層5C之樹脂部(塑模樹脂3); 第6步驟,其係藉由從與受光元件2之第2面2b對向之側研磨或研削塑模樹脂3,而使受光元件2之第2面2b與金屬柱6之端部6b露出; 第7步驟,其係於受光元件2之第2面2b上、及與第2面2b連續之塑模樹脂3之端面3b上,形成包含與金屬柱6之端部6b電性連接之金屬配線42之配線層4;及 第8步驟,其係將基板50從配線層5C及塑模樹脂3分離。 The manufacturing method of the optical semiconductor package 1C of this embodiment includes: The first step is to prepare the light-receiving element 2. The light-receiving element 2 has a first surface 2a provided with a light-receiving part 21 and an electrode terminal 22 electrically connected to the light-receiving part 21; The second step is to form a wiring layer 5C on the substrate 50. The wiring layer 5C includes an insulating layer 51C and metal wiring 52 that are transparent to the light that is the detection target of the light receiving part 21; The third step is to form a metal member (metal pillar 6) that is connected to the end 52a of the metal wiring 52 and protrudes from the wiring layer 5C toward the side opposite to the substrate 50 side; The fourth step is to arrange the light-receiving element 2 on the wiring layer 5C by electrically connecting the end 52b of the metal wiring 52 to the electrode terminal 22; The fifth step is to form a resin part (molding resin 3) covering the light-receiving element 2, the metal pillar 6, and the wiring layer 5C; The sixth step is to expose the second surface 2b of the light-receiving element 2 and the end 6b of the metal pillar 6 by grinding or grinding the molding resin 3 from the side opposite to the second surface 2b of the light-receiving element 2; The seventh step is to form metal wiring including electrical connections with the end 6b of the metal pillar 6 on the second surface 2b of the light-receiving element 2 and the end surface 3b of the molding resin 3 that is continuous with the second surface 2b. Wiring layer 4 of 42; and The eighth step is to separate the substrate 50 from the wiring layer 5C and the mold resin 3 .

首先,準備受光元件2(參照圖13之(B))(第1步驟)。繼而,如圖13之(A)所示,於作為暫時接合構件之基板50上形成配線層5C(第2步驟)。如上所述,配線層5C具有絕緣層51C及金屬配線52。例如,藉由採用半導體製程(晶種層形成、光微影、電解鍍覆等)進行絕緣層51C之圖案化及金屬配線52之圖案形成,可獲得圖13之(A)所示之配線層5C。再者,本實施方式中,絕緣層51C之開口51a之寬度形成得大於金屬柱6之端部6a之寬度,結果,金屬配線52中之連接於端部6a之部分之配線寬度形成得大於金屬柱6之端部6a之寬度。但,亦可與第2實施方式同樣,金屬配線52中之連接於端部6a之部分之配線寬度形成得小於金屬柱6之端部6a之寬度。First, the light-receiving element 2 is prepared (see (B) of FIG. 13 ) (first step). Next, as shown in FIG. 13(A) , the wiring layer 5C is formed on the substrate 50 as the temporary bonding member (second step). As described above, the wiring layer 5C has the insulating layer 51C and the metal wiring 52 . For example, by using a semiconductor process (seed layer formation, photolithography, electrolytic plating, etc.) to pattern the insulating layer 51C and pattern the metal wiring 52, the wiring layer shown in FIG. 13(A) can be obtained. 5C. Furthermore, in this embodiment, the width of the opening 51a of the insulating layer 51C is formed larger than the width of the end portion 6a of the metal pillar 6. As a result, the wiring width of the portion of the metal wiring 52 connected to the end portion 6a is formed larger than the width of the metal wiring 52. The width of the end 6a of the column 6. However, similarly to the second embodiment, the wiring width of the portion of the metal wiring 52 connected to the end portion 6 a may be formed smaller than the width of the end portion 6 a of the metal pillar 6 .

繼而,如圖13之(A)所示,形成連接於金屬配線52之端部52a且從配線層5C朝與基板50側相反之側突出之金屬柱6(第3步驟)。金屬柱6藉由例如鍍覆處理、焊料凸塊形成處理等而形成。Next, as shown in FIG. 13(A) , the metal pillar 6 is connected to the end portion 52 a of the metal wiring 52 and protrudes from the wiring layer 5C toward the side opposite to the substrate 50 side (third step). The metal pillar 6 is formed by, for example, plating processing, solder bump forming processing, or the like.

繼而,如圖13之(B)所示,以金屬配線52之端部52b與電極端子22電性連接之方式將受光元件2配置於配線層5C上(第4步驟)。端部52b與電極端子22藉由例如凸塊接合而連接。藉此,絕緣層51C與絕緣層23成為相互抵接之狀態,絕緣層51C與絕緣層23之間未形成間隙。再者,端部52b與電極端子22可藉由使用銅及絕緣膜之混合接合而連接。Next, as shown in FIG. 13(B) , the light-receiving element 2 is arranged on the wiring layer 5C such that the end portion 52b of the metal wiring 52 is electrically connected to the electrode terminal 22 (the fourth step). The end portion 52b and the electrode terminal 22 are connected by, for example, bump bonding. Thereby, the insulating layer 51C and the insulating layer 23 are in contact with each other, and no gap is formed between the insulating layer 51C and the insulating layer 23 . Furthermore, the end portion 52b and the electrode terminal 22 can be connected by a mixed bonding using copper and an insulating film.

繼而,如圖14之(A)所示,形成塑模樹脂3(第5步驟)。塑模樹脂3以覆蓋受光元件2、金屬柱6、及配線層5C之方式形成。Next, as shown in FIG. 14(A) , the mold resin 3 is formed (fifth step). The mold resin 3 is formed to cover the light-receiving element 2, the metal pillar 6, and the wiring layer 5C.

繼而,如圖14之(B)所示,藉由從與受光元件2之第2面2b對向之側(即,端面3b側)研磨或研削塑模樹脂3,而使受光元件2之第2面2b與金屬柱6之端部6b露出(第6步驟)。此時,於各單位區域中,受光元件2之第2面2b亦可與塑模樹脂3之端面3b一起被研磨或研削。同樣,金屬柱6之端部6b亦可被研磨或研削。亦即,可藉由塑模樹脂3之端面3b之研磨或研削而使各單位區域之受光元件2之第2面2b或金屬柱6之端部6b露出之後,進而繼續進行將塑模樹脂3之端面3b與第2面2b或端部6b一起進行研磨或研削之處理。結果,如圖14之(B)所示,成為受光元件2之第2面2b及金屬柱6之端部6b露出於外部之狀態。藉由以上之處理,受光元件2之第2面2b、金屬柱6之端部6b、及塑模樹脂3之端面3b成為大致同一平面。Next, as shown in FIG. 14(B) , by grinding or grinding the molding resin 3 from the side opposite to the second surface 2b of the light-receiving element 2 (that is, the end surface 3b side), the second surface of the light-receiving element 2 is The surface 2b and the end 6b of the metal pillar 6 are exposed (step 6). At this time, in each unit area, the second surface 2b of the light-receiving element 2 may also be ground or ground together with the end surface 3b of the molding resin 3. Similarly, the end 6b of the metal pillar 6 can also be ground or ground. That is, after the second surface 2b of the light-receiving element 2 or the end 6b of the metal pillar 6 in each unit area is exposed by grinding or grinding the end surface 3b of the molding resin 3, the molding resin 3 can be continued to be exposed. The end surface 3b is ground or ground together with the second surface 2b or the end 6b. As a result, as shown in FIG. 14(B) , the second surface 2b of the light-receiving element 2 and the end portion 6b of the metal pillar 6 are exposed to the outside. Through the above processing, the second surface 2b of the light-receiving element 2, the end portion 6b of the metal pillar 6, and the end surface 3b of the molding resin 3 become substantially the same plane.

繼而,如圖15之(A)所示,於受光元件2之第2面2b上、及與第2面2b連續之塑模樹脂3之端面3b上形成配線層4(第7步驟)。本實施方式中,於受光元件2之第2面2b、金屬柱6之端部6b、及塑模樹脂3之端面3b上,形成絕緣層41及金屬配線42。又,藉由對金屬配線42之外側端部進行無電解鍍覆,而於上述外側端部之表面形成鍍覆部43。Next, as shown in FIG. 15(A) , the wiring layer 4 is formed on the second surface 2b of the light-receiving element 2 and the end surface 3b of the molding resin 3 that is continuous with the second surface 2b (step 7). In this embodiment, the insulating layer 41 and the metal wiring 42 are formed on the second surface 2b of the light-receiving element 2, the end portion 6b of the metal pillar 6, and the end surface 3b of the molding resin 3. Furthermore, electroless plating is performed on the outer end portion of the metal wiring 42 to form a plated portion 43 on the surface of the outer end portion.

例如,從圖14之(B)所示之狀態,藉由採用半導體製程(晶種層形成、光微影、電解鍍覆等)進行絕緣層41之圖案化及金屬配線42之圖案形成,可獲得圖15之(A)所示之構造。再者,本實施方式中,絕緣層41之開口41a之寬度形成得大於金屬柱6之端部6b之寬度,結果,金屬配線42中之連接於端部6b之部分之配線寬度形成得大於金屬柱6之端部6b之寬度。但,亦可與第2實施方式相同,金屬配線42中之連接於端部6b之部分之配線寬度形成得小於金屬柱6之端部6b之寬度。For example, from the state shown in FIG. 14(B) , by using a semiconductor process (seed layer formation, photolithography, electrolytic plating, etc.) to pattern the insulating layer 41 and pattern the metal wiring 42, it is possible to The structure shown in (A) of Fig. 15 was obtained. Furthermore, in this embodiment, the width of the opening 41a of the insulating layer 41 is formed larger than the width of the end portion 6b of the metal pillar 6. As a result, the wiring width of the portion of the metal wiring 42 connected to the end portion 6b is formed larger than the width of the metal wiring 42. The width of the end 6b of the column 6. However, like the second embodiment, the wiring width of the portion of the metal wiring 42 connected to the end portion 6 b may be formed smaller than the width of the end portion 6 b of the metal pillar 6 .

繼而,如圖15之(B)所示,將基板50從配線層5及塑模樹脂3分離(第8步驟)。繼而,沿著單位區域間之邊界線L進行切割。藉此,可獲得單片化之複數個光半導體封裝1C。Next, as shown in FIG. 15(B) , the substrate 50 is separated from the wiring layer 5 and the mold resin 3 (eighth step). Then, cutting is performed along the boundary line L between the unit areas. Thereby, a plurality of single-chip optical semiconductor packages 1C can be obtained.

根據如上所述之製造方法,能夠按照先製作受光元件2之正面側(第1面2a側)之配線層5,然後進行受光元件2之搭載(晶片安裝)、樹脂模塑(塑模樹脂3之形成)、及受光元件2之背面側(第2面2b側)之配線層4之製作的順序,製造光半導體封裝1C。再者,於上述製造方法中,將基板50從配線層5等分離(剝離)之步驟(第8步驟),亦只要在第5步驟完成後之任意時點實施即可。例如,基板50可在第5步驟完成後直接去除。但,藉由使基板50於第6步驟及第7步驟中亦為安裝狀態,可獲得能夠在提高各構件之支持穩定性之狀態下高可靠性地實施第6步驟及第7步驟之優點。According to the manufacturing method as described above, the wiring layer 5 on the front side (first surface 2a side) of the light-receiving element 2 can be produced first, and then the light-receiving element 2 can be mounted (chip mounting) and resin molded (mold resin 3 The optical semiconductor package 1C is manufactured by following the steps of forming the wiring layer 4 on the back side (the second surface 2b side) of the light-receiving element 2 . Furthermore, in the above-mentioned manufacturing method, the step of separating (peeling off) the substrate 50 from the wiring layer 5 and the like (the eighth step) can be performed at any time after the completion of the fifth step. For example, the substrate 50 can be removed directly after the fifth step is completed. However, by having the substrate 50 in the mounted state also in the sixth and seventh steps, there is an advantage that the sixth and seventh steps can be performed with high reliability while improving the support stability of each component.

於上述之光半導體封裝1C之製造方法中,藉由將「配線層5C」及「絕緣層51C」替換為「配線層5」及「絕緣層51」,並且將圖13所示之步驟替換為圖16所示之步驟,能夠製造具有與光半導體封裝1A相同之構造之光半導體封裝。In the above-mentioned manufacturing method of optical semiconductor package 1C, by replacing "wiring layer 5C" and "insulating layer 51C" with "wiring layer 5" and "insulating layer 51", and replacing the steps shown in Figure 13 with The steps shown in FIG. 16 can manufacture an optical semiconductor package having the same structure as the optical semiconductor package 1A.

更具體而言,上述之光半導體封裝1C之製造方法之第2步驟替換為「第2步驟,其係將包含絕緣層51及金屬配線52且設有使基板50露出之開口部51b之配線層5形成於基板50上」。藉此,於第3步驟完成之時間點,可獲得圖16之(A)所示之構造以代替圖13之(A)所示之構造。More specifically, the second step of the above-mentioned manufacturing method of the optical semiconductor package 1C is replaced with "the second step, which is to form a wiring layer including an insulating layer 51 and a metal wiring 52 and having an opening 51b for exposing the substrate 50 5 is formed on the substrate 50". Thereby, when the third step is completed, the structure shown in (A) of FIG. 16 can be obtained instead of the structure shown in (A) of FIG. 13 .

又,上述之光半導體封裝1C之製造方法之第4步驟替換為「第4步驟,其係以金屬配線52之端部52b與電極端子22電性連接,且受光部21配置於與開口部51b對向之位置而於基板50與受光元件2之間形成封閉空間S1之方式,將受光元件2配置於配線層5上」。藉此,於第4步驟完成之時間點,可獲得圖16之(B)所示之構造以代替圖13之(B)所示之構造。此處,封閉空間S1設定為被基板50、絕緣層23、及絕緣層51包圍之密閉空間。因此,於第5步驟中,塑模樹脂3以覆蓋受光元件2、金屬柱6、及配線層5之方式形成,封閉空間S1中未填充塑模樹脂3。結果,於後續之第6步驟至第8步驟及切割完成之時間點,可獲得具有與圖1所示之光半導體封裝1A相同之構造之光半導體封裝。In addition, the fourth step of the above-mentioned manufacturing method of the optical semiconductor package 1C is replaced with "the fourth step, in which the end portion 52b of the metal wiring 52 is electrically connected to the electrode terminal 22, and the light receiving portion 21 is arranged with the opening 51b The light-receiving element 2 is arranged on the wiring layer 5 in such a manner that a closed space S1 is formed between the substrate 50 and the light-receiving element 2 at opposite positions." Thereby, when the fourth step is completed, the structure shown in (B) of FIG. 16 can be obtained instead of the structure shown in (B) of FIG. 13 . Here, the closed space S1 is set as a closed space surrounded by the substrate 50 , the insulating layer 23 and the insulating layer 51 . Therefore, in the fifth step, the mold resin 3 is formed to cover the light-receiving element 2, the metal pillar 6, and the wiring layer 5, and the closed space S1 is not filled with the mold resin 3. As a result, at the subsequent 6th to 8th steps and at the time when cutting is completed, an optical semiconductor package having the same structure as the optical semiconductor package 1A shown in FIG. 1 can be obtained.

以上,對本發明之若干實施方式進行了說明,但本發明並不限於上述實施方式。各構成之材料及形狀並不限於上述材料及形狀,可採用多種材料及形狀。又,上述一實施方式或變化例中之一部分構成可任意應用於其他實施方式或變化例中之構成。例如,如上述實施方式中所示,能夠將基板50適當地用作暫時接合構件,但暫時接合構件亦可為基板以外之構件。例如,片構件(例如,片狀之非常薄之構件)可用作暫時接合構件。又,上述實施方式中例示了利用CoW方式或CoP方式之製造方法,但亦可採用上述以外之方式。例如,於以晶片單位製造光半導體封裝之情形時,可省略上述實施方式中之切割步驟。Some embodiments of the present invention have been described above, but the present invention is not limited to the above-mentioned embodiments. The materials and shapes of each component are not limited to the above-mentioned materials and shapes, and a variety of materials and shapes can be used. In addition, some of the configurations in the above-mentioned embodiment or modifications may be arbitrarily applied to the configurations in other embodiments or modifications. For example, as shown in the above-mentioned embodiment, the substrate 50 can be suitably used as the temporary joining member, but the temporary joining member may be a member other than the substrate. For example, a sheet member (eg, a sheet-like very thin member) may be used as the temporary joining member. In addition, in the above-described embodiment, the manufacturing method using the CoW method or the CoP method is exemplified, but methods other than the above can also be used. For example, when optical semiconductor packages are manufactured on a wafer basis, the cutting step in the above embodiment can be omitted.

1A,1B,1C:光半導體封裝 2:受光元件 2a:第1面 2b:第2面 3,3B:塑模樹脂(樹脂部) 3a:端面 3b:端面 4:配線層(第1配線層、第2配線層) 5:配線層(第1配線層、第2配線層) 5C:配線層 6,6A:金屬柱(金屬構件) 6a:端部(第1端部) 6b:端部(第2端部) 7:金屬柱 7a:端部 7b:端部 21:受光部 22:電極端子 23:絕緣層 23a:開口 41:絕緣層 41a:開口 42:金屬配線(第1金屬配線、第2金屬配線) 43:鍍覆部 50:基板 50a:暫時接合面 51:絕緣層 51a:開口 51b:開口部 51C:絕緣層 52:金屬配線(第1金屬配線、第2金屬配線) 52a:端部(第1端部) 52b:端部(第2端部) 61:軸部 62:凸緣部 62a:內表面 100:支持構件 101:板狀構件 101a:貫通孔 102:支持基板 L:邊界線 S:內部空間 S1:封閉空間 w11:配線寬度 w12:寬度 w21:配線寬度 w22:寬度 1A, 1B, 1C: Optical semiconductor packaging 2:Light-receiving element 2a:Side 1 2b: Side 2 3,3B:Molding resin (resin part) 3a: End face 3b: End face 4: Wiring layer (1st wiring layer, 2nd wiring layer) 5: Wiring layer (1st wiring layer, 2nd wiring layer) 5C: Wiring layer 6,6A: Metal pillar (metal component) 6a: End (1st end) 6b: End (2nd end) 7:Metal pillar 7a: end 7b: end 21:Light receiving part 22:Electrode terminal 23:Insulation layer 23a: Open your mouth 41:Insulation layer 41a:Open your mouth 42: Metal wiring (first metal wiring, second metal wiring) 43:Plating Department 50:Substrate 50a: Temporary joint surface 51:Insulation layer 51a:Open your mouth 51b: opening 51C: Insulation layer 52: Metal wiring (first metal wiring, second metal wiring) 52a: End (1st end) 52b: End (2nd end) 61: Shaft 62:Flange part 62a:Inner surface 100: Support components 101: Plate-like components 101a:Through hole 102:Support substrate L: boundary line S: internal space S1: Enclosed space w11: Wiring width w12:width w21: Wiring width w22:width

圖1係第1實施方式之光半導體封裝之剖視圖。 圖2係表示圖1之光半導體封裝之製造步驟之一例之圖。 圖3(A)至(C)係表示圖1之光半導體封裝之製造步驟之一例之圖。 圖4係表示圖1之光半導體封裝之製造步驟之一例之圖。 圖5(A)、(B)係表示圖1之光半導體封裝之製造步驟之一例之圖。 圖6(A)、(B)係表示圖1之光半導體封裝之製造步驟之一例之圖。 圖7(A)、(B)係表示圖1之光半導體封裝之製造步驟之一例之圖。 圖8係第2實施方式之光半導體封裝之剖視圖。 圖9(A)、(B)係表示圖8之光半導體封裝之製造步驟之一例之圖。 圖10(A)、(B)係表示圖8之光半導體封裝之製造步驟之一例之圖。 圖11(A)、(B)係表示圖8之光半導體封裝之製造步驟之一例之圖。 圖12係第3實施方式之光半導體封裝之剖視圖。 圖13(A)、(B)係表示圖12之光半導體封裝之製造步驟之一例之圖。 圖14(A)、(B)係表示圖12之光半導體封裝之製造步驟之一例之圖。 圖15(A)、(B)係表示圖12之光半導體封裝之製造步驟之一例之圖。 圖16(A)、(B)係表示圖1之光半導體封裝之製造方法之變化例之圖。 FIG. 1 is a cross-sectional view of the optical semiconductor package according to the first embodiment. FIG. 2 is a diagram showing an example of manufacturing steps of the optical semiconductor package of FIG. 1 . 3(A) to (C) are diagrams showing an example of manufacturing steps of the optical semiconductor package of FIG. 1 . FIG. 4 is a diagram showing an example of manufacturing steps of the optical semiconductor package of FIG. 1 . 5 (A) and (B) are diagrams showing an example of the manufacturing steps of the optical semiconductor package of FIG. 1 . 6 (A) and (B) are diagrams showing an example of the manufacturing steps of the optical semiconductor package of FIG. 1 . 7(A) and (B) are diagrams showing an example of the manufacturing steps of the optical semiconductor package of FIG. 1 . FIG. 8 is a cross-sectional view of the optical semiconductor package according to the second embodiment. 9(A) and (B) are diagrams showing an example of manufacturing steps of the optical semiconductor package of FIG. 8 . FIGS. 10(A) and 10(B) are diagrams showing an example of manufacturing steps of the optical semiconductor package of FIG. 8 . 11(A) and (B) are diagrams showing an example of the manufacturing steps of the optical semiconductor package of FIG. 8 . FIG. 12 is a cross-sectional view of the optical semiconductor package according to the third embodiment. 13(A) and (B) are diagrams showing an example of manufacturing steps of the optical semiconductor package of FIG. 12 . 14(A) and (B) are diagrams showing an example of manufacturing steps of the optical semiconductor package of FIG. 12 . 15(A) and (B) are diagrams showing an example of manufacturing steps of the optical semiconductor package of FIG. 12 . FIGS. 16(A) and 16(B) are diagrams showing variations of the manufacturing method of the optical semiconductor package of FIG. 1 .

1A:光半導體封裝 1A: Optical semiconductor packaging

2:受光元件 2:Light-receiving element

2a:第1面 2a:Side 1

2b:第2面 2b: Side 2

3:塑模樹脂(樹脂部) 3:Molding resin (resin part)

3a:端面 3a: End face

3b:端面 3b: End face

4:配線層(第1配線層、第2配線層) 4: Wiring layer (1st wiring layer, 2nd wiring layer)

5:配線層(第1配線層、第2配線層) 5: Wiring layer (1st wiring layer, 2nd wiring layer)

6:金屬柱(金屬構件) 6: Metal pillar (metal component)

6a:端部(第1端部) 6a: End (1st end)

6b:端部(第2端部) 6b: End (2nd end)

21:受光部 21:Light receiving part

22:電極端子 22:Electrode terminal

23:絕緣層 23:Insulation layer

23a:開口 23a: Open your mouth

41:絕緣層 41:Insulation layer

41a:開口 41a:Open your mouth

42:金屬配線(第1金屬配線、第2金屬配線) 42: Metal wiring (first metal wiring, second metal wiring)

43:鍍覆部 43:Plating Department

51:絕緣層 51:Insulation layer

51a:開口 51a: Open your mouth

51b:開口部 51b: opening

52:金屬配線(第1金屬配線、第2金屬配線) 52: Metal wiring (first metal wiring, second metal wiring)

w11:配線寬度 w11: Wiring width

w12:寬度 w12:width

w21:配線寬度 w21: Wiring width

w22:寬度 w22:width

Claims (15)

一種光半導體封裝之製造方法,其包括: 第1步驟,其係將具有設有受光部及與上述受光部電性連接之電極端子之第1面之受光元件、與柱狀之金屬構件之第1端部暫時接合於基板,且以上述第1面與上述基板對向之方式將上述受光元件暫時接合於上述基板; 第2步驟,其係將覆蓋上述受光元件及上述金屬構件之樹脂部形成於上述基板上; 第3步驟,其係藉由從與上述受光元件之上述第1面之相反側之第2面對向之側研磨或研削上述樹脂部,而使上述受光元件之上述第2面及上述金屬構件之上述第1端部之相反側之第2端部露出; 第4步驟,其係於上述受光元件之上述第2面上、及與上述第2面連續之上述樹脂部之端面上,形成包含與上述第2端部電性連接之第1金屬配線之第1配線層; 第5步驟,其係將上述基板從上述受光元件、上述金屬構件、及上述樹脂部分離;及 第6步驟,其係於上述第5步驟之後,相對於上述受光元件及上述樹脂部在與上述第1配線層所在之側相反之側,形成包含將上述第1端部與上述電極端子電性連接之第2金屬配線之第2配線層。 A manufacturing method for optical semiconductor packaging, which includes: The first step is to temporarily join a light-receiving element having a first surface provided with a light-receiving part and an electrode terminal electrically connected to the light-receiving part, and a first end of a columnar metal member to a substrate, and use the above-mentioned Temporarily bonding the light-receiving element to the above-mentioned substrate with the first surface facing the above-mentioned substrate; The second step is to form a resin portion covering the light-receiving element and the metal member on the substrate; The third step is to grind or grind the resin portion from the side facing the second surface opposite to the first surface of the light-receiving element, so that the second surface of the light-receiving element and the metal member The second end on the opposite side to the above-mentioned first end is exposed; The fourth step is to form a first metal wiring including a first metal wiring electrically connected to the second end on the second surface of the light-receiving element and the end surface of the resin portion continuous with the second surface. 1 wiring layer; The fifth step is to separate the above-mentioned substrate from the above-mentioned light-receiving element, the above-mentioned metal member, and the above-mentioned resin part; and The sixth step, after the fifth step, is to form an electrical connection between the first end portion and the electrode terminal on the side opposite to the side where the first wiring layer is located with respect to the light-receiving element and the resin portion. The second wiring layer of the connected second metal wiring. 如請求項1之光半導體封裝之製造方法,其中 上述第1步驟包括以下步驟: 藉由支持構件而以使上述第1端部露出之狀態將上述金屬構件定位並予以支持;及 藉由使上述基板之暫時接合面接觸於支持在上述支持構件之上述金屬構件之上述第1端部,而將上述第1端部暫時接合於上述基板。 The manufacturing method of optical semiconductor package as claimed in claim 1, wherein Step 1 above includes the following steps: The above-mentioned metal member is positioned and supported by a supporting member in a state in which the above-mentioned first end is exposed; and The first end portion is temporarily joined to the substrate by bringing the temporary joining surface of the substrate into contact with the first end portion of the metal member supported by the supporting member. 如請求項2之光半導體封裝之製造方法,其中 上述支持構件具有: 板狀構件,其形成有具有較上述金屬構件之寬度大之寬度之貫通孔;及 支持基板,其供載置及支持上述第2端部; 上述金屬構件插通於上述板狀構件之上述貫通孔而被定位,並且支持於上述支持基板; 在上述金屬構件支持於上述支持構件之狀態下,上述第1端部相對於上述板狀構件而朝與上述支持基板側相反之側突出。 The manufacturing method of optical semiconductor package as claimed in claim 2, wherein The above support components include: A plate-shaped member formed with a through-hole having a width larger than the width of the above-mentioned metal member; and A support substrate for placing and supporting the above-mentioned second end; The metal member is inserted into the through hole of the plate-shaped member to be positioned, and is supported on the support substrate; In a state where the metal member is supported by the support member, the first end protrudes toward the side opposite to the support substrate side with respect to the plate-shaped member. 如請求項2之光半導體封裝之製造方法,其中 上述金屬構件具有包含上述第2端部之軸部、及包含上述第1端部且較上述軸部更寬幅地形成之凸緣部; 上述支持構件係板狀構件,形成有具有較上述軸部之寬度大且較上述凸緣部之寬度小之寬度之貫通孔; 上述金屬構件藉由上述軸部插通於上述貫通孔且上述凸緣部之上述第2端部側之內表面抵接於上述支持構件之上述貫通孔之周緣部,而支持於上述支持構件。 The manufacturing method of optical semiconductor package as claimed in claim 2, wherein The metal member has a shaft part including the second end part, and a flange part including the first end part and formed wider than the shaft part; The support member is a plate-shaped member, and is formed with a through hole having a width larger than the width of the shaft portion and smaller than the width of the flange portion; The metal member is supported on the support member by the shaft portion being inserted into the through hole and the inner surface of the second end side of the flange portion being in contact with the peripheral edge portion of the through hole of the support member. 如請求項1至4中任一項之光半導體封裝之製造方法,其中 於上述第4步驟中,以上述第1金屬配線中之連接於上述第2端部之部分之配線寬度大於上述金屬構件之上述第2端部之寬度的方式,形成上述第1配線層。 The manufacturing method of an optical semiconductor package as claimed in any one of items 1 to 4, wherein In the fourth step, the first wiring layer is formed such that the wiring width of the portion of the first metal wiring connected to the second end is larger than the width of the second end of the metal member. 如請求項1至4中任一項之光半導體封裝之製造方法,其中 於上述第4步驟中,以上述第1金屬配線中之連接於上述第2端部之部分之配線寬度小於上述金屬構件之上述第2端部之寬度的方式,形成上述第1配線層。 The manufacturing method of an optical semiconductor package as claimed in any one of items 1 to 4, wherein In the fourth step, the first wiring layer is formed such that the wiring width of the portion of the first metal wiring connected to the second end is smaller than the width of the second end of the metal member. 如請求項1至6中任一項之光半導體封裝之製造方法,其中 於上述第6步驟中,以上述第2金屬配線中之連接於上述第1端部之部分之配線寬度大於上述金屬構件之上述第1端部之寬度的方式,形成上述第2配線層。 The manufacturing method of an optical semiconductor package as claimed in any one of items 1 to 6, wherein In the sixth step, the second wiring layer is formed such that the wiring width of the portion of the second metal wiring connected to the first end is larger than the width of the first end of the metal member. 如請求項1至6中任一項之光半導體封裝之製造方法,其中 於上述第6步驟中,以上述第2金屬配線中之連接於上述第1端部之部分之配線寬度小於上述金屬構件之上述第1端部之寬度的方式,形成上述第2配線層。 The manufacturing method of an optical semiconductor package as claimed in any one of items 1 to 6, wherein In the sixth step, the second wiring layer is formed such that the wiring width of the portion of the second metal wiring connected to the first end is smaller than the width of the first end of the metal member. 如請求項1至8中任一項之光半導體封裝之製造方法,其中 上述第5步驟至少於上述第3步驟之後實施。 The manufacturing method of an optical semiconductor package as claimed in any one of items 1 to 8, wherein The above-mentioned step 5 shall be carried out at least after the above-mentioned step 3. 如請求項9之光半導體封裝之製造方法,其中 上述第4步驟於上述第3步驟之後實施, 上述第5步驟於上述第4步驟之後實施。 The manufacturing method of the optical semiconductor package of claim 9, wherein The above-mentioned step 4 is implemented after the above-mentioned step 3, The above-mentioned step 5 is implemented after the above-mentioned step 4. 如請求項1至10中任一項之光半導體封裝之製造方法,其中 上述受光元件於上述第1面具有受光面。 The manufacturing method of an optical semiconductor package according to any one of claims 1 to 10, wherein The light-receiving element has a light-receiving surface on the first surface. 一種光半導體封裝之製造方法,其包括: 第1步驟,其係於基板上形成包含第1金屬配線且設有使上述基板露出之開口部的第1配線層; 第2步驟,其係形成金屬構件,該金屬構件連接於上述第1金屬配線之第1端部,從上述第1配線層朝與上述基板側相反之側突出; 第3步驟,其係準備受光元件,該受光元件具有設有受光部及與上述受光部電性連接之電極端子之第1面; 第4步驟,其係以不同於上述第1端部之上述第1金屬配線之第2端部與上述電極端子電性連接,並且上述受光部配置於與上述開口部對向之位置而於上述基板與上述受光元件之間形成內部空間之方式,配置上述受光元件; 第5步驟,其係形成樹脂部,該樹脂部覆蓋上述受光元件、上述金屬構件、及上述第1配線層且填充至上述內部空間,具有對於成為上述受光部之檢測對象之光之透明性; 第6步驟,其係藉由從與上述受光元件之上述第1面之相反側之第2面對向之側研磨或研削上述樹脂部,而使上述第2面及上述金屬構件之連接於上述第1金屬配線之側之相反側之端部露出; 第7步驟,其係於上述受光元件之上述第2面上、及與上述第2面連續之上述樹脂部之端面上,形成包含與上述金屬構件之上述端部電性連接之第2金屬配線之第2配線層;及 第8步驟,其係將上述基板從上述第1配線層及上述樹脂部分離。 A manufacturing method for optical semiconductor packaging, which includes: The first step is to form a first wiring layer on a substrate that includes a first metal wiring and is provided with an opening for exposing the substrate; The second step is to form a metal member connected to the first end of the first metal wiring and protruding from the first wiring layer toward the side opposite to the substrate side; The third step is to prepare a light-receiving element, which has a first surface provided with a light-receiving part and an electrode terminal electrically connected to the light-receiving part; The fourth step is to electrically connect the second end of the first metal wiring, which is different from the first end, to the electrode terminal, and the light-receiving part is disposed at a position opposite to the opening. The above-mentioned light-receiving element is arranged in such a manner that an internal space is formed between the substrate and the above-mentioned light-receiving element; The fifth step is to form a resin part that covers the light-receiving element, the metal member, and the first wiring layer and fills the internal space, and has transparency with respect to light that is a detection target of the light-receiving part; The sixth step is to connect the above-mentioned second surface and the above-mentioned metal member to the above-mentioned surface by grinding or grinding the above-mentioned resin part from the side facing the second surface on the opposite side to the above-mentioned first surface of the above-mentioned light-receiving element. The end of the first metal wiring on the opposite side is exposed; The seventh step is to form a second metal wiring including a second metal wiring electrically connected to the end of the metal member on the second surface of the light-receiving element and the end surface of the resin portion continuous with the second surface. the second wiring layer; and The eighth step is to separate the substrate from the first wiring layer and the resin portion. 如請求項12之光半導體封裝之製造方法,其中 上述第8步驟至少於上述第6步驟之後實施。 The manufacturing method of optical semiconductor package as claimed in claim 12, wherein The above-mentioned step 8 is performed at least after the above-mentioned step 6. 如請求項12之光半導體封裝之製造方法,其中 上述第7步驟於上述第6步驟之後實施, 上述第8步驟於上述第7步驟之後實施。 The manufacturing method of optical semiconductor package as claimed in claim 12, wherein The above-mentioned step 7 is implemented after the above-mentioned step 6, The above-mentioned step 8 is implemented after the above-mentioned step 7. 如請求項12至14中任一項之光半導體封裝之製造方法,其中 上述受光元件於上述第1面具有受光面。 The manufacturing method of an optical semiconductor package as claimed in any one of items 12 to 14, wherein The light-receiving element has a light-receiving surface on the first surface.
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