TWI555105B - Fabrication of microelectronic assemblies having stack terminals coupled by connectors extending through encapsulation - Google Patents

Fabrication of microelectronic assemblies having stack terminals coupled by connectors extending through encapsulation Download PDF

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TWI555105B
TWI555105B TW104109645A TW104109645A TWI555105B TW I555105 B TWI555105 B TW I555105B TW 104109645 A TW104109645 A TW 104109645A TW 104109645 A TW104109645 A TW 104109645A TW I555105 B TWI555105 B TW I555105B
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connector
microelectronic
connectors
component
seal
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TW104109645A
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TW201546921A (en
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依利亞斯 穆罕默德
貝勒卡塞姆 哈巴
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英凡薩斯公司
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49833Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the chip support structure consisting of a plurality of insulating substrates
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • H01L2224/131Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73203Bump and layer connectors
    • H01L2224/73204Bump and layer connectors the bump connector being embedded into the layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1532Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H01L2924/1533Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate
    • H01L2924/15331Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate being a ball array, e.g. BGA

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Wire Bonding (AREA)

Description

具延伸通過密封連接器所耦接之堆疊端子的微電子組件的製造 Fabrication of microelectronic components with stacked terminals that are coupled through a sealed connector 【相關申請案之交互參照】[Reciprocal Reference of Related Applications]

本申請案為2013年7月15日申請的美國申請案第13/942,568號的部分連續案,其揭示內容在此以引用之方式併入本文。 This application is a continuation-in-part of U.S. Application Serial No. 13/942,568, filed on Jan. 15, 2013, the disclosure of which is hereby incorporated by reference.

本發明係關於微電子元件的封裝,特別是半導體晶片的封裝。 The invention relates to the packaging of microelectronic components, in particular the packaging of semiconductor wafers.

微電子元件通常包含半導體材料(例如矽或砷化鎵)的薄板,通常稱為晶粒或半導體晶片。半導體晶片通常提供作為個別的預封裝單元。在一些單元設計中,半導體晶片安裝至基板或晶片載體,接著安裝在電路平板上,例如印刷電路板。 Microelectronic components typically comprise a thin sheet of a semiconductor material, such as germanium or gallium arsenide, commonly referred to as a die or semiconductor wafer. Semiconductor wafers are typically provided as individual pre-packaged units. In some cell designs, a semiconductor wafer is mounted to a substrate or wafer carrier and then mounted on a circuit board, such as a printed circuit board.

主動電路製作在半導體晶片的第一面(例如,前表面)中。為了主動電路的電連接,晶片在相同的面上設有接合墊。接合墊通常以規 則的陣列設置在晶粒的邊緣周圍,或者針對許多記憶體裝置是設置在晶粒的中心。接合墊通常由導電金屬製成,例如銅或鋁,大約0.5微米(μm)厚。接合墊可包含單層或多層的金屬。接合墊的尺寸將隨裝置類型而改變,但是通常與側邊相距有數十至數百微米。 The active circuit is fabricated in a first side (eg, a front surface) of the semiconductor wafer. For electrical connection of the active circuit, the wafer is provided with bond pads on the same face. Bond pad The array is then placed around the edges of the die or at the center of the die for many memory devices. The bond pads are typically made of a conductive metal, such as copper or aluminum, about 0.5 microns (μm) thick. The bond pads can comprise a single layer or multiple layers of metal. The size of the bond pads will vary with the type of device, but is typically tens to hundreds of microns from the sides.

例如半導體晶片的微電子元件通常需要許多對於其他電子部件的輸入與輸出連接。半導體晶片或其他類似裝置的輸入與輸出接點通常設置成類似格柵的型態(通常稱為「區域陣列」),其實質上覆蓋該晶片的表面,或者設置成伸長的列,其可延伸平行於該晶片的前表面的每一邊緣且相鄰於每一邊緣,或在前表面的中心。半導體晶片通常設置於封裝中,封裝利於在製造期間以及在安裝晶片於外部基板上(例如電路板或其他電路平板)的期間晶片的處理。例如,許多半導體晶片設置於適於表面安裝的封裝中。已經提出此種一般類型的數種封裝來用於多種應用。一般而言,此種封裝包含介電質元件(通常稱為「晶片載體」),具有形成為板狀或蝕刻金屬結構的端子在該介電質上。這些端子通常藉由例如沿著晶片載體本身延伸的細線跡之特徵以及藉由延伸於晶片接點與端子或線跡之間的細引線或導線,而連接於晶片本身的接點。在表面安裝操作中,封裝置於電路板上,使得封裝上的每一端子對準於電路板上的對應接墊。焊料或其他接合材料設置於端子與接墊之間。藉由加熱該組件來熔化或「回焊」焊料或者活化該接合材料,該封裝可永久地接合在定位。 Microelectronic components such as semiconductor wafers typically require many input and output connections to other electronic components. The input and output contacts of a semiconductor wafer or other similar device are typically arranged in a grid-like pattern (commonly referred to as an "area array") that substantially covers the surface of the wafer or is arranged in an elongated column that can be extended Parallel to each edge of the front surface of the wafer and adjacent to each edge, or at the center of the front surface. Semiconductor wafers are typically disposed in a package that facilitates processing of the wafer during fabrication and during mounting of the wafer on an external substrate, such as a circuit board or other circuit board. For example, many semiconductor wafers are placed in a package suitable for surface mounting. Several packages of this general type have been proposed for a variety of applications. Generally, such packages comprise a dielectric component (commonly referred to as a "wafer carrier") having terminals formed in a plate or etched metal structure on the dielectric. These terminals are typically connected to the contacts of the wafer itself by features such as thin traces extending along the wafer carrier itself and by thin leads or wires extending between the wafer contacts and the terminals or traces. In a surface mount operation, the package is placed on a circuit board such that each terminal on the package is aligned with a corresponding pad on the circuit board. Solder or other bonding material is disposed between the terminal and the pad. The package can be permanently engaged in positioning by heating the assembly to melt or "reflow" the solder or activate the bonding material.

許多封裝包含焊料塊係為焊料球的形式,通常直徑為大約0.1mm與大約0.8mm(5與30密爾)之間,附接於封裝的端子。具有焊料球陣列從其底表面突伸的封裝通常稱為球柵陣列或「BGA(ball grid array)」 封裝。其他封裝(稱為平面柵格陣列或「LGA(land grid array)」封裝)藉由形成自焊料的薄層或平面而固定至基板。此種封裝可以很精小。某些封裝(通常稱為「晶片級封裝」)占據電路板的面積係等於(或僅稍微大於)該封裝中所併入的裝置的面積。這是有利的,因為它減小組件的整體尺寸,並且允許使用基板上的各種裝置之間的短互連,這接著限制了裝置之間的信號傳輸時間,且因此促成組件以高速操作。 Many packages contain solder bumps in the form of solder balls, typically between about 0.1 mm and about 0.8 mm (5 and 30 mils) in diameter, attached to the terminals of the package. A package having a solder ball array protruding from its bottom surface is commonly referred to as a ball grid array or "BGA (ball grid array)" Package. Other packages, referred to as planar grid arrays or "LGA (land grid array) packages), are secured to the substrate by a thin layer or plane formed from solder. This package can be very small. Some packages (often referred to as "wafer level packages") occupy an area of the board that is equal to (or only slightly larger than) the area of the device incorporated in the package. This is advantageous because it reduces the overall size of the assembly and allows for the use of short interconnections between the various devices on the substrate, which in turn limits the signal transmission time between the devices and thus facilitates operation of the assembly at high speeds.

已封裝的半導體晶片通常設置成「堆疊」的配置,其中例如提供一封裝於電路板上,且另一封裝係安裝於該第一封裝的頂部上。這些配置可允許多個不同的晶片安裝於電路板上的單一面積內,且藉由提供封裝之間的短互連,可另外促成高速操作。通常,此互連距離僅稍微大於晶片本身的厚度。為了達成晶片封裝的堆疊內的互連,需要在每一封裝的兩側上(除了最頂部的封裝之外)提供用於機械與電連接的結構。這已經實行,例如藉由提供接墊或平面於安裝有晶片之基板的兩側上,接墊藉由導電通孔或類似者而連接通過基板。堆疊式晶片配置與互連結構的範例係提供於美國專利申請案公開號第2010/0232129號中,其揭示內容在此以引用之方式將其併入。 Packaged semiconductor wafers are typically arranged in a "stacked" configuration in which, for example, a package is provided on a circuit board and another package is mounted on top of the first package. These configurations may allow multiple different wafers to be mounted within a single area of the board and may additionally facilitate high speed operation by providing short interconnects between the packages. Typically, this interconnect distance is only slightly greater than the thickness of the wafer itself. In order to achieve interconnections within the stack of wafer packages, it is desirable to provide structures for mechanical and electrical connections on both sides of each package (with the exception of the topmost package). This has been done, for example, by providing pads or planes on both sides of the substrate on which the wafer is mounted, the pads being connected through the substrate by conductive vias or the like. An example of a stacked wafer configuration and interconnect structure is provided in U.S. Patent Application Publication No. 2010/0232129, the disclosure of which is incorporated herein by reference.

尺寸為晶片的任何實體配置的重要考量。隨著可攜式電子裝置的快速發展,對於晶片的更緊密實體配置之需求已經變得更加強烈。僅藉由範例的方式,通常稱為「智慧型手機」的裝置整合了手機與強大的資料處理器、記憶體以及輔助裝置(例如,全球定位系統接收器、電子照相機、與區域網路連接,還有高解析度顯示器與相關的影像處理晶片)的功能。此種裝置可提供例如完整的網際網路連接、包含全解析度視頻的娛樂、 導航、電子銀行等的功能,所有功能都在口袋大小的裝置中。複雜的可攜式裝置需要將許多晶片封裝進小空間中。此外,一些晶片具有許多輸入與輸出連接,通常稱為「I/O」。這些I/O必須互連於其他晶片的I/O。互連應該要短,並且應該具有低阻抗,以最小化信號傳輸延遲。形成互連的部件不應該大大增加組件的尺寸。類似的需求也出現在其他應用中,例如在資料伺服器中,例如在網際網路搜尋引擎中使用的那些。例如,提供許多短的、低阻抗的互連於複雜的晶片之間之結構可增加搜尋引擎的頻寬並且減少其功率消耗。 The size is an important consideration for any physical configuration of the wafer. With the rapid development of portable electronic devices, the need for tighter physical configurations of wafers has become more intense. By way of example only, devices commonly referred to as "smart phones" integrate mobile phones with powerful data processors, memory, and auxiliary devices (eg, GPS receivers, electronic cameras, and regional network connections, There are also functions of high resolution displays and associated image processing wafers. Such a device can provide, for example, a complete internet connection, entertainment with full resolution video, Navigation, e-banking, and more, all in a pocket-sized device. Complex portable devices require many wafers to be packaged into a small space. In addition, some wafers have many input and output connections, commonly referred to as "I/O." These I/Os must be interconnected to the I/O of other wafers. The interconnect should be short and should have low impedance to minimize signal propagation delay. Forming interconnected components should not greatly increase the size of the components. Similar requirements are also found in other applications, such as those in data servers, such as those used in Internet search engines. For example, providing a structure of many short, low impedance interconnects between complex wafers can increase the bandwidth of the search engine and reduce its power consumption.

雖然已經取得進展,但是可以做到進一步的改良,以促進具有堆疊端子的微電子封裝結構以及用於製造此種封裝的製程。 Although advances have been made, further improvements can be made to facilitate microelectronic package structures with stacked terminals and processes for making such packages.

根據本發明的一態樣,提供一種製造微電子組件的方法。在此種方法中,可處理一第一子組件,使得該第一子組件的導電第一連接器的末端突伸進入一暫時層中,該等第一連接器延伸於遠離該第一子組件的一第一支撐元件之一方向中。之後可形成該第一子組件的一第一絕緣結構,包含:流動一第一介電質材料至該暫時層與該支撐元件之間的個別第一連接器之間的空間中,並且至少部分地固化該第一介電質材料。之後可移除該暫時層,使得該等第一連接器的末端突伸超出該第一子組件的該第一絕緣結構的一表面。之後,可聯合該等第一連接器以及與其並置的一第二子組件的導電第二連接器,以形成一組件,其中該第一與第二子組件的至少一者具有至少一微電子元件係安裝至該個別的支撐元件的一朝內表 面。之後可形成一第二絕緣結構,包含:流動一第二介電質材料進入該等第二連接器的相鄰一者之間以及接合至其的該等第一連接器之間的空間中。 In accordance with an aspect of the present invention, a method of making a microelectronic assembly is provided. In this method, a first subassembly can be processed such that an end of the electrically conductive first connector of the first subassembly protrudes into a temporary layer, the first connectors extending away from the first subassembly One of the first support members is oriented in one direction. Forming a first insulating structure of the first subassembly, comprising: flowing a first dielectric material into a space between the temporary layer and the individual first connector between the support element, and at least partially The first dielectric material is cured. The temporary layer can then be removed such that the ends of the first connectors project beyond a surface of the first insulating structure of the first subassembly. Thereafter, the first connector and the conductive second connector of a second subassembly collocated therewith may be combined to form an assembly, wherein at least one of the first and second subassemblies has at least one microelectronic component Attached to the inner surface of the individual support element surface. A second insulating structure can then be formed comprising: flowing a second dielectric material into a space between adjacent ones of the second connectors and between the first connectors joined thereto.

根據本發明的另一態樣,提供一種製造一微電子組件的方法。此種方法可包含:將一第一子組件的導電第一塊的部分嵌入於一膜中,該等第一塊延伸於遠離該第一子組件的一第一支撐元件之一方向中。可形成一第一密封,包含:流動一第一密封劑進入該膜與該支撐元件之間的個別第一塊之間的空間中,並且至少部分地固化該第一密封劑。之後可移除該膜,使得該等第一塊突伸超出該第一密封的一表面。之後可聯合該第一子組件與一第二子組件,以形成一組件。該第二子組件可包含一第二支撐元件與導電連接器於其一表面處,其中該聯合包含:接合在超出該第一密封的位置處的該等第一塊於該第二子組件的該等導電連接器。該等子組件的至少一者可具有至少一微電子元件係安裝至該個別的支撐元件的一朝內表面。之後可形成一第二密封,包含:流動一第二密封劑進入該等導電連接器的相鄰一者以及接合至其的該等第一塊的該等部分之間的空間中,並且至少部分地固化該第二密封劑。 In accordance with another aspect of the present invention, a method of fabricating a microelectronic assembly is provided. The method can include embedding a portion of the electrically conductive first block of a first subassembly in a film, the first block extending in a direction away from one of the first support members of the first subassembly. A first seal can be formed comprising: flowing a first sealant into the space between the individual first blocks between the film and the support member and at least partially curing the first sealant. The film can then be removed such that the first pieces protrude beyond a surface of the first seal. The first subassembly and a second subassembly can then be combined to form a component. The second subassembly can include a second support member and a conductive connector at a surface thereof, wherein the combining includes: engaging the first block at the second subassembly at a position beyond the first seal The electrically conductive connectors. At least one of the subassemblies can have at least one microelectronic component mounted to an inwardly facing surface of the individual support component. Forming a second seal, comprising: flowing a second encapsulant into a space between an adjacent one of the electrically conductive connectors and the portions of the first block joined thereto, and at least a portion The second sealant is cured.

10‧‧‧微電子封裝 10‧‧‧Microelectronics package

12‧‧‧外部部件 12‧‧‧External components

14‧‧‧組件 14‧‧‧ components

16‧‧‧外部部件 16‧‧‧External components

21、22‧‧‧子組件 21, 22‧‧‧ subcomponents

101、105‧‧‧第一表面 101, 105‧‧‧ first surface

102‧‧‧第一支撐元件 102‧‧‧First support element

103、106‧‧‧第二表面 103, 106‧‧‧ second surface

104‧‧‧第二支撐元件 104‧‧‧Second support element

120‧‧‧微電子元件 120‧‧‧Microelectronic components

121‧‧‧凸塊 121‧‧‧Bumps

122‧‧‧前面 122‧‧‧ front

124‧‧‧接點 124‧‧‧Contacts

125‧‧‧面 125‧‧‧ face

126‧‧‧接點 126‧‧‧Contacts

127‧‧‧邊緣 127‧‧‧ edge

128‧‧‧主表面 128‧‧‧Main surface

129‧‧‧表面 129‧‧‧ surface

130‧‧‧微電子元件 130‧‧‧Microelectronic components

132‧‧‧邊緣表面 132‧‧‧Edge surface

134‧‧‧主表面 134‧‧‧Main surface

141‧‧‧端子 141‧‧‧ terminals

142、142'‧‧‧端子 142, 142'‧‧‧ terminals

144‧‧‧導電塊 144‧‧‧Electrical block

146‧‧‧接合元件 146‧‧‧ Engagement components

147‧‧‧接點 147‧‧‧Contacts

148‧‧‧接點 148‧‧‧Contacts

150‧‧‧密封 150‧‧‧ Seal

152‧‧‧第二密封 152‧‧‧Second seal

153、154‧‧‧表面 153, 154‧‧‧ surface

155‧‧‧開口 155‧‧‧ openings

156‧‧‧加強環 156‧‧‧ Strengthening ring

157‧‧‧部分 Section 157‧‧‧

159‧‧‧槽 159‧‧‧ slot

161‧‧‧第一連接器 161‧‧‧First connector

162、162b‧‧‧第二連接器 162, 162b‧‧‧ second connector

163、163'、164、164'‧‧‧端部 163, 163', 164, 164' ‧ ‧ end

166‧‧‧導電元件 166‧‧‧Conductive components

169‧‧‧第三連接器 169‧‧‧ third connector

171、172‧‧‧核心 171, 172‧‧‧ core

178、179‧‧‧方向 178, 179‧‧ Directions

180‧‧‧方向 180‧‧‧ Direction

181‧‧‧第一連接器(第一柱) 181‧‧‧First connector (first column)

182‧‧‧第二連接器(第二柱) 182‧‧‧Second connector (second column)

183、184‧‧‧垂直尺寸 183, 184‧‧‧ vertical dimensions

185、186‧‧‧寬度 185, 186 ‧ ‧ width

191‧‧‧第一連接器 191‧‧‧First connector

192‧‧‧第二連接器 192‧‧‧Second connector

210‧‧‧微電子封裝 210‧‧‧Microelectronics package

221‧‧‧第一連接器 221‧‧‧First connector

222‧‧‧第二連接器 222‧‧‧Second connector

231‧‧‧導電塊 231‧‧‧Electrical block

241‧‧‧第一端子 241‧‧‧First terminal

263‧‧‧端部 263‧‧‧ end

264、264'‧‧‧端部 264, 264'‧‧‧ end

281‧‧‧第一柱 281‧‧‧First column

282‧‧‧第二柱 282‧‧‧second column

285‧‧‧邊緣表面 285‧‧‧Edge surface

291‧‧‧導電塊 291‧‧‧Electrical block

302‧‧‧支撐元件 302‧‧‧Support components

320‧‧‧第二微電子元件 320‧‧‧Second microelectronic components

321‧‧‧子組件 321‧‧‧Subcomponents

352‧‧‧密封 352‧‧‧ Seal

381‧‧‧第一連接器 381‧‧‧First connector

382‧‧‧第二連接器 382‧‧‧Second connector

410‧‧‧微電子封裝 410‧‧‧Microelectronics package

500‧‧‧系統 500‧‧‧ system

501‧‧‧殼體 501‧‧‧shell

502‧‧‧電路平板 502‧‧‧ circuit board

504‧‧‧導體 504‧‧‧Conductor

506‧‧‧結構 506‧‧‧ structure

508、510‧‧‧電子部件 508, 510‧‧‧ Electronic components

511‧‧‧透鏡 511‧‧‧ lens

610‧‧‧微電子封裝 610‧‧‧Microelectronics package

650‧‧‧第一密封 650‧‧‧First seal

910‧‧‧微電子封裝 910‧‧‧Microelectronics package

950‧‧‧密封 950‧‧‧ Seal

952‧‧‧第二密封 952‧‧‧Second seal

953、954‧‧‧表面 953, 954‧‧‧ surface

962‧‧‧第二連接器 962‧‧‧Second connector

982‧‧‧金屬柱 982‧‧‧Metal column

1010‧‧‧微電子封裝 1010‧‧‧Microelectronics package

1110‧‧‧組件 1110‧‧‧ components

1210‧‧‧組件 1210‧‧‧ components

1252‧‧‧密封 1252‧‧‧ Seal

1310‧‧‧組件 1310‧‧‧ components

1410‧‧‧組件 1410‧‧‧ components

1510‧‧‧組件 1510‧‧‧ components

1550‧‧‧第三密封 1550‧‧‧ third seal

1708‧‧‧暫時層 1708‧‧‧ Temporary layer

1711‧‧‧內表面 1711‧‧‧ inner surface

1710、1712‧‧‧模具板 1710, 1712‧‧‧ mold board

1720‧‧‧空腔 1720‧‧‧ Cavity

1721‧‧‧第一子組件 1721‧‧‧First subcomponent

1723‧‧‧第一子組件 1723‧‧‧First subcomponent

1725‧‧‧第二子組件 1725‧‧‧Second subcomponent

1730‧‧‧導電元件 1730‧‧‧Conductive components

1732‧‧‧連接器 1732‧‧‧Connector

1734‧‧‧末端 End of 1734‧‧

1736‧‧‧最大高度 1736‧‧‧Maximum height

1740‧‧‧封裝 1740‧‧‧Package

1742‧‧‧絕緣結構 1742‧‧‧Insulation structure

1744‧‧‧表面 1744‧‧‧ surface

1752‧‧‧第三絕緣結構 1752‧‧‧ Third insulation structure

1756‧‧‧最大高度 1756‧‧‧Maximum height

1761‧‧‧子組件 1761‧‧ subcomponent

1762‧‧‧第二連接器 1762‧‧‧Second connector

1764‧‧‧末端 End of 1764‧‧

1765‧‧‧子組件 1765‧‧‧subcomponent

1767‧‧‧第二子組件 1767‧‧‧Second subcomponent

1768‧‧‧暫時層 1768‧‧‧temporary layer

1769‧‧‧內表面 1769‧‧‧ inner surface

1770、1772‧‧‧模具板 1770, 1772‧‧‧ mold board

1773‧‧‧表面 1773‧‧‧ surface

1774‧‧‧絕緣結構 1774‧‧‧Insulation structure

1780‧‧‧組件 1780‧‧‧ components

a、b‧‧‧間距 a, b‧‧‧ spacing

H‧‧‧間隙高度 H‧‧‧ gap height

第1A圖為本案較佳實施例之微電子封裝剖面圖。 1A is a cross-sectional view of a microelectronic package of the preferred embodiment of the present invention.

第1B圖為第1A圖俯視平面圖,複數個端子位於支撐元件的表面。 Fig. 1B is a top plan view of Fig. 1A with a plurality of terminals on the surface of the support member.

第2圖為本案較佳實施例之微電子封裝剖面圖。 Figure 2 is a cross-sectional view of the microelectronic package of the preferred embodiment of the present invention.

第3圖為本案較佳實施例之微電子組件剖面圖。 Figure 3 is a cross-sectional view of the microelectronic assembly of the preferred embodiment of the present invention.

第4A圖為第1A-B圖之剖面圖,示意本發明的實施例的變化例之微電子封裝。 4A is a cross-sectional view of the first A-B diagram, showing a microelectronic package of a variation of the embodiment of the present invention.

第4B圖為第4A圖之俯視平面圖,微電子封裝之堆疊端子位於支撐元件的表面。 Figure 4B is a top plan view of Figure 4A with the stacked terminals of the microelectronic package on the surface of the support member.

第5圖為本案較佳實施例之微電子封裝剖面圖。 Figure 5 is a cross-sectional view of a microelectronic package of the preferred embodiment of the present invention.

第6圖為本案較佳實施例之微電子封裝剖面圖。 Figure 6 is a cross-sectional view of the microelectronic package of the preferred embodiment of the present invention.

第7圖為本案較佳實施例之微電子封裝剖面圖。 Figure 7 is a cross-sectional view of the microelectronic package of the preferred embodiment of the present invention.

第8圖為本案較佳實施例之微電子組件剖面圖。 Figure 8 is a cross-sectional view of the microelectronic assembly of the preferred embodiment of the present invention.

第9圖為本案較佳實施例之微電子封裝剖面圖。 Figure 9 is a cross-sectional view of the microelectronic package of the preferred embodiment of the present invention.

第10圖為本案較佳實施例之微電子封裝剖面圖。 Figure 10 is a cross-sectional view of a microelectronic package of the preferred embodiment of the present invention.

第11圖為本案較佳實施例之微電子封裝之方法中的階段剖面圖。 Figure 11 is a cross-sectional view of a stage in a method of microelectronic packaging in accordance with a preferred embodiment of the present invention.

第12圖為本案較佳實施例之第11圖階段之後,製造微電子封裝之方法中的階段剖面圖。 Figure 12 is a cross-sectional view of the stage in the method of fabricating a microelectronic package after the stage of Figure 11 of the preferred embodiment of the present invention.

第13圖為本案較佳實施例之第12圖的階段之後,製造微電子封裝之方法中的階段剖面圖。 Figure 13 is a cross-sectional view showing the stage in the method of fabricating a microelectronic package after the stage of Fig. 12 of the preferred embodiment of the present invention.

第14圖為本案較佳實施例之第11圖變化例的微電子封裝之方法中的階段剖面圖。 Figure 14 is a cross-sectional view showing the stage of the method of the microelectronic package of the modification of the eleventh embodiment of the preferred embodiment of the present invention.

第15圖為本案較佳實施例之製造微電子封裝之方法中的階段剖面圖。 Figure 15 is a cross-sectional view of a stage in a method of fabricating a microelectronic package in accordance with a preferred embodiment of the present invention.

第16圖為本案較佳實施例之第15圖階段後,製造微電子封裝之方法中的階段剖面圖。 Figure 16 is a cross-sectional view showing the stage in the method of fabricating a microelectronic package after the fifteenth stage of the preferred embodiment of the present invention.

第17圖為本案較佳實施例之第16圖階段後,製造微電子封裝之方法中 的階段剖面圖。 Figure 17 is a diagram showing the method of manufacturing a microelectronic package after the stage of the 16th embodiment of the preferred embodiment of the present invention. Stage profile view.

第18圖為本案較佳實施例之第15圖變化例的微電子封裝之方法中的階段剖面圖。 Figure 18 is a cross-sectional view showing the stage of the method of the microelectronic package of the modification of the fifteenth embodiment of the preferred embodiment of the present invention.

第19圖為本案較佳實施例之微電子封裝剖面圖。 Figure 19 is a cross-sectional view of the microelectronic package of the preferred embodiment of the present invention.

第20圖為本案較佳實施例之微電子封裝剖面圖。 Figure 20 is a cross-sectional view of the microelectronic package of the preferred embodiment of the present invention.

第21圖為本案較佳實施例之微電子組件之方法中的階段剖面圖。 Figure 21 is a cross-sectional view of the stage in the method of the microelectronic assembly of the preferred embodiment of the present invention.

第22圖為本案較佳實施例之第21圖的方法形成的微電子組件剖面圖。 Figure 22 is a cross-sectional view showing a microelectronic assembly formed by the method of Figure 21 of the preferred embodiment of the present invention.

第23圖為本案較佳實施例之第21圖的變化例。 Fig. 23 is a modification of Fig. 21 of the preferred embodiment of the present invention.

第24圖為本案較佳實施例之第21圖的變化例。 Figure 24 is a variation of Figure 21 of the preferred embodiment of the present invention.

第25圖為本案較佳實施例之第24圖所示方法形成的微電子組件。 Figure 25 is a diagram showing a microelectronic assembly formed by the method of Figure 24 of the preferred embodiment of the present invention.

第26圖為本案較佳實施例之第11-14圖變化例的微電子組件之方法中的階段剖面圖。 Figure 26 is a cross-sectional view showing the stage of the method of the microelectronic assembly of the modification of the preferred embodiment 11-14.

第27圖為本案較佳實施例之第26圖所示方法形成的微電子組件。 Figure 27 is a diagram showing a microelectronic assembly formed by the method of Figure 26 of the preferred embodiment of the present invention.

第28-29圖為本案較佳實施例之第11-14圖變化例的微電子組件之方法中的階段。 Figures 28-29 show the stages in the method of the microelectronic assembly of the variation of Figures 11-14 of the preferred embodiment of the present invention.

第30圖為本案較佳實施例之第28-29圖所示方法形成的微電子組件。 Figure 30 is a diagram showing the microelectronic assembly formed by the method of Figures 28-29 of the preferred embodiment of the present invention.

第31-36圖為本案較佳實施例之微電子組件之方法中的連續階段剖面圖。 31-36 are sequential cross-sectional views of the method of the microelectronic assembly of the preferred embodiment of the present invention.

第37-40圖為本案較佳實施例之第31-36圖變化例的微電子組件之方法中的連續階段剖面圖。 37-40 are cross-sectional views of successive stages in a method of a microelectronic assembly in accordance with a variation of the 31st to 36th preferred embodiments of the preferred embodiment.

第41圖為本案較佳實施例之系統示意圖。 Figure 41 is a schematic diagram of the system of the preferred embodiment of the present invention.

因此,本發明實施例提供改良的組件,其包含微電子元件且具有第一端子與第二端子(例如,頂部端子與底部端子),其中電性耦接頂部端子與底部端子的垂直互連可提供所欲的間隙高度,同時也允許垂直互連在水平方向中以所欲的間距緊密封裝,水平方向平行於組件中的微電子元件的表面。參見第1A-B圖的微電子組件或微電子封裝,在一範例中,支撐元件第二表面間的間隙高度H大於在平行於第一支撐元件的第二表面的至少一方向中的第一連接器的間距「a」。在另一範例中,間隙高度可等於或大於該間距的1.5倍。 Accordingly, embodiments of the present invention provide an improved assembly including a microelectronic component and having a first terminal and a second terminal (eg, a top terminal and a bottom terminal), wherein the vertical interconnection of the top terminal and the bottom terminal is electrically coupled Providing the desired gap height while also allowing the vertical interconnects to be tightly packed in the horizontal direction at the desired pitch, the horizontal direction being parallel to the surface of the microelectronic component in the assembly. Referring to the microelectronic assembly or microelectronic package of Figures 1A-B, in one example, the gap height H between the second surfaces of the support members is greater than the first of at least one of the directions parallel to the second surface of the first support member. The pitch of the connector is "a". In another example, the gap height can be equal to or greater than 1.5 times the pitch.

第1A圖進一步可知,微電子封裝10包含第一支撐元件102與第二支撐元件104。每一支撐元件可為例如封裝基板,例如晶片載體或介電質元件或二者結合或更多個介電質、半導體與導電材料的結構,其上可提供導電結構,如端子、線跡、接點、與通孔。例如,一兩個支撐元件可為包含片狀或板狀的介電質元件,其包含無機或有機介電質材料的至少一者,且其可主要包含無機材料或主要包含聚合物材料,或者其可為包含無機與聚合物材料兩者的合成結構。因此,例如,但非限制,一或兩個支撐元件可包含介電質元件,其包含聚合物材料,例如聚酰亞胺、聚酰胺、環氧樹脂、熱塑性材料、熱固性材料等。或者,一或兩個支撐元件可包含介電質元件,其包含無機介電質材料,例如矽的氧化物、矽的氮化物、矽的碳化物、氮氧化矽、氧化鋁,且一或兩個支撐元件可包含半導體材料(例如矽、鍺、或碳等),或一或更多個此種無機材料的組合。在另一範例中,一或兩個支撐元件可包含介電質元件,其為一或更多個聚合物材料與一或 更多個無機材料(例如上述的材料)的組合。在具體的範例中,一或兩個支撐元件可具有玻璃強化的環氧樹脂結構,例如通常稱為「FR-4」或「BT樹脂」的板結構。在另一範例中,一或兩個支撐元件可實質上由聚合物材料組成,例如聚酰亞胺,舉例來說。一或兩個支撐元件可包含一或更多個層的順應性材料,其可在一些實例中可曝露於此種支撐元件的第一表面、第二表面、或第一與第二表面兩者處。順應性材料在一些實例中可包含聚酰亞胺、聚酰胺,其通常具有小於2.0千兆帕斯卡(GPa)的楊氏模量(Young modulus),或者在一些實例中,順應性材料可包含具有明顯低於(例如,遠低於)1.0GPa的楊氏模量之彈性體。 As further seen in FIG. 1A, the microelectronic package 10 includes a first support member 102 and a second support member 104. Each support element can be, for example, a package substrate, such as a wafer carrier or a dielectric element or a combination of two or more dielectric, semiconductor, and conductive materials, on which conductive structures such as terminals, traces, Contacts, and through holes. For example, one or two supporting members may be a dielectric element comprising a sheet or a plate, which comprises at least one of an inorganic or organic dielectric material, and which may mainly comprise or mainly comprise a polymeric material, or It can be a synthetic structure comprising both inorganic and polymeric materials. Thus, for example, without limitation, one or both of the support elements can comprise a dielectric element comprising a polymeric material such as a polyimide, a polyamide, an epoxy, a thermoplastic, a thermoset, and the like. Alternatively, one or both of the support elements may comprise a dielectric element comprising an inorganic dielectric material such as an oxide of cerium, a nitride of cerium, a carbide of cerium, cerium oxynitride, aluminum oxide, and one or two The support elements can comprise a semiconductor material (e.g., tantalum, niobium, or carbon, etc.), or a combination of one or more such inorganic materials. In another example, one or both of the support elements can comprise a dielectric element that is one or more polymeric materials and one or A combination of more inorganic materials, such as the materials described above. In a specific example, one or both of the support members may have a glass reinforced epoxy structure, such as a plate structure commonly referred to as "FR-4" or "BT resin." In another example, one or both of the support elements can be substantially composed of a polymeric material, such as polyimide, for example. One or both of the support members may comprise one or more layers of compliant material, which in some instances may be exposed to the first surface, the second surface, or both the first and second surfaces of such support members At the office. The compliant material may, in some examples, comprise polyimide, polyamide, which typically has a Young modulus of less than 2.0 Giga Pascals (GPa), or in some instances, the compliant material may comprise An elastomer that is significantly lower (eg, well below) Young's modulus of 1.0 GPa.

如同第1A圖中所見的,每一支撐元件具有第一與第二相對面向的表面。當組裝在封裝10中,支撐元件的第一表面101、105向外面離彼此,且第二表面103、106向內面向彼此。微電子元件120(其可為未封裝或已封裝的半導體晶片)安裝至一或兩個支撐元件102、104的第二表面。在一具體實施例中,微電子元件可為半導體晶片,具有額外的導電結構在其耦接至晶片接墊的面處。雖然未繪示,在一實施例中,第二微電子元件可安裝在面離支撐元件104之微電子元件120的表面129上方的空間中。第二微電子元件可定位於第一支撐元件102的表面103與表面129之間。 As seen in Figure 1A, each support element has first and second opposing facing surfaces. When assembled in the package 10, the first surfaces 101, 105 of the support elements are facing away from each other, and the second surfaces 103, 106 face inwardly toward each other. Microelectronic component 120 (which may be an unpackaged or packaged semiconductor wafer) is mounted to the second surface of one or both support members 102,104. In a specific embodiment, the microelectronic component can be a semiconductor wafer having an additional conductive structure at its face that is coupled to the die pad. Although not shown, in one embodiment, the second microelectronic component can be mounted in a space above the surface 129 of the microelectronic component 120 of the support component 104. The second microelectronic element can be positioned between the surface 103 of the first support element 102 and the surface 129.

微電子元件可電性耦接第二支撐元件104表面106的導電元件。當在本揭示案中參照部件使用時,例如中介層、微電子元件、電路平板、基板等,導電元件在部件的表面「處」的陳述係表示:當部件未組裝於任何其他元件時,導電元件可用於接觸於一理論點,該理論點移動於垂直於部件的表面的方向中、從部件的外部朝向部件的表面。因此,在基板 的表面處的端子或其他導電元件可從此種表面突伸;可齊平於此種表面;或可相對於此種表面凹陷於基板中的孔或凹部。在一範例中,部件的「表面」可為介電質結構的表面;然而,在具體的實施例中,表面可為其他材料,例如金屬或其他導電材料或半導體材料。 The microelectronic component can be electrically coupled to the conductive component of the surface 106 of the second support component 104. When used in reference to a component in this disclosure, such as an interposer, microelectronic component, circuit board, substrate, etc., the statement that the conductive component is "on" the surface of the component means that the component is electrically conductive when it is not assembled in any other component. The component can be used to contact a theoretical point that moves in a direction perpendicular to the surface of the component, from the exterior of the component toward the surface of the component. Therefore, on the substrate Terminals or other conductive elements at the surface may protrude from such surfaces; may be flush with such surfaces; or may be recessed into holes or recesses in the substrate relative to such surfaces. In one example, the "surface" of the component can be the surface of the dielectric structure; however, in particular embodiments, the surface can be other materials such as metal or other conductive or semiconductor materials.

在第1A圖中,平行於第一支撐元件的第一表面101的方向在本文中係稱為第一與第二橫向方向178、179或「水平」或「橫向」方向,而垂直於第一表面的方向180在本文中係稱為向上或向下的方向,且在本文中也稱為「垂直」方向。本文中所參考的方向係該等結構所參考的參考框架。因此,這些方向可位於正常或重力參考框架的任何定向處。一特徵係比另一特徵設置在「一表面之上」的較高高度處的陳述係表示:一特徵係比另一特徵在遠離該表面的相同正交方向中的較大距離處。相反地,一特徵係係比另一特徵設置在「一表面之上」的較低高度處的陳述係表示:一特徵係比另一特徵在遠離該表面的相同正交方向中的較小距離處。 In FIG. 1A, the direction parallel to the first surface 101 of the first support member is referred to herein as the first and second lateral directions 178, 179 or the "horizontal" or "lateral" direction, and perpendicular to the first The direction 180 of the surface is referred to herein as the upward or downward direction and is also referred to herein as the "vertical" direction. The directions referred to herein are reference frames referenced by such structures. Thus, these directions can be located at any orientation of the normal or gravity reference frame. A statement that a feature is placed at a higher height above "a surface" than another feature means that one feature is at a greater distance than the other feature in the same orthogonal direction away from the surface. Conversely, a statement that a feature system is placed at a lower height above "a surface" than another feature means that a feature is a smaller distance than the other feature in the same orthogonal direction away from the surface. At the office.

因此,在第1A圖的範例中,微電子元件120可為覆晶(Flip-Chip),連接至支撐元件104的表面106處的接點126。微電子元件120具有複數個接點124在前面122處,前面122面向第二支撐元件104的第二表面106,接點124面向並且透過凸塊121而接合於第二支撐元件的對應接點126,凸塊121可包含接合金屬,或者其可包含其他類型的接合元件,例如微柱、柱等。接點可以以延伸於第一方向中的一或更多個列、延伸於橫越第一方向的第二方向中的一或更多個行、或一或更多個列與一或更多個行兩者的方式配置在前面122處。此種接點可設置在方向178、179中的任何位置處,或者可設置在與微電子元件的一或更多個邊緣127相鄰之一或更多個 列中、一或更多個行中、或者一或更多個列與一或更多個行中。在一具體範例中,接點124可以以區域陣列(具有兩或更多個列的接點且具有兩或更多個行的接點)分佈橫越微電子元件的前面的至少一部分。底部填充115可設置圍繞該等連接的個別一者(例如,凸塊121),其在一些實例中,機構上可強化該等連接。 Thus, in the example of FIG. 1A, microelectronic element 120 can be a flip-chip that is connected to contact 126 at surface 106 of support element 104. Microelectronic element 120 has a plurality of contacts 124 at front face 122, front face 122 facing second surface 106 of second support member 104, contact 124 facing and passing through bump 121 to engage corresponding contact 126 of second support member The bumps 121 may comprise bonding metals, or they may comprise other types of bonding elements, such as micropillars, posts, and the like. The junction may be in one or more columns extending in the first direction, one or more rows extending in a second direction across the first direction, or one or more columns and one or more The way of both lines is configured at the front 122. Such contacts may be disposed at any of the directions 178, 179 or may be disposed adjacent one or more of the one or more edges 127 of the microelectronic element In a column, in one or more rows, or in one or more columns and in one or more rows. In one specific example, the contacts 124 can be distributed across at least a portion of the front surface of the microelectronic element in an array of regions (contacts having two or more columns and having two or more rows). The underfill 115 can be positioned around an individual of the connections (e.g., bumps 121), which in some instances can be reinforced on the mechanism.

或者,取代覆晶連接,接點124可配置在對準於孔或「接合窗(Bond Window)」(未圖示)之一或更多個列的接點及/或一或更多個行的接點內的位置處,孔或「接合窗」延伸於支撐元件104的第一與第二表面105、106之間。在此種實例中,微電子元件的接點124可透過接合於接點124的引線而耦接於端子,例如第二支撐元件104的第一表面105處的端子142、142'。在一具體範例中,引線可為導線引線(未圖示),例如打線接合,其延伸通過孔並且接合至接點124與第一表面105處的對應接點(未圖示)。在另一範例中,引線可為下述的引線:每一引線包含沿著第一或第二表面105、106延伸作為線跡的第一部分,以及整合於第一部分的第二部分,第二部分從該線跡延伸進入孔的區域並且接合至接點。 Alternatively, instead of a flip chip connection, the contacts 124 may be disposed in contacts and/or one or more rows aligned with one or more columns of holes or "Bond Window" (not shown) At the location within the joint, the aperture or "joining window" extends between the first and second surfaces 105, 106 of the support member 104. In such an example, the contacts 124 of the microelectronic component can be coupled to the terminals, such as the terminals 142, 142' at the first surface 105 of the second support component 104, through the leads that are bonded to the contacts 124. In one specific example, the leads can be wire leads (not shown), such as wire bonds, that extend through the holes and are joined to corresponding contacts (not shown) at the contacts 124 and the first surface 105. In another example, the leads can be leads that each include a first portion that extends along the first or second surface 105, 106 as a stitch, and a second portion that is integrated into the first portion, the second portion From this stitch extends into the area of the hole and is joined to the joint.

在又另一範例中,雖然未圖示,微電子元件的後表面129可向後接合(Back-Bonded)至第二支撐元件的第二表面106,且微電子元件的前面122可改為面離支撐元件104的第一表面106,其中微電子元件的接點124面離第二表面106。在此種範例中,接點124可透過延伸於前面122上方並且延伸超出微電子元件的邊緣127之導電結構,而電性耦接於第二支撐元件的第二表面106處的對應接點。 In yet another example, although not shown, the back surface 129 of the microelectronic component can be back-bound to the second surface 106 of the second support member, and the front surface 122 of the microelectronic component can be replaced The first surface 106 of the support member 104, wherein the contacts 124 of the microelectronic element face away from the second surface 106. In this example, the contacts 124 are electrically coupled to corresponding contacts at the second surface 106 of the second support member through a conductive structure that extends above the front surface 122 and extends beyond the edge 127 of the microelectronic component.

如同第1A圖中進一步所見的,微電子封裝10可包含單塊式 密封150(Monolithic Encapsulation),密封150形成接觸於第一與第二支撐元件的支撐元件的第二表面103或106,且密封150形成接觸於下述至少一者:第一與第二支撐元件的另一支撐元件的第二表面,以及形成接觸於另一支撐元件的第二表面之第二密封。密封150可形成接觸於第一與第二支撐元件102、104的每一者的第二表面103、106。 As further seen in FIG. 1A, the microelectronic package 10 can comprise a monolithic a seal 150 that forms a second surface 103 or 106 that contacts the support members of the first and second support members, and the seal 150 forms contact with at least one of: first and second support members a second surface of the other support member and a second seal forming a second surface that contacts the other support member. The seal 150 can form a second surface 103, 106 that contacts each of the first and second support members 102, 104.

如同第1A圖中進一步所見的,微電子封裝10包含成對的導電第一連接器161係突伸於第一支撐元件102的第二表面103之上,導電第一連接器161對準於且機械性與電性耦接於對應的導電第二連接器162,導電第二連接器162突伸於第二支撐元件104的第二表面106之上。第一支撐元件102的第一表面101處的第一封裝端子141透過對準於且電性耦接於(例如,接合於)第二連接器162之個別的成對的第一連接器161,而電性耦接於第二支撐元件104的第一表面105處的對應第二封裝端子142。 As further seen in FIG. 1A, the microelectronic package 10 includes a pair of electrically conductive first connectors 161 projecting over the second surface 103 of the first support member 102, the electrically conductive first connector 161 being aligned and Mechanically and electrically coupled to the corresponding conductive second connector 162 , the conductive second connector 162 protrudes above the second surface 106 of the second support member 104 . The first package terminal 141 at the first surface 101 of the first support member 102 is permeable to an individual pair of first connectors 161 that are aligned and electrically coupled to (eg, bonded to) the second connector 162, The second package terminal 142 is electrically coupled to the first surface 105 of the second support member 104 .

如同第1A圖中進一步所見的,第一連接器與第二連接器的至少一者包含導電塊(Masses),例如接合金屬塊,例如錫、銦、焊料或共熔材料,或者嵌入在聚合物材料中的金屬顆粒的導電基質材料。在具體實施例中,第一連接器、第二連接器、或兩者可實質上由焊料組成。在第1圖所示的具體實施例中,第一連接器與第二連接器可各自包含接合金屬。在具體的範例中,第一與第二連接器的一或兩者可包含固體核心(例如,核心171或核心172),核心上可設置接合金屬。此種固體核心171、172可用於促進或維持第一與第二支撐元件102、104的第二表面103、106之間的預定間隔。固體核心可為導電、半導電或介電質材料,或一或更多個此種材料的組合。在具體的範例中,固體核心可由非焊料材料製成,該非焊料材料具 有焊料可濕性並且可塗覆有焊料。在一範例中,固體核心可實質上由銅或具有熔點比第一與第二連接器接合於彼此時的接合溫度更高的其他導電材料組成,如同將在下面敘述的。 As further seen in FIG. 1A, at least one of the first connector and the second connector comprises a conductive mass, such as a bonding metal block, such as tin, indium, solder or a eutectic material, or embedded in a polymer. A conductive matrix material of metal particles in the material. In a particular embodiment, the first connector, the second connector, or both may consist essentially of solder. In the particular embodiment illustrated in Figure 1, the first connector and the second connector may each comprise a bonding metal. In a specific example, one or both of the first and second connectors may comprise a solid core (eg, core 171 or core 172) on which the bonding metal may be disposed. Such solid cores 171, 172 can be used to promote or maintain a predetermined spacing between the second surfaces 103, 106 of the first and second support members 102, 104. The solid core can be a conductive, semiconductive or dielectric material, or a combination of one or more such materials. In a specific example, the solid core may be made of a non-solder material having It has solder wettability and can be coated with solder. In one example, the solid core may consist essentially of copper or other electrically conductive material having a higher melting temperature than when the first and second connectors are joined to each other, as will be described below.

在一具體實施例中,固體核心(Solid cores)可包含或實質上由具有熔點高於接合溫度的焊料組成,並且因此可具有比塗覆固體核心的焊料的熔點更高的熔點。在另一範例中,固體核心可實質上由玻璃、陶瓷或半導體材料組成。具有固體核心171的第一連接器可對準且接合於不具有固體核心的第二連接器。相反地,具有固體核心172的第二連接器可對準且接合於不具有固體核心的第一連接器。在另一實施例中,雖然沒有繪示,具有固體核心的第一連接器可對準且接合於具有固體核心的第二連接器。 In a specific embodiment, the solid cores may comprise or consist essentially of a solder having a melting point above the bonding temperature, and thus may have a higher melting point than the melting point of the solder coating the solid core. In another example, the solid core can consist essentially of a glass, ceramic or semiconductor material. A first connector having a solid core 171 can be aligned and bonded to a second connector that does not have a solid core. Conversely, a second connector having a solid core 172 can be aligned and bonded to a first connector that does not have a solid core. In another embodiment, although not shown, a first connector having a solid core can be aligned and bonded to a second connector having a solid core.

在本文提供的各種範例中,可看出,第一連接器與第二連接器可分別具有端部(ends)163、164,端部163、164由在第一與第二支撐元件的第二表面之上的它們的最大高度來定義,且第一連接器的端部163可對準且接合於第二連接器的端部164。如同第1A圖中進一步所見的,在一範例中,第一支撐元件102的第一表面處的第一端子141之間的間距「a」可相同於第二支撐元件104的第一表面處的第二端子142之間的間距「a」。 In various examples provided herein, it can be seen that the first connector and the second connector can have ends 163, 164, respectively, and the ends 163, 164 are second by the first and second support members. Their maximum height above the surface is defined and the end 163 of the first connector can be aligned and joined to the end 164 of the second connector. As further seen in FIG. 1A, in an example, the spacing "a" between the first terminals 141 at the first surface of the first support member 102 can be the same as at the first surface of the second support member 104. The spacing between the second terminals 142 is "a".

參見第2圖,在微電子封裝210的另一範例中,第一連接器181、第二連接器182或兩者可包含實質上剛性的實心金屬柱(Rigid solid metal posts),實心金屬柱突伸於個別的支撐元件的第二表面之上。在一範例中,柱可實質上由銅組成。通常,柱具有在微電子組件的厚度的垂直方向180中的垂直尺寸183、184。垂直尺寸通常的範圍為50與500微米之間。每一柱的垂直尺寸通常大於在第二方向178中的此種柱的個別寬度185或186 的一半,第二方向178平行於柱所延伸自的第一部件或第二部件的平面。在具體的實施例中,柱可透過包含蝕刻的處理來形成,以從金屬層移除材料,如此可促進製做具有第一柱181的封裝,第一柱181的端部163'具有高度的共平面性。類似地,此種處理可促進製做具有第二柱182的封裝,第二柱182的端部164'具有高度的共平面性。一般的蝕刻處理傾向於形成截頭圓錐形形狀的柱,因為材料移除在垂直180與橫向方向178、179兩者中進行。然而,某些減化的處理可減少橫向方向中的材料移除的程度,使得以此方法所形成的柱可具有較大程度的圓柱形形狀。在又另一範例中,藉由電鍍金屬至暫時層(例如光阻遮罩)的開口中,且然後移除暫時層,可形成柱。實心或空心的金屬柱可產生自此種電鍍處理。 Referring to FIG. 2, in another example of the microelectronic package 210, the first connector 181, the second connector 182, or both may comprise substantially rigid solid metal posts (Rigid solid metal posts), solid metal studs Extending over the second surface of the individual support members. In an example, the post can consist essentially of copper. Typically, the posts have vertical dimensions 183, 184 in the vertical direction 180 of the thickness of the microelectronic assembly. Vertical dimensions typically range between 50 and 500 microns. The vertical dimension of each column is typically greater than the individual width 185 or 186 of such a column in the second direction 178. Half of the second direction 178 is parallel to the plane of the first or second component from which the post extends. In a particular embodiment, the post may be formed by a process comprising etching to remove material from the metal layer, which may facilitate fabrication of the package having the first post 181, the end 163' of the first post 181 having a height Coplanarity. Similarly, such treatment can facilitate the fabrication of a package having a second post 182 having a high degree of coplanarity. A typical etching process tends to form a frustoconical shaped column because material removal occurs in both the vertical 180 and lateral directions 178, 179. However, certain reduction treatments may reduce the extent of material removal in the lateral direction such that the pillars formed in this manner may have a greater degree of cylindrical shape. In yet another example, a pillar can be formed by plating a metal into an opening of a temporary layer (eg, a photoresist mask) and then removing the temporary layer. Solid or hollow metal posts can be produced from such plating processes.

金屬柱所接合之另一支撐元件的個別第一或第二連接器191、192可包含導電塊,例如接合金屬(Bond metal),例如焊料、錫、銦或共熔材料。在一範例中,第一連接器221、第二連接器222或兩者可包含柱狀凸塊,柱狀凸塊突伸於個別的支撐元件的第二表面之上。在具體的範例中,柱狀凸塊可為金、銅,或者可實質上由銅組成。在一範例中,金屬(例如,鈀、鈦、鎢、鉭、鈷、鎳、或導電金屬化合物,例如一或更多個此種金屬的化合物)的電鍍塗覆或阻障層可存在於柱狀凸塊以及其所耦接的導電塊231之界面表面處。在第2圖與本文的許多其他圖式中,封裝210的其他元件與端子可從所示的特定視圖省略,但是它們仍然可存在。 The individual first or second connectors 191, 192 of the other support element to which the metal posts are joined may comprise a conductive block, such as a bond metal, such as solder, tin, indium or a eutectic material. In an example, the first connector 221, the second connector 222, or both may include stud bumps that protrude above the second surface of the individual support members. In a specific example, the stud bumps can be gold, copper, or can be substantially composed of copper. In an example, an electroplating coating or barrier layer of a metal (eg, palladium, titanium, tungsten, tantalum, cobalt, nickel, or a conductive metal compound, such as one or more compounds of such a metal) may be present in the column At the interface surface of the bump and the conductive block 231 to which it is coupled. In FIG. 2 and many other figures herein, other components and terminals of package 210 may be omitted from the particular views shown, but they may still be present.

第3圖為微電子封裝10的組件14,其中外部部件12(External component)堆疊在封裝10之上並且電性耦接於其第一端子141。例如,外部部件12可具有接點148,接點148透過接合金屬的導電塊144(例如錫、銦、 焊料、或共熔金屬合成物等)而接合至第一端子141。在一範例中,外部部件12可為具有線跡與接點在其上的電路平板,且其可具有額外的部件在其中或耦接至其。在一些進一步的範例中,外部部件可為已封裝或未封裝的微電子元件。例如,部件12可為包含第二微電子元件320的微電子封裝,第二微電子元件320具有一組接點148接合於端子141。 3 is an assembly 14 of a microelectronic package 10 in which an external component 12 is stacked over the package 10 and electrically coupled to its first terminal 141. For example, the outer member 12 can have a contact 148 that is bonded to a conductive block 144 of metal (eg, tin, indium, Solder, or eutectic metal composition, etc.) is bonded to the first terminal 141. In an example, the outer component 12 can be a circuit slab having stitches and contacts thereon, and it can have additional components therein or coupled thereto. In some further examples, the external component can be a packaged or unpackaged microelectronic component. For example, component 12 can be a microelectronic package that includes a second microelectronic component 320 having a set of contacts 148 bonded to terminal 141.

如同第3圖中進一步所示的,微電子封裝10可具有導電接合元件146(Conductive joining elements),例如接合金屬塊(例如,焊料、錫、銦、或共熔材料,或附接至第二端子142的其他此種材料),接合元件146用於接合微電子封裝10至外部部件16的接點147。外部部件16在一些實例中可為具有線跡與接點在其上的電路平板,且其可具有額外的部件在其中或耦接至其。在一些進一步的範例中,外部部件可為已封裝或未封裝的微電子元件。 As further shown in FIG. 3, the microelectronic package 10 can have conductive joining elements 146, such as bonding metal blocks (eg, solder, tin, indium, or eutectic materials, or attached to the second). Other such materials of terminal 142), bonding element 146 is used to bond microelectronic package 10 to contact 147 of external component 16. The outer component 16 can be, in some examples, a circuit slab having stitches and contacts thereon, and it can have additional components therein or coupled thereto. In some further examples, the external component can be a packaged or unpackaged microelectronic component.

第4A-B圖為第1A-B圖微電子封裝的變化例,微電子封裝410中,第二方向178的第一端子141的間距「b」可不同於在第二方向的第二端子的間距「a」。第一端子141的間距也可不同於在第三方向179中的第二端子的間距,第三方向179平行於第一表面101且橫越第一與第二方向。因此,如同所示,第一端子的間距可大於在第二方向或第三方向或兩者中的第二端子的間距。或者,第一端子的間距可小於在第二方向或第三方向或兩者中的第二端子的間距。在本文提供的任何或所有實施例中,第一端子與第二端子的間距之間的關係可如同本文相關於上面第1A-B圖所述的,或者如同本文相關於第4A與4B圖所述的。 4A-B is a variation of the microelectronic package of FIG. 1A-B. In the microelectronic package 410, the pitch "b" of the first terminal 141 in the second direction 178 may be different from the second terminal in the second direction. The spacing is "a". The pitch of the first terminals 141 may also be different from the pitch of the second terminals in the third direction 179, which is parallel to the first surface 101 and traverses the first and second directions. Thus, as shown, the pitch of the first terminals may be greater than the pitch of the second terminals in the second or third direction or both. Alternatively, the pitch of the first terminals may be smaller than the pitch of the second terminals in the second direction or the third direction or both. In any or all of the embodiments provided herein, the relationship between the spacing of the first terminal and the second terminal can be as described herein in relation to Figures 1A-B above, or as described herein in relation to Figures 4A and 4B. Said.

第5圖為第1A-B圖微電子封裝的變化例,其中第一與第二連 接器係繪示為實質上剛性實心金屬的第一柱281與第二柱282之形式,第一柱281與第二柱282的每一者可具有如同上面相關於第2圖所述的結構。但是,在此範例中,第一柱281的端部263對準於且接合於第二柱282的對應端部264。在所示的範例中,接觸於柱的端部與邊緣表面285之導電塊291可接合於每一對的第一與第二柱。然而,在具體的範例中,端部281、282可透過金屬至金屬的接合或擴散接合而接合在一起,而不需要使用焊料。 Figure 5 is a variation of the microelectronic package of Figure 1A-B, where the first and second connections The connector is depicted in the form of a first post 281 and a second post 282 of substantially rigid solid metal, each of the first post 281 and the second post 282 having a structure as described above in relation to FIG. . However, in this example, the end 263 of the first post 281 is aligned with and engages the corresponding end 264 of the second post 282. In the illustrated example, the conductive bumps 291 that contact the ends of the posts and the edge surfaces 285 can engage the first and second posts of each pair. However, in a particular example, the ends 281, 282 can be joined together by metal to metal bonding or diffusion bonding without the use of solder.

第5圖進一步說明,連接器(例如,突伸於第二支撐元件104的第二表面之上的第二連接器382)可為實質上剛性實心金屬柱之形式,且第一連接器381可藉由沉積金屬來接觸於第二連接器382的端部264'而形成,例如藉由電鍍金屬來接觸於端部264'。在一範例中,第一端子241可藉由電鍍處理而形成,電鍍處理在同一時間形成第一連接器381與第一端子的金屬層。 Figure 5 further illustrates that the connector (e.g., the second connector 382 that protrudes above the second surface of the second support member 104) can be in the form of a substantially rigid solid metal post, and the first connector 381 can Contact is formed by depositing metal to contact end 264' of second connector 382, such as by plating metal to contact end 264'. In one example, the first terminal 241 can be formed by a plating process that forms a metal layer of the first connector 381 and the first terminal at the same time.

第6圖為第1A-B圖或第4A-B圖的變化例,微電子封裝610包含第一與第二密封650、152。在一範例中,例如連接器161或連接器171的第一連接器可部分密封在第二密封152內,其中第一連接器的端部163接合於對應的第二連接器(例如連接器162或連接器172)的端部164,以提供第一與第二支撐元件之間的導電路徑。在此實例中,在第一連接器接合於第二連接器之後,可形成單塊式密封650,使得單塊式密封形成接觸於微電子元件120的面125,面125面離微電子元件所安裝至的支撐元件104。在一範例中,單塊式密封650可形成接觸於第二密封152,使得產生的封裝變成一個整體性的封裝,具有結構堅固的密封,其整合了第二密封152與單塊式密封650,單塊式密封650形成於原始的第二密封的頂部與側部表面153、154 上以及第一與第二支撐元件102、106的第二表面103、106上。封裝610可具有內部界面,其中單塊式密封650接觸於第二密封152的表面153、154並且形成於此種表面上。 6 is a variation of FIG. 1A-B or 4A-B, and the microelectronic package 610 includes first and second seals 650, 152. In an example, a first connector, such as connector 161 or connector 171, may be partially sealed within second seal 152, wherein end 163 of first connector is coupled to a corresponding second connector (eg, connector 162) Or the end 164 of the connector 172) to provide a conductive path between the first and second support members. In this example, after the first connector is bonded to the second connector, a monolithic seal 650 can be formed such that the monolithic seal forms a face 125 that contacts the microelectronic component 120, the face 125 being facing away from the microelectronic component Support member 104 to which it is mounted. In one example, the monolithic seal 650 can form a contact with the second seal 152 such that the resulting package becomes a one-piece package with a structurally strong seal that integrates the second seal 152 with the monolithic seal 650, A monolithic seal 650 is formed on the top and side surfaces 153, 154 of the original second seal Upper and second surfaces 103, 106 of the first and second support members 102, 106. The package 610 can have an internal interface in which the monolithic seal 650 contacts and is formed on the surfaces 153, 154 of the second seal 152.

如第7圖所示,在第6圖的變化例中,第一連接器可為實質上剛性實心金屬柱181,其接合至第二連接器。在一範例中,第二連接器可為導電塊162,如同上述。 As shown in Fig. 7, in the variation of Fig. 6, the first connector can be a substantially rigid solid metal post 181 that is joined to the second connector. In an example, the second connector can be a conductive block 162, as described above.

第8圖為第6圖微電子封裝610接合於另一部件12之組件,以形成類似於相關於第3圖所上述的微電子組件之微電子組件。 Figure 8 is a diagram of the microelectronic package 610 of Figure 6 bonded to another component 12 to form a microelectronic assembly similar to the microelectronic assembly described above with respect to Figure 3.

第9圖為進一步的變化例,其中形成第二密封952,使得它部分地密封第二連接器962,而非部分地密封第一連接器。在此變化例中,單塊式密封950可形成接觸於第二密封的頂部與側部表面953、954以及接觸於微電子元件120的面125。密封950可形成接觸於第一與第二支撐元件的第二表面103、106。 Figure 9 is a further variation in which the second seal 952 is formed such that it partially seals the second connector 962 without partially sealing the first connector. In this variation, the monolithic seal 950 can form a top and side surfaces 953, 954 that contact the second seal and a face 125 that contacts the microelectronic element 120. The seal 950 can form a second surface 103, 106 that contacts the first and second support members.

第10圖為微電子封裝1010的變化例,其中,取代導電塊或焊料塗覆的固體核心(如同第9圖所見),第二連接器可為實質上剛性實心金屬柱982,並且可接合於第一連接器,例如導電塊161。在封裝1010的另一變化例中(未圖示),第一連接器可為實質上剛性實心金屬柱,且第二連接器可為導電塊。 Figure 10 is a variation of the microelectronic package 1010 in which, instead of a conductive block or a solder coated solid core (as seen in Figure 9), the second connector can be a substantially rigid solid metal post 982 and can be bonded to A first connector, such as a conductive block 161. In another variation of package 1010 (not shown), the first connector can be a substantially rigid solid metal post and the second connector can be a conductive block.

第11-13圖為第6圖形成微電子封裝610的方法中的階段。因此,如同第11圖所示,包含第一支撐元件102的子組件21可形成具有第一連接器161(突伸於其第二表面103之上)與密封152(圍繞個別的第一連接器161並且將第一連接器彼此絕緣)。在一範例中,密封152可為方形或矩形框 架的形式,在所示的視圖中的方向178中具有寬度,其中框架的中心開口的尺寸設計成容納微電子元件120。第一連接器161的端部163曝露在密封152的表面153處,並且可在朝向第二支撐元件104的方向180中突伸於表面153之上,或者可與表面153齊平,或者可在朝向第一支撐元件的表面103之方向中凹陷於表面153之下。 Figures 11-13 are stages in the method of forming the microelectronic package 610 of Figure 6. Thus, as shown in FIG. 11, the subassembly 21 including the first support member 102 can be formed with a first connector 161 (projecting above its second surface 103) and a seal 152 (around the individual first connector) 161 and insulates the first connectors from each other). In an example, the seal 152 can be a square or rectangular frame The form of the frame has a width in the direction 178 in the view shown, wherein the central opening of the frame is sized to accommodate the microelectronic element 120. The end 163 of the first connector 161 is exposed at the surface 153 of the seal 152 and may protrude above the surface 153 in a direction 180 toward the second support member 104, or may be flush with the surface 153, or may be It is recessed below the surface 153 in the direction of the surface 103 of the first support element.

在一範例中,子組件21可藉由形成第一支撐元件102與突伸於其第二表面103之上的第一連接器161之結構而形成。第一連接器161可為導電塊,或者可為相關於其他實施例所上述的其他第一連接器。密封可之後模製於該結構上,例如藉由將密封劑射出至為此所做的模具中,同時模具的板靠抵第一連接器161的端部163,使得端部163可保持未被密封劑覆蓋或完全覆蓋。隨後,可使用修邊(deflashing),以進一步露出模製的第一連接器的端部。在一範例中,模具板可包含模具槽,尺寸設計成容納其端部163附近之第一連接器161的端部部分,使得密封劑流動於第一連接器的端部部分的周圍,且產生的子組件21的第一連接器的端部163延伸於模製的密封的表面153之上。類似地,模具板可包含在對準於第一連接器的位置處的突伸部,使得產生的子組件21中的第一連接器變成凹陷於模製的密封的表面153之下。 In one example, subassembly 21 can be formed by forming a structure of first support member 102 and first connector 161 that protrudes above second surface 103 thereof. The first connector 161 can be a conductive block or can be other first connectors as described above in relation to other embodiments. The seal can then be molded onto the structure, for example by ejecting the encapsulant into the mold made for this purpose, while the plate of the mold abuts the end 163 of the first connector 161 such that the end 163 can remain unattached The sealant is covered or completely covered. Subsequently, deflashing can be used to further expose the ends of the molded first connector. In one example, the mold plate can include a mold slot sized to receive an end portion of the first connector 161 near its end 163 such that the sealant flows around the end portion of the first connector and produces The end 163 of the first connector of the subassembly 21 extends over the molded sealing surface 153. Similarly, the mold plate can include a protrusion at a location aligned with the first connector such that the first connector in the resulting subassembly 21 becomes recessed below the molded sealing surface 153.

密封152可包含或實質上由聚合物材料組成。可製成密封的材料的範例有灌封化合物、環氧樹脂、液晶聚合物、熱塑性塑膠、與熱固性聚合物。在具體的範例中,密封可包含聚合物基質與聚合物基質內的顆粒裝載材料,例如藉由模製或沉積未固化的聚合物材料(其具有顆粒裝載材料在其中)至第一支撐元件102的第二表面103上而形成。在一範例中, 顆粒裝載材料可選擇性地具有小的熱膨脹係數(「CTE」),使得所產生的密封152可具有小於每攝氏度每百萬之10的CTE,此後稱為「ppm/℃」。在一範例中,密封可包含填料材料,例如玻璃或陶瓷的介電質填料或半導體填料等。 Seal 152 can comprise or consist essentially of a polymeric material. Examples of materials that can be made into seals are potting compounds, epoxy resins, liquid crystal polymers, thermoplastics, and thermoset polymers. In a particular example, the seal can comprise a polymer matrix and a particulate loading material within the polymer matrix, such as by molding or depositing an uncured polymeric material having a particulate loading material therein to the first support member 102 The second surface 103 is formed on the surface. In an example, The particulate loading material can optionally have a small coefficient of thermal expansion ("CTE") such that the resulting seal 152 can have a CTE of less than 10 per million per degree Celsius, hereinafter referred to as "ppm/°C." In an example, the seal may comprise a filler material, such as a dielectric filler or semi-semiconductor filler of glass or ceramic.

如第12圖,子組件21然後可移動至用於接合於與第二子組件22的第二支撐元件104附接的對應的第二連接器162之位置中。例如,如同第12圖所繪示,第一與第二連接器可彼此對準,且第一與第二支撐元件可進入足以使第一連接器與第二連接器的至少一者中所包含的接合金屬流動且形成第一連接器與第二連接器之間的接合之狀況。例如,在第一連接器、第二連接器或二者的溫度升高至接合金屬可流動的溫度之前或時間間隔期間,第一連接器可接觸於所對準的第二連接器。 As in Fig. 12, the subassembly 21 can then be moved into position for engagement with a corresponding second connector 162 that is attached to the second support element 104 of the second subassembly 22. For example, as depicted in FIG. 12, the first and second connectors can be aligned with each other, and the first and second support members can enter enough to be included in at least one of the first connector and the second connector. The joint metal flows and forms a condition of engagement between the first connector and the second connector. For example, the first connector may contact the aligned second connector before or during a time interval when the temperature of the first connector, the second connector, or both rises to a temperature at which the bonding metal can flow.

如第13圖,可施加密封劑650,以覆蓋接合的第一與第二連接器161、162,像是例如,藉由模製密封劑材料(例如可流動的包覆成型材料)至第一支撐元件102的第二表面103上並且填充第一與第二支撐元件102、104之間以及微電子元件與相鄰之支撐元件102的表面103之間的空間。 As in Figure 13, a sealant 650 can be applied to cover the joined first and second connectors 161, 162, such as by molding a sealant material (e.g., a flowable overmold material) to the first The second surface 103 of the support member 102 fills the space between the first and second support members 102, 104 and between the microelectronic member and the surface 103 of the adjacent support member 102.

以此方式,如同第13圖所示,形成組件或封裝610,例如上面相關於第6圖進一步敘述的。 In this manner, as shown in Fig. 13, an assembly or package 610 is formed, such as described further above in relation to Fig. 6.

參見第14圖,在第11-13圖的變化例中,第二連接器162可接合於在第二密封的表面153處露出的第一連接器161的端部163。然後,第二連接器162可接合於在第二支撐元件的第二表面106處的導電元件166,例如墊、柱、或其他導電連接器,以形成組件,例如或類似於第12圖所見的組件。然後,可施加密封劑650至該組件,以形成如同第13圖中所見且如同上 面相關於第6圖進一步敘述的組件610。 Referring to Figure 14, in a variation of Figures 11-13, the second connector 162 can be joined to the end 163 of the first connector 161 that is exposed at the second sealed surface 153. The second connector 162 can then be coupled to a conductive element 166, such as a pad, post, or other conductive connector, at the second surface 106 of the second support member to form an assembly, such as or similar to that seen in FIG. Component. A sealant 650 can then be applied to the assembly to form what is seen in Figure 13 and as above Component 610 is further described in relation to FIG.

雖然未見於圖式,相關於第11-14圖所上述的方法可用於第1A-B、2、4A-B、5、6、與7圖所述的任何類型的第一連接器與第二連接器,且非限制。關於本文的任何或所有微電子封裝與組件,形成一或更多個密封或用於形成任何或所有第一連接器及/或第二連接器與端子之處理可為如同以下所進一步例示與敘述的:美國申請案第11/166,982號(Tessera 3.0-358 CIP);第11/717,587號(Tessera 3.0-358 CIP CIP);第11/666,975號(Tessera 3.3-431);第11/318,404號(Tessera 3.0-484);第12/838,974號(Tessera 3.0-607);第12/839,038號(Tessera 3.0-608);第12/832,376號(Tessera 3.0-609)與第09/685,799號(TIPI 3.0-201),其揭示內容以引用之方式併入本文。 Although not shown in the drawings, the methods described above in relation to Figures 11-14 can be used for any type of first connector and second described in Figures 1A-B, 2, 4A-B, 5, 6, and 7. Connector, and is not limited. With respect to any or all of the microelectronic packages and components herein, the process of forming one or more seals or for forming any or all of the first connectors and/or the second connectors and terminals may be further exemplified and described below. US Application No. 11/166,982 (Tessera 3.0-358 CIP); No. 11/717,587 (Tessera 3.0-358 CIP CIP); No. 11/666,975 (Tessera 3.3-431); No. 11/318,404 ( Tessera 3.0-484); 12/838, 974 (Tessera 3.0-607); 12/839, 038 (Tessera 3.0-608); 12/832, 376 (Tessera 3.0-609) and 09/685, 799 (TIPI 3.0) -201), the disclosure of which is incorporated herein by reference.

第15-17圖為第9圖形成微電子封裝910的方法中的階段。在此變化例中,在第二連接器162接合至個別的第一連接器161來形成如同第16圖中所見的組件之前,第二支撐元件104上的第二連接器162係部分密封在第二密封952內。之後,可施加密封950來形成如同第17圖中所見的與如同上面相關於第9圖所述的組件910,其中密封950可接觸於第二密封952的表面953、954以及第一與第二支撐元件102、104的第二表面103、106。 15-17 are the stages in the method of forming the microelectronic package 910 in FIG. In this variation, the second connector 162 on the second support member 104 is partially sealed before the second connector 162 is joined to the individual first connector 161 to form the assembly as seen in FIG. Two seals 952. Thereafter, a seal 950 can be applied to form the assembly 910 as seen in FIG. 17 and as described above in relation to FIG. 9, wherein the seal 950 can contact the surfaces 953, 954 of the second seal 952 and the first and second The second surfaces 103, 106 of the support members 102, 104.

第18圖為第15-17圖的變化例,其中連接器165可接合於在第二密封劑的表面953處露出的第二連接器162的端部164。然後,連接器165可接合於在第一支撐元件102的第二表面103處的導電元件266(例如墊、柱、或其他導電連接器),以形成組件,例如或類似於第16圖所見的組件。然後,可施加密封劑950至該組件,以形成如同第17圖中所見且如同上面相關於第9圖所述的組件910。 Figure 18 is a variation of Figures 15-17 in which the connector 165 can be joined to the end 164 of the second connector 162 that is exposed at the surface 953 of the second encapsulant. Connector 165 can then be bonded to conductive element 266 (eg, a pad, post, or other conductive connector) at second surface 103 of first support element 102 to form an assembly, such as or similar to that seen in FIG. Component. Encapsulant 950 can then be applied to the assembly to form assembly 910 as seen in Figure 17 and as described above in relation to Figure 9.

第19圖為一範例組件1110,其中第一支撐元件102包含開口155,開口155延伸於其第一與第二表面101、103之間。在一範例中,開口可使用作為埠口,當製造組件1110時,通過該埠口,密封劑可提供至第一與第二支撐元件之間的內部空間中。 Figure 19 is an example assembly 1110 in which the first support member 102 includes an opening 155 that extends between its first and second surfaces 101,103. In one example, the opening can be used as a cornice through which the sealant can be provided into the interior space between the first and second support members when the assembly 1110 is fabricated.

第20圖為第9與17圖的變化例,例示組件1210,其中密封1252包含覆蓋微電子元件120的附加部分。在所示範例中,密封劑1252係形成作為單塊區域,部分地密封第二連接器162並且延伸至微電子元件的主表面129與邊緣表面127上。當微電子元件面朝上地安裝在第二支撐元件104上時,主表面129可為如同上面相關於第1A圖所述的前面。或者,當微電子元件面向第二支撐元件104時,主表面128可為相對於該前面之微電子元件120的後面。在此範例中,密封1250可形成接觸於密封1252,且可覆蓋或接觸於第一支撐元件102的第二表面103。 Figure 20 is a variation of Figures 9 and 17, illustrating an assembly 1210 in which the seal 1252 includes an additional portion that covers the microelectronic element 120. In the illustrated example, encapsulant 1252 is formed as a monolithic region that partially seals second connector 162 and extends onto major surface 129 and edge surface 127 of the microelectronic component. When the microelectronic component is mounted face up on the second support member 104, the major surface 129 can be the front as described above with respect to FIG. 1A. Alternatively, when the microelectronic component faces the second support component 104, the major surface 128 can be rearward relative to the front microelectronic component 120. In this example, the seal 1250 can form a contact with the seal 1252 and can cover or contact the second surface 103 of the first support element 102.

第21-22圖為第11-13圖變化例之處理。如第21圖所示,子組件321本身可為微電子封裝,其中微電子元件130具有接點電性耦接至其支撐元件302,以類似於上面相關於第1A圖所述之微電子元件20與支撐元件104之間的耦接的方式。在一些範例中,密封352可覆蓋微電子元件130的邊緣表面132,並且可在一些實例中覆蓋微電子元件的主表面134,主表面134面離子組件321的支撐元件302。 Figures 21-22 show the processing of the variations of Figures 11-13. As shown in FIG. 21, the subassembly 321 itself may be a microelectronic package in which the microelectronic component 130 has a contact electrically coupled to its support component 302 to resemble the microelectronic component described above in relation to FIG. 1A. The manner in which the coupling between the 20 and the support member 104 is achieved. In some examples, the seal 352 can cover the edge surface 132 of the microelectronic element 130 and can cover the major surface 134 of the microelectronic element, in some examples, the support element 302 of the surface ion assembly 321 of the main surface 134.

參見第22圖,接著,子組件321的連接器161可對準且接合於第二子組件22的對應的連接器162,且密封650可形成在微電子元件120與子組件321之間的空間中,以形成多層堆疊且電性耦接的組件1310,其包含微電子元件120、130、與其耦接的支撐元件302、104,使得微電子元件120、 130可透過支撐元件104、302以及第一與第二連接器161、162而電性耦接於彼此。接合元件146(例如,焊料球,例如上面相關於第3圖所述的)可施加至支撐元件104的端子142,通常是在形成密封650之後。 Referring to FIG. 22, the connector 161 of the subassembly 321 can then be aligned and bonded to the corresponding connector 162 of the second subassembly 22, and the seal 650 can form a space between the microelectronic component 120 and the subassembly 321 Forming a multi-layer stacked and electrically coupled component 1310 comprising microelectronic elements 120, 130, support elements 302, 104 coupled thereto, such that microelectronic element 120, 130 is electrically coupled to each other through support members 104, 302 and first and second connectors 161, 162. Engagement element 146 (eg, a solder ball, such as described above with respect to FIG. 3) can be applied to terminal 142 of support element 104, typically after formation of seal 650.

第23圖為其變化例,類似第14圖,其中組裝第一與第二子組件的處理係利用已經附接至第一連接器的端部163之第二連接器162來實行。 Figure 23 is a variation thereof, similar to Figure 14, in which the processing of assembling the first and second subassemblies is carried out using a second connector 162 that has been attached to the end 163 of the first connector.

第24圖類似第15-17圖的變化例,可在下述狀態中實行組裝處理:其中密封952部分地覆蓋第二連接器162,且其中第一連接器16接合於在密封952的表面953處露出之第二連接器162的端部164。第25圖例示以此方式形成之產生的組件1410。 Fig. 24 is similar to the variation of Figs. 15-17, in which the assembly process can be performed in which the seal 952 partially covers the second connector 162, and wherein the first connector 16 is bonded to the surface 953 of the seal 952. The end 164 of the second connector 162 is exposed. Figure 25 illustrates the resulting assembly 1410 formed in this manner.

第26-27圖為另一變化例,其中在個別的子組件中的第一連接器161與第二連接器162兩者可部分密封,如同上面相關於第11-13與15-17圖所示的方法所討論的。然而,在此實例中,第三連接器169(其可為例如上述的導電塊的形式)可附接且電性耦接於第一連接器的端部163,如同所示。如同第27圖中進一步所示的,第三連接器169可對準於且接合於第二連接器162,且產生的組件1510然後可密封在第三密封1550中,第三密封1550填充個別的第三連接器169之間的空間且填充微電子元件120與支撐元件302之間的空間。組件1510也可形成有接合元件146,接合元件146附接至支撐元件104,用於進一步連接於外部部件的對應接點,如同上述。 Figures 26-27 are another variation in which the first connector 161 and the second connector 162 in the individual sub-assemblies are partially sealed, as described above in relation to Figures 11-13 and 15-17. The method shown is discussed. However, in this example, a third connector 169 (which may be in the form of a conductive block such as described above) may be attached and electrically coupled to the end 163 of the first connector, as shown. As further shown in FIG. 27, the third connector 169 can be aligned with and coupled to the second connector 162, and the resulting assembly 1510 can then be sealed in a third seal 1550 that fills the individual The space between the third connectors 169 fills the space between the microelectronic element 120 and the support element 302. The assembly 1510 can also be formed with an engagement element 146 that is attached to the support element 104 for further attachment to a corresponding joint of the outer component, as described above.

第28-30圖為另一變化例之處理。在此範例中,在第一連接器或第二連接器或兩者上的部分密封可省略。取代地,如同第28圖所示,介電質加強環156可存在於第一連接器161、第二連接器162、或兩者的個別 一者的周圍。如同第28圖所見,加強環156包含覆蓋各自的個別連接器的表面(例如,導電塊的大體上球形表面,或替代地為相鄰的柱或其他連接器的壁部)之部分157,且加強環可形成槽159,其中相鄰的加強環相碰。加強環可藉由流動材料至支撐元件102的表面103上而形成,該材料然後可流動至第一連接器16所附接之表面103上的位置。例如,介電質加強材料可分配為液體,流動至第一連接器的個別一者的周圍區域。在一些範例中,真空塗覆、輥塗、噴塗、分配或篩分處理可用於液體材料,以形成加強環的一部分或全部。介電質加強材料可在連接器的周圍向上吸附,以支撐連接器的外表面,同時使其端部163露出,並且防止或實質上防止當此種連接器接合於其他連接器來形成本文所述的組件或封裝時,藉此加強的連接器的崩塌。修邊程序可在一些實例中使用來移除覆蓋端部163的較少量的加強材料。如同第28圖中進一步所見的,此種加強材料156也可存在於第二連接器162處與周圍。或者,加強層可省略,如同在第二連接器162b的實例中所見的。在一範例中,加強材料可為或包含環氧樹脂材料,例如具有介電質顆粒裝載材料的底部填充材料,例如通常分配至微電子元件(例如半導體晶片)的接觸承載面與晶片所覆晶附接且電性互連的基板表面之間的界面。加強環可在一些實例中降低其所施加的子組件的CTE。 Figures 28-30 show the processing of another variation. In this example, a partial seal on the first connector or the second connector or both may be omitted. Alternatively, as shown in FIG. 28, the dielectric reinforcement ring 156 may be present in the first connector 161, the second connector 162, or both of them. Around one. As seen in Fig. 28, the reinforcement ring 156 includes a portion 157 that covers the surface of the respective individual connector (e.g., the substantially spherical surface of the conductive block, or alternatively the wall of an adjacent post or other connector), and The reinforcing ring can form a groove 159 in which adjacent reinforcing rings meet. The reinforcing ring may be formed by flowing material onto the surface 103 of the support member 102, which material may then flow to a location on the surface 103 to which the first connector 16 is attached. For example, the dielectric reinforcing material can be dispensed as a liquid that flows to a surrounding area of an individual of the first connectors. In some examples, vacuum coating, roll coating, spray coating, dispensing or sieving treatment can be used on the liquid material to form part or all of the reinforcement ring. The dielectric reinforcing material can be adsorbed upwardly around the connector to support the outer surface of the connector while exposing its end 163 and preventing or substantially preventing when such a connector is bonded to other connectors to form the article The component or package is described as a result of the collapse of the reinforced connector. The trimming procedure can be used in some instances to remove a smaller amount of reinforcing material covering the ends 163. As further seen in FIG. 28, such reinforcing material 156 may also be present at and around the second connector 162. Alternatively, the reinforcement layer can be omitted as seen in the example of the second connector 162b. In one example, the reinforcing material can be or comprise an epoxy material, such as an underfill material having a dielectric particle loading material, such as a contact carrier surface typically dispensed to a microelectronic component (eg, a semiconductor wafer) and a wafer overlay An interface between the surfaces of the attached and electrically interconnected substrates. The stiffening ring may, in some instances, reduce the CTE of the subassembly to which it is applied.

如第29圖,具有第一與第二連接器的端部在其中曝露的子組件可用類似於上述的方式接合在一起。 As shown in Fig. 29, the subassemblies having the ends of the first and second connectors exposed therein can be joined together in a manner similar to that described above.

之後,如第30圖所示,接合的子組件可利用密封150來在力學上強化,密封150填充於子組件之間的空間中並且進一步強化第一與第二連接器之間的接合。如同第30圖所見,接合的第一與第二連接器161、162 可提供第一與第二支撐元件之間的連接的增加高度與增加的高寬比,以類似於前述實施例所述的方式。 Thereafter, as shown in Fig. 30, the joined subassemblies can be mechanically reinforced with a seal 150 that fills the space between the subassemblies and further strengthens the bond between the first and second connectors. As seen in Fig. 30, the joined first and second connectors 161, 162 An increased height and an increased aspect ratio of the connection between the first and second support members can be provided in a manner similar to that described in the previous embodiments.

在第28-30圖的變化例中,加強層可僅覆蓋第二連接器的壁部,或可僅覆蓋一些第二連接器的壁部。第一連接器、第二連接器或者第一與第二連接器兩者可為導電塊,或者可為前面討論且繪示的任何類型的連接器。 In a variation of Figures 28-30, the reinforcing layer may cover only the wall of the second connector or may only cover the walls of some of the second connectors. The first connector, the second connector, or both the first and second connectors may be conductive blocks or may be any type of connector discussed and illustrated above.

在進一步的變化例中,微電子封裝(例如,第21圖所示的封裝321)可用於替代第28圖的子組件(其包含支撐元件102),且此種子組件可接合於另一微電子封裝,以形成類似於第29圖所示的組件之組件。 In a further variation, a microelectronic package (eg, package 321 shown in FIG. 21) can be used in place of the subassembly of FIG. 28 (which includes support member 102), and the seed assembly can be bonded to another microelectronic Packaged to form a component similar to the assembly shown in Figure 29.

參見第31-36圖,在另一變化例中,提供第一子組件1721(第31圖),其包含支撐元件102(例如任何上述的支撐元件)與連接器1732(從支撐元件的表面103延伸遠離)。連接器1732可為任何前述的連接器,例如(但不限於):導電塊,例如可回焊塊,其可包含錫、銦、焊料或共熔合金,或者替代地為柱、導線、柱形凸塊或具有固體核心的塊,或上述的任何組合。如同在上述的實施例中,柱可為或包含實質上由銅組成的單塊金屬區域。接合金屬可設置在此種連接器的外表面上。因此,在第31圖所示的具體範例中,連接器1732可為接合至在其表面103處的導電元件1730(例如,墊、柱形凸塊等)之導電塊,例如接合金屬塊或焊料塊。在此變化例中,在組裝第一子組件與第二子組件1725(第35圖)之前,第一子組件1721可進行處理,以形成第34圖中的修改的第一子組件1723,其中第一連接器1732的末端1734突伸超出絕緣結構1744(例如,密封)的表面。 Referring to Figures 31-36, in another variation, a first subassembly 1721 (Fig. 31) is provided that includes a support member 102 (e.g., any of the above described support members) and a connector 1732 (from the surface 103 of the support member) Extend away). The connector 1732 can be any of the foregoing connectors, such as but not limited to: a conductive block, such as a solderable bump, which can comprise tin, indium, solder, or a eutectic alloy, or alternatively a post, wire, or column A bump or a block having a solid core, or any combination of the above. As in the embodiments described above, the post can be or comprise a single piece of metal that is substantially comprised of copper. The bonding metal can be disposed on the outer surface of such a connector. Thus, in the particular example shown in FIG. 31, the connector 1732 can be a conductive block bonded to a conductive element 1730 (eg, a pad, stud bump, etc.) at its surface 103, such as a bonding metal block or solder. Piece. In this variation, prior to assembling the first subassembly and the second subassembly 1725 (Fig. 35), the first subassembly 1721 can be processed to form the modified first subassembly 1723 of Fig. 34, wherein The end 1734 of the first connector 1732 projects beyond the surface of the insulating structure 1744 (eg, a seal).

具體地,參見第32圖,其可執行處理,使得第一連接器1732 的末端1734突伸至暫時層1708中且被暫時層覆蓋。為了形成絕緣結構,支撐元件與暫時層可置於各自的模具板1712、1710的相對內表面上,且可固化的介電質材料可流動於支撐元件102與暫時層1708之間的空腔1720內。暫時層在此處理期間將使介電質材料不覆蓋連接器末端1734。隨後,當將模具板移除(第33圖)時,第一連接器的末端1734免於絕緣結構,使得末端1734突伸超出絕緣結構1742的表面1744。 Specifically, referring to FIG. 32, the process can be performed such that the first connector 1732 The end 1734 protrudes into the temporary layer 1708 and is covered by the temporary layer. To form the insulating structure, the support member and the temporary layer can be placed on opposite inner surfaces of the respective mold plates 1712, 1710, and the curable dielectric material can flow between the cavity 1720 between the support member 102 and the temporary layer 1708. Inside. The temporary layer will cause the dielectric material to not cover the connector end 1734 during this process. Subsequently, when the mold plate is removed (Fig. 33), the end 1734 of the first connector is protected from the insulating structure such that the end 1734 protrudes beyond the surface 1744 of the insulating structure 1742.

在一範例中,暫時層1708(Temporary layer)可為沿著模具板的內表面延伸的膜。在此種範例中,該膜可置於模具的板1710與支撐元件102之間。該膜可置於模具板1710的內表面1711上,如同所示。支撐元件102的朝外表面101係設置成使得它直接或間接地置於與第一模具板1710相對之模具的第二板1712上。當模具板1710、1712帶至一起時,連接器1732的末端1734突伸至膜1708中且被該膜覆蓋。介電質材料(例如密封劑或模製化合物等)然後可流入空腔1720中且至少部分地固化,以形成絕緣結構1742(第33圖),使未被介電質材料覆蓋之連接器的末端1734如同被膜1708所保護。參見第34圖,在模具板與暫時膜1708移除之後,所產生的子組件1723的連接器的末端突伸超出絕緣結構1742或密封的表面1744。 In one example, the temporary layer 1708 (Temporary layer) can be a film that extends along the inner surface of the mold plate. In such an example, the film can be placed between the plate 1710 of the mold and the support member 102. The film can be placed on the inner surface 1711 of the mold plate 1710 as shown. The outwardly facing surface 101 of the support member 102 is disposed such that it is placed directly or indirectly on the second plate 1712 of the mold opposite the first mold plate 1710. When the mold plates 1710, 1712 are brought together, the end 1734 of the connector 1732 projects into and is covered by the film 1708. A dielectric material (eg, a sealant or molding compound, etc.) can then flow into the cavity 1720 and at least partially cure to form the insulating structure 1742 (FIG. 33), such that the connector is not covered by the dielectric material. End 1734 is protected by membrane 1708. Referring to Fig. 34, after the mold plate and temporary film 1708 are removed, the ends of the connectors of the resulting subassembly 1723 project beyond the insulating structure 1742 or the sealed surface 1744.

在上述的變化例中,取代使用上述的可移除膜,在形成密封層之前,水溶性膜可置於暫時層1708的位置中的模具板1710的內表面上。當模具板移除時,藉由洗掉該水溶性薄膜,可移除該水溶性薄膜,以使連接器的末端1734突伸超出絕緣結構1742或密封層的表面1744,如同上述。 In the above variations, instead of using the removable film described above, the water soluble film may be placed on the inner surface of the mold plate 1710 in the position of the temporary layer 1708 prior to forming the sealing layer. When the mold plate is removed, the water soluble film can be removed by washing away the water soluble film such that the end 1734 of the connector projects beyond the surface 1744 of the insulating structure 1742 or the sealing layer, as described above.

第35圖類似於第27圖的組件1510,組件形成時,使用第一子組件1723。如同第35圖所示,第一連接器1732的末端1734對準於對應的第 二連接器169(例如,第二子組件1725的導電塊),使得末端1734並置於連接器169的末端。如同上述的一或更多個實施例中,第二子組件1725可包含微電子元件120係電性耦接至支撐元件104,該微電子元件突伸於第二子組件的第二支撐元件104的表面106之上。如同第35圖所見,第一連接器1732的末端可設置在離第一支撐元件的表面103之最大高度1736處。類似地,第二連接器169的末端可設置在離第二支撐元件104的表面106之最大高度1756處。第二子組件1725可包含第三絕緣結構1752,第三絕緣結構1752包含至少部分固化的第三介電質材料。第三絕緣結構1752可為模製的密封,如同上述。 Figure 35 is similar to assembly 1510 of Figure 27, with the first sub-assembly 1723 being used when the assembly is formed. As shown in Fig. 35, the end 1734 of the first connector 1732 is aligned with the corresponding first A second connector 169 (e.g., a conductive block of the second subassembly 1725) is such that the end 1734 is placed at the end of the connector 169. As in one or more embodiments described above, the second sub-assembly 1725 can include the microelectronic component 120 electrically coupled to the support component 104, the microelectronic component protruding from the second support component 104 of the second subassembly. Above the surface 106. As seen in Fig. 35, the end of the first connector 1732 can be disposed at a maximum height 1736 from the surface 103 of the first support member. Similarly, the end of the second connector 169 can be disposed at a maximum height 1756 from the surface 106 of the second support member 104. The second subassembly 1725 can include a third insulating structure 1752 that includes an at least partially cured third dielectric material. The third insulating structure 1752 can be a molded seal, as described above.

接著,如第36圖所示,子組件1723係聯合於封裝1740中的第二子組件,使得連接器的末端1734接合於對應的連接器169。第二絕緣結構或密封然後可形成,例如藉由流動第二介電質材料來填充連接器之中與之間的空間且填充微電子元件120之間以及第一與第二支撐元件102與104之間的容積。第二絕緣結構可由與第一介電質材料相同的介電質材料或不同的材料製成。如同所述與所示的任何或全部的實施例中,例如,參見第1-21與28-30圖,第一端子141可設置於第一子組件1723的朝外表面處。第36圖進一步繪示附接至設置於組件1740的第二子組件1725的朝外表面105處的第二端子142之接合元件146。組件1740可為微電子封裝,其可適合於透過接合元件146而安裝至另一部件,例如電路平板(未圖示)。在端子141存在的一些實施例中,組件1740可使用作為封裝上封裝(PoP,package-on-package)組件,用於連接一或更多個額外的微電子封裝的端子至端子141。 Next, as shown in FIG. 36, subassembly 1723 is coupled to the second subassembly in package 1740 such that the end 1734 of the connector is bonded to the corresponding connector 169. A second insulating structure or seal may then be formed, for example by flowing a second dielectric material to fill the space between and between the connectors and between the microelectronic elements 120 and the first and second support members 102 and 104 The volume between. The second insulating structure may be made of the same dielectric material as the first dielectric material or a different material. As with any or all of the embodiments shown and described, for example, see FIGS. 1-21 and 28-30, the first terminal 141 can be disposed at an outwardly facing surface of the first subassembly 1723. FIG. 36 further illustrates the engagement element 146 attached to the second terminal 142 disposed at the outwardly facing surface 105 of the second subassembly 1725 of the assembly 1740. Component 1740 can be a microelectronic package that can be adapted to be mounted to another component, such as a circuit board (not shown), through bonding element 146. In some embodiments in which terminal 141 is present, component 1740 can be used as a package-on-package (PoP) component for connecting one or more additional microelectronic package terminals to terminal 141.

在其他變化例中(未圖示),第11-14、15-18或21-30圖中繪 示的任何組裝處理可實行於下述狀況中:其中具有本文所述的微電子元件或支撐元件之一或兩個子組件係由不同的結構取代。具體地,一或兩個子組件可為或可包含微電子元件與支撐元件之多層堆疊且電性互連的組件,支撐元件在每一層的此種子組件處耦接至各自的微電子元件。 In other variations (not shown), painted in Figures 11-14, 15-18 or 21-30 Any of the assembly processes shown can be practiced in situations in which one or both of the microelectronic elements or support elements described herein are replaced by different structures. In particular, one or both sub-assemblies may be or may comprise a multi-layer stacked and electrically interconnected assembly of microelectronic elements and support elements that are coupled to respective microelectronic elements at this seed component of each layer.

參見第37-40圖,在又一變化例中,第一絕緣結構可形成在子組件1761上,子組件1761包含第二支撐元件104與微電子元件120與第二連接器1762,所有該等元件都面向上、遠離支撐元件104的表面106。暫時層1768(例如膜)設置在模具板1770的內表面1769上。然後,如同第37圖所示,當模具板1770、1772帶至承載於子組件1761上時,連接器的末端1764突伸至暫時層1768中且因此被覆蓋。之後,介電質材料流入模具空腔內,以形成絕緣結構1774,且然後移除暫時層,產生如同第39圖中所見的子組件1765。此第一子組件1765然後可藉由例如上面相關於第15圖所述的處理而聯合於第二子組件1767,除了連接器1762的末端1764突伸超出絕緣結構的表面1773之外。第40圖例示藉由聯合第一與第二子組件所形成的組件1780,該組件具有透過端子等之外部連接功能,例如上述任何實施例中所提供的。 Referring to Figures 37-40, in yet another variation, a first insulating structure can be formed on subassembly 1761, and subassembly 1761 includes second support component 104 and microelectronic component 120 and second connector 1762, all of which are The components are all facing up, away from the surface 106 of the support member 104. A temporary layer 1768 (eg, a film) is disposed on the inner surface 1769 of the mold plate 1770. Then, as shown in Fig. 37, when the mold plates 1770, 1772 are brought onto the subassembly 1761, the ends 1764 of the connectors project into the temporary layer 1768 and are thus covered. Thereafter, the dielectric material flows into the mold cavity to form the insulating structure 1774, and then the temporary layer is removed, resulting in a subassembly 1765 as seen in FIG. This first subassembly 1765 can then be combined with the second subassembly 1767 by, for example, the process described above in relation to Fig. 15, except that the end 1764 of the connector 1762 protrudes beyond the surface 1773 of the insulating structure. Figure 40 illustrates an assembly 1780 formed by joining first and second subassemblies having external connection functions through terminals or the like, such as provided in any of the embodiments described above.

以上討論的結構提供卓越的三維互連功能。這些功能可用於任何類型的晶片。僅藉由範例之方式,晶片的以下組合可包含在以上討論的結構中:(i)處理器與用於處理器的記憶體;(ii)相同類型的複數個記憶體晶片;(iii)多種類型的複數個記憶體晶片,例如DRAM與SRAM;(iv)影像感測器與用於處理來自感測器的影像之影像處理器;(v)專用積體電路(ASIC)與記憶體。上面所討論的結構可用於多種電子系統的建構。例 如,第41圖的系統500包含如同上述的結構506係結合於其他電子部件508與510。在所示的範例中,部件508為半導體晶片,而部件510為顯示螢幕,但是任何其他部件都可使用。當然,雖然為了清楚地例示,第41圖僅繪示兩個附加的部件,該系統可包含任何數量的此種部件。上述的結構506可例如為微電子封裝,如同相關於任何上述實施例所提供的,或者可為微電子組件,例如相關於第3圖或第8圖所上面討論的。結構506與部件508與510安裝在共同的殼體501(以虛線示意繪示)中,且如同所需地電性互連於彼此,以形成所欲的電路。在所示的範例性系統中,系統包含電路平板502,例如撓性印刷電路板,且電路平板包含許多導體504(其中在第21圖中僅繪示一個),以將部件互連於彼此。然而,這僅是範例性的;可使用用於製做電連接的任何合適結構。殼體501係繪示為例如手機或個人數位助理中可用的可攜式殼體類型,且螢幕510在殼體的表面處露出。當結構506包含感光元件(例如成像晶片)時,也可提供透鏡511或其他光學裝置,用於傳送光至該結構。另外,第21圖所示的簡化系統僅為範例性;其他系統(包含通常視為固定結構的系統,例如桌上型電腦、路由器等)可使用上面討論的結構來製做。 The structure discussed above provides superior 3D interconnect functionality. These features are available for any type of wafer. By way of example only, the following combinations of wafers may be included in the structure discussed above: (i) processor and memory for the processor; (ii) a plurality of memory chips of the same type; (iii) various Types of memory chips, such as DRAM and SRAM; (iv) image sensors and image processors for processing images from sensors; (v) dedicated integrated circuits (ASICs) and memory. The structures discussed above can be used in the construction of a variety of electronic systems. example For example, system 500 of FIG. 41 includes structure 506 as described above coupled to other electronic components 508 and 510. In the illustrated example, component 508 is a semiconductor wafer and component 510 is a display screen, but any other component can be used. Of course, although FIG. 41 depicts only two additional components for clarity of illustration, the system can include any number of such components. The structure 506 described above can be, for example, a microelectronic package, as provided in connection with any of the above-described embodiments, or can be a microelectronic assembly, such as discussed above with respect to FIG. 3 or FIG. Structure 506 and components 508 and 510 are mounted in a common housing 501 (shown in phantom) and are electrically interconnected as desired to form the desired circuitry. In the exemplary system shown, the system includes a circuit board 502, such as a flexible printed circuit board, and the circuit board includes a plurality of conductors 504 (only one of which is shown in FIG. 21) to interconnect the components to each other. However, this is merely exemplary; any suitable structure for making electrical connections can be used. The housing 501 is depicted as a portable housing type available, for example, in a cell phone or personal digital assistant, and the screen 510 is exposed at the surface of the housing. When structure 506 includes a photosensitive element (e.g., an imaging wafer), lens 511 or other optical means may also be provided for transmitting light to the structure. In addition, the simplified system shown in FIG. 21 is merely exemplary; other systems (including systems that are generally considered to be fixed structures, such as desktops, routers, etc.) can be fabricated using the structures discussed above.

由於以上討論的特徵的這些與其他變化與組合都可使用,而不脫離本發明的範圍,因此前述較佳實施例的說明應視為例示的方式,而非如同申請專利範圍所界定之本發明的限制的方式。 Since these and other variations and combinations of the features discussed above can be used without departing from the scope of the invention, the description of the preferred embodiments described above should be considered as illustrative, rather than the invention as defined by the scope of the claims. The way to limit.

21‧‧‧子組件 21‧‧‧Subcomponents

22‧‧‧子組件 22‧‧‧Subcomponents

101‧‧‧第一表面 101‧‧‧ first surface

102‧‧‧第一支撐元件 102‧‧‧First support element

103‧‧‧第二表面 103‧‧‧ second surface

104‧‧‧第二支撐元件 104‧‧‧Second support element

120‧‧‧微電子元件 120‧‧‧Microelectronic components

152‧‧‧第二密封 152‧‧‧Second seal

153‧‧‧表面 153‧‧‧ surface

161‧‧‧第一連接器 161‧‧‧First connector

162‧‧‧第二連接器 162‧‧‧Second connector

163‧‧‧端部 163‧‧‧End

Claims (20)

一種微電子組件,包含:第一與第二支撐元件,每一支撐元件具有第一與第二相對面向的表面;一微電子元件,其安裝至該第一與第二支撐元件的一支撐元件的該第二表面上;導電的第一連接器,其突伸於該第一支撐元件的該第二表面之上;導電的第二連接器,其突伸於該第二支撐元件的該第二表面之上並且耦接至該等第一連接器的端部;及一單塊式第一密封(Monolithic First encapsulation),其形成接觸於該第一與第二支撐元件的一支撐元件的該第二表面,並且形成接觸於該第一與第二支撐元件的又一支撐元件的該第二表面之至少一個;或一單塊式第二密封,其形成接觸於該另一支撐元件的該第二表面,其中對於該單塊式第一密封、該單塊式第二密封或二者而言,在該第一支撐元件的該第一表面的第一封裝端子係通過對準且接合於該等第二連接器之該等成對的第一連接器,而電性耦接於在該第二支撐元件的該第一表面的對應的第二封裝端子,且下述至少一者成立:該等第一連接器與第二連接器包含導電塊。 A microelectronic assembly comprising: first and second support members, each support member having first and second oppositely facing surfaces; a microelectronic component mounted to a support member of the first and second support members On the second surface; a conductive first connector projecting over the second surface of the first support member; and a conductive second connector projecting from the second support member And a monolithic first encapsulation forming a contact element contacting the first and second support members a second surface and forming at least one of the second surface contacting the further support element of the first and second support members; or a monolithic second seal forming the contact with the other support member a second surface, wherein for the monolithic first seal, the monolithic second seal, or both, the first package terminal at the first surface of the first support member is aligned and bonded Such second connectors The first connector is electrically coupled to the corresponding second package terminal of the first surface of the second support component, and at least one of the following is established: the first connector is connected to the second connector The device contains a conductive block. 如申請專利範圍第1項所述之微電子組件,其中該等支撐元件的該等第二表面之間的一間隙(Standoff)高度大於在平行於該第一支撐元件的該第二表面之至少一方向中的該等第一連接器的一間距(Pitch)。 The microelectronic assembly of claim 1, wherein a gap between the second surfaces of the support members is greater than at least a second surface parallel to the first support member A pitch of the first connectors in a direction. 如申請專利範圍第1項所述之微電子組件,其中該微電子元件具有面離其所安裝的該支撐元件之一面(Face),且該第一密封之形成,係接觸於下述至少一者:該微電子元件的該面或形成於該微電子元件的該面上的一第三密封。 The microelectronic component of claim 1, wherein the microelectronic component has a face facing the support component mounted thereon, and the first seal is formed to contact at least one of the following The face of the microelectronic component or a third seal formed on the face of the microelectronic component. 如申請專利範圍第1項所述之微電子組件,其中該微電子組件包含該第二密封,且該第一密封之形成,係接觸於該第二密封。 The microelectronic assembly of claim 1, wherein the microelectronic assembly comprises the second seal, and the first seal is formed to contact the second seal. 如申請專利範圍第1項所述之微電子組件,其中該等第一連接器或該等第二連接器的至少一者包含下述至少一者:柱狀凸塊或實心的實質上剛性的金屬柱。 The microelectronic assembly of claim 1, wherein at least one of the first connectors or the second connectors comprises at least one of: a columnar bump or a solid substantially rigid Metal column. 一種堆疊式多晶片微電子組件,包含如申請專利範圍第1項所述之該微電子組件以及在該微電子組件的該第一支撐元件之上的一微電子封裝,該微電子封裝有端子連接至該微電子組件的該等第一封裝端子。 A stacked multi-wafer microelectronic assembly comprising the microelectronic assembly of claim 1 and a microelectronic package over the first support component of the microelectronic assembly, the microelectronic package having a terminal Connecting to the first package terminals of the microelectronic assembly. 如申請專利範圍第6項所述之微電子組件,其中該等第二連接器係為導電金屬塊,其從該第二支撐元件的該第二表面處的墊突出,每一導電金屬塊由該密封圍繞,且該等第一連接器包含實心實質剛性的金屬柱。 The microelectronic assembly of claim 6, wherein the second connector is a conductive metal block protruding from a pad at the second surface of the second support member, each conductive metal block being The seal surrounds and the first connectors comprise solid substantially rigid metal posts. 如申請專利範圍第6項所述之微電子組件,其中該等第一連接器係為導電 金屬塊,其從該第一支撐元件的該第二表面處的墊突出,且該等第二連接器包含實心實質剛性的金屬柱。 The microelectronic assembly of claim 6, wherein the first connectors are electrically conductive a metal block that protrudes from the pad at the second surface of the first support element, and the second connectors comprise solid substantially rigid metal posts. 如申請專利範圍第8項所述之微電子組件,其中每一導電金屬塊由該第一密封圍繞。 The microelectronic assembly of claim 8 wherein each of the conductive metal blocks is surrounded by the first seal. 如申請專利範圍第1項所述之微電子組件,另包含第三連接器,每一第三連接器對準該等第一連接器的一者的一端部,並且對準該等第二連接器的一者的一端部,且接合該等對準的第一與第二連接器的至少一者,其中耦接的第一、第二與第三連接器係在個別的行中對準,並且藉由該第一密封的該材料而與該微電子元件彼此分隔,且該等第一封裝端子通過該等第三連接器電性耦接該等對應的第二封裝端子。 The microelectronic assembly of claim 1, further comprising a third connector, each third connector being aligned with an end of one of the first connectors, and aligning the second connections One end of one of the devices, and engaging at least one of the aligned first and second connectors, wherein the coupled first, second, and third connectors are aligned in separate rows, And the microelectronic components are separated from each other by the first sealed material, and the first package terminals are electrically coupled to the corresponding second package terminals through the third connectors. 如申請專利範圍第10項所述之微電子組件,其中該第一密封將個別的第三連接器彼此分隔且絕緣。 The microelectronic assembly of claim 10, wherein the first seal separates and insulates the individual third connectors from each other. 一種微電子組件,包含:一第一微電子封裝,具一第一支撐元件、一微電子元件及一複數導電之第一連接器,其中該第一支撐元件具有第一與第二相對面向表面,該微電子元件安裝至該第一與第二表面的一表面,而該複數導電之第一連接係延伸遠離該第二表面;一第二微電子封裝,具一第二支撐元件、一微電子元件及導電第二連接 器,其中該第二支撐元件具有第一與第二相對面向表面,該微電子元件安裝至該第二支撐元件的該第二表面,該導電第二連接器突出於該第二支撐元件的該第二表面之上並且耦接至該等第一連接器的端部;及一單塊式(Monolithic)第一密封,其形成接觸於該第一與第二支撐元件的一支撐元件的該第二表面,並且形成接觸於一單塊式第二密封,該第二密封形成接觸於該第一與第二支撐元件的另一支撐元件的該第二表面,其中在該第二支撐元件的該第一表面的封裝端子通過對準且耦接於該等第二連接器之個別成對的該等第一連接器,而耦接該第一支撐元件的該第一表面的導電元件,且下述至少一者成立:該等第一連接器與第二連接器包含導電塊。 A microelectronic assembly comprising: a first microelectronic package having a first support component, a microelectronic component, and a plurality of electrically conductive first connectors, wherein the first support component has first and second opposing facing surfaces The microelectronic component is mounted to a surface of the first and second surfaces, and the plurality of electrically conductive first connections extend away from the second surface; a second microelectronic package having a second support component, a micro Electronic component and conductive second connection The second support member has first and second opposite facing surfaces, the microelectronic component being mounted to the second surface of the second support member, the conductive second connector protruding from the second support member a second surface and coupled to the ends of the first connectors; and a monolithic first seal forming the first contact element of the first and second support members a second surface and forming contact with a monolithic second seal forming the second surface of the other support element contacting the first and second support members, wherein the second support member a package terminal of the first surface is coupled to the first pair of the first connectors of the second connector, and coupled to the conductive component of the first surface of the first support component, and At least one of the above is true: the first connector and the second connector comprise conductive blocks. 如申請專利範圍第12項所述之微電子組件,其中該第一與第二支撐元件的該等第二表面之間的一間隙高度(Standoff height)大於在平行於該第一支撐元件的該第二表面之至少一方向中的該等第一連接器的一間距。 The microelectronic assembly of claim 12, wherein a gap height between the second surfaces of the first and second support members is greater than the parallel to the first support member a spacing of the first connectors in at least one direction of the second surface. 如申請專利範圍第12項所述之微電子組件,其中該微電子元件具有面離其所安裝的該支撐元件之一面,且該第一密封形成接觸於下述至少一者:該微電子元件的該面或形成於該微電子元件的該面上的一單塊式第三密封。 The microelectronic assembly of claim 12, wherein the microelectronic component has a face that faces away from the support component to which it is mounted, and the first seal is formed in contact with at least one of: the microelectronic component The face or a monolithic third seal formed on the face of the microelectronic component. 如申請專利範圍第12項所述之微電子組件,另包含第三連接器,每一第三連接器對準於該等第一連接器的一者的一端部,並且對準於該等第二連 接器的一者的一端部,且接合於該等對準的第一與第二連接器的至少一者,其中耦接的第一、第二與第三連接器係在個別的行中對準,並且藉由該密封的該材料而與該微電子元件彼此分隔,且該等第一封裝端子通過該等第三連接器而電性耦接於該第一支撐元件的該等導電元件。 The microelectronic assembly of claim 12, further comprising a third connector, each third connector being aligned with an end of one of the first connectors, and aligned with the first Erlian One end of one of the connectors, and is coupled to at least one of the aligned first and second connectors, wherein the coupled first, second, and third connectors are in an individual row And the microelectronic components are separated from each other by the sealed material, and the first package terminals are electrically coupled to the conductive components of the first support component through the third connectors. 如申請專利範圍第15項所述之微電子組件,其中該第一密封將個別的第三連接器彼此分隔且絕緣。 The microelectronic assembly of claim 15, wherein the first seal separates and insulates the individual third connectors from each other. 一種製造一微電子組件的方法,包含:接合第一與第二子組件,以形成一組件,該組件具有第一端子位於該組件的一第一朝外表面處,及第二端子位於該組件的一第二朝外表面處,該第二朝外表面相對於該第一表面,其中該等子組件的至少一者具有至少一微電子元件安裝於其一朝內的第二表面,該微電子元件電性耦接至該至少一子組件,該第一子組件包含一第一支撐元件,且該第二子組件包含一第二支撐元件,且該第一或第二子組件的至少一者包含之連接器係突出於該個別子組件的該支撐元件的該朝內的第二表面之上,並且遠離該朝內的第二表面朝向另一支撐元件的該朝內的第二表面,且複數個第一端子的每一者,係通過具有一端部耦接於一對應第二連接器的一端部之個別一對的一第一連接器,而電性耦接於個別的第二端子,該第二連接器延伸於該第一連接器之上;及流動一密封劑進入該第一與第二支撐元件之間的一空間中,且流到至少一支撐元件的該第二表面上,以形成一單塊式密封,該單塊式密封將個 別成對接合的第一與第二連接器的至少部分彼此分隔。 A method of fabricating a microelectronic assembly, comprising: joining first and second subassemblies to form a component having a first terminal at a first outwardly facing surface of the component, and a second terminal located at the component At a second outwardly facing surface, the second outwardly facing surface is opposite the first surface, wherein at least one of the subassemblies has at least one microelectronic component mounted on an inwardly facing second surface thereof, the microelectronic The component is electrically coupled to the at least one subassembly, the first subassembly includes a first support component, and the second subassembly includes a second support component, and at least one of the first or second subcomponent The included connector protrudes over the inwardly facing second surface of the support member of the individual subassembly and away from the inwardly facing second surface toward the inwardly facing second surface of the other support member, and Each of the plurality of first terminals is electrically coupled to the respective second terminal by a first connector having an end pair coupled to one end of the corresponding second connector The second connector extends over Above the first connector; and flowing a sealant into a space between the first and second support members and flowing onto the second surface of the at least one support member to form a monolithic seal, The monolithic seal will be At least portions of the first and second connectors that are not in the pair are separated from one another. 如申請專利範圍第17項所述之方法,其中下述的至少一者成立:該等第一連接器或該等第二連接器在該接合處理期間受到限制,以維持此種連接器的一高度。 The method of claim 17, wherein at least one of the following is established: the first connectors or the second connectors are limited during the bonding process to maintain one of the connectors height. 如申請專利範圍第17項所述之方法,其中該封裝為一第一密封,且該第一或第二子組件的一者包含一單塊式第二密封,該單塊式第二密封將其至少一些連接器彼此分隔,其中該第一密封係形成接觸於該第二密封。 The method of claim 17, wherein the package is a first seal, and one of the first or second sub-assemblies comprises a monolithic second seal, the monolithic second seal At least some of the connectors are spaced apart from each other, wherein the first sealing system is in contact with the second seal. 如申請專利範圍第17項所述之方法,其中該等第一連接器與該等第二連接器分別具有,在該第一與第二支撐元件的該等第二表面之上的最大高度處的端部,且該等第一連接器的該等端部對準且直接接合於該等第二連接器的端部。 The method of claim 17, wherein the first connector and the second connectors respectively have a maximum height above the second surfaces of the first and second support members The ends of the first connectors are aligned and directly joined to the ends of the second connectors.
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