WO2023184588A1 - 显示面板及显示装置 - Google Patents

显示面板及显示装置 Download PDF

Info

Publication number
WO2023184588A1
WO2023184588A1 PCT/CN2022/086884 CN2022086884W WO2023184588A1 WO 2023184588 A1 WO2023184588 A1 WO 2023184588A1 CN 2022086884 W CN2022086884 W CN 2022086884W WO 2023184588 A1 WO2023184588 A1 WO 2023184588A1
Authority
WO
WIPO (PCT)
Prior art keywords
transistor
node
signal
electrically connected
light
Prior art date
Application number
PCT/CN2022/086884
Other languages
English (en)
French (fr)
Inventor
申郑
Original Assignee
深圳市华星光电半导体显示技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 深圳市华星光电半导体显示技术有限公司 filed Critical 深圳市华星光电半导体显示技术有限公司
Priority to US17/756,652 priority Critical patent/US20240161690A1/en
Publication of WO2023184588A1 publication Critical patent/WO2023184588A1/zh

Links

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0209—Crosstalk reduction, i.e. to reduce direct or indirect influences of signals directed to a certain pixel of the displayed image on other pixels of said image, inclusive of influences affecting pixels in different frames or fields or sub-images which constitute a same image, e.g. left and right images of a stereoscopic display
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/04—Maintaining the quality of display appearance
    • G09G2320/043—Preventing or counteracting the effects of ageing
    • G09G2320/045—Compensation of drifts in the characteristics of light emitting or modulating elements

Definitions

  • the present application relates to the field of display technology, and specifically to a display panel and a display device.
  • Organic light-emitting diodes are active light-emitting devices. Compared with liquid crystal displays, organic light-emitting diodes do not need to provide a backlight. Moreover, organic light-emitting diode display devices have the advantages of ultra-thin, high brightness, and low driving voltage, and are considered to be the next generation of display devices.
  • the present application provides a display panel and a display device. By disconnecting the light-emitting devices during the writing process of the pixel voltage, the problem of voltage division in the existing display panel caused by different cross-voltage of the light-emitting devices between pixels in the same row is solved. Display unusual issues.
  • embodiments of the present application provide a display panel, which includes a plurality of pixel units arranged in an array.
  • the pixel units include a driving circuit.
  • the driving circuit includes: a light-emitting device, a driving transistor, and a writing compensation module.
  • the light-emitting device is connected in series to the light-emitting circuit; the source and drain of the driving transistor are connected in series to the light-emitting circuit, and the gate of the driving transistor is electrically connected to the first node; the write compensation module is connected to the data signal and the scan signal, and is electrically connected to the first node and the second node, and the write compensation module is used to control the scan signal under the control of the scan signal.
  • the data signal is transmitted to the first node; the current detection module is connected to the first control signal and the detection signal, and is electrically connected to the second node.
  • the current detection module is used to detect the flow through the driving transistor.
  • the actual current, and the actual current is compared with the preset current to generate the compensation voltage of the driving transistor; wherein the write compensation module is also used to calculate the threshold voltage of the driving transistor according to the compensation voltage.
  • the light-emitting control module is connected to the second control signal and connected in series to the light-emitting circuit.
  • the light-emitting control module is used to control the second node and the second node under the control of the second control signal.
  • the light-emitting devices are connected or disconnected.
  • the write compensation module includes a first transistor and a storage capacitor; the gate of the first transistor is connected to the scan signal, and the source of the first transistor is One of the source and drain of the first transistor is connected to the data signal, and the other of the source and drain of the first transistor is electrically connected to the first node; the first terminal of the storage capacitor is electrically Connected to the first node, a second terminal of the storage capacitor is electrically connected to the second node.
  • the current detection module includes a second transistor, the gate of the second transistor is connected to the first control signal, and the source and drain of the second transistor are One of the source and drain of the second transistor is connected to the detection signal, and the other of the source and drain of the second transistor is electrically connected to the second node.
  • the lighting control module includes a third transistor, the gate of the third transistor is connected to the second control signal, and the source and drain of the third transistor are connected to the second control signal.
  • One of the electrodes is connected to the second node, and the other of the source electrode and the drain electrode of the third transistor is electrically connected to the anode of the light-emitting device.
  • the scanning signal, the first control signal and the second control signal are the same signal.
  • the driving transistor, the first transistor and the second transistor are all N-type transistors, and the third transistor is a P-type transistor.
  • the first transistor and the second transistor are P-type transistors
  • the third transistor and the driving transistor are N-type transistors.
  • the lighting control module further includes an inverter, the input end of the inverter is connected to the scanning signal, and the output end of the inverter is electrically connected on the gate of the third transistor.
  • the driving transistor, the first transistor, the second transistor and the third transistor are transistors of the same type.
  • the combination of the scanning signal, the first control signal and the second control signal corresponds to the data writing phase and the light emitting phase successively.
  • the present application provides a display device, including a driver chip and a display panel.
  • the driver chip is electrically connected to the display panel.
  • the display panel includes a plurality of pixel units arranged in an array.
  • the pixels The unit includes a drive circuit.
  • the drive circuit includes: a light-emitting device, a drive transistor, a write compensation module, a current detection module and a light-emitting control module.
  • the light-emitting device is connected in series to the light-emitting circuit; the source and drain of the drive transistor Connected in series to the light-emitting circuit, the gate of the driving transistor is electrically connected to the first node; the write compensation module receives the data signal and the scanning signal, and is electrically connected to the first node and the second node.
  • the write compensation module is used to transmit the data signal to the first node under the control of the scan signal;
  • the current detection module is connected to the first control signal and the detection signal, and is electrically connected At the second node, the current detection module is used to detect the actual current flowing through the driving transistor, and compare the actual current with a preset current to generate a compensation voltage for the driving transistor; wherein, The write compensation module is also used to compensate the threshold voltage of the driving transistor according to the compensation voltage;
  • the lighting control module receives the second control signal and is connected in series to the lighting circuit.
  • the lighting control module For controlling the conduction or disconnection between the second node and the light-emitting device under the control of the second control signal.
  • the write compensation module includes a first transistor and a storage capacitor; the gate of the first transistor is connected to the scan signal, and the source of the first transistor is One of the source and drain of the first transistor is connected to the data signal, and the other of the source and drain of the first transistor is electrically connected to the first node; the first terminal of the storage capacitor is electrically Connected to the first node, a second terminal of the storage capacitor is electrically connected to the second node.
  • the current detection module includes a second transistor, the gate of the second transistor is connected to the first control signal, and the source and drain of the second transistor are One of the source and drain of the second transistor is connected to the detection signal, and the other of the source and drain of the second transistor is electrically connected to the second node.
  • the lighting control module includes a third transistor, the gate of the third transistor is connected to the second control signal, and the source and drain of the third transistor are connected to the second control signal.
  • One of the electrodes is connected to the second node, and the other of the source electrode and the drain electrode of the third transistor is electrically connected to the anode of the light-emitting device.
  • the scanning signal, the first control signal and the second control signal are the same signal.
  • the driving transistor, the first transistor and the second transistor are all N-type transistors, and the third transistor is a P-type transistor.
  • the first transistor and the second transistor are P-type transistors
  • the third transistor and the driving transistor are N-type transistors.
  • the lighting control module further includes an inverter, the input end of the inverter is connected to the scanning signal, and the output end of the inverter is electrically connected on the gate of the third transistor.
  • the driving transistor, the first transistor, the second transistor and the third transistor are transistors of the same type.
  • the combination of the scanning signal, the first control signal and the second control signal corresponds to the data writing phase and the light emitting phase successively.
  • the present application provides a display panel and a display device.
  • the display panel includes a plurality of pixel units arranged in an array.
  • the pixel units include a drive circuit.
  • the drive circuit includes a light-emitting device, a drive transistor, a write compensation module, a current Detection module and light-emitting control module, the light-emitting device is connected in series to the light-emitting circuit; the source and drain of the driving transistor are connected in series to the light-emitting circuit, and the gate of the driving transistor is electrically connected to the first node; the write compensation module is used during scanning
  • the data signal is transmitted to the first node under the control of the signal;
  • the current detection module is used to detect the actual current flowing through the driving transistor, and compare the actual current with the preset current to generate the compensation voltage of the driving transistor; where, write compensation
  • the module is also used to compensate the threshold voltage of the driving transistor according to the compensation voltage;
  • the light-emitting control module is used to control the
  • Figure 1 is a schematic structural diagram of a display panel provided by an embodiment of the present application.
  • Figure 2 is a schematic structural diagram of a driving circuit provided by an embodiment of the present application.
  • Figure 3 is a circuit diagram of a driving circuit in a display panel provided by the first embodiment of the present application.
  • Figure 4 is a timing diagram of the driving circuit in the display panel provided by the first embodiment of the present application.
  • Figure 5 is a circuit diagram of a driving circuit in a display panel provided by the second embodiment of the present application.
  • Figure 6 is a circuit diagram of a driving circuit in a display panel provided by the third embodiment of the present application.
  • Figure 7 is a circuit diagram of a driving circuit in a display panel provided by the fourth embodiment of the present application.
  • Figure 8 is a timing diagram of the driving circuit in the display panel provided by the fourth embodiment of the present application.
  • Figure 9 is a schematic structural diagram of a backlight module provided by an embodiment of the present application.
  • FIG. 10 is a schematic structural diagram of a display device provided by an embodiment of the present application.
  • Embodiments of the present application provide a display panel and a display device, which can solve the display abnormality problem of existing display panels caused by voltage division due to different cross-voltages of light-emitting devices between pixels in the same row.
  • a display panel and a display device which can solve the display abnormality problem of existing display panels caused by voltage division due to different cross-voltages of light-emitting devices between pixels in the same row.
  • the transistors used in all embodiments of this application can be thin film transistors, field effect transistors, or other devices with the same characteristics. Since the sources and drains of the transistors used here are symmetrical, their sources and drains are interchangeable. of. In the embodiment of the present application, in order to distinguish the two electrodes of the transistor except the gate electrode, one electrode is called the source electrode and the other electrode is called the drain electrode. According to the shape in the attached figure, the middle terminal of the switching transistor is the gate, the signal input terminal is the source, and the output terminal is the drain. In addition, the transistors used in the embodiments of the present application are N-type transistors or P-type transistors.
  • the light-emitting device D may be a mini light-emitting diode (Mini Light Emitting Diode (Mini LED for short), or it can be a Micro Light Emitting Diode (Micro LED for short), or an Organic Light Emitting Diode (OLED for short).
  • Figure 1 is a schematic structural diagram of a display panel provided by an embodiment of the present application
  • Figure 2 is a schematic structural diagram of a driving circuit provided by an embodiment of the present application.
  • the display panel 100 provided by the embodiment of the present application includes a plurality of pixel units 110 arranged in an array.
  • the pixel units 110 include a driving circuit 10.
  • the driving circuit 10 includes a light-emitting device D, a driving transistor T0, Write the compensation module 101, the current detection module 102, and the lighting control module 103.
  • the light-emitting device D is connected in series to the light-emitting circuit formed by the first power supply terminal VDD and the second power supply terminal VSS; the source of the driving transistor T0 is electrically connected to the first power supply terminal VDD, and the drain of the driving transistor T0 is electrically connected to At the second node VS, the gate of the driving transistor T0 is electrically connected to the first node VG; the write compensation module receives the data signal DATA and the scan signal SCAN, and is electrically connected to the first node VG and the second node VS.
  • the input compensation module is used to transmit the data signal DATA to the first node VG under the control of the scan signal SCAN; the current detection module is connected to the first control signal RD and the detection signal SENSE, and is electrically connected to the second node VS.
  • the current detection module The module is used to detect the actual current flowing through the driving transistor T0, and compare the actual current with the preset current to generate a compensation voltage for the driving transistor T0; among which, the write compensation module is also used to set the threshold of the driving transistor T0 according to the compensation voltage.
  • the light-emitting control module is connected to the second control signal WR and is connected in series to the light-emitting loop. The light-emitting control module is used to control the conduction between the second node VS and the light-emitting device D under the control of the second control signal WR or disconnect.
  • the scan signal SCAN, the first control signal RD and the second control signal WR are different signals; preferably, the scan signal SCAN, the first control signal RD and the second control signal WR can be the same signal, so that The design is conducive to simplifying the circuit, saving costs and improving product market competitiveness.
  • the display panel provided by this application detects the actual current flowing through the driving transistor T0 through the current detection module, and compares the actual current with the preset current to generate a compensation voltage for the driving transistor T0; the write compensation module adjusts the driving transistor according to the compensation voltage.
  • the threshold voltage of T0 is compensated; the light-emitting control module controls the conduction or disconnection between the second node VS and the light-emitting device D under the control of the second control signal WR, wherein during the process of writing the pixel voltage, the light-emitting device D is Disconnecting can solve the display abnormality problem caused by voltage division caused by different voltage across light-emitting devices D between pixels in the same row.
  • Figure 3 is a circuit diagram of the drive circuit in the display panel provided by the first embodiment of the present application
  • Figure 4 is the timing sequence of the drive circuit in the display panel provided by the first embodiment of the present application.
  • the display panel 100 provided by the embodiment of the present application includes a plurality of pixel units 110 arranged in an array.
  • the pixel units 110 include a driving circuit 10.
  • the driving circuit 10 includes: a light-emitting device D, a driving transistor T0 , the first transistor T1, the storage capacitor Cst, the second transistor T2, and the third transistor T3. Among them, the driving transistor T0 is used to control the current flowing through the driving circuit 10.
  • the source of the driving transistor T0 is electrically connected to the first power terminal VDD.
  • the drain of the driving transistor T0 is electrically connected to the second node VS.
  • the driving transistor T0 The gate of the first transistor T1 is electrically connected to the first node VG; the gate of the first transistor T1 is connected to the scan signal SCAN, the source of the first transistor T1 is connected to the data signal DATA, and the drain of the first transistor T1 is electrically connected to the first node VG.
  • the gate of the second transistor T2 is connected to the first control signal RD, the source of the second transistor T2 is connected to the detection signal SENSE, and the drain of the second transistor T2 is electrically connected to the second node VS;
  • Three transistors T3, the gate of the third transistor T3 is connected to the scan signal SCAN, the source of the third transistor T3 is connected to the second node VS, and the drain of the third transistor T3 is electrically connected to the anode of the light-emitting device D; the light-emitting device The anode of D is electrically connected to the drain of the third transistor T3, and the cathode of the light-emitting device D is electrically connected to the second power terminal VSS.
  • both the first power supply terminal VDD and the second power supply terminal VSS are used to output a preset voltage value.
  • the potential of the first power supply terminal VDD is greater than the potential of the second power supply terminal VSS.
  • the potential of the second power supply terminal VSS may be the potential of the ground terminal.
  • the potential of the second power supply terminal VSS can also be other.
  • the driving circuit 10 further includes an inverter 104.
  • the input terminal of the inverter 104 is connected to the scanning signal SCAN, and the output terminal of the inverter 104 is electrically connected to the gate of the third transistor T3.
  • the driving transistor T0, the first transistor T1, the second transistor T2 and the third transistor T3 are transistors of the same type. Specifically, the driving transistor T0, the first transistor T1, the second transistor T2 and the third transistor T3 are all P-type transistors or N-type transistors.
  • the driving transistor T0, the first transistor T1, the second transistor T2 and the third transistor T3 may be one of low-temperature polysilicon thin film transistors, oxide semiconductor thin film transistors, amorphous silicon thin film transistors, field effect transistors, or Various.
  • the driving circuit 10 disposes an inverter 104 between the gate of the first transistor T1 and the gate of the third transistor T3.
  • the input terminal of the inverter 104 is connected to the gate terminal of the first transistor T1.
  • the scan signal SCAN, the output end of the inverter 104 is electrically connected to the gate of the third transistor T3, and the opening or closing of the third transistor T3 is controlled under the control of the scan signal SCAN.
  • the combination of the scan signal SCAN, the first control signal RD and the scan signal SCAN' under the action of the inverter 104 corresponds to the data writing phase t1 and the light emitting phase t2 successively; that is, in one frame time
  • the driving control timing sequence of the driving circuit 10 provided by the embodiment of the present application includes a data writing phase t1 and a light emitting phase t2. It should be noted that the light-emitting device D emits light in the light-emitting stage t2.
  • the scanning signal SCAN is at a high potential
  • the scanning signal SCAN' is at a low potential
  • the first control signal RD is at a high potential
  • the first transistor T1 is turned on under the control of the high potential of the scan signal SCAN.
  • the first control signal RD is at a high potential
  • the second transistor T2 is turned on under the control of the high potential of the first control signal RD, thereby transmitting the detection signal SENSE to the second node VS, detecting the actual current flowing through the driving transistor T0, and The actual current is compared with the preset current to generate a compensation voltage for driving the transistor T0.
  • the scanning signal SCAN' connected to the third transistor T3 is at a low level, and the third transistor T3 is turned off under the control of the scanning signal SCAN'.
  • the scanning signal SCAN is at a low potential
  • the first control signal RD is at a low potential
  • the scanning signal SCAN' is at a high potential.
  • the first power supply terminal VDD and the second power supply terminal VSS are both DC voltage sources.
  • FIG. 5 is a circuit diagram of a driving circuit in a display panel provided by a second embodiment of the present application.
  • the third transistor T3 is a P-type transistor
  • the first transistor T1 , the driving transistor T0 , and the second transistor T2 are all N-type transistors. Since the P-type transistor has the same effect as the inverter 104 in this embodiment, the timing of this embodiment is the same as that of the previous embodiment.
  • the display panel 100 provided by the embodiment of the present application includes a plurality of pixel units 110 arranged in an array.
  • the pixel units 110 include a drive circuit 10.
  • the drive circuit 10 specifically includes: a light-emitting device D, a driver Transistor T0, first transistor T1, storage capacitor Cst, second transistor T2, and third transistor T3.
  • the driving transistor T0 is used to control the current flowing through the driving circuit 10.
  • the source of the driving transistor T0 is electrically connected to the first power terminal VDD.
  • the drain of the driving transistor T0 is electrically connected to the second node VS.
  • the driving transistor T0 The gate of the first transistor T1 is electrically connected to the first node VG; the gate of the first transistor T1 is connected to the scan signal SCAN, the source of the first transistor T1 is connected to the data signal DATA, and the drain of the first transistor T1 is electrically connected to the first node VG.
  • the gate of the second transistor T2 is connected to the first control signal RD, the source of the second transistor T2 is connected to the detection signal SENSE, and the drain of the second transistor T2 is electrically connected to the second node VS;
  • Three transistors T3, the gate of the third transistor T3 is connected to the scan signal SCAN, the source of the third transistor T3 is connected to the second node VS, and the drain of the third transistor T3 is electrically connected to the anode of the light-emitting device D; the light-emitting device The anode of D is electrically connected to the drain of the third transistor T3, and the cathode of the light-emitting device D is electrically connected to the second power terminal VSS.
  • the display panel 100 uses a P-type transistor as the third transistor T3, and controls the third transistor T3 to turn off when the scanning signal SCAN is at a high potential, and controls the third transistor T3 to turn on when the scanning signal SCAN is at a low potential. , wherein the third transistor T3 is turned off during the writing process of the pixel voltage, that is, even if the current does not flow through the light-emitting device D, the abnormal display problem caused by the voltage division caused by the different cross-voltage of the light-emitting device D between pixels in the same row can be solved .
  • FIG. 6 is a circuit diagram of a driving circuit in a display panel provided by a third embodiment of the present application.
  • the first transistor T1 and the second transistor T2 are P-type transistors
  • the third transistor T3 and the driving transistor T0 are N-type transistors.
  • the display panel 100 provided by the embodiment of the present application includes a plurality of pixel units 110 arranged in an array.
  • the pixel units 110 include a driving circuit 10.
  • the driving circuit 10 includes: a light-emitting device D and a driving transistor T0. , the first transistor T1, the storage capacitor Cst, the second transistor T2, and the third transistor T3. Among them, the driving transistor T0 is used to control the current flowing through the driving circuit 10.
  • the source of the driving transistor T0 is electrically connected to the first power terminal VDD.
  • the drain of the driving transistor T0 is electrically connected to the second node VS.
  • the driving transistor T0 The gate of the first transistor T1 is electrically connected to the first node VG; the gate of the first transistor T1 is connected to the scan signal SCAN, the source of the first transistor T1 is connected to the data signal DATA, and the drain of the first transistor T1 is electrically connected to the first node VG.
  • the gate of the second transistor T2 is connected to the first control signal RD, the source of the second transistor T2 is connected to the detection signal SENSE, and the drain of the second transistor T2 is electrically connected to the second node VS;
  • Three transistors T3, the gate of the third transistor T3 is connected to the scan signal SCAN, the source of the third transistor T3 is connected to the second node VS, and the drain of the third transistor T3 is electrically connected to the anode of the light-emitting device D; the light-emitting device The anode of D is electrically connected to the drain of the third transistor T3, and the cathode of the light-emitting device D is electrically connected to the second power terminal VSS.
  • the first transistor T1 and the second transistor T2 are selected as P-type transistors
  • the third transistor T3 and the driving transistor T0 are selected as N-type transistors.
  • the third transistor T3 is turned off, that is, even if the current does not flow through the light-emitting device D, the display abnormality problem caused by voltage division caused by different cross-voltage of the light-emitting device D between pixels in the same row can be solved.
  • Figure 7 is a circuit diagram of a driving circuit in a display panel provided in the fourth embodiment of the present application;
  • Figure 8 is a fourth embodiment of the present application.
  • Timing diagram of the driving circuit in the display panel is provided.
  • the gate of the third transistor T3 is connected to the second control signal WR, and the driving transistor T0 , the first transistor T1 , the second transistor T2 and the third transistor T3 are transistors of the same type.
  • the driving transistor T0, the first transistor T1, the second transistor T2, and the third transistor T3 are all P-type transistors or N-type transistors.
  • the display panel 100 provided by the embodiment of the present application includes a plurality of pixel units 110 arranged in an array.
  • the pixel units 110 include a driving circuit 10.
  • the driving circuit 10 includes: a light-emitting device D and a driving transistor T0. , the first transistor T1, the storage capacitor Cst, the second transistor T2, and the third transistor T3. Among them, the driving transistor T0 is used to control the current flowing through the driving circuit 10.
  • the source of the driving transistor T0 is electrically connected to the first power terminal VDD.
  • the drain of the driving transistor T0 is electrically connected to the second node VS.
  • the driving transistor T0 The gate of the first transistor T1 is electrically connected to the first node VG; the gate of the first transistor T1 is connected to the scan signal SCAN, the source of the first transistor T1 is connected to the data signal DATA, and the drain of the first transistor T1 is electrically connected to the first node VG.
  • the gate of the second transistor T2 is connected to the first control signal RD, the source of the second transistor T2 is connected to the detection signal SENSE, and the drain of the second transistor T2 is electrically connected to the second node VS;
  • the anode of the light-emitting device D is electrically connected to the drain of the third transistor T3, and the cathode of the light-emitting device D is electrically connected to the second power terminal VSS.
  • the scan signal SCAN is at a high potential
  • the second control signal WR is at a low potential
  • the first control signal RD is at a high potential.
  • the first transistor T1 is turned on under the control of the high potential of the scan signal SCAN.
  • the first control signal RD is at a high potential
  • the second transistor T2 is turned on under the control of the high potential of the first control signal RD, thereby transmitting the detection signal SENSE to the second node VS, detecting the actual current flowing through the driving transistor T0, and The actual current is compared with the preset current to generate a compensation voltage for driving the transistor T0.
  • the second control signal WR connected to the third transistor T3 is at a low level, and the third transistor T3 is turned off under the control of the second control signal WR.
  • the scan signal SCAN is at a low potential
  • the first control signal RD is at a low potential
  • the second control signal WR is at a high potential.
  • the first power supply terminal VDD and the second power supply terminal VSS are both DC voltage sources.
  • the second control signal WR is connected to the gate of the third transistor T3, and the driving transistor T0, the first transistor T1, the second transistor T2 and the third transistor T3 are transistors of the same type.
  • the third transistor T3 is turned off during the writing process of the pixel voltage, that is, even if the current does not flow through the light-emitting device D, the abnormal display problem caused by voltage division caused by different cross-voltage of the light-emitting device D between pixels in the same row can be solved.
  • FIG. 9 is a schematic structural diagram of a backlight module provided by an embodiment of the present application.
  • the embodiment of the present application also provides a backlight module 200 , which includes a data line 20 , a first control signal RD line 30 , a second control signal WR line 40 , a scanning line 50 , a detection line 60 and the above driving circuit 10 .
  • the data line 20 is used to provide the data signal DATA.
  • the first control signal RD line 30 is used to provide the first control signal RD.
  • the second control signal WR line 40 is used to provide the second control signal WR.
  • Detection line 60 provides detection signal SENSE.
  • Scan line 50 is used to provide scan signal SCAN.
  • the driving circuit 10 is connected to the data line 20 , the first control signal RD line 30 , the second control signal WR line 40 , the scanning line 50 and the detection line 60 .
  • the light-emitting device D can be Mini-LED or Micro-LED.
  • the driving circuit 10 reference may be made to the above description of the driving circuit 10, and no further description will be given here.
  • FIG. 10 is a schematic structural diagram of a display device according to an embodiment of the present application.
  • An embodiment of the present application also provides a display device 300, which includes a driver chip 310 and a display panel 100.
  • the driver chip 310 is electrically connected to the display panel 100.
  • the display panel can be: electronic paper, mobile phones, tablets, televisions, monitors, laptops, digital photo frames, navigators, and any other product or component with a display function.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)

Abstract

一种显示面板（100）及显示装置（300），显示面板（100）包括多个呈阵列排布的像素单元（110），像素单元（110）包括驱动电路（10），驱动电路（10）包括：发光器件（D）、驱动晶体管（T0）、写入补偿模块（101）、电流检测模块（102）以及发光控制模块（103）。可以解决因同一行像素之间发光器件（D）跨压不同引起分压导致的显示异常问题。

Description

显示面板及显示装置 技术领域
本申请涉及显示技术领域，具体涉及一种显示面板及显示装置。
 背景技术
有机发光二极管是主动发光器件，与液晶显示方式相比，有机发光二极管无需提供背光源，且有机发光二极管显示装置具有超薄、亮度高、驱动电压低等优点，被认为是下一代显示装置。
在现有大尺寸有机发光二极管显示中，在扫描到同一行像素时，写入控制信号和读取控制信号会同时打开，然后加入不同的数据电压和检测电压，用于控制驱动晶体管的开启大小，从而控制流经有机发光二极管器件的电流，用于实现不同亮度的显示，其中相邻的像素与同一检测信号线连接，也即施加相同的检测电压。
由于有机发光二极管器件的电流-电压特性并不是理想的二极管特性，其跨压会随着电流的增大（亮度升高）而有少量的增大。这就使得在写入控制信号和读取控制信号同时开启，并且在数据信号和检测信号写入电压的过程中产生偏差，其偏差来源于更高亮度的二极管的跨压更高，使得其检测端电压更高，这样在同一行像素开启写入检测电压的过程中，较高的检测电压的像素会分压给较低的检测电压像素，从而造成数据电压-检测电压跨压的失真，进而导致灰阶电压的失真造成横向串扰等显示异常现象。
 技术问题
本申请提供一种显示面板及显示装置，通过在像素电压写入的过程中使发光器件断开连接，以解决现有的显示面板因同一行像素之间发光器件跨压不同引起分压导致的显示异常问题。
 技术解决方案
第一方面，本申请实施例提供一种显示面板，其包括多个呈阵列排布的像素单元，所述像素单元包括驱动电路，所述驱动电路包括：发光器件、驱动晶体管、写入补偿模块、电流检测模块以及发光控制模块，所述发光器件串接于发光回路；所述驱动晶体管的源极和漏极串接于所述发光回路，所述驱动晶体管的栅极电性连接于第一节点；所述写入补偿模块接入数据信号以及扫描信号，并电性连接于所述第一节点以及第二节点，所述写入补偿模块用于在所述扫描信号的控制下将所述数据信号传输至所述第一节点；所述电流检测模块接入第一控制信号以及检测信号，并电性连接于所述第二节点，所述电流检测模块用于检测流经所述驱动晶体管的实际电流，并将所述实际电流与预设电流比较，以生成所述驱动晶体管的补偿电压；其中，所述写入补偿模块还用于根据所述补偿电压对所述驱动晶体管的阈值电压进行补偿；所述发光控制模块接入第二控制信号，并串接于所述发光回路，所述发光控制模块用于在所述第二控制信号的控制下控制所述第二节点与所述发光器件之间导通或者断开。
可选地，在本申请的一些实施例中，所述写入补偿模块包括第一晶体管以及存储电容；所述第一晶体管的栅极接入所述扫描信号，所述第一晶体管的源级和漏极中的一者接入所述数据信号，所述第一晶体管的源级和漏极中的另一者电性连接于所述第一节点；所述存储电容的第一端电性连接于所述第一节点，所述存储电容的第二端电性连接于所述第二节点。
可选地，在本申请的一些实施例中，电流检测模块包括第二晶体管，所述第二晶体管的栅极接入所述第一控制信号，所述第二晶体管的源级和漏极中的一者接入所述检测信号，所述第二晶体管的源级和漏极中的另一者电性连接于所述第二节点。
可选地，在本申请的一些实施例中，所述发光控制模块包括第三晶体管，所述第三晶体管的栅极接入所述第二控制信号，所述第三晶体管的源级和漏极中的一者接入所述第二节点，所述第三晶体管的源级和漏极中的另一者电性连接于所述发光器件的阳极。
可选地，在本申请的一些实施例中，所述扫描信号、所述第一控制信号以及所述第二控制信号为同一信号。
可选地，在本申请的一些实施例中，所述驱动晶体管、所述第一晶体管以及所述第二晶体管均为N型晶体管，所述第三晶体管为P型晶体管。
可选地，在本申请的一些实施例中，所述第一晶体管和所述第二晶体管为P型晶体管，所述第三晶体管和所述驱动晶体管为N型晶体管。
可选地，在本申请的一些实施例中，所述发光控制模块还包括反相器，所述反相器的输入端接入所述扫描信号，所述反相器的输出端电性连接于所述第三晶体管的栅极。
可选地，在本申请的一些实施例中，所述驱动晶体管、所述第一晶体管、所述第二晶体管以及所述第三晶体管为同类型晶体管。
可选地，在本申请的一些实施例中，所述扫描信号、所述第一控制信号以及所述第二控制信号相组合先后对应于数据写入阶段以及发光阶段。
另一方面，本申请提供一种显示装置，包括驱动芯片以及显示面板，所述驱动芯片与所述显示面板电连接，其中所述显示面板包括多个呈阵列排布的像素单元，所述像素单元包括驱动电路，所述驱动电路包括：发光器件、驱动晶体管、写入补偿模块、电流检测模块以及发光控制模块，所述发光器件串接于发光回路；所述驱动晶体管的源极和漏极串接于所述发光回路，所述驱动晶体管的栅极电性连接于第一节点；所述写入补偿模块接入数据信号以及扫描信号，并电性连接于所述第一节点以及第二节点，所述写入补偿模块用于在所述扫描信号的控制下将所述数据信号传输至所述第一节点；所述电流检测模块接入第一控制信号以及检测信号，并电性连接于所述第二节点，所述电流检测模块用于检测流经所述驱动晶体管的实际电流，并将所述实际电流与预设电流比较，以生成所述驱动晶体管的补偿电压；其中，所述写入补偿模块还用于根据所述补偿电压对所述驱动晶体管的阈值电压进行补偿；所述发光控制模块接入第二控制信号，并串接于所述发光回路，所述发光控制模块用于在所述第二控制信号的控制下控制所述第二节点与所述发光器件之间导通或者断开。
可选地，在本申请的一些实施例中，所述写入补偿模块包括第一晶体管以及存储电容；所述第一晶体管的栅极接入所述扫描信号，所述第一晶体管的源级和漏极中的一者接入所述数据信号，所述第一晶体管的源级和漏极中的另一者电性连接于所述第一节点；所述存储电容的第一端电性连接于所述第一节点，所述存储电容的第二端电性连接于所述第二节点。
可选地，在本申请的一些实施例中，电流检测模块包括第二晶体管，所述第二晶体管的栅极接入所述第一控制信号，所述第二晶体管的源级和漏极中的一者接入所述检测信号，所述第二晶体管的源级和漏极中的另一者电性连接于所述第二节点。
可选地，在本申请的一些实施例中，所述发光控制模块包括第三晶体管，所述第三晶体管的栅极接入所述第二控制信号，所述第三晶体管的源级和漏极中的一者接入所述第二节点，所述第三晶体管的源级和漏极中的另一者电性连接于所述发光器件的阳极。
可选地，在本申请的一些实施例中，所述扫描信号、所述第一控制信号以及所述第二控制信号为同一信号。
可选地，在本申请的一些实施例中，所述驱动晶体管、所述第一晶体管以及所述第二晶体管均为N型晶体管，所述第三晶体管为P型晶体管。
可选地，在本申请的一些实施例中，所述第一晶体管和所述第二晶体管为P型晶体管，所述第三晶体管和所述驱动晶体管为N型晶体管。
可选地，在本申请的一些实施例中，所述发光控制模块还包括反相器，所述反相器的输入端接入所述扫描信号，所述反相器的输出端电性连接于所述第三晶体管的栅极。
可选地，在本申请的一些实施例中，所述驱动晶体管、所述第一晶体管、所述第二晶体管以及所述第三晶体管为同类型晶体管。
可选地，在本申请的一些实施例中，所述扫描信号、所述第一控制信号以及所述第二控制信号相组合先后对应于数据写入阶段以及发光阶段。
 有益效果
本申请提供一种显示面板及显示装置，该显示面板包括多个呈阵列排布的像素单元，所述像素单元包括驱动电路，所述驱动电路包括发光器件、驱动晶体管、写入补偿模块、电流检测模块以及发光控制模块，发光器件串接于发光回路；驱动晶体管的源极和漏极串接于发光回路，驱动晶体管的栅极电性连接于第一节点；写入补偿模块用于在扫描信号的控制下将数据信号传输至第一节点；电流检测模块用于检测流经驱动晶体管的实际电流，并将实际电流与预设电流比较，以生成驱动晶体管的补偿电压；其中，写入补偿模块还用于根据补偿电压对驱动晶体管的阈值电压进行补偿；发光控制模块用于在第二控制信号的控制下控制第二节点与发光器件之间导通或者断开。通过在像素电压写入的过程中使发光器件断开连接，以解决因同一行像素之间发光器件跨压不同引起分压导致的显示异常问题。
 附图说明
为了更清楚地说明本申请实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，下面描述中的附图仅仅是本申请的一些实施例，对于本领域技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本申请实施例提供的显示面板的结构示意图；
图2为本申请实施例提供的驱动电路的结构示意图；
图3是本申请第一实施例提供的显示面板中驱动电路的电路图；
图4是本申请第一实施例提供的显示面板中驱动电路的时序图；
图5是本申请第二实施例提供的显示面板中驱动电路的电路图；
图6是本申请第三实施例提供的显示面板中驱动电路的电路图；
图7是本申请第四实施例提供的显示面板中驱动电路的电路图；
图8是本申请第四实施例提供的显示面板中驱动电路的时序图；
图9是本申请实施例提供的背光模组的结构示意图；
图10是本申请实施例提供的显示装置的结构示意图。
 本发明的实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述。显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
本申请实施例提供一种显示面板及显示装置，可以解决现有的显示面板因同一行像素之间发光器件跨压不同引起分压导致的显示异常问题。以下分别进行详细说明。需说明的是，以下实施例的描述顺序不作为对实施例优选顺序的限定。另外，在本申请的描述中，术语“包括”是指“包括但不限于”。术语“第一”、“第二”、“第三”等仅仅作为标示使用，其用于区别不同对象，而不是用于描述特定顺序。
本申请所有实施例中采用的晶体管可以为薄膜晶体管或场效应管或其他特性相同的器件，由于这里采用的晶体管的源极、漏极是对称的，所以其源极、漏极是可以互换的。在本申请实施例中，为区分晶体管除栅极之外的两极，将其中一极称为源极，另一极称为漏极。按附图中的形态规定开关晶体管的中间端为栅极、信号输入端为源极、输出端为漏极。此外本申请实施例所采用的晶体管为N型晶体管或P型晶体管，其中，N型晶体管为在栅极为高电位时导通，在栅极为低电位时截止；P型晶体管为在栅极为低电位时导通，在栅极为高电位时截止。在本申请实施例中，发光器件D可以是迷你发光二极管(Mini Light Emitting Diode，简称Mini LED)，或者，可以是微型发光二极管(Micro Light Emitting Diode，简称Micro LED)，也可以是有机发光二极管(Organic Light Emitting Diode，简称OLED)。
请参阅图1和图2，图1为本申请实施例提供的显示面板的结构示意图；图2为本申请实施例提供的驱动电路的结构示意图。如图1和图2所示，本申请实施例提供的显示面板100包括多个呈阵列排布的像素单元110，像素单元110包括驱动电路10，驱动电路10包括发光器件D、驱动晶体管T0、写入补偿模块101、电流检测模块102、发光控制模块103。
其中，发光器件D串接于第一电源端VDD与第二电源端VSS构成的发光回路；驱动晶体管T0的源极电性连接于第一电源端VDD，驱动晶体管T0的漏极电性连接于第二节点VS，驱动晶体管T0的栅极电性连接于第一节点VG；写入补偿模块接入数据信号DATA以及扫描信号SCAN，并电性连接于第一节点VG以及第二节点VS，写入补偿模块用于在扫描信号SCAN的控制下将数据信号DATA传输至第一节点VG；电流检测模块接入第一控制信号RD以及检测信号SENSE，并电性连接于第二节点VS，电流检测模块用于检测流经驱动晶体管T0的实际电流，并将实际电流与预设电流比较，以生成驱动晶体管T0的补偿电压；其中，写入补偿模块还用于根据补偿电压对驱动晶体管T0的阈值电压进行补偿；发光控制模块接入第二控制信号WR，并串接于发光回路，发光控制模块用于在第二控制信号WR的控制下控制第二节点VS与发光器件D之间导通或者断开。
在本申请实施例中，扫描信号SCAN、第一控制信号RD以及第二控制信号WR为不同信号；优选地，扫描信号SCAN、第一控制信号RD以及第二控制信号WR可以为同一信号，这样的设计，有利于简化电路，节约成本提升产品市场竞争力。
本申请提供的显示面板，通过电流检测模块检测流经驱动晶体管T0的实际电流，并将实际电流与预设电流比较，以生成驱动晶体管T0的补偿电压；写入补偿模块根据补偿电压对驱动晶体管T0的阈值电压进行补偿；发光控制模块在第二控制信号WR的控制下控制第二节点VS与发光器件D之间导通或者断开，其中，在像素电压写入的过程中使发光器件D断开连接，可以解决因同一行像素之间发光器件D跨压不同引起分压导致的显示异常问题。
请继续参阅图1并参阅图3和图4，图3是本申请第一实施例提供的显示面板中驱动电路的电路图；图4是本申请第一实施例提供的显示面板中驱动电路的时序图。如图1和图3所示，本申请实施例提供的显示面板100包括多个呈阵列排布的像素单元110，像素单元110包括驱动电路10，驱动电路10包括：发光器件D、驱动晶体管T0、第一晶体管T1、存储电容Cst、第二晶体管T2、第三晶体管T3。其中，驱动晶体管T0用于控制流经驱动电路10的电流，驱动晶体管T0的源极电性连接于第一电源端VDD，驱动晶体管T0的漏极电性连接于第二节点VS，驱动晶体管T0的栅极电性连接于第一节点VG；第一晶体管T1的栅极接入扫描信号SCAN，第一晶体管T1的源级接入数据信号DATA，第一晶体管T1的漏极电性连接于第一节点VG；存储电容Cst的第一端电性连接于第一节点VG，存储电容Cst的第二端电性连接于第二节点VS，存储电容Cst为驱动晶体管T0的栅极电压保持电容；第二晶体管T2，第二晶体管T2的栅极接入第一控制信号RD，第二晶体管T2的源级接入检测信号SENSE，第二晶体管T2的漏极电性连接于第二节点VS；第三晶体管T3，第三晶体管T3的栅极接入扫描信号SCAN，第三晶体管T3的源级接入第二节点VS，第三晶体管T3的漏极电性连接于发光器件D的阳极；发光器件D的阳极与第三晶体管T3的漏极电性连接，发光器件D的阴极与第二电源端VSS电性连接。
需要说明的是，第一电源端VDD和第二电源端VSS均用于输出一预设电压值。此外，在本申请实施例中，第一电源端VDD的电位大于第二电源端VSS的电位。具体的，第二电源端VSS的电位可以为接地端的电位。当然，可以理解地，第二电源端VSS的电位还可以为其它。
在本申请实施例中，驱动电路10还包括反相器104，反相器104的输入端接入扫描信号SCAN，反相器104的输出端电性连接于第三晶体管T3的栅极。
在本申请实施例中，驱动晶体管T0、第一晶体管T1、第二晶体管T2以及第三晶体管T3为同类型晶体管，具体地，驱动晶体管T0、第一晶体管T1、第二晶体管T2以及第三晶体管T3均为P型晶体管或N型晶体管。
需要说明的是，驱动晶体管T0、第一晶体管T1、第二晶体管T2以及第三晶体管T3可以为低温多晶硅薄膜晶体管、氧化物半导体薄膜晶体管或非晶硅薄膜晶体管、场效应晶体管中的一种或者多种。
本申请实施例提供的驱动电路10，通过在第一晶体管T1的栅极与第三晶体管T3的栅极之间设置反相器104，反相器104的输入端接入第一晶体管T1栅极端的扫描信号SCAN，反相器104的输出端电性连接于第三晶体管T3的栅极，在扫描信号SCAN的控制下控制第三晶体管T3的打开或者关闭，其中，在像素电压写入的过程中使第三晶体管T3关闭，也即使电流不流经发光器件D，可以解决因同一行像素之间发光器件D跨压不同引起分压导致的显示异常问题。
如图4所示，扫描信号SCAN、第一控制信号RD以及在反相器104作用下的扫描信号SCAN’相组合先后对应于数据写入阶段t1及发光阶段t2；也即，在一帧时间内，本申请实施例提供的驱动电路10的驱动控制时序包括数据写入阶段t1及发光阶段t2。需要说明的是，发光器件D在发光阶段t2发光。
具体的，如图3和图4所示，在数据写入阶段t1，扫描信号SCAN为高电位，扫描信号SCAN’为低电位，第一控制信号RD为高电位。
第一晶体管T1在扫描信号SCAN的高电位控制下打开。第一控制信号RD为高电位，第二晶体管T2在第一控制信号RD的高电位控制下打开，从而将检测信号SENSE传输至第二节点VS，检测流经驱动晶体管T0的实际电流，并将实际电流与预设电流比较，以生成驱动晶体管T0的补偿电压。
另外，在反相器104的作用下，第三晶体管T3接入的扫描信号SCAN’为低电位，第三晶体管T3在扫描信号SCAN’的控制下关闭。
在发光阶段t2，扫描信号SCAN为低电位，第一控制信号RD为低电位，扫描信号SCAN’为高电位。
具体的，第一电源端VDD和第二电源端VSS均为直流电压源。
作为本申请的一个具体实施方式，请继续参阅图1并参阅图5，图5是本申请第二实施例提供的显示面板中驱动电路的电路图。如图5所示，第三晶体管T3为P型晶体管，第一晶体管T1、驱动晶体管T0、第二晶体管T2均为N型晶体管。由于在本实施例中P型晶体管具有反相器104相同的效果，故本实施例的时序与上一实施例相同。
如图1和图5所示，本申请实施例提供的显示面板100包括多个呈阵列排布的像素单元110，像素单元110包括驱动电路10，驱动电路10包括具体包括：发光器件D、驱动晶体管T0、第一晶体管T1、存储电容Cst、第二晶体管T2、第三晶体管T3。其中，驱动晶体管T0用于控制流经驱动电路10的电流，驱动晶体管T0的源极电性连接于第一电源端VDD，驱动晶体管T0的漏极电性连接于第二节点VS，驱动晶体管T0的栅极电性连接于第一节点VG；第一晶体管T1的栅极接入扫描信号SCAN，第一晶体管T1的源级接入数据信号DATA，第一晶体管T1的漏极电性连接于第一节点VG；存储电容Cst的第一端电性连接于第一节点VG，存储电容Cst的第二端电性连接于第二节点VS，存储电容Cst为驱动晶体管T0的栅极电压保持电容；第二晶体管T2，第二晶体管T2的栅极接入第一控制信号RD，第二晶体管T2的源级接入检测信号SENSE，第二晶体管T2的漏极电性连接于第二节点VS；第三晶体管T3，第三晶体管T3的栅极接入扫描信号SCAN，第三晶体管T3的源级接入第二节点VS，第三晶体管T3的漏极电性连接于发光器件D的阳极；发光器件D的阳极与第三晶体管T3的漏极电性连接，发光器件D的阴极与第二电源端VSS电性连接。
本申请实施例提供的显示面板100，通过使用P型晶体管作为第三晶体管T3，在扫描信号SCAN为高电位时控制第三晶体管T3关闭，在扫描信号SCAN为低电位时控制第三晶体管T3打开，其中，在像素电压写入的过程中使第三晶体管T3关闭，也即使电流不流经发光器件D，可以解决因同一行像素之间发光器件D跨压不同引起分压导致的显示异常问题。
作为本申请的一个具体实施方式，请继续参阅图1并参阅图6，图6是本申请第三实施例提供的显示面板中驱动电路的电路图。如图6所示，第一晶体管T1和第二晶体管T2为P型晶体管，第三晶体管T3和驱动晶体管T0为N型晶体管。
如图1和图6所示，本申请实施例提供的显示面板100包括多个呈阵列排布的像素单元110，像素单元110包括驱动电路10，驱动电路10包括：发光器件D、驱动晶体管T0、第一晶体管T1、存储电容Cst、第二晶体管T2、第三晶体管T3。其中，驱动晶体管T0用于控制流经驱动电路10的电流，驱动晶体管T0的源极电性连接于第一电源端VDD，驱动晶体管T0的漏极电性连接于第二节点VS，驱动晶体管T0的栅极电性连接于第一节点VG；第一晶体管T1的栅极接入扫描信号SCAN，第一晶体管T1的源级接入数据信号DATA，第一晶体管T1的漏极电性连接于第一节点VG；存储电容Cst的第一端电性连接于第一节点VG，存储电容Cst的第二端电性连接于第二节点VS，存储电容Cst为驱动晶体管T0的栅极电压保持电容；第二晶体管T2，第二晶体管T2的栅极接入第一控制信号RD，第二晶体管T2的源级接入检测信号SENSE，第二晶体管T2的漏极电性连接于第二节点VS；第三晶体管T3，第三晶体管T3的栅极接入扫描信号SCAN，第三晶体管T3的源级接入第二节点VS，第三晶体管T3的漏极电性连接于发光器件D的阳极；发光器件D的阳极与第三晶体管T3的漏极电性连接，发光器件D的阴极与第二电源端VSS电性连接。
本申请实施例提供的显示面板100，通过将第一晶体管T1和第二晶体管T2选用P型晶体管，第三晶体管T3和驱动晶体管T0选用N型晶体管，其中，在像素电压写入的过程中使第三晶体管T3关闭，也即使电流不流经发光器件D，可以解决因同一行像素之间发光器件D跨压不同引起分压导致的显示异常问题。
作为本申请的一个具体实施方式，请继续参阅图1并参阅图7和图8，图7是本申请第四实施例提供的显示面板中驱动电路的电路图；图8是本申请第四实施例提供的显示面板中驱动电路的时序图。如图7所示，第三晶体管T3的栅极接入第二控制信号WR，且驱动晶体管T0、第一晶体管T1、第二晶体管T2以及第三晶体管T3为同类型晶体管。具体地，驱动晶体管T0、第一晶体管T1、第二晶体管T2以及第三晶体管T3均为P型晶体管或N型晶体管。
如图1和图7所示，本申请实施例提供的显示面板100包括多个呈阵列排布的像素单元110，像素单元110包括驱动电路10，驱动电路10包括：发光器件D、驱动晶体管T0、第一晶体管T1、存储电容Cst、第二晶体管T2、第三晶体管T3。其中，驱动晶体管T0用于控制流经驱动电路10的电流，驱动晶体管T0的源极电性连接于第一电源端VDD，驱动晶体管T0的漏极电性连接于第二节点VS，驱动晶体管T0的栅极电性连接于第一节点VG；第一晶体管T1的栅极接入扫描信号SCAN，第一晶体管T1的源级接入数据信号DATA，第一晶体管T1的漏极电性连接于第一节点VG；存储电容Cst的第一端电性连接于第一节点VG，存储电容Cst的第二端电性连接于第二节点VS，存储电容Cst为驱动晶体管T0的栅极电压保持电容；第二晶体管T2，第二晶体管T2的栅极接入第一控制信号RD，第二晶体管T2的源级接入检测信号SENSE，第二晶体管T2的漏极电性连接于第二节点VS；第三晶体管T3，第三晶体管T3的栅极接入第二控制信号WR，第三晶体管T3的源级接入第二节点VS，第三晶体管T3的漏极电性连接于发光器件D的阳极；发光器件D的阳极与第三晶体管T3的漏极电性连接，发光器件D的阴极与第二电源端VSS电性连接。
如图8所示，在数据写入阶段t1，扫描信号SCAN为高电位，第二控制信号WR为低电位，第一控制信号RD为高电位。
第一晶体管T1在扫描信号SCAN的高电位控制下打开。第一控制信号RD为高电位，第二晶体管T2在第一控制信号RD的高电位控制下打开，从而将检测信号SENSE传输至第二节点VS，检测流经驱动晶体管T0的实际电流，并将实际电流与预设电流比较，以生成驱动晶体管T0的补偿电压。
第三晶体管T3接入的第二控制信号WR为低电位，第三晶体管T3在第二控制信号WR的控制下关闭。
在发光阶段t2，扫描信号SCAN为低电位，第一控制信号RD为低电位，第二控制信号WR为高电位。
具体的，第一电源端VDD和第二电源端VSS均为直流电压源。
本申请实施例提供的显示面板100，通过第三晶体管T3的栅极接入第二控制信号WR，且驱动晶体管T0、第一晶体管T1、第二晶体管T2以及第三晶体管T3为同类型晶体管，其中，在像素电压写入的过程中使第三晶体管T3关闭，也即使电流不流经发光器件D，可以解决因同一行像素之间发光器件D跨压不同引起分压导致的显示异常问题。
请参阅图9，图9为本申请实施例提供的背光模组的结构示意图。本申请实施例还提供一种背光模组200，其包括数据线20、第一控制信号RD线30、第二控制信号WR线40、扫描线50、检测线60以及以上的驱动电路10。其中，数据线20用于提供数据信号DATA。第一控制信号RD线30用于提供第一控制信号RD。第二控制信号WR线40用于提供第二控制信号WR。检测线60提供检测信号SENSE。扫描线50用于提供扫描信号SCAN。驱动电路10与数据线20、第一控制信号RD线30、第二控制信号WR线40、扫描线50、检测线60均连接。其中，发光器件D可以是Mini-LED、Micro-LED。驱动电路10具体可参照以上对该驱动电路10的描述，在此不做赘述。
请参阅图10，图10为本申请实施例提供的显示装置的结构示意图。本申请实施例还提供一种显示装置300，包括驱动芯片310和显示面板100，驱动芯片310与显示面板100电连接。
该显示面板可以为：电子纸、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
以上对本申请实施例所提供的一种显示面板及显示装置进行了详细介绍，本文中应用了具体个例对本申请的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本申请的方法及其核心思想；同时，对于本领域的技术人员，依据本申请的思想，在具体实施方式及应用范围上均会有改变之处，综上，本说明书内容不应理解为对本申请的限制。

Claims (20)

  1. 一种显示面板，其包括多个呈阵列排布的像素单元，所述像素单元包括驱动电路，所述驱动电路包括：
    发光器件，所述发光器件串接于发光回路；
    驱动晶体管，所述驱动晶体管的源极和漏极串接于所述发光回路，所述驱动晶体管的栅极电性连接于第一节点；
    写入补偿模块，所述写入补偿模块接入数据信号以及扫描信号，并电性连接于所述第一节点以及第二节点，所述写入补偿模块用于在所述扫描信号的控制下将所述数据信号传输至所述第一节点；
    电流检测模块，所述电流检测模块接入第一控制信号以及检测信号，并电性连接于所述第二节点，所述电流检测模块用于检测流经所述驱动晶体管的实际电流，并将所述实际电流与预设电流比较，以生成所述驱动晶体管的补偿电压；其中，所述写入补偿模块还用于根据所述补偿电压对所述驱动晶体管的阈值电压进行补偿；以及
    发光控制模块，所述发光控制模块接入第二控制信号，并串接于所述发光回路，所述发光控制模块用于在所述第二控制信号的控制下控制所述第二节点与所述发光器件之间导通或者断开。
  2. 根据权利要求1所述的显示面板，其中，所述写入补偿模块包括第一晶体管以及存储电容；
    所述第一晶体管的栅极接入所述扫描信号，所述第一晶体管的源级和漏极中的一者接入所述数据信号，所述第一晶体管的源级和漏极中的另一者电性连接于所述第一节点；
    所述存储电容的第一端电性连接于所述第一节点，所述存储电容的第二端电性连接于所述第二节点。
  3. 根据权利要求2所述的显示面板，其中，电流检测模块包括第二晶体管，所述第二晶体管的栅极接入所述第一控制信号，所述第二晶体管的源级和漏极中的一者接入所述检测信号，所述第二晶体管的源级和漏极中的另一者电性连接于所述第二节点。
  4. 根据权利要求3所述的显示面板，其中，所述发光控制模块包括第三晶体管，所述第三晶体管的栅极接入所述第二控制信号，所述第三晶体管的源级和漏极中的一者接入所述第二节点，所述第三晶体管的源级和漏极中的另一者电性连接于所述发光器件的阳极。
  5. 根据权利要求4所述的显示面板，其中，所述扫描信号、所述第一控制信号以及所述第二控制信号为同一信号。
  6. 根据权利要求5所述的显示面板，其中，所述驱动晶体管、所述第一晶体管以及所述第二晶体管均为N型晶体管，所述第三晶体管为P型晶体管。
  7. 根据权利要求5所述的显示面板，其中，所述第一晶体管和所述第二晶体管为P型晶体管，所述第三晶体管和所述驱动晶体管为N型晶体管。
  8. 根据权利要求5所述的显示面板，其中，所述发光控制模块还包括反相器，所述反相器的输入端接入所述扫描信号，所述反相器的输出端电性连接于所述第三晶体管的栅极。
  9. 根据权利要求8所述的显示面板，其中，所述驱动晶体管、所述第一晶体管、所述第二晶体管以及所述第三晶体管为同类型晶体管。
  10. 根据权利要求1所述的显示面板，其中，所述扫描信号、所述第一控制信号以及所述第二控制信号相组合先后对应于数据写入阶段以及发光阶段。
  11. 一种显示装置，其包括驱动芯片以及显示面板，所述驱动芯片与所述显示面板电连接，其中，所述显示面板包括多个呈阵列排布的像素单元，所述像素单元包括驱动电路，所述驱动电路包括：
    发光器件，所述发光器件串接于发光回路；
    驱动晶体管，所述驱动晶体管的源极和漏极串接于所述发光回路，所述驱动晶体管的栅极电性连接于第一节点；
    写入补偿模块，所述写入补偿模块接入数据信号以及扫描信号，并电性连接于所述第一节点以及第二节点，所述写入补偿模块用于在所述扫描信号的控制下将所述数据信号传输至所述第一节点；
    电流检测模块，所述电流检测模块接入第一控制信号以及检测信号，并电性连接于所述第二节点，所述电流检测模块用于检测流经所述驱动晶体管的实际电流，并将所述实际电流与预设电流比较，以生成所述驱动晶体管的补偿电压；其中，所述写入补偿模块还用于根据所述补偿电压对所述驱动晶体管的阈值电压进行补偿；以及
    发光控制模块，所述发光控制模块接入第二控制信号，并串接于所述发光回路，所述发光控制模块用于在所述第二控制信号的控制下控制所述第二节点与所述发光器件之间导通或者断开。
  12. 根据权利要求11所述的显示装置，其中，所述写入补偿模块包括第一晶体管以及存储电容；
    所述第一晶体管的栅极接入所述扫描信号，所述第一晶体管的源级和漏极中的一者接入所述数据信号，所述第一晶体管的源级和漏极中的另一者电性连接于所述第一节点；
    所述存储电容的第一端电性连接于所述第一节点，所述存储电容的第二端电性连接于所述第二节点。
  13. 根据权利要求12所述的显示装置，其中，电流检测模块包括第二晶体管，所述第二晶体管的栅极接入所述第一控制信号，所述第二晶体管的源级和漏极中的一者接入所述检测信号，所述第二晶体管的源级和漏极中的另一者电性连接于所述第二节点。
  14. 根据权利要求13所述的显示装置，其中，所述发光控制模块包括第三晶体管，所述第三晶体管的栅极接入所述第二控制信号，所述第三晶体管的源级和漏极中的一者接入所述第二节点，所述第三晶体管的源级和漏极中的另一者电性连接于所述发光器件的阳极。
  15. 根据权利要求14所述的显示装置，其中，所述扫描信号、所述第一控制信号以及所述第二控制信号为同一信号。
  16. 根据权利要求15所述的显示装置，其中，所述驱动晶体管、所述第一晶体管以及所述第二晶体管均为N型晶体管，所述第三晶体管为P型晶体管。
  17. 根据权利要求15所述的显示装置，其中，所述第一晶体管和所述第二晶体管为P型晶体管，所述第三晶体管和所述驱动晶体管为N型晶体管。
  18. 根据权利要求15所述的显示装置，其中，所述发光控制模块还包括反相器，所述反相器的输入端接入所述扫描信号，所述反相器的输出端电性连接于所述第三晶体管的栅极。
  19. 根据权利要求18所述的显示装置，其中，所述驱动晶体管、所述第一晶体管、所述第二晶体管以及所述第三晶体管为同类型晶体管。
  20. 根据权利要求11所述的显示装置，其中，所述扫描信号、所述第一控制信号以及所述第二控制信号相组合先后对应于数据写入阶段以及发光阶段。
PCT/CN2022/086884 2022-04-01 2022-04-14 显示面板及显示装置 WO2023184588A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US17/756,652 US20240161690A1 (en) 2022-04-01 2022-04-14 Display panel and display device

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202210347158.0A CN114783376A (zh) 2022-04-01 2022-04-01 显示面板及显示装置
CN202210347158.0 2022-04-01

Publications (1)

Publication Number Publication Date
WO2023184588A1 true WO2023184588A1 (zh) 2023-10-05

Family

ID=82427751

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2022/086884 WO2023184588A1 (zh) 2022-04-01 2022-04-14 显示面板及显示装置

Country Status (3)

Country Link
US (1) US20240161690A1 (zh)
CN (1) CN114783376A (zh)
WO (1) WO2023184588A1 (zh)

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100624137B1 (ko) * 2005-08-22 2006-09-13 삼성에스디아이 주식회사 유기 전계 발광 표시장치의 화소회로 및 그의 구동방법
KR20130087128A (ko) * 2012-01-27 2013-08-06 삼성디스플레이 주식회사 화소 회로, 그 구동 방법, 및 이를 포함하는 유기 발광 표시 장치
CN106910468A (zh) * 2017-04-28 2017-06-30 上海天马有机发光显示技术有限公司 显示面板、显示装置及像素电路的驱动方法
CN107464526A (zh) * 2017-09-28 2017-12-12 京东方科技集团股份有限公司 一种像素补偿电路、其驱动方法及显示装置
CN113571009A (zh) * 2021-07-22 2021-10-29 深圳市华星光电半导体显示技术有限公司 发光器件驱动电路、背光模组以及显示面板
CN113838421A (zh) * 2021-07-30 2021-12-24 京东方科技集团股份有限公司 像素电路及其驱动方法、显示面板
CN114120874A (zh) * 2021-11-24 2022-03-01 Tcl华星光电技术有限公司 发光器件驱动电路、背光模组以及显示面板

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100873707B1 (ko) * 2007-07-27 2008-12-12 삼성모바일디스플레이주식회사 유기전계발광 표시장치 및 그의 구동방법
KR101201722B1 (ko) * 2010-02-23 2012-11-15 삼성디스플레이 주식회사 유기 발광 표시 장치 및 그의 구동 방법
CN104867442B (zh) * 2014-02-20 2017-10-31 北京大学深圳研究生院 一种像素电路及显示装置
CN105702206B (zh) * 2016-03-04 2018-11-30 北京大学深圳研究生院 一种像素矩阵的外围补偿系统及其方法、显示系统
CN106097962B (zh) * 2016-08-19 2018-09-07 京东方科技集团股份有限公司 显示基板、显示设备及区域补偿方法
CN107342052B (zh) * 2017-08-18 2019-07-26 深圳市华星光电半导体显示技术有限公司 用于oled显示设备的像素驱动电路
CN110660360B (zh) * 2019-10-12 2021-05-25 京东方科技集团股份有限公司 像素电路及其驱动方法、显示面板
CN111369947A (zh) * 2020-04-09 2020-07-03 深圳市华星光电半导体显示技术有限公司 像素补偿驱动电路及其驱动方法、显示装置
JP2022021645A (ja) * 2020-07-22 2022-02-03 武漢天馬微電子有限公司 表示装置
CN113066434B (zh) * 2021-03-24 2023-07-18 京东方科技集团股份有限公司 像素驱动电路及其驱动方法、显示面板

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100624137B1 (ko) * 2005-08-22 2006-09-13 삼성에스디아이 주식회사 유기 전계 발광 표시장치의 화소회로 및 그의 구동방법
KR20130087128A (ko) * 2012-01-27 2013-08-06 삼성디스플레이 주식회사 화소 회로, 그 구동 방법, 및 이를 포함하는 유기 발광 표시 장치
CN106910468A (zh) * 2017-04-28 2017-06-30 上海天马有机发光显示技术有限公司 显示面板、显示装置及像素电路的驱动方法
CN107464526A (zh) * 2017-09-28 2017-12-12 京东方科技集团股份有限公司 一种像素补偿电路、其驱动方法及显示装置
CN113571009A (zh) * 2021-07-22 2021-10-29 深圳市华星光电半导体显示技术有限公司 发光器件驱动电路、背光模组以及显示面板
CN113838421A (zh) * 2021-07-30 2021-12-24 京东方科技集团股份有限公司 像素电路及其驱动方法、显示面板
CN114120874A (zh) * 2021-11-24 2022-03-01 Tcl华星光电技术有限公司 发光器件驱动电路、背光模组以及显示面板

Also Published As

Publication number Publication date
CN114783376A (zh) 2022-07-22
US20240161690A1 (en) 2024-05-16

Similar Documents

Publication Publication Date Title
US10971067B1 (en) AMOLED pixel driving circuit, driving method and terminal
US11935470B2 (en) Pixel circuit and driving method thereof, and display device
CN107507568A (zh) 一种oled像素电路及减缓oled器件老化的方法
WO2021023201A1 (zh) 像素阵列、阵列基板及显示装置
US11908403B2 (en) Driving circuit of light-emitting device, backlight module and display panel
CN108877645A (zh) 像素电路及其驱动方法、显示面板、拼接屏
CN104217680A (zh) 公共电压补偿电路、其补偿方法、阵列基板及显示装置
US20220319432A1 (en) Pixel circuit, method for driving the same, display panel and display device
WO2019061981A1 (zh) 一种显示装置的驱动电路和驱动方法
US20240029676A1 (en) Backlight driving circuit and display device
WO2022120576A1 (zh) 显示基板及显示面板
CN103700331A (zh) 平面显示器及其临界电压感测电路与方法
WO2023236289A1 (zh) 像素电路及显示面板
CN111273495B (zh) 显示模组及其阵列基板的驱动方法、显示装置
WO2021184899A1 (zh) 移位寄存器单元、驱动方法、栅极驱动电路和显示装置
WO2022233083A1 (zh) 像素驱动电路、像素驱动方法及显示装置
US11749199B1 (en) Pixel driving circuit and display device
WO2022016685A1 (zh) 像素驱动电路及其驱动方法、显示面板
WO2024036897A1 (zh) 像素补偿电路及显示面板
US20230386403A1 (en) Pixel driving circuit of a display panel, method for driving a display panel, and display device
WO2023184588A1 (zh) 显示面板及显示装置
US20240046863A1 (en) Light-emitting driving circuit, backlight module and display panel
CN113707093B (zh) 显示像素电路结构及显示面板
US11929022B2 (en) Multiplexing circuitry, multiplexing method, multiplexing module, and display device
WO2023151135A1 (zh) 驱动电路及显示面板

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 17756652

Country of ref document: US

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 22934414

Country of ref document: EP

Kind code of ref document: A1