WO2023184573A1

WO2023184573A1 - Clock gating control circuit and chip test circuit

Info

Publication number: WO2023184573A1
Application number: PCT/CN2022/086522
Authority: WO
Inventors: 王泽坤; 黄现; 管逸
Original assignee: 上海韬润半导体有限公司
Priority date: 2022-03-31
Filing date: 2022-04-13
Publication date: 2023-10-05
Also published as: CN114563694B; CN114563694A

Abstract

A clock gating control circuit (200) and a chip test circuit. The clock gating control circuit (200) is used for controlling clock inputs of a plurality of tested circuit parts of a tested circuit. The clock gating control circuit (200) comprises M decoders (210), a plurality of clock gating circuit blocks (230), a functional logic circuit block (240), which outputs a functional logic signal, and L control modules (220). Each decoder (210) receives and decodes an N-bit binary input, generates an L-bit binary code, and outputs L decoding sub-signals corresponding to the L-bit binary code; each clock gating circuit block (230) is used for controlling the clock input of one or more tested circuit parts; and each control module (220) enables or disables one or more clock gating circuit blocks (230) according to an externally input enable control signal, M decoding sub-signals and the functional logic signal, wherein the M decoding sub-signals are formed by means of each decoder (210) among the M decoders (210) providing one decoding sub-signal, and M, N and L are all positive integers.

Description

Clock gating control circuit and chip test circuit

Technical field

The invention relates to the field of electronic circuits, and in particular to a clock gating control circuit and a chip test circuit.

Background technique

Currently, the test method based on scan chain can be used in chip testability design, which is tested through the test vectors generated by the test vector generation tool. When the scan chain circuit is tested at high speed, too high clock frequency and logic flip rate may cause voltage drop and power consumption problems, which may further lead to test failure.

Clock gating technology is generally used to reduce the toggle rate and power consumption of the test circuit. A clock gating circuit is added to the test circuit to turn off the clock of the sequential logic when some circuits are not working, which can reduce the clock path. And the power consumption caused by timing logic flipping. However, when most of the clock gates are difficult to turn off due to complex control logic, too many clock gates are still open, causing the circuit to still have problems with toggle rate and excessive power consumption. As a result, when most of the clock gates are difficult to open, too many clock gates are still closed, and only a very small part of the logic to be tested in each test vector is tested, resulting in an excessive number of test vectors and resulting in excessive chip testing time. long.

Therefore, it is a problem to be solved that the clock gating is difficult to open and close due to the complicated control logic, which in turn leads to an excessively high test flip rate or too many test vectors. We hope to propose a clock gating control circuit and a circuit containing this circuit. chip test circuit.

Contents of the invention

In view of the above problems, the present invention aims to provide a clock gating control circuit.

One aspect of the present invention is a clock gating control circuit, which is used to control clock inputs of multiple circuit parts under test. The clock gating control circuit may include:

M decoders, each of the M decoders receives N-bit binary input and decodes the received N-bit binary input, generates L-bit binary decoding and outputs an L-bit binary decoding corresponding to L decoding sub-signals of the code;

a plurality of clock gating circuit blocks, each clock gating circuit block of the plurality of clock gating circuit blocks being used to control a clock input of one or more circuit portions under test;

a functional logic circuit block that outputs a functional logic signal; and

L control modules, each of the L control modules enables or disables one or more clock gating circuit blocks according to the externally input enable control signal, M decoding sub-signals and functional logic signals, where , M decoding sub-signals are composed of each decoder in the M decoders providing a decoding sub-signal, and among them, M, N and L are all positive integers.

Optionally, each of the L control modules generates a first control output according to the input M decoding sub-signals, and the enable control signal may include a first instruction, a second instruction, a third instruction and a fourth instruction. There are four types of instructions, and the control module is configured such that: when the enable control signal is the first instruction, the corresponding one or more clock gating circuit blocks are enabled or disabled according to the functional logic signal; when the enable control signal is When the second instruction is given, the corresponding one or more clock gating circuit blocks are enabled or disabled according to the logical OR result of the first control output and the functional logic signal; when the enable control signal is the third instruction, according to the first control output the logical AND result of the function logic signal to enable or disable the corresponding one or more clock gating circuit blocks; and when the enable control signal is the fourth instruction, enable or disable the corresponding clock gating circuit block according to the first control output One or more clock gating circuit blocks.

Optionally, the enable control signal may include a first enable control signal and a second enable control signal, and when the first enable control signal and the second enable control signal are both set to 0, the enable control signal is the A command; when the first enable control signal is set to 1 and the second enable control signal is set to 0, the enable control signal is the second command; when the first enable control signal is set to 0 and the second enable control signal is set to 1 When, the enable control signal is the third instruction; and when the first enable control signal and the second enable control signal are both set to 1, the enable control signal is the fourth instruction.

Optionally, the clock gating control circuit may also include a NOT gate circuit, which is used to perform a logical NOT operation on the second enable control signal before inputting the second enable control signal to the control module, and generate a second control output. , the control module also includes: a first OR gate circuit, which is used to perform a logical OR operation on the M decoding sub-signals to generate a first control output; a first AND gate circuit, which is used to perform a logical OR operation on the first control output and the first Enable a logical AND operation of the control signal to generate a third control output; a second OR gate circuit used to perform a logical OR operation on the first control output and the second control output to generate a fourth control output; the third OR a gate circuit for performing a logical OR operation on the third control output and the functional logic signal to generate a fifth control output; and a second AND gate circuit for performing a logical AND operation on the fourth control output and the fifth control output To generate a sixth control output, the sixth control output is connected to the enable terminal of the corresponding one or more clock gating circuit blocks.

Optionally, the value of M can be 2.

Alternatively, the decoder can use a one-hot decoder, which generates L-bit binary one-hot decoding, and L can be equal to 2 ^N .

Optionally, the value of N can be determined based on the flip rate of the chip test.

Optionally, each decoder can be provided with N-bit binary input by M scan chains corresponding to M decoders one-to-one.

Optionally, M scan chains can be connected to each other in series.

Another aspect of the present invention is a chip test circuit, which may include any of the previous clock gating control circuits.

As above, according to the clock gating control circuit of the present invention, by adding additional control modules on the basis of the original clock gating circuit block and functional logic circuit block, the clock gating control circuit can additionally open or close part of the clock gating circuit. block to alleviate or solve the problem of too many test vectors or too high a flip rate.

Description of drawings

FIG. 1A is a schematic structural diagram showing a scan chain circuit 100 in the related art.

FIG. 1B is a timing diagram showing a scan enable signal and a clock signal input to the scan chain circuit in FIG. 1A .

FIG. 2 is a schematic structural diagram showing a clock gating control circuit 200 according to some embodiments of the present invention.

FIG. 3 is a schematic diagram showing a specific structure 300 of the clock gating control circuit in FIG. 2 according to other embodiments of the present invention.

Detailed ways

Described below are some of the various embodiments of the invention and are intended to provide a basic understanding of the invention. It is not intended to identify key or critical elements of the invention or to limit the scope of the invention.

For brevity and explanatory purposes, the principles of the invention are described herein primarily with reference to exemplary embodiments thereof. However, those skilled in the art will readily recognize that the same principles are equally applicable to and implemented in all types of clock gating control circuits, and that any such changes do not depart from the scope of this patent application. True spirit and scope.

Furthermore, in the following description, reference is made to the accompanying drawings, which illustrate specific exemplary embodiments. Electrical, mechanical, logical, and structural changes may be made in these embodiments without departing from the spirit and scope of the invention. Furthermore, although features of the invention are disclosed in connection with only one of several implementations/embodiments, such features may be combined with other implementations as may be desirable and/or advantageous for any given or identifiable function. / combined with one or more other features of the embodiments. Therefore, the following description is not to be taken in a limiting sense, and the scope of the invention is defined by the appended claims and their equivalents.

Words such as "having" and "comprising" mean that in addition to having units (modules) and steps that are directly and explicitly stated in the description and claims, the technical solution of the present invention does not exclude having units (modules) and steps that are not directly or explicitly stated. The situation of other units (modules) and steps expressed.

FIG. 1A is a schematic structural diagram showing a scan chain circuit 100 in the related art. As shown in FIG. 1A , the existing scan chain circuit 100 includes a plurality of scan flip-flops 110 connected in series through si and so ports. Each scan flip-flop 110 is used to test a plurality of circuit parts 120 of the circuit under test. A portion of the circuit under test 120 . Each scan flip-flop 110 includes a scan enable port se for inputting a scan enable signal (scan_en), a scan input port si for scan loading (scan_in) test vectors, a scan output port so for unloading test vectors, and Port clk used for input clock. When scan_en is 1, the test vector generation module (for example, automatic test vector generation tool ATPG) loads and unloads test vectors for the scan chain circuit through scan_in and scan_out, and when scan_en is 0, each scan flip-flop is loaded and unloaded from The d port captures data of the corresponding circuit part under test 120 to test the circuit part under test 120 . The entire process is controlled by inputting a unified clock from the clock input port clk.

FIG. 1B is a timing diagram showing a scan enable signal input and a clock input input to the scan chain circuit in FIG. 1A . When the scan enable signal input is 1, the scan chain circuit 100 is in a shift mode. At this stage, the test excitation data is input from each scan flip-flop 110 to each circuit part under test through a long series of low-speed clock pulses. 120, and output the tested responses from inside each tested circuit part 120 to each scan flip-flop 110. Due to the low clock frequency at this stage, even if the logic flip rate is high, there will be no voltage drop or power consumption problems. . When the scan enable signal input is 0, the scan chain circuit 100 is in capture mode. At this stage, the logic inside each tested circuit part 120 is tested through a number of full-speed clock pulses (usually 2 to 5). Due to the high clock frequency at this stage, it may lead to an excessively high logic flip rate, resulting in undesirable voltage drops and excessive power consumption.

Clock gating is a technology that reduces the flip rate and power consumption of digital circuits. It can turn off the clock of the sequential logic of some circuits when they are not working, so as to reduce the dynamic power caused by clock paths and sequential logic flips. Consumption. Clock gating technology will also be used in chip testing to only turn on an appropriate proportion of clock gating units to ensure that the number of test vectors generated and the logic flip rate during testing are at a reasonable level. However, when the control logic of clock gating is complex and makes it difficult to turn off most of the clock gating units, too many clock gating units are in the open state, causing the logic flip rate and power consumption in the test circuit to be too high, which may cause the chip to Test failed. Moreover, when the control logic of clock gating is complex and makes it difficult to open most of the clock gating units, too many gated clock units are in a closed state, resulting in only a very small part of the circuit under test being tested in each test vector. This This will cause the number of test vectors to accumulate, resulting in long chip testing time and increased testing costs.

Based on the above problems, the present invention proposes a clock gating control circuit, which is used to control the clock input of multiple tested circuit parts of the tested circuit, thereby optimizing the clock gating control method.

FIG. 2 is a schematic structural diagram showing a clock gating control circuit 200 according to some embodiments of the present invention. As shown in Figure 2, the clock gating control circuit 200 includes M decoders 210 (for simplicity, Figure 2 shows two decoders, but is not limited thereto), L control modules 220, and functional logic circuits. block 240 and a plurality of clock gating circuit blocks 230 . Each decoder 220 receives an N-bit binary input and decodes it to generate an L-bit binary decode, and then the decoder 220 may output L decodes corresponding to the L-bit binary decode through L output pins. Code sub-signal, wherein each pin outputs a decoding sub-signal on a corresponding decoding bit in the L-bit binary decoding. In this way, each pin outputs a decoded sub-signal (ie, a binary "0" or "1"). Then, each decoder 220 inputs a decoding sub-signal output by it to a corresponding control module 230 .

Referring to FIG. 2 , the functional logic circuit block 240 outputs a functional logic signal for subsequent enabling or disabling of each of the plurality of clock gating circuit blocks. Specifically, the functional logic circuit block 240 is an original functional logic circuit block that has been set up by the test circuit itself to enable or disable the clock gating circuit. It generally uses a pair of digital signals with opposite potentials to enable. or disable, for example, a binary digital signal "1" indicates enablement, and a binary digital signal "0" indicates disabling.

Referring to Figure 2, each control module 220 of the L control modules 220 responds to an enable control signal and M decoding sub-signals from an external input (for simplicity, Figure 2 shows 2 decoding sub-signals, but not limited to this) and a functional logic signal to enable or disable one or more clock gating circuit blocks (for simplicity, the figure shows that one control module 220 corresponds to one clock gating circuit block, the same applies below, but is not limited to ), wherein each of the M decoders provides a decoding sub-signal to form M decoding sub-signals. Specifically, as shown in Figure 2, the first end 221 of each control module 230 receives M decoding sub-signals from M decoders 210, and the second end 222 receives an enable control signal from the outside. The third terminal 223 receives the functional logic signal from the functional logic circuit block, and the fourth terminal 224 is the output terminal of the control module 220 . The control module 220 performs a series of logical operation operations based on the signal inputs from the above three input terminals, and outputs the operation results to one or more clock gating circuits through the fourth terminal 224 for controlling the one or more clock gating circuits. The circuit is enabled or disabled.

Referring to FIG. 2 , each clock gating circuit block 230 is used to control the clock input of one or more circuit parts under test (not shown), for example, the enable terminal of the clock gating circuit block 240 inputs a digital Signal "1" indicates that the clock gating circuit block 240 is enabled so that one or more circuit portions under test it controls have a clock input, thereby increasing the number of circuit portions under test by one or more, which makes more Multiple test vectors can be tested, speeding up the testing process; and when the enable terminal of the clock gating circuit block 240 inputs a digital signal "0", it means that the clock gating circuit block 240 is disabled, causing a Or multiple circuit parts under test do not have clock inputs, so the number of circuit parts under test is reduced by one or more, which reduces the flip rate, voltage drop, and power consumption of the entire test circuit.

It can be understood that the above mentioned L, M and N are all positive integers.

In some embodiments, the control module 220 of the present invention can be configured to select what kind of logical operation to perform on the inputs of the first terminal 221 and the third terminal 223 according to the enable control signal input content of the second terminal 222 and display the operation results. It is output through the fourth terminal 224, wherein the first terminal 221 can be configured to generate a first control output from the input M decoding sub-signals. As an example, the enable control signal may have four types of instructions (a first instruction, a second instruction, a third instruction and a fourth instruction), and each control module 220 is configured to enable the enable input at the second terminal 222 When the control signal input is the first instruction, the corresponding one or more clock gating circuit blocks 230 are enabled or disabled according to the functional logic signal (for simplicity, one is shown in the figure); when the enable control signal input is the When two instructions are issued, the corresponding one or more clock gating circuit blocks 230 (for simplicity, one is shown in the figure) are enabled or disabled according to the logical OR result of the first control output and the functional logic signal; when enabling When the control signal input is a third instruction, the corresponding one or more clock gating circuit blocks 230 are enabled or disabled according to the logical AND result of the first control output and the functional logic signal (for simplicity, one is shown in the figure. ); when the enable control signal input is the fourth instruction, the corresponding one or more clock gating circuit blocks 230 are enabled or disabled according to the first control output (for simplicity, one is shown in the figure). However, it is understood that the present invention is not limited thereto, and any number of types of instructions can be configured according to the design situation to cause the first terminal 221 input and the third terminal 223 input in the control module 220 to perform other types of logical operations, and The corresponding one or more clock gating circuit blocks are enabled or disabled through the logical operation result output ("1" or "0").

In some embodiments, the enable control signal includes a first enable control signal and a second enable control signal, and these two signals can be input into the control module 230 through two input pins provided at the second end 222 . The control module 230 can be further configured into the following four modes:

(1) When the first enable control signal and the second enable control signal are both set to 0, the first enable control signal is the first instruction, so that the control module 220 enables or disables the corresponding function according to the functional logic signal. One or more clock gating circuit blocks 230. At this time, the enable input of the clock gating circuit block 230 only comes from the functional logic signal, and the clock gating control mode of the entire test circuit is still controlled by the original functional logic.

(2) When the first enable control signal is set to 1 and the second enable control signal is set to 0, the first enable control signal is the second instruction, so that the control module 220 will generate the M decoding sub-signals input therein A logical OR operation is performed on the first control output and the functional logic signal, and the output of the logical OR operation is used to enable or disable the corresponding one or more clock gating circuit blocks 230 . At this time, when the functional logic input is 1, the corresponding clock gating circuit block 230 is enabled, and even when the functional logic input is 0, due to the existence of the first control output, the corresponding clock gating circuit block 230 is still enabled. is enabled. In this way, when some clock gating circuit blocks 230 are difficult to enable due to the complexity of the functional logic circuit block 240, the L control modules 220 can enable some of the clock gating circuit blocks 230 that are originally disabled, thereby enabling Alleviate or solve the problem of difficulty in enabling some clock gating circuit blocks. It can be understood that the M decoding sub-signals can be composed of a decoding sub-signal of 0 and a decoding sub-signal of 1, and the decoding method can be controlled according to requirements to output two decoding sub-signals in a specific ratio. . Assume that the number of decoding sub-signals that are 1 is x, and the number of decoding sub-signals that are 0 is M-x. Then the decoding method can be reasonably set so that the value of Number of circuit blocks required. For example, if it is only desired to enable a smaller number of clock gating circuit blocks 230 when some clock gating circuit blocks 230 are difficult to enable, the decoding method can be set so that the number of decoded sub-signal 1 in the decoding result is The number is small but the number of decoded sub-signal 0 is large. Through the logical operation of the control module, only a small number of binary 1s are logically ORed with the functional logic signal and the result is output to the use of the clock gating circuit block 230 enable terminal to enable a small number of clock gating circuit blocks. This mode can alleviate or solve the problem that some clock gating circuit blocks are difficult to enable, resulting in excessive test vector accumulation.

(3) When the first enable control signal is set to 0 and the second enable control signal is set to 1, the first enable control signal is the third command, so that the control module 220 will input the M decoding sub-signals and The functional logic signals are logically ANDed, and the output of the logical AND operation is used to enable or disable the corresponding one or more clock gating circuit blocks 230 . At this time, when the functional logic input is 0, the corresponding clock gating circuit block 230 must be disabled, and even when the functional logic input is 1, due to the existence of the first control output, the corresponding clock gating circuit block 230 is still disabled. May be disabled. In this way, when some clock gating circuit blocks 230 are difficult to disable due to the complexity of the functional logic circuit block 240, the L control modules 230 can disable some of the clock gating circuit blocks 230 that are originally enabled, thereby easing the problem. Or solve the problem that some clock gating circuit blocks are difficult to disable. As described above regarding point (2), the decoding method can be set appropriately so that the value of x meets the number of clock gating circuit blocks that need to be enabled or disabled. For example, if you want to disable a larger number of clock gating circuit blocks when some clock gating circuit blocks are difficult to disable, you can set the decoding method so that the number of decoded sub-signals 1 in the decoding result is smaller and the decoding result is smaller. There are a large number of code sub-signal 0s. Through the logical operation of the control module, more binary 0s are logically ANDed with the functional logic signals and the result is output to the enable end of the clock gating circuit block 230 for further disabling. More clock gating circuit blocks. This mode can alleviate or solve the problem that some clock gating circuit blocks are difficult to disable, resulting in excessive test toggle rates and excessive power consumption.

(4) When the first enable control signal and the second enable control signal are both set to 1, the first enable control signal is the fourth instruction, so that the control module 230 generates a signal based on the M decoding sub-signals input therein. A first control output is used to enable or disable the corresponding one or more clock gating circuit blocks 230 . At this time, the enable input of the clock gating circuit block 230 only depends on the first control output of the decoder, and the clock gating control mode of the entire test circuit is completely free from the original functional logic. When the test system has the problem that some clock gating circuit blocks are difficult to enable and other clock gating circuit blocks are difficult to disable, this mode can be used to avoid the original complex functional logic, thereby solving or alleviating the problem at the same time. There are problems such as too many test vectors and too high test flip rate.

It can be understood that the present invention is not limited to the above setting method of setting the enable control signal to 0 or 1, but any digital signal with opposite potential can be used to represent the above four instructions. Moreover, it can be further understood that the present invention is not limited to the above combination method of setting 0 and setting 1, but can also use other combination methods, for example, when the first enable control signal is set to 0 and the second enable control signal is set to 1 , the first enable control signal may also be the above-mentioned second instruction.

In some embodiments, the decoder may use a one-hot decoder and generate an L-bit binary one-hot decoding, and L=2 ^N . Specifically, since the N-bit binary input has 2 ^N possibilities (for example, the two-bit binary input has four possibilities: 00, 01, 10, and 11), the L kinds can be represented by 2 ^N- bit binary one-hot decoding. Possibility, and one-hot decoding can make only one code bit in the decoding result be 1, and the remaining code bits are all 0. For example, when N is 3, the one-hot decoder can encode the 3-bit binary input as shown in Table 1 below:

	3位二进制输入3-bit binary input	2 ³位独热译码 2 ³ -bit one-hot decoding
11	000000	0000000100000001
22	001001	0000001000000010

33	010010	0000010000000100
44	011011	0000100000001000
55	100100	0001000000010000
66	101101	0010000000100000
77	110110	0100000001000000
88	111111	1000000010000000

Table 1: 3-bit input one-hot decoding example

The use of one-hot decoding can make each binary input represented by a binary output including only one 1, thus controlling the number of decoding sub-signals that are 1. When there are many test vector products in the test circuit and some clock gating circuits When a block is difficult to enable, only a small proportion of the clock gating circuit blocks are enabled. In this way, only a small part of the clock gating circuit blocks are enabled each time, which will not cause the test toggle rate and power consumption to suddenly increase a lot.

FIG. 3 is a schematic diagram showing a specific structure 300 of the clock gating control circuit in FIG. 2 according to other embodiments of the present invention. As an example, the control module 220 in FIG. 2 may be, for example, a logic circuit combination of the control module 320 shown in FIG. 3 , and the clock gating control circuit 300 further includes a NOT gate circuit 350 for converting the second Before the enable control signal is input to the control module 320, a logical negation operation is performed on the second enable control signal and a second control output is generated. The control module 320 includes: a first OR gate circuit 321, which is used to perform a logical OR operation on M decoding sub-signals to generate a first control output; a first AND gate circuit 322, which is used to combine the first control output and The input of the first enable control signal performs a logical AND operation to generate a third control output; the second OR gate circuit 323 is used to perform a logical OR operation on the first control output and the second control output to generate a fourth control output. ; The third OR gate circuit 324, which is used to perform a logical OR operation on the input of the third control output and the functional logic signal to generate the fifth control output; the second AND gate circuit 325, which is used to perform a logical OR operation on the fourth control output and the third control output; The five control outputs perform a logical AND operation to generate a sixth control output, and the sixth control output is connected to the enable end of one or more clock gating circuit blocks 330 (one is shown in the figure).

In some embodiments, M preferably takes a value of 2. Moreover, the appropriate value of N can be determined based on the flip rate of the test circuit. In practice, the values of N are generally 4 (corresponding to a flip rate of 12.5%), 5 (corresponding to a flip rate of 7.25%) and 6 (corresponding to a flip rate of 3.125%). Assume that the flip rate requirement of the test circuit is 12.5%. Then you can set a 4-bit binary input. In order to illustrate the specific control process of the structure 300 of Figure 3, the following will be described based on Figure 3, in conjunction with a preferred embodiment in which M is 2, N is 4, and a one-hot decoding method is used.

First, each of the 2 one-hot decoders 310 receives a 4-bit binary input and decodes it, whereby each one-hot decoder 310 produces 2 ⁴ =16 decoding sub-signal. As shown in Figure 3, two one-hot decoders 310 each provide one decoding sub-signal to form two decoding sub-signals that are input to a corresponding control module 320. The two decoding sub-signals are input The control module 320 then enters the first OR gate circuit 321 and performs a logical OR operation to generate a first control output. Since there are 16 control modules and corresponding 16 pairs of decoding sub-signals, according to the nature of the one-hot decoding output (only one of the 16 outputs of each one-hot decoder 310 is 1), the 16 control modules Among the 16 first control outputs, 2 first control outputs are 1, and the remaining first control outputs are all 0.

Then, if both the first enable control signal and the second enable control signal are set to 0 (that is, like the first instruction), no matter whether the first control output is 0 or 1, the third output generated by the first AND gate circuit 322 The control output is always 0, and the second control output generated by the second enable control signal after passing through the inverter 350 is always 1. At this time, if the functional logic signal input is 0, the fifth control output generated by the third OR gate circuit 324 is 0, and the sixth control output generated by the second AND gate circuit 325 is always 0; and if the functional logic signal input is 1, then the fifth control output generated by the third OR gate circuit 324 is 1, and since the second control output is always 1, no matter the first control output is 0 or 1, the fourth control output generated by the second OR gate circuit 323 is 1. The control output is always 1, ultimately resulting in a sixth control output bit 1 generated by the second AND gate circuit 325 . In summary, if the first enable control signal and the second enable control signal are both set to 0, the functional logic signal input clock is consistent with the sixth control output, and the clock gating control method of the entire test circuit is still controlled by the original function. Logic signals to control.

If the first enable control signal is set to 1 and the second enable control signal is set to 0 (that is, like the second instruction), then similar to the above analysis process combined with Figure 3, it can be obtained that each control module in Figure 3 The result of the sixth control output of 320 (that is, the enable terminal input of each clock gating circuit block 330) is equivalent to a logical OR operation between the functional logic circuit block and the first control output. In this way, when the test circuit has a problem that there are too many test vectors and some clock gating circuit blocks 330 are difficult to enable, the 2 first control outputs that are 1 among the 16 first control outputs of the 16 control modules 320 can be compared with The corresponding two functional logic signals perform a logical OR operation and output a sixth control output of 1, thereby enabling two more clock gating circuit blocks 330. In this way, the clock gating circuit 330 with a ratio of 2/16 is enabled to provide clock input to 2/16 of the circuit under test to achieve the toggle rate requirement of 12.5% (2/16). This alleviates the problems of excessive test vector accumulation and long test time due to the difficulty in opening clock gating circuit blocks due to complex functional logic. Furthermore, only 2 clock gating circuit blocks are opened at a time, which does not affect the test circuit. has a huge impact on power consumption.

If the first enable control signal is set to 0 and the second enable control signal is set to 1 (that is, like the third instruction), then similar to the above analysis process combined with Figure 3, it can be obtained that each control module in Figure 3 The result of the sixth control output of 320 (that is, the enable terminal input of each clock gating circuit block 330) is equivalent to a logical AND operation between the functional logic circuit block and the first control output. In this way, when the test circuit has a problem that the toggle rate is too high and some clock gating circuit blocks 330 are difficult to disable, the 14 first control outputs of 0 among the 16 first control outputs of the 16 control modules 320 can be corresponding to The 14 functional logic signals perform a logical AND operation, and the output is a sixth control output of 0, thereby disabling 14 clock gating circuit blocks 320 . In this way, the clock input of one or more circuit parts under test corresponding to the 14 clock gating circuit blocks 320 can be stopped, which can solve problems such as excessive toggle rate and excessive power consumption, thereby increasing the success rate of the test.

If both the first enable control signal and the second enable control signal are set to 1 (that is, like the fourth instruction), then similar to the above analysis process combined with Figure 3, it can be obtained that each control module 320 in Figure 3 The result of the sixth control output (ie, the enable terminal input of each clock gating circuit block 330) is only consistent with the first control output. In this way, when the test circuit has the problems of too high toggle rate and too many test vectors (and there are also problems that some clock gating circuit blocks are difficult to enable and disable), the test circuit can completely avoid the original functional logic control. Complexity issues, generate test vectors and perform testing more efficiently.

In addition, for the problem of loss of clock gating control logic coverage caused by the first enable control signal being set to 1 (such as during the second and fourth instructions), the first enable control signal can be set to 1 after the test vector generation is completed. The control signal and the second enable control signal are both set to 0 (ie, like the first instruction), and a small amount of test vectors are additionally loaded to make up for the lost coverage.

In the above embodiment using two one-hot decoders, any two clock gating circuit blocks can be opened for testing by independently controlling the two one-hot decoders. In this way, any two clock gating circuit blocks can be traversed For all combinations of circuits, the solution of the present invention will not cause coverage loss between any two clock gating logics. Based on this, it can be understood that in embodiments using other numbers of decoders with M>2, it can be guaranteed that coverage loss between any number of clock gating logics will not occur (for example, using 3 decoders) The coder is tested by turning on any three clock gating circuit blocks to ensure that there will be no loss of coverage between any three clock gating logic).

In some embodiments, each decoder is provided with N-bit binary input by M scan chains corresponding one-to-one to the M decoders. Specifically, similar to the scan chain circuit described with reference to FIG. 1A , each scan chain circuit may be composed of N scan flip-flops connected in series. Each scan chain circuit outputs N-bit binary test vectors to a corresponding decoder 210 through its N scan flip-flops. Preferably, the M scan chains are connected to each other in series.

The present invention also includes a chip test circuit using a clock gating control circuit as in any of the various embodiments described above. For example, in a scan chain-based chip test circuit, the scan chain can be divided into M scan sub-chains (each including N scan flip-flops) and the M N-bit binary outputs are output to the above-mentioned clock gating control circuit respectively. , and then control the clock input of each circuit department under test in the chip test circuit. Of course, M scan chains (each including N scan flip-flops) may also be connected in series, and each scan chain may be connected to each other in series.

The above mainly describes the clock gating control circuit and the corresponding chip test circuit of the present invention. Although only some specific embodiments of the invention have been described, those of ordinary skill in the art will understand that the invention can be implemented in many other forms without departing from the spirit and scope thereof. Accordingly, the examples and embodiments shown are to be regarded as illustrative and not restrictive, and the present invention may cover various modifications without departing from the spirit and scope of the invention as defined by the appended claims. with replacement.

Claims

A clock gating control circuit used to control clock inputs of multiple circuit parts under test, characterized in that the clock gating control circuit includes:

M decoders, each of the M decoders receives N-bit binary input and decodes the received N-bit binary input, generates L-bit binary decoding and outputs corresponding to the L decoding sub-signals of L-bit binary decoding;

a plurality of clock gating circuit blocks, each clock gating circuit block of the plurality of clock gating circuit blocks being configured to control a clock input to one or more of the circuit portions under test;

a functional logic circuit block that outputs a functional logic signal; and

L control modules, each of the L control modules enables or disables one or more according to the externally input enable control signal, the M decoding sub-signals and the functional logic signal. of the clock gating circuit blocks, wherein the M decoding sub-signals are composed of each of the M decoders providing one of the decoding sub-signals, and wherein, M , N and L are all positive integers.
The clock gating control circuit according to claim 1, characterized in that each of the L control modules generates a first control output according to the input M decoding sub-signals, and the enable The control signal includes four types: first instruction, second instruction, third instruction and fourth instruction, and the control module is configured such that:

When the enable control signal is the first instruction, enable or disable the corresponding one or more clock gating circuit blocks according to the functional logic signal;

When the enable control signal is the second instruction, the corresponding one or more clock gating circuit blocks are enabled or disabled according to the logical OR result of the first control output and the functional logic signal. ;

When the enable control signal is the third instruction, the corresponding one or more clock gating circuit blocks are enabled or disabled according to the logical AND result of the first control output and the functional logic signal. ;as well as

When the enable control signal is the fourth instruction, the corresponding one or more clock gating circuit blocks are enabled or disabled according to the first control output.
The clock gating control circuit according to claim 2, wherein the enable control signal includes a first enable control signal and a second enable control signal, and:

When the first enable control signal and the second enable control signal are both set to 0, the enable control signal is the first instruction;

When the first enable control signal is set to 1 and the second enable control signal is set to 0, the enable control signal is a second instruction;

When the first enable control signal is set to 0 and the second enable control signal is set to 1, the enable control signal is a third instruction; and

When the first enable control signal and the second enable control signal are both set to 1, the enable control signal is a fourth instruction.
The clock gating control circuit according to claim 3, characterized in that, the clock gating control circuit further includes a NOT gate circuit, which is used to control all the second enable control signals before inputting the second enable control signal to the control module. The second enable control signal performs a logical negation operation and generates a second control output. The control module also includes:

A first OR gate circuit, which is used to perform a logical OR operation on the M decoding sub-signals to generate a first control output;

A first AND gate circuit configured to perform a logical AND operation on the first control output and the first enable control signal to generate a third control output;

a second OR gate circuit configured to perform a logical OR operation on the first control output and the second control output to generate a fourth control output;

a third OR gate circuit for performing a logical OR operation on the third control output and the functional logic signal to generate a fifth control output; and

A second AND gate circuit configured to perform a logical AND operation on the fourth control output and the fifth control output to generate a sixth control output, and the sixth control output is connected to the corresponding one or more of the The enable side of the clock gating circuit block.
The clock gating control circuit according to claim 4, wherein the value of M is 2.
The clock gating control circuit according to any one of claims 1 to 5, characterized in that the decoder adopts a one-hot decoder, which generates L-bit binary one-hot decoding, and L Equal to 2 N .
The clock gating control circuit according to any one of claims 1 to 5, characterized in that the value of N is determined according to the flip rate of chip testing.
The clock gating control circuit according to any one of claims 1-5, characterized in that, each of the decoders is provided with M scan chains corresponding to the M decoders. The N-bit binary input.
The clock gating control circuit according to claim 8, wherein the M scan chains are connected to each other in series.
A chip test circuit, characterized by comprising the clock gating control circuit according to any one of claims 1-9.