CN114563694A - Clock gating control circuit and chip test circuit - Google Patents

Clock gating control circuit and chip test circuit Download PDF

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Publication number
CN114563694A
CN114563694A CN202210332010.XA CN202210332010A CN114563694A CN 114563694 A CN114563694 A CN 114563694A CN 202210332010 A CN202210332010 A CN 202210332010A CN 114563694 A CN114563694 A CN 114563694A
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circuit
control
clock gating
control signal
clock
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CN114563694B (en
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王泽坤
黄现
管逸
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Shanghai Taorun Semiconductor Co ltd
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Shanghai Taorun Semiconductor Co ltd
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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Tests Of Electronic Circuits (AREA)

Abstract

The invention relates to a clock gating control circuit for controlling the clock input of a plurality of circuit-under-test parts of a circuit-under-test. The circuit includes M decoders, a plurality of clock gating circuit blocks, a functional logic circuit block outputting functional logic signals, and L control modules. Each decoder receives and decodes the N-bit binary input, generates L-bit binary decoding and outputs L decoding sub-signals corresponding to the L-bit binary decoding; each clock gating circuit block is used for controlling the clock input of one or more tested circuit parts; each control module enables or disables one or more clock-gated circuit blocks according to an externally input enable control signal, M decode sub-signals, and a functional logic signal, wherein the M decode sub-signals are comprised of a decode sub-signal provided by each of M decoders, and wherein M, N and L are positive integers. According to the invention, a chip test circuit can also be provided.

Description

Clock gating control circuit and chip test circuit
Technical Field
The invention relates to the field of electronic circuits, in particular to a clock gating control circuit and a chip test circuit.
Background
Currently, a Scan Chain (Scan Chain) based test method can be used in chip testability design, which performs a test by using test vectors generated by a test vector generation tool. When the scan chain circuit is used for high-speed test, too high clock frequency and logic inversion rate may cause voltage drop and power consumption problems, and further may cause test failure.
Generally, a Clock Gating (Clock Gating) technology is adopted to reduce the turnover rate and power consumption of a test circuit, and a Clock Gating circuit is added into the test circuit to turn off the Clock of sequential logic when part of circuits do not work, so that the power consumption caused by the turnover of the Clock path and the sequential logic can be reduced. However, when most clock gating is difficult to close due to the complex control logic, the excessive clock gating is still in an open state, which causes the problem that the circuit still has a high slew rate and high power consumption, and when most clock gating is difficult to open due to the complex control logic, the excessive clock gating is still in a closed state, only a few parts of logic to be tested in each test vector are tested, which causes the number of test vectors to be large, thereby causing the test time of the chip to be too long.
Therefore, it is desirable to provide a clock gating control circuit and a chip test circuit including the same, which solve the problem that the clock gating is difficult to open and close due to the complicated control logic, and thus the test flip-over rate is too high or the test vector product is too large.
Disclosure of Invention
In view of the above, the present invention aims to provide a clock gating control circuit.
A clock gating control circuit of an aspect of the invention for controlling clock inputs of a plurality of circuit-under-test portions of a circuit-under-test may comprise:
each decoder of the M decoders receives and decodes the N-bit binary input to generate L-bit binary decoding and outputs L decoding sub-signals corresponding to the L-bit binary decoding;
a plurality of clock-gated circuit blocks, each clock-gated circuit block of the plurality of clock-gated circuit blocks for controlling a clock input of one or more circuit portions under test;
a functional logic circuit block outputting a functional logic signal; and
and each control module in the L control modules enables or disables one or more clock gating circuit blocks according to an externally input enabling control signal, M decoding sub-signals and a functional logic signal, wherein the M decoding sub-signals are formed by providing one decoding sub-signal for each decoder in the M decoders, and wherein M, N and L are positive integers.
Optionally, each of the L control modules generates a first control output according to the M decoded sub-signals, and the enable control signal may include four types of a first instruction, a second instruction, a third instruction, and a fourth instruction, and the control module is configured such that: enabling or disabling the corresponding one or more clock gating circuit blocks according to the functional logic signal when the enable control signal is the first instruction; enabling or disabling the corresponding one or more clock gating circuit blocks according to a logical or result of the first control output and the functional logic signal when the enable control signal is the second instruction; enabling or disabling the corresponding one or more clock gating circuit blocks according to the logical AND result of the first control output and the functional logic signal when the enable control signal is the third instruction; and enabling or disabling the corresponding one or more clock gating circuit blocks according to the first control output when the enable control signal is the fourth instruction.
Alternatively, the enable control signal may include a first enable control signal and a second enable control signal, and the enable control signal is the first instruction when both the first enable control signal and the second enable control signal are set to 0; when the first enable control signal is set to be 1 and the second enable control signal is set to be 0, enabling the control signal to be a second instruction; when the first enable control signal is set to 0 and the second enable control signal is set to 1, enabling the control signal to be a third instruction; and when the first enable control signal and the second enable control signal are both set to 1, enabling the control signal to be a fourth instruction.
Optionally, the clock gating control circuit may further include a not circuit for logically negating the second enable control signal before the second enable control signal is input to the control module and generating the second control output, and the control module further includes: a first OR gate for logically OR-ing the M decoded sub-signals to generate a first control output; a first AND circuit for logically ANDing the first control output and the first enable control signal to generate a third control output; a second OR gate for logically OR-ing the first control output and the second control output to produce a fourth control output; a third OR gate for logically OR' ing the third control output and the functional logic signal to produce a fifth control output; and a second and circuit for logically anding the fourth control output and the fifth control output to produce a sixth control output, the sixth control output connected to the enable terminals of the respective one or more clock-gated circuit blocks.
Alternatively, M may take the value 2.
Alternatively, the decoder may employ a one-hot decoder that generates L-bit binary one-hot decoding, and L may be equal to 2N。
Optionally, the value of N may be determined according to the flip rate of the chip test.
Alternatively, an N-bit binary input may be provided for each decoder by M scan chains in one-to-one correspondence with M decoders.
Alternatively, the M scan chains may be connected in series with each other.
A chip test circuit according to another aspect of the invention may comprise a clock gating control circuit as described in any of the preceding.
As described above, according to the clock gating control circuit of the present invention, by adding an additional control module on the basis of the original clock gating circuit block and the functional logic circuit block, the clock gating control circuit can additionally open or close part of the clock gating circuit block, so as to alleviate or solve the problems of large test vector product or too high turnover rate.
Drawings
Fig. 1A is a schematic diagram showing the structure of a scan chain circuit 100 in the prior art.
Fig. 1B is a timing diagram showing a scan enable signal and a clock signal input to the scan chain circuit in fig. 1A.
Fig. 2 is a block diagram representation of a clock gating control circuit 200 according to some embodiments of the inventions.
Fig. 3 is a schematic diagram illustrating one particular configuration 300 of the clock gating control circuit of fig. 2 according to further embodiments of the present invention.
Detailed Description
The following description is of some of the several embodiments of the invention and is intended to provide a basic understanding of the invention. It is not intended to identify key or critical elements of the invention or to delineate the scope of the invention.
For the purposes of brevity and explanation, the principles of the present invention are described herein with reference primarily to exemplary embodiments thereof. However, those skilled in the art will readily recognize that the same principles are equally applicable to all types of clock gating control circuits and that these same principles may be implemented therein, as well as any such variations, without departing from the true spirit and scope of the present patent application.
Moreover, in the following description, reference is made to the accompanying drawings that illustrate certain exemplary embodiments. Electrical, mechanical, logical, and structural changes may be made to these embodiments without departing from the spirit and scope of the invention. In addition, while a feature of the invention may have been disclosed with respect to only one of several implementations/embodiments, such feature may be combined with one or more other features of the other implementations/embodiments as may be desired and/or advantageous for any given or identified function. The following description is, therefore, not to be taken in a limiting sense, and the scope of the present invention is defined by the appended claims and their equivalents.
Terms such as "comprising" and "comprises" mean that, in addition to having elements (modules) and steps that are directly and explicitly stated in the description and claims, the solution of the invention does not exclude the presence of other elements (modules) and steps that are not directly or explicitly stated.
Fig. 1A is a schematic diagram showing the structure of a scan chain circuit 100 in the prior art. As shown in FIG. 1A, the prior art scan chain circuit 100 includes a plurality of scan flip-flops 110 connected in series through si and so ports, each scan flip-flop 110 for testing one circuit portion 120 of a plurality of circuit portions 120 under test of the circuit under test. Each scan flip-flop 110 includes a scan enable port se for inputting a scan enable signal (scan _ en), a scan input port si for scan loading (scan _ in) a test vector, a scan output port so for unloading the test vector, and a port clk for inputting a clock. When scan _ en is 1, a test vector generation module (e.g., an automatic test vector generation tool ATPG) loads and unloads test vectors to the scan chain circuit through scan _ in and scan _ out, and when scan _ en is 0, each scan flip-flop captures data of the corresponding circuit portion 120 under test from the d-port to test the circuit portion 120 under test. The whole process is controlled by inputting a unified clock from the clock input port clk for timing.
Fig. 1B is a timing diagram showing a scan enable signal input and a clock input to the scan chain circuit in fig. 1A. When the scan enable signal input is 1, scan chain circuit 100 is in shift mode, and at this stage, test stimulus data is input from each scan flip-flop 110 into each circuit part 120 under test by a long series of low-speed clock pulses, and a response obtained by the test is output from each circuit part 120 under test to each scan flip-flop 110, and at this stage, due to the low clock frequency, no voltage drop or power consumption problem occurs even if the logic inversion rate is high. When the scan enable signal input is 0, the scan chain circuit 100 is in capture mode, at which stage the logic inside each circuit part 120 under test is tested by several full speed clock pulses (typically 2 to 5), which may result in too high a logic flip rate due to the high clock frequency, thereby causing undesirable voltage drop and too high power consumption.
Clock gating is a technology for reducing the turnover rate and power consumption of a digital circuit, and can turn off clocks of sequential logic of a part of circuits when the part of circuits do not work so as to reduce dynamic power consumption caused by clock paths and the turnover of the sequential logic. The clock gating technology is also used in the chip test, so that only the clock gating units with proper proportion are opened, and the quantity of the generated test vectors and the logic turnover rate during the test are ensured to be at a reasonable level. However, when the control logic of clock gating is relatively complex, which causes most clock gating units to be difficult to close, too many clock gating units are in an open state, which causes the logic in the test circuit to have too high flip rate and power consumption, which may cause the chip test to fail. Moreover, when the control logic of clock gating is complex and most clock gating units are difficult to open, too many clock gating units are in a closed state, so that only few tested circuit parts in each test vector are tested, and the test vector number is large, so that the test time of a chip is too long, and the test cost is increased.
Based on the above problems, the present invention provides a clock gating control circuit for controlling the clock input of multiple tested circuit portions of a tested circuit, thereby optimizing the control manner of clock gating.
Fig. 2 is a block diagram illustrating a clock gating control circuit 200 according to some embodiments of the invention. As shown in FIG. 2, the clock gating control circuit 200 includes M decoders 210 (for simplicity, FIG. 2 shows 2 decoders, but is not limited to), L control modules 220, a functional logic block 240, and a plurality of clock gating circuit blocks 230. Each decoder 220 receives and decodes the N-bit binary input to generate an L-bit binary decode, and then the decoder 220 may output L decoded sub-signals corresponding to the L-bit binary decode through L output pins, where each pin outputs a decoded sub-signal on a corresponding decoded bit in the L-bit binary decode. Thus, each pin outputs a decoded sub-signal (i.e., a binary "0" or "1"). Each decoder 220 then inputs a decoded sub-signal of its output to a corresponding one of the control modules 230.
Referring to fig. 2, functional logic circuit block 240 outputs functional logic signals for subsequent enabling or disabling of each of the plurality of clock-gated circuit blocks. In particular, functional logic block 240 is an original functional logic block that the test circuit itself has set to enable or disable the clock gating circuit, and is typically enabled or disabled using a pair of oppositely-charged digital signals, e.g., a binary digital signal "1" indicates enable and a binary digital signal "0" indicates disable.
Referring to fig. 2, each control module 220 of the L control modules 220 enables or disables one or more clock-gated circuit blocks (for simplicity, one control module 220 is shown for one clock-gated circuit block, the same holds true, but is not limited thereto), based on an enable control signal from an external input, M decoding sub-signals (for simplicity, fig. 2 shows 2 decoding sub-signals, but is not limited thereto), and one functional logic signal, wherein the M decoding sub-signals are composed by providing one decoding sub-signal from each of the M decoders. Specifically, as shown in fig. 2, a first terminal 221 of each control module 230 receives M decoded sub-signals from M decoders 210, a second terminal 222 receives an enable control signal from the outside, a third terminal 223 receives a functional logic signal from a functional logic circuit block, and a fourth terminal 224 is an output terminal of the control module 220. The control module 220 performs a series of logical operations according to the signal input from the above 3 input terminals, and outputs the operation result to one or more clock gating circuits through the fourth terminal 224 for enabling or disabling the one or more clock gating circuits.
Referring to fig. 2, each clock gating circuit block 230 is used to control the clock input of one or more circuit portions under test (not shown) of the circuit under test (e.g., an enable input digital signal "1" of the clock gating circuit block 240 indicates that the clock gating circuit block 240 is enabled such that the one or more circuit portions under test it controls have a clock input, thereby increasing the number of circuit portions under test by one or more, which enables more test vectors to be tested, speeding up the testing process; when the enable terminal of the clock gating circuit block 240 inputs a digital signal "0", it indicates that the clock gating circuit block 240 is disabled, so that one or more circuit parts under test controlled by the clock gating circuit block 240 do not have a clock input, thereby reducing the number of circuit parts under test by one or more, which results in a reduction in the slew rate and voltage drop, and power consumption of the whole test circuit.
It is understood that both L, M and N mentioned above are positive integers.
In some embodiments, the control module 220 of the present invention may be configured to select what kind of logic operation is performed on the inputs of the first terminal 221 and the third terminal 223 according to the input content of the enable control signal of the second terminal 222 and output the operation result through the fourth terminal 224, wherein the first terminal 221 may be configured to generate the first control output by the M decoded sub-signals inputted thereto. As an example, the enable control signal may have four types of instructions (a first instruction, a second instruction, a third instruction, and a fourth instruction), and each control module 220 is configured such that the corresponding one or more clock gating circuit blocks 230 (1 is illustrated for simplicity) are enabled or disabled according to the functional logic signal when the enable control signal input at the second terminal 222 is the first instruction; when the enable control signal input is the second instruction, enabling or disabling the corresponding one or more clock gating circuit blocks 230 (1 shown for simplicity) according to the logical or result of the first control output and the functional logic signal; when the enable control signal input is the third instruction, enabling or disabling the corresponding one or more clock gating circuit blocks 230 (1 shown for simplicity) according to the logical and result of the first control output and the functional logic signal; when the enable control signal input is the fourth instruction, the corresponding one or more clock gating circuit blocks 230 (1 shown for simplicity) are enabled or disabled according to the first control output. However, it is to be understood that the present invention is not limited thereto, and any number of types of instructions may be configured according to design conditions to cause the first terminal 221 input and the third terminal 223 input in the control module 220 to perform other types of logical operations, and to enable or disable the corresponding one or more clock-gated circuit blocks through the logical operation result output ("1" or "0").
In some embodiments, the enable control signal includes a first enable control signal and a second enable control signal, which may be input into the control module 230 through 2 input pins provided at the second end 222. The control module 230 may be further configured in four modes:
(1) when both the first enable control signal and the second enable control signal are set to 0, the first enable control signal is made to be a first instruction, thereby causing the control module 220 to enable or disable the corresponding one or more clock gating circuit blocks 230 according to the functional logic signal. At this time, the enable input of the clock gating circuit block 230 is only derived from the functional logic signal, and the clock gating control mode of the whole test circuit is still controlled by the original functional logic.
(2) When the first enable control signal is set to 1 and the second enable control signal is set to 0, the first enable control signal is a second instruction, so that the control module 220 logically or-operates the first control output and the functional logic signal generated by the M decoded sub-signals input thereto, and enables or disables the corresponding one or more clock gating circuit blocks 230 using the output of the logical or-operation. At this time, when the functional logic input is 1, the corresponding clock gating circuit block 230 is enabled, and even when the functional logic input is 0, the corresponding clock gating circuit block may be enabled due to the presence of the first control output. In this way, when some clock gating circuit blocks 230 are difficult to enable due to the complexity of the functional logic circuit block 240, the L control modules 220 may enable a portion of the clock gating circuit blocks 230 that are originally in the disabled state, thereby alleviating or solving the problem that some clock gating circuit blocks are difficult to enable. It is understood that the M decoding sub-signals may be composed of a decoding sub-signal of 0 and a decoding sub-signal of 1, and the decoding manner may be controlled according to requirements to output two decoding sub-signals in a specific ratio. If the number of the decoding sub-signals which is 1 is x, and the number of the decoding sub-signals which is 0 is M-x, the decoding mode can be reasonably set, so that the value of x meets the requirement of the number of clock gating circuit blocks which need to be enabled or disabled. For example, if it is desired to enable a smaller number of clock gating circuit blocks 230 when some clock gating circuit blocks 230 are difficult to be enabled, a decoding manner may be set such that the number of decoded sub-signals 1 is smaller and the number of decoded sub-signals 0 is larger, and only a small number of binary 1 s and functional logic signals are logically or-ed by the logic operation of the control module and the result is output to the enable terminal of the clock gating circuit block 230, so as to enable a small number of clock gating circuit blocks again. This mode may alleviate or solve the problem that some clock-gated circuit blocks are difficult to enable, resulting in many test vector products.
(3) When the first enable control signal is asserted to 0 and the second enable control signal is asserted to 1, the first enable control signal is a third instruction, such that the control module 220 logically and-operates the M decoded sub-signals and the functional logic signals input thereto, and enables or disables the corresponding one or more clock gating circuit blocks 230 using the output of the logical and-operation. At this time, when the functional logic input is 0, the corresponding clock gating circuit block 230 must be disabled, and even when the functional logic input is 1, the corresponding clock gating circuit block 230 may be disabled due to the presence of the first control output. As such, when some clock gating circuit blocks 230 are difficult to disable due to the complexity of the functional logic circuit block 240, the L control modules 230 may disable a portion of the clock gating circuit blocks 230 that are originally in the enabled state, thereby alleviating or solving the problem that some clock gating circuit blocks are difficult to disable. As described above with respect to point (2), the decoding scheme can be set appropriately so that the value of x satisfies the requirement of the number of clock-gated circuit blocks that need to be enabled or disabled. For example, if it is desired to disable a larger number of clock gating circuit blocks when some clock gating circuit blocks are difficult to be disabled, the decoding method may be set such that the number of decoded sub-signals 1 is smaller and the number of decoded sub-signals 0 is larger, and by controlling the logic operation of the module, more binary 0 and functional logic signals are logically anded and the result is output to the enable terminal of the clock gating circuit block 230, so as to disable more clock gating circuit blocks. This mode may alleviate or solve the problem that some clock-gated circuit blocks are difficult to disable, resulting in too high a test flip rate, too much power consumption, etc.
(4) When both the first enable control signal and the second enable control signal are set to 1, the first enable control signal is a fourth instruction, so that the control module 230 enables or disables the corresponding one or more clock gating circuit blocks 230 according to the first control output generated by the M decoded sub-signals input thereto. At this time, the enable input of the clock gating circuit block 230 depends only on the first control output of the decoder, and the clock gating control mode of the whole test circuit is completely free from the original functional logic. When the test system has the problem that some clock gating circuit blocks are difficult to enable and other clock gating circuit blocks are difficult to disable at the same time, the original complex functional logic can be avoided through the mode, and therefore the problems of large test vector product and high test turnover rate existing at the same time are solved or relieved.
It is to be understood that the present invention is not limited to the above setting of set 0 or set 1 of the enable control signal, but any digital signal with opposite potentials can be used to represent the above 4 instructions. It is further understood that the present invention is not limited to the above-mentioned combination of 0-to-1, but other combinations may be used, for example, when the first enable control signal is set to 0 and the second enable control signal is set to 1, the first enable control signal may be the second command.
In some embodiments, the decoder may be a one-hot decoder and generate L-bit binary one-hot decoding, and L =2N. In particular, since the N-bit binary input has 2NThe number of possibilities (e.g., four possibilities of 00, 01, 10, 11 for a two-bit binary input), may be 2NBit binary one-hot decoding represents the L possibilities, and one-hot decoding enablesAnd obtaining that only one code bit in the decoding result is 1 and the other code bits are 0. For example, when N is 3, the one-hot decoder may encode a 3-bit binary input as shown in table 1 below:
3 bit binary input 23Bit-only-hot decoding
1 000 00000001
2 001 00000010
3 010 00000100
4 011 00001000
5 100 00010000
6 101 00100000
7 110 01000000
8 111 10000000
Table 1: 3-bit input one-hot decoding example
The use of one-hot decoding enables each binary input to be represented by a binary output comprising only one 1, thereby controlling the number of decoded sub-signals of 1, and enabling only a fraction of the clock-gated circuit blocks to be enabled when there are situations in the test circuit where the test vector product is large and some clock-gated circuit blocks are difficult to enable. In this way, only a small gate clock gating circuit block is enabled at a time, without causing the test slew rate and power consumption to increase dramatically.
Fig. 3 is a diagram illustrating a specific architecture 300 of the clock gating control circuit of fig. 2 according to further embodiments of the present invention. As an example, the control module 220 in fig. 2 may be, for example, a logic circuit combination of the control module 320 shown in fig. 3, and the clock gating control circuit 300 further includes a not gate circuit 350 for logically negating the second enable control signal before the second enable control signal is input to the control module 320 and generating the second control output. The control module 320 includes: a first or gate circuit 321 for logically or-ing the M decoded sub-signals to generate a first control output; a first and circuit 322 for logically and-ing the first control output and the input of the first enable control signal to generate a third control output; a second or gate circuit 323 for logically or-ing the first control output and the second control output to generate a fourth control output; a third OR gate 324 for logically ORing the third control output and the inputs of the functional logic signal to produce a fifth control output; a second and circuit 325 for logically anding the fourth and fifth control outputs to produce sixth control outputs connected to the enable terminals of the respective one or more clock gating circuit blocks 330 (shown as 1).
In some embodiments, M preferably takes the value 2. And, the appropriate value of N can be determined according to the slew rate to the test circuit. In practice, the values of N are generally 4 (corresponding to a slew rate of 12.5%), 5 (corresponding to a slew rate of 7.25%) and 6 (corresponding to a slew rate of 3.125%), and assuming that the slew rate requirement of the test circuit is 12.5%, a 4-bit binary input may be set. To illustrate the specific control flow of the structure 300 of fig. 3, a preferred embodiment in which M is 2 and N is 4 and a one-hot decoding scheme is employed will be described below with respect to fig. 3.
First, each one-hot decoder 310 of the 2 one-hot decoders 310 receives and decodes a 4-bit binary input, whereby each one-hot decoder 310 generates 24=16 decoded sub-signals. As shown in fig. 3, each of the 2 unique heat decoders 310 provides 1 decoding sub-signal to form 2 decoding sub-signals inputted to a corresponding one of the control modules 320, and the 2 decoding sub-signals are inputted to the control module 320 and then inputted to the first or gate circuit 321 to perform a logical or operation, thereby generating a first control output. Since there are 16 control modules and corresponding 16 pairs of decoding sub-signals, there are 2 first control outputs of the 16 control modules that are 1, and the remaining first control outputs are all 0, according to the nature of the one-hot decoding outputs (only one of the 16 outputs of each one-hot decoder 310 is 1).
Then, if both the first enable control signal and the second enable control signal are set to 0 (i.e., as in the first command), the third control output generated by the first and circuit 322 is always 0 and the second control output generated by the second enable control signal after passing through the not gate 350 is always 1 regardless of whether the first control output is 0 or 1. At this time, if the functional logic signal input is 0, the fifth control output generated by the third or gate circuit 324 is 0, and the sixth control output generated by the second and gate circuit 325 is always 0; if the functional logic signal input is 1, the fifth control output generated by the third or gate circuit 324 is 1, and since the second control output is always 1, the fourth control output generated by the second or gate circuit 323 is always 1 regardless of whether the first control output is 0 or 1, which finally results in the sixth control output bit 1 generated by the second and gate circuit 325. In summary, if the first enable control signal and the second enable control signal are both set to 0, the functional logic signal input clock is consistent with the sixth control output, and the clock gating control mode of the whole test circuit is still controlled by the original functional logic signal.
If the first enable control signal is asserted to 1 and the second enable control signal is asserted to 0 (i.e., as a second command), similar to the analysis process described above in conjunction with fig. 3, it can be found that the result of the sixth control output (i.e., the enable input of each clock gating circuit block 330) of each control module 320 in fig. 3 is equivalent to the functional logic circuit block logically or-ing the first control output. Thus, when the test circuit has a problem that the number of test vector products is large and some clock gating circuit blocks 330 are difficult to enable, the 2 first control outputs of the 16 control modules 320 are 1, and can perform logic or operation with the corresponding two functional logic signals, and the sixth control output is 1, so that the 2 clock gating circuit blocks 330 are enabled again. Thus, clock gating circuit 330, which is scaled 2/16, is enabled to provide a clock input for the circuit under test 2/16 to achieve a 12.5% (2/16) slew rate requirement. The problems of large test vector product and overlong test time caused by the fact that the clock gating circuit blocks are difficult to open due to complex functional logic are solved, and the power consumption of the test circuit is not greatly influenced by opening only 2 clock gating circuit blocks each time.
If the first enable control signal is asserted to 0 and the second enable control signal is asserted to 1 (i.e., as a third command), similar to the analysis process described above in conjunction with fig. 3, it can be found that the result of the sixth control output (i.e., the enable input of each clock gating circuit block 330) of each control module 320 in fig. 3 is equivalent to the logic and operation of the functional logic circuit block and the first control output. In this way, when the test circuit has a problem that the flip rate is too high and some clock gating circuit blocks 330 are difficult to disable, the 14 first control outputs of the 16 control modules 320 that are 0 can be logically and-operated with the corresponding 14 functional logic signals, and the sixth control output that is 0 is output, so that the 14 clock gating circuit blocks 320 are disabled again. In this way, the clock input of one or more circuit parts under test corresponding to the 14 clock gating circuit blocks 320 can be stopped, which can solve the problems of too high turnover rate, too large power consumption, and the like, thereby increasing the success rate of the test.
If both the first enable control signal and the second enable control signal are set to 1 (i.e., as in the fourth instruction), then similar to the analysis flow described above in connection with fig. 3, it can be concluded that the result of the sixth control output of each control module 320 in fig. 3 (i.e., the enable input of each clock gating circuit block 330) only coincides with the first control output. Therefore, when the test circuit has the problems of too high turnover rate and more test vector products (the problems of difficult enabling and difficult disabling of some clock gating circuit blocks) at the same time, the test circuit can completely avoid the complexity problem of the original functional logic control, and more efficiently generates and tests the test vectors.
In addition, for the problem of coverage loss of the clock gating control logic caused by setting the first enable control signal to be 1 (such as in the case of the second instruction and the fourth instruction), after the test vector generation is completed, the first enable control signal and the second enable control signal are both set to be 0 (i.e. such as the first instruction), and a small number of test vectors are loaded again to make up for the lost coverage.
In the above embodiment adopting 2 unique-heat decoders, any 2 clock gating circuit blocks can be opened for testing by independently controlling two unique-heat decoders, so that all combinations of any two clock gating circuits can be traversed, and the scheme of the invention does not cause the loss of coverage rate between any 2 clock gating logics. Accordingly, it will be appreciated that embodiments employing other numbers of decoders with M > 2 may ensure that no loss of coverage between any number of clock gating logic is caused (e.g., 3 decoders may be employed to open any 3 clock gating circuit blocks for testing to ensure that no loss of coverage between any 3 clock gating logic is caused).
In some embodiments, an N-bit binary input is provided for each decoder by M scan chains in one-to-one correspondence with M decoders. Specifically, each scan chain circuit may be composed of N scan flip-flops connected in series, similar to the scan chain circuit described with reference to fig. 1A. Each scan chain circuit outputs an N-bit binary test vector to a corresponding one of the decoders 210 through its N scan flip-flops. Preferably, the M scan chains are connected to each other in series.
The invention also includes a chip test circuit using the clock gating control circuit of any of the various embodiments as described above. For example, in a chip test circuit based on a scan chain, the scan chain may be divided into M scan sub-chains (each including N scan flip-flops) and M N-bit binary outputs may be output to the clock gating control circuit, so as to control clock inputs of each circuit under test department in the chip test circuit. Of course, M scan chains (each including N scan flip-flops) may be used, and each scan chain may be connected in series with each other.
The clock gating control circuit and the corresponding chip test circuit of the invention are mainly described above. Although only a few embodiments of the present invention have been described in detail, those skilled in the art will appreciate that the present invention may be embodied in many other forms without departing from the spirit or scope thereof. Accordingly, the present examples and embodiments are to be considered as illustrative and not restrictive, and various modifications and substitutions may be made therein without departing from the spirit and scope of the present invention as defined by the appended claims.

Claims (10)

1. A clock gating control circuit for controlling a clock input to a plurality of circuit-under-test portions of a circuit-under-test, the clock gating control circuit comprising:
each decoder of the M decoders receives and decodes the N-bit binary input to generate an L-bit binary decoding and outputs L decoding sub-signals corresponding to the L-bit binary decoding;
a plurality of clock-gated circuit blocks, each clock-gated circuit block of the plurality of clock-gated circuit blocks for controlling a clock input of one or more of the circuit portions under test;
a functional logic circuit block that outputs a functional logic signal; and
l control modules, each of the L control modules enabling or disabling one or more of the clock-gated circuit blocks according to an externally input enable control signal, the M decode sub-signals, and the functional logic signal, wherein the M decode sub-signals consist of each of the M decoders providing one of the decode sub-signals, and wherein M, N and L are both positive integers.
2. The clock gating control circuit of claim 1, wherein each of the L control modules generates a first control output based on the M decoded sub-signals input thereto, the enable control signal comprising four types of a first instruction, a second instruction, a third instruction, and a fourth instruction, the control modules configured such that:
enabling or disabling the corresponding one or more clock-gated circuit blocks according to the functional logic signal when the enable control signal is the first instruction;
when the enable control signal is the second instruction, enabling or disabling the corresponding one or more clock gating circuit blocks according to a logical OR result of the first control output and the functional logic signal;
when the enable control signal is the third instruction, enabling or disabling the corresponding one or more clock-gated circuit blocks according to a logical AND result of the first control output and the functional logic signal; and
enabling or disabling the corresponding one or more clock-gated circuit blocks according to the first control output when the enable control signal is the fourth instruction.
3. The clock gating control circuit of claim 2, wherein the enable control signal comprises a first enable control signal and a second enable control signal, and wherein:
when the first enable control signal and the second enable control signal are both set to 0, the enable control signal is a first instruction;
when the first enable control signal is set to 1 and the second enable control signal is set to 0, the enable control signal is a second instruction;
when the first enable control signal is set to 0 and the second enable control signal is set to 1, the enable control signal is a third instruction; and
when the first enable control signal and the second enable control signal are both set to 1, the enable control signal is a fourth instruction.
4. The clock gating control circuit of claim 3, wherein the clock gating control circuit further comprises a NOT circuit for logically negating a second enable control signal prior to the second enable control signal being input to the control module and producing a second control output, the control module further comprising:
a first OR gate for logically OR-ing the M coded sub-signals to generate a first control output;
a first AND circuit for logically ANDing the first control output and the first enable control signal to generate a third control output;
a second OR gate for logically ORing the first control output and the second control output to produce a fourth control output;
a third OR gate for logically ORing the third control output and the functional logic signal to produce a fifth control output; and
a second AND circuit for logically ANDing the fourth control output and the fifth control output to produce a sixth control output, the sixth control output connected to an enable terminal of the respective one or more clock gating circuit blocks.
5. The clock gating control circuit of claim 4, wherein M is 2.
6. The clock gating control circuit of any one of claims 1-5, wherein the decoder employs a one-hot decoder that generates L-bit binary one-hot decoding with L equal to 2N。
7. The clock gating control circuit of any of claims 1-5, wherein the value of N is determined according to a flip rate of a chip test.
8. The clock gating control circuit of any one of claims 1-5, wherein the N-bit binary input is provided for each of the M decoders by M scan chains in one-to-one correspondence with the M decoders.
9. The clock gating control circuit of claim 8, wherein the M scan chains are connected in series with each other.
10. A chip test circuit comprising the clock gating control circuit of any one of claims 1 to 9.
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