WO2023181246A1 - Semiconductor light-emitting element chip integration device and production method for same - Google Patents

Semiconductor light-emitting element chip integration device and production method for same Download PDF

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Publication number
WO2023181246A1
WO2023181246A1 PCT/JP2022/013902 JP2022013902W WO2023181246A1 WO 2023181246 A1 WO2023181246 A1 WO 2023181246A1 JP 2022013902 W JP2022013902 W JP 2022013902W WO 2023181246 A1 WO2023181246 A1 WO 2023181246A1
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Prior art keywords
electrode
semiconductor light
chip
emitting element
light emitting
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PCT/JP2022/013902
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French (fr)
Japanese (ja)
Inventor
元伸 竹谷
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アルディーテック株式会社
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Priority to JP2024509569A priority Critical patent/JP7465612B2/en
Priority to PCT/JP2022/013902 priority patent/WO2023181246A1/en
Publication of WO2023181246A1 publication Critical patent/WO2023181246A1/en

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    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09FDISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09FDISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G09F9/30Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
    • G09F9/33Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements being semiconductor devices, e.g. diodes
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/36Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
    • H01L33/38Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/36Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
    • H01L33/40Materials therefor

Definitions

  • the present invention relates to a semiconductor light emitting element chip integration device and a method for manufacturing the same, and is suitable for application to, for example, a micro LED display in which a large number of miniaturized vertical (or vertical) micro light emitting diode (LED) chips are integrated on a substrate. It is something.
  • LCDs liquid crystal displays
  • OLEDs organic EL displays
  • Micro-LED displays are attracting attention as displays with high brightness and high efficiency (low power consumption) that far exceed LCDs and OLEDs.
  • Direct-emission micro LED displays are highly efficient, but in order to realize micro LED displays, it is necessary to arrange tens of millions of micro LED chips with sizes on the order of several micrometers to several tens of micrometers on a mounting board. .
  • Conventional methods for arranging a large number of micro LED chips on a mounting board include a method using a chip sorter, a method using a multi-chip transfer device (see Patent Documents 1 and 2), and a method using chip ejection by laser irradiation and liquid.
  • a method for arranging chips see Patent Document 3
  • a method for arranging elements (chips) using magnetic films see Patent Documents 4 and 5
  • the like have been proposed.
  • Patent Documents 1 to 5 it is difficult to realize a micro LED display at low cost.
  • Patent Documents 6 to 8 for example, ink in which micro LED chips whose p-side electrode is attracted to a magnetic field more strongly than the n-side electrode are dispersed in a liquid is applied to the chip bonding portion on the main surface of the substrate.
  • a micro LED display is manufactured by discharging and applying an external magnetic field from below the substrate to couple the p-side electrode side of the micro LED chip to the chip bonding part.
  • the problem to be solved by this invention is not only to be able to manufacture various semiconductor light emitting element chip integrated devices including micro LED displays at low cost, but also to be able to manufacture semiconductor light emitting element chips such as micro LED chips on a substrate. If a defective semiconductor light emitting element chip is found through inspection after being mounted on a semiconductor light emitting element chip, it can be easily repaired, and the number of wasted semiconductor light emitting element chips can be significantly reduced.
  • An object of the present invention is to provide an element chip integrated device and a method for manufacturing the same.
  • a vertical semiconductor light emitting device chip an upper main line electrode in the upper layer of the semiconductor light emitting element chip; and a plurality of upper branch line electrodes that branch from the upper main line electrode and straddle the chip coupling part so as to intersect with the plurality of lower branch line electrodes; and an upper electrode having
  • the semiconductor light emitting element chip has one of the p-side electrode and the n-side electrode facing the chip-coupling section and coupled to the chip-coupling section, and one of the p-side electrode and the n-side electrode. one of which is electrically connected to the lower branch line electrode, and the other of the p-side electrode and the n-side electrode and the upper branch electrode of the upper electrode are electrically connected to each other.
  • This is a light emitting element chip integrated device.
  • the substrate typically has a plurality of circuit units that can be driven independently of each other, and a lower electrode and an upper electrode are provided for each of the plurality of circuit units.
  • one pixel is typically configured by a region including three or more mutually adjacent circuit units.
  • the area of one pixel is selected as necessary.
  • the area of one pixel is typically selected to be approximately 500 ⁇ m ⁇ 500 ⁇ m, but may be larger or smaller than 500 ⁇ m ⁇ 500 ⁇ m.
  • three or more circuit units can emit light in three colors, red, green, and blue.
  • One of the p-side electrode and n-side electrode of the semiconductor light emitting element chip typically contains a soft magnetic material.
  • a soft magnetic material is a material that has a low coercive force and a high magnetic permeability, and is strongly magnetized under the influence of a magnetic field, but has the property of having no magnetic force in the absence of a magnetic field.
  • Examples of soft magnetic materials include nickel (Ni), iron (Fe), cobalt (Co), permalloy (Fe-78.5Ni alloy), supermalloy (Fe-79Ni-5Mo alloy), but are not limited to these. It is not something that will be done.
  • the semiconductor light emitting element may be a laser diode (LD) (particularly a vertical cavity surface emitting laser (VCSEL)), an organic EL element, or the like.
  • the semiconductor light emitting device may be an AlGaInN semiconductor light emitting device or an AlGaInP semiconductor light emitting device, but is not limited thereto.
  • AlGaInN-based semiconductor light-emitting devices are used to emit light in the blue-violet, blue to green wavelength range (wavelengths of 390 nm to 550 nm), and AlGaInP-based semiconductor light-emitting devices are used to emit light in the red wavelength range (wavelengths of 600 nm to 650 nm). Used when obtaining.
  • an AlGaInN semiconductor light emitting device and a phosphor may be combined.
  • the chip size of the semiconductor light emitting device chip is selected according to need, but is generally selected to be 20 ⁇ m x 20 ⁇ m or less, typically 10 ⁇ m x 10 ⁇ m or less, most typically 5 ⁇ m x 5 ⁇ m or less, and generally is 0.1 ⁇ m (100 nm) ⁇ 0.1 ⁇ m (100 nm) or more, or 0.5 ⁇ m (500 nm) ⁇ 0.5 ⁇ m (500 nm) or more. Further, the thickness of the semiconductor light emitting element chip is also selected as required, but is generally 10 ⁇ m or less, preferably 5 ⁇ m or less.
  • the semiconductor light emitting device chip is preferably obtained by separating the substrate from the semiconductor layer after crystal growth of the semiconductor layer constituting the semiconductor light emitting device on the substrate, and preferably has a thickness of, for example, 10 ⁇ m or less. .
  • the semiconductor light emitting device chip preferably has rotational symmetry about an axis perpendicular to the chip surface, and is, for example, circular, square, regular hexagonal, regular octagonal, etc. In this case, the semiconductor light emitting device chip as a whole has a rotational symmetry with respect to an axis perpendicular to the chip surface. Examples include a cylinder, a regular square prism, a regular hexagonal prism, a regular octagonal prism, etc., but are not limited to these.
  • the semiconductor light emitting element chip when the semiconductor light emitting element chip has a cylindrical shape, the semiconductor light emitting element chip preferably has a diameter of 10 ⁇ m or less and a thickness of 10 ⁇ m or less.
  • the number of p-side electrodes and n-side electrodes of a semiconductor light emitting element chip is typically one each, and the electrode size is equal to or smaller than the chip size, but which one of the p-side electrode and n-side electrode One or both of the electrodes may be formed of a plurality of electrodes having a size smaller than the chip size.
  • the semiconductor light emitting element chip is an AlGaInN-based or AlGaInP-based semiconductor light-emitting element chip
  • the maximum width of the light emitting layer of the semiconductor light-emitting element chip is 5 ⁇ m or less
  • the surroundings of this light-emitting layer are covered with an AlGaInN-based semiconductor layer that has a larger band gap and higher specific resistance than this light-emitting layer. It is covered with an AlGaInP-based semiconductor layer with a large gap and high specific resistance.
  • These semiconductor layers may be p-type, non-doped, or n-type.
  • the light emitting layer may be surrounded by a p-type semiconductor layer, and an n-type semiconductor layer, or an n-type semiconductor layer and a p-type semiconductor layer may be laminated thereon to form a covering layer.
  • the n-type semiconductor layer of the covering layer serves as a current blocking layer and reduces leakage current flowing through the covering layer.
  • it may be doped with a transition metal such as Fe that forms a deep level in the band gap of the semiconductor. Sidewall interfaces created by etching or the like have a high rate of non-radiative recombination.
  • Covering with a semiconductor layer having a large bandgap can be expected to have an effect of confining carriers in the light emitting layer in the horizontal direction. Furthermore, the effect of reducing defects on the sidewalls of the light-emitting layer can be expected due to semiconductor crystal growth at high temperatures during coating. Further, since the light-emitting layer portion is substantially n-type when covered with a p-type semiconductor layer, a depletion layer is formed at the interface of the sidewall and the resistance becomes high, thereby significantly reducing the probability that carriers will move to the sidewall.
  • AlGaInN-based or AlGaInP-based semiconductor light-emitting element chip By configuring the AlGaInN-based or AlGaInP-based semiconductor light-emitting element chip in this manner, high light-emitting efficiency can be obtained even in a fine semiconductor light-emitting element chip whose maximum width of the light-emitting layer is 5 ⁇ m or less.
  • the substrate (or mounting substrate) is not particularly limited, and includes, for example, a Si substrate, a glass substrate, a glass epoxy substrate, a resin film, a printed circuit board, and the like.
  • the substrate may be rigid or flexible, and may be transparent, translucent, or opaque, and may be selected as appropriate.
  • the width of the plurality of lower branch line electrodes constituting the lower electrode, the width of the gap between the lower branch line electrodes, etc. are selected as necessary.
  • the width of each lower branch line electrode is 5 to 100 ⁇ m
  • the width of the gap between the branch electrodes is 1 to 5 ⁇ m.
  • the number of lower branch line electrodes will be described later.
  • these plurality of lower branch electrodes are provided in parallel to each other.
  • the upper surface of each lower branch electrode constitutes a tip coupling section. This chip bonding portion is a region where semiconductor light emitting device chips are bonded.
  • At least one semiconductor light emitting element chip is coupled to the chip coupling part of at least one lower branch line part electrode of the plurality of lower branch line part electrodes, but a chip coupling part to which not a single semiconductor light emitting element chip is coupled. may also be included.
  • the semiconductor light emitting element chip may be bonded to any position in the chip bonding portion, but if the bonding position is desired to be determined in advance, a ferromagnetic region is provided in the area of the chip bonding portion. By doing so, one of the p-side electrode and the n-side electrode of the semiconductor light emitting element chip is attracted toward this ferromagnetic region by magnetic force, and is easily coupled to the ferromagnetic region.
  • ferromagnetic regions are formed at the desired bonding positions. These ferromagnetic regions may be provided between the substrate and the lower branch electrode, or may be provided on the chip coupling portion.
  • the area of the ferromagnetic region is typically selected to be less than or equal to the area of one of the p-side electrode and n-side electrode of the semiconductor light emitting element chip.
  • the shape of the ferromagnetic region is typically selected to be similar to the shape of one of the p-side electrode and n-side electrode of the semiconductor light emitting element chip, but is not limited thereto.
  • the ferromagnetic region typically consists of a soft magnetic material or a hard magnetic material.
  • Hard magnetic materials have a property of having coercive force even when a magnetic field is removed, and are used as permanent magnets. Examples of hard magnetic materials include neodymium iron boron (Nd-Fe-B) magnets, cobalt platinum (Co-Pt) magnets (Co-Pt magnets, Co-Cr-Pt magnets, etc.), and samarium cobalt (Sm-Co). magnets, samarium iron nitrogen (Sm-Fe-N) magnets, ferrite magnets, alnico magnets, etc., but are not limited thereto.
  • the width of the plurality of upper branch line part electrodes constituting the upper layer of the upper layer of the semiconductor light emitting element chip, the width of the gap between the lower branch line part electrodes, etc., are determined as necessary in the same way as the plurality of lower branch line part electrodes constituting the lower electrode.
  • the width of each upper branch line electrode is 5 to 100 ⁇ m, and the width of the gap between the upper branch line electrodes is 1 to 5 ⁇ m.
  • the number of upper branch line electrodes will be described later.
  • these upper branch line electrodes are provided parallel to each other, and these upper branch line part electrodes are provided at right angles to the lower branch line electrodes, but are not limited thereto.
  • the number of the plurality of lower branch line electrodes forming the lower electrode is L (L ⁇ 4) and the number of the plurality of upper branch line electrodes forming the upper electrode is U (U ⁇ 4)
  • L L
  • U U
  • L ⁇ U ⁇ 16 the number of circuit units included in a semiconductor light emitting device chip integrated device
  • the number of chips used in one circuit unit must be It is necessary to create a design in which the number of defective chips is set at around 5 and the circuit unit can be utilized by repair even if the number of defective chips is 3.
  • both the numbers L and U are 3 or less, there is a possibility that all the lower branch line electrodes in one circuit unit include one or more defective semiconductor light emitting element chips. In that case, repair by cutting the lower branch electrode becomes difficult. Therefore, in order to ensure the yield, it is desirable that the number of either the lower branch line electrode or the upper branch line electrode be four or more. Furthermore, it is more likely that good chips can be utilized by cutting the lower branch line electrode and the upper branch line electrode, whichever is larger in number. Therefore, in order to increase the probability of using good chips, it is preferable that the number of both the lower branch line part electrode and the upper branch line part electrode be 4 or more. If the number of chips used in one circuit unit is larger than necessary, the proportion of defective chips will increase.
  • At least a portion of the lower branch electrode and/or at least a portion of the upper branch electrode may be composed of a low melting point metal having a melting point of 350° C. or lower, typically 150° C. or higher; A part can be used as a fuse. That is, when the lower branch line electrode or the upper branch line electrode is energized, the portion made of the low melting point metal is selectively melted due to heat generation, thereby cutting the lower branch line electrode or the upper branch line electrode.
  • Such metals include In, Sn, etc. as single metals, and InSn, InSnAg, AgSn, AgSn, etc. as alloys (eutectic alloys), but are not limited thereto.
  • the entire lower branch line electrode or upper branch line electrode is made of a material with a high melting point, it can be cut by irradiating a portion of the lower branch line electrode or upper branch line electrode made of that material with a laser beam or electron beam. can do.
  • the cut point may be at any position on the lower branch line electrode or the upper branch line electrode, as long as no other problems occur, and any position can serve as a fuse.
  • the semiconductor light emitting element chip integrated device has a p-side electrode and an n-side electrode on the upper and lower sides, and one of the p-side electrode and the n-side electrode is connected to the other.
  • the device further includes a vertical Zener diode that is configured to be more strongly attracted to the magnetic field, and the Zener diode is connected so as to be reverse biased with respect to the semiconductor light emitting element chip. By connecting this Zener diode so that a reverse bias is applied between the lower electrode and the upper electrode, even if a surge voltage etc.
  • Zener diode Since the current can escape through the semiconductor light emitting element chip, electrostatic discharge damage (ESD) of the semiconductor light emitting element chip can be effectively prevented.
  • ESD electrostatic discharge damage
  • the mixing ratio of Zener diodes is one-tenth or less of the semiconductor light emitting element chip.
  • the semiconductor light emitting element chip integrated device may be of any type, and is designed as appropriate depending on the type of semiconductor light emitting element chip.
  • the semiconductor light emitting element chip integrated device may be one in which not only one type of semiconductor light emitting element chips are integrated, but also one in which two or more types of semiconductor light emitting element chips are integrated, or one in which a phosphor is combined.
  • Examples of the semiconductor light emitting element chip integrated device include, but are not limited to, a light emitting diode lighting device, a light emitting diode backlight, a light emitting diode display, and the like.
  • the size, planar shape, etc. of the semiconductor light emitting element chip integrated device are appropriately selected depending on the application of the semiconductor light emitting element chip integrated device, the functions required of the semiconductor light emitting element chip integrated device, and the like.
  • this invention applying a magnetic field to the soft magnetic region of the substrate provided with the soft magnetic region in the chip coupling portion to magnetize the soft magnetic region; After the magnetic field is removed and before the residual magnetic flux of the soft magnetic region disappears, the soft magnetic region has a p-side electrode and an n-side electrode above and below, and one of the p-side electrode and the n-side electrode is compared to the other.
  • a droplet-shaped ink containing a liquid and a plurality of vertical semiconductor light emitting element chips configured to be more strongly attracted by a magnetic field is supplied to the chip coupling portion, and the semiconductor light emitting element chips in the ink are
  • a method for manufacturing a semiconductor light emitting element chip integrated device comprising: coupling one of the p-side electrode and the n-side electrode toward the soft magnetic region and onto the soft magnetic region.
  • the liquid contained in the ink containing the semiconductor light emitting element chip is not particularly limited as long as it can disperse the semiconductor light emitting element chip used, and may be a polar solvent or a nonpolar solvent, and may be used as necessary.
  • the polar solvent may be a polar aprotic solvent or a protic solvent.
  • this liquid may be water or a non-aqueous solvent (including a mixture of two or more solvents excluding water, a mixture of water and two or more solvents excluding water), and a non-aqueous solvent.
  • the solvent may be an inert solvent or an active solvent.
  • the concentration of semiconductor light emitting device chips in the ink is selected as necessary, but typically, semiconductor light emitting device chips are dispersed in the liquid so that 10 to 10,000 semiconductor light emitting device chips exist in a volume of 100 picoliters. .
  • the volume fraction of semiconductor light emitting element chips in the ink is selected as required, but is typically 30% or less.
  • the viscosity of the ink is selected as required, and is, for example, in the range of 0.001 to 100 Pa ⁇ s.
  • the method of supplying ink to the chip bonding portion of the substrate is not particularly limited and may be selected as necessary.
  • the form of the droplet-shaped ink supplied to the chip joint varies depending on the wettability of the ink to the chip joint, and can take various forms, from spherical droplets with a large curvature to flat droplets with a small curvature. .
  • ink is ejected from the tip of the nozzle onto the tip joint.
  • the inkjet printing method is used to eject ink from the tip of the nozzle to the chip joint portion.
  • the amount of ink to be ejected may be an amount that includes a plurality of semiconductor light emitting device chips (for example, 2 to 100, or more in some cases) per one chip joint, and is typically 10 picoliters. These are the above, but they are selected according to need.
  • the liquid component of the ink supplied to the chip bonding portion of the substrate is removed by forced drying by heating or by natural drying.
  • the semiconductor light emitting element chip contained in the supplied ink is brought into contact with the chip bonding portion with one of the p-side electrode and the n-side electrode directed toward the chip bonding portion, by a method described later.
  • a droplet contains multiple semiconductor light emitting device chips, and by making the number flexible, it improves the applicability of inkjet printing methods, etc., and furthermore, the area of the chip bonding part can be reduced to the size of the semiconductor light emitting device chip.
  • the manufacturing process is dramatically simplified by setting the size larger than the area and giving a considerable degree of freedom in the bonding position between multiple semiconductor light emitting device chips and the chip bonding part, eliminating the complexity of controlling the chip bonding position. can be done.
  • the chip bonding area is a limited area that occupies a small proportion of the substrate, the multiple semiconductor light emitting device chips remain within the spread range of the ejected droplets and are not scattered over the entire substrate. , it is possible to efficiently couple with the chip coupling part.
  • This method for manufacturing a semiconductor light emitting element chip integrated device is suitable for application to manufacturing the above-mentioned semiconductor light emitting element chip integrated device.
  • the lower electrode has a lower trunk electrode and a plurality of lower branch electrodes branched from the lower trunk electrode, and the upper electrode branches from the upper trunk electrode and the upper trunk electrode, A semiconductor light-emitting element chip to which any of the upper branch electrodes was connected was defective due to the plurality of upper branch line electrodes spanning the chip coupling part so as to intersect with the plurality of lower branch line electrodes.
  • repair can be carried out by cutting only the upper branch line electrode or the lower branch line electrode where this semiconductor light emitting element chip is connected to the chip coupling part, so the semiconductor light emitting element chip is only wasted. The number of wasted semiconductor light emitting device chips can be significantly reduced.
  • the vertical By supplying a droplet-shaped ink containing a plurality of semiconductor light emitting device chips and a liquid to the chip bonding part, the semiconductor light emitting device chips in the ink are connected to the p-side electrode and the n-side electrode due to the effect of residual magnetic flux. Since one of the electrodes can be reliably coupled to the soft magnetic region, a semiconductor light emitting element chip integrated device can be easily manufactured.
  • FIG. 2 is a plan view showing an example of a vertical micro LED chip used in the micro LED chip integration device according to the first embodiment of the present invention.
  • FIG. 1 is a vertical cross-sectional view showing an example of a vertical micro LED chip used in the micro LED chip integration device according to the first embodiment of the present invention.
  • FIG. 2 is a schematic diagram showing ink used in manufacturing the micro LED chip integrated device according to the first embodiment of the present invention.
  • 1 is a schematic diagram showing an ink ejection device used for manufacturing a micro LED chip integrated device according to a first embodiment of the present invention.
  • FIG. 1 is a plan view showing a mounting board used for manufacturing a micro LED chip integrated device according to a first embodiment of the present invention.
  • FIG. 1 is a cross-sectional view showing a mounting board used for manufacturing a micro LED chip integrated device according to a first embodiment of the present invention.
  • 1 is a plan view for explaining a method of manufacturing a micro LED chip integrated device according to a first embodiment of the present invention
  • FIG. FIG. 1 is a cross-sectional view for explaining a method of manufacturing a micro LED chip integrated device according to a first embodiment of the present invention.
  • 1 is a plan view for explaining a method of manufacturing a micro LED chip integrated device according to a first embodiment of the present invention
  • FIG. FIG. 1 is a cross-sectional view for explaining a method of manufacturing a micro LED chip integrated device according to a first embodiment of the present invention.
  • FIG. 1 is a cross-sectional view for explaining a method of manufacturing a micro LED chip integrated device according to a first embodiment of the present invention.
  • 1 is a plan view for explaining a method of manufacturing a micro LED chip integrated device according to a first embodiment of the present invention;
  • FIG. 1 is a cross-sectional view for explaining a method of manufacturing a micro LED chip integrated device according to a first embodiment of the present invention.
  • FIG. 3 is a plan view for explaining a method for repairing a micro LED chip integrated device manufactured by the method for manufacturing a micro LED chip integrated device according to the first embodiment of the present invention.
  • FIG. 1 is a cross-sectional view for explaining a method of manufacturing a micro LED chip integrated device according to a first embodiment of the present invention.
  • 1 is a plan view for explaining a method of manufacturing a micro LED chip integrated device according to a first embodiment of the present invention.
  • FIG. 1 is a cross-sectional view for explaining a method of manufacturing a micro LED chip integrated device according
  • FIG. 3 is a cross-sectional view for explaining a method for repairing a micro LED chip integrated device manufactured by the method for manufacturing a micro LED chip integrated device according to the first embodiment of the present invention.
  • FIG. 3 is a plan view for explaining a method for repairing a micro LED chip integrated device manufactured by the method for manufacturing a micro LED chip integrated device according to the first embodiment of the present invention.
  • FIG. 3 is a cross-sectional view for explaining a method for repairing a micro LED chip integrated device manufactured by the method for manufacturing a micro LED chip integrated device according to the first embodiment of the present invention.
  • FIG. 7 is a plan view for explaining a method of manufacturing a micro LED chip integrated device according to a second embodiment of the present invention.
  • FIG. 7 is a cross-sectional view for explaining a method of manufacturing a micro LED chip integrated device according to a second embodiment of the present invention.
  • FIG. 7 is a cross-sectional view for explaining a method of manufacturing a micro LED chip integrated device according to a second embodiment of the present invention.
  • FIG. 7 is a cross-sectional view for explaining a method of manufacturing a micro LED chip integrated device according to a second embodiment of the present invention.
  • FIG. 7 is a cross-sectional view for explaining a method of manufacturing a micro LED chip integrated device according to a second embodiment of the present invention.
  • FIG. 7 is a cross-sectional view for explaining a method of manufacturing a micro LED chip integrated device according to a second embodiment of the present invention.
  • FIG. 7 is a cross-sectional view for explaining a method of manufacturing a micro LED chip integrated device according to a second embodiment of the present invention.
  • FIG. 7 is a cross-sectional view for explaining a method of manufacturing a micro LED chip integrated device according to a second embodiment of the present invention.
  • FIG. 7 is a plan view for explaining a method of manufacturing a micro LED chip integrated device according to a second embodiment of the present invention.
  • FIG. 7 is a plan view for explaining a method of manufacturing a micro LED chip integrated device according to a second embodiment of the present invention.
  • FIG. 7 is a plan view for explaining a method of manufacturing a micro LED chip integrated device according to a third embodiment of the present invention.
  • FIG. 7 is a plan view for explaining a method of manufacturing a micro LED chip integrated device according to a third embodiment of the present invention.
  • the micro LED chip integrated device is manufactured by mounting a large number of vertical micro LED chips on a mounting board.
  • a vertical micro LED chip configured such that the side electrode is attracted to a magnetic field more strongly than the p-side electrode, an ink containing this vertical micro LED chip, an ink ejection device used for ejecting this ink, and a mounting board explain.
  • FIGS. 1A and 1B An example of this vertical micro LED chip is shown in FIGS. 1A and 1B.
  • FIG. 1A is a plan view
  • FIG. 1B is a longitudinal cross-sectional view.
  • This vertical micro LED chip 40 has a cylindrical shape as a whole.
  • this vertical micro LED chip 40 includes an n-type GaN layer 41, an In x Ga 1-x N layer as a barrier layer, and an In y Ga 1-y N layer as a well layer.
  • a light emitting device having an In x Ga 1-x N/In y Ga 1-y N multiple quantum well (MQW) structure (x ⁇ y, 0 ⁇ x ⁇ 1, 0 ⁇ y ⁇ 1) in which layers are stacked alternately.
  • a layer 42 and a p-type GaN layer 43 are sequentially laminated. These n-type GaN layer 41, light-emitting layer 42, and p-type GaN layer 43 are each circular.
  • the diameter of the upper part of the n-type GaN layer 41 is smaller than the diameter of the lower part.
  • the diameters of the light emitting layer 42 and the p-type GaN layer 43 are the same as the diameter of the upper part of the n-type GaN layer 41.
  • the diameters of the upper part of the n-type GaN layer 41, the light-emitting layer 42, and the p-type GaN layer 43 are 5 ⁇ m or less.
  • a p-type or non-doped GaN layer 44 having a high specific resistance is provided so as to cover the upper part of the n-type GaN layer 41 and the outer periphery of the light-emitting layer 42 and the p-type GaN layer 43.
  • the diameter of the outer peripheral surface of the GaN layer 44 is the same as the diameter of the lower part of the n-type GaN layer 41.
  • a p-side electrode 45 made of ITO is formed on the p-type GaN layer 43, and an n-side electrode 46 is formed on the n-type GaN layer 41.
  • the p-side electrode 45 is circular, and is formed on the entire surface of the p-type GaN layer 43 as an example here.
  • the n-side electrode 46 is provided over the entire surface of the n-type GaN layer 41.
  • the n-side electrode 46 contains Ni as a soft magnetic material, and is made of, for example, a multilayer film such as a Ti/Al/Ti/Ni/Ti/Au film.
  • a Sn film 47 as a low melting point metal is provided on the n-side electrode 46.
  • the thickness of the Sn film 47 is, for example, 0.5 ⁇ m.
  • the total thickness of the n-type GaN layer 41, the light emitting layer 42, and the p-type GaN layer 43 is, for example, 1 to 3 ⁇ m.
  • the In composition ratios x and y of the In x Ga 1-x N/In y Ga 1-y N MQW structure constituting the light emitting layer 42 are selected according to the emission wavelength of the vertical micro
  • This vertical micro LED chip 40 can be easily manufactured by a conventionally known method.
  • ink 200 is prepared by dispersing vertical micro LED chips 40 in liquid 50 in container 100.
  • the ink 200 contains a filler, a surfactant, and the like in addition to the vertical micro LED chip 40 as necessary.
  • the size of the vertical micro LED chip 40 is small as described above, the dispersibility in the ink 200 is sufficiently high, and the ink can be easily ejected from the ejection nozzle of the ink ejection device.
  • FIG. 3 shows an ink discharge device 300.
  • the ink ejection device 300 has an inkjet print head 301.
  • the inkjet print head 301 has an ink chamber 302 inside and an ink supply section 303 at the top.
  • the inside of the inkjet print head 301 further includes a flow path 305 that connects the upper side of the ink chamber 302 and a tube section 303a provided at the bottom of the ink supply section 303, and a flow path connected to the lower side of the ink chamber 302. 306.
  • a control valve 307 is provided in the middle of the pipe section 303a of the ink supply section 303.
  • a discharge nozzle 308 is provided below the ink chamber 302 .
  • the diameter of the discharge nozzle 308 is selected as required, and is, for example, 10 to 50 ⁇ m.
  • a piezo actuator 309 is provided above the ink chamber 302 and has a structure in which a piezoelectric body is sandwiched between a pair of electrodes.
  • the flow path 306 has a function of discharging the ink 200 in the ink chamber 302 to the outside, returning the ink to the ink supply section 303 and circulating it to prevent clogging of the ejection nozzle 308, and having a function of stirring the ink 200. It is for the purpose of
  • ink 200 is supplied to the ink supply section 303 with the control valve 307 open.
  • the ink 200 thus supplied to the ink supply section 303 is supplied to the ink chamber 302 through the pipe section 303a and the flow path 305.
  • Ink 200 is supplied until channel 305, ink chamber 302, and channel 306 are filled, and then control valve 307 is closed.
  • This ink ejection device 300 further includes a magnetic field application device 311 at a position slightly shifted from the ejection nozzle 308 of this ink ejection device 300 in the horizontal direction.
  • a mounting board 400 which will be described later and which discharges ink 200, is configured to move horizontally at a height between an inkjet print head 301 and a magnetic field application device 311.
  • FIGS. 4A and 4B show a mounting board 400 used for manufacturing this micro LED chip integrated device.
  • FIG. 4A is a plan view
  • FIG. 4B is a sectional view crossing the lower branch electrode and the lower trunk electrode in the vicinity thereof.
  • a lower electrode 420 is provided on one main surface of the substrate 410.
  • a region corresponding to one circuit unit that can be electrically controlled on/off is indicated by a chain line.
  • the lower electrode 420 includes a wide lower trunk electrode 4201 extending in one direction, and a lower trunk electrode 4201 branching from the lower trunk electrode 4201 in a direction perpendicular to the lower trunk electrode 4201.
  • the substrate 410 may be rigid or flexible, and may be transparent or opaque, depending on the needs.
  • the substrate 410 may be, for example, a Si substrate, a glass substrate, a glass epoxy substrate, or a resin film.
  • the lower electrode 420 can be formed, for example, by forming a nonmagnetic metal film on the entire surface of the substrate 410 by sputtering or vacuum evaporation, and then patterning this metal film into a predetermined shape by lithography and etching.
  • a nonmagnetic metal for example, a Ti/Al/Ti/Au/Ti laminated film is used, but a Cu (or Cu alloy)/Au/Ti laminated film may also be used.
  • the thicknesses of the films constituting the Ti/Al/Ti/Au/Ti stacked film are, for example, 5 to 10 nm, 300 to 1000 nm, 50 nm, 5 to 100 nm, and 50 nm from the bottom.
  • the upper surface of the lower branch electrode 4203 constitutes a chip coupling portion 421 .
  • the width, spacing, etc. of the lower branch line electrode 4203 are selected as necessary.
  • the mounting board 400 is placed horizontally below the ejection nozzle 308 of the ink ejection device 300.
  • the ink ejection device 300 is fixed, and the mounting board 400 is moved in the direction shown by the arrow in FIG. 3 within a horizontal plane by a transport mechanism (not shown).
  • the piezo actuator 309 By operating the piezo actuator 309, the ink 200 is ejected from the ejection nozzle 308 onto the chip bonding portion 421 of the mounting board 400.
  • One drop of ink 200 ejected in this way covers a region including all the lower branch electrodes 4203 in one circuit unit, and includes a sufficient number of vertical micro LED chips 40.
  • the number of vertical micro LED chips 40 included in one drop of ink 200 can be adjusted by the concentration of vertical micro LED chips 40 in ink 200, the number of times the ink 200 is ejected, and the like.
  • An example of the ink 200 in this state is shown in FIGS. 5A and 5B.
  • FIG. 5A is a plan view
  • FIG. 5B is a sectional view.
  • the volume of one drop of ink 200 is, for example, 1 to 10 picoliters.
  • the volume of the vertical micro LED chip 40 is generally 0.001 to 0.5 picoliters. For example, if the vertical micro LED chip 40 has a circular shape with a diameter of 1 ⁇ m and a thickness of 3 ⁇ m, the volume is approximately 0.0024 picoliters.
  • the mounting board 400 is moved a predetermined distance by a transport mechanism (not shown), and the chip coupling part 421 on which the ink 200 has been ejected is positioned above the magnetic field application device 311.
  • the magnetic field applying device 311 By applying a magnetic field using the magnetic field applying device 311, the Ni film included in the n-side electrode 46 of the plurality of vertical micro LED chips 40 included in the ink 200 is magnetized. Therefore, each vertical micro LED chip 40 is drawn downward in the ink 200 by the magnetic force, and finally each vertical micro LED chip 40 comes into contact with the chip coupling part 421 with the n-side electrode 46 side facing down. do.
  • the magnetic field is preferably applied by the magnetic field applying device 310 before ejecting the ink 200. Alternatively, it is performed at the time of ejection or before the liquid of the ink 200 evaporates from that time.
  • each vertical micro LED chip 40 is kept in contact with the chip coupling part 421 by magnetic force, the solvent of the ink 200 is evaporated by heating with a lamp or the like, and then heating is performed with a lamp, laser, or the like.
  • the Sn film 47 of each vertical micro LED chip 40 is melted. Thereafter, as the molten Sn cools, the n-side electrode 46 of each vertical micro LED chip 40 is electrically and mechanically coupled to the chip coupling portion 421 of the lower branch electrode 4203.
  • FIGS. 6A and 6B An example of this state is shown in FIGS. 6A and 6B.
  • FIG. 6A is a plan view
  • FIG. 6B is a sectional view.
  • the vertical micro LED chips 40 are randomly arranged in the chip coupling part 421.
  • the chip coupling part 421 may include one in which not a single vertical micro LED chip 40 is coupled, and such an example is shown in FIG. 6A.
  • an insulating film 422 is formed on the entire surface of the mounting board 400 on which the vertical micro LED chip 40 is coupled to the chip coupling part 421 so that the surface is almost flat.
  • the p-side electrode 45 (not shown) is exposed by etching using reactive ion etching (RIE) or the like.
  • a layer is placed on the insulating film 422 so as to extend in a direction perpendicular to all the lower branch electrodes 4203 in each circuit unit, and to cover all the lower branch electrodes 4203 in each circuit unit.
  • a plurality of elongated transparent electrodes 435 in the form of strips are formed so as to straddle the area.
  • the gap between these transparent electrodes 435 is made smaller than the diameter of the p-side electrode 45 of the vertical micro LED chip 40. By doing so, the p-side electrode 45 of the vertical micro LED chip 40 coupled to the chip coupling portion 421 can come into contact with any of the transparent electrodes 435.
  • the transparent electrode 435 is made of a transparent electrode material such as ITO.
  • the upper electrode 430 includes a plurality of upper trunk electrodes 431 extending parallel to each other in a direction orthogonal to the lower trunk electrode 4201 and a plurality of upper trunk electrodes 431 extending from each upper trunk electrode 431 to each circuit in a direction orthogonal to the upper trunk electrode 431. It consists of an upper branch electrode 432 extending one per unit. Each upper branch line electrode 432 is branched into a plurality of branches so as to extend in a direction parallel to each upper trunk line electrode 431 and, therefore, in a direction perpendicular to the lower branch line part electrode 4203, and their tips are connected to a transparent electrode 435. ing.
  • the transparent electrode 435 constitutes a part of the upper branch line portion electrode 432.
  • the micro LED chip integrated device manufactured as described above is inspected. Specifically, a current conduction test is performed between the upper electrode 430 and the lower electrode 420. That is, by applying a voltage so that the upper electrode 430 has a higher potential than the lower electrode 420, a current of, for example, about 1 ⁇ A is caused to flow through each vertical micro LED chip 40, and the light emission of each vertical micro LED chip 40 is image-analyzed. Then, the transparent electrode 435 and the upper branch line electrode 432 to which the vertical micro LED chip 40 with a defective light amount due to a leakage defect is connected are identified. In FIG. 9, the upper branch line portion electrodes 432 identified in this manner are indicated by reference numerals 432A and 432B.
  • FIG. 10 shows the state of the upper branch line electrodes 432A and 432B after cutting.
  • all of the vertical micro LED chips 40 connected to the transparent electrodes 435 to which the cut upper branch line electrodes 432A and 432B are connected become unusable, but the other upper branch line electrodes 432 are connected. All vertical micro LED chips 40 connected to transparent electrodes 435 can be used.
  • the upper branch line electrode 432 is cut near the defective chip so as to be close to the upper main line electrode 431.
  • the good chips on the side can be used without being sacrificed.
  • a current of, for example, about 1 ⁇ A is caused to flow between the upper electrode 430 and the lower electrode 420, and the light emission from each vertical micro LED chip 40 is image-analyzed. As a result, if no vertical micro LED chip 40 with a defective light amount is found, the repair ends. In this way, the micro LED chip integrated device can be repaired.
  • this micro LED chip integrated device has lower trunk electrodes 4201 and 4202 on one main surface and a plurality of lower trunk electrodes 4202 branched from the lower trunk electrode 4202. a substrate 410 having a lower electrode 420 having a lower branch line electrode 4203; a chip coupling part 421 configured by the upper surface of the lower branch line part electrode 4203 of the lower electrode 420; A vertical micro LED chip 40 has a side electrode 45 and an n-side electrode 46, and is configured such that the n-side electrode 46 is attracted to a magnetic field more strongly than the p-side electrode 45; An upper main line electrode 431 of the upper layer branches from the upper main line electrode 431 and extends in a direction perpendicular to the plurality of lower branch line electrodes 4203, and a transparent electrode 435 connects to the tip coupling part 421 of the lower branch line electrode 4203.
  • the vertical micro LED chip 40 is coupled to the chip coupling part 421 with the n-side electrode 46 facing the chip coupling part 421, and the n-side electrode 46 and the lower branch electrode 4203 are electrically connected to each other.
  • the p-side electrode 45 and the upper branch electrode 432 of the upper electrode 430 are electrically connected to each other.
  • the n-side electrode 46 of the vertical micro-LED chip 40 is The electrode 46 side is configured to be attracted to the magnetic field more strongly than the p-side electrode 45 side, and ink 200 is ejected to the chip coupling part 421 of the lower branch electrode 4203 in one circuit unit, and the vertical micro LED chip
  • the vertical micro LED chip 40 and the chip coupling part 421 are electrically and mechanically coupled by attracting the n-side electrode 46 side of the chip 40 by magnetic force and bringing it into contact with the chip coupling part 421, and then melting and solidifying the Sn film 47.
  • a micro LED chip integrated device such as a micro LED display, a micro LED backlight, a micro LED lighting device, etc. can be easily realized at low cost, regardless of the degree of integration of the vertical micro LED chips 40.
  • a micro LED chip integrated device such as a micro LED display, a micro LED backlight, a micro LED lighting device, etc.
  • it is sufficient to couple the vertical micro LED chips 40 in a random arrangement on the chip coupling part 421 there is no need for highly accurate position control of the vertical micro LED chips 40, and the manufacturing of the micro LED chip integrated device is simplified. It becomes easier.
  • the vertical micro LED chip 40 to which any of the upper branch line electrodes 432 is connected If there is a defect in the LED, it can be easily repaired by simply cutting the upper branch electrode 432 or by cutting only the lower branch electrode 4203 where the vertical micro LED chip 40 is connected to the chip coupling part 421. can be done. Therefore, the number of wasted vertical micro LED chips 40 due to repair can be kept to a minimum, and the number of wasted vertical micro LED chips 40 can be significantly reduced.
  • this micro LED chip integrated device constitutes an RGB-1 pixel using the three circuit units shown in FIGS.
  • the upper electrode main line portion 431 constitutes column electrode wiring.
  • red and green phosphors are formed above the red and green light emitting regions, respectively.
  • blue, red, and green phosphors are formed above the blue, red, and green light-emitting regions, respectively.
  • a transparent substrate made of a flexible film or the like is provided thereon, and a light-diffusing layer is further placed on top of it. Provide a diffusion sheet.
  • the second embodiment differs from the first embodiment in that the mounting board 400 shown in FIGS. 11A and 11B is used instead of the mounting board 400 shown in FIGS. 4A and 4B. That is, as shown in FIGS. 11A and 11B, in this mounting board 400, a circular soft magnetic material 500 such as Ni is placed on the substrate 410 in a portion below the chip coupling part 421 of the lower branch electrode 4203. A plurality of (four in this case) branch electrodes 4203 are provided in a row at equal intervals along the center line of the branch electrodes 4203, and the lower branch electrodes 4203 are provided so as to cover these soft magnetic bodies 500.
  • a circular soft magnetic material 500 such as Ni is placed on the substrate 410 in a portion below the chip coupling part 421 of the lower branch electrode 4203.
  • a plurality of (four in this case) branch electrodes 4203 are provided in a row at equal intervals along the center line of the branch electrodes 4203, and the lower branch electrodes 4203 are provided so as to cover these soft magnetic bodies 500
  • the diameter of the soft magnetic material 500 is selected to be equal to or smaller than the diameter of the n-side electrode 46 of the vertical micro LED chip 40.
  • a portion of the chip coupling portion 421 of the lower branch electrode 4203 that corresponds to the soft magnetic material 500 is a coupling position of the vertical micro LED chip 40 .
  • a circular Sn film 47 is provided at the chip bonding portion 421 at this bonding position. In this case, it is not necessary to form the Sn film 47 of the vertical micro LED chip 40.
  • the other aspects of this mounting board 400 are the same as those of the first embodiment.
  • FIG. 12 schematically shows a part of the mounting board 400 shown in FIG. 11B.
  • the soft magnetic material 500 is magnetized by applying a magnetic field as indicated by the arrows using a magnetic field application device (not shown). After this, the application of the magnetic field is stopped. In this case, even after the application of the magnetic field is stopped, residual magnetic flux 501 is generated from the soft magnetic body 500 for a while, as shown in FIG. 13.
  • FIG. 14 shows the state immediately after discharge.
  • the ink 200 ejected in this way spreads over the entire chip coupling portion 421, and at the same time, the residual magnetic flux 501 generated from the soft magnetic material 500 causes the ink 200 to be contained therein.
  • the Ni films included in the n-side electrodes 46 of the plurality of vertical micro LED chips 40 are magnetized. Therefore, each vertical micro LED chip 40 is drawn downward by the magnetic force in the ink 200, and finally each vertical micro LED chip 40 is placed so that the n-side electrode 46 side is facing down, and the Sn The membrane 47 is contacted. This state is shown in FIG.
  • each vertical micro LED chip 40 is mechanically and electrically connected with the n-side electrode 46 side down.
  • Reference numeral 48 indicates Sn that has been melted and solidified.
  • the vertical micro LED chip 40 is coupled to the chip coupling portion 421 in each circuit unit.
  • the steps after forming the insulating film 422 are performed to manufacture the intended micro LED chip integrated device as shown in FIG. 18.
  • a soft magnetic material 500 is placed on the substrate 410 in a portion below the chip coupling portion 421 of the lower branch electrode 4203 of the mounting board 400 at the center of the lower branch electrode 4203.
  • a plurality of lower branch electrodes 4203 are provided along the line, and a lower branch electrode 4203 is provided to cover these soft magnetic bodies 500, and a vertical micro LED chip 40 is coupled to the chip coupling portion 421 with the n-side electrode 46 side facing down.
  • the micro LED chip integrated device has the same configuration as the micro LED chip integrated device according to the first embodiment except that the micro LED chip integrated device has the same configuration as the micro LED chip integrated device according to the first embodiment.
  • the lower branch electrode 4203 by providing the soft magnetic material 500 in advance on the substrate 410 below the chip coupling part 201 of the lower branch electrode 4203, the lower branch electrode 4203 can be Since the vertical micro LED chips 40 can be coupled on the chip coupling part 421, the coupling position of each vertical micro LED chip 40 is limited to the intersection of the lower branch line part electrode 4203 and the upper electrode branch part 432. I can do it. Therefore, it is possible to significantly reduce the number of vertical micro LED chips 40 that cause connection failures, and in turn, it is possible to reduce the manufacturing cost of the micro LED chip integrated device. In addition, advantages similar to those of the first embodiment can be obtained.
  • This micro LED chip integrated device also makes it possible to realize a color micro LED display using a passive matrix drive method.
  • ⁇ Third embodiment> a micro LED chip integrated device that can be used as an active matrix drive type color micro LED display will be described.
  • FIG. 19 shows a mounting board 400 before the upper electrode is formed in the third embodiment.
  • a plurality of lower trunk electrodes 4202 are provided on the mounting board 400 in parallel to each other in the row direction.
  • a plurality of lower branch line electrodes 4203 are connected to the lower main line electrode 4202 extending in a direction perpendicular to the lower main line electrode 4202, that is, in the column direction.
  • a soft magnetic material 500 is provided below the lower branch electrode 4203, similar to the second embodiment.
  • the vertical micro LED chip 40 is coupled to the chip coupling portion 421 of the lower branch electrode 4203 above the soft magnetic body 500.
  • the 19 constitute B, R, and G light emitting regions from the left, respectively, and RGB-1 pixel units constituted by these light emitting regions are arranged, and the mounting board 400 as a whole Pixels are arranged in a two-dimensional matrix.
  • On the mounting board 400 in addition to power supply lines 610 and data lines 620 extending in the column direction, scanning lines 630 extending in the row direction are also provided.
  • An active drive circuit is provided between each data line 620 and each light emitting region of each pixel, and the active drive circuit allows each light emitting region of each pixel to be selected.
  • the active drive circuit consists of transistors T1, T2 and capacitor C.
  • the transistors T1 and T2 are generally formed by thin film transistors using semiconductor thin films such as polycrystalline Si thin films, and the capacitor C is formed by laminating a lower electrode, an insulating film, and an upper electrode.
  • the source of transistor T1 is connected to data line 620, the drain is connected to the gate of transistor T2, and the gate is connected to scan line 630.
  • the source of transistor T2 is connected to power supply line 610, and the drain is connected to lower electrode 420.
  • Capacitor C is connected between the drain of transistor T1 and power supply line 610. Each light emitting region of each pixel is selected by selecting the scanning line 630 and the data line 620.
  • a narrow lower main line electrode 4202 is connected to the lower main line electrode 4201 via an active drive circuit, which will be described later, and is provided in parallel to the lower main line electrode 4201.
  • FIG. 20 shows a state in which an upper electrode 430 is formed on the mounting board 400 shown in FIG. 19. Similar to the first embodiment, a plurality of transparent electrodes 435 are provided so as to straddle the chip coupling portions 421 of all the lower branch electrodes 4203 in each circuit unit. Upper branch electrodes 432 of the upper electrode 430 are connected to these transparent electrodes 435, respectively.
  • the vertical micro LED chip 40 emits blue light, and red and green phosphors are formed above the red light emitting region and the green light emitting region, respectively, as in the first embodiment.
  • the third embodiment it is possible to easily and efficiently mount the vertical micro LED chips 40 for each of RGB light emission on the mounting board 400, and to eliminate defective vertical micro LED chips 40. Since the influence of the LED chip 40 can also be easily removed, a high-performance active drive type color micro LED display can be realized at low cost. In addition, advantages similar to those of the second embodiment can also be obtained.

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Abstract

A semiconductor light-emitting element chip integration device comprises: a mounting substrate 400 that has a lower electrode 420 which has a lower main line part electrode 4202 on one main surface and a plurality of lower branch line part electrodes 4202 branching from the lower main line part electrode 4202; chip joining part 421 that is constituted by the upper surfaces of the lower branch line part electrodes; a vertical-type semiconductor light-emitting element chip 40 that is joined to the chip joining part, that has a p-side electrode 45 and an n-side electrode 46 above and below, and that is configured such that the n-side electrode is drawn by a stronger magnetic field than the p-side electrode; and an upper electrode 430 that is in a layer above the semiconductor light-emitting element chip and that has an upper main line part electrode 431 and a plurality of upper branch line part electrodes 432 which branch from the upper main line part electrode and which straddle the chip joining part so as to intersect the plurality of lower branch line part electrodes. The semiconductor light-emitting element chip is joined such that the n-side electrode 46 faces the chip joining part. The n-side electrode and the lower branch line part electrodes are electrically connected to each other. The p-side electrode and the upper branch line part electrodes of the upper electrode are electrically connected to each other.

Description

半導体発光素子チップ集積装置およびその製造方法Semiconductor light emitting device chip integrated device and its manufacturing method
 この発明は半導体発光素子チップ集積装置およびその製造方法に関し、例えば、微小化した縦型(あるいは垂直型)マイクロ発光ダイオード(LED)チップを基板上に多数集積したマイクロLEDディスプレイに適用して好適なものである。 The present invention relates to a semiconductor light emitting element chip integration device and a method for manufacturing the same, and is suitable for application to, for example, a micro LED display in which a large number of miniaturized vertical (or vertical) micro light emitting diode (LED) chips are integrated on a substrate. It is something.
 現在、薄型テレビやスマートフォンなどの表示装置(ディスプレイ)の主流は、液晶ディスプレイ(LCD)および有機ELディスプレイ(OLED)である。このうちLCDの場合、画素の微細化に伴い、出力される光量はバックライトの光量の10分の1程度である。OLEDも、理論上の電力効率は高いが、実際の製品はLCDと同等の水準に留まっている。 Currently, the mainstream display devices (displays) such as flat-screen televisions and smartphones are liquid crystal displays (LCDs) and organic EL displays (OLEDs). Among these, in the case of LCD, the amount of light outputted is about one-tenth of the amount of light from a backlight due to miniaturization of pixels. OLEDs also have high theoretical power efficiency, but actual products remain at the same level as LCDs.
 LCDおよびOLEDを遥かに凌ぐ高輝度、高効率(低消費電力)のディスプレイとしてマイクロLEDディスプレイが注目されている。直接発光のマイクロLEDディスプレイは高効率であるが、マイクロLEDディスプレイの実現のためには、数μmから数十μmオーダーのサイズのマイクロLEDチップを実装基板上に数千万個配列させる必要がある。 Micro-LED displays are attracting attention as displays with high brightness and high efficiency (low power consumption) that far exceed LCDs and OLEDs. Direct-emission micro LED displays are highly efficient, but in order to realize micro LED displays, it is necessary to arrange tens of millions of micro LED chips with sizes on the order of several micrometers to several tens of micrometers on a mounting board. .
 このように大量のマイクロLEDチップを実装基板上に配列させる方法として従来、チップソーターを用いる方法、マルチチップ転写装置を用いる方法(特許文献1、2参照)、レーザ照射によるチップ吐出と液体を利用したチップ配列方法(特許文献3参照)、磁性体膜を利用した素子(チップ)の配列方法(特許文献4、5参照)などが提案されている。 Conventional methods for arranging a large number of micro LED chips on a mounting board include a method using a chip sorter, a method using a multi-chip transfer device (see Patent Documents 1 and 2), and a method using chip ejection by laser irradiation and liquid. A method for arranging chips (see Patent Document 3), a method for arranging elements (chips) using magnetic films (see Patent Documents 4 and 5), and the like have been proposed.
 しかしながら、特許文献1~5で提案された方法では、マイクロLEDディスプレイを低コストで実現することは困難であった。 However, with the methods proposed in Patent Documents 1 to 5, it is difficult to realize a micro LED display at low cost.
 上述のような背景の下、本発明者は、マイクロLEDディスプレイを低コストで実現することが可能なマイクロLEDディスプレイの製造方法を提案した(特許文献6~8参照)。特許文献6~8では、例えばp側電極側がn側電極側に比べてより強く磁場に引き寄せられるように構成されたマイクロLEDチップを液体に分散させたインクを基板の主面のチップ結合部に吐出し、基板の下方から外部磁場を印加することによりマイクロLEDチップのp側電極側をチップ結合部に結合させることによりマイクロLEDディスプレイを製造する。 Against the background as described above, the present inventor proposed a method for manufacturing a micro LED display that can realize a micro LED display at low cost (see Patent Documents 6 to 8). In Patent Documents 6 to 8, for example, ink in which micro LED chips whose p-side electrode is attracted to a magnetic field more strongly than the n-side electrode are dispersed in a liquid is applied to the chip bonding portion on the main surface of the substrate. A micro LED display is manufactured by discharging and applying an external magnetic field from below the substrate to couple the p-side electrode side of the micro LED chip to the chip bonding part.
特表2017-531915号公報Special Publication No. 2017-531915 特表2017-500757号公報Special table 2017-500757 publication 特開2005-174979号公報Japanese Patent Application Publication No. 2005-174979 特開2003-216052号公報Japanese Patent Application Publication No. 2003-216052 特開2016-25205号公報Japanese Patent Application Publication No. 2016-25205 特許第6694222号公報Patent No. 6694222 特許第6842783号公報Patent No. 6842783 特許第6886213号公報Patent No. 6886213
 特許文献6~8に記載のマイクロLEDディスプレイの製造方法によれば、マイクロLEDディスプレイを低コストで実現することが可能であるが、検査によりマイクロLEDチップの不良が発見された場合、その修理を行うことができたとしても、無駄になるマイクロLEDチップの個数が多いことから、改善の余地があった。 According to the micro LED display manufacturing methods described in Patent Documents 6 to 8, it is possible to realize a micro LED display at low cost, but if a defect in the micro LED chip is found through inspection, it is difficult to repair it. Even if this could be done, there would be room for improvement since the number of micro LED chips that would be wasted would be large.
 そこで、この発明が解決しようとする課題は、マイクロLEDディスプレイをはじめとする各種の半導体発光素子チップ集積装置を低コストで製造することができるだけでなく、マイクロLEDチップなどの半導体発光素子チップを基板上に実装した後、検査により半導体発光素子チップの不良が発見された場合、修理を容易に行うことができるとともに、無駄になる半導体発光素子チップの個数の大幅な低減を図ることができる半導体発光素子チップ集積装置およびその製造方法を提供することである。 Therefore, the problem to be solved by this invention is not only to be able to manufacture various semiconductor light emitting element chip integrated devices including micro LED displays at low cost, but also to be able to manufacture semiconductor light emitting element chips such as micro LED chips on a substrate. If a defective semiconductor light emitting element chip is found through inspection after being mounted on a semiconductor light emitting element chip, it can be easily repaired, and the number of wasted semiconductor light emitting element chips can be significantly reduced. An object of the present invention is to provide an element chip integrated device and a method for manufacturing the same.
 上記課題を解決するために、この発明は、
 一方の主面に下部幹線部電極と当該下部幹線部電極から分岐した複数の下部支線部電極とを有する下部電極を有する基板と、
 上記下部電極の上記下部支線部電極の上面により構成されたチップ結合部と、
 上記チップ結合部に結合した、上下にp側電極およびn側電極を有し、上記p側電極および上記n側電極のうちの一方が他方に比べてより強く磁場に引き寄せられるように構成された縦型の半導体発光素子チップと、
 上記半導体発光素子チップの上層の、上部幹線部電極と当該上部幹線部電極から分岐し、上記複数の下部支線部電極と交差するように上記チップ結合部に跨がる複数の上部支線部電極とを有する上部電極とを有し、
 上記半導体発光素子チップは、上記p側電極および上記n側電極のうちの上記一方を上記チップ結合部に向けて上記チップ結合部に結合し、上記p側電極および上記n側電極のうちの上記一方と上記下部支線部電極とが互いに電気的に接続され、上記p側電極および上記n側電極のうちの他方と上記上部電極の上記上部支線部電極とが互いに電気的に接続されている半導体発光素子チップ集積装置である。
In order to solve the above problems, this invention
A substrate having a lower electrode having a lower main line electrode and a plurality of lower branch line electrodes branched from the lower main line electrode on one main surface;
a tip coupling portion configured by an upper surface of the lower branch electrode of the lower electrode;
It has a p-side electrode and an n-side electrode on the upper and lower sides, which are connected to the chip coupling part, and is configured such that one of the p-side electrode and the n-side electrode is more strongly attracted to the magnetic field than the other. A vertical semiconductor light emitting device chip,
an upper main line electrode in the upper layer of the semiconductor light emitting element chip; and a plurality of upper branch line electrodes that branch from the upper main line electrode and straddle the chip coupling part so as to intersect with the plurality of lower branch line electrodes; and an upper electrode having
The semiconductor light emitting element chip has one of the p-side electrode and the n-side electrode facing the chip-coupling section and coupled to the chip-coupling section, and one of the p-side electrode and the n-side electrode. one of which is electrically connected to the lower branch line electrode, and the other of the p-side electrode and the n-side electrode and the upper branch electrode of the upper electrode are electrically connected to each other. This is a light emitting element chip integrated device.
 基板は、典型的には、互いに独立駆動可能な複数の回路ユニットを有し、これらの複数の回路ユニットのそれぞれに対して下部電極および上部電極が設けられる。 The substrate typically has a plurality of circuit units that can be driven independently of each other, and a lower electrode and an upper electrode are provided for each of the plurality of circuit units.
 特に、半導体発光素子チップ集積装置がカラーディスプレイである場合には、典型的には、互いに隣接する3つ以上の回路ユニットを含む領域により1画素が構成される。この1画素の面積は必要に応じて選ばれる。1画素の面積は、典型的には、500μm×500μm程度に選ばれるが、500μm×500μmより大きくても小さくてもよい。この場合、3つ以上の回路ユニットにより、赤色、緑色、青色の3色の発光が行われるようにすることができる。 In particular, when the semiconductor light emitting element chip integrated device is a color display, one pixel is typically configured by a region including three or more mutually adjacent circuit units. The area of one pixel is selected as necessary. The area of one pixel is typically selected to be approximately 500 μm×500 μm, but may be larger or smaller than 500 μm×500 μm. In this case, three or more circuit units can emit light in three colors, red, green, and blue.
 半導体発光素子チップのp側電極およびn側電極のうちの一方は、典型的には、軟磁性体を含む。軟磁性体は、保磁力が小さく透磁率が大きい材料であり、磁場の影響下では強く磁化されるが、磁場が存在しない場合は磁力を持たない性質を有する。軟磁性体は、例えば、ニッケル(Ni)、鉄(Fe)、コバルト(Co)、パーマロイ(Fe-78.5Ni合金)、スーパーマロイ(Fe-79Ni-5Mo合金)などであるが、これに限定されるものではない。 One of the p-side electrode and n-side electrode of the semiconductor light emitting element chip typically contains a soft magnetic material. A soft magnetic material is a material that has a low coercive force and a high magnetic permeability, and is strongly magnetized under the influence of a magnetic field, but has the property of having no magnetic force in the absence of a magnetic field. Examples of soft magnetic materials include nickel (Ni), iron (Fe), cobalt (Co), permalloy (Fe-78.5Ni alloy), supermalloy (Fe-79Ni-5Mo alloy), but are not limited to these. It is not something that will be done.
 半導体発光素子は、発光ダイオード(LED)のほか、レーザダイオード(LD)(特に垂直共振器面発光レーザー(VCSEL))や有機EL素子などであってもよい。半導体発光素子は、AlGaInN系半導体発光素子やAlGaInP系半導体発光素子などであるが、これに限定されるものではない。AlGaInN系半導体発光素子は、青紫、青色から緑色の波長帯(波長390nm~550nm)の発光を得る場合に使用され、AlGaInP系半導体発光素子は、赤色の波長帯(波長600nm~650nm)の発光を得る場合に使用される。青色、緑色、赤色の波長帯を得るためにはAlGaInN系半導体発光素子と蛍光体を組み合わせて実現してもよい。 In addition to a light emitting diode (LED), the semiconductor light emitting element may be a laser diode (LD) (particularly a vertical cavity surface emitting laser (VCSEL)), an organic EL element, or the like. The semiconductor light emitting device may be an AlGaInN semiconductor light emitting device or an AlGaInP semiconductor light emitting device, but is not limited thereto. AlGaInN-based semiconductor light-emitting devices are used to emit light in the blue-violet, blue to green wavelength range (wavelengths of 390 nm to 550 nm), and AlGaInP-based semiconductor light-emitting devices are used to emit light in the red wavelength range (wavelengths of 600 nm to 650 nm). Used when obtaining. In order to obtain blue, green, and red wavelength bands, an AlGaInN semiconductor light emitting device and a phosphor may be combined.
 半導体発光素子チップのチップサイズは必要に応じて選ばれるが、一般的には20μm×20μm以下、典型的には10μm×10μm以下、最も典型的には5μm×5μm以下に選ばれ、一般的には0.1μm(100nm)×0.1μm(100nm)以上、あるいは0.5μm(500nm)×0.5μm(500nm)以上である。また、半導体発光素子チップの厚さも必要に応じて選ばれるが、一般的には10μm以下、好適には5μm以下である。半導体発光素子チップは、基板上に半導体発光素子を構成する半導体層の結晶成長を行った後、基板を半導体層から分離したものであることが望ましく、厚さは例えば10μm以下であることが望ましい。半導体発光素子チップは、好適には、チップ面に垂直な軸に関し回転対称性を有し、例えば、円形、正方形、正六角形、正八角形などであり、この場合、半導体発光素子チップは全体としてそれぞれ円柱、正四角柱、正六角柱、正八角柱などであるが、これに限定されるものではない。特に、半導体発光素子チップが円柱状である場合、半導体発光素子チップは、好適には直径10μm以下、厚さ10μm以下である。また、半導体発光素子チップのp側電極およびn側電極の数は典型的にはそれぞれ1つであり、電極サイズはチップサイズと同等かそれ以下であるが、p側電極およびn側電極のどちらか一方または両方がチップサイズよりも小さいサイズの複数の電極により形成されていてもよい。また、特に半導体発光素子チップがAlGaInN系またはAlGaInP系の半導体発光素子チップである場合、好適には、半導体発光素子チップの発光層の最大幅は5μm以下であり、AlGaInN系の半導体発光素子チップにおいてはこの発光層の周囲がこの発光層よりバンドギャップが大きく、かつ比抵抗の高いAlGaInN系の半導体層によって被覆され、AlGaInP系の半導体発光素子チップにおいてはこの発光層の周囲がこの発光層よりバンドギャップが大きく、かつ比抵抗の高いAlGaInP系の半導体層によって被覆される。これらの半導体層は、p型、ノンドープ、n型のいずれであってもよい。発光層の周囲をp型半導体層で覆い、その上にn型半導体層、またはn型半導体層およびp型半導体層を積層して被覆層としてもよい。この場合は、被覆層のn型半導体層が電流ブロック層の役割を果たし、被覆層を流れるリーク電流を低減する。また、被覆層を高抵抗化させるために半導体のバンドギャップに深い準位を形成するFeなどの遷移金属をドープしてもよい。エッチングなどによって生じた側壁界面は非発光再結合の割合が高い。半導体発光素子チップが微細化するほど電子などのキャリアは発光層の側壁に到達しやすく、そこで非発光再結合し発光効率を低下させる。そのため、半導体発光素子チップは微細化されるに従って発光効率は低下する。この現象を避けるためには、発光層の側壁付近を避けて電流を流すことが有効である。そのための方法は幾つか考えられるが、発光層の側壁を発光層よりバンドギャップの大きい高抵抗のノンドープまたはp型半導体層によって被覆することが有効である。バンドギャップの大きい半導体層の被覆により水平方向での発光層内へのキャリアの閉じ込め効果が期待できる。さらに被覆時の高温での半導体結晶成長によって発光層側壁の欠陥を減少させる効果も期待できる。またp型半導体層による被覆は、発光層部分が実質的にn型であるため、側壁の界面に空乏層が形成され高抵抗化することにより、キャリアが側壁に移動する確率を著しく低減できる。AlGaInN系またはAlGaInP系の半導体発光素子チップをこのように構成することにより、発光層の最大幅が5μm以下の微細な半導体発光素子チップであっても、高い発光効率を得ることができる。 The chip size of the semiconductor light emitting device chip is selected according to need, but is generally selected to be 20 μm x 20 μm or less, typically 10 μm x 10 μm or less, most typically 5 μm x 5 μm or less, and generally is 0.1 μm (100 nm)×0.1 μm (100 nm) or more, or 0.5 μm (500 nm)×0.5 μm (500 nm) or more. Further, the thickness of the semiconductor light emitting element chip is also selected as required, but is generally 10 μm or less, preferably 5 μm or less. The semiconductor light emitting device chip is preferably obtained by separating the substrate from the semiconductor layer after crystal growth of the semiconductor layer constituting the semiconductor light emitting device on the substrate, and preferably has a thickness of, for example, 10 μm or less. . The semiconductor light emitting device chip preferably has rotational symmetry about an axis perpendicular to the chip surface, and is, for example, circular, square, regular hexagonal, regular octagonal, etc. In this case, the semiconductor light emitting device chip as a whole has a rotational symmetry with respect to an axis perpendicular to the chip surface. Examples include a cylinder, a regular square prism, a regular hexagonal prism, a regular octagonal prism, etc., but are not limited to these. In particular, when the semiconductor light emitting element chip has a cylindrical shape, the semiconductor light emitting element chip preferably has a diameter of 10 μm or less and a thickness of 10 μm or less. In addition, the number of p-side electrodes and n-side electrodes of a semiconductor light emitting element chip is typically one each, and the electrode size is equal to or smaller than the chip size, but which one of the p-side electrode and n-side electrode One or both of the electrodes may be formed of a plurality of electrodes having a size smaller than the chip size. In addition, particularly when the semiconductor light emitting element chip is an AlGaInN-based or AlGaInP-based semiconductor light-emitting element chip, preferably the maximum width of the light emitting layer of the semiconductor light-emitting element chip is 5 μm or less, and in the case of an AlGaInN-based semiconductor light-emitting element chip, The surroundings of this light-emitting layer are covered with an AlGaInN-based semiconductor layer that has a larger band gap and higher specific resistance than this light-emitting layer. It is covered with an AlGaInP-based semiconductor layer with a large gap and high specific resistance. These semiconductor layers may be p-type, non-doped, or n-type. The light emitting layer may be surrounded by a p-type semiconductor layer, and an n-type semiconductor layer, or an n-type semiconductor layer and a p-type semiconductor layer may be laminated thereon to form a covering layer. In this case, the n-type semiconductor layer of the covering layer serves as a current blocking layer and reduces leakage current flowing through the covering layer. Furthermore, in order to increase the resistance of the coating layer, it may be doped with a transition metal such as Fe that forms a deep level in the band gap of the semiconductor. Sidewall interfaces created by etching or the like have a high rate of non-radiative recombination. As semiconductor light emitting device chips become smaller, carriers such as electrons more easily reach the side walls of the light emitting layer, where they non-radiatively recombine and reduce light emitting efficiency. Therefore, as semiconductor light emitting element chips are miniaturized, their luminous efficiency decreases. In order to avoid this phenomenon, it is effective to avoid passing the current near the side walls of the light emitting layer. Although several methods can be considered for this purpose, it is effective to cover the sidewalls of the light-emitting layer with a high-resistance non-doped or p-type semiconductor layer having a larger band gap than the light-emitting layer. Covering with a semiconductor layer having a large bandgap can be expected to have an effect of confining carriers in the light emitting layer in the horizontal direction. Furthermore, the effect of reducing defects on the sidewalls of the light-emitting layer can be expected due to semiconductor crystal growth at high temperatures during coating. Further, since the light-emitting layer portion is substantially n-type when covered with a p-type semiconductor layer, a depletion layer is formed at the interface of the sidewall and the resistance becomes high, thereby significantly reducing the probability that carriers will move to the sidewall. By configuring the AlGaInN-based or AlGaInP-based semiconductor light-emitting element chip in this manner, high light-emitting efficiency can be obtained even in a fine semiconductor light-emitting element chip whose maximum width of the light-emitting layer is 5 μm or less.
 基板(あるいは実装基板)は、特に限定されないが、例えば、Si基板、ガラス基板、ガラスエポキシ基板、樹脂フィルム、プリント基板などである。基板は剛体であってもフレキシブルであってもよく、更に透明、半透明、不透明でもよく適宜選択される。 The substrate (or mounting substrate) is not particularly limited, and includes, for example, a Si substrate, a glass substrate, a glass epoxy substrate, a resin film, a printed circuit board, and the like. The substrate may be rigid or flexible, and may be transparent, translucent, or opaque, and may be selected as appropriate.
 下部電極を構成する複数の下部支線部電極の幅、下部支線部電極の間の隙間の幅などは必要に応じて選択されるが、例えば、各下部支線部電極の幅は5~100μm、下部支線部電極の間の隙間の幅は1~5μmである。下部支線部電極の数については後述する。典型的には、これらの複数の下部支線部電極は互いに平行に設けられる。各下部支線部電極の上面によりチップ結合部が構成される。このチップ結合部は半導体発光素子チップを結合させる領域である。複数の下部支線部電極のうちの少なくとも一つの下部支線部電極のチップ結合部には少なくとも一つの半導体発光素子チップが結合しているが、一つの半導体発光素子チップも結合していないチップ結合部が含まれることもある。半導体発光素子チップはチップ結合部のどの位置に結合してもよいが、結合させる位置を予め決めておきたい場合は、チップ結合部の領域に強磁性体領域が設けられる。こうすることで、半導体発光素子チップのp側電極およびn側電極のうちの一方が磁力によりこの強磁性体領域に向かって引き寄せられて結合しやすくなる。例えば、下部支線部電極のチップ結合部の中心線上に一列にかつ等間隔に半導体発光素子チップを結合させる場合は、その結合させたい位置にそれぞれ強磁性体領域が形成される。これらの強磁性体領域は、基板と下部支線部電極との間に設けてもよいし、チップ結合部上に設けてもよい。強磁性体領域の面積は、典型的には、半導体発光素子チップのp側電極およびn側電極のうちの一方の面積以下に選ばれる。また、強磁性体領域の形状は、典型的には、半導体発光素子チップのp側電極およびn側電極のうちの一方の形状と同様に選ばれるが、これに限定されるものではない。強磁性体領域は、典型的には、軟磁性体または硬磁性体からなる。硬磁性体は、磁場を取り去っても保磁力を有する性質を有し、永久磁石として用いられる。硬磁性体は、例えば、ネオジム鉄ボロン(Nd-Fe-B)磁石、コバルト白金(Co-Pt)系磁石(Co-Pt磁石、Co-Cr-Pt磁石など)、サマリウムコバルト(Sm-Co)磁石、サマリウム鉄窒素(Sm-Fe-N)磁石、フェライト磁石、アルニコ磁石などであるが、これに限定されるものではない。 The width of the plurality of lower branch line electrodes constituting the lower electrode, the width of the gap between the lower branch line electrodes, etc. are selected as necessary. For example, the width of each lower branch line electrode is 5 to 100 μm, The width of the gap between the branch electrodes is 1 to 5 μm. The number of lower branch line electrodes will be described later. Typically, these plurality of lower branch electrodes are provided in parallel to each other. The upper surface of each lower branch electrode constitutes a tip coupling section. This chip bonding portion is a region where semiconductor light emitting device chips are bonded. At least one semiconductor light emitting element chip is coupled to the chip coupling part of at least one lower branch line part electrode of the plurality of lower branch line part electrodes, but a chip coupling part to which not a single semiconductor light emitting element chip is coupled. may also be included. The semiconductor light emitting element chip may be bonded to any position in the chip bonding portion, but if the bonding position is desired to be determined in advance, a ferromagnetic region is provided in the area of the chip bonding portion. By doing so, one of the p-side electrode and the n-side electrode of the semiconductor light emitting element chip is attracted toward this ferromagnetic region by magnetic force, and is easily coupled to the ferromagnetic region. For example, when semiconductor light emitting element chips are coupled in a row and at equal intervals on the center line of the chip coupling portion of the lower branch electrode, ferromagnetic regions are formed at the desired bonding positions. These ferromagnetic regions may be provided between the substrate and the lower branch electrode, or may be provided on the chip coupling portion. The area of the ferromagnetic region is typically selected to be less than or equal to the area of one of the p-side electrode and n-side electrode of the semiconductor light emitting element chip. Further, the shape of the ferromagnetic region is typically selected to be similar to the shape of one of the p-side electrode and n-side electrode of the semiconductor light emitting element chip, but is not limited thereto. The ferromagnetic region typically consists of a soft magnetic material or a hard magnetic material. Hard magnetic materials have a property of having coercive force even when a magnetic field is removed, and are used as permanent magnets. Examples of hard magnetic materials include neodymium iron boron (Nd-Fe-B) magnets, cobalt platinum (Co-Pt) magnets (Co-Pt magnets, Co-Cr-Pt magnets, etc.), and samarium cobalt (Sm-Co). magnets, samarium iron nitrogen (Sm-Fe-N) magnets, ferrite magnets, alnico magnets, etc., but are not limited thereto.
 半導体発光素子チップの上層の上部電極を構成する複数の上部支線部電極の幅、下部支線部電極の間の隙間の幅などは下部電極を構成する複数の下部支線部電極と同様に必要に応じて選択されるが、例えば、各上部支線部電極の幅は5~100μm、上部支線部電極の間の隙間の幅は1~5μmである。上部支線部電極の数については後述する。典型的には、これらの上部支線部電極は互いに平行に設けられ、これらの上部支線部電極は下部支線部電極に対して直角に設けられるが、これに限定されるものではない。半導体発光素子チップからの光を下部支線部電極を通して外部に取り出す場合、これらの上部支線部電極のうちのチップ結合部に跨がる部分は透明電極材料により構成される。 The width of the plurality of upper branch line part electrodes constituting the upper layer of the upper layer of the semiconductor light emitting element chip, the width of the gap between the lower branch line part electrodes, etc., are determined as necessary in the same way as the plurality of lower branch line part electrodes constituting the lower electrode. For example, the width of each upper branch line electrode is 5 to 100 μm, and the width of the gap between the upper branch line electrodes is 1 to 5 μm. The number of upper branch line electrodes will be described later. Typically, these upper branch line electrodes are provided parallel to each other, and these upper branch line part electrodes are provided at right angles to the lower branch line electrodes, but are not limited thereto. When light from the semiconductor light emitting element chip is extracted to the outside through the lower branch line electrodes, the portions of these upper branch line electrodes that straddle the chip coupling part are made of a transparent electrode material.
 典型的には、下部電極を構成する複数の下部支線部電極の数をL(L≧4)、上部電極を構成する複数の上部支線部電極の数をU(U≧4)としたとき、L×U≧16を満足するように選ばれる。例えば、半導体発光素子チップ集積装置に含まれる回路ユニットの数が数十万個程度である場合、半導体発光素子チップ集積装置の製造歩留まりを確保するためには、一つの回路ユニットに使用するチップ数を5個前後として、不良チップ数が3つの場合でも修理によって回路ユニットを生かせる設計が必要である。L、Uのどちらの数も3以下の場合、一つの回路ユニット内の全ての下部支線部電極に不良の半導体発光素子チップが1つ以上含まれる可能性がある。その場合、下部支線部電極の切断による修理が困難となる。そのため、確実に歩留まりを確保するためには、下部支線部電極および上部支線部電極のいずれかの数は4つ以上が望ましい。また、下部支線部電極および上部支線部電極のうち数が多い方を切断する方が良品チップを生かせる可能性が高い。そのため、良品チップを生かせる確率を上げるには、下部支線部電極および上部支線部電極とも数は4以上である方がよい。一つの回路ユニットに使用されるチップ数が必要以上に多い場合は、却って不良チップが含まれる割合を増大させる。L=4、U=4の場合、下部支線部電極と上部支線部電極とが交差する領域の数は4×4=16であるが、チップ数は4~5個前後が望ましく、交差領域一つ当たりのチップ数は1個が理想的である。 Typically, when the number of the plurality of lower branch line electrodes forming the lower electrode is L (L≧4) and the number of the plurality of upper branch line electrodes forming the upper electrode is U (U≧4), It is selected to satisfy L×U≧16. For example, when the number of circuit units included in a semiconductor light emitting device chip integrated device is approximately several hundred thousand, in order to ensure the manufacturing yield of the semiconductor light emitting device chip integrated device, the number of chips used in one circuit unit must be It is necessary to create a design in which the number of defective chips is set at around 5 and the circuit unit can be utilized by repair even if the number of defective chips is 3. If both the numbers L and U are 3 or less, there is a possibility that all the lower branch line electrodes in one circuit unit include one or more defective semiconductor light emitting element chips. In that case, repair by cutting the lower branch electrode becomes difficult. Therefore, in order to ensure the yield, it is desirable that the number of either the lower branch line electrode or the upper branch line electrode be four or more. Furthermore, it is more likely that good chips can be utilized by cutting the lower branch line electrode and the upper branch line electrode, whichever is larger in number. Therefore, in order to increase the probability of using good chips, it is preferable that the number of both the lower branch line part electrode and the upper branch line part electrode be 4 or more. If the number of chips used in one circuit unit is larger than necessary, the proportion of defective chips will increase. In the case of L=4 and U=4, the number of areas where the lower branch line electrode and the upper branch line electrode intersect is 4×4=16, but the number of chips is preferably around 4 to 5, and the number of areas where the lower branch line electrode and the upper branch line electrode intersect is The ideal number of chips per chip is one.
 必要に応じて、下部支線部電極の少なくとも一部および/または上部支線部電極の少なくとも一部を融点が350℃以下、典型的には150℃以上の低融点金属から構成することができ、この一部をヒューズとして用いることができる。すなわち、この下部支線部電極あるいは上部支線部電極に通電を行った場合、発熱によりこの低融点金属からなる部分が選択的に溶けることにより下部支線部電極あるいは上部支線部電極が切断される。このような金属は、単体金属としてはIn、Snなどが挙げられ、合金(共晶合金)としてはInSn、InSnAg、AgSn、AgSnなどが挙げられるが、これに限定されるものではない。下部支線部電極または上部支線部電極の全体が融点の高い材料からなる場合は、その材料からなる下部支線部電極または上部支線部電極の一部にレーザービームまたは電子線の照射を行うことにより切断することができる。切断箇所は他に支障の生じない限り、下部支線部電極または上部支線部電極のどの位置であってもよく、どの位置でもヒューズとなり得る。 If necessary, at least a portion of the lower branch electrode and/or at least a portion of the upper branch electrode may be composed of a low melting point metal having a melting point of 350° C. or lower, typically 150° C. or higher; A part can be used as a fuse. That is, when the lower branch line electrode or the upper branch line electrode is energized, the portion made of the low melting point metal is selectively melted due to heat generation, thereby cutting the lower branch line electrode or the upper branch line electrode. Such metals include In, Sn, etc. as single metals, and InSn, InSnAg, AgSn, AgSn, etc. as alloys (eutectic alloys), but are not limited thereto. If the entire lower branch line electrode or upper branch line electrode is made of a material with a high melting point, it can be cut by irradiating a portion of the lower branch line electrode or upper branch line electrode made of that material with a laser beam or electron beam. can do. The cut point may be at any position on the lower branch line electrode or the upper branch line electrode, as long as no other problems occur, and any position can serve as a fuse.
 半導体発光素子チップ集積装置は、必要に応じて、半導体発光素子チップに加えて、上下にp側電極およびn側電極を有し、これらのp側電極およびn側電極のうちの一方が他方に比べてより強く磁場に引き寄せられるように構成された縦型のツェナーダイオードをさらに有し、当該ツェナーダイオードは当該半導体発光素子チップに対して逆バイアスになるように接続される。このツェナーダイオードを下部電極と上部電極との間に逆バイアスが印加されるように接続することにより、何らかの理由により下部電極と上部電極との間にサージ電圧などが印加されても、このツェナーダイオードを通して電流を逃がすことができるため、半導体発光素子チップの静電破壊(ESD)を効果的に防止することができる。典型的には、ツェナーダイオードの混合割合は半導体発光素子チップに対して10分の1以下の割合とされる。 In addition to the semiconductor light emitting element chip, the semiconductor light emitting element chip integrated device has a p-side electrode and an n-side electrode on the upper and lower sides, and one of the p-side electrode and the n-side electrode is connected to the other. The device further includes a vertical Zener diode that is configured to be more strongly attracted to the magnetic field, and the Zener diode is connected so as to be reverse biased with respect to the semiconductor light emitting element chip. By connecting this Zener diode so that a reverse bias is applied between the lower electrode and the upper electrode, even if a surge voltage etc. is applied between the lower electrode and the upper electrode for some reason, this Zener diode Since the current can escape through the semiconductor light emitting element chip, electrostatic discharge damage (ESD) of the semiconductor light emitting element chip can be effectively prevented. Typically, the mixing ratio of Zener diodes is one-tenth or less of the semiconductor light emitting element chip.
 半導体発光素子チップ集積装置は、基本的にはどのようなものであってもよく、半導体発光素子チップの種類に応じて適宜設計される。半導体発光素子チップ集積装置は、一種類の半導体発光素子チップを集積したものだけでなく、二種類以上の半導体発光素子チップを集積したものや蛍光体と組み合わせたものであってもよい。半導体発光素子チップ集積装置は、例えば、発光ダイオード照明装置、発光ダイオードバックライト、発光ダイオードディスプレイなどであるが、これに限定されるものではない。半導体発光素子チップ集積装置の大きさ、平面形状などは、半導体発光素子チップ集積装置の用途、半導体発光素子チップ集積装置に要求される機能などに応じて適宜選択される。 Basically, the semiconductor light emitting element chip integrated device may be of any type, and is designed as appropriate depending on the type of semiconductor light emitting element chip. The semiconductor light emitting element chip integrated device may be one in which not only one type of semiconductor light emitting element chips are integrated, but also one in which two or more types of semiconductor light emitting element chips are integrated, or one in which a phosphor is combined. Examples of the semiconductor light emitting element chip integrated device include, but are not limited to, a light emitting diode lighting device, a light emitting diode backlight, a light emitting diode display, and the like. The size, planar shape, etc. of the semiconductor light emitting element chip integrated device are appropriately selected depending on the application of the semiconductor light emitting element chip integrated device, the functions required of the semiconductor light emitting element chip integrated device, and the like.
 また、この発明は、
 チップ結合部に軟磁性体領域が設けられた基板の当該軟磁性体領域に磁場を印加して磁化させる工程と、
 上記磁場を取り去った後、上記軟磁性体領域の残留磁束が消える前に、上下にp側電極およびn側電極を有し、上記p側電極および上記n側電極のうちの一方が他方に比べてより強く磁場に引き寄せられるように構成された縦型の複数の半導体発光素子チップと液体とを含有する液滴状のインクを上記チップ結合部に供給し、上記インク中の上記半導体発光素子チップを、上記p側電極および上記n側電極のうちの上記一方を上記軟磁性体領域に向けて上記軟磁性体領域上に結合させる工程とを有する半導体発光素子チップ集積装置の製造方法である。
Moreover, this invention
applying a magnetic field to the soft magnetic region of the substrate provided with the soft magnetic region in the chip coupling portion to magnetize the soft magnetic region;
After the magnetic field is removed and before the residual magnetic flux of the soft magnetic region disappears, the soft magnetic region has a p-side electrode and an n-side electrode above and below, and one of the p-side electrode and the n-side electrode is compared to the other. A droplet-shaped ink containing a liquid and a plurality of vertical semiconductor light emitting element chips configured to be more strongly attracted by a magnetic field is supplied to the chip coupling portion, and the semiconductor light emitting element chips in the ink are A method for manufacturing a semiconductor light emitting element chip integrated device, comprising: coupling one of the p-side electrode and the n-side electrode toward the soft magnetic region and onto the soft magnetic region.
 半導体発光素子チップを含むインクが含有する液体は、使用する半導体発光素子チップを分散させることができる限り特に限定されず、極性溶媒であっても無極性溶媒であってもよく、必要に応じて選ばれる。極性溶媒は、極性非プロトン性溶媒であってもプロトン性溶媒であってもよい。あるいは、この液体は、水であっても非水溶媒(水を除く二種類以上の溶媒の混合物、水と水を除く二種類以上の溶媒との混合物を含む)であってもよく、非水溶媒は不活性溶媒であっても活性溶媒であってもよい。 The liquid contained in the ink containing the semiconductor light emitting element chip is not particularly limited as long as it can disperse the semiconductor light emitting element chip used, and may be a polar solvent or a nonpolar solvent, and may be used as necessary. To be elected. The polar solvent may be a polar aprotic solvent or a protic solvent. Alternatively, this liquid may be water or a non-aqueous solvent (including a mixture of two or more solvents excluding water, a mixture of water and two or more solvents excluding water), and a non-aqueous solvent. The solvent may be an inert solvent or an active solvent.
 インク中の半導体発光素子チップの濃度は必要に応じて選ばれるが、典型的には、半導体発光素子チップが液体中に100ピコリットルの体積中に10~10000個存在するように分散されている。インク中の半導体発光素子チップの体積分率は必要に応じて選ばれるが、典型的には30%以下である。インクの粘度は必要に応じて選ばれるが、例えば0.001~100Pa・sの範囲である。 The concentration of semiconductor light emitting device chips in the ink is selected as necessary, but typically, semiconductor light emitting device chips are dispersed in the liquid so that 10 to 10,000 semiconductor light emitting device chips exist in a volume of 100 picoliters. . The volume fraction of semiconductor light emitting element chips in the ink is selected as required, but is typically 30% or less. The viscosity of the ink is selected as required, and is, for example, in the range of 0.001 to 100 Pa·s.
 基板のチップ結合部にインクを供給する方法は特に限定されず、必要に応じて選ばれる。チップ結合部に供給される液滴状のインクの形態はインクのチップ結合部に対する濡れ性などにより変化し、曲率が大きく球状の液滴から曲率が小さく平坦な液滴まで様々な形態を取りうる。典型的には、ノズルの先端からインクをチップ結合部に吐出する。好適には、インクジェットプリンティング方式によりノズルの先端からインクをチップ結合部に吐出する。この場合、吐出するインクの量は、一つのチップ結合部当たり複数(例えば2~100個、場合によってはそれ以上)の半導体発光素子チップを含む量であればよく、典型的には10ピコリットル以上であるが、必要に応じて選ばれる。基板のチップ結合部に供給されたインクは、加熱などによる強制乾燥または自然乾燥により液体成分が除去される。供給されたインク中に含まれていた半導体発光素子チップは、後述する方法により、p側電極およびn側電極のうちの一方をチップ結合部に向けてチップ結合部と接触する。本方式では液滴中に複数個の半導体発光素子チップを含み、その個数に柔軟性を持たせることによりインクジェットプリンティング方式などの適用性を向上させ、更にチップ結合部の面積を半導体発光素子チップの面積よりも大きく設定し、複数の半導体発光素子チップとチップ結合部との結合位置にかなりの自由度を与えてチップ結合位置の制御の煩雑さを解消することにより製造工程を飛躍的に簡単化させることができる。また、チップ結合部は基板内に占める割合の少ない限定された領域であるが、複数の半導体発光素子チップは、吐出された液滴の広がりの範囲内に留まり基板全体に散乱されることは無く、効率的にチップ結合部との結合を行うことができる。 The method of supplying ink to the chip bonding portion of the substrate is not particularly limited and may be selected as necessary. The form of the droplet-shaped ink supplied to the chip joint varies depending on the wettability of the ink to the chip joint, and can take various forms, from spherical droplets with a large curvature to flat droplets with a small curvature. . Typically, ink is ejected from the tip of the nozzle onto the tip joint. Preferably, the inkjet printing method is used to eject ink from the tip of the nozzle to the chip joint portion. In this case, the amount of ink to be ejected may be an amount that includes a plurality of semiconductor light emitting device chips (for example, 2 to 100, or more in some cases) per one chip joint, and is typically 10 picoliters. These are the above, but they are selected according to need. The liquid component of the ink supplied to the chip bonding portion of the substrate is removed by forced drying by heating or by natural drying. The semiconductor light emitting element chip contained in the supplied ink is brought into contact with the chip bonding portion with one of the p-side electrode and the n-side electrode directed toward the chip bonding portion, by a method described later. In this method, a droplet contains multiple semiconductor light emitting device chips, and by making the number flexible, it improves the applicability of inkjet printing methods, etc., and furthermore, the area of the chip bonding part can be reduced to the size of the semiconductor light emitting device chip. The manufacturing process is dramatically simplified by setting the size larger than the area and giving a considerable degree of freedom in the bonding position between multiple semiconductor light emitting device chips and the chip bonding part, eliminating the complexity of controlling the chip bonding position. can be done. Furthermore, although the chip bonding area is a limited area that occupies a small proportion of the substrate, the multiple semiconductor light emitting device chips remain within the spread range of the ejected droplets and are not scattered over the entire substrate. , it is possible to efficiently couple with the chip coupling part.
 この半導体発光素子チップ集積装置の製造方法は、上記の半導体発光素子チップ集積装置の製造に適用して好適なものである。 This method for manufacturing a semiconductor light emitting element chip integrated device is suitable for application to manufacturing the above-mentioned semiconductor light emitting element chip integrated device.
 この半導体発光素子チップ集積装置の製造方法の発明においては、上記以外のことは、特にその性質に反しない限り、上記の半導体発光素子チップ集積装置の発明に関連して説明したことが成立する。 In this invention of a method for manufacturing a semiconductor light emitting element chip integrated device, the explanations regarding the invention of the above semiconductor light emitting element chip integrated device hold true unless otherwise specified.
 この発明によれば、下部電極が下部幹線部電極と当該下部幹線部電極から分岐した複数の下部支線部電極とを有するとともに、上部電極が上部幹線部電極と当該上部幹線部電極から分岐し、複数の下部支線部電極と交差するようにチップ結合部に跨がる複数の上部支線部電極とを有することにより、いずれかの上部支線部電極が接続された半導体発光素子チップに不良があった場合、その上部支線部電極あるいはこの半導体発光素子チップがチップ結合部に結合した下部支線部電極だけを切断すれば修理を行うことができるため、その半導体発光素子チップが無駄になるだけで済み、無駄になる半導体発光素子チップの数の大幅な低減を図ることができる。また、チップ結合部に複数の軟磁性体領域が設けられた基板のこの軟磁性体領域に磁場を印加して磁化させ磁場を取り去った後、軟磁性体領域の残留磁束が消える前に、縦型の複数の半導体発光素子チップと液体とを含有する液滴状のインクをチップ結合部に供給することにより、残留磁束の効果により、インク中の半導体発光素子チップを、p側電極およびn側電極のうちの一方を確実に軟磁性体領域に結合させることができるため、半導体発光素子チップ集積装置を容易に製造することができる。そして、例えば、チップ結合部を二次元アレイ状に設けることにより、大面積あるいは高集積密度の半導体発光素子チップ集積装置、例えば、発光ダイオード照明装置、大面積の発光ダイオードバックライト、大画面の発光ダイオードディスプレイなどを容易に実現することができる。 According to this invention, the lower electrode has a lower trunk electrode and a plurality of lower branch electrodes branched from the lower trunk electrode, and the upper electrode branches from the upper trunk electrode and the upper trunk electrode, A semiconductor light-emitting element chip to which any of the upper branch electrodes was connected was defective due to the plurality of upper branch line electrodes spanning the chip coupling part so as to intersect with the plurality of lower branch line electrodes. In this case, repair can be carried out by cutting only the upper branch line electrode or the lower branch line electrode where this semiconductor light emitting element chip is connected to the chip coupling part, so the semiconductor light emitting element chip is only wasted. The number of wasted semiconductor light emitting device chips can be significantly reduced. In addition, after applying a magnetic field to the soft magnetic material region of a substrate provided with a plurality of soft magnetic material regions in the chip coupling part to magnetize it and removing the magnetic field, before the residual magnetic flux in the soft magnetic material region disappears, the vertical By supplying a droplet-shaped ink containing a plurality of semiconductor light emitting device chips and a liquid to the chip bonding part, the semiconductor light emitting device chips in the ink are connected to the p-side electrode and the n-side electrode due to the effect of residual magnetic flux. Since one of the electrodes can be reliably coupled to the soft magnetic region, a semiconductor light emitting element chip integrated device can be easily manufactured. For example, by providing chip bonding parts in a two-dimensional array, it is possible to produce large-area or high-integration density semiconductor light-emitting element chip integrated devices, such as light-emitting diode lighting devices, large-area light-emitting diode backlights, and large-screen light emitting devices. Diode displays and the like can be easily realized.
この発明の第1の実施の形態によるマイクロLEDチップ集積装置に用いられる縦型マイクロLEDチップの一例を示す平面図である。FIG. 2 is a plan view showing an example of a vertical micro LED chip used in the micro LED chip integration device according to the first embodiment of the present invention. この発明の第1の実施の形態によるマイクロLEDチップ集積装置に用いられる縦型マイクロLEDチップの一例を示す縦断面図である。FIG. 1 is a vertical cross-sectional view showing an example of a vertical micro LED chip used in the micro LED chip integration device according to the first embodiment of the present invention. この発明の第1の実施の形態によるマイクロLEDチップ集積装置の製造に用いられるインクを示す略線図である。FIG. 2 is a schematic diagram showing ink used in manufacturing the micro LED chip integrated device according to the first embodiment of the present invention. この発明の第1の実施の形態によるマイクロLEDチップ集積装置の製造に用いられるインク吐出装置を示す略線図である。1 is a schematic diagram showing an ink ejection device used for manufacturing a micro LED chip integrated device according to a first embodiment of the present invention. この発明の第1の実施の形態によるマイクロLEDチップ集積装置の製造に用いられる実装基板を示す平面図である。FIG. 1 is a plan view showing a mounting board used for manufacturing a micro LED chip integrated device according to a first embodiment of the present invention. この発明の第1の実施の形態によるマイクロLEDチップ集積装置の製造に用いられる実装基板を示す断面図である。1 is a cross-sectional view showing a mounting board used for manufacturing a micro LED chip integrated device according to a first embodiment of the present invention. この発明の第1の実施の形態によるマイクロLEDチップ集積装置の製造方法を説明するための平面図である。1 is a plan view for explaining a method of manufacturing a micro LED chip integrated device according to a first embodiment of the present invention; FIG. この発明の第1の実施の形態によるマイクロLEDチップ集積装置の製造方法を説明するための断面図である。FIG. 1 is a cross-sectional view for explaining a method of manufacturing a micro LED chip integrated device according to a first embodiment of the present invention. この発明の第1の実施の形態によるマイクロLEDチップ集積装置の製造方法を説明するための平面図である。1 is a plan view for explaining a method of manufacturing a micro LED chip integrated device according to a first embodiment of the present invention; FIG. この発明の第1の実施の形態によるマイクロLEDチップ集積装置の製造方法を説明するための断面図である。FIG. 1 is a cross-sectional view for explaining a method of manufacturing a micro LED chip integrated device according to a first embodiment of the present invention. この発明の第1の実施の形態によるマイクロLEDチップ集積装置の製造方法を説明するための断面図である。FIG. 1 is a cross-sectional view for explaining a method of manufacturing a micro LED chip integrated device according to a first embodiment of the present invention. この発明の第1の実施の形態によるマイクロLEDチップ集積装置の製造方法を説明するための平面図である。1 is a plan view for explaining a method of manufacturing a micro LED chip integrated device according to a first embodiment of the present invention; FIG. この発明の第1の実施の形態によるマイクロLEDチップ集積装置の製造方法を説明するための断面図である。FIG. 1 is a cross-sectional view for explaining a method of manufacturing a micro LED chip integrated device according to a first embodiment of the present invention. この発明の第1の実施の形態によるマイクロLEDチップ集積装置の製造方法により製造されたマイクロLEDチップ集積装置の修理方法を説明するための平面図である。FIG. 3 is a plan view for explaining a method for repairing a micro LED chip integrated device manufactured by the method for manufacturing a micro LED chip integrated device according to the first embodiment of the present invention. この発明の第1の実施の形態によるマイクロLEDチップ集積装置の製造方法により製造されたマイクロLEDチップ集積装置の修理方法を説明するための断面図である。FIG. 3 is a cross-sectional view for explaining a method for repairing a micro LED chip integrated device manufactured by the method for manufacturing a micro LED chip integrated device according to the first embodiment of the present invention. この発明の第1の実施の形態によるマイクロLEDチップ集積装置の製造方法により製造されたマイクロLEDチップ集積装置の修理方法を説明するための平面図である。FIG. 3 is a plan view for explaining a method for repairing a micro LED chip integrated device manufactured by the method for manufacturing a micro LED chip integrated device according to the first embodiment of the present invention. この発明の第1の実施の形態によるマイクロLEDチップ集積装置の製造方法により製造されたマイクロLEDチップ集積装置の修理方法を説明するための断面図である。FIG. 3 is a cross-sectional view for explaining a method for repairing a micro LED chip integrated device manufactured by the method for manufacturing a micro LED chip integrated device according to the first embodiment of the present invention. この発明の第2の実施の形態によるマイクロLEDチップ集積装置の製造方法を説明するための平面図である。FIG. 7 is a plan view for explaining a method of manufacturing a micro LED chip integrated device according to a second embodiment of the present invention. この発明の第2の実施の形態によるマイクロLEDチップ集積装置の製造方法を説明するための断面図である。FIG. 7 is a cross-sectional view for explaining a method of manufacturing a micro LED chip integrated device according to a second embodiment of the present invention. この発明の第2の実施の形態によるマイクロLEDチップ集積装置の製造方法を説明するための断面図である。FIG. 7 is a cross-sectional view for explaining a method of manufacturing a micro LED chip integrated device according to a second embodiment of the present invention. この発明の第2の実施の形態によるマイクロLEDチップ集積装置の製造方法を説明するための断面図である。FIG. 7 is a cross-sectional view for explaining a method of manufacturing a micro LED chip integrated device according to a second embodiment of the present invention. この発明の第2の実施の形態によるマイクロLEDチップ集積装置の製造方法を説明するための断面図である。FIG. 7 is a cross-sectional view for explaining a method of manufacturing a micro LED chip integrated device according to a second embodiment of the present invention. この発明の第2の実施の形態によるマイクロLEDチップ集積装置の製造方法を説明するための断面図である。FIG. 7 is a cross-sectional view for explaining a method of manufacturing a micro LED chip integrated device according to a second embodiment of the present invention. この発明の第2の実施の形態によるマイクロLEDチップ集積装置の製造方法を説明するための断面図である。FIG. 7 is a cross-sectional view for explaining a method of manufacturing a micro LED chip integrated device according to a second embodiment of the present invention. この発明の第2の実施の形態によるマイクロLEDチップ集積装置の製造方法を説明するための平面図である。FIG. 7 is a plan view for explaining a method of manufacturing a micro LED chip integrated device according to a second embodiment of the present invention. この発明の第2の実施の形態によるマイクロLEDチップ集積装置の製造方法を説明するための平面図である。FIG. 7 is a plan view for explaining a method of manufacturing a micro LED chip integrated device according to a second embodiment of the present invention. この発明の第3の実施の形態によるマイクロLEDチップ集積装置の製造方法を説明するための平面図である。FIG. 7 is a plan view for explaining a method of manufacturing a micro LED chip integrated device according to a third embodiment of the present invention. この発明の第3の実施の形態によるマイクロLEDチップ集積装置の製造方法を説明するための平面図である。FIG. 7 is a plan view for explaining a method of manufacturing a micro LED chip integrated device according to a third embodiment of the present invention.
 以下、発明を実施するための形態(以下「実施の形態」と言う)について説明する。 Hereinafter, modes for carrying out the invention (hereinafter referred to as "embodiments") will be described.
〈第1の実施の形態〉
 第1の実施の形態によるマイクロLEDチップ集積装置は実装基板上に縦型マイクロLEDチップを多数実装することにより製造するが、最初にまず、上下にp側電極およびn側電極を有し、n側電極がp側電極に比べてより強く磁場に引き寄せられるように構成された縦型マイクロLEDチップ、この縦型マイクロLEDチップを含有するインク、このインクの吐出に用いるインク吐出装置および実装基板について説明する。
<First embodiment>
The micro LED chip integrated device according to the first embodiment is manufactured by mounting a large number of vertical micro LED chips on a mounting board. About a vertical micro LED chip configured such that the side electrode is attracted to a magnetic field more strongly than the p-side electrode, an ink containing this vertical micro LED chip, an ink ejection device used for ejecting this ink, and a mounting board explain.
[マイクロLEDチップ集積装置の製造方法]
(1)縦型マイクロLEDチップ
 この縦型マイクロLEDチップの一例を図1Aおよび図1Bに示す。図1Aは平面図、図1Bは縦断面図である。この縦型マイクロLEDチップ40は全体として円柱状の形状を有する。図1Aおよび図1Bに示すように、この縦型マイクロLEDチップ40においては、n型GaN層41、障壁層としてのInGa1-x N層と井戸層としてのInGa1-y N層とが交互に積層されたInGa1-x N/InGa1-y N多重量子井戸(MQW)構造(x<y、0≦x<1、0≦y<1)を有する発光層42およびp型GaN層43が順次積層されている。これらのn型GaN層41、発光層42およびp型GaN層43はそれぞれ円形である。n型GaN層41の上部の直径は下部の直径に比べて小さくなっている。発光層42およびp型GaN層43の直径はn型GaN層41の上部の直径と同一である。これらのn型GaN層41の上部、発光層42およびp型GaN層43の直径は5μm以下である。これらのn型GaN層41の上部、発光層42およびp型GaN層43の外周を被覆するように比抵抗の高いp型またはノンドープのGaN層44が設けられている。GaN層44の外周面の直径はn型GaN層41の下部の直径と同一である。p型GaN層43上にITOからなるp側電極45が形成され、n型GaN層41上にn側電極46が形成されている。p側電極45は円形であり、ここでは一例としてp型GaN層43の全面に形成されている。n側電極46はn型GaN層41の全面に設けられている。n側電極46は軟磁性体としてNiを含み、例えば、Ti/Al/Ti/Ni/Ti/Au膜などの多重積層膜からなる。n側電極46上には低融点金属としてのSn膜47が設けられている。Sn膜47の厚さは、例えば0.5μmである。n型GaN層41、発光層42およびp型GaN層43の合計の厚さは例えば1~3μmである。発光層42を構成するInGa1-x N/InGa1-y N MQW構造のIn組成比x、yは、縦型マイクロLEDチップ40の発光波長に応じて選ばれる。
[Method for manufacturing micro LED chip integrated device]
(1) Vertical micro LED chip An example of this vertical micro LED chip is shown in FIGS. 1A and 1B. FIG. 1A is a plan view, and FIG. 1B is a longitudinal cross-sectional view. This vertical micro LED chip 40 has a cylindrical shape as a whole. As shown in FIGS. 1A and 1B, this vertical micro LED chip 40 includes an n-type GaN layer 41, an In x Ga 1-x N layer as a barrier layer, and an In y Ga 1-y N layer as a well layer. A light emitting device having an In x Ga 1-x N/In y Ga 1-y N multiple quantum well (MQW) structure (x<y, 0≦x<1, 0≦y<1) in which layers are stacked alternately. A layer 42 and a p-type GaN layer 43 are sequentially laminated. These n-type GaN layer 41, light-emitting layer 42, and p-type GaN layer 43 are each circular. The diameter of the upper part of the n-type GaN layer 41 is smaller than the diameter of the lower part. The diameters of the light emitting layer 42 and the p-type GaN layer 43 are the same as the diameter of the upper part of the n-type GaN layer 41. The diameters of the upper part of the n-type GaN layer 41, the light-emitting layer 42, and the p-type GaN layer 43 are 5 μm or less. A p-type or non-doped GaN layer 44 having a high specific resistance is provided so as to cover the upper part of the n-type GaN layer 41 and the outer periphery of the light-emitting layer 42 and the p-type GaN layer 43. The diameter of the outer peripheral surface of the GaN layer 44 is the same as the diameter of the lower part of the n-type GaN layer 41. A p-side electrode 45 made of ITO is formed on the p-type GaN layer 43, and an n-side electrode 46 is formed on the n-type GaN layer 41. The p-side electrode 45 is circular, and is formed on the entire surface of the p-type GaN layer 43 as an example here. The n-side electrode 46 is provided over the entire surface of the n-type GaN layer 41. The n-side electrode 46 contains Ni as a soft magnetic material, and is made of, for example, a multilayer film such as a Ti/Al/Ti/Ni/Ti/Au film. A Sn film 47 as a low melting point metal is provided on the n-side electrode 46. The thickness of the Sn film 47 is, for example, 0.5 μm. The total thickness of the n-type GaN layer 41, the light emitting layer 42, and the p-type GaN layer 43 is, for example, 1 to 3 μm. The In composition ratios x and y of the In x Ga 1-x N/In y Ga 1-y N MQW structure constituting the light emitting layer 42 are selected according to the emission wavelength of the vertical micro LED chip 40 .
 この縦型マイクロLEDチップ40は従来公知の方法によって容易に製造することができる。 This vertical micro LED chip 40 can be easily manufactured by a conventionally known method.
(2)インク
 図2に示すように、容器100中において縦型マイクロLEDチップ40を液体50に分散させてインク200を作製する。インク200には、必要に応じて縦型マイクロLEDチップ40に加えてフィラーや界面活性剤などを含有させる。縦型マイクロLEDチップ40のサイズが上述のように微小であるとインク200中の分散性が十分に高く、インク吐出装置の吐出ノズルからの吐出も容易に行うことができる。
(2) Ink As shown in FIG. 2, ink 200 is prepared by dispersing vertical micro LED chips 40 in liquid 50 in container 100. The ink 200 contains a filler, a surfactant, and the like in addition to the vertical micro LED chip 40 as necessary. When the size of the vertical micro LED chip 40 is small as described above, the dispersibility in the ink 200 is sufficiently high, and the ink can be easily ejected from the ejection nozzle of the ink ejection device.
(3)インク吐出装置
 図3はインク吐出装置300を示す。
(3) Ink discharge device FIG. 3 shows an ink discharge device 300.
 図3に示すように、インク吐出装置300は、インクジェットプリントヘッド301を有する。インクジェットプリントヘッド301は内部にインク室302を有し、上部にインク供給部303を有する。インクジェットプリントヘッド301の内部にはさらに、インク室302の上部側面とインク供給部303の底面に設けられた管部303aとを連結する流路305と、インク室302の下部側面に連結された流路306とを有する。インク供給部303の管部303aの途中には制御バルブ307が設けられている。インク室302の下方には吐出ノズル308が設けられている。吐出ノズル308の直径は必要に応じて選ばれるが、例えば10~50μmである。インク室302の上には、一対の電極間に圧電体を挟んだ構造のピエゾアクチュエーター309が設けられている。流路306は、インク室302内のインク200を外部に排出したり、インク供給部303にインクを戻して循環させることにより吐出ノズル308の詰まりを防止したり、インク200の攪拌機能を持たせたりするためのものである。 As shown in FIG. 3, the ink ejection device 300 has an inkjet print head 301. The inkjet print head 301 has an ink chamber 302 inside and an ink supply section 303 at the top. The inside of the inkjet print head 301 further includes a flow path 305 that connects the upper side of the ink chamber 302 and a tube section 303a provided at the bottom of the ink supply section 303, and a flow path connected to the lower side of the ink chamber 302. 306. A control valve 307 is provided in the middle of the pipe section 303a of the ink supply section 303. A discharge nozzle 308 is provided below the ink chamber 302 . The diameter of the discharge nozzle 308 is selected as required, and is, for example, 10 to 50 μm. A piezo actuator 309 is provided above the ink chamber 302 and has a structure in which a piezoelectric body is sandwiched between a pair of electrodes. The flow path 306 has a function of discharging the ink 200 in the ink chamber 302 to the outside, returning the ink to the ink supply section 303 and circulating it to prevent clogging of the ejection nozzle 308, and having a function of stirring the ink 200. It is for the purpose of
 このインク吐出装置300においては、制御バルブ307を開いた状態でインク供給部303にインク200が供給される。こうしてインク供給部303に供給されたインク200は、管部303aおよび流路305を通ってインク室302に供給される。インク200は、流路305、インク室302および流路306が満タンになるまで供給され、その後、制御バルブ307が閉められる。 In this ink ejection device 300, ink 200 is supplied to the ink supply section 303 with the control valve 307 open. The ink 200 thus supplied to the ink supply section 303 is supplied to the ink chamber 302 through the pipe section 303a and the flow path 305. Ink 200 is supplied until channel 305, ink chamber 302, and channel 306 are filled, and then control valve 307 is closed.
 このインク吐出装置300はさらに、このインク吐出装置300の吐出ノズル308から水平方向に少しずれた位置に磁場印加装置311を有する。インク200の吐出を行う後述の実装基板400は、インクジェットプリントヘッド301と磁場印加装置311との間の高さの位置を水平方向に移動するようになっている。 This ink ejection device 300 further includes a magnetic field application device 311 at a position slightly shifted from the ejection nozzle 308 of this ink ejection device 300 in the horizontal direction. A mounting board 400, which will be described later and which discharges ink 200, is configured to move horizontally at a height between an inkjet print head 301 and a magnetic field application device 311.
(4)実装基板
 図4Aおよび図4BはこのマイクロLEDチップ集積装置の製造に用いられる実装基板400を示す。ここで、図4Aは平面図、図4Bは下部支線部電極とその近傍の下部幹線部電極とを横断する断面図である。図4Aおよび図4Bに示すように、基板410の一方の主面に下部電極420が設けられている。図4Aおよび図4Bには、電気的にオン/オフ制御が可能な1回路ユニットに相当する領域を一点鎖線で示す。この場合、下部電極420は、一方向に延在する幅広の下部幹線部電極4201と、この下部幹線部電極4201からこの下部幹線部電極4201と直交する方向に分岐した、この下部幹線部電極4201より幅狭の複数の下部幹線部電極4202と、この下部幹線部電極4202と接続され、この下部幹線部電極4202と直交する方向、従って下部幹線部電極4201と平行な方向に延在する複数の下部支線部電極4203とからなる。下部支線部電極4203の数LはL≧4に選ばれる。図4Aにおいては一例としてL=5の場合が示されている。基板410は剛性を有するものであってもフレキシブルなものであってもよく、また透明であっても不透明であってもよく、必要に応じて選ばれる。基板410は、例えば、Si基板、ガラス基板、ガラスエポキシ基板などのほか、樹脂フィルムなどであってもよい。下部電極420は、例えば、基板410の全面にスパッタリング法や真空蒸着法などにより非磁性の金属膜を形成した後、この金属膜をリソグラフィーおよびエッチングにより所定形状にパターニングすることにより形成することができる。金属膜としては、非磁性の金属からなるもの、例えば、Ti/Al/Ti/Au/Ti積層膜が用いられるが、Cu(あるいはCu合金)/Au/Ti積層膜を用いてもよい。Ti/Al/Ti/Au/Ti積層膜を構成する膜の厚さは、例えば、下から順に5~10nm、300~1000nm、50nm、5~100nm、50nmである。下部支線部電極4203の上面によりチップ結合部421が構成されている。下部支線部電極4203の幅、間隔などは必要に応じて選択される。
(4) Mounting board FIGS. 4A and 4B show a mounting board 400 used for manufacturing this micro LED chip integrated device. Here, FIG. 4A is a plan view, and FIG. 4B is a sectional view crossing the lower branch electrode and the lower trunk electrode in the vicinity thereof. As shown in FIGS. 4A and 4B, a lower electrode 420 is provided on one main surface of the substrate 410. In FIGS. 4A and 4B, a region corresponding to one circuit unit that can be electrically controlled on/off is indicated by a chain line. In this case, the lower electrode 420 includes a wide lower trunk electrode 4201 extending in one direction, and a lower trunk electrode 4201 branching from the lower trunk electrode 4201 in a direction perpendicular to the lower trunk electrode 4201. A plurality of narrower lower trunk electrodes 4202 and a plurality of lower trunk electrodes 4202 connected to the lower trunk electrode 4202 and extending in a direction perpendicular to the lower trunk electrode 4202, and therefore parallel to the lower trunk electrode 4201. It consists of a lower branch line part electrode 4203. The number L of lower branch electrodes 4203 is selected to satisfy L≧4. In FIG. 4A, a case where L=5 is shown as an example. The substrate 410 may be rigid or flexible, and may be transparent or opaque, depending on the needs. The substrate 410 may be, for example, a Si substrate, a glass substrate, a glass epoxy substrate, or a resin film. The lower electrode 420 can be formed, for example, by forming a nonmagnetic metal film on the entire surface of the substrate 410 by sputtering or vacuum evaporation, and then patterning this metal film into a predetermined shape by lithography and etching. . As the metal film, one made of a nonmagnetic metal, for example, a Ti/Al/Ti/Au/Ti laminated film is used, but a Cu (or Cu alloy)/Au/Ti laminated film may also be used. The thicknesses of the films constituting the Ti/Al/Ti/Au/Ti stacked film are, for example, 5 to 10 nm, 300 to 1000 nm, 50 nm, 5 to 100 nm, and 50 nm from the bottom. The upper surface of the lower branch electrode 4203 constitutes a chip coupling portion 421 . The width, spacing, etc. of the lower branch line electrode 4203 are selected as necessary.
(5)マイクロLEDチップ集積装置の製造方法
 以上のことを前提としてこのマイクロLEDチップ集積装置の製造方法について説明する。
(5) Manufacturing method of micro LED chip integrated device Based on the above, the manufacturing method of this micro LED chip integrated device will be explained.
 図3に示すように、インク吐出装置300の吐出ノズル308の下方に実装基板400を水平に配置する。この場合、インク吐出装置300を固定し、実装基板400を図示省略した搬送機構により水平面内で図3中矢印で示す方向に移動させるようにする。ピエゾアクチュエーター309を作動させることにより吐出ノズル308からインク200を実装基板400のチップ結合部421に吐出させる。こうして吐出される一滴のインク200は、一つの回路ユニット内の全ての下部支線部電極4203を含む領域を覆い、かつ十分な個数の縦型マイクロLEDチップ40が含まれるようにする。一滴のインク200に含まれる縦型マイクロLEDチップ40の数は、インク200中の縦型マイクロLEDチップ40の濃度やインク200の吐出回数などによって調整することができる。この状態のインク200の一例を図5Aおよび図5Bに示す。ここで、図5Aは平面図、図5Bは断面図である。この場合、一滴のインク200の体積は例えば1~10ピコリットルである。縦型マイクロLEDチップ40の体積は一般に0.001~0.5ピコリットルである。例えば、縦型マイクロLEDチップ40が直径1μmの円形の形状を有し、厚さが3μmであるとすると、体積は約0.0024ピコリットルである。 As shown in FIG. 3, the mounting board 400 is placed horizontally below the ejection nozzle 308 of the ink ejection device 300. In this case, the ink ejection device 300 is fixed, and the mounting board 400 is moved in the direction shown by the arrow in FIG. 3 within a horizontal plane by a transport mechanism (not shown). By operating the piezo actuator 309, the ink 200 is ejected from the ejection nozzle 308 onto the chip bonding portion 421 of the mounting board 400. One drop of ink 200 ejected in this way covers a region including all the lower branch electrodes 4203 in one circuit unit, and includes a sufficient number of vertical micro LED chips 40. The number of vertical micro LED chips 40 included in one drop of ink 200 can be adjusted by the concentration of vertical micro LED chips 40 in ink 200, the number of times the ink 200 is ejected, and the like. An example of the ink 200 in this state is shown in FIGS. 5A and 5B. Here, FIG. 5A is a plan view, and FIG. 5B is a sectional view. In this case, the volume of one drop of ink 200 is, for example, 1 to 10 picoliters. The volume of the vertical micro LED chip 40 is generally 0.001 to 0.5 picoliters. For example, if the vertical micro LED chip 40 has a circular shape with a diameter of 1 μm and a thickness of 3 μm, the volume is approximately 0.0024 picoliters.
 次に、図3中矢印で示すように、実装基板400を図示省略した搬送機構により所定距離移動させ、インク200が吐出されたチップ結合部421を磁場印加装置311の上方に位置させた後、磁場印加装置311により磁場を印加することにより、インク200に含まれる複数の縦型マイクロLEDチップ40のn側電極46に含まれるNi膜を磁化させる。このため、各縦型マイクロLEDチップ40はインク200中を磁力により下方に引き寄せられ、最終的に各縦型マイクロLEDチップ40はn側電極46側が下になるようにしてチップ結合部421に接触する。振動や擾乱などの外的要因などにより縦型マイクロLEDチップ40が倒れたり位置がずれたりするのを防止するため、磁場印加装置310による磁場の印加は、好適には、インク200を吐出させる前あるいは吐出させた時点あるいはその時点からインク200の液体が蒸発する前に行う。 Next, as shown by the arrow in FIG. 3, the mounting board 400 is moved a predetermined distance by a transport mechanism (not shown), and the chip coupling part 421 on which the ink 200 has been ejected is positioned above the magnetic field application device 311. By applying a magnetic field using the magnetic field applying device 311, the Ni film included in the n-side electrode 46 of the plurality of vertical micro LED chips 40 included in the ink 200 is magnetized. Therefore, each vertical micro LED chip 40 is drawn downward in the ink 200 by the magnetic force, and finally each vertical micro LED chip 40 comes into contact with the chip coupling part 421 with the n-side electrode 46 side facing down. do. In order to prevent the vertical micro LED chip 40 from falling down or shifting its position due to external factors such as vibration or disturbance, the magnetic field is preferably applied by the magnetic field applying device 310 before ejecting the ink 200. Alternatively, it is performed at the time of ejection or before the liquid of the ink 200 evaporates from that time.
 次に、磁力により各縦型マイクロLEDチップ40をチップ結合部421に接触させたまま、ランプなどにより加熱を行うことによりインク200の溶媒を蒸発させ、続いてランプやレーザーなどにより加熱を行うことにより各縦型マイクロLEDチップ40のSn膜47を溶融させる。その後、溶融Snが冷却することにより各縦型マイクロLEDチップ40のn側電極46が下部支線部電極4203のチップ結合部421に電気的および機械的に結合する。 Next, while each vertical micro LED chip 40 is kept in contact with the chip coupling part 421 by magnetic force, the solvent of the ink 200 is evaporated by heating with a lamp or the like, and then heating is performed with a lamp, laser, or the like. The Sn film 47 of each vertical micro LED chip 40 is melted. Thereafter, as the molten Sn cools, the n-side electrode 46 of each vertical micro LED chip 40 is electrically and mechanically coupled to the chip coupling portion 421 of the lower branch electrode 4203.
 同様にして、各回路ユニット内の下部支線部電極4203のチップ結合部421に縦型マイクロLEDチップ40のn側電極46を電気的および機械的に結合させる。この状態の一例を図6Aおよび図6Bに示す。ここで、図6Aは平面図、図6Bは断面図である。図6Aに示すように、チップ結合部421において、縦型マイクロLEDチップ40はランダムに配置している。チップ結合部421の中には、一つの縦型マイクロLEDチップ40も結合していないものが含まれることもあり、図6Aにはそのような例が示されている。 Similarly, the n-side electrode 46 of the vertical micro LED chip 40 is electrically and mechanically coupled to the chip coupling portion 421 of the lower branch electrode 4203 in each circuit unit. An example of this state is shown in FIGS. 6A and 6B. Here, FIG. 6A is a plan view, and FIG. 6B is a sectional view. As shown in FIG. 6A, the vertical micro LED chips 40 are randomly arranged in the chip coupling part 421. The chip coupling part 421 may include one in which not a single vertical micro LED chip 40 is coupled, and such an example is shown in FIG. 6A.
 次に、図7に示すように、縦型マイクロLEDチップ40がチップ結合部421に結合した実装基板400の全面に絶縁膜422を表面がほぼ平坦となるように形成した後、この絶縁膜422をは反応性イオンエッチング(RIE)法などによりエッチングすることによりp側電極45(図示せず)を露出させる。 Next, as shown in FIG. 7, an insulating film 422 is formed on the entire surface of the mounting board 400 on which the vertical micro LED chip 40 is coupled to the chip coupling part 421 so that the surface is almost flat. The p-side electrode 45 (not shown) is exposed by etching using reactive ion etching (RIE) or the like.
 次に、図8Aおよび図8Bに示すように、絶縁膜422上に、各回路ユニット内の全ての下部支線部電極4203と直交する方向に延在するように、かつ全ての下部支線部電極4203に跨がるように複数の短冊状の細長い透明電極435を形成する。これらの透明電極435の間の隙間は縦型マイクロLEDチップ40のp側電極45の直径より小さくする。こうすることで、チップ結合部421に結合した縦型マイクロLEDチップ40のp側電極45は、いずれかの透明電極435と接触することができる。透明電極435はITOなどの透明電極材料からなる。次に、絶縁膜422上に上部電極430を形成する。上部電極430は、下部幹線部電極4201と直交する方向に互いに平行に延在する複数の上部幹線部電極431とそれぞれの上部幹線部電極431からこの上部幹線部電極431と直交する方向に各回路ユニット当たり当たり1本延びた上部支線部電極432とからなる。各上部支線部電極432は各上部幹線部電極431に平行な方向に、従って下部支線部電極4203に直角な方向に延びるように複数に分岐しており、それらの先端は透明電極435と接続されている。分岐した複数の上部支線部電極432の数UはU≧4に選ばれる。図8AにおいてはU=4の場合が示されている。透明電極435は上部支線部電極432の一部を構成している。 Next, as shown in FIGS. 8A and 8B, a layer is placed on the insulating film 422 so as to extend in a direction perpendicular to all the lower branch electrodes 4203 in each circuit unit, and to cover all the lower branch electrodes 4203 in each circuit unit. A plurality of elongated transparent electrodes 435 in the form of strips are formed so as to straddle the area. The gap between these transparent electrodes 435 is made smaller than the diameter of the p-side electrode 45 of the vertical micro LED chip 40. By doing so, the p-side electrode 45 of the vertical micro LED chip 40 coupled to the chip coupling portion 421 can come into contact with any of the transparent electrodes 435. The transparent electrode 435 is made of a transparent electrode material such as ITO. Next, an upper electrode 430 is formed on the insulating film 422. The upper electrode 430 includes a plurality of upper trunk electrodes 431 extending parallel to each other in a direction orthogonal to the lower trunk electrode 4201 and a plurality of upper trunk electrodes 431 extending from each upper trunk electrode 431 to each circuit in a direction orthogonal to the upper trunk electrode 431. It consists of an upper branch electrode 432 extending one per unit. Each upper branch line electrode 432 is branched into a plurality of branches so as to extend in a direction parallel to each upper trunk line electrode 431 and, therefore, in a direction perpendicular to the lower branch line part electrode 4203, and their tips are connected to a transparent electrode 435. ing. The number U of the plurality of branched upper branch line electrodes 432 is selected to satisfy U≧4. In FIG. 8A, the case where U=4 is shown. The transparent electrode 435 constitutes a part of the upper branch line portion electrode 432.
 この後、上述のようにして製造されたマイクロLEDチップ集積装置の検査を行う。具体的には、上部電極430と下部電極420との間の通電試験を行う。すなわち、上部電極430が下部電極420より高電位となるように電圧を印加することにより各縦型マイクロLEDチップ40に例えば1μA程度の電流を流して各縦型マイクロLEDチップ40の発光を画像解析し、リーク不良に起因して光量不良のある縦型マイクロLEDチップ40が接続されている透明電極435および上部支線部電極432を特定する。図9において、こうして特定された上部支線部電極432を符号432A、432Bで示す。 After this, the micro LED chip integrated device manufactured as described above is inspected. Specifically, a current conduction test is performed between the upper electrode 430 and the lower electrode 420. That is, by applying a voltage so that the upper electrode 430 has a higher potential than the lower electrode 420, a current of, for example, about 1 μA is caused to flow through each vertical micro LED chip 40, and the light emission of each vertical micro LED chip 40 is image-analyzed. Then, the transparent electrode 435 and the upper branch line electrode 432 to which the vertical micro LED chip 40 with a defective light amount due to a leakage defect is connected are identified. In FIG. 9, the upper branch line portion electrodes 432 identified in this manner are indicated by reference numerals 432A and 432B.
 次に、上述のようにして特定された上部支線部電極432A、432Bの一部(図9中、×で示した箇所)にレーザービームまたは電子線を照射することにより切断する。切断後の上部支線部電極432A、432Bの状態を図10に示す。この場合、切断された上部支線部電極432A、432Bが接続された透明電極435と接続された縦型マイクロLEDチップ40は全て使用することができなくなるが、それ以外の上部支線部電極432が接続された透明電極435と接続された縦型マイクロLEDチップ40は全て使用することができる。一つの上部支線部電極432に複数の縦型マイクロLEDチップ40が接続され、不良チップが特定できる場合は、不良チップの近くで上部支線部電極432を切断することで上部幹線部電極431に近い側の良品チップは犠牲にならず使用することができる。 Next, a portion of the upper branch electrodes 432A, 432B identified as described above (locations indicated by x in FIG. 9) is cut by irradiating a laser beam or an electron beam. FIG. 10 shows the state of the upper branch line electrodes 432A and 432B after cutting. In this case, all of the vertical micro LED chips 40 connected to the transparent electrodes 435 to which the cut upper branch line electrodes 432A and 432B are connected become unusable, but the other upper branch line electrodes 432 are connected. All vertical micro LED chips 40 connected to transparent electrodes 435 can be used. If a plurality of vertical micro LED chips 40 are connected to one upper branch line electrode 432 and a defective chip can be identified, the upper branch line electrode 432 is cut near the defective chip so as to be close to the upper main line electrode 431. The good chips on the side can be used without being sacrificed.
 この後、次のようにして再検査を行う。すなわち、上部電極430と下部電極420との間に例えば1μA程度の電流を流して各縦型マイクロLEDチップ40の発光を画像解析する。その結果、光量不良のある縦型マイクロLEDチップ40が見つからなかった場合に修理を終了する。こうしてマイクロLEDチップ集積装置の修理を行うことができる。 After this, re-inspect as follows. That is, a current of, for example, about 1 μA is caused to flow between the upper electrode 430 and the lower electrode 420, and the light emission from each vertical micro LED chip 40 is image-analyzed. As a result, if no vertical micro LED chip 40 with a defective light amount is found, the repair ends. In this way, the micro LED chip integrated device can be repaired.
(6)マイクロLEDチップ集積装置の構造
 図8Aおよび図8Bに示すように、このマイクロLEDチップ集積装置は、一方の主面に下部幹線部電極4201、4202と下部幹線部電極4202から分岐した複数の下部支線部電極4203とを有する下部電極420を有する基板410と、下部電極420の下部支線部電極4203の上面により構成されたチップ結合部421と、チップ結合部421に結合した、上下にp側電極45およびn側電極46を有し、n側電極46がp側電極45に比べてより強く磁場に引き寄せられるように構成された縦型マイクロLEDチップ40と、縦型マイクロLEDチップ40の上層の、上部幹線部電極431とこの上部幹線部電極431から分岐し、複数の下部支線部電極4203と直交する方向に延在し、透明電極435が下部支線部電極4203のチップ結合部421に跨がる複数の上部支線部電極432とを有する上部電極430とを有する。そして、縦型マイクロLEDチップ40は、n側電極46をチップ結合部421に向けてこのチップ結合部421に結合し、n側電極46と下部支線部電極4203とが互いに電気的に接続され、p側電極45と上部電極430の上部支線部電極432とが互いに電気的に接続されている。
(6) Structure of micro LED chip integrated device As shown in FIGS. 8A and 8B, this micro LED chip integrated device has lower trunk electrodes 4201 and 4202 on one main surface and a plurality of lower trunk electrodes 4202 branched from the lower trunk electrode 4202. a substrate 410 having a lower electrode 420 having a lower branch line electrode 4203; a chip coupling part 421 configured by the upper surface of the lower branch line part electrode 4203 of the lower electrode 420; A vertical micro LED chip 40 has a side electrode 45 and an n-side electrode 46, and is configured such that the n-side electrode 46 is attracted to a magnetic field more strongly than the p-side electrode 45; An upper main line electrode 431 of the upper layer branches from the upper main line electrode 431 and extends in a direction perpendicular to the plurality of lower branch line electrodes 4203, and a transparent electrode 435 connects to the tip coupling part 421 of the lower branch line electrode 4203. It has an upper electrode 430 having a plurality of upper branch line part electrodes 432 spanning over it. The vertical micro LED chip 40 is coupled to the chip coupling part 421 with the n-side electrode 46 facing the chip coupling part 421, and the n-side electrode 46 and the lower branch electrode 4203 are electrically connected to each other. The p-side electrode 45 and the upper branch electrode 432 of the upper electrode 430 are electrically connected to each other.
 以上のように、この第1の実施の形態によれば、縦型マイクロLEDチップ40のn側電極46に軟磁性体であるNi膜を含ませることにより、縦型マイクロLEDチップ40のn側電極46側がp側電極45側に比べてより強く磁場に引き寄せられるように構成し、一つの回路ユニット内の下部支線部電極4203のチップ結合部421にインク200を吐出し、縦型マイクロLEDチップ40のn側電極46側を磁力により引き付けてチップ結合部421に接触させ、その後Sn膜47を溶融固化させることにより縦型マイクロLEDチップ40とチップ結合部421とを電気的および機械的に結合させることで、縦型マイクロLEDチップ40の集積度によらず、マイクロLEDチップ集積装置、例えばマイクロLEDディスプレイ、マイクロLEDバックライト、マイクロLED照明装置などを低コストで容易に実現することができる。また、縦型マイクロLEDチップ40はチップ結合部421上にランダム配置で結合させれば足りるため、縦型マイクロLEDチップ40の高精度の位置制御が不要であり、マイクロLEDチップ集積装置の製造が容易となる。また、一つの回路ユニット内には、複数の下部支線部電極4203および複数の上部支線部電極432が設けられているので、いずれかの上部支線部電極432が接続された縦型マイクロLEDチップ40に不良があった場合、その上部支線部電極432を切断するだけで、あるいは、この縦型マイクロLEDチップ40がチップ結合部421に結合した下部支線部電極4203だけを切断するだけで修理を容易に行うことができる。このため、修理に伴って無駄になる縦型マイクロLEDチップ40を最小限に留めることができ、無駄になる縦型マイクロLEDチップ40の数の大幅な低減を図ることができる。このマイクロLEDチップ集積装置は、図8Aおよび図8Bに示す3つの回路ユニットのそれぞれを青(B)、赤(R)、緑(G)の発光領域としてRGB-1画素を構成すると考えると、パッシブマトリクス駆動方式のカラーマイクロLEDディスプレイを実現することができる。この場合、上部電極幹線部431がカラム電極配線を構成する。縦型マイクロLEDチップ40を青色発光とすると、赤の発光領域および緑の発光領域の上方にそれぞれ赤および緑の蛍光体を形成する。縦型マイクロLEDチップ40を紫外領域または青紫色発光とすると、青の発光領域、赤の発光領域および緑の発光領域の上方にそれぞれ青、赤および緑の蛍光体を形成する。具体的には、例えば、図8Aおよび図8Bに示す実装基板400の表面にそれぞれの蛍光体を形成した後、その上にフレキシブルフィルムなどからなる透明基板を設け、さらにその上に光拡散用の拡散シートを設ける。 As described above, according to the first embodiment, by including the Ni film, which is a soft magnetic material, in the n-side electrode 46 of the vertical micro-LED chip 40, the n-side electrode 46 of the vertical micro-LED chip 40 is The electrode 46 side is configured to be attracted to the magnetic field more strongly than the p-side electrode 45 side, and ink 200 is ejected to the chip coupling part 421 of the lower branch electrode 4203 in one circuit unit, and the vertical micro LED chip The vertical micro LED chip 40 and the chip coupling part 421 are electrically and mechanically coupled by attracting the n-side electrode 46 side of the chip 40 by magnetic force and bringing it into contact with the chip coupling part 421, and then melting and solidifying the Sn film 47. By doing so, a micro LED chip integrated device such as a micro LED display, a micro LED backlight, a micro LED lighting device, etc. can be easily realized at low cost, regardless of the degree of integration of the vertical micro LED chips 40. In addition, since it is sufficient to couple the vertical micro LED chips 40 in a random arrangement on the chip coupling part 421, there is no need for highly accurate position control of the vertical micro LED chips 40, and the manufacturing of the micro LED chip integrated device is simplified. It becomes easier. Moreover, since a plurality of lower branch line electrodes 4203 and a plurality of upper branch line electrodes 432 are provided in one circuit unit, the vertical micro LED chip 40 to which any of the upper branch line electrodes 432 is connected If there is a defect in the LED, it can be easily repaired by simply cutting the upper branch electrode 432 or by cutting only the lower branch electrode 4203 where the vertical micro LED chip 40 is connected to the chip coupling part 421. can be done. Therefore, the number of wasted vertical micro LED chips 40 due to repair can be kept to a minimum, and the number of wasted vertical micro LED chips 40 can be significantly reduced. Considering that this micro LED chip integrated device constitutes an RGB-1 pixel using the three circuit units shown in FIGS. 8A and 8B as blue (B), red (R), and green (G) light emitting regions, A passive matrix driven color micro LED display can be realized. In this case, the upper electrode main line portion 431 constitutes column electrode wiring. When the vertical micro LED chip 40 emits blue light, red and green phosphors are formed above the red and green light emitting regions, respectively. When the vertical micro LED chip 40 emits light in the ultraviolet region or blue-violet region, blue, red, and green phosphors are formed above the blue, red, and green light-emitting regions, respectively. Specifically, for example, after forming each phosphor on the surface of the mounting board 400 shown in FIGS. 8A and 8B, a transparent substrate made of a flexible film or the like is provided thereon, and a light-diffusing layer is further placed on top of it. Provide a diffusion sheet.
〈第2の実施の形態〉
[マイクロLEDチップ集積装置の製造方法]
 第2の実施の形態においては、実装基板400として図4Aおよび図4Bに示すものの代わりに図11Aおよび図11Bに示すものを用いることが第1の実施の形態と異なる。すなわち、図11Aおよび図11Bに示すように、この実装基板400においては、下部支線部電極4203のチップ結合部421の下方の部分における基板410上にNiなどの円形の軟磁性体500が下部支線部電極4203の中心線に沿って一列にかつ等間隔に複数(この場合は4個)設けられており、これらの軟磁性体500を覆うように下部支線部電極4203が設けられている。軟磁性体500の直径は、縦型マイクロLEDチップ40のn側電極46の直径と同等またはそれ以下に選ばれる。下部支線部電極4203のチップ結合部421のうちの軟磁性体500に対応する部分が縦型マイクロLEDチップ40の結合位置となる。この結合位置のチップ結合部421には円形のSn膜47が設けられている。この場合、縦型マイクロLEDチップ40のSn膜47は形成する必要がない。この実装基板400のその他のことは第1の実施の形態と同様である。
<Second embodiment>
[Method for manufacturing micro LED chip integrated device]
The second embodiment differs from the first embodiment in that the mounting board 400 shown in FIGS. 11A and 11B is used instead of the mounting board 400 shown in FIGS. 4A and 4B. That is, as shown in FIGS. 11A and 11B, in this mounting board 400, a circular soft magnetic material 500 such as Ni is placed on the substrate 410 in a portion below the chip coupling part 421 of the lower branch electrode 4203. A plurality of (four in this case) branch electrodes 4203 are provided in a row at equal intervals along the center line of the branch electrodes 4203, and the lower branch electrodes 4203 are provided so as to cover these soft magnetic bodies 500. The diameter of the soft magnetic material 500 is selected to be equal to or smaller than the diameter of the n-side electrode 46 of the vertical micro LED chip 40. A portion of the chip coupling portion 421 of the lower branch electrode 4203 that corresponds to the soft magnetic material 500 is a coupling position of the vertical micro LED chip 40 . A circular Sn film 47 is provided at the chip bonding portion 421 at this bonding position. In this case, it is not necessary to form the Sn film 47 of the vertical micro LED chip 40. The other aspects of this mounting board 400 are the same as those of the first embodiment.
 図12は図11Bに示す実装基板400の一部を模式的に示したものである。図12に示すように、磁場印加装置(図示せず)により矢印で示すように磁場を印加することにより、軟磁性体500を磁化させる。この後、磁場の印加を停止する。この場合、磁場の印加を停止した後も、暫くは、図13に示すように、軟磁性体500から残留磁束501が生じている。 FIG. 12 schematically shows a part of the mounting board 400 shown in FIG. 11B. As shown in FIG. 12, the soft magnetic material 500 is magnetized by applying a magnetic field as indicated by the arrows using a magnetic field application device (not shown). After this, the application of the magnetic field is stopped. In this case, even after the application of the magnetic field is stopped, residual magnetic flux 501 is generated from the soft magnetic body 500 for a while, as shown in FIG. 13.
 そこで、こうして残留磁束501が存在している状態で、インク200を実装基板400の一つの回路ユニット内のチップ結合部421に吐出させる。吐出直後の状態を図14に示す。図15に示すように、こうして吐出されたインク200はチップ結合部421の全体に広がると同時に、このインク200においては、軟磁性体500から生じている残留磁束501により、その中に含まれている複数の縦型マイクロLEDチップ40のn側電極46に含まれるNi膜が磁化される。このため、各縦型マイクロLEDチップ40はインク200中を磁力により下方に引き寄せられ、最終的に各縦型マイクロLEDチップ40はn側電極46側が下になるようにしてチップ結合部421のSn膜47に接触する。この状態を図16に示す。 Therefore, while the residual magnetic flux 501 is present, the ink 200 is discharged onto the chip coupling portion 421 within one circuit unit of the mounting board 400. FIG. 14 shows the state immediately after discharge. As shown in FIG. 15, the ink 200 ejected in this way spreads over the entire chip coupling portion 421, and at the same time, the residual magnetic flux 501 generated from the soft magnetic material 500 causes the ink 200 to be contained therein. The Ni films included in the n-side electrodes 46 of the plurality of vertical micro LED chips 40 are magnetized. Therefore, each vertical micro LED chip 40 is drawn downward by the magnetic force in the ink 200, and finally each vertical micro LED chip 40 is placed so that the n-side electrode 46 side is facing down, and the Sn The membrane 47 is contacted. This state is shown in FIG.
 この後、第1の実施の形態と同様にしてインク200の溶媒の蒸発およびSn膜47の溶融固化により各縦型マイクロLEDチップ40をn側電極46側を下にして機械的および電気的に結合する。符号48は溶融固化したSnを示す。 Thereafter, in the same manner as in the first embodiment, by evaporating the solvent of the ink 200 and melting and solidifying the Sn film 47, each vertical micro LED chip 40 is mechanically and electrically connected with the n-side electrode 46 side down. Join. Reference numeral 48 indicates Sn that has been melted and solidified.
 こうして、図17に示すように、各回路ユニット内のチップ結合部421に縦型マイクロLEDチップ40を結合する。 In this way, as shown in FIG. 17, the vertical micro LED chip 40 is coupled to the chip coupling portion 421 in each circuit unit.
 この後、第1の実施の形態と同様に絶縁膜422の形成以降の工程を進めて、図18に示すように、目的とするマイクロLEDチップ集積装置を製造する。 Thereafter, as in the first embodiment, the steps after forming the insulating film 422 are performed to manufacture the intended micro LED chip integrated device as shown in FIG. 18.
[マイクロLEDチップ集積装置の構造]
 図18に示すように、このマイクロLEDチップ集積装置は、実装基板400の下部支線部電極4203のチップ結合部421の下方の部分の基板410上に軟磁性体500が下部支線部電極4203の中心線に沿って複数設けられ、これらの軟磁性体500を覆うように下部支線部電極4203が設けられ、チップ結合部421に縦型マイクロLEDチップ40がn側電極46側を下にして結合していることを除いて、第1の実施の形態によるマイクロLEDチップ集積装置と同様な構成を有する。
[Structure of micro LED chip integrated device]
As shown in FIG. 18, in this micro LED chip integrated device, a soft magnetic material 500 is placed on the substrate 410 in a portion below the chip coupling portion 421 of the lower branch electrode 4203 of the mounting board 400 at the center of the lower branch electrode 4203. A plurality of lower branch electrodes 4203 are provided along the line, and a lower branch electrode 4203 is provided to cover these soft magnetic bodies 500, and a vertical micro LED chip 40 is coupled to the chip coupling portion 421 with the n-side electrode 46 side facing down. The micro LED chip integrated device has the same configuration as the micro LED chip integrated device according to the first embodiment except that the micro LED chip integrated device has the same configuration as the micro LED chip integrated device according to the first embodiment.
 第2の実施の形態によれば、下部支線部電極4203のチップ結合部201の下方の基板410上に軟磁性体500を予め設けておくことにより、その上方の部分における下部支線部電極4203のチップ結合部421上に縦型マイクロLEDチップ40を結合させることができるため、各縦型マイクロLEDチップ40の結合位置を下部支線部電極4203と上部電極支線部432との交差部に限定することができる。このため、接続不良となる縦型マイクロLEDチップ40の大幅な低減を図ることができ、ひいてはマイクロLEDチップ集積装置の製造コストの低減を図ることができる。そのほか、第1の実施の形態と同様な利点を得ることができる。 According to the second embodiment, by providing the soft magnetic material 500 in advance on the substrate 410 below the chip coupling part 201 of the lower branch electrode 4203, the lower branch electrode 4203 can be Since the vertical micro LED chips 40 can be coupled on the chip coupling part 421, the coupling position of each vertical micro LED chip 40 is limited to the intersection of the lower branch line part electrode 4203 and the upper electrode branch part 432. I can do it. Therefore, it is possible to significantly reduce the number of vertical micro LED chips 40 that cause connection failures, and in turn, it is possible to reduce the manufacturing cost of the micro LED chip integrated device. In addition, advantages similar to those of the first embodiment can be obtained.
 このマイクロLEDチップ集積装置によっても、パッシブマトリクス駆動方式のカラーマイクロLEDディスプレイを実現することができる。 This micro LED chip integrated device also makes it possible to realize a color micro LED display using a passive matrix drive method.
〈第3の実施の形態〉
 第3の実施の形態においては、アクティブマトリクス駆動方式のカラーマイクロLEDディスプレイとして用いることができるマイクロLEDチップ集積装置について説明する。
<Third embodiment>
In the third embodiment, a micro LED chip integrated device that can be used as an active matrix drive type color micro LED display will be described.
[マイクロLEDチップ集積装置の製造方法]
 図19は第3の実施の形態における上部電極形成前の実装基板400を示す。図19に示すように、実装基板400上に下部幹線部電極4202が行方向に互いに平行に複数設けられている。下部幹線部電極4202にはこの下部幹線部電極4202と直交する方向、すなわち列方向に延在して複数の下部支線部電極4203が接続されている。下部支線部電極4203の下方には第2の実施の形態と同様に軟磁性体500が設けられている。そして、軟磁性体500の上方の下部支線部電極4203のチップ結合部421に縦型マイクロLEDチップ40が結合している。図19に示す三つの回路ユニットは左からそれぞれB、R、Gの発光領域を構成しており、これらの発光領域により構成されるRGB-1画素単位が配列しており、実装基板400全体として画素が二次元マトリクス状に配列している。実装基板400上には、列方向に延在した電源線610およびデータ線620に加え、行方向に延在した走査線630も設けられている。各データ線620と各画素の各発光領域との間にはアクティブ駆動回路が設けられ、このアクティブ駆動回路により各画素の各発光領域を選択することができるようになっている。アクティブ駆動回路はトランジスタT1、T2およびコンデンサCからなる。トランジスタT1、T2は一般的には多結晶Si薄膜などの半導体薄膜を用いた薄膜トランジスタにより構成され、コンデンサCは下部電極、絶縁膜および上部電極を積層することにより構成される。トランジスタT1のソースはデータ線620に接続され、ドレインはトランジスタT2のゲートに接続され、ゲートは走査線630に接続されている。トランジスタT2のソースは電源線610に接続され、ドレインは下部電極420に接続されている。コンデンサCはトランジスタT1のドレインと電源線610との間に接続されている。走査線630とデータ線620との選択により各画素の各発光領域を選択する。
後述のアクティブ駆動回路を介してこの下部幹線部電極4201と接続されて幅狭の下部幹線部電極4202がこの下部幹線部電極4201に平行に設けられている。
[Method for manufacturing micro LED chip integrated device]
FIG. 19 shows a mounting board 400 before the upper electrode is formed in the third embodiment. As shown in FIG. 19, a plurality of lower trunk electrodes 4202 are provided on the mounting board 400 in parallel to each other in the row direction. A plurality of lower branch line electrodes 4203 are connected to the lower main line electrode 4202 extending in a direction perpendicular to the lower main line electrode 4202, that is, in the column direction. A soft magnetic material 500 is provided below the lower branch electrode 4203, similar to the second embodiment. The vertical micro LED chip 40 is coupled to the chip coupling portion 421 of the lower branch electrode 4203 above the soft magnetic body 500. The three circuit units shown in FIG. 19 constitute B, R, and G light emitting regions from the left, respectively, and RGB-1 pixel units constituted by these light emitting regions are arranged, and the mounting board 400 as a whole Pixels are arranged in a two-dimensional matrix. On the mounting board 400, in addition to power supply lines 610 and data lines 620 extending in the column direction, scanning lines 630 extending in the row direction are also provided. An active drive circuit is provided between each data line 620 and each light emitting region of each pixel, and the active drive circuit allows each light emitting region of each pixel to be selected. The active drive circuit consists of transistors T1, T2 and capacitor C. The transistors T1 and T2 are generally formed by thin film transistors using semiconductor thin films such as polycrystalline Si thin films, and the capacitor C is formed by laminating a lower electrode, an insulating film, and an upper electrode. The source of transistor T1 is connected to data line 620, the drain is connected to the gate of transistor T2, and the gate is connected to scan line 630. The source of transistor T2 is connected to power supply line 610, and the drain is connected to lower electrode 420. Capacitor C is connected between the drain of transistor T1 and power supply line 610. Each light emitting region of each pixel is selected by selecting the scanning line 630 and the data line 620.
A narrow lower main line electrode 4202 is connected to the lower main line electrode 4201 via an active drive circuit, which will be described later, and is provided in parallel to the lower main line electrode 4201.
 図20は、図19に示す実装基板400上に上部電極430を形成した状態を示す。第1の実施の形態と同様に、各回路ユニット内の全ての下部支線部電極4203のチップ結合部421に跨がるように複数の透明電極435が設けられている。これらの透明電極435に上部電極430の上部支線部電極432がそれぞれ接続されている。 FIG. 20 shows a state in which an upper electrode 430 is formed on the mounting board 400 shown in FIG. 19. Similar to the first embodiment, a plurality of transparent electrodes 435 are provided so as to straddle the chip coupling portions 421 of all the lower branch electrodes 4203 in each circuit unit. Upper branch electrodes 432 of the upper electrode 430 are connected to these transparent electrodes 435, respectively.
 縦型マイクロLEDチップ40を青色発光とし、赤の発光領域および緑の発光領域の上方にそれぞれ赤および緑の蛍光体を形成することなどは第1の実施例と同様である。 The vertical micro LED chip 40 emits blue light, and red and green phosphors are formed above the red light emitting region and the green light emitting region, respectively, as in the first embodiment.
 この第3の実施の形態によれば、実装基板400上にRGBの各発光用の縦型マイクロLEDチップ40を容易にしかも極めて短時間に能率的に実装することができ、不良の縦型マイクロLEDチップ40の影響も容易に除去することができることにより、高性能のアクティブ駆動方式のカラーマイクロLEDディスプレイを低コストで実現することができる。加えて、第2の実施の形態と同様な利点を得ることもできる。 According to the third embodiment, it is possible to easily and efficiently mount the vertical micro LED chips 40 for each of RGB light emission on the mounting board 400, and to eliminate defective vertical micro LED chips 40. Since the influence of the LED chip 40 can also be easily removed, a high-performance active drive type color micro LED display can be realized at low cost. In addition, advantages similar to those of the second embodiment can also be obtained.
 以上、この発明の実施の形態について具体的に説明したが、この発明は上述の実施の形態に限定されるものではなく、この発明の技術的思想に基づく各種の変形が可能である。 Although the embodiments of this invention have been specifically described above, this invention is not limited to the above-described embodiments, and various modifications can be made based on the technical idea of this invention.
 例えば、上述の実施の形態において挙げた数値、構成、形状、材料、方法などはあくまでも例に過ぎず、必要に応じてこれらと異なる数値、構成、形状、材料、方法などを用いてもよい。 For example, the numerical values, configurations, shapes, materials, methods, etc. mentioned in the above-described embodiments are merely examples, and numerical values, configurations, shapes, materials, methods, etc. different from these may be used as necessary.
 40 縦型マイクロLEDチップ
 41 n型GaN層
 42 発光層
 43 p型GaN層
 44 GaN層
 45 p側電極
 46 n側電極
 47 Sn膜
 400 実装基板
 410 基板
 420 下部電極
 4201、4202 下部幹線部電極
 4203 下部支線部電極
 421 チップ結合部
 422 絶縁膜
 430 上部電極
 431 上部幹線部電極
 432 上部支線部電極
 435 透明電極
40 Vertical micro LED chip 41 N-type GaN layer 42 Light-emitting layer 43 P-type GaN layer 44 GaN layer 45 P-side electrode 46 N-side electrode 47 Sn film 400 Mounting board 410 Substrate 420 Lower electrode 4201, 4202 Lower trunk electrode 4203 Lower part Branch line part electrode 421 Chip coupling part 422 Insulating film 430 Upper electrode 431 Upper main line part electrode 432 Upper branch line part electrode 435 Transparent electrode

Claims (11)

  1.  一方の主面に下部幹線部電極と当該下部幹線部電極から分岐した複数の下部支線部電極とを有する下部電極を有する基板と、
     上記下部電極の上記複数の下部支線部電極の上面により構成されたチップ結合部と、
     上記チップ結合部に結合した、上下にp側電極およびn側電極を有し、上記p側電極および上記n側電極のうちの一方が他方に比べてより強く磁場に引き寄せられるように構成された縦型の半導体発光素子チップと、
     上記半導体発光素子チップの上層の、上部幹線部電極と当該上部幹線部電極から分岐し、上記複数の下部支線部電極と交差するように上記チップ結合部に跨がる複数の上部支線部電極とを有する上部電極とを有し、
     上記半導体発光素子チップは、上記p側電極および上記n側電極のうちの上記一方を上記チップ結合部に向けて上記チップ結合部に結合し、上記p側電極および上記n側電極のうちの上記一方と上記下部支線部電極とが互いに電気的に接続され、上記p側電極および上記n側電極のうちの他方と上記上部電極の上記上部支線部電極とが互いに電気的に接続されている半導体発光素子チップ集積装置。
    A substrate having a lower electrode having a lower main line electrode and a plurality of lower branch line electrodes branched from the lower main line electrode on one main surface;
    a chip coupling portion configured by the upper surface of the plurality of lower branch electrodes of the lower electrode;
    It has a p-side electrode and an n-side electrode on the upper and lower sides, which are connected to the chip coupling part, and is configured such that one of the p-side electrode and the n-side electrode is more strongly attracted to the magnetic field than the other. A vertical semiconductor light emitting device chip,
    an upper main line electrode in the upper layer of the semiconductor light emitting element chip; and a plurality of upper branch line electrodes that branch from the upper main line electrode and straddle the chip coupling part so as to intersect with the plurality of lower branch line electrodes; and an upper electrode having
    The semiconductor light emitting element chip has one of the p-side electrode and the n-side electrode facing the chip-coupling section and coupled to the chip-coupling section, and one of the p-side electrode and the n-side electrode. one of which is electrically connected to the lower branch line electrode, and the other of the p-side electrode and the n-side electrode and the upper branch electrode of the upper electrode are electrically connected to each other. Light emitting device chip integration device.
  2.  上記基板は互いに独立駆動可能な複数の回路ユニットを有し、上記複数の回路ユニットのそれぞれに対して上記下部電極および上記上部電極が設けられている請求項1記載の半導体発光素子チップ集積装置。 2. The semiconductor light emitting element chip integrated device according to claim 1, wherein the substrate has a plurality of circuit units that can be driven independently of each other, and the lower electrode and the upper electrode are provided for each of the plurality of circuit units.
  3.  上記半導体発光素子チップに加えて、上下にp側電極およびn側電極を有し、上記p側電極および上記n側電極のうちの一方が他方に比べてより強く磁場に引き寄せられるように構成された縦型のツェナーダイオードをさらに有し、当該ツェナーダイオードは当該半導体発光素子チップに対して逆バイアスになるように接続されている請求項1記載の半導体発光素子チップ集積装置。 In addition to the semiconductor light emitting element chip, it has a p-side electrode and an n-side electrode on the upper and lower sides, and is configured such that one of the p-side electrode and the n-side electrode is attracted to the magnetic field more strongly than the other. 2. The semiconductor light emitting device chip integrated device according to claim 1, further comprising a vertical Zener diode, the Zener diode being connected to be reverse biased with respect to the semiconductor light emitting device chip.
  4.  上記半導体発光素子チップはAlGaInN系の半導体発光素子チップであり、上記半導体発光素子チップの発光層の最大幅は5μm以下であり、当該発光層の周囲が当該発光層よりバンドギャップが大きく、かつ比抵抗の高いAlGaInN系の半導体層によって被覆されている請求項1記載の半導体発光素子チップ集積装置。 The semiconductor light-emitting element chip is an AlGaInN-based semiconductor light-emitting element chip, and the maximum width of the light-emitting layer of the semiconductor light-emitting element chip is 5 μm or less, and the periphery of the light-emitting layer has a larger band gap than the light-emitting layer, and 2. The semiconductor light emitting element chip integrated device according to claim 1, wherein the semiconductor light emitting element chip integrated device is coated with an AlGaInN semiconductor layer having high resistance.
  5.  上記半導体発光素子チップはAlGaInP系の半導体発光素子チップであり、上記半導体発光素子チップの発光層の最大幅は5μm以下であり、当該発光層の周囲が当該発光層よりバンドギャップが大きく、かつ比抵抗の高いAlGaInP系の半導体層によって被覆されている請求項1記載の半導体発光素子チップ集積装置。 The semiconductor light-emitting element chip is an AlGaInP-based semiconductor light-emitting element chip, and the maximum width of the light-emitting layer of the semiconductor light-emitting element chip is 5 μm or less, and the periphery of the light-emitting layer has a larger band gap than the light-emitting layer, and 2. The semiconductor light emitting element chip integrated device according to claim 1, wherein the semiconductor light emitting element chip integrated device is coated with an AlGaInP semiconductor layer having high resistance.
  6.  上記複数の下部支線部電極の数をL(L≧4)、上記複数の上部支線部電極の数をU(U≧4)としたとき、L×U≧16である請求項1記載の半導体発光素子チップ集積装置。 The semiconductor according to claim 1, wherein L×U≧16, where the number of the plurality of lower branch line electrodes is L (L≧4) and the number of the plurality of upper branch line electrodes is U (U≧4). Light emitting device chip integration device.
  7.  上記下部支線部電極の少なくとも一部および/または上記上部支線部電極の少なくとも一部が融点が350℃以下の低融点金属からなる請求項1記載の半導体発光素子チップ集積装置。 2. The semiconductor light emitting element chip integrated device according to claim 1, wherein at least a portion of the lower branch electrode and/or at least a portion of the upper branch electrode are made of a low melting point metal having a melting point of 350° C. or less.
  8.  上記チップ結合部の一部に強磁性体領域が形成されている請求項1記載の半導体発光素子チップ集積装置。 2. The semiconductor light emitting device chip integrated device according to claim 1, wherein a ferromagnetic region is formed in a part of the chip coupling portion.
  9.  チップ結合部に軟磁性体領域が設けられた基板の当該軟磁性体領域に磁場を印加して磁化させる工程と、
     上記磁場を取り去った後、上記軟磁性体領域の残留磁束が消える前に、上下にp側電極およびn側電極を有し、上記p側電極および上記n側電極のうちの一方が他方に比べてより強く磁場に引き寄せられるように構成された縦型の複数の半導体発光素子チップと液体とを含有する液滴状のインクを上記チップ結合部に供給し、上記インク中の上記半導体発光素子チップを、上記p側電極および上記n側電極のうちの上記一方を上記軟磁性体領域に向けて上記軟磁性体領域上に結合させる工程とを有する半導体発光素子チップ集積装置の製造方法。
    applying a magnetic field to the soft magnetic region of the substrate provided with the soft magnetic region in the chip coupling portion to magnetize the soft magnetic region;
    After the magnetic field is removed and before the residual magnetic flux of the soft magnetic region disappears, the soft magnetic region has a p-side electrode and an n-side electrode above and below, and one of the p-side electrode and the n-side electrode is compared to the other. A droplet-shaped ink containing a liquid and a plurality of vertical semiconductor light emitting element chips configured to be more strongly attracted by a magnetic field is supplied to the chip coupling portion, and the semiconductor light emitting element chips in the ink are A method for manufacturing a semiconductor light emitting element chip integrated device, comprising the step of: coupling one of the p-side electrode and the n-side electrode toward the soft magnetic region and onto the soft magnetic region.
  10.  発光層の最大幅が5μm以下であり、当該発光層の周囲が当該発光層よりバンドギャップが大きく、かつ比抵抗の高いAlGaInN系の半導体層によって被覆されているAlGaInN系の半導体発光素子チップ。 An AlGaInN-based semiconductor light-emitting element chip, in which the maximum width of the light-emitting layer is 5 μm or less, and the periphery of the light-emitting layer is covered with an AlGaInN-based semiconductor layer having a larger band gap and higher specific resistance than the light-emitting layer.
  11.  発光層の最大幅が5μm以下であり、当該発光層の周囲が当該発光層よりバンドギャップが大きく、かつ比抵抗の高いAlGaInP系の半導体層によって被覆されているAlGaInP系の半導体発光素子チップ。 An AlGaInP-based semiconductor light-emitting element chip, in which the maximum width of the light-emitting layer is 5 μm or less, and the periphery of the light-emitting layer is covered with an AlGaInP-based semiconductor layer having a larger band gap and higher specific resistance than the light-emitting layer.
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