WO2023178773A1 - 驱动电路及显示装置 - Google Patents

驱动电路及显示装置 Download PDF

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Publication number
WO2023178773A1
WO2023178773A1 PCT/CN2022/087343 CN2022087343W WO2023178773A1 WO 2023178773 A1 WO2023178773 A1 WO 2023178773A1 CN 2022087343 W CN2022087343 W CN 2022087343W WO 2023178773 A1 WO2023178773 A1 WO 2023178773A1
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WIPO (PCT)
Prior art keywords
transistor
node
terminal
source
drain
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2022/087343
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English (en)
French (fr)
Inventor
李佳龙
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
TCL China Star Optoelectronics Technology Co Ltd
Huizhou China Star Optoelectronics Display Co Ltd
Original Assignee
TCL China Star Optoelectronics Technology Co Ltd
Huizhou China Star Optoelectronics Display Co Ltd
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Filing date
Publication date
Application filed by TCL China Star Optoelectronics Technology Co Ltd, Huizhou China Star Optoelectronics Display Co Ltd filed Critical TCL China Star Optoelectronics Technology Co Ltd
Priority to US17/755,867 priority Critical patent/US12190766B2/en
Publication of WO2023178773A1 publication Critical patent/WO2023178773A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2092—Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0289—Details of voltage level shifters arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/04—Maintaining the quality of display appearance
    • G09G2320/043—Preventing or counteracting the effects of ageing

Definitions

  • the present application relates to the field of display technology, and specifically to a driving circuit and a display device.
  • gate driver chips are an important component of the display device.
  • the gate driver chip can also be called GOA (Gate Driver On Array, array substrate row driver) chip. It uses the array process of the thin film transistor display device to fabricate the gate row scanning drive signal circuit on the array substrate to realize gate-by-gate control. A technology of line scan driving method.
  • the main driving principle of the thin film transistor display device is that the system motherboard connects the R/G/B compressed signal, control signal and power to the connector on the circuit board through wires. After the data is processed by the timing controller on the circuit board, it passes through the source The driver chip and the gate driver chip are respectively connected to the display pixels, so that the display device obtains the required power supply and signals.
  • the timing controller needs multiple control signals to control the gate drive chip, but the gate drive chips of different manufacturers use the high and low levels of the control signals in different ways, which makes the timing controller unable to directly communicate with different types of gate drive chips.
  • the pole driver chip is used for matching. Therefore, different types of gate driver chips need to be matched with corresponding timing controllers, which requires the design of different versions of circuit boards, resulting in an increase in material production costs.
  • This application provides a driving circuit and a display device to solve the problem that the timing controller cannot be directly matched with different gate driving chips.
  • This application provides a driving circuit, which includes:
  • Input module the input module is connected to the first signal control end, the second signal control end and the first node respectively, and the input module is used to control the first signal control end and the second signal control end. providing a level signal to the first node;
  • An output module is connected to the first power terminal, the second power terminal, the first node and the output terminal respectively, and the output module is used to provide the signal to the first node under the control of the level signal of the first node.
  • the output terminal provides a signal of the first power terminal or the second power terminal.
  • the input module includes:
  • a first transistor, the gate of the first transistor is connected to the first signal control terminal, one of the source and drain of the first transistor is connected to the second signal control terminal, and the third signal control terminal is connected to the first transistor.
  • the other one of the source and the drain of a transistor is connected to the first node;
  • a second transistor the gate of the second transistor is connected to the first signal control terminal, one of the source and drain of the second transistor is connected to the second signal control terminal, and the second transistor has a gate connected to the first signal control terminal.
  • the other one of the source electrode and the drain electrode of the two transistors is connected to the first node;
  • the first transistor is one of a P-type transistor and an N-type transistor
  • the second transistor is the other one of a P-type transistor and an N-type transistor.
  • the output module includes:
  • a third transistor the gate of the third transistor is connected to the first node, one of the source and drain of the third transistor is connected to the first power terminal, and the third transistor has a gate connected to the first node.
  • the other one of the source electrode and the drain electrode is connected to the output terminal;
  • a fourth transistor, the gate of the fourth transistor is connected to the first node, one of the source and the drain of the fourth transistor is connected to the second power supply terminal, and the gate of the fourth transistor is connected to the first node.
  • the other one of the source electrode and the drain electrode is connected to the output terminal;
  • the third transistor is one of a P-type transistor and an N-type transistor
  • the fourth transistor is the other one of a P-type transistor and an N-type transistor.
  • the input module also includes:
  • a fifth transistor the gate of the fifth transistor is connected to the second node, one of the source and the drain of the fifth transistor is connected to the third power supply terminal, the source and drain of the first transistor The other of the poles is connected to said first node;
  • a sixth transistor the gate of the sixth transistor is connected to the second node, one of the source and drain of the sixth transistor is connected to the fourth power supply terminal, and the source of the second transistor and the other of the drains is connected to the first node;
  • the other one of the source and the drain of the first transistor is connected to the second node, the fifth transistor is one of a P-type transistor and an N-type transistor, and the sixth transistor is a P-type transistor. transistor and the other of N-type transistors.
  • the output module also includes:
  • a seventh transistor The gate of the seventh transistor is connected to the third node. One of the source and drain of the seventh transistor is connected to the fourth node. The source and drain of the first transistor are connected to the fourth node. The other one is connected to the output;
  • An eighth transistor the gate of the eighth transistor is connected to the third node, one of the source and drain of the sixth transistor is connected to the fourth node, and the source of the second transistor is connected to the third node.
  • the other of the pole and the drain is connected to the output terminal;
  • the other one of the source electrode and the drain electrode of the third transistor is connected to the fourth node, and the other one of the source electrode and the drain electrode of the fourth transistor is connected to the fourth node;
  • the first signal control terminal is connected to the third node, the seventh transistor is one of a P-type transistor and an N-type transistor, and the eighth transistor is the other of a P-type transistor and an N-type transistor.
  • the output module also includes:
  • a seventh transistor The gate of the seventh transistor is connected to the third node. One of the source and drain of the seventh transistor is connected to the fourth node. The source and drain of the first transistor are connected to the fourth node. The other one is connected to the output;
  • An eighth transistor the gate of the eighth transistor is connected to the third node, one of the source and drain of the sixth transistor is connected to the fourth node, and the source of the second transistor is connected to the third node.
  • the other of the pole and the drain is connected to the output terminal;
  • the other one of the source electrode and the drain electrode of the third transistor is connected to the fourth node, and the other one of the source electrode and the drain electrode of the fourth transistor is connected to the fourth node;
  • the second signal control terminal is connected to the third node, the seventh transistor is one of a P-type transistor and an N-type transistor, and the eighth transistor is the other of a P-type transistor and an N-type transistor.
  • the first power terminal and the third power terminal are the same power terminal; the second power terminal and the fourth power terminal are the same power terminal.
  • the first power terminal and the fourth power terminal are the same power terminal; the second power terminal and the third power terminal are the same power terminal.
  • the signals of the first power supply terminal and the third power supply terminal are high-level signals or low-level signals
  • the signals of the second power supply terminal and the fourth power supply terminal are The signal is either a low level signal or a high level signal.
  • the signals of the first power supply terminal and the fourth power supply terminal are high-level signals or low-level signals
  • the signals of the second power supply terminal and the third power supply terminal are The signal is either a low level signal or a high level signal.
  • this application also provides a display device, which includes a driving circuit; the driving circuit includes:
  • Input module the input module is connected to the first signal control end, the second signal control end and the first node respectively, and the input module is used to control the first signal control end and the second signal control end. providing a level signal to the first node;
  • An output module is connected to the first power terminal, the second power terminal, the first node and the output terminal respectively, and the output module is used to provide the signal to the first node under the control of the level signal of the first node.
  • the output terminal provides a signal of the first power terminal or the second power terminal.
  • the display device further includes:
  • timing controller connected to the first signal control terminal and the second signal control terminal of the drive circuit
  • a gate driver chip is connected to the output end of the driver circuit.
  • the input module includes:
  • a first transistor, the gate of the first transistor is connected to the first signal control terminal, one of the source and drain of the first transistor is connected to the second signal control terminal, and the third signal control terminal is connected to the first transistor.
  • the other one of the source and the drain of a transistor is connected to the first node;
  • a second transistor the gate of the second transistor is connected to the first signal control terminal, one of the source and drain of the second transistor is connected to the second signal control terminal, and the second transistor has a gate connected to the first signal control terminal.
  • the other one of the source electrode and the drain electrode of the two transistors is connected to the first node;
  • the first transistor is one of a P-type transistor and an N-type transistor
  • the second transistor is the other one of a P-type transistor and an N-type transistor.
  • the output module includes:
  • a third transistor the gate of the third transistor is connected to the first node, one of the source and drain of the third transistor is connected to the first power terminal, and the third transistor has a gate connected to the first node.
  • the other one of the source electrode and the drain electrode is connected to the output terminal;
  • a fourth transistor, the gate of the fourth transistor is connected to the first node, one of the source and the drain of the fourth transistor is connected to the second power supply terminal, and the gate of the fourth transistor is connected to the first node.
  • the other one of the source electrode and the drain electrode is connected to the output terminal;
  • the third transistor is one of a P-type transistor and an N-type transistor
  • the fourth transistor is the other one of a P-type transistor and an N-type transistor.
  • the input module also includes:
  • a fifth transistor the gate of the fifth transistor is connected to the second node, one of the source and the drain of the fifth transistor is connected to the third power supply terminal, the source and drain of the first transistor The other of the poles is connected to said first node;
  • a sixth transistor the gate of the sixth transistor is connected to the second node, one of the source and drain of the sixth transistor is connected to the fourth power supply terminal, and the source of the second transistor and the other of the drains is connected to the first node;
  • the other one of the source and the drain of the first transistor is connected to the second node, the fifth transistor is one of a P-type transistor and an N-type transistor, and the sixth transistor is a P-type transistor. transistor and the other of N-type transistors.
  • the output module also includes:
  • a seventh transistor The gate of the seventh transistor is connected to the third node. One of the source and drain of the seventh transistor is connected to the fourth node. The source and drain of the first transistor are connected to the fourth node. The other one is connected to the output;
  • An eighth transistor the gate of the eighth transistor is connected to the third node, one of the source and drain of the sixth transistor is connected to the fourth node, and the source of the second transistor is connected to the third node.
  • the other of the pole and the drain is connected to the output terminal;
  • the other one of the source electrode and the drain electrode of the third transistor is connected to the fourth node, and the other one of the source electrode and the drain electrode of the fourth transistor is connected to the fourth node;
  • the first signal control terminal is connected to the third node, the seventh transistor is one of a P-type transistor and an N-type transistor, and the eighth transistor is the other of a P-type transistor and an N-type transistor.
  • the output module also includes:
  • a seventh transistor The gate of the seventh transistor is connected to the third node. One of the source and drain of the seventh transistor is connected to the fourth node. The source and drain of the first transistor are connected to the fourth node. The other one is connected to the output;
  • An eighth transistor the gate of the eighth transistor is connected to the third node, one of the source and drain of the sixth transistor is connected to the fourth node, and the source of the second transistor is connected to the third node.
  • the other of the pole and the drain is connected to the output terminal;
  • the other one of the source electrode and the drain electrode of the third transistor is connected to the fourth node, and the other one of the source electrode and the drain electrode of the fourth transistor is connected to the fourth node;
  • the second signal control terminal is connected to the third node, the seventh transistor is one of a P-type transistor and an N-type transistor, and the eighth transistor is the other of a P-type transistor and an N-type transistor.
  • the first power terminal and the third power terminal are the same power terminal; the second power terminal and the fourth power terminal are the same power terminal.
  • the first power terminal and the fourth power terminal are the same power terminal; the second power terminal and the third power terminal are the same power terminal.
  • the signals of the first power supply terminal and the third power supply terminal are high-level signals or low-level signals
  • the signals of the second power supply terminal and the fourth power supply terminal are The signal is either a low level signal or a high level signal.
  • the present application provides a driving circuit and a display device, wherein the driving circuit includes: an input module, the input module is connected to the first signal control terminal, the second signal control terminal and the first node respectively, and the input module is used to Provide level signals to the first node under the control of the first signal control terminal and the second signal control terminal; an output module, the output module is respectively connected with the first power supply terminal, the second power supply terminal, the first power supply terminal and the first power supply terminal.
  • the node is connected to the output terminal, and the output module is configured to provide the signal of the first power terminal or the second power terminal to the output terminal under the control of the level signal of the first node.
  • This application provides a level signal to the first node under the control of the first signal control terminal and the second signal control terminal, and then provides a level signal to the output terminal under the control of the level signal of the first node.
  • the signal of the first power supply terminal or the second power supply terminal can output different level signals under the control of two control signals to solve the problem that the timing controller cannot be directly matched with different gate driver chips.
  • Figure 1 is a first structural schematic diagram of the driving circuit provided by this application.
  • FIG. 2 is a second structural schematic diagram of the driving circuit provided by this application.
  • Figure 3 is a schematic diagram of a display device provided by this application.
  • FIG. 4 is a third structural schematic diagram of the driving circuit provided by this application.
  • FIG. 5 is a fourth structural schematic diagram of the driving circuit provided by this application.
  • Figure 6 is a fifth structural schematic diagram of the driving circuit provided by this application.
  • Figure 7 is a sixth structural schematic diagram of the driving circuit provided by this application.
  • Figure 8 is a seventh structural schematic diagram of the driving circuit provided by this application.
  • FIG. 9 is an eighth structural schematic diagram of the driving circuit provided by this application.
  • Figure 10 is a ninth structural schematic diagram of the driving circuit provided by this application.
  • FIG 11 is a tenth structural schematic diagram of the driving circuit provided by this application.
  • Figure 12 is an eleventh structural schematic diagram of the driving circuit provided by this application.
  • Figure 13 is a twelfth structural schematic diagram of the driving circuit provided by this application.
  • Figure 14 is a thirteenth structural schematic diagram of the driving circuit provided by this application.
  • first and second are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Thus, features defined as “first” and “second” may explicitly or implicitly include one or more of the described features. In the description of this application, “plurality” means two or more than two, unless otherwise explicitly and specifically limited.
  • the transistors used in all embodiments of this application can be thin film transistors, field effect transistors, or other devices with the same characteristics. Since the sources and drains of the transistors used here are symmetrical, their sources and drains are interchangeable. of. In the embodiment of the present application, in order to distinguish the two electrodes of the transistor except the gate electrode, one electrode is called the source electrode and the other electrode is called the drain electrode. According to the form in the attached figure, the middle end of the control module is the gate, the signal input end is the source, and the output end is the drain. In addition, the transistors used in the embodiments of the present application may include P-type transistors and/or N-type transistors.
  • the P-type transistor is turned on when the gate is at a low level and is turned off when the gate is at a high level.
  • the N-type transistor is when the gate is at a high level. It is turned on when the gate is high and turned off when the gate is low.
  • This application provides a driving circuit and a display device, which are described in detail below. It should be noted that the description order of the following embodiments does not limit the preferred order of the embodiments of the present application.
  • FIG. 1 is a first structural schematic diagram of the driving circuit 100 provided by the present application.
  • This application provides a driving circuit 100, which includes an input module 10 and an output module 20.
  • the input module 10 is connected to the first signal control terminal S1, the second signal control terminal S2 and the first node P1 respectively, and the input module 10 is used to connect the first signal control terminal S1 and the second signal control terminal S1 to the first node P1. Provide a level signal to the first node P1 under the control of the signal control terminal S2;
  • the output module 20 is connected to the first power terminal V1, the second power terminal V2, the first node P1 and the output terminal OUT respectively.
  • the output module 20 is used to control the level signal at the first node P1.
  • a signal of the first power terminal V1 or the second power terminal V2 is provided downwardly to the output terminal OUT.
  • the input module 10 is used to provide a level signal to the first node P1 under the control of the first signal control terminal S1 and the second signal control terminal S2.
  • the first node P1 The level signal may be high level or low level
  • the output module 20 provides the first power terminal V1 or the second power terminal V1 to the output terminal OUT under the control of the level signal of the first node P1
  • the signal of the power supply terminal V2 wherein the signal of the first power supply terminal V1 is one of high level and low level, and the signal of the second power supply terminal V2 is the other one of high level and low level.
  • the timing controller is connected to the first signal control terminal S1 and the second signal control terminal S2, and the gate driver chip is connected to the output terminal OUT, and then sets the voltage of the first power terminal V1 and the second power terminal V2. If the chip is flat, the timing controller inputs accurate control signals to the gate driver chip through the output terminal OUT, thereby solving the problem that the timing controller cannot be directly matched with different gate driver chips.
  • the input module 10 includes a first transistor T1 and a second transistor T2, wherein the gate of the first transistor T1 is connected to the first signal control terminal S1, and the source and drain of the first transistor T1 One of them is connected to the second signal control terminal S2, the other of the source and drain of the first transistor T1 is connected to the first node P1; the gate of the second transistor T2 Connected to the first signal control terminal S1, one of the source and drain of the second transistor T2 is connected to the second signal control terminal S2, and the source and drain of the second transistor T2 The other one is connected to the first node P1; the first transistor T1 is one of a P-type transistor and an N-type transistor, and the second transistor T2 is the other of a P-type transistor and an N-type transistor.
  • the first transistor T1 is one of a P-type transistor and an N-type transistor
  • the second transistor T2 is the other of a P-type transistor and an N-type transistor.
  • the first transistor T1 is one of a P-type transistor and an N-type transistor
  • the second transistor T2 is the other one of a P-type transistor and an N-type transistor
  • the first transistor T1 and The second transistor T2 adopts different types of transistors and can alternately output signals of different levels to the first node P1 under the control of the first signal control terminal S1 and the second signal control terminal S2.
  • the first transistor T1 and the second transistor T2 are turned on alternately instead of continuously working, which can improve the life of the transistors.
  • the output module 20 includes a third transistor T3 and a fourth transistor T4.
  • the gate of the third transistor T3 is connected to the first node P1, and the source of the third transistor T3 is connected to the first node P1.
  • One of the drains is connected to the first power terminal V1, the other of the source and drain of the third transistor T3 is connected to the output terminal OUT;
  • the gate of the fourth transistor T4 is connected to the first node P1, one of the source electrode and the drain electrode of the fourth transistor T4 is connected to the second power terminal V2, and the other of the source electrode and the drain electrode of the fourth transistor T4 is connected to the first node P1.
  • One is connected to the output terminal OUT;
  • the third transistor T3 is one of a P-type transistor and an N-type transistor, and the fourth transistor T4 is the other of a P-type transistor and an N-type transistor.
  • the third transistor T3 is one of a P-type transistor and an N-type transistor
  • the fourth transistor T4 is the other one of a P-type transistor and an N-type transistor
  • the third transistor T3 and The fourth transistor T4 adopts different types of transistors, and turns on the third transistor T3 or the fourth transistor T4 according to the level signal of the first node P1, thereby providing the output terminal OUT with The signal of the first power terminal V1 or the second power terminal V2.
  • the third transistor T3 and the fourth transistor T4 are turned on alternately instead of continuously working, which can improve the life of the transistors.
  • the first transistor T1 is an N-type transistor
  • the second transistor T2 is a P-type transistor
  • the third transistor T3 is a P-type transistor
  • the fourth transistor T4 is an N-type transistor. type transistor.
  • the first power terminal V1 is connected to a high-level signal
  • the second power terminal V2 is connected to a low-level signal.
  • the specific working process is as follows: when the signals of the first signal control terminal S1 and the second signal control terminal S2 are both high-level signals, the first transistor T1 is turned on, and the second transistor T1 is turned on. The transistor T2 is turned off, the first transistor T1 transmits the high level signal of the second signal control terminal S2 to the first node P1, the first node P1 turns on the fourth transistor T4, and the fourth transistor T4 switches the second power terminal
  • the low-level signal of V2 is sent to the output terminal OUT; when the signals of the first signal control terminal S1 and the second signal control terminal S2 are both low-level signals, the first transistor T1 is turned off, and the second transistor T2 is turned on, and the second transistor T2 transmits the low-level signal of the second signal control terminal S2 to the first node P1.
  • the first node P1 turns on the third transistor T3, and the third transistor T3 turns on the first power terminal.
  • the high-level signal of V1 is sent to the output terminal OUT; when the signal of the first signal control terminal S1 is a high-level signal and the signal of the second signal control terminal S2 is a low-level signal, the first transistor T1 is turned on, the second transistor T2 is turned off, the first transistor T1 transmits the low level signal of the second signal control terminal S2 to the first node P1, the first node P1 causes the third transistor T3 to be turned on, and the third transistor T3 transmits the high-level signal of the first power terminal V1 to the output terminal OUT; when the signal of the first signal control terminal S1 is a low-level signal, the signal of the second signal control terminal S2 is a high-level signal.
  • the first transistor T1 When, the signals at the first signal control terminal S1 are all low-level signals, and when the signals at the second signal control terminal S2 are high-level signals, the first transistor T1 is turned off and the second transistor T2 is turned on.
  • the second transistor T2 transmits the high-level signal of the second signal control terminal S2 to the first node P1.
  • the first node P1 turns on the fourth transistor T4.
  • the fourth transistor T4 transmits the low-level signal of the second power terminal V2.
  • the flat signal is sent to the output terminal OUT.
  • FIG. 3 is a schematic diagram of a display device provided by this application.
  • An embodiment of the present application also provides a display device 1000, which includes the driving circuit 100 as described above.
  • the display device 1000 further includes a timing controller 200 and a gate driving chip 300.
  • the timing controller 200 is connected to the first signal control terminal S1 and the second signal control terminal S2 of the driving circuit 100.
  • the gate The driver chip 300 is connected to the output terminal OUT of the driver circuit 100 .
  • the timing controller 200 of the present application inputs accurate control signals to the gate driver chip 300 through the output terminal OUT, thereby solving the problem that the timing controller cannot be directly matched with different gate driver chips.
  • FIG. 4 is a third structural schematic diagram of the driving circuit 100 provided by the present application.
  • the first transistor T1 is a P-type transistor
  • the second transistor T2 is an N-type transistor
  • the third transistor T3 is a P-type transistor
  • the fourth transistor T4 is an N-type transistor. type transistor.
  • FIG. 5 is a fourth structural schematic diagram of the driving circuit 100 provided by the present application.
  • the first transistor T1 is a P-type transistor
  • the second transistor T2 is an N-type transistor
  • the third transistor T3 is an N-type transistor
  • the fourth transistor T4 is a P-type transistor. type transistor.
  • FIG. 6 is a fifth structural schematic diagram of the driving circuit 100 provided by the present application.
  • the first transistor T1 is an N-type transistor
  • the second transistor T2 is a P-type transistor
  • the third transistor T3 is an N-type transistor
  • the fourth transistor T4 is a P-type transistor. type transistor.
  • FIG. 7 is a sixth structural schematic diagram of the driving circuit 100 provided by the present application.
  • the input module 10 further includes: a fifth transistor T5 and a sixth transistor T6.
  • the gate of the fifth transistor T5 The terminal is connected to the second node P2, one of the source and drain of the fifth transistor T5 is connected to the third power terminal V3, and the other of the source and drain of the first transistor T1 is connected to the third power terminal V3.
  • the first node P1 is connected; the gate of the sixth transistor T6 is connected to the second node P2, and one of the source and drain of the sixth transistor T6 is connected to the fourth power terminal V4,
  • the other one of the source electrode and the drain electrode of the second transistor T2 is connected to the first node P1; the other one of the source electrode and the drain electrode of the first transistor T1 is connected to the second node P2.
  • the fifth transistor T5 is one of a P-type transistor and an N-type transistor
  • the sixth transistor T6 is the other one of a P-type transistor and an N-type transistor.
  • the fifth transistor T5 is one of a P-type transistor and an N-type transistor
  • the sixth transistor T6 is the other one of a P-type transistor and an N-type transistor
  • the fifth transistor T5 and The sixth transistor T6 uses different types of transistors, and turns on the fifth transistor T5 or the sixth transistor T6 according to the level signal of the second node P2, so that it can alternately move to the first node P1. Output different level signals.
  • the fifth transistor T5 and the sixth transistor T6 are turned on alternately instead of continuously working, which can improve the life of the transistors.
  • the fifth transistor T5 is an N-type transistor
  • the sixth transistor T6 is a P-type transistor.
  • the signals of the first power terminal V1 and the third power terminal V3 are high-level signals
  • the signals of the second power terminal V2 and the fourth power terminal V4 are low-level signals.
  • the specific working process is as follows: when the signals of the first signal control terminal S1 and the second signal control terminal S2 are both high-level signals, the first transistor T1 is turned on, and the second transistor T1 is turned on.
  • the transistor T2 is turned off, the first transistor T1 transmits the high-level signal of the second signal control terminal S2 to the second node P2, the second node P2 turns on the sixth transistor T6, and the sixth transistor T6 turns on the fourth
  • the low-level signal of the power terminal V4 is sent to the first node P1, the first node P1 turns on the third transistor T3, and the third transistor T3 sends the high-level signal of the first power terminal V1 to the output terminal OUT; when the When the signals of the first signal control terminal S1 and the second signal control terminal S2 are both low-level signals, the first transistor T1 is turned off, the second transistor T2 is turned on, and the second transistor T2 converts the second signal The low-level signal of the control terminal S2 is transmitted to the first node P1.
  • the first node P1 turns on the third transistor T3.
  • the third transistor T3 transmits the high-level signal of the first power terminal V1 to the output terminal OUT; when the When the signal at the first signal control terminal S1 is a high-level signal and the signal at the second signal control terminal S2 is a low-level signal, the first transistor T1 is turned on, the second transistor T2 is turned off, and the first transistor T1 The low-level signal of the second signal control terminal S2 is sent to the second node P2.
  • the second node P2 turns on the fifth transistor T5.
  • the fifth transistor T5 switches the high-level signal of the third power supply terminal V3.
  • the fourth transistor T4 sends the low-level signal of the second power terminal V2 to the output terminal OUT; when the first signal control terminal S1 When the signal is a low-level signal and the signal of the second signal control terminal S2 is a high-level signal, the first transistor T1 is turned off, the second transistor T2 is turned on, and the second transistor T2 switches the second signal control terminal S2 to a high-level signal.
  • the high-level signal of S2 is transmitted to the first node P1, which turns on the fourth transistor T4.
  • the fourth transistor T4 transmits the low-level signal of the second power terminal V2 to the output terminal OUT.
  • FIG. 8 is a seventh structural schematic diagram of the driving circuit 100 provided by the present application.
  • the first power terminal V1 and the third power terminal V3 are the same power terminal; the second power terminal V2 and the fourth power terminal V4 are the same power terminal.
  • FIG. 9 is an eighth structural schematic diagram of the driving circuit 100 provided by the present application.
  • the fifth transistor T5 is a P-type transistor
  • the sixth transistor T6 is an N-type transistor.
  • the signals of the first power terminal V1 and the third power terminal V3 are low-level signals, and the signals of the second power terminal V2 and the fourth power terminal V4 are high level signal.
  • the first power terminal V1 and the third power terminal V3 are the same power terminal; the second power terminal V2 and the fourth power terminal V4 are the same power terminal.
  • FIG. 10 is a ninth structural schematic diagram of the driving circuit 100 provided by this application.
  • the signals of the first power terminal V1 and the fourth power terminal V4 are low-level signals, and the signals of the second power terminal V2 and the third power terminal V3 are high level signal.
  • the first power terminal V1 and the fourth power terminal V4 are the same power terminal; the second power terminal V2 and the third power terminal V3 are the same power terminal.
  • the signals of the first power terminal V1 and the fourth power terminal V4 are high-level signals, and the signals of the second power terminal V2 and the third power terminal V3 are low level signal.
  • the first power terminal V1 and the fourth power terminal V4 are the same power terminal; the second power terminal V2 and the third power terminal V3 are the same power terminal.
  • FIG. 11 is a tenth structural schematic diagram of the driving circuit 100 provided by this application.
  • the output module 20 also includes: a seventh transistor T7 and an eighth transistor T8, the gate of the seventh transistor T7 is connected to the third node P3, One of the source and the drain of the seventh transistor T7 is connected to the fourth node P4, and the other of the source and the drain of the first transistor T1 is connected to the output terminal OUT;
  • the gate of the eighth transistor T8 is connected to the third node P3, one of the source and the drain of the sixth transistor T6 is connected to the fourth node P4, and the source of the second transistor T2
  • the other one of the source electrode and the drain electrode of the third transistor T3 is connected to the fourth node P4, and the source electrode of the fourth transistor T4 is connected to the output terminal OUT.
  • the other one of the electrode and the drain is connected to the fourth node P4; the first signal control terminal S1 is connected to the third node P3, and the seventh transistor T7 is a P-type transistor or an N-type transistor.
  • the eighth transistor T8 is the other one of a P-type transistor and an N-type transistor.
  • the seventh transistor T7 and the eighth transistor T8 are connected between the fourth node P4 and the output terminal OUT, and the seventh transistor T7 is a P-type transistor. and one of N-type transistors.
  • the eighth transistor T8 is the other one of P-type transistors and N-type transistors.
  • the first signal control terminal S1 is used to control the first signal control terminal S1 through the first signal control terminal S1.
  • One of the seventh transistor T7 and the eighth transistor T8 is turned on, thereby providing the signal of the first power terminal V1 or the second power terminal V2 to the output terminal OUT.
  • the seventh transistor T7 is a P-type transistor
  • the eighth transistor T8 is an N-type transistor.
  • the signals of the first power terminal V1 and the third power terminal V3 are high-level signals
  • the signals of the second power terminal V2 and the fourth power terminal V4 are low-level signals.
  • the specific working process is as follows: when the signals of the first signal control terminal S1 and the second signal control terminal S2 are both high-level signals, the first transistor T1 is turned on, and the second transistor T1 is turned on.
  • the transistor T2 is turned off, the seventh transistor T7 is turned off, the eighth transistor T8 is turned on, the first transistor T1 transmits the high level signal of the second signal control terminal S2 to the second node P2, and the second node P2 enables the sixth transistor T6 is turned on, and the sixth transistor T6 transmits the low-level signal of the fourth power terminal V4 to the first node P1.
  • the first node P1 turns on the third transistor T3, and the third transistor T3 turns on the first power terminal V1.
  • the high-level signal is transmitted to the fourth node P4, and the eighth transistor T8 transmits the high-level signal of the first power terminal V1 to the output terminal OUT;
  • the first transistor T1 When the signals of the first signal control terminal S1 and the second signal control terminal S2 are both low-level signals, the first transistor T1 is turned off, the second transistor T2 is turned on, and the seventh transistor T7 is turned on.
  • the eight transistor T8 is turned off, the second transistor T2 transmits the low level signal of the second signal control terminal S2 to the first node P1, the first node P1 turns on the third transistor T3, and the third transistor T3 turns on the first power supply
  • the high-level signal of the terminal V1 is transmitted to the fourth node P4, and the seventh transistor T7 transmits the high-level signal of the first power terminal V1 to the output terminal OUT;
  • the first transistor T1 When the signal of the first signal control terminal S1 is a high-level signal and the signal of the second signal control terminal S2 is a low-level signal, the first transistor T1 is turned on, the second transistor T2 is turned off, and the seventh transistor T2 is turned off.
  • the transistor T7 is turned off, the eighth transistor T8 is turned on, the first transistor T1 transmits the low level signal of the second signal control terminal S2 to the second node P2, the second node P2 turns on the fifth transistor T5, and the fifth transistor T5 is turned on.
  • the transistor T5 transmits the high-level signal of the third power terminal V3 to the first node P1.
  • the first node P1 turns on the fourth transistor T4.
  • the fourth transistor T4 transmits the low-level signal of the second power terminal V2.
  • the eighth transistor T8 transmits the low-level signal of the second power terminal V2 to the output terminal OUT;
  • the first transistor T1 When the signal of the first signal control terminal S1 is a low-level signal and the signal of the second signal control terminal S2 is a high-level signal, the first transistor T1 is turned off, the second transistor T2 is turned on, and the seventh transistor T2 is turned on.
  • the transistor T7 is turned on, the eighth transistor T8 is turned off, the second transistor T2 transmits the high level signal of the second signal control terminal S2 to the first node P1, the first node P1 causes the fourth transistor T4 to be turned on, and the fourth transistor T4 is turned on.
  • the transistor T4 delivers the low-level signal of the second power terminal V2 to the fourth node P4, and the seventh transistor T7 delivers the low-level signal of the second power terminal V2 to the output terminal OUT.
  • FIG. 12 is an eleventh structural schematic diagram of the driving circuit 100 provided by this application.
  • the seventh transistor T7 is an N-type transistor
  • the eighth transistor T8 is a P-type transistor.
  • FIG. 13 is a twelfth structural schematic diagram of the driving circuit 100 provided by this application.
  • the output module 20 also includes: a seventh transistor T7 and an eighth transistor T8, the gate of the seventh transistor T7 is connected to the third node P3, One of the source and the drain of the seventh transistor T7 is connected to the fourth node P4, and the other of the source and the drain of the first transistor T1 is connected to the output terminal OUT;
  • the gate of the eighth transistor T8 is connected to the third node P3, one of the source and the drain of the sixth transistor T6 is connected to the fourth node P4, and the source of the second transistor T2
  • the other one of the source electrode and the drain electrode of the third transistor T3 is connected to the fourth node P4, and the source electrode of the fourth transistor T4 is connected to the output terminal OUT.
  • the other one of the electrode and the drain is connected to the fourth node P4; the second signal control terminal S2 is connected to the third node P3; the seventh transistor T7 is one of a P-type transistor and an N-type transistor. One of them, the eighth transistor T8 is the other one of a P-type transistor and an N-type transistor.
  • the seventh transistor T7 and the eighth transistor T8 are connected between the fourth node P4 and the output terminal OUT, and the seventh transistor T7 is a P-type transistor. and one of N-type transistors.
  • the eighth transistor T8 is the other one of P-type transistors and N-type transistors.
  • the second signal control terminal S2 is used to control the first signal control terminal S1 through the second signal control terminal S2.
  • One of the seventh transistor T7 and the eighth transistor T8 is turned on, thereby providing the signal of the first power terminal V1 or the second power terminal V2 to the output terminal OUT.
  • the seventh transistor T7 is a P-type transistor
  • the eighth transistor T8 is an N-type transistor.
  • the signals of the first power terminal V1 and the third power terminal V3 are high-level signals
  • the signals of the second power terminal V2 and the fourth power terminal V4 are low-level signals.
  • the specific working process is as follows: when the signals of the first signal control terminal S1 and the second signal control terminal S2 are both high-level signals, the first transistor T1 is turned on, and the second transistor T1 is turned on.
  • the transistor T2 is turned off, the seventh transistor T7 is turned off, the eighth transistor T8 is turned on, the first transistor T1 transmits the high level signal of the second signal control terminal S2 to the second node P2, and the second node P2 enables the sixth transistor T6 is turned on, and the sixth transistor T6 transmits the low-level signal of the fourth power terminal V4 to the first node P1.
  • the first node P1 turns on the third transistor T3, and the third transistor T3 turns on the first power terminal V1.
  • the high-level signal is transmitted to the fourth node P4, and the eighth transistor T8 transmits the high-level signal of the first power terminal V1 to the output terminal OUT;
  • the first transistor T1 When the signals of the first signal control terminal S1 and the second signal control terminal S2 are both low-level signals, the first transistor T1 is turned off, the second transistor T2 is turned on, and the seventh transistor T7 is turned on.
  • the eight transistor T8 is turned off, the second transistor T2 transmits the low level signal of the second signal control terminal S2 to the first node P1, the first node P1 turns on the third transistor T3, and the third transistor T3 turns on the first power supply
  • the high-level signal of the terminal V1 is transmitted to the fourth node P4, and the seventh transistor T7 transmits the high-level signal of the first power terminal V1 to the output terminal OUT;
  • the first transistor T1 When the signal of the first signal control terminal S1 is a high-level signal and the signal of the second signal control terminal S2 is a low-level signal, the first transistor T1 is turned on, the second transistor T2 is turned off, and the seventh transistor T2 is turned off.
  • the transistor T7 is turned on, the eighth transistor T8 is turned off, the first transistor T1 transmits the low level signal of the second signal control terminal S2 to the second node P2, the second node P2 turns on the fifth transistor T5, and the fifth transistor T5 is turned on.
  • the transistor T5 transmits the high-level signal of the third power terminal V3 to the first node P1.
  • the first node P1 turns on the fourth transistor T4.
  • the fourth transistor T4 transmits the low-level signal of the second power terminal V2.
  • the seventh transistor T7 transmits the low-level signal of the second power terminal V2 to the output terminal OUT;
  • the first transistor T1 When the signal of the first signal control terminal S1 is a low-level signal and the signal of the second signal control terminal S2 is a high-level signal, the first transistor T1 is turned off, the second transistor T2 is turned on, and the seventh transistor T2 is turned on.
  • the transistor T7 is turned off, the eighth transistor T8 is turned on, the second transistor T2 transmits the high level signal of the second signal control terminal S2 to the first node P1, the first node P1 causes the fourth transistor T4 to be turned on, and the fourth transistor T2 is turned on.
  • the transistor T4 delivers the low-level signal of the second power terminal V2 to the fourth node P4, and the eighth transistor T8 delivers the low-level signal of the second power terminal V2 to the output terminal OUT.
  • FIG. 14 is a thirteenth structural schematic diagram of the driving circuit 100 provided by this application.
  • the seventh transistor T7 is an N-type transistor
  • the eighth transistor T8 is a P-type transistor.

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Abstract

一种驱动电路（100）及显示装置（1000），该驱动电路（100）在第一信号控制端（S1）和第二信号控制端（S2）的控制下向第一节点（P1）提供电平信号，再在第一节点（P1）的电平信号控制下向输出端（OUT）提供第一电源端（V1）或第二电源端（V2）的信号，从而实现在两个控制信号控制下输出不同的电平信号，以解决时序控制器（200）不能与不同的栅极驱动芯片（300）直接匹配使用的问题。

Description

驱动电路及显示装置 技术领域
本申请涉及显示技术领域，具体涉及一种驱动电路及显示装置。
 背景技术
显示装置作为电子设备的显示部件已经广泛的应用于各种电子产品中，其中，栅极驱动芯片为显示装置的一个重要组成部分。栅极驱动芯片也可以称为GOA(Gate Driver On Array，阵列基板行驱动) 芯片，其利用薄膜晶体管显示装置的阵列制程将栅极行扫描驱动信号电路制作在阵列基板上，实现对栅极逐行扫描的驱动方式的一项技术。
薄膜晶体管显示装置主要驱动原理是，系统主板将R/G/B压缩信号、控制信号及动力通过线材与电路板上的连接器连接，数据经过电路板上的时序控制器处理后，通过源极驱动芯片和栅极驱动芯片分别与显示像素连接，从而使得显示装置获得所需的电源和信号。时序控制器控制栅极驱动芯片需要多个控制信号，但是不同制造产商的栅极驱动芯片对于控制信号的高低电平的使用方式各不相同，这使得时序控制器不能直接与不同类型的栅极驱动芯片进行匹配使用。因此不同类型的栅极驱动芯片需要与相对应的时序控制器进行匹配，从而需要设计不同版本的电路板，导致物料生产成本的增加。
 技术问题
本申请提供一种驱动电路及显示装置，以解决时序控制器不能与不同的栅极驱动芯片直接匹配使用的问题。
 技术解决方案
本申请提供一种驱动电路，其包括：
输入模块，所述输入模块分别与第一信号控制端、第二信号控制端和第一节点连接，所述输入模块用于在所述第一信号控制端和所述第二信号控制端的控制下向所述第一节点提供电平信号；
输出模块，所述输出模块分别与第一电源端、第二电源端、所述第一节点以及输出端连接，所述输出模块用于在所述第一节点的电平信号控制下向所述输出端提供所述第一电源端或所述第二电源端的信号。
可选的，在本申请一些实施例中，所述输入模块包括：
第一晶体管，所述第一晶体管的栅极与所述第一信号控制端连接，所述第一晶体管的源极和漏极中的一者与所述第二信号控制端连接，所述第一晶体管的源极和漏极中的另一者与所述第一节点连接；
第二晶体管，所述第二晶体管的栅极与所述第一信号控制端连接，所述第二晶体管的源极和漏极中的一者与所述第二信号控制端连接，所述第二晶体管的源极和漏极中的另一者与所述第一节点连接；
所述第一晶体管为P型晶体管和N型晶体管中的一者，所述第二晶体管为P型晶体管和N型晶体管中的另一者。
可选的，在本申请一些实施例中，所述输出模块包括：
第三晶体管，所述第三晶体管的栅极与所述第一节点连接，所述第三晶体管的源极和漏极中的一者与所述第一电源端连接，所述第三晶体管的源极和漏极中的另一者与所述输出端连接；
第四晶体管，所述第四晶体管的栅极与所述第一节点连接，所述第四晶体管的源极和漏极中的一者与所述第二电源端连接，所述第四晶体管的源极和漏极中的另一者与所述输出端连接；
所述第三晶体管为P型晶体管和N型晶体管中的一者，所述第四晶体管为P型晶体管和N型晶体管中的另一者。
可选的，在本申请一些实施例中，所述输入模块还包括：
第五晶体管，所述第五晶体管的栅极与第二节点连接，所述第五晶体管的源极和漏极中的一者与第三电源端连接，所述第一晶体管的源极和漏极中的另一者与所述第一节点连接；
第六晶体管，所述第六晶体管的栅极与所述第二节点连接，所述第六晶体管的源极和漏极中的一者与第四电源端连接，所述第二晶体管的源极和漏极中的另一者与所述第一节点连接；
所述第一晶体管的源极和漏极中的另一者与所述第二节点连接，所述第五晶体管为P型晶体管和N型晶体管中的一者，所述第六晶体管为P型晶体管和N型晶体管中的另一者。
可选的，在本申请一些实施例中，所述输出模块还包括：
第七晶体管，所述第七晶体管的栅极与第三节点连接，所述第七晶体管的源极和漏极中的一者与第四节点连接，所述第一晶体管的源极和漏极中的另一者与所述输出端连接；
第八晶体管，所述第八晶体管的栅极与所述第三节点连接，所述第六晶体管的源极和漏极中的一者与所述第四节点连接，所述第二晶体管的源极和漏极中的另一者与所述输出端连接；
所述第三晶体管的源极和漏极中的另一者与所述第四节点连接，所述第四晶体管的源极和漏极中的另一者与所述第四节点连接；
所述第一信号控制端与所述第三节点连接，所述第七晶体管为P型晶体管和N型晶体管中的一者，所述第八晶体管为P型晶体管和N型晶体管中的另一者。
可选的，在本申请一些实施例中，所述输出模块还包括：
第七晶体管，所述第七晶体管的栅极与第三节点连接，所述第七晶体管的源极和漏极中的一者与第四节点连接，所述第一晶体管的源极和漏极中的另一者与所述输出端连接；
第八晶体管，所述第八晶体管的栅极与所述第三节点连接，所述第六晶体管的源极和漏极中的一者与所述第四节点连接，所述第二晶体管的源极和漏极中的另一者与所述输出端连接；
所述第三晶体管的源极和漏极中的另一者与所述第四节点连接，所述第四晶体管的源极和漏极中的另一者与所述第四节点连接；
所述第二信号控制端与所述第三节点连接，所述第七晶体管为P型晶体管和N型晶体管中的一者，所述第八晶体管为P型晶体管和N型晶体管中的另一者。
可选的，在本申请一些实施例中，所述第一电源端和所述第三电源端为同一电源端；所述第二电源端和所述第四电源端为同一电源端。
可选的，在本申请一些实施例中，所述第一电源端和所述第四电源端为同一电源端；所述第二电源端和所述第三电源端为同一电源端。
可选的，在本申请一些实施例中，所述第一电源端和所述第三电源端的信号为高电平信号或低电平信号，所述第二电源端和所述第四电源端的信号为低电平信号或高电平信号。
可选的，在本申请一些实施例中，所述第一电源端和所述第四电源端的信号为高电平信号或低电平信号，所述第二电源端和所述第三电源端的信号为低电平信号或高电平信号。
相对应地，本申请还提供一种显示装置，其包括驱动电路；所述驱动电路包括：
输入模块，所述输入模块分别与第一信号控制端、第二信号控制端和第一节点连接，所述输入模块用于在所述第一信号控制端和所述第二信号控制端的控制下向所述第一节点提供电平信号；
输出模块，所述输出模块分别与第一电源端、第二电源端、所述第一节点以及输出端连接，所述输出模块用于在所述第一节点的电平信号控制下向所述输出端提供所述第一电源端或所述第二电源端的信号。
可选的，在本申请一些实施例中，所述显示装置还包括：
时序控制器，所述时序控制器与所述驱动电路的第一信号控制端和第二信号控制端连接，
栅极驱动芯片，所述栅极驱动芯片与所述驱动电路的输出端连接。
可选的，在本申请一些实施例中，所述输入模块包括：
第一晶体管，所述第一晶体管的栅极与所述第一信号控制端连接，所述第一晶体管的源极和漏极中的一者与所述第二信号控制端连接，所述第一晶体管的源极和漏极中的另一者与所述第一节点连接；
第二晶体管，所述第二晶体管的栅极与所述第一信号控制端连接，所述第二晶体管的源极和漏极中的一者与所述第二信号控制端连接，所述第二晶体管的源极和漏极中的另一者与所述第一节点连接；
所述第一晶体管为P型晶体管和N型晶体管中的一者，所述第二晶体管为P型晶体管和N型晶体管中的另一者。
可选的，在本申请一些实施例中，所述输出模块包括：
第三晶体管，所述第三晶体管的栅极与所述第一节点连接，所述第三晶体管的源极和漏极中的一者与所述第一电源端连接，所述第三晶体管的源极和漏极中的另一者与所述输出端连接；
第四晶体管，所述第四晶体管的栅极与所述第一节点连接，所述第四晶体管的源极和漏极中的一者与所述第二电源端连接，所述第四晶体管的源极和漏极中的另一者与所述输出端连接；
所述第三晶体管为P型晶体管和N型晶体管中的一者，所述第四晶体管为P型晶体管和N型晶体管中的另一者。
可选的，在本申请一些实施例中，所述输入模块还包括：
第五晶体管，所述第五晶体管的栅极与第二节点连接，所述第五晶体管的源极和漏极中的一者与第三电源端连接，所述第一晶体管的源极和漏极中的另一者与所述第一节点连接；
第六晶体管，所述第六晶体管的栅极与所述第二节点连接，所述第六晶体管的源极和漏极中的一者与第四电源端连接，所述第二晶体管的源极和漏极中的另一者与所述第一节点连接；
所述第一晶体管的源极和漏极中的另一者与所述第二节点连接，所述第五晶体管为P型晶体管和N型晶体管中的一者，所述第六晶体管为P型晶体管和N型晶体管中的另一者。
可选的，在本申请一些实施例中，所述输出模块还包括：
第七晶体管，所述第七晶体管的栅极与第三节点连接，所述第七晶体管的源极和漏极中的一者与第四节点连接，所述第一晶体管的源极和漏极中的另一者与所述输出端连接；
第八晶体管，所述第八晶体管的栅极与所述第三节点连接，所述第六晶体管的源极和漏极中的一者与所述第四节点连接，所述第二晶体管的源极和漏极中的另一者与所述输出端连接；
所述第三晶体管的源极和漏极中的另一者与所述第四节点连接，所述第四晶体管的源极和漏极中的另一者与所述第四节点连接；
所述第一信号控制端与所述第三节点连接，所述第七晶体管为P型晶体管和N型晶体管中的一者，所述第八晶体管为P型晶体管和N型晶体管中的另一者。
可选的，在本申请一些实施例中，所述输出模块还包括：
第七晶体管，所述第七晶体管的栅极与第三节点连接，所述第七晶体管的源极和漏极中的一者与第四节点连接，所述第一晶体管的源极和漏极中的另一者与所述输出端连接；
第八晶体管，所述第八晶体管的栅极与所述第三节点连接，所述第六晶体管的源极和漏极中的一者与所述第四节点连接，所述第二晶体管的源极和漏极中的另一者与所述输出端连接；
所述第三晶体管的源极和漏极中的另一者与所述第四节点连接，所述第四晶体管的源极和漏极中的另一者与所述第四节点连接；
所述第二信号控制端与所述第三节点连接，所述第七晶体管为P型晶体管和N型晶体管中的一者，所述第八晶体管为P型晶体管和N型晶体管中的另一者。
可选的，在本申请一些实施例中，所述第一电源端和所述第三电源端为同一电源端；所述第二电源端和所述第四电源端为同一电源端。
可选的，在本申请一些实施例中，所述第一电源端和所述第四电源端为同一电源端；所述第二电源端和所述第三电源端为同一电源端。
可选的，在本申请一些实施例中，所述第一电源端和所述第三电源端的信号为高电平信号或低电平信号，所述第二电源端和所述第四电源端的信号为低电平信号或高电平信号。
 有益效果
本申请提供一种驱动电路及显示装置，其中驱动电路包括：输入模块，所述输入模块分别与第一信号控制端、第二信号控制端和第一节点连接，所述输入模块用于在所述第一信号控制端和所述第二信号控制端的控制下向所述第一节点提供电平信号；输出模块，所述输出模块分别与第一电源端、第二电源端、所述第一节点以及输出端连接，所述输出模块用于在所述第一节点的电平信号控制下向所述输出端提供所述第一电源端或所述第二电源端的信号。本申请在所述第一信号控制端和所述第二信号控制端的控制下向所述第一节点提供电平信号，再在所述第一节点的电平信号控制下向所述输出端提供所述第一电源端或所述第二电源端的信号，从而实现在两个控制信号控制下输出不同的电平信号，以解决时序控制器不能与不同的栅极驱动芯片直接匹配使用的问题。
 附图说明
为了更清楚地说明本申请实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图得到其他的附图。
图1为本申请提供的驱动电路的第一结构示意图；
图2为本申请提供的驱动电路的第二结构示意图；
图3为本申请提供的显示装置的示意图；
图4为本申请提供的驱动电路的第三结构示意图；
图5为本申请提供的驱动电路的第四结构示意图；
图6为本申请提供的驱动电路的第五结构示意图；
图7为本申请提供的驱动电路的第六结构示意图；
图8为本申请提供的驱动电路的第七结构示意图；
图9为本申请提供的驱动电路的第八结构示意图；
图10为本申请提供的驱动电路的第九结构示意图；
图11为本申请提供的驱动电路的第十结构示意图；
图12为本申请提供的驱动电路的第十一结构示意图；
图13为本申请提供的驱动电路的第十二结构示意图；
图14为本申请提供的驱动电路的第十三结构示意图。
 本发明的实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域技术人员在没有作出创造性劳动前提下所得到的所有其他实施例，都属于本申请保护的范围。
在本申请的描述中，需要理解的是，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个所述特征。在本申请的描述中，“多个”的含义是两个或两个以上，除非另有明确具体的限定。
本申请所有实施例中采用的晶体管可以为薄膜晶体管或场效应管或其他特性相同的器件，由于这里采用的晶体管的源极、漏极是对称的，所以其源极、漏极是可以互换的。在本申请实施例中，为区分晶体管除栅极之外的两极，将其中一极称为源极，另一极称为漏极。按附图中的形态规定控制模块的中间端为栅极、信号输入端为源极、输出端为漏极。此外本申请实施例所采用的晶体管可以包括 P 型晶体管和/或 N 型晶体管两种，其中，P 型晶体管在栅极为低电平时导通，在栅极为高电平时截止，N 型晶体管为在栅极为高电平时导通，在栅极为低电平时截止。
本申请提供一种驱动电路及显示装置，以下进行详细说明。需要说明的是，以下实施例的描述顺序不作为对本申请实施例优选顺序的限定。
请参阅图1，图1为本申请提供的驱动电路100的第一结构示意图。本申请提供一种驱动电路100，其包括输入模块10和输出模块20。
其中，所述输入模块10分别与第一信号控制端S1、第二信号控制端S2和第一节点P1连接，所述输入模块10用于在所述第一信号控制端S1和所述第二信号控制端S2的控制下向所述第一节点P1提供电平信号；
所述输出模块20分别与第一电源端V1、第二电源端V2、所述第一节点P1以及输出端OUT连接，所述输出模块20用于在所述第一节点P1的电平信号控制下向所述输出端OUT提供所述第一电源端V1或所述第二电源端V2的信号。
具体地，在工作过程中，输入模块10用于在所述第一信号控制端S1和所述第二信号控制端S2的控制下向所述第一节点P1提供电平信号，第一节点P1的电平信号可以为高电平或低电平，接着输出模块20在所述第一节点P1的电平信号控制下向所述输出端OUT提供所述第一电源端V1或所述第二电源端V2的信号，其中所述第一电源端V1的信号为高电平和低电平中的一者，所述第二电源端V2的信号为高电平和低电平中的另一者。在实际使用时，时序控制器与第一信号控制端S1以及第二信号控制端S2连接，而栅极驱动芯片与输出端OUT连接，再设置第一电源端V1和第二电源端V2的电平大小，则时序控制器通过输出端OUT向栅极驱动芯片输入准确的控制信号，从而解决时序控制器不能与不同的栅极驱动芯片直接匹配使用的问题。
请参阅图2，图2为本申请提供的驱动电路100的第二结构示意图。所述输入模块10包括第一晶体管T1和第二晶体管T2，其中，所述第一晶体管T1的栅极与所述第一信号控制端S1连接，所述第一晶体管T1的源极和漏极中的一者与所述第二信号控制端S2连接，所述第一晶体管T1的源极和漏极中的另一者与所述第一节点P1连接；所述第二晶体管T2的栅极与所述第一信号控制端S1连接，所述第二晶体管T2的源极和漏极中的一者与所述第二信号控制端S2连接，所述第二晶体管T2的源极和漏极中的另一者与所述第一节点P1连接；所述第一晶体管T1为P型晶体管和N型晶体管中的一者，所述第二晶体管T2为P型晶体管和N型晶体管中的另一者。
也即是，所述第一晶体管T1为P型晶体管和N型晶体管中的一者，所述第二晶体管T2为P型晶体管和N型晶体管中的另一者，所述第一晶体管T1和所述第二晶体管T2采用不同类型的晶体管，在所述第一信号控制端S1和所述第二信号控制端S2的控制下能交替地向所述第一节点P1输出不同电平的信号。同时所述第一晶体管T1和所述第二晶体管T2交替导通而不是持续工作，可以提高晶体管的寿命。
在一些实施例中，所述输出模块20包括第三晶体管T3和第四晶体管T4，所述第三晶体管T3的栅极与所述第一节点P1连接，所述第三晶体管T3的源极和漏极中的一者与所述第一电源端V1连接，所述第三晶体管T3的源极和漏极中的另一者与所述输出端OUT连接；所述第四晶体管T4的栅极与所述第一节点P1连接，所述第四晶体管T4的源极和漏极中的一者与所述第二电源端V2连接，所述第四晶体管T4的源极和漏极中的另一者与所述输出端OUT连接；所述第三晶体管T3为P型晶体管和N型晶体管中的一者，所述第四晶体管T4为P型晶体管和N型晶体管中的另一者。
也即是，所述第三晶体管T3为P型晶体管和N型晶体管中的一者，所述第四晶体管T4为P型晶体管和N型晶体管中的另一者，所述第三晶体管T3和所述第四晶体管T4采用不同类型的晶体管，根据所述第一节点P1的电平信号的高低而导通所述第三晶体管T3或所述第四晶体管T4，从而向所述输出端OUT提供所述第一电源端V1或所述第二电源端V2的信号。同时所述第三晶体管T3和所述第四晶体管T4交替导通而不是持续工作，可以提高晶体管的寿命。
具体地，在本实施例中，所述第一晶体管T1为N型晶体管，所述第二晶体管T2为P型晶体管，所述第三晶体管T3为P型晶体管，所述第四晶体管T4为N型晶体管。其中所述第一电源端V1接入高电平信号，所述第二电源端V2接入低电平信号。
在本实施例中，具体的工作过程如下：当所述第一信号控制端S1和所述第二信号控制端S2的信号均为高电平信号时，则第一晶体管T1导通，第二晶体管T2关闭，第一晶体管T1将所述第二信号控制端S2的高电平信号输送至第一节点P1，第一节点P1使得第四晶体管T4导通，第四晶体管T4将第二电源端V2的低电平信号输送至输出端OUT；当所述第一信号控制端S1和所述第二信号控制端S2的信号均为低电平信号时，则第一晶体管T1关闭，第二晶体管T2导通，第二晶体管T2将所述第二信号控制端S2的低电平信号输送至第一节点P1，第一节点P1使得第三晶体管T3导通，第三晶体管T3将第一电源端V1的高电平信号输送至输出端OUT；当所述第一信号控制端S1的信号为高电平信号，所述第二信号控制端S2的信号为低电平信号时，则第一晶体管T1导通，第二晶体管T2关闭，第一晶体管T1将所述第二信号控制端S2的低电平信号输送至第一节点P1，第一节点P1使得第三晶体管T3导通，第三晶体管T3将第一电源端V1的高电平信号输送至输出端OUT；当所述第一信号控制端S1的信号为低电平信号，所述第二信号控制端S2的信号为高电平信号时，所述第一信号控制端S1的信号均为低电平信号，所述第二信号控制端S2的信号为高电平信号时，则第一晶体管T1关闭，第二晶体管T2导通，第二晶体管T2将所述第二信号控制端S2的高电平信号输送至第一节点P1，第一节点P1使得第四晶体管T4导通，第四晶体管T4将第二电源端V2的低电平信号输送至输出端OUT。
请参阅图3，图3为本申请提供的显示装置的示意图。本申请实施例还提供一种显示装置1000，其包括如上述所述的驱动电路100。
所述显示装置1000还包括时序控制器200和栅极驱动芯片300，所述时序控制器200与所述驱动电路100的第一信号控制端S1和第二信号控制端S2连接，所述栅极驱动芯片300与所述驱动电路100的所述输出端OUT连接。
本申请的时序控制器200通过输出端OUT向栅极驱动芯片300输入准确的控制信号，从而解决时序控制器不能与不同的栅极驱动芯片直接匹配使用的问题。
该显示装置解决问题的原理与前述驱动电路100相似，因此该显示装置的实施和有益效果可以参见前述驱动电路100的描述，重复之处在此不再赘述。
请参阅图4，图4为本申请提供的驱动电路100的第三结构示意图。在本申请的其他实施例中，所述第一晶体管T1为P型晶体管，所述第二晶体管T2为N型晶体管，所述第三晶体管T3为P型晶体管，所述第四晶体管T4为N型晶体管。
请参阅图5，图5为本申请提供的驱动电路100的第四结构示意图。在本申请的其他实施例中，所述第一晶体管T1为P型晶体管，所述第二晶体管T2为N型晶体管，所述第三晶体管T3为N型晶体管，所述第四晶体管T4为P型晶体管。
请参阅图6，图6为本申请提供的驱动电路100的第五结构示意图。在本申请的其他实施例中，所述第一晶体管T1为N型晶体管，所述第二晶体管T2为P型晶体管，所述第三晶体管T3为N型晶体管，所述第四晶体管T4为P型晶体管。
请参阅图7，图7为本申请提供的驱动电路100的第六结构示意图。本实施例与图1所提供的驱动电路100不同的是：在本申请一些实施例中，所述输入模块10还包括：第五晶体管T5和第六晶体管T6，所述第五晶体管T5的栅极与第二节点P2连接，所述第五晶体管T5的源极和漏极中的一者与第三电源端V3连接，所述第一晶体管T1的源极和漏极中的另一者与所述第一节点P1连接；所述第六晶体管T6的栅极与所述第二节点P2连接，所述第六晶体管T6的源极和漏极中的一者与第四电源端V4连接，所述第二晶体管T2的源极和漏极中的另一者与所述第一节点P1连接；所述第一晶体管T1的源极和漏极中的另一者与所述第二节点P2连接，所述第五晶体管T5为P型晶体管和N型晶体管中的一者，所述第六晶体管T6为P型晶体管和N型晶体管中的另一者。
也即是，所述第五晶体管T5为P型晶体管和N型晶体管中的一者，所述第六晶体管T6为P型晶体管和N型晶体管中的另一者，所述第五晶体管T5和所述第六晶体管T6采用不同类型的晶体管，根据所述第二节点P2的电平信号的高低而导通所述第五晶体管T5或所述第六晶体管T6，从而可以向第一节点P1交替输出不同的电平信号。同时所述第五晶体管T5和所述第六晶体管T6交替导通而不是持续工作，可以提高晶体管的寿命。
具体地，在本实施例中，所述第五晶体管T5为N型晶体管，所述第六晶体管T6为P型晶体管。所述第一电源端V1和所述第三电源端V3的信号为高电平信号，所述第二电源端V2和所述第四电源端V4的信号为低电平信号。
在本实施例中，具体的工作过程如下：当所述第一信号控制端S1和所述第二信号控制端S2的信号均为高电平信号时，则第一晶体管T1导通，第二晶体管T2关闭，第一晶体管T1将所述第二信号控制端S2的高电平信号输送至第二节点P2，第二节点P2使得第六晶体管T6导通，第六晶体管T6将所述第四电源端V4的低电平信号输送至第一节点P1，第一节点P1使得第三晶体管T3导通，第三晶体管T3将第一电源端V1的高电平信号输送至输出端OUT；当所述第一信号控制端S1和所述第二信号控制端S2的信号均为低电平信号时，则第一晶体管T1关闭，第二晶体管T2导通，第二晶体管T2将所述第二信号控制端S2的低电平信号输送至第一节点P1，第一节点P1使得第三晶体管T3导通，第三晶体管T3将第一电源端V1的高电平信号输送至输出端OUT；当所述第一信号控制端S1的信号为高电平信号，所述第二信号控制端S2的信号为低电平信号时，则第一晶体管T1导通，第二晶体管T2关闭，第一晶体管T1将所述第二信号控制端S2的低电平信号输送至第二节点P2，第二节点P2使得第五晶体管T5导通，第五晶体管T5将所述第三电源端V3的高电平信号输送至第一节点P1，第一节点P1使得第四晶体管T4导通，第四晶体管T4将第二电源端V2的低电平信号输送至输出端OUT；当所述第一信号控制端S1的信号为低电平信号，所述第二信号控制端S2的信号为高电平信号时，则第一晶体管T1关闭，第二晶体管T2导通，第二晶体管T2将所述第二信号控制端S2的高电平信号输送至第一节点P1，第一节点P1使得第四晶体管T4导通，第四晶体管T4将第二电源端V2的低电平信号输送至输出端OUT。
请参阅图8，图8为本申请提供的驱动电路100的第七结构示意图。在一些实施例中，所述第一电源端V1和所述第三电源端V3为同一电源端；所述第二电源端V2和所述第四电源端V4为同一电源端。
请参阅图9，图9为本申请提供的驱动电路100的第八结构示意图。在本申请的其他实施例中，所述第五晶体管T5为P型晶体管，所述第六晶体管T6为N型晶体管。
在本申请的其他实施例中，所述第一电源端V1和所述第三电源端V3的信号为低电平信号，所述第二电源端V2和所述第四电源端V4的信号为高电平信号。所述第一电源端V1和所述第三电源端V3为同一电源端；所述第二电源端V2和所述第四电源端V4为同一电源端。
请参阅图10，图10为本申请提供的驱动电路100的第九结构示意图。在本申请的其他实施例中，所述第一电源端V1和所述第四电源端V4的信号为低电平信号，所述第二电源端V2和所述第三电源端V3的信号为高电平信号。所述第一电源端V1和所述第四电源端V4为同一电源端；所述第二电源端V2和所述第三电源端V3为同一电源端。
在本申请的其他实施例中，所述第一电源端V1和所述第四电源端V4的信号为高电平信号，所述第二电源端V2和所述第三电源端V3的信号为低电平信号。在本申请一些实施例中，所述第一电源端V1和所述第四电源端V4为同一电源端；所述第二电源端V2和所述第三电源端V3为同一电源端。
请参阅图11，图11为本申请提供的驱动电路100的第十结构示意图。本实施例与图7所提供的驱动电路100不同的是：所述输出模块20还包括：第七晶体管T7和第八晶体管T8，所述第七晶体管T7的栅极与第三节点P3连接，所述第七晶体管T7的源极和漏极中的一者与第四节点P4连接，所述第一晶体管T1的源极和漏极中的另一者与所述输出端OUT连接；所述第八晶体管T8的栅极与所述第三节点P3连接，所述第六晶体管T6的源极和漏极中的一者与所述第四节点P4连接，所述第二晶体管T2的源极和漏极中的另一者与所述输出端OUT连接；所述第三晶体管T3的源极和漏极中的另一者与所述第四节点P4连接，所述第四晶体管T4的源极和漏极中的另一者与所述第四节点P4连接；所述第一信号控制端S1与所述第三节点P3连接，所述第七晶体管T7为P型晶体管和N型晶体管中的一者，所述第八晶体管T8为P型晶体管和N型晶体管中的另一者。
也即是，在本实施例中，所述第七晶体管T7和所述第八晶体管T8连接在所述第四节点P4与所述输出端OUT之间，所述第七晶体管T7为P型晶体管和N型晶体管中的一者，所述第八晶体管T8为P型晶体管和N型晶体管中的另一者，利用所述第一信号控制端S1通过所述第一信号控制端S1控制所述第七晶体管T7和所述第八晶体管T8中的一个导通，从而向输出端OUT提供所述第一电源端V1或所述第二电源端V2的信号。
具体地，所述第七晶体管T7为P型晶体管，所述第八晶体管T8为N型晶体管。所述第一电源端V1和所述第三电源端V3的信号为高电平信号，所述第二电源端V2和所述第四电源端V4的信号为低电平信号。
在本实施例中，具体的工作过程如下：当所述第一信号控制端S1和所述第二信号控制端S2的信号均为高电平信号时，则第一晶体管T1导通，第二晶体管T2关闭，第七晶体管T7关闭，第八晶体管T8导通，第一晶体管T1将所述第二信号控制端S2的高电平信号输送至第二节点P2，第二节点P2使得第六晶体管T6导通，第六晶体管T6将所述第四电源端V4的低电平信号输送至第一节点P1，第一节点P1使得第三晶体管T3导通，第三晶体管T3将第一电源端V1的高电平信号输送至第四节点P4，第八晶体管T8将第一电源端V1的高电平信号输送至输出端OUT；
当所述第一信号控制端S1和所述第二信号控制端S2的信号均为低电平信号时，则第一晶体管T1关闭，第二晶体管T2导通，第七晶体管T7导通，第八晶体管T8关闭，第二晶体管T2将所述第二信号控制端S2的低电平信号输送至第一节点P1，第一节点P1使得第三晶体管T3导通，第三晶体管T3将第一电源端V1的高电平信号输送至第四节点P4，第七晶体管T7将第一电源端V1的高电平信号输送至输出端OUT；
当所述第一信号控制端S1的信号为高电平信号，所述第二信号控制端S2的信号为低电平信号时，则第一晶体管T1导通，第二晶体管T2关闭，第七晶体管T7关闭，第八晶体管T8导通，第一晶体管T1将所述第二信号控制端S2的低电平信号输送至第二节点P2，第二节点P2使得第五晶体管T5导通，第五晶体管T5将所述第三电源端V3的高电平信号输送至第一节点P1，第一节点P1使得第四晶体管T4导通，第四晶体管T4将第二电源端V2的低电平信号输送至第四节点P4，第八晶体管T8将第二电源端V2的低电平信号输送至输出端OUT；
当所述第一信号控制端S1的信号为低电平信号，所述第二信号控制端S2的信号为高电平信号时，则第一晶体管T1关闭，第二晶体管T2导通，第七晶体管T7导通，第八晶体管T8关闭，第二晶体管T2将所述第二信号控制端S2的高电平信号输送至第一节点P1，第一节点P1使得第四晶体管T4导通，第四晶体管T4将第二电源端V2的低电平信号输送至第四节点P4，第七晶体管T7将第二电源端V2的低电平信号输送至输出端OUT。
请参阅图12，图12为本申请提供的驱动电路100的第十一结构示意图。在本申请的其他实施例中，所述第七晶体管T7为N型晶体管，所述第八晶体管T8为P型晶体管。
请参阅图13，图13为本申请提供的驱动电路100的第十二结构示意图。本实施例与图7所提供的驱动电路100不同的是：所述输出模块20还包括：第七晶体管T7和第八晶体管T8，所述第七晶体管T7的栅极与第三节点P3连接，所述第七晶体管T7的源极和漏极中的一者与第四节点P4连接，所述第一晶体管T1的源极和漏极中的另一者与所述输出端OUT连接；所述第八晶体管T8的栅极与所述第三节点P3连接，所述第六晶体管T6的源极和漏极中的一者与所述第四节点P4连接，所述第二晶体管T2的源极和漏极中的另一者与所述输出端OUT连接；所述第三晶体管T3的源极和漏极中的另一者与所述第四节点P4连接，所述第四晶体管T4的源极和漏极中的另一者与所述第四节点P4连接；所述第二信号控制端S2与所述第三节点P3连接，所述第七晶体管T7为P型晶体管和N型晶体管中的一者，所述第八晶体管T8为P型晶体管和N型晶体管中的另一者。
也即是，在本实施例中，所述第七晶体管T7和所述第八晶体管T8连接在所述第四节点P4与所述输出端OUT之间，所述第七晶体管T7为P型晶体管和N型晶体管中的一者，所述第八晶体管T8为P型晶体管和N型晶体管中的另一者，利用所述第二信号控制端S2通过所述第一信号控制端S1控制所述第七晶体管T7和所述第八晶体管T8中的一个导通，从而向输出端OUT提供所述第一电源端V1或所述第二电源端V2的信号。
具体地，所述第七晶体管T7为P型晶体管，所述第八晶体管T8为N型晶体管。所述第一电源端V1和所述第三电源端V3的信号为高电平信号，所述第二电源端V2和所述第四电源端V4的信号为低电平信号。
在本实施例中，具体的工作过程如下：当所述第一信号控制端S1和所述第二信号控制端S2的信号均为高电平信号时，则第一晶体管T1导通，第二晶体管T2关闭，第七晶体管T7关闭，第八晶体管T8导通，第一晶体管T1将所述第二信号控制端S2的高电平信号输送至第二节点P2，第二节点P2使得第六晶体管T6导通，第六晶体管T6将所述第四电源端V4的低电平信号输送至第一节点P1，第一节点P1使得第三晶体管T3导通，第三晶体管T3将第一电源端V1的高电平信号输送至第四节点P4，第八晶体管T8将第一电源端V1的高电平信号输送至输出端OUT；
当所述第一信号控制端S1和所述第二信号控制端S2的信号均为低电平信号时，则第一晶体管T1关闭，第二晶体管T2导通，第七晶体管T7导通，第八晶体管T8关闭，第二晶体管T2将所述第二信号控制端S2的低电平信号输送至第一节点P1，第一节点P1使得第三晶体管T3导通，第三晶体管T3将第一电源端V1的高电平信号输送至第四节点P4，第七晶体管T7将第一电源端V1的高电平信号输送至输出端OUT；
当所述第一信号控制端S1的信号为高电平信号，所述第二信号控制端S2的信号为低电平信号时，则第一晶体管T1导通，第二晶体管T2关闭，第七晶体管T7导通，第八晶体管T8关闭，第一晶体管T1将所述第二信号控制端S2的低电平信号输送至第二节点P2，第二节点P2使得第五晶体管T5导通，第五晶体管T5将所述第三电源端V3的高电平信号输送至第一节点P1，第一节点P1使得第四晶体管T4导通，第四晶体管T4将第二电源端V2的低电平信号输送至第四节点P4，第七晶体管T7将第二电源端V2的低电平信号输送至输出端OUT；
当所述第一信号控制端S1的信号为低电平信号，所述第二信号控制端S2的信号为高电平信号时，则第一晶体管T1关闭，第二晶体管T2导通，第七晶体管T7关闭，第八晶体管T8导通，第二晶体管T2将所述第二信号控制端S2的高电平信号输送至第一节点P1，第一节点P1使得第四晶体管T4导通，第四晶体管T4将第二电源端V2的低电平信号输送至第四节点P4，第八晶体管T8将第二电源端V2的低电平信号输送至输出端OUT。
请参阅图14，图14为本申请提供的驱动电路100的第十三结构示意图。在本申请的其他实施例中，所述第七晶体管T7为N型晶体管，所述第八晶体管T8为P型晶体管。
以上对本申请实施例所提供的一种驱动电路及显示装置进行了详细介绍，本文中应用了具体个例对本申请的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本申请的方法及其核心思想；同时，对于本领域的技术人员，依据本申请的思想，在具体实施方式及应用范围上均会有改变之处，综上，本说明书内容不应理解为对本申请的限制。

Claims (20)

  1. 一种驱动电路，其中，包括：
    输入模块，所述输入模块分别与第一信号控制端、第二信号控制端和第一节点连接，所述输入模块用于在所述第一信号控制端和所述第二信号控制端的控制下向所述第一节点提供电平信号；
    输出模块，所述输出模块分别与第一电源端、第二电源端、所述第一节点以及输出端连接，所述输出模块用于在所述第一节点的电平信号控制下向所述输出端提供所述第一电源端或所述第二电源端的信号。
  2. 根据权利要求1所述的驱动电路，其中，所述输入模块包括：
    第一晶体管，所述第一晶体管的栅极与所述第一信号控制端连接，所述第一晶体管的源极和漏极中的一者与所述第二信号控制端连接，所述第一晶体管的源极和漏极中的另一者与所述第一节点连接；
    第二晶体管，所述第二晶体管的栅极与所述第一信号控制端连接，所述第二晶体管的源极和漏极中的一者与所述第二信号控制端连接，所述第二晶体管的源极和漏极中的另一者与所述第一节点连接；
    所述第一晶体管为P型晶体管和N型晶体管中的一者，所述第二晶体管为P型晶体管和N型晶体管中的另一者。
  3. 根据权利要求1所述的驱动电路，其中，所述输出模块包括：
    第三晶体管，所述第三晶体管的栅极与所述第一节点连接，所述第三晶体管的源极和漏极中的一者与所述第一电源端连接，所述第三晶体管的源极和漏极中的另一者与所述输出端连接；
    第四晶体管，所述第四晶体管的栅极与所述第一节点连接，所述第四晶体管的源极和漏极中的一者与所述第二电源端连接，所述第四晶体管的源极和漏极中的另一者与所述输出端连接；
    所述第三晶体管为P型晶体管和N型晶体管中的一者，所述第四晶体管为P型晶体管和N型晶体管中的另一者。
  4. 根据权利要求2所述的驱动电路，其中，所述输入模块还包括：
    第五晶体管，所述第五晶体管的栅极与第二节点连接，所述第五晶体管的源极和漏极中的一者与第三电源端连接，所述第一晶体管的源极和漏极中的另一者与所述第一节点连接；
    第六晶体管，所述第六晶体管的栅极与所述第二节点连接，所述第六晶体管的源极和漏极中的一者与第四电源端连接，所述第二晶体管的源极和漏极中的另一者与所述第一节点连接；
    所述第一晶体管的源极和漏极中的另一者与所述第二节点连接，所述第五晶体管为P型晶体管和N型晶体管中的一者，所述第六晶体管为P型晶体管和N型晶体管中的另一者。
  5. 根据权利要求3所述的驱动电路，其中，所述输出模块还包括：
    第七晶体管，所述第七晶体管的栅极与第三节点连接，所述第七晶体管的源极和漏极中的一者与第四节点连接，所述第一晶体管的源极和漏极中的另一者与所述输出端连接；
    第八晶体管，所述第八晶体管的栅极与所述第三节点连接，所述第六晶体管的源极和漏极中的一者与所述第四节点连接，所述第二晶体管的源极和漏极中的另一者与所述输出端连接；
    所述第三晶体管的源极和漏极中的另一者与所述第四节点连接，所述第四晶体管的源极和漏极中的另一者与所述第四节点连接；
    所述第一信号控制端与所述第三节点连接，所述第七晶体管为P型晶体管和N型晶体管中的一者，所述第八晶体管为P型晶体管和N型晶体管中的另一者。
  6. 根据权利要求3所述的驱动电路，其中，所述输出模块还包括：
    第七晶体管，所述第七晶体管的栅极与第三节点连接，所述第七晶体管的源极和漏极中的一者与第四节点连接，所述第一晶体管的源极和漏极中的另一者与所述输出端连接；
    第八晶体管，所述第八晶体管的栅极与所述第三节点连接，所述第六晶体管的源极和漏极中的一者与所述第四节点连接，所述第二晶体管的源极和漏极中的另一者与所述输出端连接；
    所述第三晶体管的源极和漏极中的另一者与所述第四节点连接，所述第四晶体管的源极和漏极中的另一者与所述第四节点连接；
    所述第二信号控制端与所述第三节点连接，所述第七晶体管为P型晶体管和N型晶体管中的一者，所述第八晶体管为P型晶体管和N型晶体管中的另一者。
  7. 根据权利要求4所述的驱动电路，其中，所述第一电源端和所述第三电源端为同一电源端；所述第二电源端和所述第四电源端为同一电源端。
  8. 根据权利要求4所述的驱动电路，其中，所述第一电源端和所述第四电源端为同一电源端；所述第二电源端和所述第三电源端为同一电源端。
  9. 根据权利要求7所述的驱动电路，其中，所述第一电源端和所述第三电源端的信号为高电平信号或低电平信号，所述第二电源端和所述第四电源端的信号为低电平信号或高电平信号。
  10. 根据权利要求8所述的驱动电路，其中，所述第一电源端和所述第四电源端的信号为高电平信号或低电平信号，所述第二电源端和所述第三电源端的信号为低电平信号或高电平信号。
  11. 一种显示装置，其中，包括驱动电路；所述驱动电路包括：
    输入模块，所述输入模块分别与第一信号控制端、第二信号控制端和第一节点连接，所述输入模块用于在所述第一信号控制端和所述第二信号控制端的控制下向所述第一节点提供电平信号；
    输出模块，所述输出模块分别与第一电源端、第二电源端、所述第一节点以及输出端连接，所述输出模块用于在所述第一节点的电平信号控制下向所述输出端提供所述第一电源端或所述第二电源端的信号。
  12. 根据权利要求11所述的显示装置，其中，所述显示装置还包括：
    时序控制器，所述时序控制器与所述驱动电路的第一信号控制端和第二信号控制端连接，
    栅极驱动芯片，所述栅极驱动芯片与所述驱动电路的输出端连接。
  13. 根据权利要求11所述的显示装置，其中，所述输入模块包括：
    第一晶体管，所述第一晶体管的栅极与所述第一信号控制端连接，所述第一晶体管的源极和漏极中的一者与所述第二信号控制端连接，所述第一晶体管的源极和漏极中的另一者与所述第一节点连接；
    第二晶体管，所述第二晶体管的栅极与所述第一信号控制端连接，所述第二晶体管的源极和漏极中的一者与所述第二信号控制端连接，所述第二晶体管的源极和漏极中的另一者与所述第一节点连接；
    所述第一晶体管为P型晶体管和N型晶体管中的一者，所述第二晶体管为P型晶体管和N型晶体管中的另一者。
  14. 根据权利要求11所述的显示装置，其中，所述输出模块包括：
    第三晶体管，所述第三晶体管的栅极与所述第一节点连接，所述第三晶体管的源极和漏极中的一者与所述第一电源端连接，所述第三晶体管的源极和漏极中的另一者与所述输出端连接；
    第四晶体管，所述第四晶体管的栅极与所述第一节点连接，所述第四晶体管的源极和漏极中的一者与所述第二电源端连接，所述第四晶体管的源极和漏极中的另一者与所述输出端连接；
    所述第三晶体管为P型晶体管和N型晶体管中的一者，所述第四晶体管为P型晶体管和N型晶体管中的另一者。
  15. 根据权利要求13所述的显示装置，其中，所述输入模块还包括：
    第五晶体管，所述第五晶体管的栅极与第二节点连接，所述第五晶体管的源极和漏极中的一者与第三电源端连接，所述第一晶体管的源极和漏极中的另一者与所述第一节点连接；
    第六晶体管，所述第六晶体管的栅极与所述第二节点连接，所述第六晶体管的源极和漏极中的一者与第四电源端连接，所述第二晶体管的源极和漏极中的另一者与所述第一节点连接；
    所述第一晶体管的源极和漏极中的另一者与所述第二节点连接，所述第五晶体管为P型晶体管和N型晶体管中的一者，所述第六晶体管为P型晶体管和N型晶体管中的另一者。
  16. 根据权利要求14所述的显示装置，其中，所述输出模块还包括：
    第七晶体管，所述第七晶体管的栅极与第三节点连接，所述第七晶体管的源极和漏极中的一者与第四节点连接，所述第一晶体管的源极和漏极中的另一者与所述输出端连接；
    第八晶体管，所述第八晶体管的栅极与所述第三节点连接，所述第六晶体管的源极和漏极中的一者与所述第四节点连接，所述第二晶体管的源极和漏极中的另一者与所述输出端连接；
    所述第三晶体管的源极和漏极中的另一者与所述第四节点连接，所述第四晶体管的源极和漏极中的另一者与所述第四节点连接；
    所述第一信号控制端与所述第三节点连接，所述第七晶体管为P型晶体管和N型晶体管中的一者，所述第八晶体管为P型晶体管和N型晶体管中的另一者。
  17. 根据权利要求14所述的显示装置，其中，所述输出模块还包括：
    第七晶体管，所述第七晶体管的栅极与第三节点连接，所述第七晶体管的源极和漏极中的一者与第四节点连接，所述第一晶体管的源极和漏极中的另一者与所述输出端连接；
    第八晶体管，所述第八晶体管的栅极与所述第三节点连接，所述第六晶体管的源极和漏极中的一者与所述第四节点连接，所述第二晶体管的源极和漏极中的另一者与所述输出端连接；
    所述第三晶体管的源极和漏极中的另一者与所述第四节点连接，所述第四晶体管的源极和漏极中的另一者与所述第四节点连接；
    所述第二信号控制端与所述第三节点连接，所述第七晶体管为P型晶体管和N型晶体管中的一者，所述第八晶体管为P型晶体管和N型晶体管中的另一者。
  18. 根据权利要求15所述的显示装置，其中，所述第一电源端和所述第三电源端为同一电源端；所述第二电源端和所述第四电源端为同一电源端。
  19. 根据权利要求15所述的显示装置，其中，所述第一电源端和所述第四电源端为同一电源端；所述第二电源端和所述第三电源端为同一电源端。
  20. 根据权利要求18所述的显示装置，其中，所述第一电源端和所述第三电源端的信号为高电平信号或低电平信号，所述第二电源端和所述第四电源端的信号为低电平信号或高电平信号。
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