WO2023178759A1 - Oled显示面板及其制作方法 - Google Patents

Oled显示面板及其制作方法 Download PDF

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Publication number
WO2023178759A1
WO2023178759A1 PCT/CN2022/086984 CN2022086984W WO2023178759A1 WO 2023178759 A1 WO2023178759 A1 WO 2023178759A1 CN 2022086984 W CN2022086984 W CN 2022086984W WO 2023178759 A1 WO2023178759 A1 WO 2023178759A1
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WIPO (PCT)
Prior art keywords
layer
via hole
display panel
oled display
thin film
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Ceased
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PCT/CN2022/086984
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English (en)
French (fr)
Inventor
覃事建
陈小童
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Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Priority to US17/755,043 priority Critical patent/US12495681B2/en
Publication of WO2023178759A1 publication Critical patent/WO2023178759A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/122—Pixel-defining structures or layers, e.g. banks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/80—Constructional details
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/80—Constructional details
    • H10K50/84—Passivation; Containers; Encapsulations
    • H10K50/844—Encapsulations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/124—Insulating layers formed between TFT elements and OLED elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/126—Shielding, e.g. light-blocking means over the TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/87—Passivation; Containers; Encapsulations
    • H10K59/873—Encapsulations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass

Definitions

  • the present invention relates to the technical field of display panels, and in particular to an OLED display panel and a manufacturing method thereof.
  • OLED organic light emitting devices
  • LCD liquid-crystal display
  • OLED organic light emitting devices
  • LCD liquid-crystal display
  • OLED has the advantages of self-illumination, fast response, wide viewing angle, high brightness, bright colors, and thinness.
  • OLED has the advantages of being able to The characteristics of flexibility are considered to be the next generation display technology.
  • OLEDs are divided into two categories: bottom emission (Bottom Emission) and top emission (Top Emission) devices.
  • bottom emission has a relatively low aperture rate and is used in high PPI (Pixels Per Inch, pixel density). /pixels per inch) products are limited.
  • Large-sized top-emitting devices also have the problem that the transparent cathode cannot be made too thick, causing power supply voltage drop (IR Drop).
  • IJP ink-jet Printing
  • IJP ink-jet Printing
  • the purpose of the present invention is to provide an OLED display panel and a manufacturing method thereof, which can effectively isolate and cut off the water and oxygen propagation paths between adjacent light-emitting layers (pixels), thereby increasing the reliability of the display area and the use of the OLED display panel. life.
  • the present invention provides an OLED display panel including a substrate, a thin film transistor layer, a flat layer and a pixel definition layer.
  • the thin film transistor layer is disposed on one side of the substrate.
  • the flat layer is provided on a side of the thin film transistor layer away from the substrate.
  • the pixel definition layer is provided on a side of the flat layer away from the thin film transistor layer, wherein the flat layer is provided with a first via hole, and the pixel definition layer is provided with a second via hole and a through hole, The first via hole and the second via hole are connected;
  • the OLED display panel also includes a light emitting device layer, and the light emitting device layer includes anodes arranged sequentially on the side of the flat layer away from the thin film transistor layer. , a luminescent layer and a cathode, the anode is electrically connected to the thin film transistor layer, the luminescent layer is arranged in the through hole, the cathode covers the pixel definition layer, the first via hole, the second via hole and the light-emitting layer.
  • the OLED display panel includes a display area and a non-display area arranged at the periphery of the display area, and the first via hole and the second via hole are provided with the display area and between the non-display areas.
  • the display area includes a plurality of pixel units, and the first via hole and the second via hole are provided between at least two adjacent pixel units.
  • the OLED display panel further includes an encapsulation layer, the flat layer and the pixel definition layer are provided in the display area, and the flat layer has a third layer close to the non-display area.
  • the pixel definition layer has a second side close to the non-display area, and the encapsulation layer covers the cathode, the first side, and the second side of the display area.
  • the OLED display panel further includes a first metal layer disposed between the substrate and the thin film transistor layer.
  • the thin film transistor layer includes a plurality of thin film transistors arranged in an array and A third via hole is provided between the thin film transistors, and the third via hole is provided corresponding to the first via hole.
  • the first metal layer includes a light-shielding layer provided corresponding to the thin film transistor and a first metal wiring layer provided corresponding to the first via hole, and the cathode passes through the first via hole.
  • Three via holes are electrically connected to the first metal wiring layer.
  • the thin film transistor layer includes a buffer layer, a semiconductor layer, a gate insulating layer, a gate layer, and an interlayer which are sequentially disposed on the side of the first metal layer away from the substrate.
  • the second metal layer includes a source and drain layer connected to the semiconductor layer and a first metal wiring electrode provided corresponding to the first metal wiring layer.
  • the first metal wiring layer The wiring electrode electrically connects the cathode and the first metal wiring layer through the third via hole.
  • the OLED display panel further includes a third metal layer disposed on a side of the thin film transistor layer away from the substrate, and the third metal layer includes the anode and the anode.
  • a second metal wiring electrode is provided on the same layer, and the second metal wiring electrode is electrically connected to the first metal wiring electrode.
  • the first via hole and the penetrating second via hole expose at least part of the second metal wiring electrode, and the cathode passes through the first via hole, the second via hole, and the second via hole.
  • Two via holes are connected to the second metal wiring electrode.
  • the present invention also provides a method for manufacturing a display panel, which includes the following steps:
  • a first via hole is formed on the flat layer, a second via hole and a through hole are formed on the pixel definition layer, and the first via hole and the second via hole are connected; the OLED display
  • the panel further includes a light-emitting device layer.
  • the light-emitting device layer includes an anode, a light-emitting layer and a cathode formed in sequence on a side of the flat layer away from the thin film transistor layer.
  • the anode and the thin film transistor layer are electrically connected, so The luminescent layer is formed in the through hole, and the cathode covers the pixel definition layer, the first via hole, the second via hole and the luminescent layer.
  • the OLED display panel includes a display area and a non-display area formed around the display area, and the first via hole and the second via hole form the between the display area and the non-display area.
  • the display area includes a plurality of pixel units, and the first via hole and the second via hole are formed between at least two adjacent pixel units.
  • the OLED display panel further includes an encapsulation layer, the flat layer and the pixel definition layer are formed in the display area, and the flat layer has a structure close to the non-display layer.
  • the pixel definition layer has a second side close to the non-display area, and the encapsulation layer covers the cathode, the first side, and the second side of the display area.
  • the OLED display panel further includes forming a first metal layer between the substrate and the thin film transistor layer, and the thin film transistor layer includes a plurality of arrays arranged in A thin film transistor and a third via hole formed between the thin film transistor, the third via hole being formed corresponding to the first via hole.
  • the first metal layer includes a light-shielding layer formed corresponding to the thin film transistor and a first metal wiring layer formed corresponding to the first via hole, and the cathode passes through The third via hole is electrically connected to the first metal wiring layer.
  • the thin film transistor layer includes a buffer layer, a semiconductor layer, a gate insulating layer, and a gate layer that are sequentially arranged on the side of the first metal layer away from the substrate. , an interlayer dielectric layer and a second metal layer, the second metal layer includes a source and drain layer connected to the semiconductor layer and a first metal wiring electrode formed corresponding to the first metal wiring layer, the The first metal wiring electrode electrically connects the cathode and the first metal wiring layer through the third via hole.
  • the OLED display panel further includes a third metal layer disposed on a side of the thin film transistor layer away from the substrate, and the third metal layer includes the anode and The anode is provided with a second metal wiring electrode on the same layer, and the second metal wiring electrode is electrically connected to the first metal wiring electrode.
  • the first via hole and the penetrating second via hole expose at least part of the second metal wiring electrode, and the cathode passes through the first via hole,
  • the second via hole is connected to the second metal wiring electrode.
  • the pixel definition layer further includes a hydrophilic organic layer and a hydrophobic layer deposited on the hydrophilic organic layer.
  • the thickness of the hydrophilic organic layer is greater than or equal to The thickness of the hydrophobic layer.
  • the encapsulation layer further includes a first inorganic encapsulation layer, an organic encapsulation layer is ink-jet printed on the first inorganic encapsulation layer, and a third encapsulation layer is deposited on the organic encapsulation layer.
  • Two inorganic encapsulation layers or a combination thereof, the first inorganic encapsulation layer and the second inorganic encapsulation layer are made of silicon oxide, and the organic encapsulation layer is made of silicon nitride or silicon oxynitride.
  • the present invention also has the following effects.
  • the present invention has separate openings on the two film layers of the pixel definition layer (PDL) and the flat layer (PLN).
  • the via hole i.e., the through-hole first via hole and the second via hole
  • a third via hole is provided between the plurality of thin film transistors corresponding to the first via hole, and the cathode passes through the third via hole and the first metal wiring layer provided corresponding to the first via hole ( As a VSS ground voltage trace) electrical connection, it can also effectively reduce the problem of power supply voltage drop (IR Drop) of the top-emitting device of a large-size OLED display panel, thereby making the display more uniform.
  • the pixel definition layer and the flat layer may not be provided in the non-display area (NDA), that is, the non-display area is fully covered by the encapsulation layer, effectively isolating the intrusion of external water, oxygen/moisture, thereby increasing the display area. The reliability and service life of most devices.
  • Figure 1A is a first cross-sectional view of an OLED display panel according to an embodiment of the present invention.
  • Figure 1B is a second cross-section embodiment diagram of the OLED display panel of the present invention.
  • Figure 2 is a schematic plan view of the OLED display panel of the present invention.
  • Figure 3 is a cross-sectional structural view of the substrate of Figure 1A or Figure 1B;
  • FIG. 4 is a diagram of another embodiment of the OLED display panel of the present invention.
  • 5 to 16 are cross-sectional structural views of the manufacturing method of the OLED display panel of the present invention.
  • Figure 17 is a block flow chart of the manufacturing method of the OLED display panel of the present invention.
  • FIG. 1A and FIG. 1B are first and second cross-sectional views of the OLED display panel according to the present invention.
  • the present invention provides an OLED display panel 100 including a substrate 101, a thin film transistor layer (not labeled), a flat layer 150 and a pixel definition layer 160.
  • the thin film transistor layer is provided on one side of the substrate 101 .
  • the flat layer 150 is provided on a side of the thin film transistor layer away from the substrate 101 .
  • the pixel definition layer 160 is disposed on a side of the flat layer 150 away from the thin film transistor layer.
  • the flat layer 150 is provided with a first via hole 180
  • the pixel definition layer 160 is provided with a second via hole 182 and a through hole 184
  • the first via hole 180 and the second via hole 182 are connected with each other. .
  • the OLED display panel 100 further includes a light-emitting device layer 170.
  • the light-emitting device layer 170 includes an anode 172, a light-emitting layer 174 and a cathode 176 sequentially arranged on the side of the flat layer 150 away from the thin film transistor layer.
  • the anode 172 is electrically connected to the thin film transistor layer
  • the light-emitting layer 174 is disposed in the through hole 184
  • the cathode 176 covers the pixel definition layer 160, the first via hole 180, the second via hole 172 and the thin film transistor layer 172. holes 182 and the light-emitting layer 174 .
  • the OLED display panel 100 includes a display area AA and a non-display area NDA arranged at the periphery of the display area AA.
  • the first via hole 180 and the third Two via holes 182 are provided between the display area AA and the non-display area NDA.
  • FIG. 2 is a schematic plan view of the OLED display panel of the present invention.
  • the display area AA includes a plurality of pixel units P, and each pixel unit P includes at least three sub-pixels, such as red sub-pixels, green sub-pixels and blue sub-pixels.
  • the first via hole 180 and the second via hole 182 are provided between at least two adjacent pixel units P.
  • at least one penetrating first via hole 180 and the second via hole 182 is provided between two adjacent pixel units P.
  • three penetrating first via holes 180 and second via holes 182 may also be provided between two adjacent pixel units P.
  • the number of the first via holes 180 and the second via holes 182 close to the non-display area NDA may be three (but not limited to this), which is greater than the number provided in the display area AA.
  • the number of the first via holes 180 and the second via holes 182 close to the non-display area NDA may also be equal to the number provided in the display area AA, and may be changed as needed. In the embodiment shown in FIG. 1A and FIG.
  • the OLED display panel 100 further includes an encapsulation layer 190 , the flat layer 150 and the pixel definition layer 160 are disposed in the display area AA, and the flat layer 150 has a structure close to the A first side 152 of the non-display area NDA, the pixel definition layer 160 has a second side 166 close to the non-display area NDA.
  • the encapsulation layer 190 covers the cathode 176, the first side 152, and the second side 166 of the display area AA.
  • the non-display area NDA does not include the pixel definition layer 160 and the flat layer 150. That is, the non-display area NDA is fully covered by the encapsulation layer 190, effectively blocking the intrusion of external water, oxygen/humidity, thereby increasing the display The reliability and service life of most devices in area AA.
  • the encapsulation layer 190 as shown in FIG. 1A and FIG. 1B also includes a first inorganic encapsulation layer 192, an organic encapsulation layer 194 and a second inorganic encapsulation layer 196.
  • the encapsulation layer 190 also includes the above three or more layers or other different combinations, which is not limited.
  • the material of the first inorganic encapsulation layer 192 and the second inorganic encapsulation layer 196 is preferably silicon oxide (SiO), and the material of the organic encapsulation layer 194 is preferably silicon nitride (SiN) or silicon oxynitride (SiNxOy). .
  • the substrate 101 in this embodiment can be a rigid layer or a flexible layer.
  • the substrate 101 can be plain glass, PE resin or other suitable materials.
  • a number of polyimide (PI) and barrier layers can be provided on the plain glass.
  • the single-layer or multi-layer stacked structure of the layer is not limited.
  • the substrate 101 also includes a substrate 102 (plain glass), an amorphous silicon layer 103 (as a sacrificial layer), a first photoresist layer 104 (polyimide PI), The first barrier layer 105 (material is, for example, silicon oxide), the second photoresist layer 106 (polyimide PI), the second barrier layer 107 (material is, for example, SiO), or a combination thereof.
  • the OLED display panel 100 further includes a first metal layer 110 disposed between the substrate 101 and the thin film transistor layer.
  • the thin film transistor layer includes a plurality of thin film transistors TFT arranged in an array and disposed on the thin film transistor.
  • the third via hole 186 between the TFTs is provided corresponding to the first via hole 180.
  • the first metal layer 110 includes a light shielding layer 111 provided corresponding to the thin film transistor TFT and a light shielding layer 111 provided corresponding to the thin film transistor TFT.
  • the first metal wiring layer 112 is provided with the first via hole 180 , and the cathode 176 is electrically connected to the first metal wiring layer 112 through the third via hole 186 .
  • the thin film transistor layer includes a buffer layer 120, a semiconductor layer (IGZO/IGTO) 132, a gate insulating layer 134, and a gate layer that are sequentially disposed on the side of the first metal layer 110 away from the substrate 101. 136.
  • the second metal layer 135 includes a source and drain layer 138 connected to the semiconductor layer 132 and a first metal wiring electrode 139 provided corresponding to the first metal wiring layer 112.
  • the first metal wiring electrode 139 electrically connect the cathode 176 and the first metal wiring layer 112 through the third via hole 186 .
  • the OLED display panel 100 further includes a third metal layer 178 disposed on the side of the thin film transistor layer away from the substrate 101 .
  • the third metal layer 178 includes the anode 172 and the anode 172 disposed in the same layer.
  • the second metal wiring electrode 177 is electrically connected to the first metal wiring electrode 139 , and the first via hole 180 and the penetrating second via hole 182 are exposed At least part of the second metal wiring electrode 177 , the cathode 176 is connected to the second metal wiring electrode 177 through the first via hole 180 and the second via hole 182 .
  • the cathode 176 communicates with the first metal wiring layer 112 (as a VSS ground) through the third via hole 186 Voltage wiring) electrical connection can effectively reduce the problem of power supply voltage drop (IR Drop) of the top-emitting device of the large-size OLED display panel 100, thereby making the display more uniform.
  • IR Drop power supply voltage drop
  • the pixel definition layer 160 can be configured as two layers, including a hydrophilic organic layer 162 and a hydrophobic layer deposited on the hydrophilic organic layer 162 Layer 164.
  • the bottom layer is a hydrophilic organic layer 162, so that the ink can be spread to the maximum layer
  • the top layer is a hydrophobic layer 164, so that the ink does not remain on the surface.
  • the thickness of the hydrophilic organic layer 162 is greater than or equal to the thickness of the hydrophobic layer 164. In a preferred embodiment, the thickness of the hydrophilic organic layer 162 is 4000 ⁇ , and the thickness of the hydrophobic layer 164 is 10000 ⁇ .
  • FIGS. 5 to 17 are cross-sectional schematic diagrams and flow diagrams of the manufacturing method of the OLED display panel of the present invention.
  • the present invention also provides a method for manufacturing a flexible OLED display panel 100.
  • the manufacturing method includes the following steps:
  • Step S10 Provide a substrate 101;
  • Step S20 Form a thin film transistor layer (not labeled) on one side of the substrate 101.
  • Step S30 Form a flat layer 150 on a side of the thin film transistor layer away from the substrate 101.
  • Step S40 Form a pixel definition layer 160 on a side of the flat layer 150 away from the thin film transistor layer.
  • a first via hole 180 is formed on the flat layer 150
  • a second via hole 182 and a through hole 184 are formed on the pixel definition layer 160
  • the first via hole 180 and the second via hole 182 are connected with each other.
  • the OLED display panel 100 further includes a light-emitting device layer 170.
  • the light-emitting device layer 170 includes an anode 172, a light-emitting layer 174 and a cathode 176 sequentially formed on the side of the flat layer 150 away from the thin film transistor layer.
  • 172 is electrically connected to the thin film transistor layer
  • the light-emitting layer 174 is formed in the through hole 184
  • the cathode 176 covers the pixel definition layer 160, the first via hole 180, the second via hole 172 and the thin film transistor layer 172. holes 182 and the light-emitting layer 174 .
  • the OLED display panel 100 includes a display area AA and a non-display area NDA formed around the display area AA.
  • the first via hole 180 and the second via hole 182 are formed between the display area AA and the non-display area NDA.
  • the display area AA includes a plurality of pixel units P, and the first via hole 180 and the second via hole 182 are formed between at least two adjacent pixel units P.
  • Each pixel unit P includes at least three sub-pixels, such as red sub-pixels, green sub-pixels and blue sub-pixels.
  • the number of the penetrating first via holes 180 and the second via holes 182 close to the non-display area NDA may be three (but not limited to this), which is greater than one provided in the display area AA.
  • the number of the first via hole 180 and the second via hole 182 may also be equal to the number provided in the display area AA, and may be changed as needed.
  • the substrate 101 can be a rigid layer or a flexible layer.
  • the substrate 101 can be plain glass, PE resin or other materials. Made of suitable materials.
  • the substrate 101 is a flexible layer, several single-layer or multi-layer stacked structures made of polyimide (PI) and barrier layers can be provided on the plain glass, without limitation.
  • the substrate 101 also includes a substrate 102 (plain glass).
  • the substrate 101 may also include a multi-layer structure or a combination thereof as in the embodiment shown in FIG. 3 , which is not limited.
  • the OLED display panel 100 further includes forming a first layer between the substrate 101 and the thin film transistor layer.
  • the thin film transistor layer includes a plurality of thin film transistors TFT arranged in an array and third via holes 186 formed between the thin film transistors TFT.
  • the third via hole 186 is formed corresponding to the first via hole 180
  • the first metal layer 110 includes a light shielding layer 111 formed corresponding to the thin film transistor TFT and a first metal layer formed corresponding to the first via hole 180 Routing layer 112.
  • the cathode 176 is electrically connected to the first metal wiring layer 112 through the third via hole 186 .
  • the thin film transistor layer includes a buffer layer 120 , a semiconductor layer 132 , and a gate insulation layer arranged in sequence on the side of the first metal layer 110 away from the substrate 101 .
  • the second metal layer 135 includes a source and drain layer 138 connected to the semiconductor layer 132 and a first metal wiring electrode 139 formed corresponding to the first metal wiring layer 112.
  • the first metal wiring electrode 139 electrically connect the cathode 176 and the first metal wiring layer 112 through the third via hole 186 .
  • the first metal layer 110 is made of a single layer, a multi-layer combination, or an alloy thereof, such as copper (Cu), molybdenum (Mo), titanium (Ti), aluminum (Al), or an alloy thereof, and is formed through a physical vapor phase.
  • PVD Physical vapor deposition
  • LS layer the light-shielding layer 111
  • photoresist coating, exposure, development, etching, film stripping and other operations are performed respectively to form a structure as shown in Figure 5 cross-sectional view shown.
  • the first metal layer 110 can be used to shield light from the outside and prevent leakage current from being generated in the thin film transistor layer.
  • CVD is further used to deposit a buffer layer 120 , whose composition may be silicon nitride, silicon oxide, or a combination of both, forming a cross-sectional view as shown in FIG. 6 .
  • semiconductor materials such as indium zinc tin oxide (IZTO), indium aluminum zinc oxide (IAZO), indium gallium zinc oxide (IGZO), indium gallium tin oxide (IGTO) are further used.
  • PVD indium zinc tin oxide
  • IAZO indium aluminum zinc oxide
  • IGZO indium gallium zinc oxide
  • IGTO indium gallium tin oxide
  • CVD is used to deposit the gate insulating layer 134 , and its material can be silicon nitride, silicon oxide, or a combination of the two.
  • the gate 136 is made of materials such as copper (Cu), molybdenum (Mo), titanium (Ti), aluminum (Al) and other single-layer, multi-layer combinations or their alloys, and is made by PVD, and then processed separately.
  • Photoresist coating, exposure, development, etching, and film stripping form a cross-sectional view as shown in Figure 8. It should be noted that the above etching step is to first etch the pattern of the gate electrode 136 through a wet etching process, then etch the pattern of the gate insulating layer 134 through a dry etching process, and use helium (He) to induce conductivity. , to form the embodiment diagram of Figure 8.
  • CVD is further used to deposit the interlayer dielectric layer 130 (ILD).
  • ILD interlayer dielectric layer 130
  • Its material can be silicon nitride, silicon oxide or a combination of both, and is coated with photoresist and exposed. , development, etching, film stripping, etc., to form a cross-sectional view as shown in Figure 9.
  • the mask for making the interlayer dielectric layer 130 is etched simultaneously through the interlayer dielectric layer 130 and the buffer layer 120 in a half-tone manner.
  • the second metal layer 135 is made of a single layer, multi-layer combination or alloy thereof such as copper (Cu), molybdenum (Mo), titanium (Ti), aluminum (Al), etc. It is formed by PVD deposition, and then performs photoresist coating, exposure, development, etching, film stripping and other operations respectively to form a cross-sectional view as shown in Figure 10.
  • the thin film transistor layer includes a plurality of thin film transistors TFT arranged in an array and a third via hole 186 formed between the thin film transistors TFT.
  • the third via hole 186 is formed corresponding to the first via hole 180
  • the first metal layer 110 includes a light shielding layer 111 formed corresponding to the thin film transistor TFT and a first metal layer formed corresponding to the first via hole 180 Routing layer 112.
  • the cathode 176 is electrically connected to the first metal wiring layer 112 through the third via hole 186 .
  • the second metal layer 135 includes a source and drain layer 138 connected to the semiconductor layer 132 and a first metal wiring electrode 139 formed corresponding to the first metal wiring layer 112 .
  • the first metal wiring electrode 139 is made of the same layer and the same material as the source and drain layer 138 , and the first metal wiring electrode 139 connects the cathode 176 and the third via hole 186 through the third via hole 186 .
  • a metal wiring layer 112 is electrically connected.
  • the flat layer 150 is coated with a coater, and then exposed, developed, and baked respectively, and then ashed to form a cross section as shown in FIG. 12 picture.
  • the OLED display panel 100 further includes a third metal layer 178 formed on a side of the thin film transistor layer away from the substrate 101 .
  • the third metal layer 178 includes the anode 172 and a second metal wiring electrode 177 formed in the same layer as the anode 172.
  • the second metal wiring electrode 177 is made of the same layer and the same material as the anode 172, for example. , and is electrically connected to the first metal wiring electrode 139 .
  • the first via hole 180 and the penetrating second via hole 182 expose at least part of the second metal wiring electrode 177 .
  • the cathode 176 is connected to the second metal wiring electrode 177 through the first via hole 180 and the second via hole 182 .
  • the cathode 176 communicates with the first metal wiring layer 112 (as a VSS ground) through the third via hole 186 Voltage wiring) electrical connection can effectively reduce the problem of power supply voltage drop (IR Drop) of the top-emitting device of the large-size OLED display panel 100, thereby making the display more uniform.
  • IR Drop power supply voltage drop
  • PVD is further used to continuously deposit the anode 172 (such as a double-layer sandwich structure of ITO/Ag/ITO, IZO/Ag/IZO or other transparent conductive layers and silver (Ag))
  • anode 172 such as a double-layer sandwich structure of ITO/Ag/ITO, IZO/Ag/IZO or other transparent conductive layers and silver (Ag)
  • processes such as photoresist coating, exposure, development, etching, and film stripping are performed respectively to form the shape as shown in Figure 13 cross-sectional view shown.
  • a coater is further used to coat the pixel definition layer 160 (PDL/BANK). Then exposure, development and baking are performed respectively to form a cross-sectional view as shown in Figure 14.
  • the flat layer 150 and the pixel definition layer 160 are formed in the display area AA, the flat layer 150 is formed with a first side 152 close to the non-display area NDA, and the pixel definition layer 160 is close to the non-display area NDA.
  • the non-display area NDA is formed with a second side surface 166 .
  • the encapsulation layer 190 covers the cathode 176, the first side 152, and the second side 166 of the display area AA.
  • the non-display area NDA does not include the pixel definition layer 160 and the flat layer 150. That is, the non-display area NDA is fully covered by the encapsulation layer 190, effectively blocking the intrusion of external water, oxygen/humidity, thereby increasing the display The reliability and service life of most devices in area AA.
  • inkjet printing is further used to complete material injection and VCD baking of the hole injection layer, hole transport layer, light emitting layer, electron input layer, electron injection layer, etc. to form
  • the light emitting layer 174 is shown in Figure 15 .
  • the above-mentioned hole injection layer, hole transport layer, light-emitting layer, electron input layer, electron injection layer and other materials in the light-emitting layer 174 in this embodiment are preferably injected using inkjet printing.
  • the light-emitting layer 174 may include a combination of the above five layers or other multi-layer structures, and is not limited thereto.
  • the cathode 176 is further evaporated by evaporation ( Figure 16).
  • the cathode 176 Due to the design of the second metal wiring electrode 177, the cathode 176 has a great Designability can effectively reduce the problem of power supply voltage drop (IR Drop) of the top-emitting device of the large-size OLED display panel 100, thereby making the display more uniform.
  • IR Drop power supply voltage drop
  • the OLED display panel 100 further includes an encapsulation layer 190.
  • the flat layer 150 and the pixel definition layer 160 are formed in the display area AA.
  • the flat layer 150 has a first side 152 close to the non-display area NDA.
  • the pixel definition layer 160 has a second side 166 close to the non-display area NDA.
  • the encapsulation layer 190 covers the cathode 176, the first side 152, and the second side 166 of the display area AA.
  • the non-display area NDA does not include the pixel definition layer 160 and the flat layer 150. That is, the non-display area NDA is fully covered by the encapsulation layer 190, effectively blocking the intrusion of external water, oxygen/humidity, thereby increasing the display The reliability and service life of most devices in area AA.
  • the encapsulation layer 190 also includes a first inorganic encapsulation layer 192, an organic encapsulation layer 194 (TEF) and a second inorganic encapsulation layer 196.
  • the encapsulation layer 190 also includes the above three or more layers or other different combinations, which is not limited.
  • the material of the first inorganic encapsulation layer 192 and the second inorganic encapsulation layer 196 is preferably silicon oxide (SiO), and the material of the organic encapsulation layer 194 is preferably silicon nitride (SiN) or silicon oxynitride (SiNxOy). .
  • the step of preparing the encapsulation layer 190 on the cathode 176 also includes using CVD to deposit a first inorganic encapsulation layer 192, inkjet printing an organic encapsulation layer 194 on the first inorganic encapsulation layer 192, and printing an organic encapsulation layer 194 on the first inorganic encapsulation layer 192.
  • a second inorganic encapsulation layer 196 is deposited on 194 .
  • the encapsulation layer 190 also includes the above three or more layers or other different combinations, which is not limited.
  • the material of the first inorganic encapsulation layer 192 and the second inorganic encapsulation layer 196 is preferably silicon oxide, and the material of the organic encapsulation layer 194 is preferably silicon nitride or silicon oxynitride, as shown in FIG. 16 .
  • the pixel definition layer 160 can be provided as two layers (as shown in FIG. 4 ).
  • the pixel definition layer 160 includes a hydrophilic organic layer 162 and a hydrophobic layer 164 deposited on the hydrophilic organic layer 162 .
  • the bottom layer is a hydrophilic organic layer 162, so that the ink can be spread to the maximum layer
  • the top layer is a hydrophobic layer 164, so that the ink does not remain on the surface.
  • the thickness of the hydrophilic organic layer 162 is greater than or equal to the thickness of the hydrophobic layer 164. In a preferred embodiment, the thickness of the hydrophilic organic layer 162 is 4000 ⁇ , and the thickness of the hydrophobic layer 164 is 10000 ⁇ .
  • via holes that is, through the first via holes 180
  • the pixel definition layer 160 and the flat layer 150 on both sides of the via hole can effectively block the path of water and oxygen propagation, even if the package of a single pixel unit P fails It does not affect the normal use of other pixel units, thereby increasing the display reliability of most pixel units P in the display area (AA) and the service life of the OLED display panel 100 .
  • a third via hole 186 is provided between the plurality of thin film transistors TFT corresponding to the first via hole 180 , and the cathode 176 communicates with the third via hole 186 provided corresponding to the first via hole 180 through the third via hole 186 .
  • the electrical connection of a metal wiring layer 112 (as a VSS ground voltage wiring) can also effectively reduce the problem of power supply voltage drop (IR Drop) of the top-emitting device of the large-size OLED display panel 100, thereby making the display more uniform.
  • the pixel definition layer 160 and the flat layer 150 may not be provided in the non-display area NDA, that is, the non-display area NDA is fully covered by the encapsulation layer, effectively isolating the intrusion of external water, oxygen/moisture, thereby increasing the display area.

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Abstract

一种OLED显示面板（100），包括依次设置的衬底（101）、薄膜晶体管层、平坦层（150）及像素定义层（160）。平坦层（150）上设有第一过孔（180），像素定义层（160）上设置有第二过孔（182）和一通孔（184），第一过孔（180）和第二过孔（182）相贯通。OLED显示面板（100）还包括发光器件层（170），发光器件层（170）包括在平坦层（150）一侧依次设置的阳极（172）、发光层（174）和阴极（176），发光层（174）设置在通孔（184）内，阴极（176）覆盖像素定义层（160）、第一过孔（180）、第二过孔（182）以及发光层（174）。

Description

OLED显示面板及其制作方法 技术领域
本发明涉及一种显示面板技术领域，特别是涉及一种OLED显示面板及其制作方法。
 背景技术
有机发光器件(Organic Light Emitting Diode, OLED)相对于液晶显示器(liquid-crystal display，LCD)，具有自发光、反应快、视角广、亮度高、色彩艳、轻薄等优点，特别是，OLED具有可柔性化的特点，被认为是下一代显示技术。根据出光方向的不同，OLED又区分为底发射(Bottom Emission)和顶发射(Top Emission)两大类器件，其中底发射因其开口率相对较低，应用于高PPI (Pixels Per Inch，像素密度/每英寸像素)产品受限。大尺寸的顶发射器件也存在透明阴极不能做太厚而引发电源电压降(IR Drop)问题。此外，由于喷墨打印技术(Ink-jet Printing, IJP)因其成本较蒸镀低廉，也备受人们青睐而应用于OLED的制作中。
 技术问题
在现有顶发射喷墨打印技术研发过程中，因RGB材料流平性需求，需要在TFT器件上方铺设平坦层(PLN)和像素定义层(PDL)，然而当平坦层和像素定义层局部封装失效时，外界的水氧/湿气容易顺着这两层进入显示区的TFT及RGB发光材料中，影响器件的可靠性与信赖性。
 技术解决方案
本发明的目的，在于提供一种OLED显示面板及其制作方法，有效地隔绝切断相鄰发光层(像素)之间的水氧传播的路径，从而增加显示区域的可靠性及OLED显示面板的使用寿命。
为达到本发明前述目的，本发明提供一种OLED显示面板包括衬底、薄膜晶体管层、平坦层及像素定义层。所述薄膜晶体管层设置所述衬底的一侧。所述平坦层设置所述薄膜晶体管层远离所述衬底的一侧。所述像素定义层设置在所述平坦层远离所述薄膜晶体管层的一侧，其中所述平坦层上设有第一过孔，所述像素定义层上设置有第二过孔和一通孔，所述第一过孔和所述第二过孔相贯通；所述OLED显示面板还包括发光器件层，所述发光器件层包括在所述平坦层远离所述薄膜晶体管层一侧依次设置的阳极、发光层和阴极，所述阳极和所述薄膜晶体管层电性连接，所述发光层设置在所述通孔内，所述阴极覆盖所述像素定义层、所述第一过孔、所述第二过孔以及所述发光层。
在本申请提供的OLED显示面板中，所述OLED显示面板包括显示区和设置在所述显示区外围的非显示区，所述第一过孔和所述第二过孔设置所述显示区和所述非显示区之间。
在本申请提供的OLED显示面板中，所述显示区包括多个像素单元，所述第一过孔和所述第二过孔设置在相邻至少两个所述像素单元之间。
在本申请提供的OLED显示面板中，所述OLED显示面板还包括封装层，所述平坦层和所述像素定义层设置在所述显示区，所述平坦层具有靠近所述非显示区的第一侧面，所述像素定义层具有靠近所述非显示区的第二侧面，所述封装层覆盖所述显示区的所述阴极、所述第一侧面、所述第二侧面。
在本申请提供的OLED显示面板中，所述OLED显示面板还包括设置所述衬底和所述薄膜晶体管层之间的第一金属层，所述薄膜晶体管层包括多个阵列设置的薄膜晶体管和设置在所述薄膜晶体管之间的第三过孔，所述第三过孔对应所述第一过孔设置。
在本申请提供的OLED显示面板中，所述第一金属层包括对应所述薄膜晶体管设置的遮光层以及对应所述第一过孔设置的第一金属走线层，所述阴极通过所述第三过孔与所述第一金属走线层电性连接。
在本申请提供的OLED显示面板中，所述薄膜晶体管层包括依次设置在所述第一金属层远离所述衬底一侧的缓冲层、半导体层、栅极绝缘层、栅极层、层间介质层以及第二金属层，所述第二金属层包括和所述半导体层连接的源漏极层以及对应所述第一金属走线层设置的第一金属走线电极，所述第一金属走线电极通过所述第三过孔将所述阴极与所述第一金属走线层电性连接。
在本申请提供的OLED显示面板中，所述OLED显示面板还包括设置所述薄膜晶体管层远离所述衬底一侧的第三金属层，所述第三金属层包括所述阳极与所述阳极同层设置的第二金属走线电极，所述第二金属走线电极与所述第一金属走线电极电性连接。
在本申请提供的OLED显示面板中，所述第一过孔与贯通的所述第二过孔暴露出至少部分第二金属走线电极，所述阴极通过所述第一过孔、所述第二过孔与所述第二金属走线电极连接。
再者，本发明还提供一种显示面板的制作方法，包括如下步骤：
提供衬底；
在所述衬底的一侧形成薄膜晶体管层；
在所述薄膜晶体管层远离所述衬底的一侧形成平坦层；以及
在所述平坦层远离所述薄膜晶体管层的一侧形成像素定义层；
其中，所述平坦层上形成有第一过孔，所述像素定义层上形成有第二过孔和一通孔，所述第一过孔和所述第二过孔相贯通；所述OLED显示面板还包括发光器件层，所述发光器件层包括在所述平坦层远离所述薄膜晶体管层一侧依次形成的阳极、发光层和阴极，所述阳极和所述薄膜晶体管层电性连接，所述发光层形成在所述通孔内，所述阴极覆盖所述像素定义层、所述第一过孔、所述第二过孔以及所述发光层。
在本申请提供的OLED显示面板的制作方法中，所述OLED显示面板包括显示区和形成在所述显示区外围的非显示区，所述第一过孔和所述第二过孔形成所述显示区和所述非显示区之间。
在本申请提供的OLED显示面板的制作方法中，所述显示区包括多个像素单元，所述第一过孔和所述第二过孔形成在相邻至少两个所述像素单元之间。
在本申请提供的OLED显示面板的制作方法中，所述OLED显示面板还包括封装层，所述平坦层和所述像素定义层形成在所述显示区，所述平坦层具有靠近所述非显示区的第一侧面，所述像素定义层具有靠近所述非显示区的第二侧面，所述封装层覆盖所述显示区的所述阴极、所述第一侧面、所述第二侧面。
在本申请提供的OLED显示面板的制作方法中，所述OLED显示面板还包括形成所述衬底和所述薄膜晶体管层之间的第一金属层，所述薄膜晶体管层包括多个阵列布置的薄膜晶体管和形成在所述薄膜晶体管之间的第三过孔，所述第三过孔对应所述第一过孔形成。
在本申请提供的OLED显示面板的制作方法中，所述第一金属层包括对应所述薄膜晶体管形成的遮光层以及对应所述第一过孔形成的第一金属走线层，所述阴极通过所述第三过孔与所述第一金属走线层电性连接。
在本申请提供的OLED显示面板的制作方法中，所述薄膜晶体管层包括依次布置在所述第一金属层远离所述衬底一侧的缓冲层、半导体层、栅极绝缘层、栅极层、层间介质层以及第二金属层，所述第二金属层包括和所述半导体层连接的源漏极层以及对应所述第一金属走线层形成的第一金属走线电极，所述第一金属走线电极通过所述第三过孔将所述阴极与所述第一金属走线层电性连接。
在本申请提供的OLED显示面板的制作方法中，所述OLED显示面板还包括设置所述薄膜晶体管层远离所述衬底一侧的第三金属层，所述第三金属层包括所述阳极与所述阳极同层设置的第二金属走线电极，所述第二金属走线电极与所述第一金属走线电极电性连接。
在本申请提供的OLED显示面板的制作方法中，所述第一过孔与贯通的所述第二过孔暴露出至少部分第二金属走线电极，所述阴极通过所述第一过孔、所述第二过孔与所述第二金属走线电极连接。
在本申请提供的OLED显示面板的制作方法中，所述像素定义层还包括有亲水有机层以及沉积在所述亲水有机层上的疏水层，所述亲水有机层的厚度大于或等于所述疏水层的厚度。
在本申请提供的OLED显示面板的制作方法中，所述封装层还包括第一无机封装层、在所述第一无机封装层上喷墨打印有机封装层、在所述有机封装层上沉积第二无机封装层或其组合，所述第一无机封装层及所述第二无机封装层的材料为氧化硅，所述有机封装层的材料为氮化硅或氮氧化硅。
 有益效果
本发明还具有以下功效，本发明在显示区域的所述发光层(每一像素單元)中，通过所述像素定义层(PDL)及所述平坦层(PLN)这两道膜层上分别开设过孔(即贯通的第一过孔和第二过孔)，使每一像素單元之间通过过孔两侧的所述像素定义层及所述平坦层有效地隔断水氧传播的路径，即使单个像素封装失效也不影响其他像素單元的正常使用，从而增加显示区域(AA)的绝大部分像素單元显示的可靠性及OLED显示面板的使用寿命。在多个薄膜晶体管之间对应所述第一过孔设置第三过孔，且所述阴极通过所述第三过孔与对应所述第一过孔设置的所述第一金属走线层(作为VSS接地电压走线)电性连接，还可以有效地降低大尺寸OLED显示面板顶发射器件电源电压降(IR Drop)的问题，从而使显示更加均匀。此外，在非显示区域(NDA)中还可以不设置所述像素定义层及所述平坦层，即通过封装层全面覆盖非显示区域，有效隔绝外界水氧/湿气侵入，从而增加显示区域的绝大部分器件的可靠性及使用寿命。
 附图说明
为了更清楚地说明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单介绍，显而易见地，下面描述中的附图仅仅是发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1A是本发明OLED显示面板的第一横截面的实施例图；
图1B是本发明OLED显示面板的第二横截面的实施例图；
图２是本发明OLED显示面板的平面示意图；
图3是图1A或图1B的衬底的横截面結構图；
图4是本发明OLED显示面板的另一实施例图；
图5至图16是本发明OLED显示面板的制作方法的各横截面結構图；以及
图17是本发明OLED显示面板的制作方法的方块流程图。
 本发明的最佳实施方式
在具体实施方式中提及“实施例”意指结合实施例描述的特定特征、结构或特性可以包含在本发明的至少一个实施例中。在说明书中的不同位置出现的相同用语并非必然被限制为相同的实施方式，而应当理解为与其它实施例互为独立的或备选的实施方式。在本发明提供的实施例所公开的技术方案启示下，本领域的普通技术人员应理解本发明所描述的实施例可具有其他符合本发明构思的技术方案结合或变化。
请参照图1A及图1B所示，其为本发明OLED显示面板的第一及第二横截面的实施例图。本发明提供一种OLED显示面板100包括衬底101、薄膜晶体管层(未标示)、平坦层150及像素定义层160。所述薄膜晶体管层设置所述衬底101的一侧。所述平坦层150设置所述薄膜晶体管层远离所述衬底101的一侧。所述像素定义层160设置在所述平坦层150远离所述薄膜晶体管层的一侧。所述平坦层150上设有第一过孔180，所述像素定义层160上设置有第二过孔182和一通孔184，所述第一过孔180和所述第二过孔182相贯通。
所述OLED显示面板100还包括发光器件层170，所述发光器件层170包括在所述平坦层150远离所述薄膜晶体管层一侧依次设置的阳极172、发光层174和阴极176，所述阳极172和所述薄膜晶体管层电性连接，所述发光层174设置在所述通孔184内，所述阴极176覆盖所述像素定义层160、所述第一过孔180、所述第二过孔182以及所述发光层174。在如图1A及图1B所示的实施例中，所述OLED显示面板100包括显示区AA和设置在所述显示区AA外围的非显示区NDA，所述第一过孔180和所述第二过孔182设置所述显示区AA和所述非显示区NDA之间。
请一并参考图2所示，其为本发明OLED显示面板的平面示意图。所述显示区AA包括多个像素单元P，每一像素单元P包括至少三个子像素，例如红色子像素、绿色子像素及蓝色子像素。在一实施例中，所述第一过孔180和所述第二过孔182设置在相邻至少两个所述像素单元P之间。在如图1A所示的实施例中，相邻的两个所述像素单元P之间至少设置有1个贯通的所述第一过孔180和所述第二过孔182。然而在如图1B所示的实施例中，在相邻的两个所述像素单元P之间，也可以设置有3个贯通的所述第一过孔180和所述第二过孔182，以增加隔绝外界水氧侵入所述像素单元P的效果。
也就是说，所述第一过孔180和所述第二过孔182靠近所述非显示区域NDA的数量可以为3个(但不以此为限)，大于设置在所述显示区域AA的1个第一过孔180和所述第二过孔182的数量。然而在其他不同的实施例中，第一过孔180和所述第二过孔182靠近所述非显示区域NDA的数量也可以等于设置在所述显示区域AA的数量，视需要而改变。在如图1A及图2所示的实施例中，由于水氧/湿气传播的路径有效地被所述第一过孔180和所述第二过孔182隔绝切断，即使单个像素单元P封装失效也不影响其他像素单元P的正常使用，从而增加显示区域AA的绝大部分像素显示的可靠性及OLED显示面板100的使用寿命。
如图1A及图1B所示，所述OLED显示面板100还包括封装层190，所述平坦层150和所述像素定义层160设置在所述显示区AA，所述平坦层150具有靠近所述非显示区NDA的第一侧面152，所述像素定义层160具有靠近所述非显示区NDA的第二侧面166。所述封装层190覆盖所述显示区AA的所述阴极176、所述第一侧面152、所述第二侧面166。具体的，在所述非显示区域NDA中，并不包括像素定义层160及平坦层150，即通过封装层190全面覆盖在非显示区域NDA，有效隔绝外界水氧/湿气侵入，从而增加显示区域AA的绝大部分器件的可靠性及使用寿命。
如图1A及图1B所示的所述封装层190还包括第一无机封装层192、有机封装层194以及第二无机封装层196。然而在其他不同的实施例中，所述封装层190还包含上述三层以上或其他不同的组合，并不限制。所述第一无机封装层192及所述第二无机封装层196的材料优选为氧化硅(SiO)，所述有机封装层194的材料优选为氮化硅(SiN)或氮氧化硅(SiNxOy)。
请一并参考图3所示，本实施例的所述衬底101可以是刚性层或者是柔性层，当衬底101为刚性层时则可为素玻璃、PE树脂或其他适合的材料。当衬底101为柔性层时，则可以在素玻璃上设置若干由聚酰亚胺(PI)及阻挡层(Barrier layer)的单层或多层的叠构结构，并不限制。具体而言，如图3所示，所述衬底101还包括衬底102(素玻璃)、非晶硅层103(作为牺牲层)、第一光阻层104(聚酰亚胺PI)、第一阻挡层105(材料例如为氧化硅)、第二光阻层106(聚酰亚胺PI)、第二阻挡层107(材料例如为SiO)或其组合。
所述OLED显示面板100还包括设置所述衬底101和所述薄膜晶体管层之间的第一金属层110，所述薄膜晶体管层包括多个阵列设置的薄膜晶体管TFT和设置在所述薄膜晶体管TFT之间的第三过孔186，所述第三过孔186对应所述第一过孔180设置，所述第一金属层110包括对应所述薄膜晶体管TFT设置的遮光层111以及对应所述第一过孔180设置的第一金属走线层112，所述阴极176通过所述第三过孔186与所述第一金属走线层112电性连接。
具体的，所述薄膜晶体管层包括依次设置在所述第一金属层110远离所述衬底101一侧的缓冲层120、半导体层(IGZO/IGTO)132、栅极绝缘层134、栅极层136、层间介质层(ILD)130以及第二金属层135。所述第二金属层135包括和所述半导体层132连接的源漏极层138以及对应所述第一金属走线层112设置的第一金属走线电极139，所述第一金属走线电极139通过所述第三过孔186将所述阴极176与所述第一金属走线层112电性连接。
所述OLED显示面板100还包括设置所述薄膜晶体管层远离所述衬底101一侧的第三金属层178，所述第三金属层178包括所述阳极172与所述阳极172同层设置的第二金属走线电极177，所述第二金属走线电极177与所述第一金属走线电极139电性连接，所述第一过孔180与贯通的所述第二过孔182暴露出至少部分第二金属走线电极177，所述阴极176通过所述第一过孔180、所述第二过孔182与所述第二金属走线电极177连接。
因此，在本实施例中，通过在多个薄膜晶体管TFT之间设置第三过孔186，所述阴极176通过所述第三过孔186与所述第一金属走线层112(作为VSS接地电压走线)电性连接，可以有效地降低大尺寸OLED显示面板100顶发射器件电源电压降(IR Drop)的问题，从而使显示更加均匀。
请一并参考图4所示，其为本发明OLED显示面板的另一实施例图。在本实施例中，为了更好地提高喷墨打印的效果，所述像素定义层160可以设置为两层，其包括有亲水有机层162以及沉积在所述亲水有机层162上的疏水层164。具体的，底层为亲水有机层162，从而使墨水最大层度铺展开，其上为疏水层164，可以使墨水不残留在其表面。所述亲水有机层162的厚度大于或等于所述疏水层164的厚度，在一较佳实施例中，所述亲水有机层162的厚度为4000Å，所述疏水层164的厚度为10000Å。
请一并参考图5至图17所示，其为本发明OLED显示面板的制作方法的各横截面示意图及流程方块图。本发明还提供一种柔性OLED显示面板100的制作方法，所述制作方法包括如下步骤：
步骤S10、提供衬底101；步骤S20、在所述衬底101的一侧形成薄膜晶体管层(未标示)。步骤S30、在所述薄膜晶体管层远离所述衬底101的一侧形成平坦层150。步骤S40、在所述平坦层150远离所述薄膜晶体管层的一侧形成像素定义层160。所述平坦层150上形成有第一过孔180，所述像素定义层160上形成有第二过孔182和一通孔184，所述第一过孔180和所述第二过孔182相贯通。所述OLED显示面板100还包括发光器件层170，所述发光器件层170包括在所述平坦层150远离所述薄膜晶体管层一侧依次形成的阳极172、发光层174和阴极176，所述阳极172和所述薄膜晶体管层电性连接，所述发光层174形成在所述通孔184内，所述阴极176覆盖所述像素定义层160、所述第一过孔180、所述第二过孔182以及所述发光层174。
如图1A及图1B所示，所述OLED显示面板100包括显示区AA和形成在所述显示区AA外围的非显示区NDA，所述第一过孔180和所述第二过孔182形成所述显示区AA和所述非显示区NDA之间。所述显示区AA包括多个像素单元P，所述第一过孔180和所述第二过孔182形成在相邻至少两个所述像素单元P之间。每一像素单元P包括至少三个子像素，例如红色子像素、绿色子像素及蓝色子像素。贯通的所述第一过孔180和所述第二过孔182靠近所述非显示区域NDA的数量可以为3个(但不以此为限)，大于设置在所述显示区域AA的1个第一过孔180和所述第二过孔182的数量。然而在其他不同的实施例中，第一过孔180和所述第二过孔182靠近所述非显示区域NDA的数量也可以等于设置在所述显示区域AA的数量，视需要而改变。由于水氧/湿气传播的路径有效地被所述第一过孔180和所述第二过孔182隔绝切断，即使单个像素单元P封装失效也不影响其他像素单元P的正常使用，从而增加显示区域AA的绝大部分像素显示的可靠性及OLED显示面板100的使用寿命。
在提供所述衬底101的步骤S10中，如图3所示，所述衬底101可以是刚性层或者是柔性层，当衬底101为刚性层时则可为素玻璃、PE树脂或其他适合的材料制成。当衬底101为柔性层时，则可以在素玻璃上设置若干由聚酰亚胺(PI)及阻挡层(Barrier layer)的单层或多层的叠构结构，并不限制。具体而言，如图3所示，所述衬底101还包括衬底102(素玻璃)、在所述衬底102上通过化学气相(chemical vapor deposition，CVD)沉积非晶硅层103(Asi作为牺牲层)、涂布第一光阻层104(聚酰亚胺PI，并通过VCD进行干燥后形成)、通过VCD沉积第一阻挡层105(材料例如为氧化硅)、涂布第二光阻层106(聚酰亚胺PI，并通过VCD进行干燥后形成)、通过VCD沉积第二阻挡层(材料例如为氧化硅)。然而在其他不同的实施例中，所述衬底101也可以包括采用如图3实施例的多层结构或其组合，并不限制。
在所述衬底101一侧形成薄膜晶体管层的步骤S20中，如图5至图9中，所述OLED显示面板100还包括形成所述衬底101和所述薄膜晶体管层之间的第一金属层110。所述薄膜晶体管层包括多个阵列布置的薄膜晶体管TFT和形成在所述薄膜晶体管TFT之间的第三过孔186。所述第三过孔186对应所述第一过孔180形成，所述第一金属层110包括对应所述薄膜晶体管TFT形成的遮光层111以及对应所述第一过孔180形成的第一金属走线层112。所述阴极176通过所述第三过孔186与所述第一金属走线层112电性连接。
在如图5至图9所示的实施例中，所述薄膜晶体管层包括依次布置在所述第一金属层110远离所述衬底101一侧的缓冲层120、半导体层132、栅极绝缘层134、栅极层136、层间介质层130以及第二金属层135。所述第二金属层135包括和所述半导体层132连接的源漏极层138以及对应所述第一金属走线层112形成的第一金属走线电极139，所述第一金属走线电极139通过所述第三过孔186将所述阴极176与所述第一金属走线层112电性连接。
具体的，所述第一金属层110的材料如铜(Cu)、钼(Mo)、钛(Ti)、铝(Al)等单层、多层组合或其合金所构成，并通过物理气相 (Physical vapor deposition，PVD)沉积在所述衬底101上，作为遮光层111(LS层)，再分别进行光阻涂布、曝光、显影、刻蚀、剥膜等作业，形成如图5所示的横截面图。所述第一金属层110能够用来屏蔽来自外部的光，并且防止在薄膜晶体管层中生成漏电流。在如图5所示的实施例中，进一步采用CVD沉积缓冲层120(buffer layer)，其成分可以是氮化硅、氧化硅或者两者的组合，形成如图6所示的横截面图。
在如图7所示的实施例中，进一步采用半导体材料如铟锌锡氧化物（IZTO)、铟铝锌氧化物（IAZO)、铟镓锌氧化物（IGZO)、铟镓锡氧化物(IGTO)等单层、多层组合或其合金材料，用PVD沉积所述半导体层132，再分别进行光阻涂布、曝光、显影、刻蚀、剥膜等作业，形成如图8所示的横截面图。在如图8所示的实施例中，更采用CVD沉积所述栅极绝缘层134，其材料可以是氮化硅、氧化硅或者两者的组合。所述栅极136采用的材料如铜(Cu)、钼(Mo)、钛(Ti)、铝(Al)等单层、多层组合或其合金所构成，并利用PVD制成，再分别进行光阻涂布、曝光、显影、刻蚀、剥膜，形成如图8所示的横截面图。需要说明的是，上述刻蚀步骤是先通过湿刻工艺刻蚀出栅极136的图形，再用干刻工艺刻蚀出栅极绝缘层134的图形，并用氦气(He)进行诱导导体化，以形成图8的实施例图。
在如图8所示的实施例中，进一步采用CVD沉积所述层间介质层130(ILD)，其材料可以是氮化硅、氧化硅或者两者的组合，并通过光阻涂布、曝光、显影、刻蚀、剥膜等方式，形成如图9所示的横截面图。特别是，制作所述层间介质层130的掩模版是采用半色调(Half-tone)的方式同步刻蚀完所述层间介质层130及缓冲层120。在如图9所示的实施例中，所述第二金属层135的材料如铜(Cu)、钼(Mo)、钛(Ti)、铝(Al)等单层、多层组合或其合金所构成，并采用PVD沉积，再分别进行光阻涂布、曝光、显影、刻蚀、剥膜等作业，形成如图10所示的横截面图。
须说明的是，所述薄膜晶体管层包括多个阵列布置的薄膜晶体管TFT和形成在所述薄膜晶体管TFT之间的第三过孔186。所述第三过孔186对应所述第一过孔180形成，所述第一金属层110包括对应所述薄膜晶体管TFT形成的遮光层111以及对应所述第一过孔180形成的第一金属走线层112。所述阴极176通过所述第三过孔186与所述第一金属走线层112电性连接。此外，所述第二金属层135包括和所述半导体层132连接的源漏极层138以及对应所述第一金属走线层112形成的第一金属走线电极139。所述第一金属走线电极139例如与源漏极层138同层同材料制成，且所述第一金属走线电极139通过所述第三过孔186将所述阴极176与所述第一金属走线层112电性连接。
在所述薄膜晶体管层远离所述衬底101的一侧形成平坦层150的步骤S30中，如图10所示，所述钝化层140采用CVD沉积，其材料可以是氮化硅、氧化硅或者两者的组合，并通过光阻涂布、曝光、显影、刻蚀、剥膜等方式，形成如图11所示的横截面图。在如图11所示的实施例中，用涂布机涂布所述平坦层150，再分别进行曝光、显影以及烘烤等方式后，灰化(Ashing)形成如图12所示的横截面图。
所述OLED显示面板100还包括形成在所述薄膜晶体管层远离所述衬底101一侧的第三金属层178。所述第三金属层178包括所述阳极172与所述阳极172同层形成的第二金属走线电极177，所述第二金属走线电极177例如与所述阳极172同层同材料制成，并与所述第一金属走线电极139电性连接。所述第一过孔180与贯通的所述第二过孔182暴露出至少部分第二金属走线电极177。所述阴极176通过所述第一过孔180、所述第二过孔182与所述第二金属走线电极177连接。因此，在本实施例中，通过在多个薄膜晶体管TFT之间设置第三过孔186，所述阴极176通过所述第三过孔186与所述第一金属走线层112(作为VSS接地电压走线)电性连接，可以有效地降低大尺寸OLED显示面板100顶发射器件电源电压降(IR Drop)的问题，从而使显示更加均匀。
在如图12所示的实施例中，进一步采用PVD连续沉积所述阳极172(如ITO/Ag/ITO、IZO/Ag/IZO或其它透明导电层与银(Ag)的双层三明治夹层结构)，作为OLED显示面板100的像素电极、辅助电极及/或触控电极的另一电极走线，再分别进行光阻涂布、曝光、显影、刻蚀、剥膜等制程，形成如图13所示的横截面图。
在所述平坦层150远离所述薄膜晶体管层的一侧形成像素定义层160的步骤S40中，如图13所示，更采用涂布机涂布所述像素定义层160(PDL/BANK)，再分别进行曝光、显影以及烘烤，形成如图14所示的横截面图。特别是，所述平坦层150和所述像素定义层160形成在所述显示区AA，所述平坦层150靠近所述非显示区NDA形成有第一侧面152，所述像素定义层160靠近所述非显示区NDA形成有第二侧面166。所述封装层190覆盖所述显示区AA的所述阴极176、所述第一侧面152、所述第二侧面166。具体的，在所述非显示区域NDA中，并不包括像素定义层160及平坦层150，即通过封装层190全面覆盖在非显示区域NDA，有效隔绝外界水氧/湿气侵入，从而增加显示区域AA的绝大部分器件的可靠性及使用寿命。
在如图14所示的实施例中，进一步采用喷墨打印的方式分别完成空穴注入层、空穴传输层、发光层、电子输入层、电子注入层等材料注入与VCD烘烤，以形成如图15所示的发光层174。特别是，本实施例中的发光层174中的上述空穴注入层、空穴传输层、发光层、电子输入层、电子注入层等材料优选的采用喷墨打印方式进行注入。然而在其他不同的实施例中，所述发光层174可以包括上述5层等多层结构之组合，并不限制。在如图15所示的实施例中，进一步采用蒸镀方式蒸镀所述阴极176(如图16)，由于形成有第二金属走线电极177的设计，使所述阴极176有极大的可设计性，可以有效地降低大尺寸OLED显示面板100顶发射器件电源电压降(IR Drop)的问题，从而使显示更加均匀。
所述OLED显示面板100还包括封装层190，所述平坦层150和所述像素定义层160形成在所述显示区AA，所述平坦层150具有靠近所述非显示区NDA的第一侧面152，所述像素定义层160具有靠近所述非显示区NDA的第二侧面166。所述封装层190覆盖所述显示区AA的所述阴极176、所述第一侧面152、所述第二侧面166。具体的，在所述非显示区域NDA中，并不包括像素定义层160及平坦层150，即通过封装层190全面覆盖在非显示区域NDA，有效隔绝外界水氧/湿气侵入，从而增加显示区域AA的绝大部分器件的可靠性及使用寿命。
所述封装层190还包括第一无机封装层192、有机封装层194(TEF)以及第二无机封装层196。然而在其他不同的实施例中，所述封装层190还包含上述三层以上或其他不同的组合，并不限制。所述第一无机封装层192及所述第二无机封装层196的材料优选为氧化硅(SiO)，所述有机封装层194的材料优选为氮化硅(SiN)或氮氧化硅(SiNxOy)。
在所述阴极176上制备封装层190的步骤中，还包括采用CVD沉积第一无机封装层192、在所述第一无机封装层192上喷墨打印有机封装层194、在所述有机封装层194上沉积第二无机封装层196。然而在其他不同的实施例中，所述封装层190还包含上述三层以上或其他不同的组合，并不限制。所述第一无机封装层192及所述第二无机封装层196的材料优选为氧化硅，所述有机封装层194的材料优选为氮化硅或氮氧化硅，如图16所示。
须说明的是，为了更好地提高喷墨打印的效果，所述像素定义层160可设置为两层(如图4所示)。所述像素定义层160包括有亲水有机层162以及沉积在所述亲水有机层162上的疏水层164。具体的，底层为亲水有机层162，从而使墨水最大层度铺展开，其上为疏水层164，可以使墨水不残留在其表面。所述亲水有机层162的厚度大于或等于所述疏水层164的厚度，在一较佳实施例中，所述亲水有机层162的厚度为4000Å，所述疏水层164的厚度为10000Å。
在显示区域AA的所述发光层174(每一像素单元P)中，通过所述像素定义层160及所述平坦层150两道膜层上分别开设过孔(即贯通的第一过孔180和第二过孔182)，使每一像素单元P之间通过过孔两侧的所述像素定义层160及所述平坦层150有效地隔断水氧传播的路径，即使单个像素单元P封装失效也不影响其他像素单元的正常使用，从而增加显示区域(AA)的绝大部分像素单元P显示的可靠性及OLED显示面板100的使用寿命。
在多个薄膜晶体管TFT之间对应所述第一过孔180设置第三过孔186，且所述阴极176通过所述第三过孔186与对应所述第一过孔180设置的所述第一金属走线层112(作为VSS接地电压走线)电性连接，还可以有效地降低大尺寸OLED显示面板100顶发射器件电源电压降(IR Drop)的问题，从而使显示更加均匀。此外，在非显示区域NDA中还可以不设置所述像素定义层160及所述平坦层150，即通过封装层全面覆盖非显示区域NDA，有效隔绝外界水氧/湿气侵入，从而增加显示区域AA的绝大部分器件的可靠性及使用寿命。
综上所述，虽然本发明结合其具体实施例而被描述，应该理解的是，许多替代、修改及变化对于那些本领域的技术人员将是显而易见的。因此，其意在包含落入所附权利要求书的范围内的所有替代、修改及变化。

Claims (20)

  1. 一种OLED显示面板，包括：
    衬底；
    薄膜晶体管层，设置所述衬底的一侧；
    平坦层，设置所述薄膜晶体管层远离所述衬底的一侧；以及
    像素定义层，设置在所述平坦层远离所述薄膜晶体管层的一侧；
    其中，所述平坦层上设有第一过孔，所述像素定义层上设置有第二过孔和一通孔，所述第一过孔和所述第二过孔相贯通；所述OLED显示面板还包括发光器件层，所述发光器件层包括在所述平坦层远离所述薄膜晶体管层一侧依次设置的阳极、发光层和阴极，所述阳极和所述薄膜晶体管层电性连接，所述发光层设置在所述通孔内，所述阴极覆盖所述像素定义层、所述第一过孔、所述第二过孔以及所述发光层。
  2. 根据权利要求1所述的OLED显示面板，其中，所述OLED显示面板包括显示区和设置在所述显示区外围的非显示区，所述第一过孔和所述第二过孔设置所述显示区和所述非显示区之间。
  3. 根据权利要求1所述的OLED显示面板，其中，所述显示区包括多个像素单元，所述第一过孔和所述第二过孔设置在相邻至少两个所述像素单元之间。
  4. 根据权利要求2所述的OLED显示面板，其中，所述OLED显示面板还包括封装层，所述平坦层和所述像素定义层设置在所述显示区，所述平坦层具有靠近所述非显示区的第一侧面，所述像素定义层具有靠近所述非显示区的第二侧面，所述封装层覆盖所述显示区的所述阴极、所述第一侧面、所述第二侧面。
  5. 根据权利要求1所述的OLED显示面板，其中，所述OLED显示面板还包括设置所述衬底和所述薄膜晶体管层之间的第一金属层，所述薄膜晶体管层包括多个阵列设置的薄膜晶体管和设置在所述薄膜晶体管之间的第三过孔，所述第三过孔对应所述第一过孔设置。
  6. 根据权利要求5所述的OLED显示面板，其中，所述第一金属层包括对应所述薄膜晶体管设置的遮光层以及对应所述第一过孔设置的第一金属走线层，所述阴极通过所述第三过孔与所述第一金属走线层电性连接。
  7. 根据权利要求5所述的OLED显示面板，其中，所述薄膜晶体管层包括依次设置在所述第一金属层远离所述衬底一侧的缓冲层、半导体层、栅极绝缘层、栅极层、层间介质层以及第二金属层，所述第二金属层包括和所述半导体层连接的源漏极层以及对应所述第一金属走线层设置的第一金属走线电极，所述第一金属走线电极通过所述第三过孔将所述阴极与所述第一金属走线层电性连接。
  8. 根据权利要求7所述的OLED显示面板，其中，所述OLED显示面板还包括设置所述薄膜晶体管层远离所述衬底一侧的第三金属层，所述第三金属层包括所述阳极与所述阳极同层设置的第二金属走线电极，所述第二金属走线电极与所述第一金属走线电极电性连接。
  9. 根据权利要求8所述的OLED显示面板，其中，所述第一过孔与贯通的所述第二过孔暴露出至少部分第二金属走线电极，所述阴极通过所述第一过孔、所述第二过孔与所述第二金属走线电极连接。
  10. 一种OLED显示面板的制作方法，包括如下步骤:
    提供衬底；
    在所述衬底的一侧形成薄膜晶体管层；
    在所述薄膜晶体管层远离所述衬底的一侧形成平坦层；以及
    在所述平坦层远离所述薄膜晶体管层的一侧形成像素定义层；
    其中，所述平坦层上形成有第一过孔，所述像素定义层上形成有第二过孔和一通孔，所述第一过孔和所述第二过孔相贯通；所述OLED显示面板还包括发光器件层，所述发光器件层包括在所述平坦层远离所述薄膜晶体管层一侧依次形成的阳极、发光层和阴极，所述阳极和所述薄膜晶体管层电性连接，所述发光层形成在所述通孔内，所述阴极覆盖所述像素定义层、所述第一过孔、所述第二过孔以及所述发光层。
  11. 根据权利要求10所述OLED显示面板的制作方法，其中，所述OLED显示面板包括显示区和形成在所述显示区外围的非显示区，所述第一过孔和所述第二过孔形成所述显示区和所述非显示区之间。
  12. 根据权利要求10所述OLED显示面板的制作方法，其中，所述显示区包括多个像素单元，所述第一过孔和所述第二过孔形成在相邻至少两个所述像素单元之间。
  13. 根据权利要求11所述OLED显示面板的制作方法，其中，所述OLED显示面板还包括封装层，所述平坦层和所述像素定义层形成在所述显示区，所述平坦层具有靠近所述非显示区的第一侧面，所述像素定义层具有靠近所述非显示区的第二侧面，所述封装层覆盖所述显示区的所述阴极、所述第一侧面、所述第二侧面。
  14. 根据权利要求10所述OLED显示面板的制作方法，其中，所述OLED显示面板还包括形成所述衬底和所述薄膜晶体管层之间的第一金属层，所述薄膜晶体管层包括多个阵列布置的薄膜晶体管和形成在所述薄膜晶体管之间的第三过孔，所述第三过孔对应所述第一过孔形成。
  15. 根据权利要求14所述OLED显示面板的制作方法，其中，所述第一金属层包括对应所述薄膜晶体管形成的遮光层以及对应所述第一过孔形成的第一金属走线层，所述阴极通过所述第三过孔与所述第一金属走线层电性连接。
  16. 根据权利要求14所述OLED显示面板的制作方法，其中，所述薄膜晶体管层包括依次布置在所述第一金属层远离所述衬底一侧的缓冲层、半导体层、栅极绝缘层、栅极层、层间介质层以及第二金属层，所述第二金属层包括和所述半导体层连接的源漏极层以及对应所述第一金属走线层形成的第一金属走线电极，所述第一金属走线电极通过所述第三过孔将所述阴极与所述第一金属走线层电性连接。
  17. 根据权利要求16所述OLED显示面板的制作方法，其中，所述OLED显示面板还包括设置所述薄膜晶体管层远离所述衬底一侧的第三金属层，所述第三金属层包括所述阳极与所述阳极同层设置的第二金属走线电极，所述第二金属走线电极与所述第一金属走线电极电性连接。
  18. 根据权利要求17所述OLED显示面板的制作方法，其中，所述第一过孔与贯通的所述第二过孔暴露出至少部分第二金属走线电极，所述阴极通过所述第一过孔、所述第二过孔与所述第二金属走线电极连接。
  19. 根据权利要求10所述OLED显示面板的制作方法，其中，所述像素定义层还包括有亲水有机层以及沉积在所述亲水有机层上的疏水层，所述亲水有机层的厚度大于或等于所述疏水层的厚度。
  20. 根据权利要求13所述OLED显示面板的制作方法，其中，所述封装层还包括第一无机封装层、在所述第一无机封装层上喷墨打印有机封装层、在所述有机封装层上沉积第二无机封装层或其组合，所述第一无机封装层及所述第二无机封装层的材料为氧化硅，所述有机封装层的材料为氮化硅或氮氧化硅。
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Families Citing this family (4)

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CN115411216B (zh) * 2022-09-15 2024-09-03 惠科股份有限公司 显示面板及其制作方法
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Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107910347A (zh) * 2017-10-18 2018-04-13 深圳市华星光电半导体显示技术有限公司 一种显示器件及oled显示面板
CN110071225A (zh) * 2019-04-08 2019-07-30 深圳市华星光电半导体显示技术有限公司 显示面板及制作方法
CN110085648A (zh) * 2019-05-17 2019-08-02 京东方科技集团股份有限公司 阵列基板及其制作方法、显示面板、显示装置
CN110649069A (zh) * 2019-09-02 2020-01-03 武汉华星光电半导体显示技术有限公司 显示面板及显示面板的制作方法
CN111883574A (zh) * 2020-09-02 2020-11-03 深圳市华星光电半导体显示技术有限公司 Oled显示面板及其制作方法
CN112885870A (zh) * 2019-11-29 2021-06-01 华为技术有限公司 显示面板、柔性显示屏和电子设备及显示面板的制备方法
US20210233955A1 (en) * 2020-01-27 2021-07-29 Japan Display Inc. Display device
CN114171569A (zh) * 2021-12-07 2022-03-11 深圳市华星光电半导体显示技术有限公司 显示面板及其制作方法

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102080008B1 (ko) * 2013-07-12 2020-02-24 삼성디스플레이 주식회사 유기발광표시장치 및 그 제조방법
US10756292B2 (en) * 2017-10-13 2020-08-25 Shenzhen China Star Optoelectronics Semiconductor Display Technology Co., Ltd. Method of manufacturing an OLED panel and an OLED panel
KR102657529B1 (ko) * 2018-11-02 2024-04-12 엘지디스플레이 주식회사 유기 발광 표시 장치
KR102756221B1 (ko) * 2018-12-14 2025-01-17 엘지디스플레이 주식회사 표시 장치
CN112071893B (zh) * 2020-09-27 2024-07-05 京东方科技集团股份有限公司 触控显示装置、触控显示面板及其制作方法
KR20240144082A (ko) * 2022-01-30 2024-10-02 보에 테크놀로지 그룹 컴퍼니 리미티드 표시 패널, 제조 방법 및 표시 장치

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107910347A (zh) * 2017-10-18 2018-04-13 深圳市华星光电半导体显示技术有限公司 一种显示器件及oled显示面板
CN110071225A (zh) * 2019-04-08 2019-07-30 深圳市华星光电半导体显示技术有限公司 显示面板及制作方法
CN110085648A (zh) * 2019-05-17 2019-08-02 京东方科技集团股份有限公司 阵列基板及其制作方法、显示面板、显示装置
CN110649069A (zh) * 2019-09-02 2020-01-03 武汉华星光电半导体显示技术有限公司 显示面板及显示面板的制作方法
CN112885870A (zh) * 2019-11-29 2021-06-01 华为技术有限公司 显示面板、柔性显示屏和电子设备及显示面板的制备方法
US20210233955A1 (en) * 2020-01-27 2021-07-29 Japan Display Inc. Display device
CN111883574A (zh) * 2020-09-02 2020-11-03 深圳市华星光电半导体显示技术有限公司 Oled显示面板及其制作方法
CN114171569A (zh) * 2021-12-07 2022-03-11 深圳市华星光电半导体显示技术有限公司 显示面板及其制作方法

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