WO2023168971A1 - 一种片上差分有源rc滤波器的校准和调谐方法 - Google Patents

一种片上差分有源rc滤波器的校准和调谐方法 Download PDF

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WO2023168971A1
WO2023168971A1 PCT/CN2022/130627 CN2022130627W WO2023168971A1 WO 2023168971 A1 WO2023168971 A1 WO 2023168971A1 CN 2022130627 W CN2022130627 W CN 2022130627W WO 2023168971 A1 WO2023168971 A1 WO 2023168971A1
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filter
calibration
pole
array
bandwidth
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French (fr)
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高山
陈志坚
董雨欣
钟世广
王日炎
周伶俐
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华南理工大学
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H11/00—Networks using active elements
    • H03H11/02—Multiple-port networks
    • H03H11/04—Frequency selective two-port networks
    • H03H11/12—Frequency selective two-port networks using amplifiers with feedback
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E40/00—Technologies for an efficient electrical power generation, transmission or distribution
    • Y02E40/40—Arrangements for reducing harmonics

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  • the present invention relates to analog integrated circuits and, more particularly, to a calibration and tuning method for an on-chip differential active RC filter.
  • Active RC filters are often used for baseband signal filtering in transceivers. In order to ensure signal quality and adapt to various signal bandwidths, the filter bandwidth needs to be accurately adjustable. The resistors and capacitors on the chip will have large deviations due to PVT changes, so the filter needs to be calibrated to ensure the accuracy of the bandwidth.
  • the current active RC filter calibration methods mainly include integral type and exponential type.
  • the idea of the integral type is to charge C with a current of V ref /R, compare the charging time to V ref with the reference clock cycle, and modify the RC configuration according to the comparison result through successive approximation.
  • the voltage on C is the integral of V ref /R over time. It is not difficult to conclude that the time to charge C to V ref is the time constant RC. As long as the reference clock frequency is set to the target bandwidth of the filter, the filter can be calibrated. References in this area include [1], [2], [3], [4], [5]. It is worth mentioning that the integral structure requires a voltage buffer because it uses V re f to generate current.
  • the idea of exponential type is to use RC to form a first-order low-pass filter and test its step response.
  • the step response is an exponential curve related to the filter time constant. By comparing the time when the step response reaches a certain reference voltage and the reference clock cycle, the calibration can also be completed by modifying the RC configuration using the successive approximation method. References in this area include [6], [7], [8]. It is worth mentioning that this structure does not require a voltage buffer.
  • references [1]-[8] are:
  • Jin Gang, Huang Piao, Zhuang Yiqi, et al. voltage-divided integral type time constant calibration circuit for on-chip active RC filter.
  • the traditional method often sets up a separate set of RC arrays for testing without reusing the RC array on the filter, resulting in a waste of area.
  • the traditional method also requires a circuit to generate a reference voltage, and the integral calibration method also requires a voltage buffer, making the circuit more complex.
  • the technical problem to be solved by the present invention is to provide a calibration and tuning method for an on-chip differential active RC filter in view of the shortcomings of the existing technology, which reuses the capacitance on the filter and does not require an additional capacitor array; nor does it require Reference voltage and voltage buffer, strong anti-interference ability.
  • the calibration method of an on-chip differential active RC filter obtains the zero-crossing time of the differential signal output by analyzing the single-pole real filter; according to the zero-crossing time and the RC filter bandwidth A reference clock cycle is set according to the relationship, and a calibration working sequence is set according to the reference clock cycle; the RC configuration of the RC array is scanned with the calibration working sequence to realize the calibration of the RC array.
  • the first step is to set up a pulse generating unit connected to the input end of the single-pole real filter.
  • the pulse generating unit outputs a pulse signal in the calibration working sequence; an RC configuration is preset for the RC array;
  • the second step is to sample the differential signal output by the single-pole real filter through a comparator according to the pulse signal to obtain the comparison result;
  • the third step is to determine the relationship between the current bandwidth and the target bandwidth of the single-pole real filter based on the comparison result
  • the fourth step is to use the successive approximation algorithm to set the next set of RC configurations in the RC array, and repeat the above second and third steps; until the successive approximation algorithm ends, the bandwidth closest to the target can be obtained Bandwidth RC configuration to complete the calibration of the RC array.
  • the transfer function of the single-pole real filter is changed through the inverse Laplace transform to obtain the differential time domain response of the single-pole real filter to the falling edge of the pulse input; according to the differential time domain response, When the output of the single-pole real filter is zero, obtain the zero-crossing time;
  • the zero-crossing time is:
  • ⁇ is the time constant
  • f n is the bandwidth of the single-pole real filter.
  • the reference clock period is:
  • f n1 is the target bandwidth of the single-pole real filter.
  • the comparator If the comparator outputs a high level, then the current zero-crossing time of the differential signal is ahead of the reference clock cycle, indicating that the bandwidth obtained through the current RC configuration is too large;
  • the comparator If the comparator outputs a low level, the current zero-crossing time of the differential signal lags behind the reference clock cycle, indicating that the bandwidth obtained through the current RC configuration is too small.
  • a compensation unit is provided according to the operational amplifier delay of the operational amplifier in the single-pole real filter, so that the comparator is delayed by the operational amplifier delay and then samples the output voltage of the single-pole real filter.
  • the compensation unit is an inverter chain.
  • the input end of the comparator is connected to a first switch group, a second switch group and a sampling capacitor; the first switch group is connected to the output end of a single-pole real number filter, and the second switch group is connected to a pulse generating unit .
  • the pulse generating unit is mainly composed of a resistor voltage dividing structure and two sets of switch groups with opposite phases.
  • a tuning method for an on-chip differential active RC filter is used to tune the RC array according to the target bandwidth of the single-pole real filter.
  • the calibration working sequence is set so that when testing the time constant, the RC array on the filter can be reused without adding an additional RC array, which reduces the area occupied by the calibration circuit. .
  • the calibration circuit structure adopts a fully differential circuit structure, which makes pulse generation and zero-crossing detection simple.
  • the positive and negative poles of the single-pole real filter output are directly connected to the positive and negative input terminals of the comparator, so no reference voltage is required when detecting the zero-crossing point of the filter output.
  • the zero-crossing point has nothing to do with the pulse input amplitude, so there is no need for a voltage buffer. Only a simple resistor voltage divider is needed to generate the test pulse signal.
  • Figure 1 is a schematic diagram of the overall structure of the active RC filter calibration circuit of the present invention
  • Figure 2 is a calibration working timing waveform diagram of the present invention
  • Figure 3 is an output waveform diagram of the single-pole real filter during calibration of the present invention.
  • Figure 4 is a schematic diagram of the impact of the operational amplifier bandwidth of the present invention on the calibration waveform
  • Figure 5 is a schematic diagram of the error caused by the operational amplifier of the present invention at different K values
  • Figure 6 is a schematic diagram of the operational amplifier delay of the operational amplifier of the present invention on a general time scale
  • Figure 7 is a schematic diagram of the successive approximation of the capacitor array
  • Figure 8 is a capacitor array successive approximation simulation waveform diagram.
  • the invention provides a calibration method for an on-chip differential active RC filter, which obtains the zero-crossing time of the output differential signal V out by analyzing the single-pole real number filter.
  • a reference clock cycle is set according to the relationship between the zero-crossing time and the single-pole real filter bandwidth, and the calibration working sequence is set according to the reference clock cycle. Scan the RC configuration of the RC array in a calibration working sequence to achieve calibration of the RC array.
  • the entire calibration process does not require a reference voltage, which reduces the complexity of the calibration circuit.
  • the RC array on the filter can be reused when testing the time constant. There is no need to add an additional RC array, which reduces the area occupied by the calibration circuit.
  • Figure 1 shows a schematic structural diagram of the active RC filter calibration circuit of this embodiment.
  • the pulse generating unit generates the pulse input required to test the time constant ⁇ .
  • Single-pole real filters are the basic building blocks of higher-order active RC filters.
  • Single-pole real filters are mainly composed of operational amplifiers and RC arrays.
  • the single-pole real filter can be isolated by simply disconnecting it from the rest of the active RC filter. Therefore, during calibration, there is no need to set up a separate set of RC configurations of the RC array for testing.
  • the RC array on the active RC filter can be reused without adding an additional RC array, thereby reducing the area of the active RC filter.
  • the comparator is used to sample the response of a single-pole real filter to a pulse input and detect the relationship between the current zero-crossing time and the reference clock period.
  • the comparison result of the comparator is fed back to the control logic module, and the control logic module determines the next set of RC array control words R T ⁇ T:0>, R P ⁇ X:0>, and C P ⁇ Y:0> based on the sampling results.
  • the transfer function of the single-pole real filter is as follows:
  • the transfer function of the single-pole real filter is changed through the inverse Laplace transform to obtain the differential time domain response of the single-pole real filter to the falling edge of the pulse input.
  • the differential time domain response is expressed as:
  • ⁇ is the time constant
  • ⁇ R P C P
  • f n is the bandwidth of the single-pole real filter.
  • Different ⁇ corresponds to different single-pole real filter bandwidths.
  • f n1 is the target bandwidth of the single-pole real filter. That is, f n1 is the desired single-pole real filter bandwidth.
  • the present invention sets the calibration working sequence as shown in Figure 2 based on the reference clock cycle.
  • the first step is to set up a pulse generating unit connected to the input end of the single-pole real filter.
  • the pulse generating unit outputs a pulse signal in a calibrated working sequence; an RC configuration is preset for the RC array.
  • the differential signal output by the single-pole real filter is sampled through the comparator to obtain the comparison result.
  • the third step is to determine the relationship between the current bandwidth and the target bandwidth of the single-pole real filter based on the comparison results.
  • the comparator If the comparator outputs a high level, the current zero-crossing time of the differential signal V out is ahead of the reference clock cycle, that is, tr ⁇ T, indicating that the bandwidth obtained through the current RC configuration is too large.
  • the comparator If the comparator outputs a low level, the current zero-crossing time of the differential signal V out lags behind the reference clock cycle, that is, tr>T, indicating that the bandwidth obtained through the current RC configuration is too small.
  • the fourth step is to use the successive approximation algorithm to set the next set of RC configurations in the RC array, and repeat the above second and third steps; until the end of the successive approximation algorithm, the RC configuration with the bandwidth closest to the target bandwidth can be obtained, and the process is completed. Calibration of RC array.
  • the single-pole real filter of this embodiment provides a pulse signal through a pulse generating unit.
  • the pulse generation unit outputs a pulse signal according to the calibration working sequence, and the pulse signal is the pulse input required by the single-pole real filter.
  • the pulse generating unit of this embodiment is mainly composed of a resistor voltage dividing structure and two switch groups with opposite phases.
  • the resistor voltage dividing structure mainly consists of two resistors R a and one resistor R b . These three resistors are connected in series between the power terminal and the ground terminal. Among them, one of the resistors R a is connected to the power terminal, and its connection terminal is the first DC signal terminal, which outputs the DC signal V H .
  • One ends of the two resistors R a are connected to each other, and the connection end is a common mode reference voltage end, and the common mode reference voltage V cm is output.
  • the other end of the other resistor R a is connected to one end of the resistor R b , and its connection end serves as the second DC signal end to output the DC signal V L .
  • the other end of resistor R b is connected to ground.
  • the resistor voltage dividing structure uses resistor voltage division to generate three output voltages. Because the output common mode voltage of the single-pole real filter is the same as the input common mode voltage, both are the output common mode reference voltage V cm . Therefore, considering the virtual short characteristics of the operational amplifier, the voltage at point X in Figure 1 is also the output common mode voltage. Mode reference voltage V cm . Therefore, the current I p in Figure 1 is:
  • the current I n is:
  • V cm (V H +V L )/2
  • V cm I b *R b +(I b -I p )*R a
  • the reduction of resistance RT will cause the pulse amplitude Va and common mode reference voltage V cm to decrease, but the pulse amplitude Va does not affect the output of the single-pole real filter rising to the zero-crossing time.
  • the common-mode reference voltage V cm drops too much and may cause the single-pole real filter to not operate. Therefore, in order to ensure that the electrical signal provided by the pulse generating unit can make the single-pole real filter work effectively and reliably, the resistance of the resistor RT is set to be much larger than the resistor R a , so that the pulse amplitude V a and the common mode reference voltage V cm will not be affected much.
  • the relationship between the resistance R a and the resistance R T in the present invention is set to: R a ⁇ R T /10.
  • the two sets of switch groups with opposite phases include a third switch group and a fourth switch group whose switching state is opposite to that of the third switch group. That is, the high level of the differential pulse output by these two switch groups is V H -V L and the low level is V L -V H. The amplitudes of the high and low levels are symmetrical.
  • the third switch group is controlled by the control signal PG, and the fourth switch group is controlled by the control signal PG. control.
  • the pulse signal is generated through these two switch groups, and its structure is simple and easy to implement.
  • the input terminal of the comparator is connected with the first switch group, the second switch group and the sampling capacitor C S .
  • the first switch group is connected to the output end of the single-pole real number filter, and the second switch group is connected to the pulse generating unit.
  • the first switch group uses the calibration working sequence to input the differential signal V out output by the single-pole real filter into the comparator for comparison, obtain the comparison result of the positive and negative terminals of the comparator, and obtain the zero-crossing relationship based on the comparison result.
  • the first switch group is controlled by the control signal PHI1 output by the control logic module in Figure 1
  • the second switch group is controlled by the control signal PHI2 output by the control logic module in Figure 1.
  • the first switch group When sampling the differential signal V out output by the single-pole real filter, the first switch group is turned on, and the voltage on the sampling capacitor CS is the differential signal V out output by the single-pole real filter.
  • the sampling capacitor C S holds the input of the comparator to the voltage before the switch is turned off.
  • the second switch group is turned on, the voltage on the sampling capacitor C S is set to the DC signal V L and the DC signal V H output by the pulse generating unit respectively, and the comparator completes the reset.
  • the calibration working sequence of this embodiment mainly includes the control signal PG, and the control signals PHI1 and PHI2.
  • the control signal PHI1 leads the control signal PG by one reference clock cycle; the control signal PHI2 lags behind the control signal PG by three reference clock cycles; and the high levels of the control signals PG, PHI1, and PHI2 are equal to two reference clock cycles.
  • the input signal of the comparator is the differential signal V out output by the operational amplifier. Furthermore, the differential signal V out charges the sampling capacitor CS .
  • V out >0 the comparator outputs a high level; otherwise, it outputs a low level.
  • the control signal PHI1 is low, the connection between the comparator and the operational amplifier is disconnected.
  • the comparator samples the differential signal V out .
  • the output voltage As shown in Figure 3, if the voltage V s of the sampling capacitor C S > 0, it means that the zero-crossing time of the differential signal V out is ahead of the reference clock cycle.
  • the zero-crossing time is advanced, indicating that the RC configuration value of the RC array is too small, and the RC value should be increased. If V s ⁇ 0, it means that the zero-crossing time of the differential signal V out lags behind the reference clock period. The zero-crossing lag indicates that the RC configuration value of the RC array is too large, and the RC value should be reduced.
  • the voltages on the two sampling capacitors C S of the comparator are respectively set to V L and V H , the comparator completes the reset.
  • the calibration working sequence is repeated with 16 reference clock cycles.
  • the calibration circuit calibrates the RC array based on this relationship. Specifically, the control logic module uses a successive approximation algorithm to scan the RC array based on each comparison result to complete the calibration.
  • a compensation unit is set up according to the operational amplifier delay td of the operational amplifier in the single-pole real filter, so that the comparator delays with the operational amplifier delay td and then acts to sample the output voltage of the single-pole real filter. Effectively improve calibration accuracy.
  • the compensation unit is an inverter chain.
  • An inverter chain consists of multiple inverters connected in series.
  • the pole ⁇ p2 introduced by the operational amplifier will delay the output waveform of the single-pole real filter. This will make the calibrated single-pole real filter have a larger bandwidth. And the larger ⁇ p2 is, the smaller the impact.
  • V ideal 1-2e t
  • K is the operation factor
  • Figure 5 shows the error of K at some values calculated through MATLAB.
  • the error value is:
  • FIG. 7 a capacitor array with 32 unit capacitors connected in parallel is taken as an example to show how to achieve successive approximation calibration of capacitance.
  • the same principle applies to the successive approximation algorithm for more complex RC arrays.
  • Figure 8 is a simulation waveform of the calibration circuit of Figure 1.
  • C at the bottom of the figure is the number of unit capacitors connected in parallel.
  • a tuning method for on-chip differential active RC filters According to the target bandwidth of the single-pole real filter, the applied calibration method is simple and effective to tune the RC array.

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Abstract

本发明公开了一种片上差分有源RC滤波器的校准和调谐方法，涉及模拟集成电路，解决了有源RC滤波器传统的校准方法独立设置RC阵列造成的面积浪费，以及需要额外设置参考电压电路、电压缓冲器的技术问题。通过对单极点实数滤波器的分析，获取其输出的差分信号的过零点时间；根据所述过零点时间与单极点实数滤波器带宽的关系设置一参考时钟周期，并根据所述参考时钟周期设置校准工作时序；以所述校准工作时序扫描RC阵列的RC配置，以实现RC阵列的校准。本发明结构简单，复用了滤波器上的电容，不需要额外增加电容阵列；且不需要参考电压，不需要电压缓冲器，抗干扰能力强。

Description

一种片上差分有源RC滤波器的校准和调谐方法 技术领域
本发明涉及模拟集成电路，更具体地说，它涉及一种片上差分有源RC滤波器的校准和调谐方法。
背景技术
有源RC滤波器常用于收发机的基带信号滤波。为了保证信号质量和适应多种信号带宽，滤波器带宽需要精确可调。芯片上的电阻电容会因为PVT变化出现较大偏差，因此为了保证带宽的精确需要对滤波器进行校准。目前的有源RC滤波器校准方法主要有积分型和指数型两种。
积分型的思想是用一个V ref/R的电流对C充电，将充电到V ref的时间与参考时钟周期比较，根据比较结果逐次逼近的方法修改RC配置。C上的电压为V ref/R对时间的积分，不难得出，将C充电到V ref的时间为时间常数RC，只要将参考时钟频率设为滤波器的目标带宽就可以将滤波器校准。这方面的参考文献有[1]、[2]、[3]、[4]、[5]。值得一提的是，积分型结构因为要用V ref产生电流，因此需要一个电压缓冲器。
指数型的思想是用RC构成一个一阶低通滤波器，测试其阶跃响应。其阶跃响应为一个与滤波器时间常数有关的指数曲线，通过比较阶跃响应到达某个参考电压的时间和参考时钟周期，用逐次逼近的方法修改RC配置，也可以完成校准。这方面的参考文献有[6]、[7]、[8]。值得一提的是这种结构不需要电压缓冲器。
其中，参考文献[1]-[8]为：
[1]Jinup L,Youngjoo C,Kyungsoo J,et al.A wide-band active-RC filter with a fast tuning scheme for wireless communication receivers[C]//IEEE Custom Integrated Circuits Conference.IEEE,2005。
[2]Cho Y,Lim J,Jung K,et al.Fast on-chip tuning circuit for active RC filters using the SAR scheme[C]//Symposium on Circuits&Systems.IEEE Xplore,2005:1522-1525 Vol.2。
[3]司翠英.一种有源滤波器的RC时间常数校准电路及方法:,CN108134592A[P].2018。
[4]付永文，有源滤波器的时间常数的自动校准电路,CN108111146A[P].2018。
[5]靳刚,黄飘,庄奕琪,等，片上有源RC滤波器的分压积分型时常数校准电路。
[6]Xin J,Dai F F.A 6th order zero capacitor spread 1MHz–10MHz tunable CMOS active-RC low pass filter with fast tuning scheme[C]//IEEE International Symposium on Circuits&Systems.IEEE,2012。
[7]Chen Y C,Chiu W H,Lin T H.A 120-MHz active-RC filter with an agile frequency tuning scheme in 0.18-μm CMOS[C]//IEEE International Symposium on Vlsi Design.IEEE,2008。
[8]张超轩，可编程射频收发芯片滤波技术研究[D].中国航天科技集团公司。
总的来说，传统的方法往往单独设置一组RC阵列来测试，没有复用滤波器上的RC阵列，造成了面积的浪费。此外，传统的方法还需要产生参考电压的电路，积分型校准方法中还需要电压缓冲器，电路较为复杂。
发明内容
本发明要解决的技术问题是针对现有技术的不足，提供一种片上差分有源RC滤波器的校准和调谐方法，复用了滤波器上的电容，不需要额外增加电容阵列；也不需要参考电压以及电压缓冲器，抗干扰能力强。
本发明所述的一种片上差分有源RC滤波器的校准方法，通过对单极点实数滤波器的分析，获取其输出的差分信号的过零点时间；根据所述过零点时间与RC滤波器带宽的关系设置一参考时钟周期，并根据所述参考时钟周期设置校准工作时序；以所述校准工作时序扫描RC阵列的RC配置，以实现RC阵列的校准。
以所述校准工作时序扫描RC阵列的RC配置，具体包括，
第一步、设一与单极点实数滤波器输入端连接的脉冲发生单元，所述脉冲发生单元以所述校准工作时序输出脉冲信号；为所述RC阵列预设一RC配置；
第二步、根据脉冲信号，通过比较器对所述单极点实数滤波器输出的差分信号进行采样，获取比较结果；
第三步、根据所述比较结果判断单极点实数滤波器当前的带宽与目标带宽之间的大小关系；
第四步、利用逐次逼近算法设置所述RC阵列中的下一组RC配置，并重复上述第二和第三步；直至所述逐次逼近算法运行结束，即可获取到带宽最接近所述目标带宽的RC配置，完成RC阵列的校准。
通过拉普拉斯逆变换对所述单极点实数滤波器的传输函数进行变化，获取所述单极点实数滤波器对脉冲输入下降沿的差分时域响应；根据所述差分时域响应在所述单极点实数滤波器的输出为零时，获取所述过零点时间；
所述过零点时间为：
tr＝ln(2)τ；
Figure PCTCN2022130627-appb-000001
其中，τ为时间常数；f n为单极点实数滤波器的带宽。
所述参考时钟周期为：
Figure PCTCN2022130627-appb-000002
其中，f n1为单极点实数滤波器的目标带宽。
在第三步中：
若所述比较器输出高电平，则所述差分信号的当前过零点时间超前于参考时钟周期，说明通过当前的RC配置得到的带宽偏大；
若所述比较器输出低电平，则所述差分信号的当前过零点时间滞后于参考时钟周期，说明通过当前的RC配置得到的带宽偏小。
根据所述单极点实数滤波器中运算放大器的运放延迟设一补偿单元，以使所述比较器以运放延迟进行延时后再对单极点实数滤波器的输出电压进行采样。
所述补偿单元为反相器链。
所述比较器的输入端连接有第一开关组、第二开关组和采样电容；所述第一开关组与单极点实数滤波器的输出端连接，所述第二开关组与脉冲发生单元连接。
所述脉冲发生单元主要由电阻分压结构以及两组相位相反的开关组构成。
一种片上差分有源RC滤波器的调谐方法，根据单极点实数滤波器的目标带宽，应用所述的校准方法对RC阵列进行调谐。
有益效果
本发明的优点在于：
1、通过对单极点实数滤波器的分析，设置校准工作时序，使得在测试时间常数时，可复用滤波器上的RC阵列，不需要额外增加RC阵列，减小了校准电路所占用的面积。
2、校准电路结构采用了全差分的电路结构，使得脉冲产生和过零点检测变得简单。单极点实数滤波器输出的正负极直接接在比较器的正负输入端，因而检测滤波器输出的过零点时不需要参考电压。过零点与脉冲输入幅度无关，因此也不需要电压缓冲器，只需要简单的电阻分压来产生测试脉冲信号即可。
3、在比较器输入加入采样电容，并设计了可靠的校准工作时序，能更精确的采样到一个参考时钟周期后的运算放大器的输出，而不受比较器速度的限制，提高了校准的精确度。
4、通过反相器链的延时补偿运放延迟造成的误差，从而实现了较高的校准精度。
附图说明
图1为本发明的有源RC滤波器校准电路整体结构示意图；
图2为本发明的校准工作时序波形图；
图3为本发明的校准时单极点实数滤波器的输出波形图；
图4为本发明的运算放大器带宽对校准波形影响的示意图；
图5为本发明的运算放大器在不同K值造成的误差的示意图；
图6为本发明的运算放大器在一般时间尺度下的运放延时示意图；
图7为电容阵列逐次逼近示意图；
图8为电容阵列逐次逼近仿真波形图。
具体实施方式
下面结合实施例，对本发明作进一步的描述，但不构成对本发明的任何限制，任何人在本发明权利要求范围所做的有限次的修改，仍在本发明的权利要求范围内。
本发明的一种片上差分有源RC滤波器的校准方法，通过对单极点实数滤波器的分析，获取其输出的差分信号V out的过零点时间。根据过零点时间与单极点实数滤波器带宽的关系设置一参考时钟周期，并根据参考时钟周期设置校准工作时序。以校准工作时序扫描RC阵列的RC配置，以实现RC阵列的校准。
整个校准过程不需要参考电压，降低了校准电路的复杂程度。通过校准工作时序的设置，使得在测试时间常数时，可复用滤波器上的RC阵列，不需要额外增加RC阵列，减小了校准电路所占用的面积。
如图1所示为本实施例的有源RC滤波器校准电路的结构示意图。
图1中，脉冲发生单元产生测试时间常数τ所需要的脉冲输入。
单极点实数滤波器为构成更高阶有源RC滤波器的基本模块。单极点实数滤波器主要由运算放大器和RC阵列组成。在对RC阵列校准的过程中，只需将单极点实数滤波器与有源RC滤波器中的其他部分断开连接，即可将其独立出来。因此在校准时，无需单独设置RC阵列的一组RC配置进行测试，可复用有源RC滤波器上的RC阵列，不需要额外增加RC阵列，达到减小有源RC滤波器面积的目的。
比较器用于采样单极点实数滤波器对脉冲输入的响应，检测当前过零点时间与参考时钟周期之间的关系。比较器的比较结果反馈至控制逻辑模块中，控制逻辑模块根据采样结果确定下一组RC阵列控制字R T<T:0>、R P<X:0>、C P<Y:0>。
本实施例关于过零点时间的理论推导如下。
设单极点实数滤波器中的运算放大器为理想的运算放大器，则单极点实数滤波器的传输函数如下：
Figure PCTCN2022130627-appb-000003
设输入至运算放大器输入端的脉冲幅度为V a＝V H-V L。不考虑运算放大器造成的延迟，通过拉普拉斯逆变换对单极点实数滤波器的传输函数进行变化，获取单极点实数滤波器对脉冲输入下降沿的差分时域响应。差分时域响应表示为：
Figure PCTCN2022130627-appb-000004
令单极点实数滤波器输出的差分信号V out＝0，即可求得差分信号V out波形上升至过零点所需的时间，即过零点时间为：
tr＝ln(2)τ
Figure PCTCN2022130627-appb-000005
其中，τ为时间常数，τ＝R PC P；f n为单极点实数滤波器的带宽。不同的τ对应不同的单极点实数滤波器带宽。
本实施例的参考时钟周期为：
Figure PCTCN2022130627-appb-000006
其中，f n1为单极点实数滤波器的目标带宽。即f n1是期望得到的单极点实数滤波器带宽。
为比较运算放大器在实际运行时其输出的差分信号V out上升至过零点的时间与参考时钟周期之间的差异，本发明根据参考时钟周期设置了如图2所示的校准工作时序。
以校准工作时序扫描RC阵列的RC配置，具体包括，
第一步、设一与单极点实数滤波器输入端连接的脉冲发生单元，脉冲发生单元以校准工作时序输出脉冲信号；为RC阵列预设一RC配置。
第二步、在脉冲信号输入一个参考时钟周期时，通过比较器对单极点实数滤波器输出的差分信号进行采样，获取比较结果。
第三步、根据比较结果判断单极点实数滤波器当前的带宽与目标带宽之间的大小关系。
在该步骤中：
若比较器输出高电平，则差分信号V out的当前过零点时间超前于参考时钟周期，即tr<T，说明通过当前的RC配置得到的带宽偏大。
若比较器输出低电平，则差分信号V out的当前过零点时间滞后于参考时钟周期，即tr>T，说明通过当前的RC配置得到的带宽偏小。
第四步、利用逐次逼近算法设置RC阵列中的下一组RC配置，并重复上述第二和第三 步；直至逐次逼近算法运行结束，即可获取到带宽最接近目标带宽的RC配置，完成RC阵列的校准。
本实施例的单极点实数滤波器通过脉冲发生单元提供脉冲信号。脉冲发生单元按照校准工作时序输出脉冲信号，该脉冲信号即为单极点实数滤波器所需的脉冲输入。
本实施例的脉冲发生单元主要由电阻分压结构以及两组相位相反的开关组构成。具体的，电阻分压结构主要由两个电阻R a和一个电阻R b组成。这三个电阻串联在电源端和接地端之间。其中，其中一个电阻R a与电源端连接，且其连接端为第一直流信号端，输出直流信号V H。两个电阻R a的一端相互连接，且其连接端为共模参考电压端，输出共模参考电压V cm。另一个电阻R a的另一端与电阻R b的一端连接，且其连接端作为第二直流信号端，输出直流信号V L。而电阻R b的另一端接地。
也就是说，电阻分压结构采用电阻分压产生三个输出电压。因为单极点实数滤波器的输出共模电压和输入共模电压相同，都是输出共模参考电压V cm，所以考虑到运算放大器的虚短特性，在图1中的X点位置电压也是输出共模参考电压V cm。因此，图1中的电流I p为：
Figure PCTCN2022130627-appb-000007
电流I n为：
Figure PCTCN2022130627-appb-000008
又由于V cm＝(V H+V L)/2，故I p＝I n。即流过电阻R b的电流仍然是电源端的输入电流I b。即V a＝V H-V L＝2*(I b-I p)*R a；
V cm＝I b*R b+(I b-I p)*R a
从上述表达式看，电阻R T的减小会导致脉冲幅度V a和共模参考电压V cm下降，但脉冲幅度V a不影响单极点实数滤波器的输出上升到过零点时间。然而，共模参考电压V cm下降太多可能会导致单极点实数滤波器不工作。所以，为确保脉冲发生单元提供的电信号能使单极点实数滤波器有效可靠的进行工作，将电阻R T的阻值设置为远大于电阻R a，这样脉冲幅度V a和共模参考电压V cm就不会受到太大影响。
优选的，本发明中电阻R a与电阻R T的关系，设为：R a<R T/10。
两组相位相反的开关组包括第三开关组和开关状态与第三开关组相反的第四开关组。即这两个开关组输出的差分脉冲高电平为V H-V L，低电平为V L-V H，高低电平的幅度是对称的。第三开关组由控制信号PG控制，第四开关组由控制信号
Figure PCTCN2022130627-appb-000009
控制。通过这两个开关组实现脉冲信号的发生，其结构简单，易于实现。
比较器的输入端连接有第一开关组、第二开关组和采样电容C S。第一开关组与单极点实数滤波器的输出端连接，第二开关组与脉冲发生单元连接。第一开关组以校准工作时序使单极点实数滤波器输出的差分信号V out输入至比较器中进行比较，获取比较器正负端的对比结果，从而根据对比结果获取过零点关系。本实施例中，第一开关组由图1中控制逻辑模块输出的控制信号PHI1控制，第二开关组由图1中控制逻辑模块输出的控制信号PHI2控制。对单极点实数滤波器输出的差分信号V out采样时，第一开关组接通，采样电容C S上的电压为单极点实数滤波器输出的差分信号V out，第一开关组断开时，完成采样，采样电容C S将比较器的输入保持为开关断开前的电压。复位时，第二开关组接通，采样电容C S上的电压分别被置为脉冲发生单元输出的直流信号V L、直流信号V H，比较器完成复位。
通过图2可知，本实施例的校准工作时序主要包含了控制信号PG、以及控制信号PHI1和PHI2。其中，控制信号PHI1超前于控制信号PG一个参考时钟周期；控制信号PHI2滞后于控制信号PG三个参考时钟周期；且控制信号PG、PHI1、PHI2的高电平均为两个参考时钟周期。
在校准的过程中，控制信号PHI1为高电平时，比较器的输入信号为运算放大器输出的差分信号V out。并且，差分信号V out对采样电容C S充电。当V out>0时，比较器输出高电平；否则输出低电平。控制信号PHI1为低电平时，比较器与运算放大器之间的连接断开。此时比较器输入为断开前保持在采样电容C S的电压V s＝V out。若V s>0，则比较器的输出仍为高电平。因此，本实施例采样电容C S的设置目的是为了更精确的采样到一个参考时钟周期后的差分信号V out，而不受比较器速度的限制。
如图2所示，当控制信号PHI1为高电平时，比较器对差分信号V out进行采样。控制信号PHI1上升沿到来一个时钟周期后，控制信号PG的上升沿到来，差分信号V out开始上升。控制信号PG上升沿到来一个时钟周期后，控制信号PHI1变为低电平，对单极点实数滤波器输出的采样完成，采样电容C S上的电压保持为这一刻的单极点实数滤波器滤波器输出电压。如图3所示，若采样电容C S的电压V s>0，说明差分信号V out的过零点时间超前于参考时钟周期。过零点时间超前，说明RC阵列的RC配置值过小，应该加大RC值。若V s<0，说明差 分信号V out的过零点时间落后于参考时钟周期。过零点滞后说明RC阵列的RC配置值过大，应该减小RC值。控制信号PG上升沿到来两个时钟周期后，控制信号PG变为低电平，单极点实数滤波器输出的差分信号V out开始下降，并最终恢复到最低电压。控制信号PG下降沿到来一个时钟周期后，控制信号PHI2上升沿到来后保持两个时钟周期的高电平随后变为低电平，比较器的两个采样电容C S上的电压分别被置为V L和V H，比较器完成复位。
本实施例为了保证在下一次比较前单极点实数滤波器输出恢复到最低电压，校准工作时序以16个参考时钟周期重复。
校准电路在获取过零点与参考时钟周期的关系后，根据这一关系校准RC阵列。具体的，控制逻辑模块根据每一次的比较结果用逐次逼近算法扫描RC阵列，即可完成校准。
优选的，根据单极点实数滤波器中运算放大器的运放延迟td设一补偿单元，以使比较器以运放延迟td进行延时后再动作对单极点实数滤波器的输出电压进行采样，能有效的提高校准精度。
具体的，补偿单元为反相器链。反相器链由多个串联连接的反相器组成。
由于运算放大器有限的带宽，信号经过运算放大器时会产生延迟。下面分析运算放大器的运放延迟td对校准的影响，以说明用反相器链补偿延时的可行性。
在有源RC滤波器的校准电路中，令R p＝R T＝R，C p＝C，采用解析式A 0/(1+s/ω 0)对运算放大器进行建模。其中，A 0为低频增益，ω 0为主极点。考虑运算放大器带宽后的单极点实数滤波器传递函数为：
Figure PCTCN2022130627-appb-000010
假设传递函数H(s)的两个极点隔得很远，ω p1＜＜ω p2，则：
Figure PCTCN2022130627-appb-000011
ω p2≈(A 0+2)ω 0≈A 0ω 0
运算放大器引入的极点ω p2会使单极点实数滤波器输出波形延迟。这会使校准出来的单极点实数滤波器带宽偏大。且ω p2越大，影响越小。
将时间单位归一化到理想滤波器时间常数τ，则使用理想运算放大器的滤波器的阶跃响应为：
V ideal＝1-2e t
设ω p2＝Kω p1，则使用非理想运放的滤波器的阶跃响应为：
Figure PCTCN2022130627-appb-000012
其中，K为运算因子。
如图4为通过MATLAB画出K＝14时的瞬态波形图。
如图5为通过MATLAB算得K在部分取值下的误差。
其中，误差值为：
Figure PCTCN2022130627-appb-000013
则非理想过零点相对于理想过零点的延时为：
δt＝t@(V non-ideal＝0)-t@(V ideal＝0)
上述时间归一化到理想单极点实数滤波器的时间常数τ，但不能直接比较各种带宽下的运算放大器延时。因此我们尝试把它转换到一般时间尺度下，如下式所示。
Figure PCTCN2022130627-appb-000014
若将ω p2设为2π×600MHz，则不同K时的运放延时如图6所示。
以上分析表明，在K较小时，运放延迟td造成的误差非常大。但图6显示，不同K时的实际延时相差不大，因此可用一个固定的延时将其抵消。如图1所示，本发明将控制信号PHI1用反相器链延迟以补偿运放延迟td造成的误差。控制信号PHI1延迟后的信号为PHI1_D。经过实际测试，这一方法表现出了较好的精度。
关于逐次逼近算法，本实施例通过如图7所示的示意图进行说明。图7中，以32个单位电容并联的电容阵列为例，展示了如何实现逐次逼近校准电容的。而对更复杂RC阵列的逐 次逼近算法与其同理。
图8为图1的校准电路的仿真波形。图8中，图下方的C为单位电容并联个数。
一种片上差分有源RC滤波器的调谐方法，根据单极点实数滤波器的目标带宽，应用的校准方法对RC阵列进行调谐，简单有效。
以上所述的仅是本发明的优选实施方式，应当指出对于本领域的技术人员来说，在不脱离本发明结构的前提下，还可以作出若干变形和改进，这些都不会影响本发明实施的效果和专利的实用性。

Claims (6)

  1. 一种片上差分有源RC滤波器的校准方法，其特征在于，通过对单极点实数滤波器的分析，获取其输出的差分信号的过零点时间；根据所述过零点时间与单极点实数滤波器带宽的关系设置一参考时钟周期，并根据所述参考时钟周期设置校准工作时序；以所述校准工作时序扫描RC阵列的RC配置，以实现RC阵列的校准；
    其中，以所述校准工作时序扫描RC阵列的RC配置，具体包括，
    第一步、设一与单极点实数滤波器输入端连接的脉冲发生单元，所述脉冲发生单元以所述校准工作时序输出脉冲信号；为所述RC阵列预设一RC配置；
    第二步、根据脉冲信号，通过比较器对所述单极点实数滤波器输出的差分信号进行采样，获取比较结果；
    第三步、根据所述比较结果判断单极点实数滤波器当前的带宽与目标带宽之间的大小关系；
    第四步、利用逐次逼近算法设置所述RC阵列中的下一组RC配置，并重复上述第二和第三步；直至所述逐次逼近算法运行结束，即可获取到带宽最接近所述目标带宽的RC配置，完成RC阵列的校准；
    根据所述单极点实数滤波器中运算放大器的运放延迟设一补偿单元，以使所述比较器以运放延迟进行延时后再对单极点实数滤波器的输出电压进行采样；
    所述补偿单元为反相器链，用于对比较器采样控制信号进行固定延时，以将所述运放延迟抵消；
    所述脉冲发生单元由电阻分压结构以及两组相位相反的开关组构成；
    所述电阻分压结构由两个电阻R a和一个电阻R b组成；其中一个电阻R a的一端作为电阻分压结构的电源端，所述电阻R b的一端作为电压分压结构的接地端，两个所述电阻R a和一个电阻R b依次串联连接在电源端和接地端之间；且所述电源端还作为第一直流信号端，两个电阻R a相互连接的一端为共模参考电压端，所述电阻R a与电阻R b连接的一端作为第二直流信号端；
    所述开关组由第三开关组和开关状态与第三开关组相反的第四开关组组成；所述第三开 关组由第一开关和第二开关组成，且所述第一开关的两端分别与第一直流信号端和单极点实数滤波器的第一输入端一一对应连接，所述第二开关的两端分别与第二直流信号端和单极点实数滤波器的第二输入端一一对应连接；所述第四开关组由第三开关和第四开关组成，且所述第三开关的两端分别与第一直流信号端和单极点实数滤波器的第一输入端一一对应连接，所述第四开关的两端分别与第二直流信号端和单极点实数滤波器的第二输入端一一对应连接。
  2. 根据权利要求1所述的一种片上差分有源RC滤波器的校准方法，其特征在于，通过拉普拉斯逆变换对所述单极点实数滤波器的传输函数进行变化，获取所述单极点实数滤波器对脉冲输入下降沿的差分时域响应；根据所述差分时域响应在所述单极点实数滤波器的输出为零时，获取所述过零点时间；
    所述过零点时间为：
    tr＝ln(2)τ；
    其中，τ为时间常数，
    Figure PCTCN2022130627-appb-100001
    f n为单极点实数滤波器的带宽。
  3. 根据权利要求2所述的一种片上差分有源RC滤波器的校准方法，其特征在于，所述参考时钟周期为：
    Figure PCTCN2022130627-appb-100002
    其中，f n1为单极点实数滤波器的目标带宽。
  4. 根据权利要求1所述的一种片上差分有源RC滤波器的校准方法，其特征在于，在第三步中：
    若所述比较器输出高电平，则所述差分信号的当前过零点时间超前于参考时钟周期，说明通过当前的RC配置得到的带宽偏大；
    若所述比较器输出低电平，则所述差分信号的当前过零点时间滞后于参考时钟周期，说明通过当前的RC配置得到的带宽偏小。
  5. 根据权利要求1所述的一种片上差分有源RC滤波器的校准方法，其特征在于，所述比较器的输入端连接有第一开关组、第二开关组和采样电容；所述第一开关组与单极点实数滤波器的输出端连接，所述第二开关组与脉冲发生单元连接。
  6. 一种片上差分有源RC滤波器的调谐方法，其特征在于，根据单极点实数滤波器的目标带宽，应用如权利要求1-5任一项所述的校准方法对RC阵列进行调谐。
PCT/CN2022/130627 2022-03-11 2022-11-08 一种片上差分有源rc滤波器的校准和调谐方法 WO2023168971A1 (zh)

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