WO2023166793A1 - Imaging element and electronic device - Google Patents

Imaging element and electronic device Download PDF

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Publication number
WO2023166793A1
WO2023166793A1 PCT/JP2022/042631 JP2022042631W WO2023166793A1 WO 2023166793 A1 WO2023166793 A1 WO 2023166793A1 JP 2022042631 W JP2022042631 W JP 2022042631W WO 2023166793 A1 WO2023166793 A1 WO 2023166793A1
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WIPO (PCT)
Prior art keywords
image signal
pixel
signal
charge
unit
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PCT/JP2022/042631
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French (fr)
Japanese (ja)
Inventor
豪大 佐藤
征志 中田
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ソニーセミコンダクタソリューションズ株式会社
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Publication of WO2023166793A1 publication Critical patent/WO2023166793A1/en

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/10—Circuitry of solid-state image sensors [SSIS]; Control thereof for transforming different wavelengths into image signals
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
    • H04N25/78—Readout circuits for addressed sensors, e.g. output amplifiers or A/D converters

Definitions

  • the present disclosure relates to imaging devices and electronic devices.
  • Imaging in which a plurality of pixels including photoelectric conversion elements that perform photoelectric conversion of incident light share a charge holding portion that holds charges generated by photoelectric conversion and a signal generation portion that generates an image signal corresponding to the charges in the charge holding portion element is used.
  • an image pickup device has been proposed in which pixels corresponding to white light and pixels corresponding to light other than white light share the above-described charge holding unit (FD unit) and signal generation unit (for example, see Patent Document 1).
  • image signals are generated by individually transferring charges of pixels corresponding to different colors to charge holding units. For this reason, each image signal contains noise, and there is a problem that the signal-to-noise ratio deteriorates when taking an image in a dark place.
  • this disclosure proposes an image sensor and an electronic device that reduce the effects of noise.
  • a first aspect thereof is a first aspect in which incident light of a predetermined wavelength out of incident light is photoelectrically converted to generate electric charge.
  • a pixel, a second pixel that performs photoelectric conversion of incident light with a wavelength different from that of the first pixel to generate a charge, and holds the charge generated by the first pixel and the second pixel a pixel block including a charge holding portion and a signal generating portion for generating an image signal based on the charge held in the charge holding portion; and transferring the charge generated by the first pixel to the charge holding portion.
  • the imaging device has a signal processing section for switching between a first mode for outputting an added image signal and a second mode for outputting the first image signal and the second image signal.
  • FIG. 1 is a diagram showing a configuration example of a pixel block according to the first embodiment of the present disclosure
  • FIG. 1 is a diagram showing a configuration example of a pixel block according to the first embodiment of the present disclosure
  • FIG. 4 is a diagram illustrating a configuration example of a column signal processing unit according to the first embodiment of the present disclosure
  • FIG. 4 is a diagram illustrating an example of image signal generation according to the first embodiment of the present disclosure
  • FIG. 7 is a diagram showing an example of an image signal according to the second embodiment of the present disclosure
  • FIG. FIG. 7 is a diagram illustrating an example of addition image signal generation according to the second embodiment of the present disclosure
  • FIG. 11 is a diagram showing a configuration example of an image block according to the third embodiment of the present disclosure
  • FIG. 10 is a diagram illustrating an example of charge transfer in a pixel block according to the third embodiment of the present disclosure
  • FIG. FIG. 11 is a diagram illustrating an example of image signal generation according to the third embodiment of the present disclosure
  • FIG. 11 is a diagram showing a configuration example of a pixel block according to a fourth embodiment of the present disclosure
  • FIG. FIG. 11 is a diagram showing a configuration example of a pixel block according to a fourth embodiment of the present disclosure
  • FIG. FIG. 12 is a diagram illustrating an example of charge transfer in a pixel block according to the fourth embodiment of the present disclosure
  • FIG. FIG. 10 is a diagram illustrating an example of charge transfer in a pixel block according to the third embodiment of the present disclosure
  • FIG. FIG. 11 is a diagram illustrating an example of image signal generation according to the third embodiment of the present disclosure
  • FIG. 11 is a diagram showing a configuration example
  • FIG. 12 is a diagram illustrating an example of image signal generation according to the fourth embodiment of the present disclosure
  • FIG. 12 is a diagram illustrating an example of image signal generation according to the fifth embodiment of the present disclosure
  • FIG. 12 is a diagram illustrating another example of image signal generation according to the fifth embodiment of the present disclosure
  • FIG. 13 is a diagram showing a configuration example of a pixel block according to the sixth embodiment of the present disclosure
  • FIG. FIG. 13 is a diagram showing a configuration example of a pixel block according to the sixth embodiment of the present disclosure
  • FIG. FIG. 13 is a diagram showing a configuration example of a pixel block according to the sixth embodiment of the present disclosure
  • FIG. FIG. 13 is a diagram showing a configuration example of a pixel block according to the sixth embodiment of the present disclosure
  • FIG. 21 is a diagram illustrating another configuration example of a pixel block according to the sixth embodiment of the present disclosure
  • FIG. FIG. 21 is a diagram illustrating another configuration example of a pixel block according to the sixth embodiment of the present disclosure
  • FIG. FIG. 21 is a diagram illustrating another configuration example of a pixel block according to the sixth embodiment of the present disclosure
  • FIG. FIG. 21 is a diagram illustrating another configuration example of a pixel block according to the sixth embodiment of the present disclosure
  • FIG. FIG. 21 is a diagram illustrating another configuration example of a pixel block according to the sixth embodiment of the present disclosure
  • FIG. 1 is a diagram illustrating a configuration example of an imaging device to which technology according to the present disclosure may be applied;
  • FIG. 1 is a diagram illustrating a configuration example of an imaging device to which technology according to the present disclosure may be applied;
  • FIG. 1 is a diagram illustrating a configuration example of an imaging device to which technology according to the present disclosure may be applied;
  • FIG. 1 is a diagram
  • FIG. 1 is a diagram showing a configuration example of an imaging device according to an embodiment of the present disclosure. This figure is a block diagram showing a configuration example of the imaging element 1 .
  • a semiconductor device according to an embodiment of the present disclosure will be described by taking this imaging device 1 as an example.
  • the imaging device 1 is a semiconductor device that generates image data of a subject.
  • the imaging device 1 includes a pixel array section 10 , a vertical driving section 20 , a column signal processing section 30 and a control section 40 .
  • the pixel array section 10 is configured by arranging a plurality of pixel blocks 100 .
  • the pixel array section 10 has a plurality of pixel blocks 100 arranged in a two-dimensional matrix.
  • the pixel block 100 includes a plurality of pixels having photoelectric conversion units that perform photoelectric conversion of incident light and a charge holding unit (charge holding unit 106 described later) that holds charges generated by the photoelectric conversion. It is what is done.
  • a photodiode for example, can be used for the photoelectric conversion unit.
  • An image signal generator (signal generator 120 to be described later) is arranged for each pixel block 100 .
  • the signal generation section 120 generates an image signal based on the charges held in the charge holding section 106 of the pixel block 100 .
  • a signal line 11 is wired to each pixel block 100 and signal generation unit 120 .
  • the pixel block 100 and the signal generator 120 are controlled by control signals transmitted through the signal line 11 .
  • a signal line 12 is wired to the signal generator 120 .
  • An image signal is output from the signal generator 120 to the signal line 12 .
  • the signal line 11 is arranged for each row in a two-dimensional matrix, and is commonly wired to the plurality of pixel blocks 100 and the signal generator 120 arranged in one row.
  • the signal lines 12 are arranged in the column direction of the two-dimensional matrix and are wired commonly to the plurality of pixel blocks 100 arranged in one column.
  • the vertical driving section 20 generates control signals for the pixel block 100 described above.
  • a vertical drive unit 20 in FIG. 1 generates a control signal for each row of the two-dimensional matrix of the pixel array unit 10 and sequentially outputs the control signal via the signal line 11 .
  • the column signal processing unit 30 processes image signals generated by the pixel block 100 .
  • a column signal processing unit 30 shown in the figure simultaneously processes image signals from a plurality of pixel blocks 100 arranged in one row of the pixel array unit 10 and transmitted through the signal line 12 .
  • this processing for example, analog-to-digital conversion that converts the analog image signal generated by the pixel block 100 into a digital image signal and correlated double sampling (CDS: Correlated Double Sampling) that removes the offset error of the image signal are performed. be able to.
  • the processed image signal is output to a circuit or the like outside the imaging device 1 .
  • the control unit 40 controls the vertical driving unit 20 and the column signal processing unit 30.
  • a control unit 40 shown in the figure outputs control signals through signal lines 41 and 42 to control the vertical driving unit 20 and the column signal processing unit 30 .
  • the vertical drive unit 20 shown in the figure is an example of a pixel block control unit.
  • the column signal processing section 30 is an example of a signal processing section.
  • FIG. 2 is a diagram showing a configuration example of a pixel block according to the first embodiment of the present disclosure. This figure is a circuit diagram showing a configuration example of the pixel block 100 . In addition, the vertical driving section 20 and the column signal processing section 30 are further shown in the figure. The pixel block 100 in FIG.
  • the pixel 110a includes a photoelectric conversion unit 101a and a charge transfer unit 102a.
  • the pixel 110b includes a photoelectric conversion portion 101b and a charge transfer portion 102b.
  • the pixel 110c includes a photoelectric conversion portion 101c and a charge transfer portion 102c.
  • the pixel 110d includes a photoelectric conversion portion 101d and a charge transfer portion 102d. Photodiodes can be used for the photoelectric conversion units 101a to 101d. N-channel MOS transistors can be used for the charge transfer units 102a-102d.
  • the signal generator 120 includes an amplification transistor 121 and a selection transistor 122 .
  • N-channel MOS transistors can be used for the reset transistor 104, the amplification transistor 121, and the selection transistor 122.
  • FIG. In this n-channel MOS transistor the drain-source can be made conductive by applying a voltage exceeding the threshold of the gate-source voltage Vgs to the gate.
  • a voltage exceeding the threshold of the gate-source voltage Vgs is hereinafter referred to as an on-voltage.
  • a control signal including this on-voltage is called an on-signal.
  • a control signal is transmitted by a signal line TG1 or the like.
  • the signal lines 11 and 12 are wired in the pixel block 100 .
  • the signal lines 11 in the figure include signal lines TG1 to TG4, a signal line RST, and a signal line SEL.
  • the pixel block 100 is wired with a power line Vdd.
  • the power line Vdd is a wiring for supplying power to the pixel block 100 .
  • the anode of the photoelectric conversion unit 101a is grounded, and the cathode is connected to the source of the charge transfer unit 102a.
  • the photoelectric conversion unit 101b has an anode grounded and a cathode connected to the source of the charge transfer unit 102b.
  • the photoelectric conversion unit 101c has an anode grounded and a cathode connected to the source of the charge transfer unit 102c.
  • the photoelectric conversion unit 101d has an anode grounded and a cathode connected to the source of the charge transfer unit 102d.
  • the drains of the charge transfer units 102 a to 102 d are connected to the source of the reset transistor 104 , the gate of the amplification transistor 121 and one end of the charge holding unit 106 . Another end of the charge holding unit 106 is grounded.
  • the drain of the reset transistor 104 and the drain of the amplification transistor 121 are connected to the power supply line Vdd.
  • the source of the amplification transistor 121 is connected to the drain of the selection transistor 122 and the source of the selection transistor 122 is connected to the signal line 12 .
  • the gates of the charge transfer units 102a-102d are connected to the signal lines TG1-TG4, respectively.
  • a gate of the reset transistor 104 is connected to the signal line RST, and a gate of the select transistor 122 is connected to the signal line SEL.
  • the photoelectric conversion units 101a-101d perform photoelectric conversion of incident light.
  • the photoelectric conversion units 101a to 101d can be composed of photodiodes formed on a semiconductor substrate.
  • the photoelectric conversion units 101a to 101d perform photoelectric conversion of incident light during the exposure period and hold charges generated by the photoelectric conversion.
  • the charge holding unit 106 holds charges generated by the photoelectric conversion units 101a to 101d.
  • the charge holding portion 106 can be configured by a floating diffusion region (FD: Floating Diffusion), which is a semiconductor region formed in a semiconductor substrate.
  • FD floating diffusion region
  • the charge transfer units 102a-102d transfer charges.
  • the charge transfer units 102a-102d transfer the charges generated by the photoelectric conversion units 101a-101d to the charge holding unit 106, respectively.
  • the charge transfer units 102a and the like transfer charges by establishing electrical continuity between the photoelectric conversion units 101a and the like and the charge holding unit 106, respectively.
  • Control signals for the charge transfer units 102a-102h are transmitted by signal lines TG1-TG4, respectively.
  • the reset transistor 104 resets the charge holding section 106 . This reset can be performed by conducting between the charge holding portion 106 and the power supply line Vdd to discharge the charge in the charge holding portion 106 . A control signal for the reset transistor 104 is transmitted through a signal line RST. Note that the reset transistor 104 is an example of a reset unit.
  • the signal generation section 120 generates an image signal based on the charges held in the charge holding section 106 .
  • the signal generator 120 is composed of the amplification transistor 121 and the selection transistor 122 .
  • the amplification transistor 121 amplifies the voltage of the charge holding section 106 .
  • a gate of the amplification transistor 121 is connected to the charge holding unit 106 . Therefore, an image signal is generated at the source of the amplification transistor 121 with a voltage corresponding to the charge held in the charge holding unit 106 . Also, the image signal can be output to the signal line 12 by turning on the selection transistor 122 .
  • a control signal for the select transistor 122 is transmitted by a signal line SEL.
  • the photoelectric conversion units 101a to 101d perform photoelectric conversion of incident light during the exposure period to generate charges and store them in themselves. After the exposure period has elapsed, the charges of the photoelectric conversion units 101a to 101d are transferred to and held by the charge holding unit 106 by the charge transfer units 102a to 102d. An image signal is generated by the signal generator 120 based on the held charge.
  • the pixels 110a and 110c are provided with color filters that transmit incident light of the same wavelength.
  • the pixels 110a and 110c are called first pixels.
  • the first pixel photoelectrically converts incident light having a wavelength corresponding to the color filter arranged.
  • a color filter that transmits any one of red light, green light, and blue light can be arranged in the first pixel.
  • the pixels 110b and 110d are provided with color filters that transmit incident light having a wavelength different from that of the color filters of the pixels 110a and 110c, which are the first pixels.
  • the pixels 110b and 110d are called second pixels.
  • the second pixel photoelectrically converts incident light with a wavelength different from that of the first pixel.
  • a color filter that transmits white light can be arranged in the second pixel.
  • pixels 110a-110d share charge storage portion 106, reset transistor 104 and signal generation portion 120.
  • FIG. Therefore, it is possible to generate image signals for the pixels 110a-110d individually and simultaneously generate image signals for a plurality of pixels 110 out of the pixels 110a-110d.
  • the charge transfer units 102a and 102c are made conductive at the same time to transfer the charges of the photoelectric conversion units 101a and 101d to the charge holding unit 106.
  • the signal generator 120 by causing the signal generator 120 to generate an image signal.
  • An image signal generated based on the charge of the first pixel is called a first image signal. Since color filters corresponding to red light, green light and blue light are arranged in the first pixel, image signals corresponding to red light, green light and blue light are generated.
  • Image signals corresponding to red light, green light, and blue light are referred to as R image signal, G image signal, and B image signal, respectively.
  • These R image signal, G image signal and B image signal correspond to the first image signal.
  • "R", “G” and “B” in the figure represent the R image signal, the G image signal and the B image signal, respectively.
  • the charge transfer units 102b and 102d are made conductive in a state where the charge of the first pixel is held in the charge holding unit 106, and the second pixel ( The charges of pixels 110b and 110d) are summed.
  • the signal generation unit 120 to generate an image signal, it is possible to generate an image signal based on charges obtained by adding the charges generated by the first pixel and the second pixel. This image signal is called an added image signal. Since a color filter corresponding to white light is arranged in the second pixel, the added image signal is obtained by adding the image signal corresponding to white light to the image signal corresponding to red light, green light, and blue light. image signal.
  • An image signal obtained by adding an image signal corresponding to white light to an image signal corresponding to red light is called an R+W image signal.
  • An image signal obtained by adding an image signal corresponding to white light to an image signal corresponding to green light is called a G+W image signal.
  • An image signal obtained by adding an image signal corresponding to white light to an image signal corresponding to blue light is called a B+W image signal.
  • R+W image signal, G+W image signal and B+W image signal correspond to the added image signal.
  • "R+W”, “G+W” and “B+W” in the figure represent the R+W image signal, the G+W image signal and the B+W image signal, respectively.
  • the vertical drive section 20 in the figure outputs a control signal to the pixel block 100 via the signal line TG1 or the like, and controls the pixel block 100 to generate the first image signal and the added image signal. That is, the vertical drive section 20 transfers the charge generated by the first pixel to the charge holding section 106 and controls the signal generation section 120 to generate the first image signal. In addition, the vertical driving unit 20 further transfers the charges generated by the second pixels to the charge holding unit 106 that holds the charges generated by the first pixels, and generates an addition image signal in the signal generation unit 120. Further control is performed. Prior to generating the first image signal, the vertical driving section 20 further performs control to reset the charge holding section 106 .
  • the vertical driving section 20 further controls the signal generating section 120 to generate an image signal at the time of resetting.
  • This image signal is called an image signal at the time of reset.
  • CDS which will be described later, can be performed by the image signal at the time of this reset.
  • the image signal at reset is an example of the reference image signal.
  • an image signal based on the charge of the second pixel By subtracting the first image signal from the added image signal, an image signal based on the charge of the second pixel can be generated.
  • This image signal is called a second image signal.
  • the second pixels (the pixels 110b and 110d) are provided with color filters corresponding to white light, so the second image signal is an image signal corresponding to white light.
  • An image signal corresponding to white light is called a W image signal.
  • the W image signal corresponds to the second image signal.
  • the column signal processing unit 30 in the figure processes the first image signal and the added image signal.
  • a subtraction unit 34 is arranged in the column signal processing unit 30 .
  • the subtractor 34 subtracts the first image signal from the added image signal to generate the second image signal.
  • the column signal processing unit 30 outputs a first image signal (R image signal, G image signal and B image signal) and added image signals (R+W image signal, G+W image signal and B+W image signal) and a first mode.
  • the mode of outputting the image signal and the second image signal (W image signal) generated by the subtraction unit 34 can be switched.
  • a mode in which the first image signal and the added image signal are output is called a first mode.
  • a mode in which the first image signal and the second image signal are output is called a second mode. Mode switching can be performed, for example, under the control of the control unit 40 in FIG. Note that "W" in the figure represents a W image signal.
  • FIG. 3 is a diagram illustrating a configuration example of a pixel block according to the first embodiment of the present disclosure; This figure is a plan view showing a configuration example of the pixel block 100 .
  • the state of the charge holding unit 106 at the time of resetting, the generation of the first image signal, and the generation of the added image signal is also shown in FIG.
  • the configuration of the pixel block 100 will be described using the leftmost drawing in the upper row of the figure.
  • the rectangles represent pixels 110a to 110d.
  • a dotted rectangle represents a pixel block 100 .
  • a pixel block 100 in the figure represents an example in which pixels 110a to 110d are arranged in two rows and two columns.
  • the letters attached to the pixels 110a, etc. in the figure represent the types of image signals to be generated.
  • the first pixels (pixels 110a and 110c) generate G image signals
  • the second pixels (pixels 110b and pixels 110d) produce the W image signal.
  • the first pixels (pixels 110a and 110c) generate B image signals
  • the second pixels (pixels 110b and 110d) generate W image signals.
  • the first pixels (pixels 110a and 110c) generate R image signals
  • the second pixels (pixels 110b and 110d) generate W image signals.
  • Such four pixel blocks 100 are arranged in the pixel array section 10 .
  • two first pixels and two second pixels are arranged in a square matrix of 2 rows and 2 columns, and the first pixels and the second pixels are arranged in the row direction and the column direction. alternately arranged.
  • the lower part of the figure is a potential diagram showing the state of the charge holding portion 106 of the upper left pixel block 100 .
  • the left end of the figure shows the states of the pixel block 100 and the charge holding portion 106 at the time of resetting. By resetting, the charge in the charge holding portion 106 is discharged.
  • the center of the figure represents the state in which the charge of the first pixel has been transferred to the charge holding portion 106 .
  • a first image signal is generated.
  • the dotted hatched pixels represent pixels to which charge has been transferred.
  • the charges of the first pixels (pixel 110a and pixel 110c) are transferred to the charge holding portion 106.
  • FIG. The parts in parentheses in FIG. The four pixel blocks 100 generate an R image signal, a G image signal and a B image signal.
  • the charge holding unit 106 holds the charge of the first pixels (pixel 110a and pixel 110c). Rectangles marked with "G" in the potential diagram of the charge holding portion 106 in the figure represent charges from the first pixels (pixel 110a and pixel 110c).
  • the charge of the second pixel is transferred to the charge holding unit 106 and added without resetting the charge holding unit 106 after generating the first image signal.
  • the level of the image signal can be increased, and the signal-to-noise ratio can be improved.
  • the noise components contained in the respective charges are leveled. Thereby, the noise of the addition image signal can also be reduced.
  • the right end of the figure represents the state in which the charge of the second pixel has been transferred to the charge holding portion 106 .
  • an added image signal is generated.
  • the dotted hatched pixels represent pixels to which charge has been transferred.
  • the charges of the second pixels (pixel 110b and pixel 110d) are transferred to the charge holding portion 106.
  • an added image signal is generated by adding the W signal to the R image signal, G image signal, and B image signal in the four pixel blocks 100 .
  • the charge holding unit 106 holds the charges of the first pixels (the pixels 110a and 110c) and the charges of the second pixels (the pixels 110b and 110d). Rectangles marked with "W" in the potential diagram of the charge holding portion 106 in FIG.
  • FIG. 4 is a diagram illustrating a configuration example of a column signal processing unit according to the first embodiment of the present disclosure; This figure is a block diagram showing a configuration example of the column signal processing unit 30. As shown in FIG. The column signal processing unit 30 in FIG. 37 and an interface unit 38 .
  • the reference signal generator 32 generates a reference signal and supplies it to the analog-to-digital converter 31 .
  • This reference signal is a signal whose value changes like a ramp function.
  • the analog-to-digital converter 31 performs analog-to-digital conversion of image signals.
  • the analog-to-digital converter 31 converts analog image signals generated by the pixels 110 into digital image signals.
  • An analog-to-digital converter 31 in FIG. 1 converts an analog image signal into a digital image signal based on the reference signal output from the reference signal generator 32 .
  • the analog-to-digital converter 31 compares the analog image signal and the reference signal and detects a period until the analog image signal and the reference signal match. Since the reference signal is a voltage signal corresponding to the elapsed time, the period from the start of the output of the reference signal until it matches the analog image signal corresponds to the voltage of the analog image signal. By outputting a digital signal corresponding to this period, an analog image signal can be converted into a digital image signal.
  • the holding unit 33 holds the image signal converted into a digital signal by the analog-to-digital conversion unit 31 . Further, the holding unit 33 can perform CDS.
  • This CDS is a process of removing the offset (noise) by taking the difference of the image signal at the time of resetting from the image signal. Charges that are not discharged at reset remain in the charge holding unit 106 described with reference to FIG. A signal component based on this remaining charge becomes an offset component of an image signal and causes noise. Therefore, the offset component can be removed by holding the image signal at the time of reset and subtracting the image signal at the time of reset from the first image signal or the added image signal.
  • the holding unit 33 shown in the figure can hold the image signal at the time of resetting and the process of subtracting the image signal at the time of resetting from the first image signal. By performing this CDS, noise in the image signal can be reduced.
  • the subtraction unit 34 subtracts the first image signal from the added image signal to generate the second image signal as described above.
  • the signal processing unit 35 selects an image signal to be output according to the mode.
  • the signal processing unit 35 outputs the first image signal and the added image signal when the first mode is selected, and outputs the first image signal and the second image signal when the second mode is selected. Output a signal.
  • the Bayer array conversion unit 36 converts the first image signal or the like into a Bayer array image signal.
  • the signal processing unit 37 performs processing such as interpolation processing of image signals.
  • the interface unit 38 exchanges with external devices.
  • An interface unit 38 shown in the figure exchanges data with the application processor.
  • FIG. 5 is a diagram illustrating an example of image signal generation according to the first embodiment of the present disclosure. This figure is a timing chart showing an example of generation of the first image signal and the added image signal in the pixel block 100. As shown in FIG.
  • ⁇ SEL'', ⁇ RST'', ⁇ TG1'', ⁇ TG2'', ⁇ TG3'' and ⁇ TG4'' in FIG. TG3 and TG4 signals are represented.
  • REF represents the waveform of the reference signal output from the reference signal generator 32 described with reference to FIG.
  • ADC represents the output of the analog-to-digital converter 31 .
  • the value "1" portion of the binarized waveform represents the ON voltage (Von). Also, the value "0" represents the off-voltage.
  • the dashed line in the figure represents the level of the off-voltage. Note that the dotted line in the drawing represents the potential of the charge holding portion 106 .
  • an off voltage is input to the signal line SEL, the signal line TG1, the signal line TG2, the signal lines TG3 and TG4.
  • An ON voltage is input to the signal line RST. Since the reset transistor 104 becomes conductive, the charge holding unit 106 is reset. Further, exposure is performed during the period up to T1. Note that exposure can be started by turning on the reset transistor 104 and the charge transfer section 102a.
  • an ON voltage is input from the signal line SEL. Thereby, the pixel block 100 is selected.
  • the reference signal generator 32 outputs a ramp function reference signal, and the analog-to-digital converter 31 performs analog-to-digital conversion.
  • "a" in the figure represents the conversion result. This corresponds to a digital image signal at reset. The image signal at this reset is held in the holding unit 33 .
  • the reference signal generator 32 outputs the reference signal, and the analog-to-digital converter 31 performs analog-to-digital conversion.
  • "b" in the figure represents the conversion result. This corresponds to the digital first image signal.
  • CDS can be performed by subtracting the digital image signal at the time of reset from this digital first image signal.
  • the input of the ON voltage from the signal lines TG2 and TG4 is stopped, and the charge transfer sections 102b and 102d are brought into a non-conducting state.
  • the reference signal generator 32 outputs the reference signal, and the analog-to-digital converter 31 performs analog-to-digital conversion.
  • "c" in the figure represents the conversion result. This corresponds to a digital added image signal.
  • CDS can be performed by subtracting the digital image signal at the time of reset from this digital added image signal.
  • the first image signal and the added image signal can be generated in the pixel block 100 by the above procedure.
  • the imaging device 1 of the first embodiment of the present disclosure generates an added image signal by adding the charge of the second pixel to the charge of the first pixel. This allows a higher signal level and an improved signal-to-noise ratio.
  • the imaging device 1 of the first embodiment described above outputs the first image signal and the added image signal.
  • the imaging device 1 of the second embodiment of the present disclosure differs from the above-described first embodiment in that the bit width of the added image signal is aligned with that of the first image signal and output.
  • FIG. 6 is a diagram illustrating an example of an image signal according to the second embodiment of the present disclosure; The same figure is a figure explaining the image signal based on 2nd Embodiment of this indication.
  • the drawing on the left end of the figure shows the arrangement of the pixel blocks 100 .
  • a first image signal and an added image signal are generated from this pixel block 100 .
  • the generated first image signal and added image signal are analog-to-digital converted into a digital first image signal and a digital added image signal.
  • the diagram in the middle of the figure shows the arrangement of the digital first image signal 301 and the digital added image signal 302 .
  • the digital first image signal 301 is a 10-bit width signal
  • the digital addition image signal 302 is an 11-bit width signal.
  • Signal processing is performed on these digital first image signal 301 and digital added image signal 302 .
  • the diagram on the right end of the figure represents the image signal after the signal processing.
  • the upper row represents the output signal in the first mode. In the first mode, a 10-bit width first image signal 301 and a 10-bit width added image signal 303 are output.
  • the bottom row represents the output signal in the second mode. In the second mode, a 10-bit wide first image signal 301 and a 10-bit wide second image signal are output.
  • FIG. 7 is a diagram illustrating an example of addition image signal generation according to the second embodiment of the present disclosure. This figure is a diagram for explaining the procedure for converting the bit width of the added image signal 302 of 11-bit width into 10-bit width.
  • (1) in the figure shows an example of converting the added image signal 302 of 11-bit width to 10-bit width by removing the most significant bit. Since the signal of the least significant bit is held, it is preferable to apply this method when priority is given to the image quality of dark areas.
  • (2) in the figure shows an example of converting the added image signal 302 of 11-bit width to 10-bit width by removing the least significant bit. Since the signal of the most significant bit is held, this method is preferably applied when giving priority to the image quality of the bright portion.
  • the second mode is selected to transmit the first image signal and the second image signal of 10-bit width to an external device, and after the transmission, the first image signal and the second image signal are added, By generating the added image signal, it is possible to prevent the lack of the added image signal.
  • the configuration of the imaging device 1 other than this is the same as the configuration of the imaging device 1 in the first embodiment of the present disclosure, the description is omitted.
  • the image sensor 1 according to the second embodiment of the present disclosure can match the bit widths of the first image signal and the added image signal by adjusting the bit width of the added image signal. As a result, it is possible to simplify the handling of signals in subsequent devices.
  • the image sensor 1 of the first embodiment described above adds charges of pixels corresponding to incident light of the same wavelength.
  • the imaging device 1 of the third embodiment of the present disclosure differs from the above-described first embodiment in that charges of pixels corresponding to incident light of different wavelengths are added.
  • FIG. 8 is a diagram showing a configuration example of an image block according to the third embodiment of the present disclosure. This figure is a diagram showing a configuration example of the pixel block 100 .
  • a pixel 110 corresponding to red-violet light and a pixel 110 corresponding to blue-green light are further arranged.
  • "Y", "M” and “C” in the figure represent image signals corresponding to yellow light, red-violet light and blue-green light, respectively.
  • the pixel 110a In the pixel block 100 on the upper left of the figure, the pixel 110a generates the R image signal, the pixel 110c generates the M image signal, and the pixels 110b and 110d generate the W image signal.
  • the pixel 110a In the upper right pixel block 100, the pixel 110a generates a G image signal, the pixel 110c generates a Y image signal, and the pixels 110b and 110d generate a W image signal.
  • the pixel 110a In the lower left pixel block 100, the pixel 110a generates a G image signal, the pixel 110c generates a Y image signal, and the pixels 110b and 110d generate a W image signal.
  • pixel 110a produces the B image signal, pixel 110c produces the C image signal, and pixels 110b and 110d produce the W image signal.
  • Such four pixel blocks 100 are arranged in the pixel array section 10 .
  • FIG. 9 is a diagram illustrating an example of charge transfer in a pixel block according to the third embodiment of the present disclosure.
  • This figure is a diagram for explaining the charge transfer of the pixels 110 of the pixel block 100 after reset.
  • the pixel block 100 on the upper left of the figure will be described as an example.
  • the charge of the pixel 110 a is transferred to the charge holding portion 106 .
  • an image signal is generated.
  • the charge of the pixel 110c is transferred to the charge holding unit 106 and added.
  • an image signal is generated.
  • the charges of pixel 110b and pixel 110d are then transferred and summed.
  • an image signal is generated.
  • the pixel block 100 of FIG. 1 generates three image signals.
  • FIG. 10 is a diagram illustrating an example of image signal generation according to the third embodiment of the present disclosure. This figure is a timing chart showing an example of generation of the first image signal and the addition image signal in the pixel block 100, similar to FIG. The same processing as in FIG. 5 can be applied to the processing up to T20.
  • an ON voltage is input from the signal line TG1, and the charge transfer section 102a becomes conductive. Thereby, the charge accumulated in the photoelectric conversion unit 101 a is transferred to the charge holding unit 106 .
  • the reference signal generator 32 outputs the reference signal, and the analog-to-digital converter 31 performs analog-to-digital conversion.
  • "d” in the figure represents the image signal of the conversion result.
  • the reference signal generator 32 outputs the reference signal, and the analog-to-digital converter 31 performs analog-to-digital conversion.
  • "e” in the figure represents the image signal of the conversion result.
  • the reference signal generator 32 outputs the reference signal, and the analog-to-digital converter 31 performs analog-to-digital conversion.
  • "f" in the figure represents the image signal of the conversion result.
  • the configuration of the imaging device 1 other than this is the same as the configuration of the imaging device 1 in the first embodiment of the present disclosure, the description is omitted.
  • the imaging device 1 of the third embodiment of the present disclosure generates image signals by adding the charges of the pixels 110 that generate image signals corresponding to incident light of different wavelengths.
  • the imaging device 1 of the first embodiment described above generates the first image signal and the added image signal.
  • the imaging device 1 of the fourth embodiment of the present disclosure differs from the above-described first embodiment in that it further generates a phase difference signal for detecting the image plane phase difference.
  • FIG. 11 is a diagram illustrating a configuration example of a pixel block according to the fourth embodiment of the present disclosure.
  • This figure, like FIG. 2, is a circuit diagram showing a configuration example of the pixel block 100.
  • the pixel block 100 in FIG. 2 differs from the pixel block 100 in FIG. 2 in that pixels 110a and 110c each include a plurality of photoelectric conversion units 101 and a plurality of charge transfer units 102.
  • FIG. 11 is a diagram illustrating a configuration example of a pixel block according to the fourth embodiment of the present disclosure.
  • FIG. 2 is a circuit diagram showing a configuration example of the pixel block 100.
  • pixels 110a and 110c each include a plurality of photoelectric conversion units 101 and a plurality of charge transfer units 102.
  • the pixel 110a includes photoelectric conversion units 101e and 101f and charge transfer units 102e and 102f.
  • the pixel 110c includes photoelectric conversion units 101g and 101h and charge transfer units 102g and 102h.
  • the anode of the photoelectric conversion unit 101e is grounded, and the cathode is connected to the source of the charge transfer unit 102e.
  • the photoelectric conversion unit 101f has an anode grounded and a cathode connected to the source of the charge transfer unit 102f.
  • the photoelectric conversion section 101g has an anode grounded and a cathode connected to the source of the charge transfer section 102g.
  • the photoelectric conversion unit 101h has an anode grounded and a cathode connected to the source of the charge transfer unit 102h.
  • the drains of the charge transfer units 102e, 102f, 102g and 102h are connected to one end of the charge holding unit 106.
  • Gates of the charge transfer units 102e, 102f, 102g and 102h are connected to signal lines TG11, TG12, TG31 and TG32, respectively.
  • the photoelectric conversion units 101e and 101f are photoelectric conversion units that pupil-divide the subject.
  • the photoelectric conversion units 101g and 101h are photoelectric conversion units that pupil-divide the subject.
  • FIG. 12 is a diagram illustrating a configuration example of a pixel block according to the fourth embodiment of the present disclosure; This figure is a plan view showing a configuration example of the pixel block 100 .
  • the pixel 110a is pupil-divided by the photoelectric conversion units 101e and 101f.
  • the pixel 110c is pupil-divided by the photoelectric conversion units 101g and 101h.
  • a phase difference signal can be generated by these pupil-divided pixels 110 .
  • FIG. 13 is a diagram illustrating an example of charge transfer in a pixel block according to the fourth embodiment of the present disclosure. Similar to FIG. 9, this figure is a diagram for explaining the charge transfer of the pixels 110 of the pixel block 100 after reset.
  • the pixel block 100 on the upper left of the figure will be described as an example.
  • the charge of the photoelectric conversion portion 101e of the pixel 110a is transferred to the charge holding portion .
  • an image signal is generated.
  • the charge of the photoelectric conversion unit 101f of the pixel 110a is transferred to the charge holding unit 106 and added.
  • an image signal is generated.
  • the charges of pixel 110b and pixel 110d are then transferred and summed. At this time, an image signal is generated.
  • the pixel block 100 in the figure produces three image signals including phase difference signals.
  • FIG. 14 is a diagram illustrating an example of image signal generation according to the fourth embodiment of the present disclosure.
  • This figure is a timing chart showing an example of generation of the first image signal and the addition image signal in the pixel block 100, similar to FIG.
  • a procedure similar to that of FIG. 11 can be applied except that the ON voltage is input to TG11 and TG31 during the period from T20 to T21, and the ON voltage is input to TG12 and TG32 during the period from T24 to T25.
  • a phase signal can be generated from the image signal of "d” and the image signal of "e” in the figure.
  • the configuration of the imaging device 1 other than this is the same as the configuration of the imaging device 1 in the first embodiment of the present disclosure, the description is omitted.
  • the image sensor 1 of the fourth embodiment of the present disclosure can generate phase difference signals in the pixel block 100 .
  • the imaging device 1 of the first embodiment described above generates a digital first image signal and a digital added image signal by one analog-to-digital conversion.
  • the imaging device 1 of the fifth embodiment of the present disclosure differs from the above-described first embodiment in that image signals are generated by performing multiple analog-to-digital conversions.
  • FIG. 15 is a diagram illustrating an example of image signal generation according to the fifth embodiment of the present disclosure. Similar to FIG. 5, this figure is a timing chart showing an example of generation of the first image signal and the added image signal in the pixel block 100. In FIG. It differs from the processing procedure in FIG. 5 in that processing procedures from T40 to T41 are added. In the processing procedure shown in the figure, after the generation of the image signal "b" in the period T7 to T8, the same processing of T40 to T41 is performed to generate the image signal "b" again.
  • the average of the two "b" image signals is calculated to generate the first image signal. Since the noise of the two image signals is leveled, the noise of the first image signal can be reduced.
  • FIG. 16 is a diagram showing another example of image signal generation according to the fifth embodiment of the present disclosure. Similar to FIG. 5, this figure is a timing chart showing an example of generation of the first image signal and the added image signal in the pixel block 100. In FIG. It differs from the processing procedure in FIG. 5 in that processing procedures from T45 to T46 are added. In the processing procedure shown in the figure, after generating the image signal of "c" in the period of T11 to T12, the processing of T45 to T46 in the same procedure is performed to generate the image signal of "c" again.
  • the average of the two "c" image signals is calculated to generate an added image signal. Since the noise of the two image signals is leveled, the noise of the added image signal can be reduced.
  • the configuration of the imaging device 1 other than this is the same as the configuration of the imaging device 1 in the first embodiment of the present disclosure, the description is omitted.
  • the image sensor 1 of the fifth embodiment of the present disclosure can reduce noise by calculating the average of digital image signals generated by performing analog-to-digital conversion multiple times.
  • FIGS. 17A-17C are diagrams showing configuration examples of pixel blocks according to the sixth embodiment of the present disclosure. This figure is a plan view showing a configuration example of the pixel block 100 .
  • FIG. 17A shows an example of changing the arrangement of pixels 110 with respect to the pixel block 100 of FIG.
  • FIG. 17B shows an example of changing the arrangement of the pixels 110 with respect to the pixel block 100 of FIG.
  • FIG. 17C shows an example in which pixels 110 that generate image signals corresponding to infrared light are arranged instead of the pixels 110 that generate W image signals in the pixel block 100 of FIG. Pixels 110 labeled with “IR” in the figure represent pixels 110 that generate image signals corresponding to infrared light.
  • FIG. 18A and 18B are diagrams showing other configuration examples of pixel blocks according to the sixth embodiment of the present disclosure.
  • This figure is a plan view showing a configuration example of the pixel block 100 .
  • An example of changing the exposure time for each pixel 110 is shown. Note that pixels 110 that generate image signals of the same color can be arranged in the pixel block 100 in FIG.
  • pixels 110 hatched with oblique lines in the upper right represent pixels 110 with relatively long exposure times. Also, the pixels 110 hatched with oblique lines in the lower right represent the pixels 110 with relatively short exposure times.
  • the pixels 110 with mesh hatching represent the pixels 110 with medium exposure times.
  • FIG. 19 is a diagram showing another configuration example of the pixel block according to the sixth embodiment of the present disclosure.
  • This figure like FIG. 3, is a plan view showing a configuration example of the pixel block 100.
  • the figure shows an example of a pixel block 100 in which eight pixels 110 of 4 rows and 2 columns share the charge holding portion 106 and the signal generating portion 120 .
  • FIG. 20A and 20B are diagrams showing other configuration examples of pixel blocks according to the sixth embodiment of the present disclosure.
  • This figure like FIG. 3, is a plan view showing a configuration example of the pixel block 100. As shown in FIG.
  • FIG. 20A shows an example of a pixel block 100 in which 9 pixels 110 of 3 rows and 3 columns share the charge holding portion 106 and the signal generating portion 120.
  • FIG. 20A shows an example of a pixel block 100 in which 9 pixels 110 of 3 rows and 3 columns share the charge holding portion 106 and the signal generating portion 120.
  • FIG. 20B shows an example of a pixel block 100 in which 16 pixels 110 arranged in 4 rows and 4 columns share the charge holding portion 106 and the signal generating portion 120 .
  • the technology according to the present disclosure can be applied to various products.
  • the technology according to the present disclosure can be applied to imaging devices such as cameras.
  • FIG. 21 is a diagram showing a configuration example of an imaging device to which the technology according to the present disclosure can be applied.
  • An imaging apparatus 1000 shown in FIG. 21 is a diagram showing a configuration example of an imaging device to which the technology according to the present disclosure can be applied.
  • a photographing lens 1006 is a lens that collects light from a subject.
  • the photographing lens 1006 forms an image of the subject on the light receiving surface of the image sensor 1001 .
  • An imaging device 1001 is a device that takes an image of a subject.
  • a plurality of pixels each having a photoelectric conversion unit for performing photoelectric conversion of light from an object are arranged on the light receiving surface of the image sensor 1001 . These pixels each generate an image signal based on charges generated by photoelectric conversion.
  • the image sensor 1001 converts image signals generated by pixels into digital image signals and outputs the digital image signals to the image processing unit 1003 .
  • An image signal for one screen is called a frame.
  • the imaging device 1001 can also output an image signal on a frame-by-frame basis.
  • the control unit 1002 controls the image pickup device 1001 and the image processing unit 1003 .
  • the control unit 1002 can be configured by, for example, an electronic circuit using a microcomputer or the like.
  • the image processing unit 1003 processes the image signal from the imaging device 1001 .
  • the image signal processing in the image processing unit 1003 corresponds to, for example, demosaic processing for generating image signals of insufficient colors when generating a color image, and noise reduction processing for removing noise from image signals.
  • the image processing unit 1003 can be configured by, for example, an electronic circuit using a microcomputer or the like.
  • the display unit 1004 displays an image based on the image signal processed by the image processing unit 1003 .
  • the display unit 1004 can be configured by, for example, a liquid crystal monitor.
  • the recording unit 1005 records an image (frame) based on the image signal processed by the image processing unit 1003 .
  • the recording unit 1005 can be composed of, for example, a hard disk or a semiconductor memory.
  • the imaging device to which the present disclosure can be applied has been described above.
  • the present technology can be applied to the imaging device 1001 among the above components.
  • the image sensor 1 described with reference to FIG. 1 can be applied to the image sensor 1001 .
  • the image processing unit 1003 is an example of an image processing circuit.
  • a first pixel for generating charges by performing photoelectric conversion on incident light with a predetermined wavelength out of incident light and a second pixel for generating charges by performing photoelectric conversion on incident light with a wavelength different from that of the first pixels.
  • a pixel block comprising a control for transferring the charge generated by the first pixel to the charge holding unit and causing the signal generation unit to generate a first image signal, which is the image signal based on the charge;
  • the charge generated by the second pixel is further transferred to the charge holding portion holding the generated charge, and the charge generated by the first pixel and the charge generated by the second pixel are added together.
  • a pixel block control unit that controls the signal generation unit to generate an added image signal that is the image signal based on A first mode for outputting the first image signal and the added image signal, comprising a subtracting unit that generates a second image signal that is the image signal obtained by subtracting the first image signal from the added image signal.
  • a plurality of the first pixels and a plurality of the second pixels are arranged in a square matrix, and the first pixels and the second pixels are arranged alternately in a row direction and a column direction.
  • the imaging device which is configured by: (7) further comprising a reset unit for resetting by discharging the charge in the charge holding unit;
  • the pixel block control unit further performs control to generate a reference image signal, which is an image signal at the time of reset by the reset unit,
  • the signal processing unit corrects the first image signal by subtracting the reference image signal from the first image signal, and corrects the addition image signal by subtracting the reference image signal from the addition image signal.
  • the imaging device further comprising: (8) the first pixel includes a plurality of photoelectric conversion units for pupil-dividing the subject; The pixel block control section transfers the charge generated by one of the plurality of photoelectric conversion sections of the first pixel to the charge holding section and controls the signal generation section to generate an image signal based on the charge. and transferring the charges generated by the plurality of photoelectric conversion units of the first pixel to the charge holding unit, and generating an image signal based on the charges as the first image signal in the signal generation unit.
  • the imaging device according to any one of (1) to (7) above.
  • the signal processing unit further includes an analog-to-digital conversion unit that converts the first image signal and the added image signal into digital signals,
  • the imaging device according to any one of (1) to (6), wherein the signal processing section outputs the first image signal and the added image signal of digital signals converted by the analog-to-digital conversion section.
  • (11) The image pickup device according to (10), wherein the signal processing unit deletes the most significant bit of the added image signal of the digital signal converted by the analog-to-digital conversion unit to match the bit width of the first image signal. .
  • the image pickup device wherein the signal processing unit deletes the least significant bit of the added image signal of the digital signal converted by the analog-to-digital conversion unit to match the bit width of the first image signal. .
  • the pixel block control unit generates a plurality of at least one of the first image signal and the added image signal
  • the analog-to-digital converter converts the plurality of first image signals or the plurality of added image signals into digital signals
  • the signal processing unit outputs an average of the first image signal of a plurality of digital signals or the added image signal of a plurality of digital signals as the first image signal or the added image signal. image sensor.
  • a first pixel for generating charges by performing photoelectric conversion on incident light with a predetermined wavelength out of incident light and a second pixel for generating charges by performing photoelectric conversion on incident light with a wavelength different from that of the first pixels.
  • a pixel block comprising a control for transferring the charge generated by the first pixel to the charge holding unit and causing the signal generation unit to generate a first image signal, which is the image signal based on the charge;
  • the charge generated by the second pixel is further transferred to the charge holding portion holding the generated charge, and the charge generated by the first pixel and the charge generated by the second pixel are added together.
  • a pixel block control unit that controls the signal generation unit to generate an added image signal that is the image signal based on A first mode for outputting the first image signal and the added image signal, comprising a subtracting unit that generates a second image signal that is the image signal obtained by subtracting the first image signal from the added image signal. and a second mode for outputting the first image signal and the second image signal; and a processing circuit that processes at least one of the first image signal, the added image signal, and the second image signal.

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Abstract

The present invention reduces the influence of noise. This imaging element comprises: a pixel block provided with a first pixel that generates an electric charge by performing photoelectric conversion of incident light of a predetermined wavelength, a second pixel that generates an electric charge by performing photoelectric conversion of incident light of a wavelength different from that of the first pixel, an electric charge holding unit that holds the electric charges of the first pixel and the second pixel, and a signal generation unit that generates an image signal on the basis of the electric charges held in the electric charge holding unit; a pixel block control unit that performs control for transferring the electric charge of the first pixel to the electric charge holding unit and causing the signal generation unit to generate a first image signal, and control for further transferring the electric charge of the second pixel to the electric charge holding unit in which the electric charge generated by the first pixel is held and causes the signal generation unit to generate an added image signal; and a signal processing unit that switches between a first mode in which the first image signal and the added image signal are outputted and a second mode in which the first image signal and a second image signal obtained by subtracting the first image signal from the added image signal are outputted.

Description

撮像素子及び電子機器Image sensor and electronic equipment
　本開示は、撮像素子及び電子機器に関する。 The present disclosure relates to imaging devices and electronic devices.
　入射光の光電変換を行う光電変換素子を備える複数の画素において光電変換により生成される電荷を保持する電荷保持部及び電荷保持部の電荷に応じた画像信号を生成する信号生成部を共有する撮像素子が使用されている。このような撮像素子のうち、白色光に対応する画素と白色光以外の光に対応する画素とにおいて上述の電荷保持部（ＦＤ部）及び信号生成部を共有する撮像素子が提案されている（例えば、特許文献１参照）。 Imaging in which a plurality of pixels including photoelectric conversion elements that perform photoelectric conversion of incident light share a charge holding portion that holds charges generated by photoelectric conversion and a signal generation portion that generates an image signal corresponding to the charges in the charge holding portion element is used. Among such image pickup devices, an image pickup device has been proposed in which pixels corresponding to white light and pixels corresponding to light other than white light share the above-described charge holding unit (FD unit) and signal generation unit ( For example, see Patent Document 1).
国際公開第２０１３／１７２２０５号WO2013/172205
　しかしながら、上記の従来技術では、異なる色に対応する画素の電荷を個別に電荷保持部に転送して画像信号を生成する。このため、それぞれの画像信号にはノイズが含まれることとなり、暗所における撮像の際に信号対ノイズ比が悪化するという問題がある。 However, in the conventional technology described above, image signals are generated by individually transferring charges of pixels corresponding to different colors to charge holding units. For this reason, each image signal contains noise, and there is a problem that the signal-to-noise ratio deteriorates when taking an image in a dark place.
　そこで、本開示では、ノイズの影響を低減する撮像素子及び電子機器を提案する。 Therefore, this disclosure proposes an image sensor and an electronic device that reduce the effects of noise.
　本開示は、上述の問題点を解消するためになされたものであり、その第１の態様は、入射光のうちの所定の波長の入射光の光電変換を行って電荷を生成する第１の画素と、上記第１の画素とは異なる波長の入射光の光電変換を行って電荷を生成する第２の画素と、上記第１の画素及び上記第２の画素により生成される電荷を保持する電荷保持部と、上記電荷保持部に保持された電荷に基づいて画像信号を生成する信号生成部とを備える画素ブロックと、上記第１の画素により生成された電荷を上記電荷保持部に転送して当該電荷に基づく上記画像信号である第１の画像信号を上記信号生成部に生成させる制御と、上記第１の画素により生成された電荷が保持された上記電荷保持部に上記第２の画素により生成された電荷を更に転送して上記第１の画素及び上記第２の画素によりそれぞれ生成される電荷が加算された電荷に基づく上記画像信号である加算画像信号を上記信号生成部に生成させる制御とを行う画素ブロック制御部と、上記加算画像信号から上記第１の画像信号を減算した上記画像信号である第２の画像信号を生成する減算部を備え、上記第１の画像信号及び上記加算画像信号を出力する第１のモードと上記第１の画像信号及び上記第２の画像信号を出力する第２のモードとを切り替える信号処理部とを有する撮像素子である。 The present disclosure has been made to solve the above-described problems, and a first aspect thereof is a first aspect in which incident light of a predetermined wavelength out of incident light is photoelectrically converted to generate electric charge. a pixel, a second pixel that performs photoelectric conversion of incident light with a wavelength different from that of the first pixel to generate a charge, and holds the charge generated by the first pixel and the second pixel a pixel block including a charge holding portion and a signal generating portion for generating an image signal based on the charge held in the charge holding portion; and transferring the charge generated by the first pixel to the charge holding portion. and controlling the signal generating section to generate a first image signal, which is the image signal based on the charge, and controlling the second pixel in the charge retaining section in which the charge generated by the first pixel is retained. causing the signal generation unit to generate a sum image signal, which is the image signal based on the charges obtained by adding the charges generated by the first pixel and the second pixel by further transferring the charges generated by and a subtraction unit for generating a second image signal, which is the image signal obtained by subtracting the first image signal from the added image signal, wherein the first image signal and the The imaging device has a signal processing section for switching between a first mode for outputting an added image signal and a second mode for outputting the first image signal and the second image signal.
本開示の実施形態に係る撮像素子の構成例を示す図である。It is a figure showing an example of composition of an image sensor concerning an embodiment of this indication. 本開示の第１の実施形態に係る画素ブロックの構成例を示す図である。1 is a diagram showing a configuration example of a pixel block according to the first embodiment of the present disclosure; FIG. 本開示の第１の実施形態に係る画素ブロックの構成例を示す図である。1 is a diagram showing a configuration example of a pixel block according to the first embodiment of the present disclosure; FIG. 本開示の第１の実施形態に係るカラム信号処理部構成例を示す図である。4 is a diagram illustrating a configuration example of a column signal processing unit according to the first embodiment of the present disclosure; FIG. 本開示の第１の実施形態に係る画像信号の生成の一例を示す図である。FIG. 4 is a diagram illustrating an example of image signal generation according to the first embodiment of the present disclosure; 本開示の第２の実施形態に係る画像信号の一例を示す図である。FIG. 7 is a diagram showing an example of an image signal according to the second embodiment of the present disclosure; FIG. 本開示の第２の実施形態に係る加算画像信号生成の一例を示す図である。FIG. 7 is a diagram illustrating an example of addition image signal generation according to the second embodiment of the present disclosure; 本開示の第３の実施形態に係る画像ブロックの構成例を示す図である。FIG. 11 is a diagram showing a configuration example of an image block according to the third embodiment of the present disclosure; FIG. 本開示の第３の実施形態に係る画素ブロックの電荷の転送の一例を示す図である。FIG. 10 is a diagram illustrating an example of charge transfer in a pixel block according to the third embodiment of the present disclosure; FIG. 本開示の第３の実施形態に係る画像信号の生成の一例を示す図である。FIG. 11 is a diagram illustrating an example of image signal generation according to the third embodiment of the present disclosure; 本開示の第４の実施形態に係る画素ブロックの構成例を示す図である。FIG. 11 is a diagram showing a configuration example of a pixel block according to a fourth embodiment of the present disclosure; FIG. 本開示の第４の実施形態に係る画素ブロックの構成例を示す図である。FIG. 11 is a diagram showing a configuration example of a pixel block according to a fourth embodiment of the present disclosure; FIG. 本開示の第４の実施形態に係る画素ブロックの電荷の転送の一例を示す図である。FIG. 12 is a diagram illustrating an example of charge transfer in a pixel block according to the fourth embodiment of the present disclosure; FIG. 本開示の第４の実施形態に係る画像信号の生成の一例を示す図である。FIG. 12 is a diagram illustrating an example of image signal generation according to the fourth embodiment of the present disclosure; 本開示の第５の実施形態に係る画像信号の生成の一例を示す図である。FIG. 12 is a diagram illustrating an example of image signal generation according to the fifth embodiment of the present disclosure; 本開示の第５の実施形態に係る画像信号の生成の他の例を示す図である。FIG. 12 is a diagram illustrating another example of image signal generation according to the fifth embodiment of the present disclosure; 本開示の第６の実施形態に係る画素ブロックの構成例を示す図である。FIG. 13 is a diagram showing a configuration example of a pixel block according to the sixth embodiment of the present disclosure; FIG. 本開示の第６の実施形態に係る画素ブロックの構成例を示す図である。FIG. 13 is a diagram showing a configuration example of a pixel block according to the sixth embodiment of the present disclosure; FIG. 本開示の第６の実施形態に係る画素ブロックの構成例を示す図である。FIG. 13 is a diagram showing a configuration example of a pixel block according to the sixth embodiment of the present disclosure; FIG. 本開示の第６の実施形態に係る画素ブロックの他の構成例を示す図である。FIG. 21 is a diagram illustrating another configuration example of a pixel block according to the sixth embodiment of the present disclosure; FIG. 本開示の第６の実施形態に係る画素ブロックの他の構成例を示す図である。FIG. 21 is a diagram illustrating another configuration example of a pixel block according to the sixth embodiment of the present disclosure; FIG. 本開示の第６の実施形態に係る画素ブロックの他の構成例を示す図である。FIG. 21 is a diagram illustrating another configuration example of a pixel block according to the sixth embodiment of the present disclosure; FIG. 本開示の第６の実施形態に係る画素ブロックの他の構成例を示す図である。FIG. 21 is a diagram illustrating another configuration example of a pixel block according to the sixth embodiment of the present disclosure; FIG. 本開示の第６の実施形態に係る画素ブロックの他の構成例を示す図である。FIG. 21 is a diagram illustrating another configuration example of a pixel block according to the sixth embodiment of the present disclosure; FIG. 本開示に係る技術が適用され得る撮像装置の構成例を示す図である。1 is a diagram illustrating a configuration example of an imaging device to which technology according to the present disclosure may be applied; FIG.
　以下に、本開示の実施形態について図面に基づいて詳細に説明する。説明は、以下の順に行う。なお、以下の各実施形態において、同一の部位には同一の符号を付することにより重複する説明を省略する。
１．第１の実施形態
２．第２の実施形態
３．第３の実施形態
４．第４の実施形態
５．第５の実施形態
６．第６の実施形態
７．撮像装置 Embodiments of the present disclosure will be described in detail below with reference to the drawings. The explanation is given in the following order. In addition, in each of the following embodiments, the same parts are denoted by the same reference numerals, thereby omitting redundant explanations.
1. First Embodiment 2. Second Embodiment 3. Third Embodiment 4. Fourth Embodiment 5. Fifth embodiment6. Sixth embodiment7. Imaging device
　（１．第１の実施形態）
　［撮像素子の構成］
　図１は、本開示の実施形態に係る撮像素子の構成例を示す図である。同図は、撮像素子１の構成例を表すブロック図である。この撮像素子１を例に挙げて本開示の実施形態に係る半導体素子を説明する。撮像素子１は、被写体の画像データを生成する半導体素子である。撮像素子１は、画素アレイ部１０と、垂直駆動部２０と、カラム信号処理部３０と、制御部４０とを備える。 (1. First embodiment)
[Configuration of imaging device]
FIG. 1 is a diagram showing a configuration example of an imaging device according to an embodiment of the present disclosure. This figure is a block diagram showing a configuration example of the imaging element 1 . A semiconductor device according to an embodiment of the present disclosure will be described by taking this imaging device 1 as an example. The imaging device 1 is a semiconductor device that generates image data of a subject. The imaging device 1 includes a pixel array section 10 , a vertical driving section 20 , a column signal processing section 30 and a control section 40 .
　画素アレイ部１０は、複数の画素ブロック１００が配置されて構成されたものである。この画素アレイ部１０は、複数の画素ブロック１００が２次元行列の形状に配置される。ここで、画素ブロック１００は、入射光の光電変換を行う光電変換部を有する複数の画素と光電変換により生成される電荷を保持する電荷保持部（後述する電荷保持部１０６）とを備えて構成されるものである。その光電変換部には、例えば、フォトダイオードを使用することができる。また、画素ブロック１００毎に画像信号生成部（後述する信号生成部１２０）が配置される。この信号生成部１２０は、画素ブロック１００の電荷保持部１０６に保持された電荷に基づいて画像信号を生成する。 The pixel array section 10 is configured by arranging a plurality of pixel blocks 100 . The pixel array section 10 has a plurality of pixel blocks 100 arranged in a two-dimensional matrix. Here, the pixel block 100 includes a plurality of pixels having photoelectric conversion units that perform photoelectric conversion of incident light and a charge holding unit (charge holding unit 106 described later) that holds charges generated by the photoelectric conversion. It is what is done. A photodiode, for example, can be used for the photoelectric conversion unit. An image signal generator (signal generator 120 to be described later) is arranged for each pixel block 100 . The signal generation section 120 generates an image signal based on the charges held in the charge holding section 106 of the pixel block 100 .
　それぞれの画素ブロック１００及び信号生成部１２０には、信号線１１が配線される。画素ブロック１００及び信号生成部１２０は、信号線１１により伝達される制御信号により制御される。また、信号生成部１２０には、信号線１２が配線される。この信号線１２には、信号生成部１２０から画像信号が出力される。なお、信号線１１は、２次元行列の形状の行毎に配置され、１行に配置された複数の画素ブロック１００及び信号生成部１２０に共通に配線される。信号線１２は、２次元行列の列方向に配置され、１列に配置された複数の画素ブロック１００に共通に配線される。 A signal line 11 is wired to each pixel block 100 and signal generation unit 120 . The pixel block 100 and the signal generator 120 are controlled by control signals transmitted through the signal line 11 . A signal line 12 is wired to the signal generator 120 . An image signal is output from the signal generator 120 to the signal line 12 . The signal line 11 is arranged for each row in a two-dimensional matrix, and is commonly wired to the plurality of pixel blocks 100 and the signal generator 120 arranged in one row. The signal lines 12 are arranged in the column direction of the two-dimensional matrix and are wired commonly to the plurality of pixel blocks 100 arranged in one column.
　垂直駆動部２０は、上述の画素ブロック１００の制御信号を生成するものである。同図の垂直駆動部２０は、画素アレイ部１０の２次元行列の行毎に制御信号を生成し、信号線１１を介して順次出力する。 The vertical driving section 20 generates control signals for the pixel block 100 described above. A vertical drive unit 20 in FIG. 1 generates a control signal for each row of the two-dimensional matrix of the pixel array unit 10 and sequentially outputs the control signal via the signal line 11 .
　カラム信号処理部３０は、画素ブロック１００により生成された画像信号の処理を行うものである。同図のカラム信号処理部３０は、信号線１２を介して伝達される画素アレイ部１０の１行に配置された複数の画素ブロック１００からの画像信号の処理を同時に行う。この処理として、例えば、画素ブロック１００により生成されたアナログの画像信号をデジタルの画像信号に変換するアナログデジタル変換や画像信号のオフセット誤差を除去する相関二重サンプリング（ＣＤＳ：Correlated　Double　Sampling）を行うことができる。処理後の画像信号は、撮像素子１の外部の回路等に対して出力される。 The column signal processing unit 30 processes image signals generated by the pixel block 100 . A column signal processing unit 30 shown in the figure simultaneously processes image signals from a plurality of pixel blocks 100 arranged in one row of the pixel array unit 10 and transmitted through the signal line 12 . As this processing, for example, analog-to-digital conversion that converts the analog image signal generated by the pixel block 100 into a digital image signal and correlated double sampling (CDS: Correlated Double Sampling) that removes the offset error of the image signal are performed. be able to. The processed image signal is output to a circuit or the like outside the imaging device 1 .
　制御部４０は、垂直駆動部２０及びカラム信号処理部３０を制御するものである。同図の制御部４０は、信号線４１及び４２を介して制御信号をそれぞれ出力して垂直駆動部２０及びカラム信号処理部３０を制御する。なお、同図の垂直駆動部２０は、画素ブロック制御部の一例である。カラム信号処理部３０は、信号処理部の一例である。 The control unit 40 controls the vertical driving unit 20 and the column signal processing unit 30. A control unit 40 shown in the figure outputs control signals through signal lines 41 and 42 to control the vertical driving unit 20 and the column signal processing unit 30 . It should be noted that the vertical drive unit 20 shown in the figure is an example of a pixel block control unit. The column signal processing section 30 is an example of a signal processing section.
　［画素ブロックの構成］
　図２は、本開示の第１の実施形態に係る画素ブロックの構成例を示す図である。同図は、画素ブロック１００の構成例を表す回路図である。なお、同図には、垂直駆動部２０及びカラム信号処理部３０を更に記載した。同図の画素ブロック１００は、画素１１０ａ－１１０ｄと、電荷保持部１０６と、リセットトランジスタ１０４と、信号生成部１２０とを備える。 [Configuration of pixel block]
FIG. 2 is a diagram showing a configuration example of a pixel block according to the first embodiment of the present disclosure. This figure is a circuit diagram showing a configuration example of the pixel block 100 . In addition, the vertical driving section 20 and the column signal processing section 30 are further shown in the figure. The pixel block 100 in FIG.
　画素１１０ａは、光電変換部１０１ａ及び電荷転送部１０２ａを備える。画素１１０ｂは、光電変換部１０１ｂ及び電荷転送部１０２ｂを備える。画素１１０ｃは、光電変換部１０１ｃ及び電荷転送部１０２ｃを備える。画素１１０ｄは、光電変換部１０１ｄ及び電荷転送部１０２ｄを備える。光電変換部１０１ａ－１０１ｄには、フォトダイオードを使用することができる。電荷転送部１０２ａ－１０２ｄには、ｎチャネルＭＯＳトランジスタを使用することができる。 The pixel 110a includes a photoelectric conversion unit 101a and a charge transfer unit 102a. The pixel 110b includes a photoelectric conversion portion 101b and a charge transfer portion 102b. The pixel 110c includes a photoelectric conversion portion 101c and a charge transfer portion 102c. The pixel 110d includes a photoelectric conversion portion 101d and a charge transfer portion 102d. Photodiodes can be used for the photoelectric conversion units 101a to 101d. N-channel MOS transistors can be used for the charge transfer units 102a-102d.
　信号生成部１２０は、増幅トランジスタ１２１及び選択トランジスタ１２２を備える。リセットトランジスタ１０４、増幅トランジスタ１２１及び選択トランジスタ１２２には、ｎチャネルＭＯＳトランジスタを使用することができる。このｎチャネルＭＯＳトランジスタでは、ゲート－ソース間電圧Ｖｇｓの閾値を超える電圧をゲートに印加することにより、ドレイン－ソース間を導通させることができる。以下、このゲート－ソース間電圧Ｖｇｓの閾値を超える電圧をオン電圧と称する。また、このオン電圧を含む制御信号をオン信号と称する。制御信号は、信号線ＴＧ１等により伝達される。 The signal generator 120 includes an amplification transistor 121 and a selection transistor 122 . N-channel MOS transistors can be used for the reset transistor 104, the amplification transistor 121, and the selection transistor 122. FIG. In this n-channel MOS transistor, the drain-source can be made conductive by applying a voltage exceeding the threshold of the gate-source voltage Vgs to the gate. A voltage exceeding the threshold of the gate-source voltage Vgs is hereinafter referred to as an on-voltage. A control signal including this on-voltage is called an on-signal. A control signal is transmitted by a signal line TG1 or the like.
　前述のように、画素ブロック１００には、信号線１１及び信号線１２が配線される。同図の信号線１１には、信号線ＴＧ１－ＴＧ４、信号線ＲＳＴ及び信号線ＳＥＬが含まれる。この他、画素ブロック１００には、電源線Ｖｄｄが配線される。この電源線Ｖｄｄは、画素ブロック１００に電源を供給する配線である。 As described above, the signal lines 11 and 12 are wired in the pixel block 100 . The signal lines 11 in the figure include signal lines TG1 to TG4, a signal line RST, and a signal line SEL. In addition, the pixel block 100 is wired with a power line Vdd. The power line Vdd is a wiring for supplying power to the pixel block 100 .
　光電変換部１０１ａのアノードは接地され、カソードは電荷転送部１０２ａのソースに接続される。光電変換部１０１ｂのアノードは接地され、カソードは電荷転送部１０２ｂのソースに接続される。光電変換部１０１ｃのアノードは接地され、カソードは電荷転送部１０２ｃのソースに接続される。光電変換部１０１ｄのアノードは接地され、カソードは電荷転送部１０２ｄのソースに接続される。 The anode of the photoelectric conversion unit 101a is grounded, and the cathode is connected to the source of the charge transfer unit 102a. The photoelectric conversion unit 101b has an anode grounded and a cathode connected to the source of the charge transfer unit 102b. The photoelectric conversion unit 101c has an anode grounded and a cathode connected to the source of the charge transfer unit 102c. The photoelectric conversion unit 101d has an anode grounded and a cathode connected to the source of the charge transfer unit 102d.
　電荷転送部１０２ａ－１０２ｄのドレインは、リセットトランジスタ１０４のソース、増幅トランジスタ１２１のゲート及び電荷保持部１０６の一端に接続される。電荷保持部１０６の他の一端は、接地される。リセットトランジスタ１０４のドレイン及び増幅トランジスタ１２１のドレインは、電源線Ｖｄｄに接続される。増幅トランジスタ１２１のソースは選択トランジスタ１２２のドレインに接続され、選択トランジスタ１２２のソースは信号線１２に接続される。 The drains of the charge transfer units 102 a to 102 d are connected to the source of the reset transistor 104 , the gate of the amplification transistor 121 and one end of the charge holding unit 106 . Another end of the charge holding unit 106 is grounded. The drain of the reset transistor 104 and the drain of the amplification transistor 121 are connected to the power supply line Vdd. The source of the amplification transistor 121 is connected to the drain of the selection transistor 122 and the source of the selection transistor 122 is connected to the signal line 12 .
　電荷転送部１０２ａ－１０２ｄのゲートは信号線ＴＧ１－ＴＧ４にそれぞれ接続される。リセットトランジスタ１０４のゲートは信号線ＲＳＴに接続され、選択トランジスタ１２２のゲートは信号線ＳＥＬに接続される。 The gates of the charge transfer units 102a-102d are connected to the signal lines TG1-TG4, respectively. A gate of the reset transistor 104 is connected to the signal line RST, and a gate of the select transistor 122 is connected to the signal line SEL.
　光電変換部１０１ａ－１０１ｄは、入射光の光電変換を行うものである。この光電変換部１０１ａ－１０１ｄは、半導体基板に形成されるフォトダイオードにより構成することができる。光電変換部１０１ａ－１０１ｄは、露光期間において入射光の光電変換を行うとともに光電変換により生成される電荷を保持する。 The photoelectric conversion units 101a-101d perform photoelectric conversion of incident light. The photoelectric conversion units 101a to 101d can be composed of photodiodes formed on a semiconductor substrate. The photoelectric conversion units 101a to 101d perform photoelectric conversion of incident light during the exposure period and hold charges generated by the photoelectric conversion.
　電荷保持部１０６は、光電変換部１０１ａ－１０１ｄにより生成される電荷を保持するものである。電荷保持部１０６は、半導体基板に形成される半導体領域である浮遊拡散領域（ＦＤ：Floating　Diffusion）により構成することができる。 The charge holding unit 106 holds charges generated by the photoelectric conversion units 101a to 101d. The charge holding portion 106 can be configured by a floating diffusion region (FD: Floating Diffusion), which is a semiconductor region formed in a semiconductor substrate.
　電荷転送部１０２ａ－１０２ｄは、電荷を転送するものである。この電荷転送部１０２ａ－１０２ｄは、光電変換部１０１ａ－１０１ｄにより生成された電荷を電荷保持部１０６にそれぞれ転送する。この電荷転送部１０２ａ等は、光電変換部１０１ａ等と電荷保持部１０６との間をそれぞれ導通させることにより、電荷を転送する。電荷転送部１０２ａ－１０２ｈの制御信号は、信号線ＴＧ１－ＴＧ４によりそれぞれ伝達される。 The charge transfer units 102a-102d transfer charges. The charge transfer units 102a-102d transfer the charges generated by the photoelectric conversion units 101a-101d to the charge holding unit 106, respectively. The charge transfer units 102a and the like transfer charges by establishing electrical continuity between the photoelectric conversion units 101a and the like and the charge holding unit 106, respectively. Control signals for the charge transfer units 102a-102h are transmitted by signal lines TG1-TG4, respectively.
　リセットトランジスタ１０４は、電荷保持部１０６をリセットするものである。このリセットは、電荷保持部１０６と電源線Ｖｄｄとの間を導通して電荷保持部１０６の電荷を排出することにより行うことができる。リセットトランジスタ１０４の制御信号は、信号線ＲＳＴにより伝達される。なお、リセットトランジスタ１０４は、リセット部の一例である。 The reset transistor 104 resets the charge holding section 106 . This reset can be performed by conducting between the charge holding portion 106 and the power supply line Vdd to discharge the charge in the charge holding portion 106 . A control signal for the reset transistor 104 is transmitted through a signal line RST. Note that the reset transistor 104 is an example of a reset unit.
　信号生成部１２０は、電荷保持部１０６に保持される電荷に基づいて画像信号を生成するものである。前述のように、信号生成部１２０は、増幅トランジスタ１２１及び選択トランジスタ１２２により構成される。 The signal generation section 120 generates an image signal based on the charges held in the charge holding section 106 . As described above, the signal generator 120 is composed of the amplification transistor 121 and the selection transistor 122 .
　増幅トランジスタ１２１は、電荷保持部１０６の電圧を増幅するものである。増幅トランジスタ１２１のゲートは、電荷保持部１０６に接続されている。このため、増幅トランジスタ１２１のソースには、電荷保持部１０６に保持された電荷に応じた電圧の画像信号が生成される。また、選択トランジスタ１２２を導通させることにより、この画像信号を信号線１２に出力させることができる。選択トランジスタ１２２の制御信号は、信号線ＳＥＬにより伝達される。 The amplification transistor 121 amplifies the voltage of the charge holding section 106 . A gate of the amplification transistor 121 is connected to the charge holding unit 106 . Therefore, an image signal is generated at the source of the amplification transistor 121 with a voltage corresponding to the charge held in the charge holding unit 106 . Also, the image signal can be output to the signal line 12 by turning on the selection transistor 122 . A control signal for the select transistor 122 is transmitted by a signal line SEL.
　光電変換部１０１ａ－１０１ｄは、露光期間に入射光の光電変換を行って電荷を生成し、自身に蓄積する。露光期間の経過後に、電荷転送部１０２ａ－１０２ｄにより光電変換部１０１ａ－１０１ｄの電荷が電荷保持部１０６に転送されて保持される。この保持された電荷に基づいて信号生成部１２０により画像信号が生成される。 The photoelectric conversion units 101a to 101d perform photoelectric conversion of incident light during the exposure period to generate charges and store them in themselves. After the exposure period has elapsed, the charges of the photoelectric conversion units 101a to 101d are transferred to and held by the charge holding unit 106 by the charge transfer units 102a to 102d. An image signal is generated by the signal generator 120 based on the held charge.
　後述するように、画素１１０ａ及び画素１１０ｃには同じ波長の入射光を透過するカラーフィルタが配置される。この画素１１０ａ及び画素１１０ｃを第１の画素と称する。第１の画素は、配置されるカラーフィルタに応じた波長の入射光の光電変換を行う。第１の画素には、例えば、赤色光、緑色光及び青色光の何れかを透過するカラーフィルタを配置することができる。 As will be described later, the pixels 110a and 110c are provided with color filters that transmit incident light of the same wavelength. The pixels 110a and 110c are called first pixels. The first pixel photoelectrically converts incident light having a wavelength corresponding to the color filter arranged. For example, a color filter that transmits any one of red light, green light, and blue light can be arranged in the first pixel.
　また、画素１１０ｂ及び画素１１０ｄには、第１の画素である画素１１０ａ及び画素１１０ｃのカラーフィルタとは異なる波長の入射光を透過するカラーフィルタが配置される。この画素１１０ｂ及び画素１１０ｄを第２の画素と称する。第２の画素は、第１の画素とは異なる波長の入射光の光電変換を行う。第２の画素には、例えば、白色光を透過するカラーフィルタを配置することができる。 Also, the pixels 110b and 110d are provided with color filters that transmit incident light having a wavelength different from that of the color filters of the pixels 110a and 110c, which are the first pixels. The pixels 110b and 110d are called second pixels. The second pixel photoelectrically converts incident light with a wavelength different from that of the first pixel. For example, a color filter that transmits white light can be arranged in the second pixel.
　前述のように、画素ブロック１００においては、画素１１０ａ－１１０ｄが電荷保持部１０６、リセットトランジスタ１０４及び信号生成部１２０を共有する。このため、画素１１０ａ－１１０ｄの画像信号を個別に生成すること及び画素１１０ａ－１１０ｄのうちの複数の画素１１０の画像信号を同時に生成することが可能である。 As described above, in pixel block 100, pixels 110a-110d share charge storage portion 106, reset transistor 104 and signal generation portion 120. FIG. Therefore, it is possible to generate image signals for the pixels 110a-110d individually and simultaneously generate image signals for a plurality of pixels 110 out of the pixels 110a-110d.
　例えば、第１の画素である画素１１０ａ及び画素１１０ｃの画像信号を生成する場合には、電荷転送部１０２ａ及び１０２ｃを同時に導通させて光電変換部１０１ａ及び１０１ｄの電荷を電荷保持部１０６に転送し、信号生成部１２０に画像信号を生成させることにより行うことができる。この第１の画素の電荷に基づいて生成された画像信号を第１の画像信号と称する。第１の画素には、赤色光、緑色光及び青色光に対応するカラーフィルタが配置されるため、赤色光、緑色光及び青色光に対応する画像信号が生成される。なお、赤色光、緑色光及び青色光に対応する画像信号をそれぞれＲ画像信号、Ｇ画像信号及びＢ画像信号と称する。これらＲ画像信号、Ｇ画像信号及びＢ画像信号は、第１の画像信号に相当する。同図の「Ｒ」、「Ｇ」及び「Ｂ」は、それぞれＲ画像信号、Ｇ画像信号及びＢ画像信号を表す。 For example, when generating image signals for the pixels 110a and 110c, which are the first pixels, the charge transfer units 102a and 102c are made conductive at the same time to transfer the charges of the photoelectric conversion units 101a and 101d to the charge holding unit 106. , by causing the signal generator 120 to generate an image signal. An image signal generated based on the charge of the first pixel is called a first image signal. Since color filters corresponding to red light, green light and blue light are arranged in the first pixel, image signals corresponding to red light, green light and blue light are generated. Image signals corresponding to red light, green light, and blue light are referred to as R image signal, G image signal, and B image signal, respectively. These R image signal, G image signal and B image signal correspond to the first image signal. "R", "G" and "B" in the figure represent the R image signal, the G image signal and the B image signal, respectively.
　上述の第１の画素（画素１１０ａ及び画素１１０ｃ）の電荷を電荷保持部１０６に転送した後に第２の画素（画素１１０ｂ及び画素１１０ｄ）の電荷を電荷保持部１０６に更に転送することもできる。具体的には、上述の第１の画像信号を生成した後に、電荷保持部１０６における第１の画素の電荷を保持した状態において、電荷転送部１０２ｂ及び１０２ｄを導通させて、第２の画素（画素１１０ｂ及び画素１１０ｄ）の電荷を加算する。次に、信号生成部１２０に画像信号を生成させることにより、第１の画素及び第２の画素によりそれぞれ生成される電荷が加算された電荷に基づく画像信号を生成することができる。この画像信号を加算画像信号と称する。第２の画素には、白色光に対応するカラーフィルタが配置されるため、加算画像信号は、赤色光、緑色光及び青色光に対応する画像信号に白色光に対応する画像信号が加算された画像信号となる。 It is also possible to transfer the charges of the second pixels ( pixels 110b and 110d) to the charge holding portion 106 after the charges of the first pixels ( pixels 110a and 110c) are transferred to the charge holding portion 106 described above. Specifically, after the above-described first image signal is generated, the charge transfer units 102b and 102d are made conductive in a state where the charge of the first pixel is held in the charge holding unit 106, and the second pixel ( The charges of pixels 110b and 110d) are summed. Next, by causing the signal generation unit 120 to generate an image signal, it is possible to generate an image signal based on charges obtained by adding the charges generated by the first pixel and the second pixel. This image signal is called an added image signal. Since a color filter corresponding to white light is arranged in the second pixel, the added image signal is obtained by adding the image signal corresponding to white light to the image signal corresponding to red light, green light, and blue light. image signal.
　なお、赤色光に対応する画像信号に白色光に対応する画像信号が加算された画像信号をＲ＋Ｗ画像信号と称する。緑色光に対応する画像信号に白色光に対応する画像信号が加算された画像信号をＧ＋Ｗ画像信号と称する。青色光に対応する画像信号に白色光に対応する画像信号が加算された画像信号をＢ＋Ｗ画像信号と称する。これらＲ＋Ｗ画像信号、Ｇ＋Ｗ画像信号及びＢ＋Ｗ画像信号は、加算画像信号に相当する。同図の「Ｒ＋Ｗ」、「Ｇ＋Ｗ」及び「Ｂ＋Ｗ」は、それぞれＲ＋Ｗ画像信号、Ｇ＋Ｗ画像信号及びＢ＋Ｗ画像信号を表す。 An image signal obtained by adding an image signal corresponding to white light to an image signal corresponding to red light is called an R+W image signal. An image signal obtained by adding an image signal corresponding to white light to an image signal corresponding to green light is called a G+W image signal. An image signal obtained by adding an image signal corresponding to white light to an image signal corresponding to blue light is called a B+W image signal. These R+W image signal, G+W image signal and B+W image signal correspond to the added image signal. "R+W", "G+W" and "B+W" in the figure represent the R+W image signal, the G+W image signal and the B+W image signal, respectively.
　同図の垂直駆動部２０は、信号線ＴＧ１等を介して制御信号を画素ブロック１００に出力し、画素ブロック１００に第１の画像信号及び加算画像信号を生成させる制御を行う。すなわち、垂直駆動部２０は、第１の画素により生成された電荷を電荷保持部１０６に転送して信号生成部１２０に第１の画像信号を生成させる制御を行う。また、垂直駆動部２０は、第１の画素により生成された電荷が保持された電荷保持部１０６に第２の画素により生成された電荷を更に転送して信号生成部１２０に加算画像信号を生成させる制御を更に行う。また、第１の画像信号の生成に先立って、垂直駆動部２０は、電荷保持部１０６をリセットする制御を更に行う。 The vertical drive section 20 in the figure outputs a control signal to the pixel block 100 via the signal line TG1 or the like, and controls the pixel block 100 to generate the first image signal and the added image signal. That is, the vertical drive section 20 transfers the charge generated by the first pixel to the charge holding section 106 and controls the signal generation section 120 to generate the first image signal. In addition, the vertical driving unit 20 further transfers the charges generated by the second pixels to the charge holding unit 106 that holds the charges generated by the first pixels, and generates an addition image signal in the signal generation unit 120. Further control is performed. Prior to generating the first image signal, the vertical driving section 20 further performs control to reset the charge holding section 106 .
　また、垂直駆動部２０は、リセット時に信号生成部１２０に画像信号を生成させる制御を更に行う。この画像信号をリセット時の画像信号と称する。このリセット時の画像信号により後述するＣＤＳを行うことができる。リセット時の画像信号は、基準画像信号の一例である。 In addition, the vertical driving section 20 further controls the signal generating section 120 to generate an image signal at the time of resetting. This image signal is called an image signal at the time of reset. CDS, which will be described later, can be performed by the image signal at the time of this reset. The image signal at reset is an example of the reference image signal.
　なお、加算画像信号から第１の画像信号を減算することにより第２の画素の電荷に基づく画像信号を生成することができる。この画像信号を第２の画像信号と称する。上述のように、第２の画素（画素１１０ｂ及び画素１１０ｄ）には、白色光に対応するカラーフィルタが配置されるため、第２の画像信号は、白色光に対応する画像信号となる。なお、白色光に対応する画像信号をＷ画像信号と称する。Ｗ画像信号は、第２の画像信号に相当する。 By subtracting the first image signal from the added image signal, an image signal based on the charge of the second pixel can be generated. This image signal is called a second image signal. As described above, the second pixels (the pixels 110b and 110d) are provided with color filters corresponding to white light, so the second image signal is an image signal corresponding to white light. An image signal corresponding to white light is called a W image signal. The W image signal corresponds to the second image signal.
　同図のカラム信号処理部３０は、第１の画像信号及び加算画像信号を処理する。カラム信号処理部３０には、減算部３４が配置される。この減算部３４は、加算画像信号から第１の画像信号を減算して第２の画像信号を生成するものである。カラム信号処理部３０は、第１の画像信号（Ｒ画像信号、Ｇ画像信号及びＢ画像信号）及び加算画像信号（Ｒ＋Ｗ画像信号、Ｇ＋Ｗ画像信号及びＢ＋Ｗ画像信号）を出力するモードと第１の画像信号及び減算部３４により生成された第２の画像信号（Ｗ画像信号）を出力するモードとを切り替えることができる。第１の画像信号及び加算画像信号を出力するモードを第１のモードと称する。また、第１の画像信号及び第２の画像信号を出力するモードを第２のモードと称する。モードの切替えは、例えば、図１の制御部４０の制御に基づいて行うことができる。なお、同図の「Ｗ」は、Ｗ画像信号を表す。 The column signal processing unit 30 in the figure processes the first image signal and the added image signal. A subtraction unit 34 is arranged in the column signal processing unit 30 . The subtractor 34 subtracts the first image signal from the added image signal to generate the second image signal. The column signal processing unit 30 outputs a first image signal (R image signal, G image signal and B image signal) and added image signals (R+W image signal, G+W image signal and B+W image signal) and a first mode. The mode of outputting the image signal and the second image signal (W image signal) generated by the subtraction unit 34 can be switched. A mode in which the first image signal and the added image signal are output is called a first mode. A mode in which the first image signal and the second image signal are output is called a second mode. Mode switching can be performed, for example, under the control of the control unit 40 in FIG. Note that "W" in the figure represents a W image signal.
　［画素ブロックの平面の構成］
　図３は、本開示の第１の実施形態に係る画素ブロックの構成例を示す図である。同図は、画素ブロック１００の構成例を表す平面図である。なお、同図には、リセット時、第１の画像信号生成時及び加算画像信号生成時の電荷保持部１０６の様子を更に記載した。 [Structure of Plane of Pixel Block]
FIG. 3 is a diagram illustrating a configuration example of a pixel block according to the first embodiment of the present disclosure; This figure is a plan view showing a configuration example of the pixel block 100 . In addition, the state of the charge holding unit 106 at the time of resetting, the generation of the first image signal, and the generation of the added image signal is also shown in FIG.
　同図の上段の左端の図を使用して画素ブロック１００の構成を説明する。同図の上段の左端の図において、矩形は画素１１０ａ－１１０ｄを表す。また、点線の矩形は、画素ブロック１００を表す。同図の画素ブロック１００は、画素１１０ａ－１１０ｄが２行２列に配置される例を表したものである。同図の画素１１０ａ等に付された文字は、生成される画像信号の種類を表す。 The configuration of the pixel block 100 will be described using the leftmost drawing in the upper row of the figure. In the leftmost drawing in the upper row of the figure, the rectangles represent pixels 110a to 110d. A dotted rectangle represents a pixel block 100 . A pixel block 100 in the figure represents an example in which pixels 110a to 110d are arranged in two rows and two columns. The letters attached to the pixels 110a, etc. in the figure represent the types of image signals to be generated.
　同図の上段の左端の図において、左上の画素ブロック１００及び右下の画素ブロック１００においては、第１の画素（画素１１０ａ及び画素１１０ｃ）はＧ画像信号を生成し、第２の画素（画素１１０ｂ及び画素１１０ｄ）はＷ画像信号を生成する。また、右上の画素ブロック１００においては、第１の画素（画素１１０ａ及び画素１１０ｃ）はＢ画像信号を生成し、第２の画素（画素１１０ｂ及び画素１１０ｄ）はＷ画像信号を生成する。また、左下の画素ブロック１００においては、第１の画素（画素１１０ａ及び画素１１０ｃ）はＲ画像信号を生成し、第２の画素（画素１１０ｂ及び画素１１０ｄ）はＷ画像信号を生成する。このような４つの画素ブロック１００が画素アレイ部１０に配列される。このように、画素ブロック１００は、２つの第１の画素及び２つの第２の画素が２行２列の正方行列に配置され、第１の画素及び第２の画素が行方向及び列方向に交互に配置される。 In the upper leftmost drawing of the figure, in the upper left pixel block 100 and the lower right pixel block 100, the first pixels ( pixels 110a and 110c) generate G image signals, and the second pixels (pixels 110b and pixels 110d) produce the W image signal. In the upper right pixel block 100, the first pixels ( pixels 110a and 110c) generate B image signals, and the second pixels ( pixels 110b and 110d) generate W image signals. In the lower left pixel block 100, the first pixels ( pixels 110a and 110c) generate R image signals, and the second pixels ( pixels 110b and 110d) generate W image signals. Such four pixel blocks 100 are arranged in the pixel array section 10 . Thus, in the pixel block 100, two first pixels and two second pixels are arranged in a square matrix of 2 rows and 2 columns, and the first pixels and the second pixels are arranged in the row direction and the column direction. alternately arranged.
　なお、同図の下段は、左上の画素ブロック１００の電荷保持部１０６の状態を表すポテンシャル図である。同図の左端は、リセット時の画素ブロック１００及び電荷保持部１０６の様子を表したものである。リセットにより、電荷保持部１０６の電荷が排出された状態となる。 Note that the lower part of the figure is a potential diagram showing the state of the charge holding portion 106 of the upper left pixel block 100 . The left end of the figure shows the states of the pixel block 100 and the charge holding portion 106 at the time of resetting. By resetting, the charge in the charge holding portion 106 is discharged.
　同図の中央は、第１の画素の電荷が電荷保持部１０６に転送された状態を表す。この際、第１の画像信号が生成される。画素ブロック１００の図において、点ハッチングが付された画素は電荷が転送された画素を表す。同図に表したように、第１の画素（画素１１０ａ及び画素１１０ｃ）の電荷が電荷保持部１０６に転送される。同図の括弧書きの部分は、それぞれの画素ブロック１００の信号生成部１２０により生成される画像信号を表したものである。４つの画素ブロック１００においてＲ画像信号、Ｇ画像信号及びＢ画像信号が生成される。また、電荷保持部１０６は、第１の画素（画素１１０ａ及び画素１１０ｃ）の電荷を保持する。同図の電荷保持部１０６のポテンシャル図の「Ｇ」が付された矩形は、第１の画素（画素１１０ａ及び画素１１０ｃ）からの電荷を表す。 The center of the figure represents the state in which the charge of the first pixel has been transferred to the charge holding portion 106 . At this time, a first image signal is generated. In the diagram of pixel block 100, the dotted hatched pixels represent pixels to which charge has been transferred. As shown in the figure, the charges of the first pixels (pixel 110a and pixel 110c) are transferred to the charge holding portion 106. FIG. The parts in parentheses in FIG. The four pixel blocks 100 generate an R image signal, a G image signal and a B image signal. Also, the charge holding unit 106 holds the charge of the first pixels (pixel 110a and pixel 110c). Rectangles marked with "G" in the potential diagram of the charge holding portion 106 in the figure represent charges from the first pixels (pixel 110a and pixel 110c).
　このように、第１の画像信号を生成した後の電荷保持部１０６のリセットを行わずに第２の画素の電荷を電荷保持部１０６に転送して加算する。これにより、画像信号のレベルを高くすることができ、信号対ノイズ比を向上させることができる。また、第１の画素の電荷及び第２の画素の電荷を加算して加算画像信号を生成するため、それぞれの電荷に含まれるノイズ成分が平準化され。これにより、加算画像信号のノイズを低減することもできる。 In this way, the charge of the second pixel is transferred to the charge holding unit 106 and added without resetting the charge holding unit 106 after generating the first image signal. Thereby, the level of the image signal can be increased, and the signal-to-noise ratio can be improved. Further, since the sum image signal is generated by adding the charges of the first pixels and the charges of the second pixels, the noise components contained in the respective charges are leveled. Thereby, the noise of the addition image signal can also be reduced.
　同図の右端は、第２の画素の電荷が電荷保持部１０６に転送された状態を表す。この際、加算画像信号が生成される。画素ブロック１００の図において、点ハッチングが付された画素は電荷が転送された画素を表す。同図に表したように、第２の画素（画素１１０ｂ及び画素１１０ｄ）の電荷が電荷保持部１０６に転送される。同図の括弧書きの部分において、４つの画素ブロック１００におけるＲ画像信号、Ｇ画像信号及びＢ画像信号にＷ信号が加算された加算画像信号が生成される。また、電荷保持部１０６は、第１の画素（画素１１０ａ及び画素１１０ｃ）の電荷と第２の画素（画素１１０ｂ及び画素１１０ｄ）の電荷とを保持する。同図の電荷保持部１０６のポテンシャル図に記載された「Ｗ」が付された矩形は、第２の画素（画素１１０ａ及び画素１１０ｃ）からの電荷を表す。 The right end of the figure represents the state in which the charge of the second pixel has been transferred to the charge holding portion 106 . At this time, an added image signal is generated. In the diagram of pixel block 100, the dotted hatched pixels represent pixels to which charge has been transferred. As shown in the figure, the charges of the second pixels (pixel 110b and pixel 110d) are transferred to the charge holding portion 106. FIG. In the parenthesized portions in the figure, an added image signal is generated by adding the W signal to the R image signal, G image signal, and B image signal in the four pixel blocks 100 . Also, the charge holding unit 106 holds the charges of the first pixels (the pixels 110a and 110c) and the charges of the second pixels (the pixels 110b and 110d). Rectangles marked with "W" in the potential diagram of the charge holding portion 106 in FIG.
　［カラム信号処理部の構成］
　図４は、本開示の第１の実施形態に係るカラム信号処理部構成例を示す図である。同図は、カラム信号処理部３０の構成例を表すブロック図である。同図のカラム信号処理部３０は、参照信号生成部３２と、アナログデジタル変換部３１と、保持部３３と、減算部３４と、信号処理部３５と、ベイヤー配列変換部３６と、信号処理部３７と、インターフェイス部３８とを備える。 [Configuration of Column Signal Processing Unit]
FIG. 4 is a diagram illustrating a configuration example of a column signal processing unit according to the first embodiment of the present disclosure; This figure is a block diagram showing a configuration example of the column signal processing unit 30. As shown in FIG. The column signal processing unit 30 in FIG. 37 and an interface unit 38 .
　参照信号生成部３２は、参照信号を生成してアナログデジタル変換部３１に供給するものである。この参照信号は、ランプ関数状に値が変化する信号である。 The reference signal generator 32 generates a reference signal and supplies it to the analog-to-digital converter 31 . This reference signal is a signal whose value changes like a ramp function.
　アナログデジタル変換部３１は、画像信号のアナログデジタル変換を行うものである。このアナログデジタル変換部３１は、画素１１０により生成されたアナログの画像信号をデジタルの画像信号に変換する。同図のアナログデジタル変換部３１は、参照信号生成部３２から出力される参照信号に基づいてアナログの画像信号をデジタルの画像信号に変換する。具体的には、アナログデジタル変換部３１は、アナログの画像信号と参照信号との比較を行ってアナログの画像信号と参照信号とが一致するまでの期間を検出する。参照信号は経過時間に応じた電圧の信号であるため、参照信号の出力の開始からアナログの画像信号と一致するまでの期間はアナログの画像信号の電圧に応じた期間となる。この期間に応じたデジタルの信号を出力することにより、アナログの画像信号をデジタルの画像信号に変換することができる。 The analog-to-digital converter 31 performs analog-to-digital conversion of image signals. The analog-to-digital converter 31 converts analog image signals generated by the pixels 110 into digital image signals. An analog-to-digital converter 31 in FIG. 1 converts an analog image signal into a digital image signal based on the reference signal output from the reference signal generator 32 . Specifically, the analog-to-digital converter 31 compares the analog image signal and the reference signal and detects a period until the analog image signal and the reference signal match. Since the reference signal is a voltage signal corresponding to the elapsed time, the period from the start of the output of the reference signal until it matches the analog image signal corresponds to the voltage of the analog image signal. By outputting a digital signal corresponding to this period, an analog image signal can be converted into a digital image signal.
　保持部３３は、アナログデジタル変換部３１によりデジタルの信号に変換された画像信号を保持するものである。また、保持部３３は、ＣＤＳを行うことができる。このＣＤＳは、画像信号から前述のリセット時の画像信号の差分を取ることによりオフセット（ノイズ）分を除去する処理である。図２において説明した電荷保持部１０６には、リセットにおいて排出されない電荷が残留する。この残留する電荷に基づく信号成分は、画像信号のオフセット成分となりノイズの原因となる。そこで、リセット時の画像信号を保持し、第１の画像信号や加算画像信号からリセット時の画像信号を減算することにより、オフセット成分を除去することができる。同図の保持部３３は、リセット時の画像信号の保持と第１の画像信号からからリセット時の画像信号を減算する処理とを行うことができる。このＣＤＳを行うことにより、画像信号のノイズを低減することができる。 The holding unit 33 holds the image signal converted into a digital signal by the analog-to-digital conversion unit 31 . Further, the holding unit 33 can perform CDS. This CDS is a process of removing the offset (noise) by taking the difference of the image signal at the time of resetting from the image signal. Charges that are not discharged at reset remain in the charge holding unit 106 described with reference to FIG. A signal component based on this remaining charge becomes an offset component of an image signal and causes noise. Therefore, the offset component can be removed by holding the image signal at the time of reset and subtracting the image signal at the time of reset from the first image signal or the added image signal. The holding unit 33 shown in the figure can hold the image signal at the time of resetting and the process of subtracting the image signal at the time of resetting from the first image signal. By performing this CDS, noise in the image signal can be reduced.
　減算部３４は、前述のように加算画像信号から第１の画像信号を減算して第２の画像信号を生成するものである。 The subtraction unit 34 subtracts the first image signal from the added image signal to generate the second image signal as described above.
　信号処理部３５は、モードに応じて出力する画像信号を選択するものである。信号処理部３５は、第１のモードが選択された際に第１の画像信号及び加算画像信号を出力し、第２のモードが選択された際には第１の画像信号及び第２の画像信号を出力する。 The signal processing unit 35 selects an image signal to be output according to the mode. The signal processing unit 35 outputs the first image signal and the added image signal when the first mode is selected, and outputs the first image signal and the second image signal when the second mode is selected. Output a signal.
　ベイヤー配列変換部３６は、第１の画像信号等をベイヤー配列の画像信号に変換するものである。 The Bayer array conversion unit 36 converts the first image signal or the like into a Bayer array image signal.
　信号処理部３７は、画像信号の補間処理等の処理を行うものである。 The signal processing unit 37 performs processing such as interpolation processing of image signals.
　インターフェイス部３８は、外部の装置との間のやり取りを行うものである。同図のインターフェイス部３８は、アプリケーションプロセッサとの間のやり取りを行う。 The interface unit 38 exchanges with external devices. An interface unit 38 shown in the figure exchanges data with the application processor.
　［画像信号の生成］
　図５は、本開示の第１の実施形態に係る画像信号の生成の一例を示す図である。同図は、画素ブロック１００における第１の画像信号及び加算画像信号の生成の一例を表すタイミング図である。 [Image signal generation]
FIG. 5 is a diagram illustrating an example of image signal generation according to the first embodiment of the present disclosure. This figure is a timing chart showing an example of generation of the first image signal and the added image signal in the pixel block 100. As shown in FIG.
　同図の「ＳＥＬ」、「ＲＳＴ」、「ＴＧ１」、「ＴＧ２」、「ＴＧ３」及び「ＴＧ４」は、画素ブロック１００における信号線ＳＥＬ、信号線ＲＳＴ、信号線ＴＧ１、信号線ＴＧ２、信号線ＴＧ３及びＴＧ４の信号を表す。「ＲＥＦ」は、図４において説明した参照信号生成部３２から出力される参照信号の波形を表す。「ＡＤＣ」は、アナログデジタル変換部３１の出力を表す。 ``SEL'', ``RST'', ``TG1'', ``TG2'', ``TG3'' and ``TG4'' in FIG. TG3 and TG4 signals are represented. "REF" represents the waveform of the reference signal output from the reference signal generator 32 described with reference to FIG. “ADC” represents the output of the analog-to-digital converter 31 .
　「ＳＥＬ」、「ＲＳＴ」、「ＴＧ１」、「ＴＧ２」、「ＴＧ３」及び「ＴＧ４」の信号は、２値化された波形の値「１」の部分がオン電圧（Ｖｏｎ）を表す。また、値「０」の部分がオフ電圧を表す。同図の破線は、オフ電圧のレベルを表す。なお、同図の点線は、電荷保持部１０６の電位を表す。 In the signals "SEL", "RST", "TG1", "TG2", "TG3" and "TG4", the value "1" portion of the binarized waveform represents the ON voltage (Von). Also, the value "0" represents the off-voltage. The dashed line in the figure represents the level of the off-voltage. Note that the dotted line in the drawing represents the potential of the charge holding portion 106 .
　初期状態において、信号線ＳＥＬ及び信号線ＴＧ１、信号線ＴＧ２、信号線ＴＧ３及びＴＧ４には、オフ電圧が入力される。また、信号線ＲＳＴには、オン電圧が入力される。リセットトランジスタ１０４が導通状態になるため、電荷保持部１０６がリセットされる。また、Ｔ１までの期間において露光が行われる。なお、露光は、リセットトランジスタ１０４とともに電荷転送部１０２ａ等を導通させることにより開始することができる。 In the initial state, an off voltage is input to the signal line SEL, the signal line TG1, the signal line TG2, the signal lines TG3 and TG4. An ON voltage is input to the signal line RST. Since the reset transistor 104 becomes conductive, the charge holding unit 106 is reset. Further, exposure is performed during the period up to T1. Note that exposure can be started by turning on the reset transistor 104 and the charge transfer section 102a.
　Ｔ１において、リセット信号線ＲＳＴのオン電圧の入力が停止される。これにより、電荷保持部１０６のリセットが停止される。 At T1, the input of the ON voltage to the reset signal line RST is stopped. This stops resetting of the charge holding unit 106 .
　Ｔ２において、信号線ＳＥＬからオン電圧が入力される。これにより、画素ブロック１００が選択される。 At T2, an ON voltage is input from the signal line SEL. Thereby, the pixel block 100 is selected.
　Ｔ３からＴ４の期間において、参照信号生成部３２がランプ関数状の参照信号を出力し、アナログデジタル変換部３１がアナログデジタル変換を行う。同図の「ａ」は、変換結果を表す。これは、リセット時のデジタルの画像信号に該当する。このリセット時の画像信号は、保持部３３に保持される。 During the period from T3 to T4, the reference signal generator 32 outputs a ramp function reference signal, and the analog-to-digital converter 31 performs analog-to-digital conversion. "a" in the figure represents the conversion result. This corresponds to a digital image signal at reset. The image signal at this reset is held in the holding unit 33 .
　Ｔ５において、信号線ＴＧ１及びＴＧ３からオン電圧が入力され、電荷転送部１０２ａ及び１０２ｃが導通状態になる。これにより、光電変換部１０１ａ及び１０１ｃに蓄積された電荷が電荷保持部１０６に転送される。 At T5, an ON voltage is input from the signal lines TG1 and TG3, and the charge transfer portions 102a and 102c become conductive. Thereby, the charges accumulated in the photoelectric conversion units 101 a and 101 c are transferred to the charge holding unit 106 .
　Ｔ６において、信号線ＴＧ１及びＴＧ３からのオン電圧の入力が停止され、電荷転送部１０２ａ及び１０２ｃが非導通の状態になる。 At T6, the input of the ON voltage from the signal lines TG1 and TG3 is stopped, and the charge transfer sections 102a and 102c are brought into a non-conducting state.
　Ｔ７からＴ８の期間において、参照信号生成部３２が参照信号を出力し、アナログデジタル変換部３１がアナログデジタル変換を行う。同図の「ｂ」は、変換結果を表す。これは、デジタルの第１の画像信号に該当する。このデジタルの第１の画像信号からリセット時のデジタルの画像信号を減算することにより、ＣＤＳを行うことができる。 During the period from T7 to T8, the reference signal generator 32 outputs the reference signal, and the analog-to-digital converter 31 performs analog-to-digital conversion. "b" in the figure represents the conversion result. This corresponds to the digital first image signal. CDS can be performed by subtracting the digital image signal at the time of reset from this digital first image signal.
　Ｔ９において、信号線ＴＧ２及びＴＧ４からオン電圧が入力され、電荷転送部１０２ｂ及び１０２ｄが導通状態になる。これにより、光電変換部１０１ｂ及び１０１ｄに蓄積された電荷が電荷保持部１０６に転送される。 At T9, an ON voltage is input from the signal lines TG2 and TG4, and the charge transfer portions 102b and 102d become conductive. Thereby, the charges accumulated in the photoelectric conversion units 101b and 101d are transferred to the charge holding unit 106. FIG.
　Ｔ１０において、信号線ＴＧ２及びＴＧ４からのオン電圧の入力が停止され、電荷転送部１０２ｂ及び１０２ｄが非導通の状態になる。 At T10, the input of the ON voltage from the signal lines TG2 and TG4 is stopped, and the charge transfer sections 102b and 102d are brought into a non-conducting state.
　Ｔ１１からＴ１２の期間において、参照信号生成部３２が参照信号を出力し、アナログデジタル変換部３１がアナログデジタル変換を行う。同図の「ｃ」は、変換結果を表す。これは、デジタルの加算画像信号に該当する。このデジタルの加算画像信号からリセット時のデジタルの画像信号を減算することにより、ＣＤＳを行うことができる。 During the period from T11 to T12, the reference signal generator 32 outputs the reference signal, and the analog-to-digital converter 31 performs analog-to-digital conversion. "c" in the figure represents the conversion result. This corresponds to a digital added image signal. CDS can be performed by subtracting the digital image signal at the time of reset from this digital added image signal.
　Ｔ１３において、信号線ＳＥＬのオン電圧の印加が停止され、画素ブロック１００が非選択の状態になる。また、信号線ＲＳＴからオン電圧が印加されリセットトランジスタ１０４が導通状態になる。これにより、初期状態に戻る。 At T13, application of the ON voltage to the signal line SEL is stopped, and the pixel block 100 is put into a non-selected state. Also, an on-voltage is applied from the signal line RST, and the reset transistor 104 becomes conductive. This returns to the initial state.
　以上の手順により画素ブロック１００において第１の画像信号及び加算画像信号を生成することができる。 The first image signal and the added image signal can be generated in the pixel block 100 by the above procedure.
　このように、本開示の第１の実施形態の撮像素子１は、第１の画素の電荷に第２の画素の電荷を加算した加算画像信号を生成する。これにより、信号レベルを高くすることができ、信号対ノイズ比を向上させることができる。 Thus, the imaging device 1 of the first embodiment of the present disclosure generates an added image signal by adding the charge of the second pixel to the charge of the first pixel. This allows a higher signal level and an improved signal-to-noise ratio.
　（２．第２の実施形態）
　上述の第１の実施形態の撮像素子１は、第１の画像信号及び加算画像信号を出力していた。これに対し、本開示の第２の実施形態の撮像素子１は、加算画像信号のビット幅を第１の画像信号に揃えて出力する点で、上述の第１の実施形態と異なる。 (2. Second embodiment)
The imaging device 1 of the first embodiment described above outputs the first image signal and the added image signal. On the other hand, the imaging device 1 of the second embodiment of the present disclosure differs from the above-described first embodiment in that the bit width of the added image signal is aligned with that of the first image signal and output.
　［画像信号］
　図６は、本開示の第２の実施形態に係る画像信号の一例を示す図である。同図は、本開示の第２の実施形態に係る画像信号を説明する図である。同図の左端の図は、画素ブロック１００の配列を表したものである。この画素ブロック１００から第１の画像信号及び加算画像信号が生成される。 [Image signal]
FIG. 6 is a diagram illustrating an example of an image signal according to the second embodiment of the present disclosure; The same figure is a figure explaining the image signal based on 2nd Embodiment of this indication. The drawing on the left end of the figure shows the arrangement of the pixel blocks 100 . A first image signal and an added image signal are generated from this pixel block 100 .
　生成された第１の画像信号及び加算画像信号がアナログデジタル変換されて、デジタルの第１の画像信号及びデジタルの加算画像信号となる。同図の中央の図は、デジタルの第１の画像信号３０１及びデジタルの加算画像信号３０２の配列を表したものである。同図に表したように、デジタルの第１の画像信号３０１は１０ビット幅の信号となり、デジタルの加算画像信号３０２は１１ビット幅の信号となる。 The generated first image signal and added image signal are analog-to-digital converted into a digital first image signal and a digital added image signal. The diagram in the middle of the figure shows the arrangement of the digital first image signal 301 and the digital added image signal 302 . As shown in the figure, the digital first image signal 301 is a 10-bit width signal, and the digital addition image signal 302 is an 11-bit width signal.
　これらデジタルの第１の画像信号３０１及びデジタルの加算画像信号３０２に対して信号処理が行われる。同図の右端の図は、信号処理後の画像信号を表したものである。上段は、第１のモードにおける出力信号を表したものである。第１のモードにおいては、１０ビット幅の第１の画像信号３０１及び１０ビット幅に変換された加算画像信号３０３が出力される。下段は、第２のモードにおける出力信号を表したものである。第２のモードにおいは、１０ビット幅の第１の画像信号３０１及び１０ビット幅の第２の画像信号が出力される。 Signal processing is performed on these digital first image signal 301 and digital added image signal 302 . The diagram on the right end of the figure represents the image signal after the signal processing. The upper row represents the output signal in the first mode. In the first mode, a 10-bit width first image signal 301 and a 10-bit width added image signal 303 are output. The bottom row represents the output signal in the second mode. In the second mode, a 10-bit wide first image signal 301 and a 10-bit wide second image signal are output.
　［加算画像信号の生成］
　図７は、本開示の第２の実施形態に係る加算画像信号生成の一例を示す図である。同図は、１１ビット幅の加算画像信号３０２のビット幅を１０ビットに変換する手順を説明する図である。 [Generation of addition image signal]
FIG. 7 is a diagram illustrating an example of addition image signal generation according to the second embodiment of the present disclosure. This figure is a diagram for explaining the procedure for converting the bit width of the added image signal 302 of 11-bit width into 10-bit width.
　同図の（１）は、１１ビット幅の加算画像信号３０２の最上位ビットを削減することにより１０ビット幅に変換する例を表したものである。最下位ビットの信号が保持されるため、暗部の画質を優先させる場合にこの方式を適用すると好適である。 (1) in the figure shows an example of converting the added image signal 302 of 11-bit width to 10-bit width by removing the most significant bit. Since the signal of the least significant bit is held, it is preferable to apply this method when priority is given to the image quality of dark areas.
　また、同図の（２）は、１１ビット幅の加算画像信号３０２の最下位ビットを削減することにより１０ビット幅に変換する例を表したものである。最上位ビットの信号が保持されるため、明部の画質を優先させる場合にこの方式を適用すると好適である。 In addition, (2) in the figure shows an example of converting the added image signal 302 of 11-bit width to 10-bit width by removing the least significant bit. Since the signal of the most significant bit is held, this method is preferably applied when giving priority to the image quality of the bright portion.
　このように、出力する画像信号のビット幅を揃えることにより、後段の装置における信号の取り扱いを簡便なものとすることができる。なお、第２のモードを選択して１０ビット幅の第１の画像信号及び第２の画像信号を外部の装置に伝送し、伝送後に第１の画像信号及び第２の画像信号を加算して加算画像信号を生成することにより、加算画像信号の信号の欠落を無防ぐことができる。 In this way, by aligning the bit widths of the output image signals, it is possible to simplify the handling of the signals in the subsequent devices. In addition, the second mode is selected to transmit the first image signal and the second image signal of 10-bit width to an external device, and after the transmission, the first image signal and the second image signal are added, By generating the added image signal, it is possible to prevent the lack of the added image signal.
　これ以外の撮像素子１の構成は本開示の第１の実施形態における撮像素子１の構成と同様であるため、説明を省略する。 Since the configuration of the imaging device 1 other than this is the same as the configuration of the imaging device 1 in the first embodiment of the present disclosure, the description is omitted.
　このように、本開示の第２の実施形態の撮像素子１は、加算画像信号のビット幅を調整することにより、第１の画像信号及び加算画像信号のビット幅を揃えることができる。これにより、後段の装置における信号の取り扱いを簡便なものとすることができる。 In this way, the image sensor 1 according to the second embodiment of the present disclosure can match the bit widths of the first image signal and the added image signal by adjusting the bit width of the added image signal. As a result, it is possible to simplify the handling of signals in subsequent devices.
　（３．第３の実施形態）
　上述の第１の実施形態の撮像素子１は、同じ波長の入射光に対応する画素の電荷を加算していた。これに対し、本開示の第３の実施形態の撮像素子１は、異なる波長の入射光に対応する画素の電荷を加算する点で、上述の第１の実施形態と異なる。 (3. Third Embodiment)
The image sensor 1 of the first embodiment described above adds charges of pixels corresponding to incident light of the same wavelength. On the other hand, the imaging device 1 of the third embodiment of the present disclosure differs from the above-described first embodiment in that charges of pixels corresponding to incident light of different wavelengths are added.
　［画像ブロックの構成］
　図８は、本開示の第３の実施形態に係る画像ブロックの構成例を示す図である。同図は、画素ブロック１００の構成例を表す図である。 [Configuration of image block]
FIG. 8 is a diagram showing a configuration example of an image block according to the third embodiment of the present disclosure. This figure is a diagram showing a configuration example of the pixel block 100 .
　同図の画素ブロック１００は、赤色光に対応する画素１１０、緑色光に対応する画素１１０、青色光に対応する画素１１０及び白色光に対応する画素１１０の他に、黄色光に対応する画素１１０、赤紫色光に対応する画素１１０及び青緑色光に対応する画素１１０が更に配置される例を表したものである。同図の「Ｙ」、「Ｍ」及び「Ｃ」は、それぞれ黄色光、赤紫色光及び青緑色光に対応する画像信号を表す。 The pixel block 100 shown in FIG. , a pixel 110 corresponding to red-violet light and a pixel 110 corresponding to blue-green light are further arranged. "Y", "M" and "C" in the figure represent image signals corresponding to yellow light, red-violet light and blue-green light, respectively.
　同図の左上の画素ブロック１００においては、画素１１０ａはＲ画像信号を生成し、画素１１０ｃはＭ画像信号を生成し、画素１１０ｂ及び画素１１０ｄはＷ画像信号を生成する。また、右上の画素ブロック１００においては、画素１１０ａはＧ画像信号を生成し、画素１１０ｃはＹ画像信号を生成し、画素１１０ｂ及び画素１１０ｄはＷ画像信号を生成する。また、左下の画素ブロック１００においては、画素１１０ａはＧ画像信号を生成し、画素１１０ｃはＹ画像信号を生成し、画素１１０ｂ及び画素１１０ｄはＷ画像信号を生成する。右下の画素ブロック１００においては、画素１１０ａはＢ画像信号を生成し、画素１１０ｃはＣ画像信号を生成し、画素１１０ｂ及び画素１１０ｄはＷ画像信号を生成する。このような４つの画素ブロック１００が画素アレイ部１０に配列される。 In the pixel block 100 on the upper left of the figure, the pixel 110a generates the R image signal, the pixel 110c generates the M image signal, and the pixels 110b and 110d generate the W image signal. In the upper right pixel block 100, the pixel 110a generates a G image signal, the pixel 110c generates a Y image signal, and the pixels 110b and 110d generate a W image signal. In the lower left pixel block 100, the pixel 110a generates a G image signal, the pixel 110c generates a Y image signal, and the pixels 110b and 110d generate a W image signal. In the lower right pixel block 100, pixel 110a produces the B image signal, pixel 110c produces the C image signal, and pixels 110b and 110d produce the W image signal. Such four pixel blocks 100 are arranged in the pixel array section 10 .
　［画素ブロックの電荷の転送］
　図９は、本開示の第３の実施形態に係る画素ブロックの電荷の転送の一例を示す図である。同図は、リセット後の画素ブロック１００の画素１１０の電荷の転送を説明する図である。同図の左上の画素ブロック１００を例に挙げて説明する。まず、画素１１０ａの電荷が電荷保持部１０６に転送される。この際、画像信号が生成される。次に、画素１１０ｃの電荷が電荷保持部１０６転送されて加算される。この際、画像信号が生成される。次に、画素１１０ｂ及び画素１１０ｄの電荷が転送されて加算される。この際、画像信号が生成される。このように、同図の画素ブロック１００は、３つの画像信号を生成する。 [Transfer of charge in pixel block]
FIG. 9 is a diagram illustrating an example of charge transfer in a pixel block according to the third embodiment of the present disclosure. This figure is a diagram for explaining the charge transfer of the pixels 110 of the pixel block 100 after reset. The pixel block 100 on the upper left of the figure will be described as an example. First, the charge of the pixel 110 a is transferred to the charge holding portion 106 . At this time, an image signal is generated. Next, the charge of the pixel 110c is transferred to the charge holding unit 106 and added. At this time, an image signal is generated. The charges of pixel 110b and pixel 110d are then transferred and summed. At this time, an image signal is generated. Thus, the pixel block 100 of FIG. 1 generates three image signals.
　［画像信号の生成］
　図１０は、本開示の第３の実施形態に係る画像信号の生成の一例を示す図である。同図は、図５と同様に画素ブロック１００における第１の画像信号及び加算画像信号の生成の一例を表すタイミング図である。Ｔ２０までの処理は図５と同様の処理を適用することができる。 [Image signal generation]
FIG. 10 is a diagram illustrating an example of image signal generation according to the third embodiment of the present disclosure. This figure is a timing chart showing an example of generation of the first image signal and the addition image signal in the pixel block 100, similar to FIG. The same processing as in FIG. 5 can be applied to the processing up to T20.
　Ｔ２０において、信号線ＴＧ１からオン電圧が入力され、電荷転送部１０２ａが導通状態になる。これにより、光電変換部１０１ａに蓄積された電荷が電荷保持部１０６に転送される。 At T20, an ON voltage is input from the signal line TG1, and the charge transfer section 102a becomes conductive. Thereby, the charge accumulated in the photoelectric conversion unit 101 a is transferred to the charge holding unit 106 .
　Ｔ２１において、信号線ＴＧ１からのオン電圧の入力が停止され、電荷転送部１０２ａが非導通の状態になる。 At T21, the input of the ON voltage from the signal line TG1 is stopped, and the charge transfer section 102a becomes non-conductive.
　Ｔ２２からＴ２３の期間において、参照信号生成部３２が参照信号を出力し、アナログデジタル変換部３１がアナログデジタル変換を行う。同図の「ｄ」は、変換結果の画像信号を表す。 During the period from T22 to T23, the reference signal generator 32 outputs the reference signal, and the analog-to-digital converter 31 performs analog-to-digital conversion. "d" in the figure represents the image signal of the conversion result.
　Ｔ２４において、信号線ＴＧ３からオン電圧が入力され、電荷転送部１０２ｃが導通状態になる。これにより、光電変換部１０１ｃに蓄積された電荷が電荷保持部１０６に転送される。 At T24, an ON voltage is input from the signal line TG3, and the charge transfer section 102c becomes conductive. Thereby, the charge accumulated in the photoelectric conversion unit 101c is transferred to the charge holding unit 106. FIG.
　Ｔ２５において、信号線ＴＧ３からのオン電圧の入力が停止され、電荷転送部１０２ｃが非導通の状態になる。 At T25, the input of the ON voltage from the signal line TG3 is stopped, and the charge transfer section 102c becomes non-conductive.
　Ｔ２６からＴ２７の期間において、参照信号生成部３２が参照信号を出力し、アナログデジタル変換部３１がアナログデジタル変換を行う。同図の「ｅ」は、変換結果の画像信号を表す。 During the period from T26 to T27, the reference signal generator 32 outputs the reference signal, and the analog-to-digital converter 31 performs analog-to-digital conversion. "e" in the figure represents the image signal of the conversion result.
　Ｔ２８において、信号線ＴＧ２及びＴＧ４からオン電圧が入力され、電荷転送部１０２ｂ及び１０２ｄが導通状態になる。これにより、光電変換部１０１ｂ及び１０１ｄに蓄積された電荷が電荷保持部１０６に転送される。 At T28, an ON voltage is input from the signal lines TG2 and TG4, and the charge transfer sections 102b and 102d are brought into a conductive state. Thereby, the charges accumulated in the photoelectric conversion units 101b and 101d are transferred to the charge holding unit 106. FIG.
　Ｔ２９において、信号線ＴＧ２及びＴＧ４からのオン電圧の入力が停止され、電荷転送部１０２ｂ及び１０２ｄが非導通の状態になる。 At T29, the input of the ON voltage from the signal lines TG2 and TG4 is stopped, and the charge transfer sections 102b and 102d are rendered non-conductive.
　Ｔ３０からＴ３１の期間において、参照信号生成部３２が参照信号を出力し、アナログデジタル変換部３１がアナログデジタル変換を行う。同図の「ｆ」は、変換結果の画像信号を表す。 During the period from T30 to T31, the reference signal generator 32 outputs the reference signal, and the analog-to-digital converter 31 performs analog-to-digital conversion. "f" in the figure represents the image signal of the conversion result.
　これ以外の撮像素子１の構成は本開示の第１の実施形態における撮像素子１の構成と同様であるため、説明を省略する。 Since the configuration of the imaging device 1 other than this is the same as the configuration of the imaging device 1 in the first embodiment of the present disclosure, the description is omitted.
　このように、本開示の第３の実施形態の撮像素子１は、異なる波長の入射光に対応する画像信号を生成する画素１１０の電荷を加算した画像信号を生成する。 In this way, the imaging device 1 of the third embodiment of the present disclosure generates image signals by adding the charges of the pixels 110 that generate image signals corresponding to incident light of different wavelengths.
　（４．第４の実施形態）
　上述の第１の実施形態の撮像素子１は、第１の画像信号及び加算画像信号を生成していた。これに対し、本開示の第４の実施形態の撮像素子１は、像面位相差を検出する位相差信号を更に生成する点で、上述の第１の実施形態と異なる。 (4. Fourth Embodiment)
The imaging device 1 of the first embodiment described above generates the first image signal and the added image signal. On the other hand, the imaging device 1 of the fourth embodiment of the present disclosure differs from the above-described first embodiment in that it further generates a phase difference signal for detecting the image plane phase difference.
　［画素ブロックの構成］
　図１１は、本開示の第４の実施形態に係る画素ブロックの構成例を示す図である。同図は、図２と同様に、画素ブロック１００の構成例を表す回路図である。なお、同図の画素ブロック１００は、画素１１０ａ及び１１０ｃが複数の光電変換部１０１及び複数の電荷転送部１０２をそれぞれ備える点で、図２の画素ブロック１００と異なる。 [Configuration of pixel block]
FIG. 11 is a diagram illustrating a configuration example of a pixel block according to the fourth embodiment of the present disclosure; This figure, like FIG. 2, is a circuit diagram showing a configuration example of the pixel block 100. As shown in FIG. The pixel block 100 in FIG. 2 differs from the pixel block 100 in FIG. 2 in that pixels 110a and 110c each include a plurality of photoelectric conversion units 101 and a plurality of charge transfer units 102. FIG.
　画素１１０ａは、光電変換部１０１ｅ及び１０１ｆと、電荷転送部１０２ｅ及び１０２ｆを備える。画素１１０ｃは、光電変換部１０１ｇ及び１０１ｈと、電荷転送部１０２ｇ及び１０２ｈを備える。 The pixel 110a includes photoelectric conversion units 101e and 101f and charge transfer units 102e and 102f. The pixel 110c includes photoelectric conversion units 101g and 101h and charge transfer units 102g and 102h.
　光電変換部１０１ｅのアノードは接地され、カソードは電荷転送部１０２ｅのソースに接続される。光電変換部１０１ｆのアノードは接地され、カソードは電荷転送部１０２ｆのソースに接続される。光電変換部１０１ｇのアノードは接地され、カソードは電荷転送部１０２ｇのソースに接続される。光電変換部１０１ｈのアノードは接地され、カソードは電荷転送部１０２ｈのソースに接続される。 The anode of the photoelectric conversion unit 101e is grounded, and the cathode is connected to the source of the charge transfer unit 102e. The photoelectric conversion unit 101f has an anode grounded and a cathode connected to the source of the charge transfer unit 102f. The photoelectric conversion section 101g has an anode grounded and a cathode connected to the source of the charge transfer section 102g. The photoelectric conversion unit 101h has an anode grounded and a cathode connected to the source of the charge transfer unit 102h.
　電荷転送部１０２ｅ、１０２ｆ、１０２ｇ及び１０２ｈのドレインは、電荷保持部１０６の一端に接続される。電荷転送部１０２ｅ、１０２ｆ、１０２ｇ及び１０２ｈのゲートは信号線ＴＧ１１、ＴＧ１２、ＴＧ３１及びＴＧ３２にそれぞれ接続される。 The drains of the charge transfer units 102e, 102f, 102g and 102h are connected to one end of the charge holding unit 106. Gates of the charge transfer units 102e, 102f, 102g and 102h are connected to signal lines TG11, TG12, TG31 and TG32, respectively.
　光電変換部１０１ｅ及び１０１ｆは、被写体を瞳分割する光電変換部である。また、光電変換部１０１ｇ及び１０１ｈも同様に被写体を瞳分割する光電変換部である。 The photoelectric conversion units 101e and 101f are photoelectric conversion units that pupil-divide the subject. Similarly, the photoelectric conversion units 101g and 101h are photoelectric conversion units that pupil-divide the subject.
　［画素ブロックの平面の構成］
　図１２は、本開示の第４の実施形態に係る画素ブロックの構成例を示す図である。同図は、画素ブロック１００の構成例を表す平面図である。同図に表したように、画素１１０ａは光電変換部１０１ｅ及び１０１ｆにより瞳分割される。また、画素１１０ｃも同様に、光電変換部１０１ｇ及び１０１ｈにより瞳分割される。これら瞳分割された画素１１０により位相差信号を生成することができる。 [Structure of Plane of Pixel Block]
FIG. 12 is a diagram illustrating a configuration example of a pixel block according to the fourth embodiment of the present disclosure; This figure is a plan view showing a configuration example of the pixel block 100 . As shown in the figure, the pixel 110a is pupil-divided by the photoelectric conversion units 101e and 101f. Similarly, the pixel 110c is pupil-divided by the photoelectric conversion units 101g and 101h. A phase difference signal can be generated by these pupil-divided pixels 110 .
　［画素ブロックの電荷の転送］
　図１３は、本開示の第４の実施形態に係る画素ブロックの電荷の転送の一例を示す図である。同図は、図９と同様に、リセット後の画素ブロック１００の画素１１０の電荷の転送を説明する図である。同図の左上の画素ブロック１００を例に挙げて説明する。まず、画素１１０ａの光電変換部１０１ｅの電荷が電荷保持部１０６に転送される。この際、画像信号が生成される。次に、画素１１０ａの光電変換部１０１ｆの電荷が電荷保持部１０６転送されて加算される。この際、画像信号が生成される。次に、画素１１０ｂ及び画素１１０ｄの電荷が転送されて加算される。この際、画像信号が生成される。このように、同図の画素ブロック１００は、位相差信号を含む３つの画像信号を生成する。 [Transfer of charge in pixel block]
FIG. 13 is a diagram illustrating an example of charge transfer in a pixel block according to the fourth embodiment of the present disclosure. Similar to FIG. 9, this figure is a diagram for explaining the charge transfer of the pixels 110 of the pixel block 100 after reset. The pixel block 100 on the upper left of the figure will be described as an example. First, the charge of the photoelectric conversion portion 101e of the pixel 110a is transferred to the charge holding portion . At this time, an image signal is generated. Next, the charge of the photoelectric conversion unit 101f of the pixel 110a is transferred to the charge holding unit 106 and added. At this time, an image signal is generated. The charges of pixel 110b and pixel 110d are then transferred and summed. At this time, an image signal is generated. Thus, the pixel block 100 in the figure produces three image signals including phase difference signals.
　［画像信号の生成］
　図１４は、本開示の第４の実施形態に係る画像信号の生成の一例を示す図である。同図は、図１０と同様に画素ブロック１００における第１の画像信号及び加算画像信号の生成の一例を表すタイミング図である。Ｔ２０乃至Ｔ２１の期間においてＴＧ１１及びＴＧ３１にオン電圧を入力し、Ｔ２４乃至Ｔ２５の期間においてＴＧ１２及びＴＧ３２にオン電圧を入力する以外は図１１と同様の処理手順を適用することができる。なお、同図の「ｄ」の画像信号及び「ｅ」の画像信号から位相信号を生成することができる。 [Image signal generation]
FIG. 14 is a diagram illustrating an example of image signal generation according to the fourth embodiment of the present disclosure. This figure is a timing chart showing an example of generation of the first image signal and the addition image signal in the pixel block 100, similar to FIG. A procedure similar to that of FIG. 11 can be applied except that the ON voltage is input to TG11 and TG31 during the period from T20 to T21, and the ON voltage is input to TG12 and TG32 during the period from T24 to T25. A phase signal can be generated from the image signal of "d" and the image signal of "e" in the figure.
　これ以外の撮像素子１の構成は本開示の第１の実施形態における撮像素子１の構成と同様であるため、説明を省略する。 Since the configuration of the imaging device 1 other than this is the same as the configuration of the imaging device 1 in the first embodiment of the present disclosure, the description is omitted.
　このように、本開示の第４の実施形態の撮像素子１は、画素ブロック１００において位相差信号を生成することができる。 In this way, the image sensor 1 of the fourth embodiment of the present disclosure can generate phase difference signals in the pixel block 100 .
　（５．第５の実施形態）
　上述の第１の実施形態の撮像素子１は、１度のアナログデジタル変換によりデジタルの第１の画像信号及びデジタルの加算画像信号を生成していた。これに対し、本開示の第５の実施形態の撮像素子１は、複数のアナログデジタル変換を行って画像信号を生成する点で、上述の第１の実施形態と異なる。 (5. Fifth embodiment)
The imaging device 1 of the first embodiment described above generates a digital first image signal and a digital added image signal by one analog-to-digital conversion. In contrast, the imaging device 1 of the fifth embodiment of the present disclosure differs from the above-described first embodiment in that image signals are generated by performing multiple analog-to-digital conversions.
　［画像信号の生成］
　図１５は、本開示の第５の実施形態に係る画像信号の生成の一例を示す図である。同図は、図５と同様に、画素ブロック１００における第１の画像信号及び加算画像信号の生成の一例を表すタイミング図である。Ｔ４０乃至Ｔ４１の処理手順が追加される点で、図５の処理手順と異なる。同図の処理手順では、Ｔ７乃至Ｔ８の期間の「ｂ」の画像信号の生成の後に同様の手順のＴ４０乃至Ｔ４１の処理を行って「ｂ」の画像信号を再度生成する。 [Image signal generation]
FIG. 15 is a diagram illustrating an example of image signal generation according to the fifth embodiment of the present disclosure. Similar to FIG. 5, this figure is a timing chart showing an example of generation of the first image signal and the added image signal in the pixel block 100. In FIG. It differs from the processing procedure in FIG. 5 in that processing procedures from T40 to T41 are added. In the processing procedure shown in the figure, after the generation of the image signal "b" in the period T7 to T8, the same processing of T40 to T41 is performed to generate the image signal "b" again.
　その後、２つの「ｂ」の画像信号の平均を算出して第１の画像信号を生成する。２つの画像信号のノイズが平準化されるため、第１の画像信号のノイズを低減することができる。 After that, the average of the two "b" image signals is calculated to generate the first image signal. Since the noise of the two image signals is leveled, the noise of the first image signal can be reduced.
　図１６は、本開示の第５の実施形態に係る画像信号の生成の他の例を示す図である。同図は、図５と同様に、画素ブロック１００における第１の画像信号及び加算画像信号の生成の一例を表すタイミング図である。Ｔ４５乃至Ｔ４６の処理手順が追加される点で、図５の処理手順と異なる。同図の処理手順では、Ｔ１１乃至Ｔ１２の期間の「ｃ」の画像信号の生成の後に同様の手順のＴ４５乃至Ｔ４６の処理を行って「ｃ」の画像信号を再度生成する。 FIG. 16 is a diagram showing another example of image signal generation according to the fifth embodiment of the present disclosure. Similar to FIG. 5, this figure is a timing chart showing an example of generation of the first image signal and the added image signal in the pixel block 100. In FIG. It differs from the processing procedure in FIG. 5 in that processing procedures from T45 to T46 are added. In the processing procedure shown in the figure, after generating the image signal of "c" in the period of T11 to T12, the processing of T45 to T46 in the same procedure is performed to generate the image signal of "c" again.
　その後、２つの「ｃ」の画像信号の平均を算出して加算画像信号を生成する。２つの画像信号のノイズが平準化されるため、加算画像信号のノイズを低減することができる。 After that, the average of the two "c" image signals is calculated to generate an added image signal. Since the noise of the two image signals is leveled, the noise of the added image signal can be reduced.
　これ以外の撮像素子１の構成は本開示の第１の実施形態における撮像素子１の構成と同様であるため、説明を省略する。 Since the configuration of the imaging device 1 other than this is the same as the configuration of the imaging device 1 in the first embodiment of the present disclosure, the description is omitted.
　このように、本開示の第５の実施形態の撮像素子１は、アナログデジタル変換を複数回行って生成したデジタルの画像信号の平均を算出することにより、ノイズを低減することができる。 In this way, the image sensor 1 of the fifth embodiment of the present disclosure can reduce noise by calculating the average of digital image signals generated by performing analog-to-digital conversion multiple times.
　（６．第６の実施形態）
　画素ブロック１００のバリエーションについて説明する。 (6. Sixth Embodiment)
Variations of the pixel block 100 will be described.
　［画素ブロックの平面の構成］
　図１７Ａ－１７Ｃは、本開示の第６の実施形態に係る画素ブロックの構成例を示す図である。同図は、画素ブロック１００の構成例を表す平面図である。 [Structure of Plane of Pixel Block]
17A-17C are diagrams showing configuration examples of pixel blocks according to the sixth embodiment of the present disclosure. This figure is a plan view showing a configuration example of the pixel block 100 .
　図１７Ａは、図３の画素ブロック１００に対して画素１１０の配置を変更する例を表したものである。 FIG. 17A shows an example of changing the arrangement of pixels 110 with respect to the pixel block 100 of FIG.
　図１７Ｂは、図８の画素ブロック１００に対して画素１１０の配置を変更する例を表したものである。 FIG. 17B shows an example of changing the arrangement of the pixels 110 with respect to the pixel block 100 of FIG.
　図１７Ｃは、図３の画素ブロック１００のＷ画像信号を生成する画素１１０の代わりに赤外光に対応する画像信号を生成する画素１１０を配置する例を表したものである。同図の「ＩＲ」が付された画素１１０は、赤外光に対応する画像信号を生成する画素１１０を表す。 FIG. 17C shows an example in which pixels 110 that generate image signals corresponding to infrared light are arranged instead of the pixels 110 that generate W image signals in the pixel block 100 of FIG. Pixels 110 labeled with “IR” in the figure represent pixels 110 that generate image signals corresponding to infrared light.
　図１８Ａ及び１８Ｂは、本開示の第６の実施形態に係る画素ブロックの他の構成例を示す図である。同図は、画素ブロック１００の構成例を表す平面図である。画素１１０毎に露光時間を変更する例を表したものである。なお、同図の画素ブロック１００には、同色の画像信号を生成する画素１１０を配置することができる。 18A and 18B are diagrams showing other configuration examples of pixel blocks according to the sixth embodiment of the present disclosure. This figure is a plan view showing a configuration example of the pixel block 100 . An example of changing the exposure time for each pixel 110 is shown. Note that pixels 110 that generate image signals of the same color can be arranged in the pixel block 100 in FIG.
　図１８Ａにおいて、右上の斜線のハッチングが付された画素１１０は、比較的長い露光時間の画素１１０を表す。また、右下の斜線のハッチングが付された画素１１０は、比較的短い露光時間の画素１１０を表す。 In FIG. 18A, pixels 110 hatched with oblique lines in the upper right represent pixels 110 with relatively long exposure times. Also, the pixels 110 hatched with oblique lines in the lower right represent the pixels 110 with relatively short exposure times.
　図１８Ｂにおいて、網掛けのハッチングが付された画素１１０は、中位の露光時間の画素１１０を表す。 In FIG. 18B, the pixels 110 with mesh hatching represent the pixels 110 with medium exposure times.
　図１９は、本開示の第６の実施形態に係る画素ブロックの他の構成例を示す図である。同図は、図３と同様に、画素ブロック１００の構成例を表す平面図である。同図は、４行２列の８個の画素１１０が電荷保持部１０６及び信号生成部１２０を共有する画素ブロック１００の例を表したものである。 FIG. 19 is a diagram showing another configuration example of the pixel block according to the sixth embodiment of the present disclosure. This figure, like FIG. 3, is a plan view showing a configuration example of the pixel block 100. As shown in FIG. The figure shows an example of a pixel block 100 in which eight pixels 110 of 4 rows and 2 columns share the charge holding portion 106 and the signal generating portion 120 .
　図２０Ａ及び２０Ｂは、本開示の第６の実施形態に係る画素ブロックの他の構成例を示す図である。同図は、図３と同様に、画素ブロック１００の構成例を表す平面図である。　　　 20A and 20B are diagrams showing other configuration examples of pixel blocks according to the sixth embodiment of the present disclosure. This figure, like FIG. 3, is a plan view showing a configuration example of the pixel block 100. As shown in FIG.　　　
　図２０Ａは、３行３列の９個の画素１１０が電荷保持部１０６及び信号生成部１２０を共有する画素ブロック１００の例を表したものである。 FIG. 20A shows an example of a pixel block 100 in which 9 pixels 110 of 3 rows and 3 columns share the charge holding portion 106 and the signal generating portion 120. FIG.
　図２０Ｂは、４行４列の１６個の画素１１０が電荷保持部１０６及び信号生成部１２０を共有する画素ブロック１００の例を表したものである。 FIG. 20B shows an example of a pixel block 100 in which 16 pixels 110 arranged in 4 rows and 4 columns share the charge holding portion 106 and the signal generating portion 120 .
　（７．撮像装置）
　本開示に係る技術は、様々な製品へ応用することができる。例えば、本開示に係る技術は、カメラ等の撮像装置に適用することができる。 (7. Imaging device)
The technology according to the present disclosure can be applied to various products. For example, the technology according to the present disclosure can be applied to imaging devices such as cameras.
　図２１は、本開示に係る技術が適用され得る撮像装置の構成例を示す図である。同図の撮像装置１０００は、撮像素子１００１と、制御部１００２と、画像処理部１００３と、表示部１００４と、記録部１００５と、撮影レンズ１００６とを備える。 FIG. 21 is a diagram showing a configuration example of an imaging device to which the technology according to the present disclosure can be applied. An imaging apparatus 1000 shown in FIG.
　撮影レンズ１００６は、被写体からの光を集光するレンズである。この撮影レンズ１００６により、被写体が撮像素子１００１の受光面に結像される。 A photographing lens 1006 is a lens that collects light from a subject. The photographing lens 1006 forms an image of the subject on the light receiving surface of the image sensor 1001 .
　撮像素子１００１は、被写体の撮像を行う素子である。この撮像素子１００１の受光面には、被写体からの光の光電変換を行う光電変換部を有する複数の画素が配置される。これら複数の画素は、光電変換により生成された電荷に基づく画像信号をそれぞれ生成する。撮像素子１００１は、画素により生成された画像信号をデジタルの画像信号に変換して画像処理部１００３に対して出力する。なお、１画面分の画像信号はフレームと称される。撮像素子１００１は、フレーム単位で画像信号を出力することもできる。 An imaging device 1001 is a device that takes an image of a subject. A plurality of pixels each having a photoelectric conversion unit for performing photoelectric conversion of light from an object are arranged on the light receiving surface of the image sensor 1001 . These pixels each generate an image signal based on charges generated by photoelectric conversion. The image sensor 1001 converts image signals generated by pixels into digital image signals and outputs the digital image signals to the image processing unit 1003 . An image signal for one screen is called a frame. The imaging device 1001 can also output an image signal on a frame-by-frame basis.
　制御部１００２は、撮像素子１００１および画像処理部１００３を制御するものである。制御部１００２は、例えば、マイコン等を使用した電子回路により構成することができる。 The control unit 1002 controls the image pickup device 1001 and the image processing unit 1003 . The control unit 1002 can be configured by, for example, an electronic circuit using a microcomputer or the like.
　画像処理部１００３は、撮像素子１００１からの画像信号を処理するものである。画像処理部１００３における画像信号の処理には、例えば、カラーの画像を生成する際に不足する色の画像信号を生成するデモザイク処理や画像信号のノイズを除去するノイズリダクション処理が該当する。画像処理部１００３は、例えば、マイコン等を使用した電子回路により構成することができる。 The image processing unit 1003 processes the image signal from the imaging device 1001 . The image signal processing in the image processing unit 1003 corresponds to, for example, demosaic processing for generating image signals of insufficient colors when generating a color image, and noise reduction processing for removing noise from image signals. The image processing unit 1003 can be configured by, for example, an electronic circuit using a microcomputer or the like.
　表示部１００４は、画像処理部１００３により処理された画像信号に基づいて、画像を表示するものである。表示部１００４は、例えば、液晶モニタにより構成することができる。 The display unit 1004 displays an image based on the image signal processed by the image processing unit 1003 . The display unit 1004 can be configured by, for example, a liquid crystal monitor.
　記録部１００５は、画像処理部１００３により処理された画像信号に基づく画像（フレーム）を記録するものである。記録部１００５は、例えば、ハードディスクや半導体メモリにより構成することができる。 The recording unit 1005 records an image (frame) based on the image signal processed by the image processing unit 1003 . The recording unit 1005 can be composed of, for example, a hard disk or a semiconductor memory.
　以上、本開示が適用され得る撮像装置について説明した。本技術は上述の構成要素のうちの撮像素子１００１に適用することができる。具体的には、図１において説明した撮像素子１は、撮像素子１００１に適用することができる。なお、画像処理部１００３は、画像処理回路の一例である。 The imaging device to which the present disclosure can be applied has been described above. The present technology can be applied to the imaging device 1001 among the above components. Specifically, the image sensor 1 described with reference to FIG. 1 can be applied to the image sensor 1001 . Note that the image processing unit 1003 is an example of an image processing circuit.
　なお、本明細書に記載された効果はあくまで例示であって限定されるものでは無く、また他の効果があってもよい。 It should be noted that the effects described in this specification are merely examples and are not limited, and other effects may also occur.
　なお、本技術は以下のような構成も取ることができる。
（１）
　入射光のうちの所定の波長の入射光の光電変換を行って電荷を生成する第１の画素と、前記第１の画素とは異なる波長の入射光の光電変換を行って電荷を生成する第２の画素と、前記第１の画素及び前記第２の画素により生成される電荷を保持する電荷保持部と、前記電荷保持部に保持された電荷に基づいて画像信号を生成する信号生成部とを備える画素ブロックと、
　前記第１の画素により生成された電荷を前記電荷保持部に転送して当該電荷に基づく前記画像信号である第１の画像信号を前記信号生成部に生成させる制御と、前記第１の画素により生成された電荷が保持された前記電荷保持部に前記第２の画素により生成された電荷を更に転送して前記第１の画素及び前記第２の画素によりそれぞれ生成される電荷が加算された電荷に基づく前記画像信号である加算画像信号を前記信号生成部に生成させる制御とを行う画素ブロック制御部と、
　前記加算画像信号から前記第１の画像信号を減算した前記画像信号である第２の画像信号を生成する減算部を備え、前記第１の画像信号及び前記加算画像信号を出力する第１のモードと前記第１の画像信号及び前記第２の画像信号を出力する第２のモードとを切り替える信号処理部と
　を有する撮像素子。
（２）
　前記第１の画素は、前記入射光のうちの赤色光、緑色光及び青色光の何れかの光電変換を行う前記（１）に記載の撮像素子。
（３）
　前記第２の画素は、前記入射光のうちの白色光の光電変換を行う前記（１）に記載の撮像素子。
（４）
　前記第２の画素は、前記入射光のうちの黄色光、赤紫色光及び青緑色光の何れかの光電変換を行う前記（１）に記載の撮像素子。
（５）
　前記第２の画素は、前記入射光のうちの赤外光の光電変換を行う前記（１）に記載の撮像素子。
（６）
　前記画素ブロックは、複数の前記第１の画素及び複数の前記第２の画素が正方行列に配置されるとともに前記第１の画素及び前記第２の画素が行方向及び列方向に交互に配置されて構成される前記（１）から（５）の何れかに記載の撮像素子。
（７）
　前記電荷保持部の電荷を排出することによりリセットを行うリセット部を更に有し、
　前記画素ブロック制御部は、前記リセット部によるリセット時の画像信号である基準画像信号を生成させる制御を更に行い、
　前記信号処理部は、前記第１の画像信号から前記基準画像信号を減算することによる第１の画像信号の補正と、前記加算画像信号から前記基準画像信号を減算することによる加算画像信号の補正とを更に行う前記（１）から（６）の何れかに記載の撮像素子。
（８）
　前記第１の画素は、被写体を瞳分割するための複数の光電変換部を備え、
　前記画素ブロック制御部は、前記第１の画素の複数の光電変換部の何れかにより生成された電荷を前記電荷保持部に転送して当該電荷に基づく画像信号を前記信号生成部に生成させる制御を更に行い、前記第１の画素の複数の前記光電変換部により生成された電荷を前記電荷保持部に転送して当該電荷に基づく画像信号を前記第１の画像信号として前記信号生成部に生成させる
　前記（１）から（７）の何れかに記載の撮像素子。
（９）
　前記信号処理部は、前記第１の画像信号及び前記加算画像信号をデジタル信号に変換するアナログデジタル変換部を更に備え、
　前記信号処理部は、前記アナログデジタル変換部により変換されたデジタル信号の前記第１の画像信号及び前記加算画像信号を出力する
　前記（１）から（６）の何れかに記載の撮像素子。
（１０）
　前記信号処理部は、デジタル信号の前記第１の画像信号とビット幅を揃えたデジタル信号の前記加算画像信号を生成して出力する前記（９）に記載の撮像素子。
（１１）
　前記信号処理部は、アナログデジタル変換部により変換されたデジタル信号の前記加算画像信号の最上位ビットを削除することにより前記第１の画像信号とビット幅を揃える前記（１０）に記載の撮像素子。
（１２）
　前記信号処理部は、アナログデジタル変換部により変換されたデジタル信号の前記加算画像信号の最下位ビットを削除することにより前記第１の画像信号とビット幅を揃える前記（１０）に記載の撮像素子。
（１３）
　前記画素ブロック制御部は、前記第１の画像信号及び前記加算画像信号の少なくとも一方を複数生成し、
　前記アナログデジタル変換部は、複数の前記第１の画像信号又は複数の前記加算画像信号のデジタル信号に変換し、
　前記信号処理部は、複数のデジタル信号の前記第１の画像信号又は複数のデジタル信号の前記加算画像信号の平均を前記第１の画像信号又は前記加算画像信号として出力する
　前記（９）に記載の撮像素子。
（１４）
　入射光のうちの所定の波長の入射光の光電変換を行って電荷を生成する第１の画素と、前記第１の画素とは異なる波長の入射光の光電変換を行って電荷を生成する第２の画素と、前記第１の画素及び前記第２の画素により生成される電荷を保持する電荷保持部と、前記電荷保持部に保持された電荷に基づいて画像信号を生成する信号生成部とを備える画素ブロックと、
　前記第１の画素により生成された電荷を前記電荷保持部に転送して当該電荷に基づく前記画像信号である第１の画像信号を前記信号生成部に生成させる制御と、前記第１の画素により生成された電荷が保持された前記電荷保持部に前記第２の画素により生成された電荷を更に転送して前記第１の画素及び前記第２の画素によりそれぞれ生成される電荷が加算された電荷に基づく前記画像信号である加算画像信号を前記信号生成部に生成させる制御とを行う画素ブロック制御部と、
　前記加算画像信号から前記第１の画像信号を減算した前記画像信号である第２の画像信号を生成する減算部を備え、前記第１の画像信号及び前記加算画像信号を出力する第１のモードと前記第１の画像信号及び前記第２の画像信号を出力する第２のモードとを切り替える信号処理部と、
　前記第１の画像信号、前記加算画像信号及び前記第２の画像信号の少なくとも１つを処理する処理回路と
　を有する電子機器。 Note that the present technology can also take the following configuration.
(1)
A first pixel for generating charges by performing photoelectric conversion on incident light with a predetermined wavelength out of incident light, and a second pixel for generating charges by performing photoelectric conversion on incident light with a wavelength different from that of the first pixels. 2 pixels, a charge holding unit that holds charges generated by the first pixel and the second pixel, and a signal generation unit that generates an image signal based on the charges held in the charge holding unit. a pixel block comprising
a control for transferring the charge generated by the first pixel to the charge holding unit and causing the signal generation unit to generate a first image signal, which is the image signal based on the charge; The charge generated by the second pixel is further transferred to the charge holding portion holding the generated charge, and the charge generated by the first pixel and the charge generated by the second pixel are added together. a pixel block control unit that controls the signal generation unit to generate an added image signal that is the image signal based on
A first mode for outputting the first image signal and the added image signal, comprising a subtracting unit that generates a second image signal that is the image signal obtained by subtracting the first image signal from the added image signal. and a signal processing unit that switches between a second mode for outputting the first image signal and the second image signal.
(2)
The imaging device according to (1), wherein the first pixel photoelectrically converts any one of red light, green light, and blue light in the incident light.
(3)
The imaging device according to (1), wherein the second pixel photoelectrically converts white light in the incident light.
(4)
The imaging device according to (1), wherein the second pixel photoelectrically converts any one of yellow light, red-violet light, and blue-green light in the incident light.
(5)
The imaging device according to (1), wherein the second pixel photoelectrically converts infrared light in the incident light.
(6)
In the pixel block, a plurality of the first pixels and a plurality of the second pixels are arranged in a square matrix, and the first pixels and the second pixels are arranged alternately in a row direction and a column direction. The imaging device according to any one of (1) to (5) above, which is configured by:
(7)
further comprising a reset unit for resetting by discharging the charge in the charge holding unit;
The pixel block control unit further performs control to generate a reference image signal, which is an image signal at the time of reset by the reset unit,
The signal processing unit corrects the first image signal by subtracting the reference image signal from the first image signal, and corrects the addition image signal by subtracting the reference image signal from the addition image signal. The imaging device according to any one of (1) to (6), further comprising:
(8)
the first pixel includes a plurality of photoelectric conversion units for pupil-dividing the subject;
The pixel block control section transfers the charge generated by one of the plurality of photoelectric conversion sections of the first pixel to the charge holding section and controls the signal generation section to generate an image signal based on the charge. and transferring the charges generated by the plurality of photoelectric conversion units of the first pixel to the charge holding unit, and generating an image signal based on the charges as the first image signal in the signal generation unit. The imaging device according to any one of (1) to (7) above.
(9)
The signal processing unit further includes an analog-to-digital conversion unit that converts the first image signal and the added image signal into digital signals,
The imaging device according to any one of (1) to (6), wherein the signal processing section outputs the first image signal and the added image signal of digital signals converted by the analog-to-digital conversion section.
(10)
The imaging device according to (9), wherein the signal processing unit generates and outputs the added image signal of a digital signal having the same bit width as the first image signal of a digital signal.
(11)
The image pickup device according to (10), wherein the signal processing unit deletes the most significant bit of the added image signal of the digital signal converted by the analog-to-digital conversion unit to match the bit width of the first image signal. .
(12)
The image pickup device according to (10), wherein the signal processing unit deletes the least significant bit of the added image signal of the digital signal converted by the analog-to-digital conversion unit to match the bit width of the first image signal. .
(13)
The pixel block control unit generates a plurality of at least one of the first image signal and the added image signal,
The analog-to-digital converter converts the plurality of first image signals or the plurality of added image signals into digital signals,
The signal processing unit outputs an average of the first image signal of a plurality of digital signals or the added image signal of a plurality of digital signals as the first image signal or the added image signal. image sensor.
(14)
A first pixel for generating charges by performing photoelectric conversion on incident light with a predetermined wavelength out of incident light, and a second pixel for generating charges by performing photoelectric conversion on incident light with a wavelength different from that of the first pixels. 2 pixels, a charge holding portion that holds charges generated by the first pixel and the second pixel, and a signal generating portion that generates an image signal based on the charges held in the charge holding portion. a pixel block comprising
a control for transferring the charge generated by the first pixel to the charge holding unit and causing the signal generation unit to generate a first image signal, which is the image signal based on the charge; The charge generated by the second pixel is further transferred to the charge holding portion holding the generated charge, and the charge generated by the first pixel and the charge generated by the second pixel are added together. a pixel block control unit that controls the signal generation unit to generate an added image signal that is the image signal based on
A first mode for outputting the first image signal and the added image signal, comprising a subtracting unit that generates a second image signal that is the image signal obtained by subtracting the first image signal from the added image signal. and a second mode for outputting the first image signal and the second image signal;
and a processing circuit that processes at least one of the first image signal, the added image signal, and the second image signal.
　１、１００１　撮像素子
　２０　垂直駆動部
　３０　カラム信号処理部
　３１　アナログデジタル変換部
　３４　減算部
　１００　画素ブロック
　１０１、１０１ａ、１０１ｂ、１０１ｃ、１０１ｄ、１０１ｅ、１０１ｆ、１０１ｇ、１０１ｈ　光電変換部
　１０２ａ、１０２ｂ、１０２ｃ、１０２ｄ、１０２ｅ、１０２ｆ、１０２ｇ、１０２ｈ　電荷転送部
　１０４　リセットトランジスタ
　１０６　電荷保持部
　１１０、１１０ａ、１１０ｂ、１１０ｃ、１１０ｄ　画素
　１２０　信号生成部
　１０００　撮像装置
　１００３　画像処理部 1, 1001 image sensor 20 vertical driving unit 30 column signal processing unit 31 analog-digital converting unit 34 subtracting unit 100 pixel block 101, 101a, 101b, 101c, 101d, 101e, 101f, 101g, 101h photoelectric converting unit 102a, 102b, 102c , 102d, 102e, 102f, 102g, 102h charge transfer section 104 reset transistor 106 charge holding section 110, 110a, 110b, 110c, 110d pixel 120 signal generation section 1000 imaging device 1003 image processing section

Claims (14)

  1. 　入射光のうちの所定の波長の入射光の光電変換を行って電荷を生成する第１の画素と、前記第１の画素とは異なる波長の入射光の光電変換を行って電荷を生成する第２の画素と、前記第１の画素及び前記第２の画素により生成される電荷を保持する電荷保持部と、前記電荷保持部に保持された電荷に基づいて画像信号を生成する信号生成部とを備える画素ブロックと、
    　前記第１の画素により生成された電荷を前記電荷保持部に転送して当該電荷に基づく前記画像信号である第１の画像信号を前記信号生成部に生成させる制御と、前記第１の画素により生成された電荷が保持された前記電荷保持部に前記第２の画素により生成された電荷を更に転送して前記第１の画素及び前記第２の画素によりそれぞれ生成される電荷が加算された電荷に基づく前記画像信号である加算画像信号を前記信号生成部に生成させる制御とを行う画素ブロック制御部と、
    　前記加算画像信号から前記第１の画像信号を減算した前記画像信号である第２の画像信号を生成する減算部を備え、前記第１の画像信号及び前記加算画像信号を出力する第１のモードと前記第１の画像信号及び前記第２の画像信号を出力する第２のモードとを切り替える信号処理部と
    　を有する撮像素子。     A first pixel for generating charges by performing photoelectric conversion on incident light with a predetermined wavelength out of incident light, and a second pixel for generating charges by performing photoelectric conversion on incident light with a wavelength different from that of the first pixels. 2 pixels, a charge holding unit that holds charges generated by the first pixel and the second pixel, and a signal generation unit that generates an image signal based on the charges held in the charge holding unit. a pixel block comprising
    a control for transferring the charge generated by the first pixel to the charge holding unit and causing the signal generation unit to generate a first image signal, which is the image signal based on the charge; The charge generated by the second pixel is further transferred to the charge holding portion holding the generated charge, and the charge generated by the first pixel and the charge generated by the second pixel are added together. a pixel block control unit that controls the signal generation unit to generate an added image signal that is the image signal based on
    A first mode for outputting the first image signal and the added image signal, comprising a subtracting unit that generates a second image signal that is the image signal obtained by subtracting the first image signal from the added image signal. and a signal processing unit that switches between a second mode for outputting the first image signal and the second image signal.
  2. 　前記第１の画素は、前記入射光のうちの赤色光、緑色光及び青色光の何れかの光電変換を行う請求項１に記載の撮像素子。 The imaging device according to claim 1, wherein the first pixels photoelectrically convert any one of red light, green light, and blue light in the incident light.
  3. 　前記第２の画素は、前記入射光のうちの白色光の光電変換を行う請求項１に記載の撮像素子。 The imaging device according to claim 1, wherein the second pixel photoelectrically converts white light in the incident light.
  4. 　前記第２の画素は、前記入射光のうちの黄色光、赤紫色光及び青緑色光の何れかの光電変換を行う請求項１に記載の撮像素子。 The imaging device according to claim 1, wherein the second pixel photoelectrically converts any one of yellow light, red-violet light, and blue-green light out of the incident light.
  5. 　前記第２の画素は、前記入射光のうちの赤外光の光電変換を行う請求項１に記載の撮像素子。 The imaging device according to claim 1, wherein the second pixel photoelectrically converts infrared light in the incident light.
  6. 　前記画素ブロックは、複数の前記第１の画素及び複数の前記第２の画素が正方行列に配置されるとともに前記第１の画素及び前記第２の画素が行方向及び列方向に交互に配置されて構成される請求項１に記載の撮像素子。 In the pixel block, a plurality of the first pixels and a plurality of the second pixels are arranged in a square matrix, and the first pixels and the second pixels are arranged alternately in a row direction and a column direction. 2. The imaging device according to claim 1, comprising:
  7. 　前記電荷保持部の電荷を排出することによりリセットを行うリセット部を更に有し、
    　前記画素ブロック制御部は、前記リセット部によるリセット時の画像信号である基準画像信号を生成させる制御を更に行い、
    　前記信号処理部は、前記第１の画像信号から前記基準画像信号を減算することによる第１の画像信号の補正と、前記加算画像信号から前記基準画像信号を減算することによる加算画像信号の補正とを更に行う
    　請求項１に記載の撮像素子。     further comprising a reset unit for resetting by discharging the charge in the charge holding unit;
    The pixel block control unit further performs control to generate a reference image signal, which is an image signal at the time of reset by the reset unit,
    The signal processing unit corrects the first image signal by subtracting the reference image signal from the first image signal, and corrects the addition image signal by subtracting the reference image signal from the addition image signal. and further performing the imaging device according to claim 1 .
  8. 　前記第１の画素は、被写体を瞳分割するための複数の光電変換部を備え、
    　前記画素ブロック制御部は、前記第１の画素の複数の光電変換部の何れかにより生成された電荷を前記電荷保持部に転送して当該電荷に基づく画像信号を前記信号生成部に生成させる制御を更に行い、前記第１の画素の複数の前記光電変換部により生成された電荷を前記電荷保持部に転送して当該電荷に基づく画像信号を前記第１の画像信号として前記信号生成部に生成させる
    　請求項１に記載の撮像素子。     the first pixel includes a plurality of photoelectric conversion units for pupil-dividing the subject;
    The pixel block control section transfers the charge generated by one of the plurality of photoelectric conversion sections of the first pixel to the charge holding section and controls the signal generation section to generate an image signal based on the charge. and transferring the charges generated by the plurality of photoelectric conversion units of the first pixel to the charge holding unit, and generating an image signal based on the charges as the first image signal in the signal generation unit. The imaging device according to claim 1 .
  9. 　前記信号処理部は、前記第１の画像信号及び前記加算画像信号をデジタル信号に変換するアナログデジタル変換部を更に備え、
    　前記信号処理部は、前記アナログデジタル変換部により変換されたデジタル信号の前記第１の画像信号及び前記加算画像信号を出力する
    　請求項１に記載の撮像素子。     The signal processing unit further includes an analog-to-digital conversion unit that converts the first image signal and the added image signal into digital signals,
    The imaging device according to claim 1, wherein the signal processing section outputs the first image signal and the added image signal of digital signals converted by the analog-to-digital conversion section.
  10. 　前記信号処理部は、デジタル信号の前記第１の画像信号とビット幅を揃えたデジタル信号の前記加算画像信号を生成して出力する請求項９に記載の撮像素子。 The imaging device according to claim 9, wherein the signal processing unit generates and outputs the added image signal of a digital signal having the same bit width as that of the first image signal of a digital signal.
  11. 　前記信号処理部は、アナログデジタル変換部により変換されたデジタル信号の前記加算画像信号の最上位ビットを削除することにより前記第１の画像信号とビット幅を揃える請求項１０に記載の撮像素子。 The image pickup device according to claim 10, wherein the signal processing unit aligns the bit width with the first image signal by deleting the most significant bit of the added image signal of the digital signal converted by the analog-to-digital conversion unit.
  12. 　前記信号処理部は、アナログデジタル変換部により変換されたデジタル信号の前記加算画像信号の最下位ビットを削除することにより前記第１の画像信号とビット幅を揃える請求項１０に記載の撮像素子。 The image pickup device according to claim 10, wherein the signal processing unit aligns the bit width with the first image signal by deleting the least significant bit of the added image signal of the digital signal converted by the analog-to-digital conversion unit.
  13. 　前記画素ブロック制御部は、前記第１の画像信号及び前記加算画像信号の少なくとも一方を複数生成し、
    　前記アナログデジタル変換部は、複数の前記第１の画像信号又は複数の前記加算画像信号のデジタル信号に変換し、
    　前記信号処理部は、複数のデジタル信号の前記第１の画像信号又は複数のデジタル信号の前記加算画像信号の平均を前記第１の画像信号又は前記加算画像信号として出力する
    　請求項９に記載の撮像素子。     The pixel block control unit generates a plurality of at least one of the first image signal and the added image signal,
    The analog-to-digital converter converts the plurality of first image signals or the plurality of added image signals into digital signals,
    10. The signal processing unit according to claim 9, wherein an average of the first image signal of a plurality of digital signals or the added image signal of a plurality of digital signals is output as the first image signal or the added image signal. image sensor.
  14. 　入射光のうちの所定の波長の入射光の光電変換を行って電荷を生成する第１の画素と、前記第１の画素とは異なる波長の入射光の光電変換を行って電荷を生成する第２の画素と、前記第１の画素及び前記第２の画素により生成される電荷を保持する電荷保持部と、前記電荷保持部に保持された電荷に基づいて画像信号を生成する信号生成部とを備える画素ブロックと、
    　前記第１の画素により生成された電荷を前記電荷保持部に転送して当該電荷に基づく前記画像信号である第１の画像信号を前記信号生成部に生成させる制御と、前記第１の画素により生成された電荷が保持された前記電荷保持部に前記第２の画素により生成された電荷を更に転送して前記第１の画素及び前記第２の画素によりそれぞれ生成される電荷が加算された電荷に基づく前記画像信号である加算画像信号を前記信号生成部に生成させる制御とを行う画素ブロック制御部と、
    　前記加算画像信号から前記第１の画像信号を減算した前記画像信号である第２の画像信号を生成する減算部を備え、前記第１の画像信号及び前記加算画像信号を出力する第１のモードと前記第１の画像信号及び前記第２の画像信号を出力する第２のモードとを切り替える信号処理部と、
    　前記第１の画像信号、前記加算画像信号及び前記第２の画像信号の少なくとも１つを処理する処理回路と
    　を有する電子機器。     A first pixel for generating charges by performing photoelectric conversion on incident light with a predetermined wavelength out of incident light, and a second pixel for generating charges by performing photoelectric conversion on incident light with a wavelength different from that of the first pixels. 2 pixels, a charge holding unit that holds charges generated by the first pixel and the second pixel, and a signal generation unit that generates an image signal based on the charges held in the charge holding unit. a pixel block comprising
    a control for transferring the charge generated by the first pixel to the charge holding unit and causing the signal generation unit to generate a first image signal, which is the image signal based on the charge; The charge generated by the second pixel is further transferred to the charge holding portion holding the generated charge, and the charge generated by the first pixel and the charge generated by the second pixel are added together. a pixel block control unit that controls the signal generation unit to generate an added image signal that is the image signal based on
    A first mode for outputting the first image signal and the added image signal, comprising a subtracting unit that generates a second image signal that is the image signal obtained by subtracting the first image signal from the added image signal. and a second mode for outputting the first image signal and the second image signal;
    and a processing circuit that processes at least one of the first image signal, the added image signal, and the second image signal.
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