WO2023165072A1 - 一种高可靠性低缺陷半导体发光器件及其制备方法 - Google Patents

一种高可靠性低缺陷半导体发光器件及其制备方法 Download PDF

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WO2023165072A1
WO2023165072A1 PCT/CN2022/106853 CN2022106853W WO2023165072A1 WO 2023165072 A1 WO2023165072 A1 WO 2023165072A1 CN 2022106853 W CN2022106853 W CN 2022106853W WO 2023165072 A1 WO2023165072 A1 WO 2023165072A1
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layer
doped
semiconductor
emitting device
protective layer
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PCT/CN2022/106853
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English (en)
French (fr)
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王俊
谭少阳
张立晨
胡燚文
赵武
李波
李泉灵
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苏州长光华芯光电技术股份有限公司
苏州长光华芯半导体激光创新研究院有限公司
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Priority to JP2022579921A priority Critical patent/JP2024512837A/ja
Priority to EP22808568.4A priority patent/EP4266515A4/en
Publication of WO2023165072A1 publication Critical patent/WO2023165072A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00—Semiconductor lasers
    • H01S5/20—Structure or shape of the semiconductor body to guide the optical wave ; Confining structures perpendicular to the optical axis, e.g. index or gain guiding, stripe geometry, broad area lasers, gain tailoring, transverse or lateral reflectors, special cladding structures, MQW barrier reflection layers
    • H01S5/2054—Methods of obtaining the confinement
    • H01S5/2081—Methods of obtaining the confinement using special etching techniques
    • H01S5/2086—Methods of obtaining the confinement using special etching techniques lateral etch control, e.g. mask induced
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00—Semiconductor lasers
    • H01S5/04—Processes or apparatus for excitation, e.g. pumping, e.g. by electron beams
    • H01S5/042—Electrical excitation ; Circuits therefor
    • H01S5/0421—Electrical excitation ; Circuits therefor characterised by the semiconducting contacting layers
    • H—ELECTRICITY
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    • H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00—Semiconductor lasers
    • H01S5/04—Processes or apparatus for excitation, e.g. pumping, e.g. by electron beams
    • H01S5/042—Electrical excitation ; Circuits therefor
    • H01S5/0425—Electrodes, e.g. characterised by the structure
    • H01S5/04254—Electrodes, e.g. characterised by the structure characterised by the shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00—Semiconductor lasers
    • H01S5/10—Construction or shape of the optical resonator, e.g. extended or external cavity, coupled cavities, bent-guide, varying width, thickness or composition of the active region
    • H01S5/16—Window-type lasers, i.e. with a region of non-absorbing material between the active region and the reflecting surface
    • H01S5/168—Window-type lasers, i.e. with a region of non-absorbing material between the active region and the reflecting surface with window regions comprising current blocking layers
    • H—ELECTRICITY
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    • H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00—Semiconductor lasers
    • H01S5/02—Structural details or components not essential to laser action
    • H01S5/0201—Separation of the wafer into individual elements, e.g. by dicing, cleaving, etching or directly during growth
    • H—ELECTRICITY
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    • H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00—Semiconductor lasers
    • H01S5/02—Structural details or components not essential to laser action
    • H01S5/022—Mountings; Housings
    • H01S5/0235—Method for mounting laser chips
    • H01S5/02355—Fixing laser chips on mounts
    • H01S5/0237—Fixing laser chips on mounts by soldering
    • H—ELECTRICITY
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    • H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00—Semiconductor lasers
    • H01S5/02—Structural details or components not essential to laser action
    • H01S5/028—Coatings ; Treatment of the laser facets, e.g. etching, passivation layers or reflecting layers
    • H01S5/0287—Facet reflectivity
    • H—ELECTRICITY
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    • H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00—Semiconductor lasers
    • H01S5/04—Processes or apparatus for excitation, e.g. pumping, e.g. by electron beams
    • H01S5/042—Electrical excitation ; Circuits therefor
    • H01S5/0425—Electrodes, e.g. characterised by the structure
    • H01S5/04256—Electrodes, e.g. characterised by the structure characterised by the configuration
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00—Semiconductor lasers
    • H01S5/20—Structure or shape of the semiconductor body to guide the optical wave ; Confining structures perpendicular to the optical axis, e.g. index or gain guiding, stripe geometry, broad area lasers, gain tailoring, transverse or lateral reflectors, special cladding structures, MQW barrier reflection layers
    • H01S5/2054—Methods of obtaining the confinement
    • H01S5/2081—Methods of obtaining the confinement using special etching techniques
    • H01S5/209—Methods of obtaining the confinement using special etching techniques special etch stop layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00—Semiconductor lasers
    • H01S5/20—Structure or shape of the semiconductor body to guide the optical wave ; Confining structures perpendicular to the optical axis, e.g. index or gain guiding, stripe geometry, broad area lasers, gain tailoring, transverse or lateral reflectors, special cladding structures, MQW barrier reflection layers
    • H01S5/22—Structure or shape of the semiconductor body to guide the optical wave ; Confining structures perpendicular to the optical axis, e.g. index or gain guiding, stripe geometry, broad area lasers, gain tailoring, transverse or lateral reflectors, special cladding structures, MQW barrier reflection layers having a ridge or stripe structure
    • H01S5/2205—Structure or shape of the semiconductor body to guide the optical wave ; Confining structures perpendicular to the optical axis, e.g. index or gain guiding, stripe geometry, broad area lasers, gain tailoring, transverse or lateral reflectors, special cladding structures, MQW barrier reflection layers having a ridge or stripe structure comprising special burying or current confinement layers
    • H01S5/2222—Structure or shape of the semiconductor body to guide the optical wave ; Confining structures perpendicular to the optical axis, e.g. index or gain guiding, stripe geometry, broad area lasers, gain tailoring, transverse or lateral reflectors, special cladding structures, MQW barrier reflection layers having a ridge or stripe structure comprising special burying or current confinement layers having special electric properties
    • H01S5/2224—Structure or shape of the semiconductor body to guide the optical wave ; Confining structures perpendicular to the optical axis, e.g. index or gain guiding, stripe geometry, broad area lasers, gain tailoring, transverse or lateral reflectors, special cladding structures, MQW barrier reflection layers having a ridge or stripe structure comprising special burying or current confinement layers having special electric properties semi-insulating semiconductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00—Semiconductor lasers
    • H01S5/20—Structure or shape of the semiconductor body to guide the optical wave ; Confining structures perpendicular to the optical axis, e.g. index or gain guiding, stripe geometry, broad area lasers, gain tailoring, transverse or lateral reflectors, special cladding structures, MQW barrier reflection layers
    • H01S5/22—Structure or shape of the semiconductor body to guide the optical wave ; Confining structures perpendicular to the optical axis, e.g. index or gain guiding, stripe geometry, broad area lasers, gain tailoring, transverse or lateral reflectors, special cladding structures, MQW barrier reflection layers having a ridge or stripe structure
    • H01S5/223—Buried stripe structure
    • H01S5/2231—Buried stripe structure with inner confining structure only between the active layer and the upper electrode

Definitions

  • the present application relates to the field of semiconductor technology, in particular to a high-reliability and low-defect semiconductor light-emitting device and a preparation method thereof.
  • a semiconductor light-emitting device is a device that produces stimulated emission with a certain semiconductor material as a working substance.
  • the particle number inversion of the non-equilibrium carrier is realized between the energy band of the energy band of the impurity and the energy level of the impurity (acceptor or donor).
  • Semiconductor light-emitting devices are widely used due to their small size and high electro-optical conversion efficiency.
  • the existing defect optimization technology for the surface of semiconductor light-emitting devices is difficult to take into account the problems of improving reliability and reducing process control costs.
  • the technical problem to be solved in the present application is to overcome the problem of high reliability and low process control cost in the prior art, so as to provide a semiconductor light-emitting device with high reliability and low defect and its preparation method.
  • the present application provides a high-reliability and low-defect semiconductor light-emitting device, including: a semiconductor substrate layer; an active layer located on the semiconductor substrate layer; a doped semiconductor located on the side of the active layer away from the semiconductor substrate layer A contact layer, the doped semiconductor contact layer includes a first region and an edge region surrounding the first region; a protective layer located on the side of the edge region of the doped semiconductor contact layer away from the active layer; a front electrode Layer, located on the side of the first region away from the active layer, the upper surface of the front electrode layer on the first region is lower than the upper surface of the protective layer.
  • the height difference between the upper surface of the protective layer and the upper surface of the front electrode layer on the first region is 0.05 ⁇ m-5 ⁇ m.
  • the thickness of the protective layer in a direction perpendicular to the surface of the semiconductor substrate layer is 0.1 ⁇ m-5 ⁇ m.
  • the high-reliability and low-defect semiconductor light-emitting device has a front cavity surface and a rear cavity surface oppositely disposed, and both the front cavity surface and the rear cavity surface expose the sidewall surface of the active layer and the doped semiconductor contact layer
  • the side wall surface; the protective layer includes a first sub-protection area and a second sub-protection area oppositely arranged, the first sub-protection area and the second sub-protection area are arranged along the light-emitting direction, and the first sub-protection area
  • the outer sidewall is aligned with the sidewall surface of the active layer exposed on the front cavity surface and the sidewall surface of the doped semiconductor contact layer exposed on the front cavity surface, and the outer sidewall of the second sub-protection region is aligned with the back cavity
  • the sidewall surface of the active layer exposed on the back cavity surface is aligned with the sidewall surface of the doped semiconductor contact layer exposed on the rear cavity surface.
  • the material of the doped semiconductor contact layer is a first host semiconductor material doped with first conductive ions; the material of the protection layer is an undoped second host semiconductor material, or, the protection The material of the layer is a second host semiconductor material doped with second conductive particles, the conductivity type of the second conductive particles is opposite to that of the first conductive ions; or, the material of the protective layer is doped with The second host semiconductor material of the second conductive particles, the conductivity type of the second conductive particles is the same as that of the first conductive ions, and the doping concentration of the second conductive particles is lower than that of the first conductive ions doping concentration.
  • the doping concentration of the second conductive particles is 10 -6 times to 10 -6 times the doping concentration of the first conductive ions. 10 -1 times.
  • the average lattice mismatch between the second host semiconductor material and the first host semiconductor material is less than or equal to 1%.
  • the second bulk semiconductor material is the same as the first bulk semiconductor material.
  • the protective layer is a single-layer structure or a multi-layer structure.
  • the material of the protective layer is doped or undoped GaAs, or the material of the protective layer is doped or undoped AlGaAs, Or, the material of the protective layer is doped or undoped InGaP; or, the material of the protective layer is doped or undoped InGaAsP, or, the material of the protective layer is doped or undoped doped InGaAs; when the material of the semiconductor substrate layer is an InP substrate, the material of the protective layer is doped or undoped InGaAsP, or the material of the protective layer is doped or undoped InGaAlAs, or, the material of the protective layer is doped or undoped InGaAs, or, the material of the protective layer is doped or undoped InAlAs, or, the material of the protective layer is doped or Undoped InP; when the material of the semiconductor substrate layer is a GaN substrate, the material of the protective layer is doped or undoped InGaP; when the material
  • the front electrode layer is also located on the side of the protective layer away from the doped semiconductor contact layer;
  • the high-reliability and low-defect semiconductor light-emitting device further includes: a current-limiting insulating layer, the current-limiting insulating layer The side between the front electrode layer on the protective layer and the protective layer and the edge of the first region is away from the active layer.
  • the doped semiconductor contact layer includes a first sub-doped semiconductor layer and a second sub-doped semiconductor layer located on the surface of the first sub-doped semiconductor layer away from the active layer, the The doping concentration of the second sub-doped semiconductor layer is greater than that of the first sub-doped semiconductor layer.
  • the doping concentration of the second sub-doped semiconductor layer is 10 to 50 times that of the first sub-doped semiconductor layer.
  • it also includes: an upper waveguide layer located between the doped semiconductor contact layer and the active layer; an upper confinement layer located between the upper waveguide layer and the doped semiconductor contact layer; The lower waveguide layer between the active layer and the semiconductor substrate layer, the lower confinement layer between the lower waveguide layer and the semiconductor substrate layer; the back side of the surface of the semiconductor substrate layer away from the active layer electrode layer.
  • the present application also provides a method for manufacturing a high-reliability and low-defect semiconductor light-emitting device, including: providing a semiconductor substrate layer; forming an active layer on the semiconductor substrate layer; A doped semiconductor contact layer is formed on one side, the doped semiconductor contact layer includes a first region and an edge region surrounding the first region; the edge region of the doped semiconductor contact layer is away from the side of the active layer Forming a protective layer; forming a front electrode layer on the side of the first region away from the active layer, the upper surface of the front electrode layer on the first region is lower than the upper surface of the protective layer.
  • the step of forming the protective layer includes: epitaxially growing an initial protective layer on the side of the first region and the edge region away from the active layer; etching and removing the initial protective layer on the first region to form The protective layer on the surface of the first region is exposed.
  • the doped semiconductor contact layer and the initial protection layer are successively formed in one epitaxial process.
  • a current confinement insulating layer is formed, and the current confinement insulating layer is located on the side of the protective layer and part of the edge of the first region away from the active layer;
  • the front electrode layer is also formed on the side of the current limiting insulating layer facing away from the protective layer.
  • the step of forming the doped semiconductor contact layer includes: forming a first sub-doped semiconductor layer on a side of the active layer away from the semiconductor substrate layer; A second sub-doped semiconductor layer is formed on a side surface away from the active layer, and the doping concentration of the second sub-doped semiconductor layer is greater than that of the first sub-doped semiconductor layer.
  • the method for manufacturing a high-reliability and low-defect semiconductor light-emitting device further includes: Cleaving the front electrode layer, the current confinement insulating layer, the protective layer, the doped semiconductor contact layer, the active layer and the semiconductor substrate layer along the cutting area.
  • the high-reliability and low-defect semiconductor light-emitting device includes a protective layer, which is located on the side of the edge region of the doped semiconductor contact layer away from the active layer, and the protective layer is used to The edge region of the hetero-semiconductor contact layer is raised so that the upper surface of the front electrode layer on the first region is lower than the upper surface of the protection layer. Since the upper surface of the front electrode layer on the first region is lower than the upper surface of the protection layer, the protection layer protects the front electrode layer on the first region.
  • the protective layer can avoid scratches and pollution defects caused by external forces in the preparation of semiconductor light-emitting devices; secondly, the introduction of the protective layer increases the distance from the front electrode layer on the protective layer to the active layer, which greatly reduces the performance of semiconductor light-emitting devices. The effect of cleaving defects on the cavity surface and sides of the active layer. Even if a small amount of material of the front electrode layer extends to part of the cavity surface of the semiconductor light emitting device, the existence of the protective layer can prevent the material of the front electrode layer from extending to the active layer, which reduces the coating shielding of the material of the front electrode layer on the cavity surface , reducing optical catastrophe damage on the cavity surface. In summary, the reliability of the semiconductor light emitting device is improved. Secondly, setting a protective layer is easier to implement, the technical difficulty is reduced, and the cost is lower.
  • the conductivity type of the second conductive particles when the conductivity type of the second conductive particles is opposite to that of the first conductive ions, an electrical isolation is formed between the doped semiconductor contact layer and the protective layer, so that the doped semiconductor contact layer The current in the edge region is limited.
  • the conductivity type of the second conductive particles is the same as that of the first conductive ions, since the doping concentration of the second conductive particles is smaller than the doping concentration of the first conductive ions, the protective layer It is not easy to conduct electricity, and the protective layer restricts the current in the edge region of the doped semiconductor contact layer to a certain extent.
  • the doping concentration of the second conductive particles is 10 ⁇ 6 to 10 ⁇ 1 times that of the first conductive ions.
  • the protection layer provides additional electrical insulation, so that the current in the edge region of the doped semiconductor contact layer is guaranteed by the double limitation of the current confinement insulating layer and the protection layer.
  • the material of the doped semiconductor contact layer is a first host semiconductor material doped with first conductive ions; the material of the protective layer is an undoped second host semiconductor material, or, the material of the protective layer
  • the material is a second host semiconductor material doped with second conductive particles.
  • the average lattice mismatch between the second host semiconductor material and the first host semiconductor material is less than or equal to 1%, so that the stress at the interface between the doped semiconductor contact layer and the protective layer is reduced, and the doped semiconductor contact layer and the protective layer
  • the lattice matching degree of the interface of the protection layer is high, so that the protection layer can be easily formed on the doped semiconductor contact layer.
  • the doped semiconductor contact layer includes a first sub-doped semiconductor layer and a second sub-doped semiconductor layer located on the surface of the first sub-doped semiconductor layer away from the active layer, the second sub-doped semiconductor layer
  • the doping concentration of the sub-doped semiconductor layer is greater than the doping concentration of the first sub-doped semiconductor layer. Since the doping concentration of the second sub-doped semiconductor layer is relatively high, the contact resistance between the second sub-doped semiconductor layer and the front electrode layer is reduced.
  • the doping concentration of the first sub-doped semiconductor layer is relatively low, and the second sub-doped semiconductor layer is far away from the active layer relative to the first sub-doped semiconductor layer, the doping ions of the doped semiconductor contact layer are active The absorption loss effect of the light emitted by the layer is reduced.
  • a protective layer is formed on the side of the edge region of the doped semiconductor contact layer away from the active layer, and the protective layer is used for doping
  • the edge region of the semiconductor contact layer is elevated such that the upper surface of the front electrode layer on the first region is lower than the upper surface of the protection layer. Since the upper surface of the front electrode layer on the first region is lower than the upper surface of the protection layer, the protection layer protects the front electrode layer on the first region.
  • the protective layer can avoid scratches and pollution defects caused by external forces in the preparation of semiconductor light-emitting devices; secondly, the introduction of the protective layer increases the distance from the front electrode layer on the protective layer to the active layer, which greatly reduces the performance of semiconductor light-emitting devices. The effect of cleaving defects on the cavity surface and sides of the active layer. Even if a small amount of material of the front electrode layer extends to part of the cavity surface of the semiconductor light emitting device, the existence of the protective layer can prevent the material of the front electrode layer from extending to the active layer, which reduces the coating shielding of the material of the front electrode layer on the cavity surface , reducing optical catastrophe damage on the cavity surface. In summary, the reliability of the semiconductor light emitting device is improved. Secondly, setting a protective layer is easier to implement, the technical difficulty is reduced, and the cost is lower.
  • the doped semiconductor contact layer and the initial protective layer are successively formed in one epitaxial process, which simplifies the process. And since the formation of the doped semiconductor contact layer and the initial protective layer is continuous, defects are avoided between the doped semiconductor contact layer and the initial protective layer, so that the edge regions of the protective layer and the doped semiconductor contact layer The defects between are reduced, so as to avoid affecting the carrier mobility and avoid increasing the resistance voltage of the device.
  • the electrical isolation of the protective layer can prevent the current limiting insulating layer from The phenomenon of breakdown due to the increase of charge can avoid the reduction of the aging life of the semiconductor light-emitting device or the leakage and burning of the semiconductor light-emitting device.
  • FIG. 1 is a schematic structural diagram of a high-reliability and low-defect semiconductor light-emitting device according to an embodiment of the present application
  • FIGS. 2 to 6 are structural views of the manufacturing process of a high-reliability and low-defect semiconductor light-emitting device in another embodiment of the present application.
  • the failure of semiconductor light-emitting devices is usually caused by the introduction of contamination or scratch defects on the wafer surface during the process of preparation or packaging, and the cleavage defects of the chip cavity surface close to the surface during the chip cleavage coating packaging process. Defects on the surface lead to stacking faults in the dielectric film during the deposition process. If such anomalies occur near the light-emitting region, it will affect the carrier mobility and cause the resistance voltage of the device to increase, or the charge of the dielectric layer will increase and cause dielectric breakdown.
  • Wafer surface defects also lead to packaging defects in the current injection area of the chip, which leads to high local temperature and stress of the chip, thereby causing active material failure. Cleavage defects on the cavity surface and side surfaces close to the surface lead to catastrophic damage on the cavity surface, thereby causing bypass leakage and burning during the packaging process. Therefore, device reliability is usually improved through strict control of epitaxial growth adjustment, wafer preparation, cavity surface coating and packaging process.
  • each of the above-mentioned technologies will bring defects such as technical complexity, reduction of process stability, and increase of process production cost.
  • An embodiment of the present application provides a high-reliability and low-defect semiconductor light-emitting device, referring to FIG. 1 , including:
  • a doped semiconductor contact layer 160 located on a side of the active layer 130 away from the semiconductor substrate layer 100, the doped semiconductor contact layer 160 comprising a first region and an edge region surrounding the first region;
  • a protection layer 170 located on a side of the edge region of the doped semiconductor contact layer 160 away from the active layer 130;
  • the front electrode layer 190 is located on the side of the first region away from the active layer 130 , and the upper surface of the front electrode layer 190 on the first region is lower than the upper surface of the protective layer 170 .
  • the protective layer 170 is used to raise the edge region of the doped semiconductor contact layer 160, so that the upper surface of the front electrode layer 190 on the first region is lower than the upper surface of the protective layer 170. surface. Since the upper surface of the front electrode layer 190 on the first region is lower than the upper surface of the protection layer 170 , the protection layer protects the front electrode layer 190 on the first region.
  • the protective layer 170 can avoid scratches and pollution defects caused by external forces in the semiconductor light-emitting device manufacturing process; secondly, the introduction of the protective layer 170 increases the distance from the front electrode layer 190 on the protective layer 170 to the active layer, which greatly reduces The effect of cleaving defects generated on the cavity surface and side surfaces of semiconductor light-emitting devices on the active layer. Even if a small amount of material of the front electrode layer 190 extends to part of the cavity surface of the semiconductor light emitting device, the existence of the protective layer 170 can prevent the material of the front electrode layer 190 from extending to the active layer 130, which reduces the material impact of the front electrode layer 190. The coating shielding of the cavity surface reduces the optical catastrophe damage of the cavity surface. In summary, the reliability of the semiconductor light emitting device is improved. Secondly, setting the protective layer 170 is relatively easy to implement, the technical difficulty is reduced, and the cost is low.
  • the height difference between the upper surface of the protection layer 170 and the upper surface of the front electrode layer 190 on the first region is 0.05 ⁇ m-5 ⁇ m, for example, 0.05 ⁇ m, 0.1 ⁇ m, 0.5 ⁇ m , 2 ⁇ m, 3 ⁇ m, 4 ⁇ m or 5 ⁇ m.
  • the protective layer 170 has a greater impact on the first region and the active layer 130
  • the protective effect is weak; if the height difference between the upper surface of the protective layer 170 and the upper surface of the front electrode layer 190 located on the first region is greater than 5 ⁇ m, the height of the semiconductor light emitting device will be too high, and it is not used for miniaturization.
  • the thickness of the protection layer 170 in a direction perpendicular to the surface of the semiconductor substrate layer 100 is 0.1 ⁇ m-5 ⁇ m, such as 0.1 ⁇ m, 0.5 ⁇ m, 2 ⁇ m, 3 ⁇ m, 4 ⁇ m or 5 ⁇ m. If the thickness of the protective layer 170 in the direction perpendicular to the surface of the semiconductor substrate layer 100 is too small, the protective effect of the protective layer 170 on the first region and the active layer 130 is weak; If the thickness in the direction of the surface of the semiconductor substrate layer 100 is too large, the height of the semiconductor light emitting device will be too high, and it is not suitable for miniaturization.
  • the protection layer 170 is a ring structure.
  • the protective layer 170 is not disposed over the first region.
  • the high-reliability and low-defect semiconductor light-emitting device has a front cavity surface and a back cavity surface opposite to each other, and both the front cavity surface and the back cavity surface expose the side wall surface of the active layer 130 and the side of the doped semiconductor contact layer 160 Wall surface;
  • the protective layer 170 includes a first sub-protection area and a second sub-protection area oppositely arranged, the first sub-protection area and the second sub-protection area are arranged along the light emitting direction, and the outer side of the first sub-protection area
  • the wall is aligned with the side wall surface of the active layer 130 exposed on the front cavity surface and the side wall surface of the doped semiconductor contact layer 160 exposed on the front cavity surface, and the outer side wall of the second sub-protection region is aligned with the rear
  • the sidewall surface of the active layer 130 exposed on the cavity surface is aligned with the sidewall surface of the doped semiconductor contact layer 160 exposed on the rear cavity surface.
  • the protective layer 170 also includes a third sub-protection area and a fourth sub-protection area oppositely arranged, the third sub-protection area is respectively connected with the first sub-protection area and the second sub-protection area, and the fourth sub-protection area is respectively connected with the first sub-protection area.
  • the first sub-protection area is connected with the second sub-protection area.
  • the material of the protective layer 170 is an undoped second host semiconductor material, or the material of the protective layer 170 is a second host semiconductor material doped with second conductive particles, and the conductivity of the second conductive particles
  • the type is opposite to the conductivity type of the first conductive ions; or, the material of the protective layer 170 is a second host semiconductor material doped with second conductive particles, and the conductivity type of the second conductive particles is the same as that of the first conductive particles.
  • the conductivity types of the conductive ions are the same, and the doping concentration of the second conductive particles is smaller than that of the first conductive ions.
  • the conductivity type of the second conductive particles is opposite to that of the first conductive ions, electrical isolation is formed between the doped semiconductor contact layer 160 and the protective layer 170, so that the edge of the doped semiconductor contact layer 160 area current is limited.
  • the conductivity type of the doped semiconductor contact layer 160 is N type
  • the conductivity type of the protection layer 170 is P type.
  • the protective layer 170 is not easy to conduct electricity, and the protective layer 170 limits the current in the edge region of the doped semiconductor contact layer 160 to a certain extent.
  • the average lattice mismatch between the second host semiconductor material and the first host semiconductor material is less than or equal to 1%, so that the interface between the doped semiconductor contact layer 160 and the protective layer 170 The stress is reduced, and the interface lattice matching between the doped semiconductor contact layer 160 and the protection layer 170 is high, so that the protection layer 170 can be easily formed on the doped semiconductor contact layer.
  • the second bulk semiconductor material is the same as the first bulk semiconductor material.
  • the doped semiconductor contact layer 160 and the protective layer 170 use the same host semiconductor material, so that the further stress at the interface between the doped semiconductor contact layer 160 and the protective layer 170 is reduced, and the doped semiconductor contact layer 160 and the protective layer 170 The lattice matching degree of the interface is further improved.
  • the protective layer 170 is a single-layer structure or a multi-layer structure.
  • the material of the protection layer 170 is a P-type semiconductor protection layer, an N-type semiconductor protection layer or an intrinsic semiconductor protection layer.
  • the material of the protective layer 170 is doped or undoped GaAs, or the material of the protective layer 170 is doped or undoped AlGaAs, or, the material of the protective layer 170 is doped or undoped InGaP, or, the material of the protective layer 170 is doped or undoped InGaAsP, or, the material of the protective layer is doped doped or non-doped InGaAs;
  • the material of the semiconductor substrate layer 100 is an InP substrate, the material of the protection layer 170 is doped or non-doped InGaAsP, or the material of the protection layer 170 is Doped or undoped InP, or, the material of the protective layer is doped or undoped InGaAlAs, or, the material of the protective layer is
  • the protective layer 170 When the protective layer 170 has a multi-layer structure, the protective layer 170 includes the first sub-protective layer to the Nth sub-protective layer, the k+1th sub-protective layer is located on the side of the k-th sub-protective layer away from the semiconductor substrate layer 100, N is an integer greater than or equal to 2, and k is an integer greater than or equal to 1 and less than or equal to N.
  • the conductivity type of the k+1th sub-protection layer is opposite to that of the kth sub-protection layer, and the conductivity type of the first sub-protection layer is opposite to that of the doped semiconductor contact layer. In one embodiment, the conductivity types of the first sub-protection layer to the Nth sub-protection layer are opposite to those of the doped semiconductor contact layer.
  • the front electrode layer 190 is also located on the side of the protective layer 170 away from the doped semiconductor contact layer 160; the high-reliability and low-defect semiconductor light emitting device further includes: a current limiting insulating layer 180, so The current limiting insulating layer 180 is located between the front electrode layer 190 on the protection layer 170 and the protection layer 170 .
  • the material of the current limiting insulating layer 180 includes silicon oxide.
  • the doping concentration of the second conductive particles is 10 -6 to 10 -1 times the doping concentration of the first conductive ions, such as 10 -6 times, 10 -5 times, 10 -4 times, 10 -3 times, 10 -2 times or 10 -1 times.
  • the protective layer 170 provides an additional electrical insulation function, so that the current in the edge region of the doped semiconductor contact layer 160 is guaranteed by the double limitation of the current limiting insulating layer 180 and the protective layer 170 .
  • the current limiting insulating layer 180 is located between the front electrode layer 190 on the protective layer 170 and the protective layer 170 and the edge of the first region is away from the side of the active layer 130, the current limiting insulating layer 180 also covers the inner sidewall of protective layer 170 . At this time, the region of the first region not covered by the current limiting insulating layer 180 serves as a current injection region.
  • the advantage is that when injecting current into the current injection region, since the current injection region has a certain distance from the interface between the protective layer 170 and the edge region of the doped semiconductor contact layer 160, the protective layer 170 is in contact with the doped semiconductor contact layer 160. The interfaces between the edge regions of layer 160 are less likely to form leakage paths.
  • the front electrode layer 190 also covers the current confining insulating layer 180 on the first region.
  • the width of the current confinement insulating layer 180 covering the edge of the first region refers to the width of any single side of the edge of the first region covered by the current confinement insulating layer 180 .
  • the doped semiconductor contact layer 160 includes a first sub-doped semiconductor layer 161 and a second sub-doped semiconductor layer located on the surface of the first sub-doped semiconductor layer 161 away from the active layer 130.
  • the semiconductor layer 162 , the doping concentration of the second sub-doped semiconductor layer 162 is greater than the doping concentration of the first sub-doped semiconductor layer 161 . Since the doping concentration of the second sub-doped semiconductor layer 162 is higher, the contact resistance between the second sub-doped semiconductor layer 162 and the front electrode layer 190 is reduced.
  • the doping concentration of the first sub-doped semiconductor layer 161 is low, and the second sub-doped semiconductor layer 162 is far away from the active layer 130 relative to the first sub-doped semiconductor layer 161, the doping of the doped semiconductor contact layer 160 The effect of hetero ions on absorption loss of light emitted from the active layer 130 is reduced.
  • the doping concentration of the second sub-doped semiconductor layer 162 is 10 times to 50 times that of the first sub-doped semiconductor layer 161 .
  • a good balance can be obtained between reducing the contact resistance between the second sub-doped semiconductor layer 162 and the front electrode layer 190 and reducing the influence of light absorption loss.
  • the doped semiconductor contact layer may be a single layer structure.
  • the first region of the doped semiconductor contact layer is used to make contact with the front electrode layer, thereby lowering the contact electrode.
  • the high-reliability and low-defect semiconductor light-emitting device further includes: an upper waveguide layer 140 located between the doped semiconductor contact layer 160 and the active layer 130; The upper confinement layer 150 between the contact layers 160; the lower waveguide layer 120 between the semiconductor substrate layer 100 and the active layer 130; The lower confinement layer 110 ; the back electrode layer 101 located on the surface of the semiconductor substrate layer 100 away from the active layer 130 .
  • the protective layer 170 increases the distance between the solder and the active layer during the soldering process, reducing the leakage and burnout failure caused by solder bumps. Therefore, the reliability of the semiconductor light emitting device is improved.
  • it also includes: an anti-reflection film covering the front cavity surface; and a reflection film covering the rear cavity surface.
  • This embodiment provides a method for manufacturing a high-reliability and low-defect semiconductor light-emitting device, referring to FIG. 1 , including:
  • S3 forming a doped semiconductor contact layer on a side of the active layer away from the semiconductor substrate layer, the doped semiconductor contact layer including a first region and an edge region surrounding the first region;
  • semiconductor substrate layer 100 is provided; Form lower confinement layer 110 on semiconductor substrate layer 100; Form lower waveguide layer 120 at the side of lower confinement layer 110 away from semiconductor substrate layer 100;
  • the active layer 130 is formed on the side;
  • the upper waveguide layer 140 is formed on the side of the active layer 130 away from the semiconductor substrate layer 100;
  • the upper confinement layer 150 is formed on the side of the upper waveguide layer 140 away from the active layer 130;
  • a doped semiconductor contact layer 160 is formed on a side facing away from the active layer 130 .
  • the step of forming the doped semiconductor contact layer 160 includes: forming a first sub-doped semiconductor layer 161 on the side of the active layer 130 away from the semiconductor substrate layer 100; A second sub-doped semiconductor layer 162 is formed on the surface of the sub-doped semiconductor layer 161 away from the active layer 130, and the doping concentration of the second sub-doped semiconductor layer 162 is higher than that of the first sub-doped semiconductor layer.
  • the doped semiconductor contact layer is a single layer structure.
  • a protection layer 170 is formed on a side of the edge region of the doped semiconductor contact layer away from the active layer.
  • the step of forming the protection layer 170 includes: referring to FIG. 2 , epitaxially growing an initial protection layer 17 on the side of the first region and the edge region away from the active layer 130 ; referring to FIG. 3 , etching and removing the first region The initial protection layer 17 on the upper surface forms a protection layer 170 that exposes the surface of the first region.
  • the initial protective layer 17 is a single-layer structure or a multi-layer structure.
  • the initial protective layer 17 When the initial protective layer 17 is a multilayer structure, the initial protective layer 17 includes the first sub-initial protective layer to the Nth sub-initial protective layer from bottom to top; the initial protective layer 17 on the first region is etched and removed, so that the k-th sub-initial protective layer The initial protection layer forms the kth sub-protection layer, so that the k+1th sub-initial protection layer forms the k+1th sub-initial protection layer.
  • the material of any k+1th sub-initial protective layer and the first sub-initial is greater than or equal to 5, such as 5, 8, 10, 15 or 20, and the etching selectivity ratio of the material of the first sub-initial protection layer and the material of the doped semiconductor contact layer 160 is greater than or equal to 5, such as 5, 8, 10, 15 or 20.
  • the etching selectivity ratio of the material of the first sub-initial protection layer to the material of the second sub-doped semiconductor layer 162 is greater than or equal to 5.
  • the process for forming the initial protective layer includes metal organic compound chemical vapor deposition (MOCVD) and molecular beam epitaxy (MEB).
  • MOCVD metal organic compound chemical vapor deposition
  • MEB molecular beam epitaxy
  • the doped semiconductor contact layer 160 and the initial protection layer 17 are formed successively in one epitaxial process, thereby simplifying the process. Since the formation of the doped semiconductor contact layer 160 and the initial protective layer 17 is continuous, defects are avoided between the doped semiconductor contact layer 160 and the initial protective layer 17, so that the protective layer 170 and the doped semiconductor contact Defects between the edge regions of the layer 160 are reduced, which avoids affecting carrier mobility, thereby avoiding causing an increase in device resistance voltage.
  • the doped semiconductor contact layer 160 and the initial protective layer 17 are continuously formed in the same chamber.
  • a current limiting insulating layer 180 is formed, and the current limiting insulating layer 180 is located on the side of the protective layer 170 away from the active layer 130. Further, the current limiting insulating layer 180 is located on the side of the protective layer 170 away from the One side of the active layer 130 , the side of the edge of the first region away from the active layer 130 , and the inner sidewall of the passivation layer 170 .
  • a front electrode layer is formed on the side of the first region away from the active layer, and the upper surface of the front electrode layer on the first region is lower than the upper surface of the protective layer.
  • the front electrode layer is also formed on a side of the current limiting insulating layer away from the protection layer.
  • the electrical isolation of the protective layer can prevent the current limiting insulating layer from forming. Layer breakdown occurs due to the increase of charge, thereby avoiding the reduction of the aging life of the semiconductor light-emitting device or the leakage and burning of the semiconductor light-emitting device.
  • a back electrode layer 101 is formed on the surface of the semiconductor substrate layer 100 facing away from the active layer 130 .
  • the method for manufacturing a high-reliability and low-defect semiconductor light-emitting device further includes : Cleave the front electrode layer, current confinement insulating layer, protective layer, doped semiconductor contact layer, upper confinement layer, upper waveguide layer, active layer, lower waveguide layer, lower confinement layer and semiconductor substrate layer along the cutting area.
  • it also includes: forming an anti-reflection film on the surface of the front cavity; forming a reflection film on the surface of the rear cavity.

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Abstract

一种高可靠性低缺陷半导体发光器件及其制备方法，高可靠性低缺陷半导体发光器件包括：半导体衬底层（100）；位于半导体衬底层（100）上的有源层（130）；位于有源层（130）背离半导体衬底层（100）一侧的掺杂半导体接触层（160），掺杂半导体接触层（160）包括第一区和包围第一区的边缘区；位于掺杂半导体接触层（160）的边缘区背离有源层（130）一侧的保护层（170）；正面电极层（190），位于第一区背离有源层（130）一侧，第一区上的正面电极层（190）的上表面低于保护层（170）的上表面。半导体发光器件兼顾可靠性高和降低工艺控制成本。

Description

一种高可靠性低缺陷半导体发光器件及其制备方法
本申请要求在2022年03月04日提交中国专利局、申请号为202210205786.5、发明名称为“一种高可靠性低缺陷半导体发光器件及其制备方法”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及半导体技术领域，具体涉及一种高可靠性低缺陷半导体发光器件及其制备方法。
背景技术
半导体发光器件是以一定的半导体材料作为工作物质而产生受激发射作用的器件，其工作原理是：通过一定的激励方式在半导体材料的能带(导带与价带)之间或者在半导体材料的能带与杂质(受主或施主)能级之间实现非平衡载流子的粒子数反转，当处于粒子数反转状态的大量电子与空穴复合时便产生受激发射作用，因半导体发光器件体积小、电光转换效率高被广泛的使用。
现有对半导体发光器件表面的缺陷优化技术难以兼顾提高可靠性和降低工艺控制成本的问题。
发明内容
因此，本申请要解决的技术问题在于克服现有技术难以兼顾可靠性高和降低工艺控制成本的问题，从而提供一种高可靠性低缺陷半导体发光器件及其制备方法。
本申请提供一种高可靠性低缺陷半导体发光器件，包括：半导体衬底层；位于所述半导体衬底层上的有源层；位于所述有源层背离所述半导体衬底层一侧的掺杂半导体接触层，所述掺杂半导体接触层包括第一区和包围所述第一区的边缘区；位于所述掺杂半导体接触层的边缘区背离所述有源层一侧的保护层；正面电极层，位于所述第一区背离所述有源层的一侧，所述第一区上的正面电极层的上表面低于所述保护层的上表面。
可选地，所述保护层的上表面与位于所述第一区上的所述正面电极层的上表面的高度差为0.05μm-5μm。
可选地，所述保护层在垂直于所述半导体衬底层表面的方向上的厚度为0.1μm-5μm。
可选地，所述高可靠性低缺陷半导体发光器件具有相对设置的前腔面和后腔面，所述前腔面和后腔面均暴露出有源层侧壁表面和掺杂半导体接触层的侧壁表面；所述保护层包括相对设置的第一子保护区和第二子保护区，第一子保护区和第二子保护区沿出光方向排布，所述第一子保护区的外侧壁与所述前腔面暴露出的有源层侧壁表面和所述前腔面暴露出的掺杂半导体接触层的侧壁表面对齐，所述第二子保护区的外侧壁与后腔面暴露出的有源层侧壁表面和后腔面暴露出的掺杂半导体接触层的侧壁表面对齐。
可选地，所述掺杂半导体接触层的材料为掺杂有第一导电离子的第一主体半导体材料；所述保护层的材料为未掺杂的第二主体半导体材料，或者，所述保护层的材料为掺杂有第二导电粒子的第二主体半导体材料，所述第二导电粒子的导电类型与所述第一导电离子的导电类型相反；或者，述保护层的材料为掺杂有第二导电粒子的第二主体半导体材料，所述第二导电粒子的导电类型与所述第一导电离子的导电类型相同，且所述第二导电粒子的掺杂浓度小于所述第 一导电离子的掺杂浓度。
当所述第二导电粒子的导电类型与所述第一导电离子的导电类型相同时，所述第二导电粒子的掺杂浓度为所述第一导电离子的掺杂浓度的10 -6倍～10 -1倍。
可选地，所述第二主体半导体材料与所述第一主体半导体材料的平均晶格失配小于或等于1％。
可选地，所述第二主体半导体材料与所述第一主体半导体材料相同。
可选地，所述保护层为单层结构或多层结构。
可选地，当所述半导体衬底层为GaAs衬底时，所述保护层的材料为掺杂或者非掺杂的GaAs，或者，所述保护层的材料为掺杂或非掺杂的AlGaAs，或者，所述保护层的材料为掺杂或者非掺杂的InGaP；或者，所述保护层的材料为掺杂或者非掺杂的InGaAsP，或者，所述保护层的材料为掺杂或者非掺杂的InGaAs；当所述半导体衬底层的材料为InP衬底时，所述保护层的材料为掺杂或者非掺杂的InGaAsP，或者，所述保护层的材料为掺杂或者非掺杂的InGaAlAs，或者，所述保护层的材料为掺杂或者非掺杂的InGaAs，或者，所述保护层的材料为掺杂或者非掺杂的InAlAs，或者，所述保护层的材料为掺杂或者非掺杂的InP；当所述半导体衬底层的材料为GaN衬底时，所述保护层的材料为掺杂或者非掺杂的AlGaN，或者，所述保护层的材料为掺杂或者非掺杂的GaN，或者，所述保护层的材料为掺杂或者非掺杂的InAlGaN。
可选地，所述正面电极层还位于所述保护层背离所述掺杂半导体接触层一侧；所述高可靠性低缺陷半导体发光器件还包括：电流限制绝缘层，所述电流限制绝缘层位于所述保护层上的正面电极层和所述保护层之间以及第一区的边缘背离所述有源层的一侧。
可选地，所述掺杂半导体接触层包括第一子掺杂半导体层和位于所述第一子掺杂半导体层背离所述有源层一侧表面的第二子掺杂半导体层，所述第二子掺杂半导体层的掺杂浓度大于所述第一子掺杂半导体层的掺杂浓度。
可选地，所述第二子掺杂半导体层的掺杂浓度为所述第一子掺杂半导体层的掺杂浓度的10倍～50倍。
可选地，还包括：位于所述掺杂半导体接触层和所述有源层之间的上波导层；位于所述上波导层和所述掺杂半导体接触层之间的上限制层；位于所述有源层与半导体衬底层之间的下波导层，位于所述下波导层与半导体衬底层之间的下限制层；位于所述半导体衬底层背离所述有源层一侧表面的背面电极层。
本申请还提供一种高可靠性低缺陷半导体发光器件的制备方法，包括：提供半导体衬底层；在所述半导体衬底层上形成有源层；在所述有源层背离所述半导体衬底层的一侧形成掺杂半导体接触层，所述掺杂半导体接触层包括第一区和包围所述第一区的边缘区；在所述掺杂半导体接触层的边缘区背离所述有源层一侧形成保护层；在所述第一区背离所述有源层的一侧形成正面电极层，所述第一区上的正面电极层的上表面低于所述保护层的上表面。
可选地，形成所述保护层的步骤包括：在所述第一区和边缘区背离所述有源层的一侧外延生长初始保护层；刻蚀去除第一区上的初始保护层，形成暴露出第一区表面的保护层。
可选地，所述掺杂半导体接触层和所述初始保护层在一道外延工序中先后形成。
可选地，在形成所述正面电极层之前，形成电流限制绝缘层，所述电流限制绝缘层位于保护层和部分第一区边缘背离所述有源层的一侧；在形成所述正面电极层的步骤中，所述正面电 极层还形成在电流限制绝缘层背离所述保护层的一侧。
可选地，形成所述掺杂半导体接触层的步骤包括：在所述有源层背离所述半导体衬底层的一侧形成第一子掺杂半导体层；在所述第一子掺杂半导体层背离所述有源层的一侧表面形成第二子掺杂半导体层，所述第二子掺杂半导体层的掺杂浓度大于所述第一子掺杂半导体层的掺杂浓度。
可选地，形成正面电极层之前，第一区的数量为若干个，不同的第一区周围的边缘区之间具有切割区；所述高可靠性低缺陷半导体发光器件的制备方法还包括：沿切割区解理正面电极层、电流限制绝缘层、保护层、掺杂半导体接触层、有源层和半导体衬底层。
本申请技术方案具有以下有益效果：
本申请技术方案提供的高可靠性低缺陷半导体发光器件，包括保护层，保护层位于所述掺杂半导体接触层的边缘区背离所述有源层的一侧，所述保护层用于将掺杂半导体接触层的边缘区垫高，这样使得所述第一区上的正面电极层的上表面低于所述保护层的上表面。由于第一区上的正面电极层的上表面低于所述保护层的上表面，保护层对第一区上的正面电极层进行保护。因此保护层能避免半导体发光器件制备工程中受到外力产生划伤及污染缺陷；其次，保护层的引入增加了保护层上的正面电极层到有源层的距离，这大大降低了在半导体发光器件的腔面和侧面产生的解理缺陷对有源层的影响。即使正面电极层的少量材料延伸至半导体发光器件的部分腔面上，但是保护层的存在能避免正面电极层的材料延伸至有源层，这降低了正面电极层的材料对腔面的镀膜遮挡，减少了腔面光学灾变损伤。综上，提高了半导体发光器件的可靠性。其次，设置保护层较为容易实现，技术难度降低，且成本较低。
可选地，当所述第二导电粒子的导电类型与所述第一导电离子的导电类型相反时，这样使得掺杂半导体接触层和保护层之间形成电隔离，使得掺杂半导体接触层的边缘区的电流得到限制。当所述第二导电粒子的导电类型与所述第一导电离子的导电类型相同时，由于所述第二导电粒子的掺杂浓度小于所述第一导电离子的掺杂浓度，所述保护层不易导电，保护层对掺杂半导体接触层的边缘区的电流在一定程度起到限制作用。
可选地，所述第二导电粒子的掺杂浓度为所述第一导电离子的掺杂浓度的10 -6倍～10 -1倍。这样使得保护层提供了附加的电绝缘作用，这样使得掺杂半导体接触层的边缘区的电流得到电流限制绝缘层和保护层双重限制保障。
可选地，掺杂半导体接触层的材料为掺杂有第一导电离子的第一主体半导体材料；所述保护层的材料为未掺杂的第二主体半导体材料，或者，所述保护层的材料为掺杂有第二导电粒子的第二主体半导体材料。所述第二主体半导体材料与所述第一主体半导体材料的平均晶格失配小于等于1％，这样使得掺杂半导体接触层和保护层之间界面处的应力降低，掺杂半导体接触层和保护层的界面晶格匹配度高，这样使得保护层容易在掺杂半导体接触层上形成。
可选地，掺杂半导体接触层包括第一子掺杂半导体层和位于所述第一子掺杂半导体层背离所述有源层一侧表面的第二子掺杂半导体层，所述第二子掺杂半导体层的掺杂浓度大于所述第一子掺杂半导体层的掺杂浓度。由于第二子掺杂半导体层的掺杂浓度较高，因此第二子掺杂半导体层和正面电极层的接触电阻降低。由于第一子掺杂半导体层的掺杂浓度较低，且第二子掺杂半导体层相对于第一子掺杂半导体层远离有源层，因此掺杂半导体接触层的掺杂离子对有源层发出的光的吸收损耗影响降低。
本申请技术方案提供的高可靠性低缺陷半导体发光器件的制备方法，在所述掺杂半导体接触层的边缘区背离所述有源层一侧形成保护层，所述保护层用于将掺杂半导体接触层的边缘区垫高，这样使得所述第一区上的正面电极层的上表面低于所述保护层的上表面。由于第一区上的正面电极层的上表面低于所述保护层的上表面，保护层对第一区上的正面电极层进行保护。因此保护层能避免半导体发光器件制备工程中受到外力产生划伤及污染缺陷；其次，保护层的引入增加了保护层上的正面电极层到有源层的距离，这大大降低了在半导体发光器件的腔面和侧面产生的解理缺陷对有源层的影响。即使正面电极层的少量材料延伸至半导体发光器件的部分腔面上，但是保护层的存在能避免正面电极层的材料延伸至有源层，这降低了正面电极层的材料对腔面的镀膜遮挡，减少了腔面光学灾变损伤。综上，提高了半导体发光器件的可靠性。其次，设置保护层较为容易实现，技术难度降低，且成本较低。
可选地，所述掺杂半导体接触层和所述初始保护层在一道外延工序中先后形成，简化了工艺。且由于掺杂半导体接触层和所述初始保护层的形成是连续的，这样在掺杂半导体接触层和所述初始保护层之间避免引入缺陷，使得保护层和掺杂半导体接触层的边缘区之间的缺陷降低，这样避免影响载流子迁移率，避免导致器件电阻电压升高。
可选地，即使电流限制绝缘层在形成之前，保护层的上表面具有缺陷，保护层上的电流限制绝缘层在形成过程中产生层错，但是保护层的电隔离作用能避免电流限制绝缘层由于电荷增加产生击穿现象，避免半导体发光器件老化寿命降低或漏电烧毁。
附图说明
为了更清楚地说明本申请具体实施方式或现有技术中的技术方案，下面将对具体实施方式或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图是本申请的一些实施方式，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本申请一实施例的高可靠性低缺陷半导体发光器件的结构示意图；
图2至图6为本申请另一实施例中高可靠性低缺陷半导体发光器件制备过程的结构图。
具体实施方式
随着大功率的半导体发光器件的市场及应用不断拓展，用户对于其高可靠性性能以及成本降低的这两个因素的要求促使厂家更加关注大功率半导体发光器件在长期运行中的抗失效能力。半导体发光器件的失效通常是源于在工艺制备过程或封装过程中在晶圆表面引入污染或划痕缺陷，以及在芯片解理镀膜封装过程中芯片腔面靠近表面的解理缺陷。表面的缺陷导致介质膜在沉积过程中产生层错，如该类异常发生在发光区附近则会影响载流子迁移率导致器件电阻电压升高，或介质层电荷增加产生介质击穿现象，从而使半导体发光器件老化寿命降低或漏电烧毁。晶圆表面缺陷还导致芯片的电流注入区封装缺陷导致芯片局部温度高，应力大，从而引起有源材料失效。腔面和侧面靠近表面的解理缺陷导致腔面灾变损伤，从而引起封装过程旁路漏电烧毁。因此，通常通过外延生长调整，晶圆制备，腔面镀膜和封装过程的工艺严格控制来提升器件可靠性。但上述各项技术均会带来技术复杂度，工艺稳定性的降低，以及工艺生产成本的上升等缺陷。
下面将结合附图对本申请的技术方案进行清楚、完整地描述，显然，所描述的实施例是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没 有做出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
在本申请的描述中，需要说明的是，术语“中心”、“上”、“下”、“左”、“右”、“竖直”、“水平”、“内”、“外”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本申请和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本申请的限制。此外，术语“第一”、“第二”、“第三”仅用于描述目的，而不能理解为指示或暗示相对重要性。
此外，下面所描述的本申请不同实施方式中所涉及的技术特征只要彼此之间未构成冲突就可以相互结合。
实施例1
本申请一实施例提供一种高可靠性低缺陷半导体发光器件，参考图1，包括：
半导体衬底层100；
位于所述半导体衬底层上的有源层130；
位于所述有源层130背离所述半导体衬底层100一侧的掺杂半导体接触层160，所述掺杂半导体接触层160包括第一区和包围所述第一区的边缘区；
位于所述掺杂半导体接触层160的边缘区背离所述有源层130一侧的保护层170；
正面电极层190，位于所述第一区背离所述有源层130的一侧，所述第一区上的正面电极层190的上表面低于所述保护层170的上表面。
本实施例中，所述保护层170用于将掺杂半导体接触层160的边缘区垫高，这样使得所述第一区上的正面电极层190的上表面低于所述保护层170的上表面。由于第一区上的正面电极层190的上表面低于所述保护层170的上表面，保护层对第一区上的正面电极层190进行保护。因此保护层170能避免半导体发光器件制备工程中受到外力产生划伤及污染缺陷；其次，保护层170的引入增加了保护层170上的正面电极层190到有源层的距离，这大大降低了在半导体发光器件的腔面和侧面产生的解理缺陷对有源层的影响。即使正面电极层190的少量材料延伸至半导体发光器件的部分腔面上，但是保护层170的存在能避免正面电极层190的材料延伸至有源层130，这降低了正面电极层190的材料对腔面的镀膜遮挡，减少了腔面光学灾变损伤。综上，提高了半导体发光器件的可靠性。其次，设置保护层170较为容易实现，技术难度降低，且成本较低。
在一个实施例中，所述保护层170的上表面与位于所述第一区上的所述正面电极层190的上表面的高度差为0.05μm-5μm，例如0.05μm、0.1μm、0.5μm、2μm、3μm、4μm或5μm。若所述保护层170的上表面与位于所述第一区上的所述正面电极层190的上表面的高度差小于0.05μm，则所述保护层170对第一区和有源层130的保护作用较弱；若保护层170的上表面与位于所述第一区上的所述正面电极层190的上表面的高度差大于5μm，则会使得半导体发光器件的高度过高，且不用于小型化。
在一个实施例中，所述保护层170在垂直于所述半导体衬底层100表面的方向上的厚度为0.1μm-5μm，例如0.1μm、0.5μm、2μm、3μm、4μm或5μm。若保护层170在垂直于所述半导体衬底层100表面的方向上的厚度过小，则所述保护层170对第一区和有源层130的保护作用较弱；若保护层170在垂直于所述半导体衬底层100表面的方向上的厚度过大，则会使得半导体发光器件的高度过高，且不用于小型化。
所述保护层170为环状结构。保护层170不设置在第一区的上方。
所述高可靠性低缺陷半导体发光器件具有相对设置的前腔面和后腔面，所述前腔面和后腔面均暴露出有源层130侧壁表面和掺杂半导体接触层160的侧壁表面；所述保护层170包括相对设置的第一子保护区和第二子保护区，第一子保护区和第二子保护区沿出光方向排布，所述第一子保护区的外侧壁与所述前腔面暴露出的有源层130侧壁表面和所述前腔面暴露出的掺杂半导体接触层160的侧壁表面对齐，所述第二子保护区的外侧壁与后腔面暴露出的有源层130侧壁表面和后腔面暴露出的掺杂半导体接触层160的侧壁表面对齐。
所述保护层170还包括相对设置的第三子保护区和第四子保护区，第三子保护区分别与第一子保护区和第二子保护区连接，第四子保护区分别与第一子保护区和第二子保护区连接。
所述保护层170的材料为未掺杂的第二主体半导体材料，或者，所述保护层170的材料为掺杂有第二导电粒子的第二主体半导体材料，所述第二导电粒子的导电类型与所述第一导电离子的导电类型相反；或者，述保护层170的材料为掺杂有第二导电粒子的第二主体半导体材料，所述第二导电粒子的导电类型与所述第一导电离子的导电类型相同，且所述第二导电粒子的掺杂浓度小于所述第一导电离子的掺杂浓度。
当所述第二导电粒子的导电类型与所述第一导电离子的导电类型相反时，这样使得掺杂半导体接触层160和保护层170之间形成电隔离，使得掺杂半导体接触层160的边缘区的电流得到限制。在一个具体的实施例中，掺杂半导体接触层160的导电类型为N型，所述保护层170的导电类型为P型。
当所述第二导电粒子的导电类型与所述第一导电离子的导电类型相同时，由于所述第二导电粒子的掺杂浓度小于所述第一导电离子的掺杂浓度，所述保护层170不易导电，保护层170对掺杂半导体接触层160的边缘区的电流在一定程度起到限制作用。
在一个实施例中，所述第二主体半导体材料与所述第一主体半导体材料的平均晶格失配小于或等于1％，这样使得掺杂半导体接触层160和保护层170之间界面处的应力降低，掺杂半导体接触层160和保护层170的界面晶格匹配度高，这样使得保护层170容易在掺杂半导体接触层上形成。
进一步地，在一个实施例中，所述第二主体半导体材料与所述第一主体半导体材料相同。所述掺杂半导体接触层160和保护层170采用一致的主体半导体材料，这样使得掺杂半导体接触层160和保护层170之间界面处的进一步应力降低，掺杂半导体接触层160和保护层170的界面晶格匹配度进一步提高。
所述保护层170为单层结构或多层结构。
在一个实施例中，所述保护层170的材料为P型半导体保护层、N型半导体保护层或本征半导体保护层。具体地，当所述半导体衬底层100为GaAs衬底时，所述保护层170的材料为掺杂或者非掺杂的GaAs，或者，所述保护层170的材料为掺杂或非掺杂的AlGaAs，或者，所述保护层170的材料为掺杂或者非掺杂的InGaP，或者，所述保护层170的材料为掺杂或者非掺杂的InGaAsP，或者，所述保护层的材料为掺杂或者非掺杂的InGaAs；当所述半导体衬底层100的材料为InP衬底时，所述保护层170的材料为掺杂或者非掺杂的InGaAsP，或者，所述保护层170的材料为掺杂或者非掺杂的InP，或者，所述保护层的材料为掺杂或者非掺杂的InGaAlAs，或者，所述保护层的材料为掺杂或者非掺杂的InGaAs，或者，所述保护层的材料 为掺杂或者非掺杂的InAlAs；当所述半导体衬底层100的材料为GaN衬底时，所述保护层170的材料为掺杂或者非掺杂的AlGaN，或者，所述保护层170的材料为掺杂或者非掺杂的GaN，或者，所述保护层170的材料为掺杂或者非掺杂的InAlGaN。
当保护层170为多层结构时，所述保护层170包括第一子保护层至第N子保护层，第k+1子保护层位于第k子保护层背离半导体衬底层100的一侧，N为大于或等于2的整数，k为大于或等于1且小于或等于N的整数。
在一个具体的实施例中，第k+1子保护层位于第k子保护层的导电类型相反，第一子保护层的导电类型和掺杂半导体接触层的导电类型相反。在一个实施例中，第一子保护层至第N子保护层均与掺杂半导体接触层的导电类型相反。
本实施例中，所述正面电极层190还位于所述保护层170背离所述掺杂半导体接触层160一侧；所述高可靠性低缺陷半导体发光器件还包括：电流限制绝缘层180，所述电流限制绝缘层180位于所述保护层170上的正面电极层190和所述保护层170之间。所述电流限制绝缘层180的材料包括氧化硅。
进一步，所述第二导电粒子的掺杂浓度为所述第一导电离子的掺杂浓度的10 -6倍～10 -1倍，例如10 -6倍、10 -5倍、10 -4倍、10 -3倍、10 -2倍或10 -1倍。这样使得保护层170提供了附加的电绝缘作用，这样使得掺杂半导体接触层160的边缘区的电流得到电流限制绝缘层180和保护层170双重限制保障。
进一步，所述电流限制绝缘层180位于所述保护层170上的正面电极层190和所述保护层170之间以及第一区的边缘背离所述有源层130的一侧，电流限制绝缘层180还覆盖保护层170的内侧壁。此时，第一区未被所述电流限制绝缘层180覆盖的区域作为电流注入区。好处在于：在给电流注入区注入电流时，由于电流注入区距离保护层170和掺杂半导体接触层160的边缘区之间的界面处有一定的距离，这样使得保护层170和掺杂半导体接触层160的边缘区之间的界面难以形成漏电路径。
当电流限制绝缘层180还位于第一区的边缘背离所述有源层130的一侧时，正面电极层190还覆盖第一区上的电流限制绝缘层180。
电流限制绝缘层180覆盖第一区的边缘的宽度指的是：电流限制绝缘层180覆盖第一区的边缘的任意单侧的宽度。
本实施例中，所述掺杂半导体接触层160包括第一子掺杂半导体层161和位于所述第一子掺杂半导体层161背离所述有源层130一侧表面的第二子掺杂半导体层162，所述第二子掺杂半导体层162的掺杂浓度大于所述第一子掺杂半导体层161的掺杂浓度。由于第二子掺杂半导体层162的掺杂浓度较高，因此第二子掺杂半导体层162和正面电极层190的接触电阻降低。由于第一子掺杂半导体层161的掺杂浓度较低，且第二子掺杂半导体层162相对于第一子掺杂半导体层161远离有源层130，因此掺杂半导体接触层160的掺杂离子对有源层130发出的光的吸收损耗影响降低。
在一个实施例中，所述第二子掺杂半导体层162的掺杂浓度为所述第一子掺杂半导体层161的掺杂浓度的10倍～50倍。使得在降低第二子掺杂半导体层162和正面电极层190的接触电阻和降低光的吸收损耗影响之间均得到较好的兼顾。
在其他实施例中，掺杂半导体接触层可以为单层结构。掺杂半导体接触层的第一区用于和 正面电极层接触，从而降低接触电极。
所述高可靠性低缺陷半导体发光器件还包括：位于所述掺杂半导体接触层160和所述有源层130之间的上波导层140；位于所述上波导层140和所述掺杂半导体接触层160之间的上限制层150；位于所述半导体衬底层100和所述有源层130之间的下波导层120；位于所述下波导层120和所述半导体衬底层100之间的下限制层110；位于所述半导体衬底层100背离所述有源层130一侧表面的背面电极层101。
本实施例中，当高可靠性低缺陷半导体发光器件与热沉焊接在一起时，保护层170增加了在焊接过程中焊料与有源层的距离，降低了焊料隆起导致的件漏电烧毁失效，从而提高半导体发光器件的可靠性。
本实施例中，还包括：覆盖前腔面的增透膜；覆盖后腔面的反射膜。
实施例2
本实施例提供一种高可靠性低缺陷半导体发光器件的制备方法，参考图1，包括：
S1:提供半导体衬底层；
S2:在所述半导体衬底层上形成有源层；
S3:在所述有源层背离所述半导体衬底层的一侧形成掺杂半导体接触层，所述掺杂半导体接触层包括第一区和包围所述第一区的边缘区；
S4:在所述掺杂半导体接触层的边缘区背离所述有源层一侧形成保护层；
S5:在所述第一区背离所述有源层的一侧形成正面电极层，所述第一区上的正面电极层的上表面低于所述保护层的上表面。
参考图2，提供半导体衬底层100；在半导体衬底层100上形成下限制层110；在下限制层110背离半导体衬底层100的一侧形成下波导层120；在下波导层背离半导体衬底层100的一侧形成有源层130；在有源层130背离半导体衬底层100的一侧形成上波导层140；在上波导层140背离有源层130的一侧形成上限制层150；在上限制层150背离有源层130的一侧形成掺杂半导体接触层160。
本实施例中，形成所述掺杂半导体接触层160的步骤包括：在所述有源层130背离所述半导体衬底层100的一侧形成第一子掺杂半导体层161；在所述第一子掺杂半导体层161背离所述有源层130的一侧表面形成第二子掺杂半导体层162，所述第二子掺杂半导体层162的掺杂浓度大于所述第一子掺杂半导体层161的掺杂浓度。关于第一子掺杂半导体层161和第二子掺杂半导体层162的参数描述参照前述实施例。
在其他实施例中，掺杂半导体接触层为单层结构。
在步骤S4中，在所述掺杂半导体接触层的边缘区背离所述有源层一侧形成保护层170。形成所述保护层170的步骤包括：参考图2，在所述第一区和边缘区背离所述有源层130的一侧外延生长初始保护层17；参考图3，刻蚀去除第一区上的初始保护层17，形成暴露出第一区表面的保护层170。
所述初始保护层17为单层结构或者多层结构。
当初始保护层17为多层结构时，初始保护层17从下至上包括第一子初始保护层至第N子初始保护层；刻蚀去除第一区上的初始保护层17，使得第k子初始保护层形成第k子保护层，使得第k+1子初始保护层形成第k+1子初始保护层。
在一个实施例中，当初始保护层17为多层结构时，在刻蚀去除第一区上的初始保护层17的步骤中，任意第k+1子初始保护层的材料与第一子初始保护层的材料的刻蚀选择比大于或等于5，例如5、8、10、15或20，第一子初始保护层的材料与掺杂半导体接触层160的材料的刻蚀选择比大于或等于5，例如5、8、10、15或20。
第一子初始保护层的材料与第二子掺杂半导体层162的材料的刻蚀选择比大于或等于5。
形成所述初始保护层的工艺包括工艺金属有机化合物化学气相沉积工艺(MOCVD)和分子束外延工艺(MEB)。
在一个实施例中，所述掺杂半导体接触层160和所述初始保护层17在一道外延工序中先后形成，从而简化了工艺。由于掺杂半导体接触层160和所述初始保护层17的形成是连续的，这样在掺杂半导体接触层160和所述初始保护层17之间避免引入缺陷，使得保护层170和掺杂半导体接触层160的边缘区之间的缺陷降低，这样避免影响载流子迁移率，从而避免导致器件电阻电压升高。
掺杂半导体接触层160和所述初始保护层17在同一个腔室中连续形成。
关于保护层的具体参数描述参照实施例1，不再详述。
参考图4，形成电流限制绝缘层180，所述电流限制绝缘层180位于保护层170背离所述有源层130的一侧，进一步地，所述电流限制绝缘层180位于保护层170背离所述有源层130的一侧、第一区的边缘背离所述有源层130的一侧以及保护层170的内侧壁。
参考图5，在所述第一区背离所述有源层的一侧形成正面电极层，所述第一区上的正面电极层的上表面低于所述保护层的上表面。
在形成所述正面电极层的步骤中，所述正面电极层还形成在电流限制绝缘层背离所述保护层的一侧。
本实施例中，即使电流限制绝缘层在形成之前，保护层的上表面具有缺陷，保护层上的电流限制绝缘层在形成过程中产生层错，但是保护层的电隔离作用能避免电流限制绝缘层由于电荷增加产生击穿现象，从而避免半导体发光器件老化寿命降低或漏电烧毁。
参考图6，在半导体衬底层100背离有源层130的一侧表面形成背面电极层101。
本实施例中，形成正面电极层之前，第一区的数量为若干个，不同的第一区周围的边缘区之间具有切割区；所述高可靠性低缺陷半导体发光器件的制备方法还包括：沿切割区解理正面电极层、电流限制绝缘层、保护层、掺杂半导体接触层、上限制层、上波导层、有源层、下波导层、下限制层和半导体衬底层。
本实施例中，还包括：在前腔面形成增透膜；在后腔面形成反射膜。
显然，上述实施例仅仅是为清楚地说明所作的举例，而并非对实施方式的限定。对于所属领域的普通技术人员来说，在上述说明的基础上还可以做出其它不同形式的变化或变动。这里无需也无法对所有的实施方式予以穷举。而由此所引伸出的显而易见的变化或变动仍处于本申请的保护范围之中。

Claims (20)

  1. 一种高可靠性低缺陷半导体发光器件，其特征在于，包括：
    半导体衬底层；
    位于所述半导体衬底层上的有源层；
    位于所述有源层背离所述半导体衬底层一侧的掺杂半导体接触层，所述掺杂半导体接触层包括第一区和包围所述第一区的边缘区；
    位于所述掺杂半导体接触层的边缘区背离所述有源层一侧的保护层；
    正面电极层，位于所述第一区背离所述有源层的一侧，所述第一区上的正面电极层的上表面低于所述保护层的上表面。
  2. 根据权利要求1所述的高可靠性低缺陷半导体发光器件，其特征在于，所述保护层的上表面与位于所述第一区上的所述正面电极层的上表面的高度差为0.05μm-5μm。
  3. 根据权利要求1或2所述的高可靠性低缺陷半导体发光器件，其特征在于，所述保护层在垂直于所述半导体衬底层表面的方向上的厚度为0.1μm-5μm。
  4. 根据权利要求1所述的高可靠性低缺陷半导体发光器件，其特征在于，所述高可靠性低缺陷半导体发光器件具有相对设置的前腔面和后腔面，所述前腔面和后腔面均暴露出有源层侧壁表面和掺杂半导体接触层的侧壁表面；所述保护层包括相对设置的第一子保护区和第二子保护区，第一子保护区和第二子保护区沿出光方向排布，所述第一子保护区的外侧壁与所述前腔面暴露出的有源层侧壁表面和所述前腔面暴露出的掺杂半导体接触层的侧壁表面对齐，所述第二子保护区的外侧壁与后腔面暴露出的有源层侧壁表面和后腔面暴露出的掺杂半导体接触层的侧壁表面对齐。
  5. 根据权利要求1所述的高可靠性低缺陷半导体发光器件，其特征在于，所述掺杂半导体接触层的材料为掺杂有第一导电离子的第一主体半导体材料；
    所述保护层的材料为未掺杂的第二主体半导体材料，或者，所述保护层的材 料为掺杂有第二导电粒子的第二主体半导体材料，所述第二导电粒子的导电类型与所述第一导电离子的导电类型相反；或者，述保护层的材料为掺杂有第二导电粒子的第二主体半导体材料，所述第二导电粒子的导电类型与所述第一导电离子的导电类型相同，且所述第二导电粒子的掺杂浓度小于所述第一导电离子的掺杂浓度。
  6. 根据权利要求5所述的高可靠性低缺陷半导体发光器件，其特征在于，当所述第二导电粒子的导电类型与所述第一导电离子的导电类型相同时，所述第二导电粒子的掺杂浓度为所述第一导电离子的掺杂浓度的10 -6倍～10 -1倍。
  7. 根据权利要求5所述的高可靠性低缺陷半导体发光器件，其特征在于，所述第二主体半导体材料与所述第一主体半导体材料的平均晶格失配小于或等于1％。
  8. 根据权利要求7所述的高可靠性低缺陷半导体发光器件，其特征在于，所述第二主体半导体材料与所述第一主体半导体材料相同。
  9. 根据权利要求1所述的高可靠性低缺陷半导体发光器件，其特征在于，所述保护层为单层结构或多层结构。
  10. 根据权利要求1或9所述的高可靠性低缺陷半导体发光器件，其特征在于，当所述半导体衬底层为GaAs衬底时，所述保护层的材料为掺杂或者非掺杂的GaAs，或者，所述保护层的材料为掺杂或非掺杂的AlGaAs，或者，所述保护层的材料为掺杂或者非掺杂的InGaP；或者，所述保护层的材料为掺杂或者非掺杂的InGaAsP，或者，所述保护层的材料为掺杂或者非掺杂的InGaAs；
    当所述半导体衬底层的材料为InP衬底时，所述保护层的材料为掺杂或者非掺杂的InGaAsP，或者，所述保护层的材料为掺杂或者非掺杂的InGaAlAs，或者，所述保护层的材料为掺杂或者非掺杂的InGaAs，或者，所述保护层的材料为掺杂或者非掺杂的InAlAs，或者，所述保护层的材料为掺杂或者非掺杂的InP；
    当所述半导体衬底层的材料为GaN衬底时，所述保护层的材料为掺杂或者非掺杂的AlGaN，或者，所述保护层的材料为掺杂或者非掺杂的GaN，或者，所述 保护层的材料为掺杂或者非掺杂的InAlGaN。
  11. 根据权利要求1所述的高可靠性低缺陷半导体发光器件，其特征在于，所述正面电极层还位于所述保护层背离所述掺杂半导体接触层一侧；
    所述高可靠性低缺陷半导体发光器件还包括：电流限制绝缘层，所述电流限制绝缘层位于所述保护层上的正面电极层和所述保护层之间以及第一区的边缘背离所述有源层的一侧。
  12. 根据权利要求1所述的高可靠性低缺陷半导体发光器件，其特征在于，所述掺杂半导体接触层包括第一子掺杂半导体层和位于所述第一子掺杂半导体层背离所述有源层一侧表面的第二子掺杂半导体层，所述第二子掺杂半导体层的掺杂浓度大于所述第一子掺杂半导体层的掺杂浓度。
  13. 根据权利要求12所述的高可靠性低缺陷半导体发光器件，其特征在于，所述第二子掺杂半导体层的掺杂浓度为所述第一子掺杂半导体层的掺杂浓度的10倍～50倍。
  14. 根据权利要求1所述的高可靠性低缺陷半导体发光器件，其特征在于，还包括：位于所述掺杂半导体接触层和所述有源层之间的上波导层；位于所述上波导层和所述掺杂半导体接触层之间的上限制层；位于所述有源层与半导体衬底层之间的下波导层，位于所述下波导层与半导体衬底层之间的下限制层；位于所述半导体衬底层背离所述有源层一侧表面的背面电极层。
  15. 一种高可靠性低缺陷半导体发光器件的制备方法，其特征在于，包括：
    提供半导体衬底层；
    在所述半导体衬底层上形成有源层；
    在所述有源层背离所述半导体衬底层的一侧形成掺杂半导体接触层，所述掺杂半导体接触层包括第一区和包围所述第一区的边缘区；
    在所述掺杂半导体接触层的边缘区背离所述有源层一侧形成保护层；
    在所述第一区背离所述有源层的一侧形成正面电极层，所述第一区上的正面 电极层的上表面低于所述保护层的上表面。
  16. 根据权利要求15所述的高可靠性低缺陷半导体发光器件的制备方法，其特征在于，形成所述保护层的步骤包括：在所述第一区和边缘区背离所述有源层的一侧外延生长初始保护层；刻蚀去除第一区上的初始保护层，形成暴露出第一区表面的保护层。
  17. 根据权利要求16所述的高可靠性低缺陷半导体发光器件的制备方法，其特征在于，所述掺杂半导体接触层和所述初始保护层在一道外延工序中先后形成。
  18. 根据权利要求15所述的高可靠性低缺陷半导体发光器件的制备方法，其特征在于，在形成所述正面电极层之前，形成电流限制绝缘层，所述电流限制绝缘层位于保护层和部分第一区边缘背离所述有源层的一侧；在形成所述正面电极层的步骤中，所述正面电极层还形成在电流限制绝缘层背离所述保护层的一侧。
  19. 根据权利要求15所述的高可靠性低缺陷半导体发光器件的制备方法，其特征在于，形成所述掺杂半导体接触层的步骤包括：在所述有源层背离所述半导体衬底层的一侧形成第一子掺杂半导体层；在所述第一子掺杂半导体层背离所述有源层的一侧表面形成第二子掺杂半导体层，所述第二子掺杂半导体层的掺杂浓度大于所述第一子掺杂半导体层的掺杂浓度。
  20. 根据权利要求18所述的高可靠性低缺陷半导体发光器件的制备方法，其特征在于，形成正面电极层之前，第一区的数量为若干个，不同的第一区周围的边缘区之间具有切割区；
    所述高可靠性低缺陷半导体发光器件的制备方法还包括：沿切割区解理正面电极层、电流限制绝缘层、保护层、掺杂半导体接触层、有源层和半导体衬底层。
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