WO2023164827A1 - 一种sot-mram存储单元、存储阵列、存储器及操作方法 - Google Patents

一种sot-mram存储单元、存储阵列、存储器及操作方法 Download PDF

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WO2023164827A1
WO2023164827A1 PCT/CN2022/078760 CN2022078760W WO2023164827A1 WO 2023164827 A1 WO2023164827 A1 WO 2023164827A1 CN 2022078760 W CN2022078760 W CN 2022078760W WO 2023164827 A1 WO2023164827 A1 WO 2023164827A1
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layer
sot
mram
spin
orbital
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PCT/CN2022/078760
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English (en)
French (fr)
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邢国忠
刘龙
赵雪峰
王迪
林淮
张昊
王紫崴
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中国科学院微电子研究所
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Priority to PCT/CN2022/078760 priority Critical patent/WO2023164827A1/zh
Publication of WO2023164827A1 publication Critical patent/WO2023164827A1/zh

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/18—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using Hall-effect devices

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  • the disclosure relates to the technical field of magnetic random access memory, in particular to a SOT-MRAM storage unit, a storage array, a memory and an operation method.
  • SOT-MRAM Spin-Orbit Torque Magnetic Random Access Memory, spin-orbit moment magnetic memory
  • SOT-MRAM Spin-Orbit Torque Magnetic Random Access Memory, spin-orbit moment magnetic memory
  • SOT-MRAM has a technical challenge that has not been completely overcome, that is, for SOT-MRAM with perpendicular anisotropy (PMA), its data writing needs to be assisted by an in-plane magnetic field along the current direction, which limits the integration of SOT-MRAM. , miniature and large-scale applications.
  • Existing data writing methods without external magnetic field assistance such as: structural asymmetry, exchange bias/interlayer exchange coupling to introduce built-in in-plane field, etc., all have problems of difficulty in microscale integration and poor compatibility with CMOS processes .
  • the SOT-MRAM in the prior art uses a large number of expensive heavy metal materials as the spin-orbit coupling layer, which is not conducive to further reducing the cost of the SOT-MRAM.
  • the present disclosure provides a SOT-MRAM memory cell, memory array, memory and operation method, aiming to combine orbital Hall effect, ferromagnetic material spin-orbit precession effect or planar Hall effect, competing spin Flow realizes SOT-MRAM memory cell without external magnetic field assistance.
  • a first aspect of the present disclosure provides a SOT-MRAM memory cell, comprising: a bottom electrode; a magnetic tunnel junction layer located on the bottom electrode; an orbital Hall effect layer located on the magnetic tunnel junction layer; a first transistor, a drain connected to the track Hall effect layer; and a second transistor whose drain is connected to the bottom electrode.
  • the memory cell further includes: a heavy metal layer located between the magnetic tunnel junction layer and the orbital Hall effect layer.
  • the orbital Hall effect layer and the heavy metal layer are configured to pass the write current; wherein, the orbital Hall effect layer is used to convert the write current into orbital polarized orbital current through the orbital Hall effect; the heavy metal layer is used to pass the self- Spin-orbit coupling converts the write current into a spin-polarized spin current.
  • the orbital current diffused into the heavy metal layer is transformed into a spin current under the strong spin-orbit coupling of the heavy metal layer.
  • the spin current generated by the heavy metal layer is opposite in polarity to the spin current formed by the transformation of the orbital current, forming a competing spin current, wherein the competing spin current is used to achieve deterministic magnetization switching assisted by an external magnetic field.
  • the magnetic tunnel junction layer includes: a bottom-up ferromagnetic reference layer, a non-magnetic barrier layer and a ferromagnetic free layer.
  • the ferromagnetic reference layer adopts a pinning structure, including: a bottom-up antiferromagnetic structure layer, a second space layer and a reference layer.
  • the antiferromagnetic structure layer has RKKY effect, including: the second ferromagnetic layer, the first space layer and the first ferromagnetic layer from bottom to top, and the first space layer is used for the first ferromagnetic layer and the second ferromagnetic layer.
  • An antiferromagnetic coupling is formed between the ferromagnetic layers.
  • the structure formed by the first ferromagnetic layer and the second ferromagnetic layer is a synthetic ferromagnetic structure composed of periodic Co/Pt or Co/Pd.
  • the source line is connected to the track Hall effect layer; and the bit line is respectively connected to the sources of the first transistor and the second transistor.
  • the heavy metal layer is one or more of Pt, Ta, W and Gd.
  • the ferromagnetic reference layer is any one of Co, CoFeB, Co/Pt and contains a synthetic antiferromagnetic structure
  • the bottom electrode is made of one or more materials in Pt, Ta and W
  • the layer is composed of MgO or Al 2 O 3
  • the ferromagnetic free layer is any one of Co, CoFe and CoFeB
  • the orbital Hall effect layer is composed of Cu or Cr.
  • a second aspect of the present disclosure provides a SOT-MRAM memory, including: the SOT-MRAM storage unit provided in the first aspect of the present disclosure.
  • the third aspect of the present disclosure provides a method for operating a SOT-MRAM memory, which is characterized in that it includes: controlling the voltage bias applied to the first transistor and the second transistor in the SOT-MRAM memory, and the SOT-MRAM The memory performs data writing and reading operations respectively.
  • performing a data reading operation on the SOT-MRAM memory includes: controlling the first transistor to be turned off and the second transistor to be turned on, and reading stored data in the SOT-MRAM memory through the tunnel magnetoresistance effect.
  • the data writing operation to the SOT-MRAM memory includes: controlling the first transistor to be turned on and the second transistor to be turned off, and forming a competitive spin current through the track Hall effect and the spin Hall effect to realize the SOT-MRAM memory data write.
  • a fourth aspect of the present disclosure provides an SOT-MRAM storage array, including: a plurality of SOT-MRAM storage units as provided in the first aspect of the present disclosure, wherein each SOT-MRAM storage unit is arranged periodically.
  • a fifth aspect of the present disclosure provides an SOT-MRAM memory, including: the SOT-MRAM memory array provided in the fourth aspect of the present disclosure.
  • Embodiments of the present disclosure provide a SOT-MRAM memory cell, a memory array, and a memory.
  • the memory cell converts a write current into a rail polarized rail current by configuring an orbital Hall effect layer, and spin-orbit coupling
  • the layer is set to convert the write current and the orbital current diffused into the layer into spin currents with opposite spin polarization, forming competing spin currents to realize fully electrically controlled deterministic magnetization switching without external magnetic field assistance.
  • the SOT-MRAM device has a simple structure, reduces the use of expensive heavy metal materials, and the material system is compatible with the CMOS process, which is conducive to the large-scale preparation and practical application of the SOT-MRAM device.
  • FIG. 1 schematically shows a schematic diagram of the evolution of the research background of SOT-MRAM according to an embodiment of the present disclosure
  • Fig. 2 schematically shows a schematic structural view of a SOT-MRAM storage unit according to an embodiment of the present disclosure
  • FIG. 3 schematically shows a schematic structural diagram of a magnetic tunnel junction layer according to an embodiment of the present disclosure
  • Fig. 4 schematically shows a schematic diagram of deterministic magnetization switching without external magnetic field assistance for the SOT-MRAM memory cell shown in Fig. 2;
  • FIG. 5 schematically shows a schematic structural view of a SOT-MRAM storage unit according to another embodiment of the present disclosure
  • FIG. 6 schematically shows a schematic diagram of deterministic magnetization switching without external magnetic field assistance for the SOT-MRAM memory cell shown in FIG. 5 .
  • FIG. 1 schematically shows the evolution of the research background of SOT-MRAM according to the embodiment of the present disclosure.
  • the disclosure mainly aims at the scalability of the existing SOT-MRAM without external magnetic field assisted magnetization flipping structure, the compatibility with CMOS, and the problem that the existing SOT-MRAM uses expensive heavy metal materials as the spin-orbit coupling layer.
  • the existing non-external magnetic field assisted magnetization switching mechanisms mainly include structural asymmetry (such as wedge-shaped barrier layer, ferromagnetic layer, heavy metal layer, etc.), built-in bias field (such as ferromagnetic/antiferromagnetic exchange bias , interlayer coupling, etc.), hybrid methods (e.g., STT and SOT synergy, based on magnetic domain wall motion, etc.), spin flow configurations (e.g., gradient spin flow, competitive spin flow, out-of-plane polarized spin stream, etc.) four types.
  • structural asymmetry such as wedge-shaped barrier layer, ferromagnetic layer, heavy metal layer, etc.
  • built-in bias field such as ferromagnetic/antiferromagnetic exchange bias , interlayer coupling, etc.
  • hybrid methods e.g., STT and SOT synergy, based on magnetic domain wall motion, etc.
  • spin flow configurations e.g., gradient spin flow, competitive spin flow, out-of-plane
  • Heavy metals are widely used as the spin-orbit coupling layer of SOT-MRAM due to their strong spin-orbit coupling, but heavy metals also have problems such as high price and high resistivity. Since 2018, some researchers have proposed the orbital Hall effect. Orbital current can be converted into spin current through spin-orbit coupling, which can enhance the conversion efficiency of spin current. And in light metal (such as Cu)/ferromagnetic materials, the combination of orbital Hall effect and spin-orbit coupling can achieve spin current conversion efficiency comparable to that of heavy metals.
  • the present disclosure aims at inventing a SOT-MRAM that combines orbital Hall effect, spin-orbit precession effect of ferromagnetic material or planar Hall effect, and competing spin currents to realize SOT-MRAM without external magnetic field assistance.
  • a SOT-MRAM memory cell comprising: a bottom electrode; a magnetic tunnel junction layer located on the bottom electrode; an orbital Hall effect layer located on the magnetic tunnel junction layer; a first a transistor whose drain is connected to the track Hall effect layer; and a second transistor whose drain is connected to the bottom electrode.
  • the memory cell is configured to convert the write current into a rail polarized rail flow by configuring the track Hall effect layer, and the spin-orbit coupling layer is configured to convert the write current
  • the orbital current that diffuses into this layer is transformed into a spin current with the opposite spin polarization, forming a competing spin current to realize fully electrically controlled deterministic magnetization switching without the assistance of an external magnetic field.
  • the SOT-MRAM device provided by the present disclosure has a simple structure, reduces the use of expensive heavy metal materials, and the material system is compatible with the CMOS process, which is conducive to the large-scale preparation and practical application of the SOT-MRAM device.
  • FIG. 2 schematically shows a schematic structural diagram of a SOT-MRAM storage unit according to an embodiment of the present disclosure.
  • the SOT-MRAM memory cell includes: a bottom electrode 10 from bottom to top, a magnetic tunnel junction layer 20, a heavy metal layer 30, a track Hall effect layer 40, and a first transistor 50. and the second transistor 60 , the drain of the first transistor 50 is connected to the top of the track Hall effect layer 40 , and the drain of the second transistor 60 is connected to the top of the bottom electrode 10 .
  • the magnetic tunnel junction layer 20 is a spin-orbit moment magnetic tunnel junction (SOT-MTJ).
  • the magnetic tunnel junction layer 20 includes a bottom-up ferromagnetic reference layer 201 , a non-magnetic barrier layer 202 and a ferromagnetic free layer 203 .
  • the ferromagnetic reference layer 201 adopts a pinning structure, which specifically includes: a bottom-up antiferromagnetic structure layer 2011 , a second space layer 2012 and a reference layer 2013 .
  • the antiferromagnetic structure layer 2011 has an RKKY effect, which specifically includes: a bottom-up second ferromagnetic layer 201I, a first space layer 201II, and a first ferromagnetic layer 201III.
  • the space layer 201II is used to form an antiferromagnetic coupling between the first ferromagnetic layer 201III and the second ferromagnetic layer 201I.
  • the second ferromagnetic layer 201I, the first space layer 201II and the first ferromagnetic layer 201III are a synthetic antiferromagnetic structure (SAF) realized by RKKY action.
  • SAF synthetic antiferromagnetic structure
  • the structure formed by the first ferromagnetic layer 201III and the second ferromagnetic layer 201I is specifically a synthetic ferromagnetic structure composed of periodic Co/Pt or Co/Pd.
  • the SOT-MRAM memory cell further includes: a source line SL and a bit line BL.
  • the source line SL is connected to the track Hall effect layer 40
  • the bit line BL is respectively connected to the sources of the first transistor 50 and the second transistor 60 .
  • the gates of the first transistor 50 and the second transistor 60 are respectively used for accessing bias voltages for writing and reading.
  • the track Hall effect layer 40 and the heavy metal layer 30 are configured to pass a write current.
  • the orbital Hall effect layer 40 is used to convert the write current into an orbital current polarized by the orbital magnetic moment (L) through the orbital Hall effect, and the orbital current can diffuse into the heavy metal layer 30 .
  • the heavy metal layer 30 is used to convert the write current into a spin (S) polarized spin current through spin-orbit coupling, and at the same time diffuse the orbital current into the heavy metal layer 30, under the strong spin-orbit coupling of the heavy metal layer 30 is transformed into a spin current. Its spin polarization direction is determined by the heavy metal spin-orbit coupling polarity.
  • the intrinsic spin current at the interface of the heavy metal layer 30 and the ferromagnetic free layer 203 is polarized in the opposite direction to the spin current converted from the orbital current, and the two form a competing spin current, thereby realizing the free spin current. Deterministic magnetization switching assisted by an applied magnetic field.
  • the heavy metal layer 30 is one or more of Pt, Ta, W and Gd, and its layer thickness can be set according to actual application requirements, which is not limited in the embodiments of the present disclosure.
  • the ferromagnetic reference layer 201 is any one of Co, CoFeB, Co/Pt, and a synthetic antiferromagnetic structure.
  • the bottom electrode 10 is made of one or more materials among Pt, Ta and W.
  • the non-magnetic barrier layer 202 may be composed of MgO or Al 2 O 3 .
  • the ferromagnetic free layer 203 is any one of Co, CoFe, and CoFeB.
  • the orbital Hall effect layer 40 may be composed of Cu or Cr. It should be noted that the selection of these materials is only for illustrative purposes, and may be replaced by other materials during practical application.
  • FIG. 5 schematically shows a schematic structural diagram of a SOT-MRAM storage unit according to another embodiment of the present disclosure.
  • the difference between the structure of the SOT-MRAM memory cell and the structure of the SOT-MRAM memory cell shown in FIG. 2 is that it does not include the heavy metal layer 30 .
  • Other material layers are consistent with those shown in FIG. 2 .
  • the orbital Hall effect layer 40 and the ferromagnetic free layer 203 are configured to pass a write current.
  • the orbital Hall effect layer 40 converts the write current into an orbital current polarized by the orbital magnetic moment (L) through the orbital Hall effect, and the orbital current can diffuse into the ferromagnetic free layer 203 .
  • the ferromagnetic free layer 203 converts the write current into a spin-polarized (S) spin current through the spin-orbit precession effect or the planar Hall effect, and at the same time diffuses into the orbit of the ferromagnetic free layer 203 through the spin-orbit coupling
  • the current is transformed into a spin current whose spin polarization direction is determined by the polarity of the spin-orbit coupling of the ferromagnetic layer.
  • the intrinsic spin current and the spin current converted from the orbital current have opposite polarization directions, and the two form a competing spin current, thereby Deterministic magnetization switching without external magnetic field assistance is realized.
  • the coupling polarity of the orbital Hall effect and the spin Hall effect in the system of the orbital Hall effect layer, the heavy metal layer, and the ferromagnetic layer is described below with reference to Table 1.
  • the polarity of the spin current transformed by the orbital Hall effect and the spin current generated by the spin Hall effect is determined by the polarity of the spin-orbit coupling of the ferromagnetic layer and the heavy metal layer.
  • the configuration of the heavy metal layer and the ferromagnetic layer material can realize the enhancement or competition of the orbital Hall effect on the spin Hall effect.
  • each material layer of the storage unit provided by the embodiments of the present disclosure is set according to actual application requirements, and can be realized in the manufacturing process.
  • the embodiments of the present disclosure set the thickness of each material layer No limit.
  • SOT-MRAM memory which includes: the SOT-MRAM storage unit as shown in the above embodiments.
  • the control process can also be realized by the logic control unit, specifically, the logic control unit can set the word line, the bit line, and the applied gate voltage bias, so as to realize data reading and writing operations, respectively.
  • the embodiment does not limit this.
  • a method for operating the above-mentioned SOT-MRAM memory including: controlling the voltage bias applied to the first transistor and the second transistor in the SOT-MRAM memory, Perform data writing and reading operations on the SOT-MRAM memory respectively.
  • the operation method includes the operation method of data reading and the operation method of data writing, wherein, there is no fixed sequence of execution between the operation method of data reading and the operation method of data writing.
  • the data reading operation is performed on the SOT-MRAM memory, including: controlling the first transistor 50 to be turned off and the second transistor 60 to be turned on, forming a bit line BL-magnetic tunnel junction (MTJ) - the current path of the source line SL-ground, and read the stored data in the SOT-MRAM memory through the tunnel magnetoresistance effect.
  • BL-magnetic tunnel junction MTJ
  • the data writing operation for the SOT-MRAM memory includes: controlling the first transistor 50 to be turned on and the second transistor 60 to be turned off, forming a Hall effect layer/ The current path of the heavy metal layer forms a competing spin current through the orbital Hall effect and the spin Hall effect to realize data writing to the SOT-MRAM memory.
  • a memory array composed of a plurality of SOT-MRAM memory cells as described above is provided, wherein each SOT-MRAM memory cell is arranged periodically.
  • periodically arranged SOT-MRAM memory cells can share word lines, bit lines, source lines, etc., so as to achieve high integration of the device.
  • another SOT-MRAM memory including: the above-mentioned SOT-MRAM memory array.
  • the selection of the word line and the bit line in the memory and the setting of the applied voltage bias can be realized through the logic control unit, so as to respectively realize operations such as data reading and writing.
  • the SOT-MRAM storage unit provided by the present disclosure can realize data writing without the assistance of an external magnetic field, which is beneficial to the large-scale integration of SOT-MRAM.
  • the SOT-MRAM storage unit can reduce the use of expensive heavy metal materials, thereby reducing the manufacturing cost of the SOT-MRAM.
  • the competitive spin current used in the SOT-MRAM realizes the field-free assisted writing method without introducing structural asymmetry, antiferromagnetic materials, etc., which improves the compatibility with the CMOS process and is beneficial to Large-scale preparation and practical application of SOT-MRAM.

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Abstract

本公开提供了一种SOT-MRAM存储单元，包括：底电极；磁隧道结层，位于底电极上；轨道霍尔效应层，位于磁隧道结层上；第一晶体管，其漏极与轨道霍尔效应层连接；以及第二晶体管，其漏极与底电极连接。本公开还提供了一种SOT-MRAM存储器、操作方法、SOT-MRAM存储阵列。

Description

一种SOT-MRAM存储单元、存储阵列、存储器及操作方法 技术领域
本公开涉及磁随机存储器技术领域，具体涉及SOT-MRAM存储单元、存储阵列、存储器及操作方法。
背景技术
SOT-MRAM(Spin-Orbit Torque Magnetic Random Access Memory，自旋轨道矩磁性存储器)作为新一代磁随机存储器，由于其亚纳秒级的写入速度、高数据保持时间、高耐久度、低功耗、抗辐射等特性，以及独特的读写分离的三端器件结构克服了上一代STT-MRAM存在的信息写入速度和可靠性瓶颈问题，而受到学界和工业界的广泛关注，有望成为下一代通用非易失存储器。
然而，SOT-MRAM存在尚未完全克服的技术挑战，即对于垂直各向异性(PMA)的SOT-MRAM而言其数据写入需要外加沿电流方向的面内磁场辅助，限制了SOT-MRAM的集成、微缩和大规模应用。现有的无外加磁场辅助的数据写入方法，如：结构非对称性、交换偏置/层间交换耦合引入内建面内场等都存在难以微缩集成且与CMOS工艺兼容性较差的问题。同时，现有技术中的SOT-MRAM大量使用价格昂贵的重金属材料作为自旋轨道耦合层，不利于进一步降低SOT-MRAM的成本。
发明内容
鉴于上述问题，本公开提供了一种SOT-MRAM存储单元、存储阵列、存储器及操作方法，旨在结合轨道霍尔效应、铁磁材料自旋轨道进动效应或平面霍尔效应、竞争自旋流实现无外加磁场辅助的SOT-MRAM存储单元。
本公开的第一个方面提供了一种SOT-MRAM存储单元，包括：底电极；磁隧道结层，位于底电极上；轨道霍尔效应层，位于磁隧道结层上；第一晶体管，其漏极与轨道霍尔效应层连接；以及第二晶体管，其漏极与底电极连接。
进一步地，该存储单元还包括：重金属层，位于磁隧道结层与轨道霍尔效应层之间。
进一步地，轨道霍尔效应层和重金属层被配置为通过写电流；其中，轨道霍尔效应层用于通过轨道霍尔效应将写电流转化为轨道极化的轨道流；重金属层用于通过自旋轨道耦合将写电流转化为自旋极化的自旋流。
进一步地，扩散进入重金属层的轨道流，在重金属层的强自旋轨道耦合作用下被转化为自旋流。
进一步地，重金属层产生的自旋流与轨道流转化形成的自旋流极性相反，形成竞争自旋流，其中，该竞争自旋流用于实现外加磁场辅助的确定性磁化翻转。
进一步地，磁隧道结层包括：自下而上的铁磁参考层、非磁性势垒层及铁磁自由层。
进一步地，铁磁参考层采用钉扎结构，包括：自下而上的反铁磁结构层、第二空间层及参考层。
进一步地，反铁磁结构层具有RKKY作用，包括：自下而上的第二铁磁层、第一空间层及第一铁磁层，第一空间层用于第一铁磁层与第二铁磁层之间形成反铁磁耦合。
进一步地，第一铁磁层与第二铁磁层构成的结构为周期性的Co/Pt或Co/Pd构成的合成铁磁结构。
进一步地，还包括：源线和位线；其中，源线与轨道霍尔效应层连接；位线分别与第一晶体管及第二晶体管的源极连接。
进一步地，重金属层为Pt、Ta、W和Gd中的一种或多种。
进一步地，铁磁参考层为Co、CoFeB、Co/Pt和包含合成反铁磁结构中的任一种；底电极为Pt、Ta和W中的一种或多种材料构成；非磁 性势垒层由MgO或Al 2O 3构成；铁磁自由层为Co、CoFe和CoFeB中的任一种；轨道霍尔效应层由Cu或Cr构成。
本公开的第二个方面提供了一种SOT-MRAM存储器，包括：本公开第一个方面提供的SOT-MRAM存储单元。
本公开的第三个方面提供了一种SOT-MRAM存储器的操作方法，其特征在于，包括：控制施加于SOT-MRAM存储器中第一晶体管及第二晶体管上的电压偏置，对SOT-MRAM存储器分别进行数据写入及读取操作。
进一步地，对SOT-MRAM存储器进行数据读取操作，包括：控制第一晶体管截止及第二晶体管导通，通过隧道磁电阻效应读取SOT-MRAM存储器中的存储数据。
进一步地，对SOT-MRAM存储器进行数据写入操作，包括：控制第一晶体管导通及第二晶体管截止，通过轨道霍尔效应和自旋霍尔效应形成竞争自旋流实现对SOT-MRAM存储器的数据写入。
本公开的第四个方面提供了一种SOT-MRAM存储阵列，包括：多个如本公开第一个提供的SOT-MRAM存储单元，其中，每个SOT-MRAM存储单元呈周期性布置。
本公开的第五个方面提供了一种SOT-MRAM存储器，包括：如本公开的第四个方面提供的SOT-MRAM存储阵列。
本公开的实施例提供了一种SOT-MRAM存储单元、存储阵列及存储器，该存储单元通过将轨道霍尔效应层被配置为将写电流转化为轨道极化的轨道流，且自旋轨道耦合层被设置为将写电流和扩散进入该层的轨道流转化为自旋极化相反的自旋流，形成竞争自旋流实现了无外加磁场辅助的全电控确定性磁化翻转。另外，该SOT-MRAM器件结构简单，减少了使用昂贵的重金属材料，材料体系与CMOS工艺兼容，有利于该SOT-MRAM器件的大规模制备和实用化。
附图说明
为了更完整地理解本公开及其优势，现在将参考结合附图的以下描述，其中：
图1示意性示出了本公开实施例的SOT-MRAM的研究背景演化示意图；
图2示意性示出了根据本公开一实施例的SOT-MRAM存储单元的结构示意图；
图3示意性示出了根据本公开一实施例的磁隧道结层的结构示意图；
图4示意性示出了图2所示的SOT-MRAM存储单元的实现无外加磁场辅助的确定性磁化翻转示意图；
图5示意性示出了根据本公开另一实施例的SOT-MRAM存储单元的结构示意图；
图6示意性示出了图5所示的SOT-MRAM存储单元的实现无外加磁场辅助的确定性磁化翻转示意图。
具体实施方式
以下，将参照附图来描述本公开的实施例。但是应该理解，这些描述只是示例性的，而并非要限制本公开的范围。在下面的详细描述中，为便于解释，阐述了许多具体的细节以提供对本公开实施例的全面理解。然而，明显地，一个或多个实施例在没有这些具体细节的情况下也可以被实施。此外，在以下说明中，省略了对公知结构和技术的描述，以避免不必要地混淆本公开的概念。
应该理解的是，当元件(诸如层、膜、区域、或衬底)描述为在另一元件“上”时，该元件可直接在该另一元件上，或者也可存在中间元件。而且，在说明书以及权利要求书中，当描述有元件“连接”至另一元件时，该元件可“直接连接”至该另一元件，或者通过第三元件“连接”至该另一元件。
在详述本公开实施例时，为便于说明，表示器件结构的剖面图会不 依一般比例作局部放大，而且示意图只是示例，其在此不应限制本公开保护的范围。此外，在实际制作中应包含长度、宽度及深度的三维空间尺寸。
图1示意性示出了本公开实施例的SOT-MRAM的研究背景演化示意图。本公开主要针对现有SOT-MRAM无外加磁场辅助磁化翻转结构可微缩性，与CMOS兼容性问题，以及现有SOT-MRAM使用昂贵重金属材料作为自旋轨道耦合层问题。现有的无外加磁场辅助磁化翻转机制主要有结构非对称性(如，楔形势垒层、铁磁层、重金属层等)，内建偏置场(如，铁磁/反铁磁交换偏置，层间耦合等)，混合方式(如，STT和SOT协同作用，基于磁畴壁运动等)，自旋流构型(如，梯度自旋流、竞争自旋流、面外极化自旋流等)四种类型。
重金属由于其很强的自旋轨道耦合被广泛采用为SOT-MRAM的自旋轨道耦合层，但是重金属同时也存在着价格昂贵、电阻率较高等问题。2018年以来，有研究人员提出轨道霍尔效应，轨道流可通过自旋轨道耦合转化为自旋流，可增强自旋流转化效率。且在轻金属(如Cu)/铁磁材料中，轨道霍尔效应与自旋轨道耦合结合可实现与重金属相当的自旋流转化效率。本公开旨在发明将结合轨道霍尔效应、铁磁材料自旋轨道进动效应或平面霍尔效应、竞争自旋流实现无外加磁场辅助的SOT-MRAM。
针对现有技术存在的问题，本公开提供了一种SOT-MRAM存储单元，包括：底电极；磁隧道结层，位于底电极上；轨道霍尔效应层，位于磁隧道结层上；第一晶体管，其漏极与轨道霍尔效应层连接；以及第二晶体管，其漏极与底电极连接。
本公开的实施例提供的SOT-MRAM存储单元，该存储单元通过将轨道霍尔效应层被配置为将写电流转化为轨道极化的轨道流，且自旋轨道耦合层被设置为将写电流和扩散进入该层的轨道流转化为自旋极化相反的自旋流，形成竞争自旋流实现了无外加磁场辅助的全电控确定性磁化翻转。本公开提供的SOT-MRAM器件结构简单，减少了使用昂贵的重金属材料，材料体系与CMOS工艺兼容，有利于该SOT-MRAM器 件的大规模制备和实用化。
下面将结合本公开具体的实施例中的SOT-MRAM存储单元的结构，对本公开的技术方案进行详细说明。应当理解，图2～图5中示出的SOT-MRAM存储单元的结构中各部分的材料层、形状和结构仅是示例性的，以帮助本领域的技术人员理解本公开的技术方案，并非用以限制本公开的保护范围。
图2示意性示出了根据本公开一实施例的SOT-MRAM存储单元的结构示意图。
如图2所示，本公开一实施例的SOT-MRAM存储单元，包括：自下而上的底电极10、磁隧道结层20、重金属层30、轨道霍尔效应层40、第一晶体管50及第二晶体管60，第一晶体管50的漏极与轨道霍尔效应层40的顶部连接，第二晶体管60的漏极与底电极10的顶部连接。其中，该磁隧道结层20为自旋轨道矩磁隧道结(SOT-MTJ)。
本公开的实施例中，如图2和图3所示，该磁隧道结层20包括自下而上的铁磁参考层201、非磁性势垒层202及铁磁自由层203。其中，铁磁参考层201采用钉扎结构，其具体包括：自下而上的反铁磁结构层2011、第二空间层2012及参考层2013。
具体地，如图3所示，反铁磁结构层2011具有RKKY作用，其具体包括：自下而上的第二铁磁层201I、第一空间层201II及第一铁磁层201III，第一空间层201II用于第一铁磁层201III与第二铁磁层201I之间形成反铁磁耦合。其中，第二铁磁层201I、第一空间层201II及第一铁磁层201III通过RKKY作用实现的合成反铁磁结构(SAF)。
进一步地，第一铁磁层201III与第二铁磁层201I构成的结构具体为周期性的Co/Pt或Co/Pd构成的合成铁磁结构。
根据本公开的实施例，该SOT-MRAM存储单元还包括：源线SL和位线BL。其中，源线SL与轨道霍尔效应层40连接，位线BL分别与第一晶体管50及第二晶体管60的源极连接。第一晶体管50及第二晶体管60的栅极分别用于接入写入和读取的偏置电压。
本实施例中，轨道霍尔效应层40和重金属层30被配置为通过写电 流。其中，如图4所示，轨道霍尔效应层40用于通过轨道霍尔效应将写电流转化为轨道磁矩(L)极化的轨道流，且该轨道流可以扩散进入重金属层30。重金属层30用于通过自旋轨道耦合将写电流转化为自旋(S)极化的自旋流，同时将扩散进入重金属层30的轨道流，在重金属层30的强自旋轨道耦合作用下被转化为自旋流。其自旋极化方向由重金属自旋轨道耦合极性确定。
如图4所示，在重金属层30、铁磁自由层203界面的本征自旋流和轨道流转化而来的自旋流极化方向相反，两者形成竞争自旋流，从而实现了无外加磁场辅助的确定性磁化翻转。
本公开的实施例中，重金属层30为Pt、Ta、W和Gd中的一种或多种，其层厚可以根据实际应用需求进行设定，本公开的实施例对此不做限定。
具体地，铁磁参考层201为Co、CoFeB、Co/Pt和包含合成反铁磁结构中的任一种。底电极10为Pt、Ta和W中的一种或多种材料构成。非磁性势垒层202可以由MgO或Al 2O 3构成。铁磁自由层203为Co、CoFe和CoFeB中的任一种。轨道霍尔效应层40可以由Cu或Cr构成。需说明的是，这些材料的选取仅为示例性的说明，在实际应用过程中，其还可以为其他材料的替换。
图5示意性示出了根据本公开另一实施例的SOT-MRAM存储单元的结构示意图。
如图5所示，该SOT-MRAM存储单元的结构对比如图2所示的SOT-MRAM存储单元的结构区别在于：其不包含重金属层30。其他材料层均与如图2所示的材料层保持一致。
本实施例中，如图6所示，轨道霍尔效应层40和铁磁自由层203(即铁磁自旋轨道耦合层)被配置为用于通过写电流。轨道霍尔效应层40通过轨道霍尔效应将写电流转化为轨道磁矩(L)极化的轨道流，该轨道流可以扩散进入铁磁自由层203。铁磁自由层203通过自旋轨道进动效应或平面霍尔效应将写电流转化为自旋极化(S)的自旋流，同时通过自旋轨道耦合将扩散进入铁磁自由层203的轨道流转化为自旋流， 其自旋极化方向由铁磁层自旋轨道耦合极性确定。
如图6所示，在轨道霍尔效应层40与铁磁自由层203的界面本征自旋流和轨道流转化而来的自旋流极化方向相反，两者形成竞争自旋流，从而实现了无外加磁场辅助的确定性磁化翻转。
本公开的实施例中，下面结合表1说明轨道霍尔效应层、重金属层、铁磁层体系中轨道霍尔效应和自旋霍尔效应耦合极性。
表1 轨道霍尔效应与自旋霍尔效应耦合极性
Figure PCTCN2022078760-appb-000001
从上表1可知，轨道霍尔效应转化的自旋流和自旋霍尔效应产生的自旋流极性由铁磁层和重金属层自旋轨道耦合极性决定。配置重金属层和铁磁层材料，可以实现轨道霍尔效应对自旋霍尔效应的增强或竞争。
需说明的是，本公开实施例提供的存储单元的各材料层的层厚根据实际应用需求进行设定，以及在制备工艺上能够实现即可，本公开的实施例对各材料层的层厚不做限定。
本公开另一方面还提供了SOT-MRAM存储器，其包括：如上述实施例所示的SOT-MRAM存储单元。
本实施例中，通过控制该SOT-MRAM存储器上晶体管的偏置电压，可分别实现对存储器数据的读取及写入操作。该控制过程还可以通过逻辑控制单元进行实现，具体可通过逻辑控制单元对字线、位线以及施加栅极电压偏置的设定，从而分别实现数据读取及写入等操作，本公开的实施例对此不做限定。
在本公开的再一示例性实施例中，提供了一种如上述的SOT-MRAM存储器的操作方法，包括：控制施加于SOT-MRAM存储器中第一晶体管及第二晶体管上的电压偏置，对SOT-MRAM存储器分别进行数据写入及读取操作。该操作方法包括数据读取的操作方法及数据写入的操作 方法，其中，数据读取的操作方法及数据写入的操作方法之间并无固定先后执行顺序。
具体地，如图2或5所示，对SOT-MRAM存储器进行数据读取操作，包括：控制第一晶体管50截止及第二晶体管60导通，形成由位线BL-磁隧道结(MTJ)-源线SL-地的电流通路，通过隧道磁电阻效应读取SOT-MRAM存储器中的存储数据。
具体地，如图2或5所示，对SOT-MRAM存储器进行数据写入操作，包括：控制第一晶体管导通50及第二晶体管60截止，形成由位线BL-轨道霍尔效应层/重金属层的电流通路，通过轨道霍尔效应和自旋霍尔效应形成竞争自旋流实现对SOT-MRAM存储器的数据写入。
在本公开的再一示例性实施例中，提供了一种如上所述的多个SOT-MRAM存储单元构成的存储阵列，其中，每个SOT-MRAM存储单元呈周期性布置。
具体地，周期性布置的SOT-MRAM存储单元可以共用字线、位线、源线等，以实现器件的高集成度。
在本公开的还一示例性实施例中，还提供了另一种SOT-MRAM存储器，包括：如上所述的SOT-MRAM存储阵列。
具体地，可以通过逻辑控制单元实现对该存储器中字线、位线的选择以及施加电压偏置的设定，从而分别实现数据读取及写入等操作。
从以上的描述中，可以看出，本公开上述的实施例至少实现了以下技术效果：
(1)、本公开提供的SOT-MRAM存储单元无需外加磁场辅助，即可实现数据写入，有利于SOT-MRAM的大规模集成。
(2)、该SOT-MRAM存储单元可以减少使用昂贵的重金属材料，进而降低了SOT-MRAM的制作成本。
(3)、本公开提供的SOT-MRAM所采用的竞争自旋流实现无场辅助写入方式，不需要引入结构非对称性、反铁磁材料等，提高了与CMOS工艺兼容性，有利于SOT-MRAM的大规模制备和实用化。
尽管已经在附图和前面的描述中详细地图示和描述了本公开，但是 这样的图示和描述应认为是说明性的或示例性的而非限制性的。
本领域技术人员可以理解，本公开的各个实施例和/或权利要求中记载的特征可以进行多种范围组合和/或结合，即使这样的组合或结合没有明确记载于本公开中。特别地，在不脱离本公开精神和教导的情况下，本公开的各个实施例和/或权利要求中记载的特征可以进行多种组合和/或结合。所有这些组合和/或结合均落入本公开的范围。
尽管已经参照本公开的特定示例性实施例示出并描述了本公开，但是本领域技术人员应该理解，在不背离所附权利要求及其等同物限定的本公开的精神和范围的情况下，可以对本公开进行形式和细节上的多种改变。因此，本公开的范围不应该限于上述实施例，而是应该不仅由所附权利要求来进行确定，还由所附权利要求的等同物来进行限定。

Claims (18)

  1. 一种SOT-MRAM存储单元，其特征在于，包括：
    底电极；
    磁隧道结层，位于所述底电极上；
    轨道霍尔效应层，位于所述磁隧道结层上；
    第一晶体管，其漏极与所述轨道霍尔效应层连接；以及
    第二晶体管，其漏极与所述底电极连接。
  2. 根据权利要求1所述的SOT-MRAM存储单元，其特征在于，还包括：
    重金属层，位于所述磁隧道结层与所述轨道霍尔效应层之间。
  3. 根据权利要求2所述的SOT-MRAM存储单元，其特征在于，所述轨道霍尔效应层和所述重金属层被配置为通过写电流；其中，
    所述轨道霍尔效应层用于通过轨道霍尔效应将所述写电流转化为轨道极化的轨道流；
    所述重金属层用于通过自旋轨道耦合将所述写电流转化为自旋极化的自旋流。
  4. 根据权利要求3所述的SOT-MRAM存储单元，其特征在于，扩散进入所述重金属层的所述轨道流，在所述重金属层的强自旋轨道耦合作用下被转化为自旋流。
  5. 根据权利要求4所述的SOT-MRAM存储单元，其特征在于，所述重金属层产生的自旋流与所述轨道流转化形成的自旋流极性相反，形成竞争自旋流，其中，该竞争自旋流用于实现外加磁场辅助的确定性磁化翻转。
  6. 根据权利要求1或2所述的SOT-MRAM存储单元，其特征在于， 所述磁隧道结层包括：自下而上的铁磁参考层、非磁性势垒层及铁磁自由层。
  7. 根据权利要求6所述的SOT-MRAM存储单元，其特征在于，所述铁磁参考层采用钉扎结构，包括：自下而上的反铁磁结构层、第二空间层及参考层。
  8. 根据权利要求7所述的SOT-MRAM存储单元，其特征在于，所述反铁磁结构层具有RKKY作用，包括：自下而上的第二铁磁层、第一空间层及第一铁磁层，所述第一空间层用于所述第一铁磁层与所述第二铁磁层之间形成反铁磁耦合。
  9. 根据权利要求8所述的SOT-MRAM存储单元，其特征在于，所述第一铁磁层与所述第二铁磁层构成的结构为周期性的Co/Pt或Co/Pd构成的合成铁磁结构。
  10. 根据权利要求1所述的SOT-MRAM存储单元，其特征在于，还包括：
    源线和位线；其中，
    所述源线与所述轨道霍尔效应层连接；
    所述位线分别与所述第一晶体管及所述第二晶体管的源极连接。
  11. 根据权利要求2所述的SOT-MRAM存储单元，其特征在于，所述重金属层为Pt、Ta、W和Gd中的一种或多种。
  12. 根据权利要求6所述的SOT-MRAM存储单元，其特征在于，所述铁磁参考层为Co、CoFeB、Co/Pt和包含合成反铁磁结构中的任一种；
    所述底电极为Pt、Ta和W中的一种或多种材料构成；
    所述非磁性势垒层由MgO或Al 2O 3构成；
    所述铁磁自由层为Co、CoFe和CoFeB中的任一种；
    所述轨道霍尔效应层由Cu或Cr构成。
  13. 一种SOT-MRAM存储器，其特征在于，包括：如权利要求1～10中任一项所述的SOT-MRAM存储单元。
  14. 一种如权利要求13所述的SOT-MRAM存储器的操作方法，其特征在于，包括：
    控制施加于SOT-MRAM存储器中第一晶体管及第二晶体管上的电压偏置，对SOT-MRAM存储器分别进行数据写入及读取操作。
  15. 根据权利要求13所述的操作方法，其特征在于，所述对SOT-MRAM存储器进行数据读取操作，包括：
    控制所述第一晶体管截止及所述第二晶体管导通，通过隧道磁电阻效应读取所述SOT-MRAM存储器中的存储数据。
  16. 根据权利要求13所述的操作方法，其特征在于，所述对SOT-MRAM存储器进行数据写入操作，包括：
    控制所述第一晶体管导通及所述第二晶体管截止，通过轨道霍尔效应和自旋霍尔效应形成竞争自旋流实现对所述SOT-MRAM存储器的数据写入。
  17. 一种SOT-MRAM存储阵列，其特征在于，包括：
    多个如权利要求1～12中任一项所述的SOT-MRAM存储单元，其中，每个SOT-MRAM存储单元呈周期性布置。
  18. 一种SOT-MRAM存储器，其特征在于，包括：如权利要求17所述的SOT-MRAM存储阵列。
PCT/CN2022/078760 2022-03-02 2022-03-02 一种sot-mram存储单元、存储阵列、存储器及操作方法 WO2023164827A1 (zh)

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