WO2023155531A1 - 数据读写方法、装置及相关设备 - Google Patents

数据读写方法、装置及相关设备 Download PDF

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Publication number
WO2023155531A1
WO2023155531A1 PCT/CN2022/134789 CN2022134789W WO2023155531A1 WO 2023155531 A1 WO2023155531 A1 WO 2023155531A1 CN 2022134789 W CN2022134789 W CN 2022134789W WO 2023155531 A1 WO2023155531 A1 WO 2023155531A1
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data
read
ram
write
storage address
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PCT/CN2022/134789
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English (en)
French (fr)
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孙旭
周玉龙
杨萌
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苏州浪潮智能科技有限公司
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Priority to US18/697,426 priority Critical patent/US20240264778A1/en
Publication of WO2023155531A1 publication Critical patent/WO2023155531A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/061—Improving I/O performance
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
    • G06F3/0659—Command handling arrangements, e.g. command buffers, queues, command scheduling
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0893—Caches characterised by their organisation or structure
    • G06F12/0895—Caches characterised by their organisation or structure of parts of caches, e.g. directory or tag array
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/0604—Improving or facilitating administration, e.g. storage management
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0638—Organizing or formatting or addressing of data
    • G06F3/064—Management of blocks
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
    • G06F3/0656—Data buffering arrangements
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
    • G06F3/0671—In-line storage system
    • G06F3/0673—Single storage device

Definitions

  • the present application relates to the technical field of data storage, in particular to a data reading and writing method, and also to a data reading and writing device, equipment, and computer-readable storage medium.
  • Cache buffer memory/cache
  • CPU Central Processing Unit, central processing unit
  • main memory main memory
  • the access speed is faster than the main memory.
  • An important technique for matching It can provide instructions and data to the CPU at high speed to speed up the execution speed of the program.
  • Cache replacement strategies can generally be divided into the following three categories: (1) first-in-first-out-based replacement; (2) random replacement; (3) least-recently-used method or other derivative methods based on Cache historical information.
  • the first two methods do not need to consider the actual usage of the Cache, and replace the data first written to the Cache first or completely randomly.
  • this implementation method has a low cache hit rate, which reduces the efficiency of data reading and writing to a certain extent. ;
  • the last method has a higher cache hit rate, its implementation process needs to rely on more cumbersome information statistics and algorithm calculations, as well as a more complicated hardware structure, which will also reduce the efficiency of data reading and writing.
  • the embodiment of the present application provides a method for reading and writing data, including:
  • determine whether the read and write data hits the cache including:
  • the read and write data hits the cache, it also includes:
  • the one-hot code CAM_B_rd_data is converted into binary information and connected to the RAM_B_rd_addr of the B port of DATA_RAM, where CAM_B_rd_data is the B port read data of CAM, CAM is content addressable memory, and RAM_B_rd_addr It is the B port read address of RAM, and the data memory includes RAM;
  • RAM_B_rd_addr_en is the B port read enable of RAM
  • RAM_B_rd_data is the B port read data of RAM
  • the read and write data hits the cache, it also includes:
  • the one-hot code CAM_B_rd_data is converted into binary information and connected to the RAM_B_rd_addr of the B port of DATA_RAM, where CAM_B_rd_data is the B port read data of CAM, CAM is content addressable memory, and RAM_B_rd_addr It is the B port read address of RAM, and the data memory includes RAM;
  • RAM_B_rd_addr_en is the B port read enable of RAM
  • RAM_B_rd_data is the B port read data of RAM
  • the read data cache line cache line remains unchanged, the write flag position is 1, the read flag position is 1, and the newly generated signal is assigned to the write data RAM_A_wr_data signal of the A port of DATA_RAM, and RAM_A_wr_addr_en is pulled high at the same time, And assign the address of the B port to the A port, and write the data and flag bits into the data RAM, wherein, RAM_A_wr_data is the write data of the A port of the RAM, and RAM_A_wr_addr_en is the write enable of the A port of the RAM.
  • the read-write data input is set in the content-addressable memory in the cache, including:
  • Cpu_addr is connected to the read address end CAM_B_rd_addr of the B port of data memory, wherein, Cpu_addr is the instruction execution address of central processing unit CPU, and CAM_B_rd_addr is the B port read address of CAM, and CAM is content addressable memory;
  • the storage address of the read-write data in the data memory and the storage address in the main memory are both updated to the content addressable memory.
  • judging whether there is a free storage address in the data memory includes:
  • the read-write flag bit includes a read flag bit and a write flag bit
  • the read flag bit is used to set the read flag or the unread flag
  • the write flag bit is used to set the The written flag or the unwritten flag is determined.
  • the read flag is used to indicate that the data information stored in the corresponding storage address has been read
  • the unread flag is used to indicate that the data information stored in the corresponding storage address is being written. It has not been read after that, the written flag is used to indicate that the corresponding storage address stores data information
  • the unwritten flag is used to indicate that the corresponding storage address is an idle storage address.
  • the method when the read and write data hits the cache, the method also includes:
  • a read flag is set for the storage address of the read data in the data memory
  • a written flag is set for the storage address of the write data in the data memory.
  • the data reading and writing method also includes:
  • the read-write data misses the cache and there is an idle storage address in the data memory, the read-write data is written into the idle storage address.
  • the read and write data before writing the read and write data to the free storage address, it also includes:
  • addr_cnt_rd also adds 1 operation, where RAM_B_rd_addr is the B port read address of RAM, the data memory includes RAM, RAM_B_rd_addr_en is the B port read enable of RAM, addr_cnt_rd is Read address search times;
  • RAM_B_rd_data is the B port read data of the RAM
  • the data_ram_next_addr is determined as an idle storage address for writing read and write data.
  • the read and write data before writing the read and write data to the free storage address, it also includes:
  • RAM_B_rd_addr Connect data_ram_next_addr_rd to RAM_B_rd_addr, and pull RAM_B_rd_addr_en high for read operation, and addr_cnt_rd also adds 1 operation, where RAM_B_rd_addr is the B port read address of RAM, the data memory includes RAM, RAM_B_rd_addr_en is the B port read enable of RAM, addr_cnt_rd is Read address search times;
  • RAM_B_rd_data is the B port read data of the RAM
  • data_ram_next_addr_rd is determined as an idle storage address for writing read and write data.
  • the method further includes:
  • CAM_A_wr_addr ⁇ Cpu_addr, data_ram_next_addr_one_rd ⁇ ;
  • data_ram_next_addr_one_rd is the one-hot code address of data_ram_next_addr_rd
  • data_ram_next_addr_one_rd 16'b1 ⁇ data_ram_next_addr_rd
  • the high bit is the address sent by the CPU
  • the low bit is the one-hot code address of the read-write data that needs to be replaced in the content addressable memory.
  • CAM_A_wr_addr is A port write address of CAM
  • CAM is a content addressable memory
  • Cpu_addr is an instruction execution address of a central processing unit CPU.
  • the method before traversing from the initial storage address of the data memory, the method further includes:
  • write read and write data into storage addresses with unread flags including:
  • the read data is obtained from the main memory; the read data is written into a storage address with an unread flag;
  • the read and write data is write data
  • the write data is written into the storage address and the main memory where the unread flag exists.
  • write the read and write data into the previous storage address of the initial storage address including:
  • the read data is obtained from the main memory; the read data is written into the previous storage address of the initial storage address;
  • the write data is written into the previous storage address of the initial storage address and into the main memory.
  • the embodiment of the present application also discloses a data reading and writing device, including:
  • a read-write data determination module configured to determine read-write data according to a data read-write request
  • the storage address traversal module is used to start traversing from the initial storage address of the data memory when the read and write data misses the cache and there is no free storage address in the data memory set in the cache;
  • the first data writing module is used to write the read and write data into the storage address with the unread mark when traversing to the storage address with the unread mark;
  • the second data writing module is used to write the read and write data into the previous storage address of the initial storage address when the storage address with the unread flag has not been traversed.
  • the embodiment of the present application also discloses a data reading and writing device, including:
  • the processor is configured to implement the steps of any one of the above data reading and writing methods when executing the computer program.
  • the embodiment of the present application also discloses a computer-readable storage medium, on which a computer program is stored, and when the computer program is executed by a processor, the steps of any one of the above data reading and writing methods are realized.
  • a method for reading and writing data includes determining the read and write data according to the data read and write request; The initial storage address of the memory starts to traverse; when traversing to the storage address with unread flags, write the read and write data into the storage address with unread flags; when not traversing to the storage addresses with unread flags, read and write Write data is written in the previous storage address of the initial storage address.
  • the read and write flag bits are set in advance for each data storage address of the data memory in the cache, which is used to mark whether the corresponding stored data has been read or written.
  • the read and write data misses the cache and there is no free storage address in the data memory in the cache, it can traverse from the initial storage address of the data memory until it traverses to the storage address with an unread flag, indicating that the storage The data information stored in the address has never been read, and the usage rate is low.
  • the read and write data can be directly written to the storage address with the unread mark; when the unread mark cannot be traversed
  • the read and write data can be directly written to the previous storage address of the initial storage address, that is, the last storage address in the traversed data memory, so as to effectively ensure that the read and write data are stored in the cache. It can be seen that this implementation method can effectively ensure a high cache hit rate and at the same time improve the efficiency of data reading and writing.
  • FIG. 1 is a schematic flow diagram of a data reading and writing method provided by an embodiment of the present application
  • Fig. 2 is a schematic structural diagram of a data reading and writing system provided by an embodiment of the present application
  • FIG. 3 is a schematic structural diagram of a data reading and writing device provided by an embodiment of the present application.
  • FIG. 4 is a schematic structural diagram of a data reading and writing device provided by an embodiment of the present application.
  • the data reading and writing device, equipment, and computer-readable storage medium also have the above-mentioned beneficial effects.
  • An embodiment of the present application provides a method for reading and writing data.
  • FIG. 1 is a schematic flow diagram of a data reading and writing method provided in the embodiment of the present application.
  • the data reading and writing method may include:
  • S101 Determine read and write data according to the data read and write request
  • This step aims to determine the read and write data, that is, determine the corresponding read and write data according to the data read and write request, that is, when a data read request is received, the required read and write data can be determined according to the data read request.
  • the data information; when receiving the data writing request, the data information to be stored can be determined according to the data writing request.
  • the data reading and writing request may be initiated by a technician based on a corresponding front-end device.
  • This step aims to realize the traversal of the storage addresses in the data memory, so as to find the storage addresses with unread flags.
  • the storage of data information can be realized by setting the data memory, wherein the type of the data memory does not affect the implementation of the technical solution, for example, it can be realized by using RAM (Random Access Memory). This is not limited.
  • RAM Random Access Memory
  • the initial storage address is a preset storage address, which can be customized and set by technicians, which is not limited in this application.
  • the read and write data misses the cache and there is no free storage address in the data storage, if the storage address with the unread flag is traversed, it means that the data information stored in the storage address is being written into the storage The address has not been read since then, that is, the usage rate is low. Therefore, the read and write data can be replaced by the original data stored in the storage address, that is, the read and write data can be directly written to the location where the unread flag exists. In the storage address, thus, the read and write data is written into the cache, and the replacement and update of the cache is completed.
  • the read and write data misses the cache and there is no free storage address in the data memory, if the storage address with the unread flag is not traversed from the initial storage address to the last storage address, it means that the data The usage rate of all data stored in the memory is relatively high.
  • the read and write data can be directly replaced by the last storage address (that is, the upper address of the above initial storage address).
  • the original data stored in the first storage address directly writes the read-write data into the last storage address, thereby realizing the writing of the read-write data into the cache and completing the replacement and update of the cache.
  • the data reading and writing method pre-sets the reading and writing flag bits for each data storage address of the data memory in the cache to mark whether the corresponding stored data has been read or written.
  • the read and write data misses the cache and there is no free storage address in the data memory in the cache, it can traverse from the initial storage address of the data memory until it traverses to the storage address with an unread flag. It means that the data information stored in this storage address has never been read, and the usage rate is low.
  • judging whether the read-write data hits the cache may include: inputting the read-write data into the content-addressable memory set in the cache; When address information is received, it is determined that the read-write data hits the cache; when the address information fed back by the content addressable memory according to the read-write data is not received, it is determined that the read-write data misses the cache.
  • the embodiment of the present application provides a cache hit judging method, that is, judging whether the read/write data hits the cache, and the method can be implemented based on a content addressable memory.
  • Fig. 2 is the structural representation of a kind of data read-write system provided by the embodiment of the present application, and this data read-write system mainly comprises CPU, Cache (caching) and Main memory (main memory), in Cache Among them, it mainly includes CU (control unit), CAM (Content-Addressable Memory, content-addressable memory), RAM_DATA (RAM for storing data, that is, the above-mentioned data memory), etc.
  • CU control unit
  • CAM Content-Addressable Memory
  • RAM_DATA RAM for storing data, that is, the above-mentioned data memory
  • CU mainly completes Cache hit judgment, Cache replacement policy control, generation of CAM unit control signal, generation of RAM_DATA unit control signal, etc.;
  • CAM unit is mainly used to address data content according to address content;
  • RAM_DATA is mainly used to store cache line (cache line )data.
  • Table 1 is a key signal group description table provided by the embodiment of the present application:
  • Table 1 A key signal group description table
  • CAM is different from RAM, it checks the corresponding address data through the input data content, and outputs it.
  • RAM the input address is used to read the data stored at the address location; while using CAM, the input data is compared with the data already stored in the CAM at the same time, if there is the same content, The address data stored in the same data and the search success signal are output, otherwise, the search success signal is not output.
  • the structure and working principle of CAM are as follows:
  • the main part of CAM is a dual-port random access memory, and the two data ports have different bit widths. Taking a random access memory with a capacity of 4096 bits as an example, you can configure the A port to have a data bit width of 1 bit and a data depth of 4096 (the address is 0-4095); configure the B port to have a data bit width of 4 bits and a data depth of 256 (The address is 0-255).
  • the 12-bit address of the A port of RAM is composed of high 8-bit data "00000111” and low 4 A combination of bits "0100" (one-hot code 2).
  • the write enable and data bits of port A are both set to 1, then actually write "1" into the unit whose address is 074H.
  • CAM When CAM is written, it does not really store the 8-bit data, but makes a record in the storage line corresponding to the 8-bit data.
  • the read operation is completed at port B, and the read operation of the CAM is actually a data matching process.
  • the data corresponding to address 0 is the data of address 0-3 of port A
  • the data corresponding to address 1 is the data of address 4-7 of port A
  • ADDRB address line
  • the output value is "0100" (one-hot code 2).
  • Table 2 is a conversion table of encoding methods provided by the embodiment of the present application:
  • Table 2 A coding method conversion table
  • the CAM finds the corresponding address information based on the read-write data, it means that the read-write data is stored in the RAM, that is, read-write The data hits the cache; if the CAM fails to query the corresponding address information based on the read and write data, it means that the read and write data is not stored in the PAM, that is, the read and write data misses the cache.
  • the read-write data into the storage address with the unread flag after writing the read-write data into the previous storage address of the initial storage address, it may also include: The storage address of the write data in the data memory and the storage address in the main memory are updated to the content addressable memory together.
  • the data reading and writing method provided by the embodiment of the present application aims at updating the content addressable memory, so as to effectively ensure the accuracy of the cache hit judgment result. After writing the read and write data into the cache, whether it is written to the storage address with an unread flag or the previous storage address of the initial storage address, the storage address of the read and write data in the data memory and the storage address of the main The storage address in the memory is updated to the content-addressable memory together, so as to perform subsequent new cache hit judgment.
  • judging whether there is an idle storage address in the data storage may include: starting to traverse from the initial storage address of the data storage; when traversing to a storage address with an unwritten flag, determining that there is an idle storage address in the data storage , and use the storage address with the unwritten flag as the free storage address; when the storage address with the unwritten flag is not traversed, it is determined that there is no free storage address in the data memory.
  • the embodiment of the present application provides a judging method for judging whether there is a free storage address in the data memory, and the judging method can be realized according to the read/write flag bit of the storage address.
  • the read and write flag bits can be set for each storage address in advance to set the read flag, the written flag, the unread flag, and the unwritten flag. Then, after the data information is written into the corresponding memory address, it can be Setting the written flag indicates that data information is stored at the storage address.
  • the storage address of the unwritten mark is the free storage address, and the read and write data can be written directly to the free storage address, without the need to continue traversing the storage address; if the unwritten mark cannot be traversed until the last storage address storage address (equivalent to all storage addresses being written flags), then it can be determined that there is no free storage address in the data memory.
  • the read-write data into the storage address with the unread flag after writing the read-write data into the storage address with the unread flag, or after writing the read-write data into the previous storage address of the initial storage address, it may also include: The storage address of the write data in the data memory sets a written flag and an unread flag.
  • the data reading and writing method provided by the embodiment of the present application aims to realize the setting of the reading and writing flag bit. It can be understood that, in order to effectively ensure the accuracy of the judgment result of the above free storage address, the read and write flag bits of the storage address can be updated in real time.
  • the storage address, or the previous storage address written to the initial storage address does not need to consider the state of the read and write flags before the storage address, you can set the written flag and unread for the storage address of the read and write data in the data storage address flags, wherein the written flag is used to indicate that data information has been stored in the current storage location, and the unread flag is used to indicate that the data information stored in the current storage location has not been read after being written.
  • the method may further include: if the read-write data is specifically read data, setting a read flag for the storage address of the read data in the data memory; If the write data is specifically write data, a written flag is set for a storage address of the write data in the data memory.
  • the data reading and writing method provided by the embodiment of the present application aims at setting the reading and writing flag bits for different types of data (reading data and writing data).
  • the read data when the read data hits the cache, there is no need to obtain the read data from the main memory, and it can be read directly from the cache. On this basis, after the read data is read from the cache, it can be A read flag is set at the storage address of the read data in the data memory, indicating that the data information stored in the storage address has been read. Of course, when the read data misses the cache, it is necessary to obtain the read data from the main memory and store the read data in the cache at the same time. At this time, the storage address of the read data in the data memory can be set. read sign.
  • the write data when the write data hits the cache, it means that the write data has been stored in the data memory.
  • the written flag can be set for its storage address in the data memory, and the read flag bit can be set according to the read situation. It can be understood that when the write data hits the cache, it means that the write data has already been stored in the main memory, and there is no need to write it into the main memory again at this time.
  • the write data misses the cache it can also be written into the cache while storing the write data in the main memory, and after writing into the cache, set a written flag for its storage address in the data memory and unread flag.
  • the method may further include: when the read-write data misses the cache and there is a free storage address in the data memory, writing the read-write data into the free storage address.
  • the embodiment of the present application provides a cache replacement strategy, which is implemented as follows:
  • the cache line is replaced, and the data in the subsequent RAM address and the read/write flag are read by adding 1 to the original RAM address.
  • the write flag indicates the storage location If it is empty, write the cache line data read from the main memory to this location, set the write flag to 1, and update the address information of the cache line in the main memory and the address information in RAM in the CAM; when When the write flag is 1, the address continues to add 1 and jump until the next write flag is 0; when the entire RAM has stored data, that is, the address has jumped back to the initial address, this time At this time, add 1 to the address again for a round of judgment.
  • the read flag is 0, it means that the data of this cache line has not been read again after being written.
  • the cache line data read from the main memory will be read. Write at this location, and set the write flag to 1.
  • the read flag is 1, the address continues to add 1 to jump; when jumping back to the starting address again, it means the read and write flag of the entire storage space Both are 1, at this time, the previous address of the starting address is used as the replacement address, the cache line data read from the main memory is written to this position, and the write flag position is set to 1. And, when the replacement address is determined, the address of the cache line in the main memory and the address information in the RAM are updated in the CAM.
  • the size of the cache line is 64bit; the depth of the data RAM (DATA_RAM) is 64 (that is, it can store 64 cache line data), and the address bit
  • the width depth_size is 4, and the address is 0-15;
  • the operation address bit width Cpu_addr_size issued by the CPU side is 16 bits, and the address bit width of the main memory is also 16 bits.
  • the corresponding read and write operation process is as follows:
  • DATA_RAM is used to store cache line information. In the cache, it is generally stored and replaced in units of cache lines.
  • the size of cache lines is generally 8, 16, 32, 64, 128bit, etc., and is subsequently represented by line_size.
  • the data bit width of the two ports is line_size+2, and the upper two bits are the read and write flag bits.
  • Attached Table 3 Table 3 is a description of the identification in a RAM provided by this application. Table); the address bit width can be freely configured according to different actual usage scenarios, and will be represented by depth_size later.
  • the actual data depth is represented by depth.
  • the data depth of the memory is 64, that is, 64 groups of data can be stored.
  • CAM is mainly used to store address information and flag bit information.
  • the data bit width and address bit width of the two ports are different.
  • Cpu_addr is the operation address issued by the CPU (commonly used such as 8, 16, 32, 64, etc.), and its data bit width is recorded as Cpu_addr_size.
  • the data bit width of port A is 1, the address bit width is Cpu_addr_size+depth, the high bit of the address is the CPU address, and the low bit of the address is the one-hot code address in RAM.
  • the data bit width of port B is depth, and the address bit width is Cpu_addr_size.
  • the write cache operation includes write cache hit (hit) and write cache miss (miss).
  • hit write cache hit
  • miss write cache miss
  • Cpu_req When Cpu_req is 1, that is, a request is initiated, and when cpu_type is a write operation of store type, connect Cpu_addr to the read address terminal (CAM_B_rd_addr) of the B port of the CAM module, and pull CAM_B_rd_addr_en high for a read operation, and obtain a read at the CAM_B_rd_data port Data (that is, the storage address (ram_addr_one_hot) of the one-hot code of the cache line in the data RAM.
  • CAM_B_rd_data When CAM_B_rd_data is 0, it is considered to be a write cache miss (miss); when CAM_B_rd_data is not 0, it is considered to be a write cache hit (hit) ).
  • RAM_B_rd_addr log2(ram_addr_one_hot);
  • RAM_B_rd_addr_en high to read out RAM_B_rd_data data.
  • the CPU issues a write operation with the address 16’h1000.
  • next write address indicates the data_ram address to be replaced when a write miss occurs;
  • addr_cnt indicates the number of jumps to add 1 to the address.
  • RAM_B_rd_addr data_ram_next_addr
  • the current address of data_ram is 1, and a write miss occurs at this time, data_ram_next_addr addresses downwards, and the write flag bit of address 14 is found to be 0 by reading data, and address 14 is used as the replacement address of the cache line at this time.
  • the address of data_ram in the last operation is 2.
  • data_ram_next_addr addresses downwards.
  • the write flag is always 1.
  • CAM_A_wr_addr ⁇ Cpu_addr, data_ram_next_addr_one ⁇ ;
  • data_ram_next_addr_one is the one-hot code address of data_ram_next_addr
  • the high bit is the address sent by the CPU
  • the low bit is the one-hot code address of the cache line to be replaced in RAM.
  • the CPU issues a write operation with the address 16’h1000.
  • the replacement address of the cache line is calculated as the binary address 1, and the write address of the A port of the CAM is 32’h1000_0002, and the write data is 1.
  • the read cache operation includes two situations: a read cache hit (hit) and a read cache miss (miss).
  • a read cache hit hit
  • a read cache miss miss
  • Cpu_req When Cpu_req is 1, that is, a request is initiated, and cpu_type is a load type read operation, connect Cpu_addr to the read address terminal (CAM_B_rd_addr) of the B port of the CAM module, and pull CAM_B_rd_addr_en high to perform a read operation, and obtain a read at the CAM_B_rd_data port Data (that is, the storage address (ram_addr_one_hot) of the one-hot code of the cache line in the data RAM.
  • CAM_B_rd_data When CAM_B_rd_data is 0, it is considered that the read cache miss (miss); when CAM_B_rd_data is not 0, it is considered that the read cache hit (hit) ).
  • RAM_B_rd_addr log2(ram_addr_one_hot);
  • the CPU issues a read operation with the address 16’h1000. First connect this address to the address line of the B port of the CAM, read the data 16'b0000_0000_0000_1000, convert it into binary data 3, use 3 as the read address of the B port of the data RAM, read the Cache line data, and then After the cache line data, read and write flag position is set to 1, it is written into the address 3 space of the RAM through the A port of the RAM.
  • next read address indicates the data_ram address to be replaced when a read miss occurs;
  • addr_cnt_rd indicates the number of address plus 1 jumps.
  • RAM_B_rd_addr data_ram_next_addr_rd
  • addr_cnt_rd addr_cnt_rd+1;
  • address 1 of the current data_ram when a read miss occurs at this time, data_ram_next_addr_rd is addressed downward, and the write flag bit of address 14 is found to be 0 by reading data, and address 14 is used as the replacement address of the cache line at this time.
  • the address of data_ram in the last operation is 2, and a write miss occurs at this time, and data_ram_next_addr_rd is addressed downwards. After reading data, it is found that the write flag is always 1, and the read flag is at address 14, then use address 14 as The replacement address of the cache line.
  • the address of data_ram in the last operation is 2, and a write miss occurs at this time, and data_ram_next_addr_rd addresses downwards, and it is found that both the read and write flags are always 1 by reading data.
  • the CPU When sending a read operation miss, the CPU will read the corresponding data from the main memory, cache the returned data in the replacement address space of the data RAM, and then send it back to the CPU.
  • the write flag position is 1, and the read flag position is 0, and write it into the replacement address space of the data RAM together, and assign this newly generated signal to the write data RAM_A_wr_data signal of the A port of DATA_RAM , and pull RAM_A_wr_addr_en high at the same time, RAM_A_wr_addr is the above replacement address.
  • CAM_A_wr_addr ⁇ Cpu_addr, data_ram_next_addr_one_rd ⁇ ;
  • data_ram_next_addr_one_rd is the one-hot code address of data_ram_next_addr_rd;
  • the high bit is the address sent by the CPU
  • the low bit is the one-hot code address of the cache line to be replaced in RAM.
  • the CPU issues a read operation with the address 16’h1000.
  • the replacement address of the cache line is calculated to be the binary address 1.
  • the write address of the A port of the CAM is 32’h1000_0002, and the write data is 1.
  • the data reading and writing method pre-sets the reading and writing flag bits for each data storage address of the data memory in the cache to mark whether the corresponding stored data has been read or written.
  • the read and write data misses the cache and there is no free storage address in the data memory in the cache, it can traverse from the initial storage address of the data memory until it traverses to the storage address with an unread flag. It means that the data information stored in this storage address has never been read, and the usage rate is low.
  • the embodiment of the present application also provides a data reading and writing device, please refer to FIG. 3, which is a schematic structural diagram of a data reading and writing device provided in the embodiment of the present application.
  • the data reading and writing device may include:
  • the read-write data determination module 1 is used to determine the read-write data according to the data read-write request
  • the storage address traversal module 2 is used to start traversing from the initial storage address of the data memory when the read and write data misses the cache, and the data memory set in the cache does not have a free storage address;
  • the first data writing module 3 is used to write the read and write data into the storage address with the unread mark when traversing to the storage address with the unread mark;
  • the second data writing module 4 is used to write the read and write data into the previous storage address of the initial storage address when the storage address with the unread flag has not been traversed.
  • the data reading and writing device pre-sets the reading and writing flag bits for each data storage address of the data storage in the cache, and is used to mark whether the corresponding stored data has been read or written.
  • the read and write data misses the cache and there is no free storage address in the data memory in the cache, it can traverse from the initial storage address of the data memory until it traverses to the storage address with an unread flag. It means that the data information stored in this storage address has never been read, and the usage rate is low.
  • the data reading and writing device may also include a cache hit judging module, which is used to input the read and write data into the content addressable memory in the cache; when receiving the content addressable memory according to the read When writing the address information fed back by the data, it is determined that the read and write data hits the cache; when the address information fed back by the content addressable memory according to the read and write data is not received, it is determined that the read and write data misses the cache.
  • a cache hit judging module which is used to input the read and write data into the content addressable memory in the cache; when receiving the content addressable memory according to the read When writing the address information fed back by the data, it is determined that the read and write data hits the cache; when the address information fed back by the content addressable memory according to the read and write data is not received, it is determined that the read and write data misses the cache.
  • the data reading and writing device may also include an address information storage module, which is used to write the reading and writing data into the storage address where the unread flag exists, or to write the reading and writing data into the initial storage After the last storage address of the address, the storage address of the read-write data in the data memory and the storage address in the main memory are both updated to the content addressable memory.
  • an address information storage module which is used to write the reading and writing data into the storage address where the unread flag exists, or to write the reading and writing data into the initial storage After the last storage address of the address, the storage address of the read-write data in the data memory and the storage address in the main memory are both updated to the content addressable memory.
  • the data reading and writing device may also include a free storage address judging module, which is used to start traversing from the initial storage address of the data storage; when traversing to a storage address with an unwritten flag, determine the There is a free storage address, and the storage address with the unwritten flag is used as the free storage address; when the storage address with the unwritten flag is not traversed, it is determined that there is no free storage address in the data memory.
  • a free storage address judging module which is used to start traversing from the initial storage address of the data storage; when traversing to a storage address with an unwritten flag, determine the There is a free storage address, and the storage address with the unwritten flag is used as the free storage address; when the storage address with the unwritten flag is not traversed, it is determined that there is no free storage address in the data memory.
  • the data reading and writing device may also include a first flag setting module, which is used to write the reading and writing data into the storage address where the unread flag exists, or write the reading and writing data to After the previous storage address of the initial storage address, the written flag and the unread flag are set for the storage address of the read and write data in the data memory.
  • a first flag setting module which is used to write the reading and writing data into the storage address where the unread flag exists, or write the reading and writing data to After the previous storage address of the initial storage address, the written flag and the unread flag are set for the storage address of the read and write data in the data memory.
  • the data reading and writing device may further include a second flag bit setting module, which is used for when the reading and writing data hits the cache, if the reading and writing data is specifically read data, then the read data is in the data memory Set the read flag for the storage address in ; if the read and write data is specifically write data, set the written flag for the storage address of the write data in the data memory.
  • a second flag bit setting module which is used for when the reading and writing data hits the cache, if the reading and writing data is specifically read data, then the read data is in the data memory Set the read flag for the storage address in ; if the read and write data is specifically write data, set the written flag for the storage address of the write data in the data memory.
  • the data reading and writing device may also include a third data writing module, which is used to write the reading and writing data into the idle address when the reading and writing data misses the cache and there is a free storage address in the data memory. storage address.
  • the embodiment of the present application also provides a data reading and writing device, please refer to FIG. 4, which is a schematic structural diagram of a data reading and writing device provided in the embodiment of the present application.
  • the data reading and writing device may include:
  • the processor is used to implement the steps of any one of the above-mentioned data reading and writing methods when executing the computer program.
  • the data reading and writing device may include: a processor 10 , a memory 11 , a communication interface 12 and a communication bus 13 .
  • the processor 10, the memory 11, and the communication interface 12 all complete mutual communication through the communication bus 13.
  • the processor 10 may be a central processing unit (Central Processing Unit, CPU), an application-specific integrated circuit, a digital signal processor, a field programmable gate array, or other programmable logic devices.
  • CPU Central Processing Unit
  • application-specific integrated circuit e.g., an application-specific integrated circuit
  • digital signal processor e.g., a digital signal processor
  • field programmable gate array e.g., a field programmable gate array
  • the processor 10 can call the program stored in the memory 11, and the processor 10 can execute the operations in the embodiment of the data reading and writing method.
  • the memory 11 is used to store one or more programs.
  • the programs may include program codes, and the program codes include computer operation instructions.
  • the memory 11 stores at least programs for realizing the following functions:
  • the memory 11 may include a program storage area and a data storage area, wherein the program storage area may store an operating system and at least one application program required by a function; the data storage area may store The data created.
  • the memory 11 may include a high-speed random access memory, and may also include a non-volatile memory, such as at least one magnetic disk storage device or other volatile solid-state storage devices.
  • the communication interface 12 may be an interface of a communication module, and is used for connecting with other devices or systems.
  • the structure shown in FIG. 4 does not constitute a limitation on the data read-write device in the embodiment of the present application.
  • the data read-write device may include more or less components, or combinations of certain components.
  • the present application also provides a computer-readable storage medium, on which a computer program is stored, and when the computer program is executed by a processor, the steps of any one of the above-mentioned data reading and writing methods can be realized.
  • the computer-readable storage medium may include: U disk, mobile hard disk, read-only memory (Read-Only Memory, ROM), random access memory (Random Access Memory, RAM), magnetic disk or optical disk, etc., which can store program codes. medium.
  • each embodiment in the description is described in a progressive manner, each embodiment focuses on the difference from other embodiments, and the same and similar parts of each embodiment can be referred to each other.
  • the description is relatively simple, and for relevant details, please refer to the description of the method part.
  • RAM random access memory
  • ROM read-only memory
  • EEPROM electrically programmable ROM
  • EEPROM electrically erasable programmable ROM
  • registers hard disk, removable disk, CD-ROM or Any other form of storage medium known in the technical field.

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Abstract

本申请公开了一种数据读写方法，包括根据数据读写请求确定读写数据；当所述读写数据未命中缓存，且设置于所述缓存中的数据存储器不存在空闲存储地址时，从所述数据存储器的初始存储地址开始遍历；当遍历到存在未读标志的存储地址时，将所述读写数据写入存在所述未读标志的存储地址中；当未遍历到存在未读标志的存储地址时，将所述读写数据写入所述初始存储地址的上一存储地址中。应用本申请所提供的技术方案，可以在有效保证较高缓存命中率的同时，提高数据读写效率。本申请还公开了一种数据读写装置、设备及计算机可读存储介质，均具有上述有益效果。

Description

数据读写方法、装置及相关设备
相关申请的交叉引用
本申请要求于2022年02月18日提交中国专利局，申请号为202210148645.4，申请名称为“一种数据读写方法、装置及相关设备”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及数据存储技术领域，特别涉及一种数据读写方法，还涉及一种数据读写装置、设备及计算机可读存储介质。
背景技术
Cache(缓冲存储器/缓存)是介于CPU(Central Processing Unit，中央处理器)和主存之间的小容量高速存储器，存取速度比主存快，是为了解决CPU和主存之间速度不匹配而采用的一项重要技术。它能高速地向CPU提供指令和数据，加快程序的执行速度。
当CPU在Cache中找不到需要的数据时，此时就需要去主存中获取相应的数据，并在Cache中进行替换。Cache的替换策略一般可分为以下三大类：(1)基于先进先出的替换；(2)随机替换；(3)基于Cache历史信息的最近最少使用法或其他衍生方法。其中，前两种方法不需要考虑Cache的实际使用情况，优先替换首先写入Cache的数据或完全随机替换，但是，这种实现方式缓存命中率较低，在一定程度上降低了数据读写效率；最后一种方法虽然缓存命中率较高，但其实现过程需要依赖于较为繁琐的信息统计和算法计算，以及较为复杂的硬件结构，同样会降低数据读写效率。
因此，如何在有效保证较高缓存命中率的同时，提高数据读写效率是本领域技术人员亟待解决的问题。
发明内容
本申请实施例的目的是提供一种数据读写方法，该数据读写方法可以在有效保证较高缓存命中率的同时，提高数据读写效率；本申请实施例的另一目的是提供一种数据读写装置、设备及计算机可读存储介质，均具有上述有益效果。
本申请实施例提供了一种数据读写方法，包括：
根据数据读写请求确定读写数据；
当读写数据未命中缓存，且设置于缓存中的数据存储器不存在空闲存储地址时，从数据存储器的初始存储地址开始遍历；
当遍历到存在未读标志的存储地址时，将读写数据写入存在未读标志的存储地址中；
当未遍历到存在未读标志的存储地址时，将读写数据写入初始存储地址的上一存储地址中。
可选的，判断读写数据是否命中缓存，包括：
将读写数据输入设置于缓存中的内容可寻址存储器；
当接收到内容可寻址存储器根据读写数据反馈的地址信息时，确定读写数据命中缓存；
当未接收到内容可寻址存储器根据读写数据反馈的地址信息时，确定读写数据未命中缓存。
可选的，确定读写数据命中缓存之后，还包括：
在读写数据为写数据的情况下，将独热码CAM_B_rd_data转换为二进制信息并连接至DATA_RAM的B端口的RAM_B_rd_addr，其中，CAM_B_rd_data为CAM的B端口读数据，CAM为内容可寻址存储器，RAM_B_rd_addr为RAM的B端口读地址，数据存储器包括RAM；
将RAM_B_rd_addr_en拉高，将RAM_B_rd_data数据读出，其中，RAM_B_rd_addr_en为RAM的B端口读使能，RAM_B_rd_data为RAM的B端口读数据；
将中央处理器CPU发送的写数据部分代替RAM_B_rd_data中对应的部分，其他部分保持不变，写标志位置为1，读标志位置为0，并将该新生成的信号赋给DATA_RAM的A端口的写数据RAM_A_wr_data信号，同时将RAM_A_wr_addr_en拉高，并将B端口的地址赋给A端口，把数据和标志位写入数据RAM中，其中，RAM_A_wr_data为RAM的A端口写数据，RAM_A_wr_addr_en为RAM的A端口写使能。
可选的，确定读写数据命中缓存之后，还包括：
在读写数据为读数据的情况下，将独热码CAM_B_rd_data转换为二进制信息并连接至DATA_RAM的B端口的RAM_B_rd_addr，其中，CAM_B_rd_data为CAM的B端口读数据，CAM为内容可寻址存储器，RAM_B_rd_addr为RAM的B端口读地址，数据存储器包括RAM；
将RAM_B_rd_addr_en拉高，将RAM_B_rd_data数据读出，然后返回给中央处理器CPU，其中，RAM_B_rd_addr_en为RAM的B端口读使能，RAM_B_rd_data为RAM的B端口读数据；
将读出的数据缓存行cache line保持不变，写标志位置为1，读标志位置为1，并将该新生成的信号赋给DATA_RAM的A端口的写数据RAM_A_wr_data信号，同时将RAM_A_wr_addr_en拉高，并将B端口的地址赋给A端口，把数据和标志位写入数据RAM中，其中，RAM_A_wr_data为RAM的A端口写数据，RAM_A_wr_addr_en为RAM的A端口写使能。
可选的，将读写数据输入设置于缓存中的内容可寻址存储器，包括：
将Cpu_addr连接到数据存储器的B端口的读地址端CAM_B_rd_addr，其中，Cpu_addr为中央处理器CPU的指令执行地址，CAM_B_rd_addr为CAM的B端口读地址，CAM为内容可寻址存储器；
将CAM_B_rd_addr_en拉高进行读操作，在CAM_B_rd_data端口获得读写数据在数据存储器中独热码的存储地址ram_addr_one_hot，其中，CAM_B_rd_addr_en为CAM的B端口读使能。
可选的，将读写数据写入存在未读标志的存储地址中之后，或将读写数据写入初始存储地址的上一存储地址中之后，还包括：
将读写数据在数据存储器中的存储地址和在主存中的存储地址一同更新至内容可寻址存储器。
可选的，判断数据存储器是否存在空闲存储地址，包括：
从数据存储器的初始存储地址开始遍历；
当遍历到存在未写标志的存储地址时，确定数据存储器存在空闲存储地址，并将存在未写标志的存储地址作为空闲存储地址；
当未遍历到存在未写标志的存储地址时，确定数据存储器不存在空闲存储地址。
可选的，在从数据存储器的初始存储地址开始遍历之前，还包括：
为数据存储器中的各个存储地址设置读写标志位，其中，读写标志位包括读标志位和写标志位，读标志位用于设定已读标志或者未读标志，写标志位用于设定已写标志或者未写标志，已读标志用于表示所对应的存储地址中所存储的数据信息已经被读取过，未读标志用于表示对应的存储地址所存储的数据信息在写入之后并未被读取过，已写标志用于表示所对应的存储地址存储有数据信息，未写标志用于表示对应的存储地址为空闲存储地址。
可选的，将读写数据写入存在未读标志的存储地址中之后，或将读写数据写入初始存储地址的上一存储地址中之后，还包括：
为读写数据在数据存储器中的存储地址设置已写标志和未读标志。
可选的，当读写数据命中缓存时，方法还包括：
若读写数据具体为读数据，则为读数据在数据存储器中的存储地址设置已读标志；
若读写数据具体为写数据，则为写数据在数据存储器中的存储地址设置已写标志。
可选的，数据读写方法还包括：
当读写数据未命中缓存，且数据存储器存在空闲存储地址时，将读写数据写入空闲存储地址。
可选的，在将读写数据写入空闲存储地址之前，还包括：
在读写数据为写数据的情况下，将data_ram_next_addr加1，其中，data_ram_next_addr为下一次写入地址；
将data_ram_next_addr连接到RAM_B_rd_addr，并将RAM_B_rd_addr_en拉高进行读操作，addr_cnt_rd也进行加1操作，其中，RAM_B_rd_addr为RAM的B端口读地址，数据存储器包括RAM，RAM_B_rd_addr_en为RAM的B端口读使能，addr_cnt_rd为读地址搜索次数；
判断此时的写标志位RAM_B_rd_data[line_size]的取值，其中， RAM_B_rd_data为RAM的B端口读数据；
在写标志位的取值为1的情况下，再次执行对data_ram_next_addr加1的操作；
在写标志位的取值为0时，将data_ram_next_addr确定为写入读写数据的空闲存储地址。
可选的，在将读写数据写入空闲存储地址之前，还包括：
在读写数据为读数据的情况下，将data_ram_next_addr_rd加1；
将data_ram_next_addr_rd连接到RAM_B_rd_addr，并将RAM_B_rd_addr_en拉高进行读操作，addr_cnt_rd也进行加1操作，其中，RAM_B_rd_addr为RAM的B端口读地址，数据存储器包括RAM，RAM_B_rd_addr_en为RAM的B端口读使能，addr_cnt_rd为读地址搜索次数；
判断此时的写标志位RAM_B_rd_data[line_size]的取值，其中，RAM_B_rd_data为RAM的B端口读数据；
在写标志位的取值为1的情况下，再次执行对data_ram_next_addr_rd加1的操作；
在写标志位的取值为0时，将data_ram_next_addr_rd确定为写入读写数据的空闲存储地址。
可选的，在将读写数据写入空闲存储地址之后，方法还包括：
将内容可寻址存储器的A端口的写使能和写数据置为1，同时将写地址按如下赋值：
CAM_A_wr_addr＝{Cpu_addr，data_ram_next_addr_one_rd}；
data_ram_next_addr_one_rd为data_ram_next_addr_rd的独热码地址，data_ram_next_addr_one_rd＝16‘b1＜＜data_ram_next_addr_rd，其中，高位为CPU发送的地址，低位为需要替换的读写数据在内容可寻址存储器的存储独热码地址，CAM_A_wr_addr为CAM的A端口写地址，CAM为内容可寻址存储器，Cpu_addr为中央处理器CPU的指令执行地址。
可选的，在从数据存储器的初始存储地址开始遍历之前，方法还包括：
判断读写数据是否命中缓存；
在读写数据命中缓存的情况下，对缓存中进行数据读写；
在读写数据未命中缓存的情况下，判断数据存储器中是否存在空闲地址；在数据存储器中存在空闲地址的情况下，将读写数据写入空闲地址；在数据存储器中不存在空闲地址的情况下，从数据存储器的初始存储地址开始遍历，查询存在未读标志的存储地址，其中，初始存储地址为预先设定的存储地址。
可选的，将读写数据写入存在未读标志的存储地址中，包括：
在读写数据为读数据的情况下，向主存获取读数据；将读数据写入存在未读标志的存储地址；
在读写数据为写数据的情况下，将写数据写入存在未读标志的存储地址和主存中。
可选的，将读写数据写入初始存储地址的上一存储地址中，包括：
在读写数据为读数据的情况下，向主存获取读数据；将读数据写入初始存储地址的上一存储地址中；
在读写数据为写数据的情况下，将写数据写入初始存储地址的上一存储地址和主存中。
本申请实施例还公开了一种数据读写装置，包括：
读写数据确定模块，用于根据数据读写请求确定读写数据；
存储地址遍历模块，用于当读写数据未命中缓存，且设置于缓存中的数据存储器不存在空闲存储地址时，从数据存储器的初始存储地址开始遍历；
第一数据写入模块，用于当遍历到存在未读标志的存储地址时，将读写数据写入存在未读标志的存储地址中；
第二数据写入模块，用于当未遍历到存在未读标志的存储地址时，将读写数据写入初始存储地址的上一存储地址中。
本申请实施例还公开了一种数据读写设备，包括：
存储器，用于存储计算机程序；
处理器，用于执行计算机程序时实现如上的任一种数据读写方法的步骤。
本申请实施例还公开了一种计算机可读存储介质，计算机可读存储介质上存储有计算机程序，计算机程序被处理器执行时实现如上的任一种数据读写方法的步骤。
本申请实施例所提供的一种数据读写方法，包括根据数据读写请求确定读写数据；当读写数据未命中缓存，且设置于缓存中的数据存储器不存在空闲存储地址时，从数据存储器的初始存储地址开始遍历；当遍历到存在未读标志的存储地址时，将读写数据写入存在未读标志的存储地址中；当未遍历到存在未读标志的存储地址时，将读写数据写入初始存储地址的上一存储地址中。
应用本申请实施例所提供的技术方案，预先为缓存中数据存储器的各个数据存储地址设置读写标志位，用于标志对应的存储数据是否已经发生过读写操作，由此，在数据读写过程中，面对读写数据未命中缓存且缓存中数据存储器不存在空闲存储地址的情况下，可以从数据存储器的初始存储地址开始遍历，直至遍历到存在未读标志的存储地址，说明该存储地址中所存储的数据信息从未被读取过，使用率较低，此时，则可以直接将读写数据写入至该存在未读标志的存储地址中；当无法遍历到存在未读标志的存储地址时，则可以直接将读写数据写入初始存储地址的上一存储地址中，也即遍历到的数据存储器中的最后一个存储地址，以有效保证将读写数据存储至缓存。可见，该种实现方式可以在有效保证较高缓存命中率的同时，提高数据读写效率。
本申请实施例所提供的一种数据读写装置、设备及计算机可读存储介质，均具有上述有益效果，在此不再赘述。
附图说明
为了更清楚地说明现有技术和本申请实施例中的技术方案，下面将对现有技术和本申请实施例描述中需要使用的附图作简要的介绍。当然，下面有关本 申请实施例的附图描述的仅仅是本申请中的一部分实施例，对于本领域普通技术人员来说，在不付出创造性劳动的前提下，还可以根据提供的附图获得其他的附图，所获得的其他附图也属于本申请的保护范围。
图1为本申请实施例所提供的一种数据读写方法的流程示意图；
图2为本申请实施例所提供的一种数据读写系统的结构示意图；
图3为本申请实施例所提供的一种数据读写装置的结构示意图；
图4为本申请实施例所提供的一种数据读写设备的结构示意图。
具体实施方式
本申请实施例的核心是提供一种数据读写方法，该数据读写方法可以在有效保证较高缓存命中率的同时，提高数据读写效率；本申请实施例的另一核心是提供一种数据读写装置、设备及计算机可读存储介质，也具有上述有益效果。
为了对本申请实施例中的技术方案进行更加清楚、完整地描述，下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行介绍。显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
本申请实施例提供了一种数据读写方法。
请参考图1，图1为本申请实施例所提供的一种数据读写方法的流程示意图，该数据读写方法可包括：
S101：根据数据读写请求确定读写数据；
本步骤旨在实现读写数据的确定，即根据数据读写请求确定相应的读写数据，也就是说，当接收到数据读取请求时，即可根据该数据读取请求确定所需读取的数据信息；当接收到数据写入请求时，即可根据该数据写入请求确定所需存储的数据信息。其中，数据读写请求可以由技术人员基于相应的前端设备发起。
S102：当读写数据未命中缓存，且设置于缓存中的数据存储器不存在空闲存储地址时，从数据存储器的初始存储地址开始遍历；
本步骤旨在实现数据存储器中存储地址的遍历，以便于查找到存在未读标志的存储地址。在缓存中，可以通过设置数据存储器实现数据信息的存储，其中，数据存储器的类型并不影响本技术方案的实施，例如，可以采用RAM(Random Access Memory，随机存取存储器)实现，本申请对此不做限定。在此基础上，在基于数据读写请求确定读写数据之后，首先判断读写数据是否命中缓存，如若命中缓存，则可以直接从缓存中进行数据读取，如若未命中缓存，则可以判断数据存储器中是否存在空闲存储地址，即没有存储任何数据的存储地址，若存在，则可以直接将读写数据写入该空闲地址，以提高下一次读写相同数据的命中率，若不存在，则可以从数据存储器的初始存储地址开始遍 历，以求查询获得存在未读标志的存储地址。其中，初始存储地址为预先设定的一个存储地址，由技术人员自定义设置即可，本申请对此不做限定。
S103：当遍历到存在未读标志的存储地址时，将读写数据写入存在未读标志的存储地址中；
可以理解的是，在读写数据未命中缓存且数据存储器不存在空闲存储地址的情况下，如若遍历到存在未读标志的存储地址，说明该存储地址中所存储的数据信息在写入该存储地址之后并未被读取过，即使用率较低，因此，则可以将读写数据替换掉该存储地址中所存储的原有数据，即直接将读写数据写入该存在未读标志的存储地址中，由此，实现将读写数据写入至缓存，完成缓存的替换更新。
S104：当未遍历到存在未读标志的存储地址时，将读写数据写入初始存储地址的上一存储地址中。
可以理解的是，在读写数据未命中缓存且数据存储器不存在空闲存储地址的情况下，如若从初始存储地址遍历到最后一个存储地址，都没有遍历到存在未读标志的存储地址，说明数据存储器中所存储的所有数据的使用率都相对较高，此时，为实现将读写数据写入至缓存，则可以直接将读写数据替换掉最后一个存储地址(即上述初始存储地址的上一存储地址)中所存储的原有数据，即直接将读写数据写入至该最后一个存储地址中，由此，实现将读写数据写入至缓存，完成缓存的替换更新。
其中，由于是在遍历到最后一个存储地址时才可以确定数据存储器中是否具有存在未读标志的存储地址，因此，选择将读写数据直接写入数据存储器的最后一个存储地址中，可以有效保证读写数据及时写入缓存，提高写入效率。
可见，本申请实施例所提供的数据读写方法，预先为缓存中数据存储器的各个数据存储地址设置读写标志位，用于标志对应的存储数据是否已经发生过读写操作，由此，在数据读写过程中，面对读写数据未命中缓存且缓存中数据存储器不存在空闲存储地址的情况下，可以从数据存储器的初始存储地址开始遍历，直至遍历到存在未读标志的存储地址，说明该存储地址中所存储的数据信息从未被读取过，使用率较低，此时，则可以直接将读写数据写入至该存在未读标志的存储地址中；当无法遍历到存在未读标志的存储地址时，则可以直接将读写数据写入初始存储地址的上一存储地址中，也即遍历到的数据存储器中的最后一个存储地址，以有效保证将读写数据存储至缓存。可见，该种实现方式可以在有效保证较高缓存命中率的同时，提高数据读写效率。
在本申请的一个实施例中，判断读写数据是否命中缓存，可以包括：将读写数据输入设置于缓存中的内容可寻址存储器；当接收到内容可寻址存储器根据读写数据反馈的地址信息时，确定读写数据命中缓存；当未接收到内容可寻址存储器根据读写数据反馈的地址信息时，确定读写数据未命中缓存。
本申请实施例提供了一种缓存命中判断方法，即判断读写数据是否命中缓存，该方法可基于内容可寻址存储器实现。
首先，请参考图2，图2为本申请实施例所提供的一种数据读写系统的结 构示意图，该数据读写系统主要包括CPU、Cache(缓存)以及Main memory(主存)，在Cache中，其主要包括CU(控制单元)、CAM(Content-Addressable Memory，内容寻址存储器)、RAM_DATA(存储数据的RAM，即上述数据存储器)等。其中，CU主要完成Cache命中判断、Cache替换策略控制、生成CAM单元控制信号、生成RAM_DATA单元控制信号等；CAM单元主要用于根据地址内容寻址数据内容；RAM_DATA主要用于存储cache line(缓存行)数据。基于图2，请参考表1，表1为本申请实施例所提供的一种关键信号组描述表：
表1 一种关键信号组描述表
Figure PCTCN2022134789-appb-000001
其中，CAM与RAM不同，其是通过输入的数据内容反查其对应的地址数据，并输出。在使用RAM时，是利用输入的地址，读取该地址位置上所存储的数据；而在使用CAM时，是通过输入的数据同时与CAM内部已经存储的数据相比较，如果有相同内容的话，输出相同数据所存储的地址数据和查找成功信号，反之，不输出查找成功信号。CAM的结构与工作原理如下：
CAM的主要部分为一个双端口随机存取存储器，两个数据端口位宽不同。 以一个容量为4096bit的随机存储器为例，可以将A端口配置为数据位宽为1bit，数据深度为4096(地址即为0-4095)；将B端口配置为数据位宽4bit，数据深度为256(地址为0-255)。
其中，对于写操作：例如，如果需要向地址0010(即二进制2)写入数据“00000111”(即二进制7)时，RAM的A端口的12位地址由高8位数据“00000111”和低4位“0100”(独热码2)组合而成。A端口的写使能和数据位均置为1，则实际上将“1”写入地址为074H单元中。CAM写入时，并不是真的把8位数据存储起来，而是在8位数据所对应的存储行做一记录。
其中，对于读操作：在端口B完成读操作，CAM的读操作实际上就是数据匹配过程。(在B端口读数据时，地址0对应的数据即为端口A的地址0-3的数据，地址1对应的数据即为端口A的地址4-7的数据)将被检索内容连接到端口B的地址线(ADDRB)。如果数据之前被写入CAM某地址，在读时就会输出相应的4位匹配地址，否则输出全0。如上述举例中，当需要搜索数据“00000111”(即二进制7)时，将7连接到端口B的地址线(ADDRB)，输出值即为“0100”(独热码2)。
基于以上阐述，请参考表2，表2为本申请实施例所提供的一种编码方式转换表：
表2 一种编码方式转换表
Figure PCTCN2022134789-appb-000002
在判断读写数据是否命中缓存的过程中，则可以将读写数据输入CAM，如 若CAM基于该读写数据查询到其对应的地址信息，则说明RAM中存储有该读写数据，即读写数据命中缓存；如若CAM未能基于读写数据查询到其对应的地址信息，则说明PAM中未存储有该读写数据，即读写数据未命中缓存。
在本申请的一个实施例中，上述将读写数据写入存在未读标志的存储地址中之后，或将读写数据写入初始存储地址的上一存储地址中之后，还可以包括：将读写数据在数据存储器中的存储地址和在主存中的存储地址一同更新至内容可寻址存储器。
本申请实施例所提供的数据读写方法旨在实现内容可寻址存储器的更新，以有效保证缓存命中判断结果的准确性。在将读写数据写入缓存之后，无论是写入存在未读标志的存储地址，还是写入初始存储地址的上一存储地址，均可以将读写数据在数据存储器中的存储地址以及在主存中的存储地址一同更新至内容可寻址存储器，以便于进行后续新的缓存命中判断。
在本申请的一个实施例中，判断数据存储器是否存在空闲存储地址，可以包括：从数据存储器的初始存储地址开始遍历；当遍历到存在未写标志的存储地址时，确定数据存储器存在空闲存储地址，并将存在未写标志的存储地址作为空闲存储地址；当未遍历到存在未写标志的存储地址时，确定数据存储器不存在空闲存储地址。
本申请实施例提供了一种判断数据存储器中是否存在空闲存储地址的判断方法，该判断方法可根据存储地址的读写标志位实现。可以预先为各个存储地址设置读写标志位，用于设定已读标志、已写标志、未读标志、未写标志，那么，在将数据信息写入相应的存储地址之后，则可以为其设置已写标志，表示该存储地址存储有数据信息。在此基础上，在判断数据存储器是否存在空闲存储地址时，同样可以从数据存储器的初始存储地址开始遍历，如若遍历到存在未写标志的存储地址，则说明数据存储器存在空闲存储地址，该存在未写标志的存储地址即为空闲存储地址，且可以将读写数据直接写入该空闲存储地址，无需再继续进行存储地址的遍历；如若直至最后一个存储地址都未能遍历到存在未写标志的存储地址(相当于全部存储地址均为已写标志)，则可以确定数据存储器不存在空闲存储地址。
在本申请的一个实施例中，上述将读写数据写入存在未读标志的存储地址中之后，或将读写数据写入初始存储地址的上一存储地址中之后，还可以包括：为读写数据在数据存储器中的存储地址设置已写标志和未读标志。
本申请实施例所提供的数据读写方法旨在实现读写标志位的设置。可以理解的是，为有效保证上述空闲存储地址判断结果的准确性，可以对存储地址的读写标志位进行实时更新，在将读写数据写入缓存之后，无论是写入存在未读标志的存储地址，还是写入初始存储地址的上一存储地址，也无需考虑存储地址之前的读写标志位的状态，均可以为读写数据在数据存储地址中的存储地址设置已写标志和未读标志，其中，已写标志用于表示当前存储位置已经存储有数据信息，未读标志用于表示当前存储位置所存储的数据信息在写入之后并未被读取过。
在本申请的一个实施例中，当读写数据命中缓存时，该方法还可以包括：若读写数据具体为读数据，则为读数据在数据存储器中的存储地址设置已读标志；若读写数据具体为写数据，则为写数据在数据存储器中的存储地址设置已写标志。
本申请实施例所提供的数据读写方法旨在针对不同类型的数据(读数据和写数据)进行读写标志位的设定。
对于读数据，当读数据命中缓存时，则无需向主存获取该读数据，直接从缓存中读取即可，在此基础上，在从缓存中读取获得该读数据之后，则可以为该读数据在数据存储器中的存储地址设置已读标志，表示该存储地址中所存储的数据信息已经被读取过。当然，当读数据未命中缓存时，则需要向主存获取该读数据，并将读数据同时存储至缓存中，此时，可为读数据在数据存储器中的存储地址设置已写标志和未读标志。
对于写数据，当写数据命中缓存时，说明写数据已经存储于数据存储器，此时，可以为其在数据存储器中的存储地址设置已写标志，并根据读取情况设置读标志位。可以理解的是，当写数据命中缓存时，说明该写数据已经存储于主存，此时则无需再次将其写入主存。当然，当写数据未命中缓存时，可以在将该写数据存储至主存的同时，也将其写入缓存，并在写入缓存之后，为其在数据存储器中的存储地址设置已写标志和未读标志。
在本申请的一个实施例中，该方法还可以包括：当读写数据未命中缓存，且数据存储器存在空闲存储地址时，将读写数据写入空闲存储地址。
可以理解的是，在读写数据未命中缓存，但缓存的数据存储器中存在空闲存储地址时，则可以直接将读写数据写入该空闲存储地址中，无需再进行存储地址的遍历以查询可以存储该读写数据的存储地址，从而可以有效保证数据读写效率。
在上述各实施例的基础上，本申请实施例提供了一种缓存替换策略，策略实现如下：
1、将cache line数据和对应的cache line读写信息存储到RAM的同一个地址中；将此cache line在主存中的地址和在RAM中的地址信息存储在CAM中。
2、当读操作命中缓存时，将RAM中对应的读标志位置为1(不考虑原有状态)。
3、当写操作命中缓存时，将RAM中对应的写标志位置为1(不考虑原有状态)，并将写数据更新到主存中。
4、当读操作未命中缓存时，对cache line进行替换，通过在原有RAM的地址加1读取后续RAM地址中的数据和读写标志位，当写标志位为0时，说明此存储位置为空，将从主存读取的cache line数据写于此位置，并将写标志位置为1，同时将此cache line在主存中的地址和在RAM中的地址信息更新在CAM中；当写标志位为1时，地址继续加1跳转，直到找到下一个写标志位为 0的为止；当整个RAM全部已经存储了数据时，即地址已经又跳转回了起始地址时，此时再次将地址加1进行一轮循环判断，当读标志位为0时，说明此cache line的数据在写入后并没有被再读取过，此时将从主存读取的cache line数据写于此位置，并将写标志位置为1，当读标志位为1时，地址继续加1跳转；当再次跳转回起始地址时，此时意味着整个存储空间的读写标志位均为1，此时将起始地址的前一个地址作为替换地址，将从主存读取的cache line数据写于此位置，并将写标志位置为1。并且，确定替换地址的同时将此cache line在主存中的地址和在RAM中的地址信息更新在CAM中。
5、当写操作未命中缓存时，对cache line进行替换，通过在原有RAM的地址加1读取后续RAM地址中的数据和写标志位，当写标志位为0时，说明此存储位置为空，将CPU下发的写的cache line数据写于此位置，并将写标志位置为1，同时将此cache line在主存中的地址和在RAM中的地址信息更新在CAM中；当写标志位为1时，地址继续加1跳转，直到找到下一个写标志位为0的为止；当整个RAM全部已经存储了数据时，即地址已经跳转了整个地址空间，此时地址跳转回起始地址前一个地址，将CPU下发的写的cache line数据写于此位置(覆盖原有数据)，并将写标志位置为1，同时将此cache line在主存中的地址和在RAM中的地址信息更新在CAM中，并将写数据更新到主存中。
为了便于理解，以下举一个实际场景的例子配合说明，假设有这样一个场景：cache line的大小为64bit；数据RAM(DATA_RAM)的深度depth为64(即可以存储64个cache line数据)，地址位宽depth_size为4，地址为0-15；CPU端发出的操作地址位宽Cpu_addr_size为16位，主存的地址位宽也为16位。对应的读写操作流程如下：
1、计算并生成存储单元(CAM和DATA_RAM)规格：
(1)DATA_RAM：
DATA_RAM用于存储cache line信息，在cache中一般都是以cache line为单位进行存储和替换的，cache line的大小一般为8、16、32、64、128bit等等，后续用line_size表示。在生成DATA_RAM时，两个端口的数据位宽均为line_size+2，其中高两位为读写标记位，详细可参考附表3(表3为本申请所提供的一种RAM中的标识描述表)；地址位宽根据实际使用场景的不同可自由配置，后续用depth_size表示。实际数据深度用depth表示。例如存储器的数据深度为64，即可以存储64组数据，此时其地址位宽为log264＝6，用6bit二进制数就可以表示64个地址。
表3 一种RAM中的标识描述表
Figure PCTCN2022134789-appb-000003
(2)CAM：
CAM主要用于存储地址信息和标志位信息。两个端口的数据位宽和地址位宽是不同的。Cpu_addr为CPU端发出的操作地址(常用的如8、16、32、64等位)，其数据位宽记为Cpu_addr_size。A端口数据位宽为1，地址位宽为Cpu_addr_size+depth，地址高位为CPU地址，地址低位为在RAM中的独热码地址。B端口数据位宽为depth，地址位宽为Cpu_addr_size。
2、数据初始化：将RAM_A_wr_addr置为0，即默认起始地址。
3、写cache操作：
写cache操作包括写Cache命中(hit)和写Cache不命中(miss)两种情况。在系统刚刚初始化时，CPU并没有写数据，此时是写cache不命中的；当系统开始工作一段时间后，CPU进行了多次写操作时，cache中已经缓存了部分cache line信息，因此再进行写操作时则可能会写入之前操作过的已经缓存的Cache地址中，此时便是写Cache命中，此时只需要将数据写入对应的Cache中，不必进行后续的替换处理。当然也可能写入Cache中没有缓存的地址，此时便是写Cache不命中。
(1)写Cache命中判断：
当Cpu_req为1，即发起一次请求，cpu_type为store类型的写操作时，将Cpu_addr连接到CAM模块的B端口的读地址端(CAM_B_rd_addr)，并将CAM_B_rd_addr_en拉高进行读操作，在CAM_B_rd_data端口获得读数据(即cache line在数据RAM中独热码的存储地址(ram_addr_one_hot)。当CAM_B_rd_data为0时，即认为写cache不命中(miss)；当CAM_B_rd_data的不为0时，即认为写cache命中(hit)。
(2)写命中处理(hit)：
将上述步骤中CAM_B_rd_data(为独热码)转换为二进制信息并连接至DATA_RAM的B端口的RAM_B_rd_addr，有：
RAM_B_rd_addr＝log2(ram_addr_one_hot)；
同时将RAM_B_rd_addr_en拉高，将RAM_B_rd_data数据读出。在生成DATA_RAM时，其数据位宽为cache line的大小，因此每次读出的RAM_B_rd_data为一个cache line的信息，但CPU发送的写数据可能只是Cache中的一部分内容，因此将CPU发送的写数据部分代替RAM_B_rd_data中对应的部分，其他部分保持不变，写标志位置为1，读标志位置为0，并将这个新生成的信号赋给DATA_RAM的A端口的写数据RAM_A_wr_data信号，同时将RAM_A_wr_addr_en拉高，并将B端口的地址赋给A，即：RAM_A_wr_addr＝＝RAM_B_rd_addr，把数据和标志位写入数据RAM中。
例如，CPU下发一个写操作，地址为16’h1000。首先将这个地址连接CAM的B端口的地址线，将数据读出16’b0000_0000_0000_1000，将其转换为二进制数据3，把3作为数据RAM的A端口的写地址，将CPU新下发的数据写入RAM的地址3空间中。
(3)写不命中处理(miss)：
a.下一次写入地址(data_ram_next_addr)表示当发生写miss时进行替 换的data_ram地址；地址搜索次数(addr_cnt)表示进行地址加1跳转的次数。
b.两个变量复位后的默认值为起始地址0，当发生写miss后，data_ram_next_addr进行加1(即向下寻址)，当跳转至最后一个地址时将返回首地址，并将data_ram_next_addr连接到RAM_B_rd_addr，并将RAM_B_rd_addr_en拉高进行读操作，addr_cnt也进行加1操作：
data_ram_next_addr＝data_ram_next_addr+1；
RAM_B_rd_addr＝data_ram_next_addr；
addr_cnt＝addr_cnt+1；
判断此时的RAM_B_rd_data[line_size]，即写标志位。当写标志位为1时，说明此地址空间已经写入cache line数据，此时data_ram_next_addr进行再加1，判断下一个地址的数据写标志位是否为1，直至判断到写标志位为0的地址停止，此时的data_ram_next_addr即为进行替换的cache line的写入地址，同时将addr_cnt清零。
例如，当前的data_ram的地址为1，此时发生写miss，data_ram_next_addr向下进行寻址，通过读数据发现地址14的写标志位为0，此时则将地址14作为cache line的替换地址。
当写标志位始终为1，并且addr_cnt＝2 depth_size-1时(例如数据RAM容量为16，addr_cnt为15)，说明已经将整个数据RAM的地址空间遍历，所有的空间都已写入cache line数据，此时data_ram_next_addr即为进行替换的cache line的写入地址，同时将addr_cnt清零。
例如，上一次操作的data_ram的地址为2，此时发生写miss，data_ram_next_addr向下进行寻址，通过读数据发现写标志位始终为1，当addr_cnt＝＝15时，此时data_ram_next_addr跳转至地址1，则将地址1作为cache line的替换地址。
c.将数据和标志位写入数据RAM中：
将CPU发送的写cache line数据部分，其他部分保持不变，写标志位置为1，读标志位置为0，并将这个新生成的信号赋给DATA_RAM的A端口的写数据RAM_A_wr_data信号，同时将RAM_A_wr_addr_en拉高，并将B端口的地址赋给A：
RAM_A_wr_addr＝＝RAM_B_rd_addr。
d.将cache line替换地址写入CAM中：
将CAM的A端口的写使能和写数据置为1，同时将写地址按如下赋值：
CAM_A_wr_addr＝{Cpu_addr，data_ram_next_addr_one}；
data_ram_next_addr_one为data_ram_next_addr的独热码地址；
data_ram_next_addr_one＝16‘b1＜＜data_ram_next_addr；
即高位为CPU发送的地址，低位为需要替换的cache line在RAM的存储独热码地址。
例如，CPU下发一个写操作，地址为16’h1000。当发生写miss时，通过 计算得到cache line的替换地址为二进制的地址1时，此时CAM的A端口的写入地址为32’h1000_0002，写入数据为1。
4、读cache操作：
读cache操作包括读cache命中(hit)和读cache不命中(miss)两种情况。在系统刚刚初始化时，CPU并没有写数据，此时是读Cache不命中的；当系统开始工作一段时间后，CPU进行了多次写操作时，Cache中已经缓存了部分cache line信息，因此再进行读操作时则可能读入之前操作过的已经缓存的Cache地址中，此时便是写Cache命中，此时只需要将数据从对应的Cache中读出返回至CPU，不必进行后续的替换处理。当然也可能要读入数据地址在Cache中没有缓存，此时便是读Cache不命中。
(1)读Cache命中判断：
当Cpu_req为1，即发起一次请求，cpu_type为load类型的读操作时，将Cpu_addr连接到CAM模块的B端口的读地址端(CAM_B_rd_addr)，并将CAM_B_rd_addr_en拉高进行读操作，在CAM_B_rd_data端口获得读数据(即cache line在数据RAM中独热码的存储地址(ram_addr_one_hot)。当CAM_B_rd_data为0时，即认为读cache不命中(miss)；当CAM_B_rd_data的不为0时，即认为读cache命中(hit)。
(2)读命中处理(hit)：
a.将上述步骤中CAM_B_rd_data(为独热码)转换为二进制信息并连接至DATA_RAM的B端口的RAM_B_rd_addr，有：
RAM_B_rd_addr＝log2(ram_addr_one_hot)；
同时将RAM_B_rd_addr_en拉高，将RAM_B_rd_data数据读出，然后返回给CPU。
b.更新数据RAM：将读出的数据cache line保持不变，写标志位置为1，读标志位置为1，并将这个新生成的信号赋给DATA_RAM的A端口的写数据RAM_A_wr_data信号，同时将RAM_A_wr_addr_en拉高，并将B端口的地址赋给A，即：RAM_A_wr_addr＝＝RAM_B_rd_addr；把数据和标志位写入数据RAM中。
例如，CPU下发一个读操作，地址为16’h1000。首先将这个地址连接CAM的B端口的地址线，将数据读出16’b0000_0000_0000_1000，将其转换为二进制数据3，把3作为数据RAM的B端口的读地址，将Cache line数据读出，然后将此cache line数据、读和写标志位置为1后通过RAM的A端口写入RAM的地址3空间中。
(a)读不命中处理(miss)：
a.下一次读取地址(data_ram_next_addr)表示当发生读miss时进行替换的data_ram地址；读地址搜索次数(addr_cnt_rd)表示进行地址加1跳转的次数。
b.两个变量复位后的默认值为起始地址0，当发生读miss后，data_ram_next_addr_rd进行加1(即向下寻址)，当跳转至最后一个地址时将返回首地址，并将data_ram_next_addr_rd连接到RAM_B_rd_addr，并将 RAM_B_rd_addr_en拉高进行读操作，addr_cnt_rd也进行加1操作：
data_ram_next_addr_rd＝data_ram_next_addr_rd+1；
RAM_B_rd_addr＝data_ram_next_addr_rd；
addr_cnt_rd＝addr_cnt_rd+1；
判断此时的RAM_B_rd_data[line_size]，即写标志位。当写标志位为1时，说明此地址空间已经写入cache line数据，此时data_ram_next_addr_rd进行再加1，判断下一个地址的数据写标志位是否为1，直至判断到写标志位为0的地址停止，此时的data_ram_next_addr_rd即为进行替换的cache line的写入地址，同时将addr_cnt_rd清零。
例如，当前的data_ram的地址1，此时发生读miss，data_ram_next_addr_rd向下进行寻址，通过读数据发现地址14的写标志位为0，此时则将地址14作为cache line的替换地址。
当写标志位始终为1，并且addr_cnt＝2 depth_size-1时(例如数据RAM容量为16，addr_cnt为15)，说明已经将整个数据RAM的地址空间遍历，所有的空间都已写入cache line数据。此时将data_ram_next_addr_rd再次进行加1，即重新开始一轮向下寻址，同样是当跳转至最后一个地址时将返回首地址，并将data_ram_next_addr_rd连接到RAM_B_rd_addr，并将RAM_B_rd_addr_en拉高进行读操作，addr_cnt_rd也进行继续的加1操作。
判断此时的RAM_B_rd_data[line_size+1]，即读标志位。当读标志位为1时，说明此地址空间近期有过此cache line数据读取，此时data_ram_next_addr_rd进行再加1，判断下一个地址的读标志位是否为0，直至判断读标志位为0的地址停止，此时的data_ram_next_addr_rd即为进行替换的cache line的地址，同时将addr_cnt_rd清零。
例如，上一次操作的data_ram的地址为2，此时发生写miss，data_ram_next_addr_rd向下进行寻址，通过读数据发现写标志位都始终为1，读标志位在地址14位，则将地址14作为cache line的替换地址。
当读标志位也始终为1，并且addr_cnt＝2*2 depth_size-1时(例如数据RAM容量为16，addr_cnt为31)，说明已经将整个数据RAM的地址空间遍历2次，所有的空间都已写入cache line数据，且近期都有读取记录，则此时data_ram_next_addr_rd即为进行替换的cache line的写入地址，同时将addr_cnt_rd清零。
例如，上一次操作的data_ram的地址为2，此时发生写miss，data_ram_next_addr_rd向下进行寻址，通过读数据发现读和写标志位都始终为1，当addr_cnt＝＝31时，此时data_ram_next_addr_rd跳转至地址1，则将地址1作为cache line的替换地址。
c.将主存返回的数据和标志位写入数据RAM中：
当发送读操作miss时，CPU会从主存中读取对应的数据，并将返回的数据缓存在数据RAM的替换地址空间中，然后再发送返回CPU。将主存返回的cache line数据部分，写标志位置为1，读标志位置为0，一同写入数据RAM 的替换地址空间中，将这个新生成的信号赋给DATA_RAM的A端口的写数据RAM_A_wr_data信号，同时将RAM_A_wr_addr_en拉高，RAM_A_wr_addr为上述的替换地址。
d.将cache line替换地址写入CAM中：
将CAM的A端口的写使能和写数据置为1，同时将写地址按如下赋值：
CAM_A_wr_addr＝{Cpu_addr，data_ram_next_addr_one_rd}；
data_ram_next_addr_one_rd为data_ram_next_addr_rd的独热码地址；
data_ram_next_addr_one_rd＝16‘b1＜＜data_ram_next_addr_rd；
即高位为CPU发送的地址，低位为需要替换的cache line在RAM的存储独热码地址。
例如，CPU下发一个读操作，地址为16’h1000。当发生写miss时，通过计算得到cache line的替换地址为二进制的地址1时，此时CAM的A端口的写入地址为32’h1000_0002，写入数据为1。
可见，本申请实施例所提供的数据读写方法，预先为缓存中数据存储器的各个数据存储地址设置读写标志位，用于标志对应的存储数据是否已经发生过读写操作，由此，在数据读写过程中，面对读写数据未命中缓存且缓存中数据存储器不存在空闲存储地址的情况下，可以从数据存储器的初始存储地址开始遍历，直至遍历到存在未读标志的存储地址，说明该存储地址中所存储的数据信息从未被读取过，使用率较低，此时，则可以直接将读写数据写入至该存在未读标志的存储地址中；当无法遍历到存在未读标志的存储地址时，则可以直接将读写数据写入初始存储地址的上一存储地址中，也即遍历到的数据存储器中的最后一个存储地址，以有效保证将读写数据存储至缓存。可见，该种实现方式可以在有效保证较高缓存命中率的同时，提高数据读写效率。
本申请实施例还提供了一种数据读写装置，请参考图3，图3为本申请实施例所提供的一种数据读写装置的结构示意图，该数据读写装置可包括：
读写数据确定模块1，用于根据数据读写请求确定读写数据；
存储地址遍历模块2，用于当读写数据未命中缓存，且设置于缓存中的数据存储器不存在空闲存储地址时，从数据存储器的初始存储地址开始遍历；
第一数据写入模块3，用于当遍历到存在未读标志的存储地址时，将读写数据写入存在未读标志的存储地址中；
第二数据写入模块4，用于当未遍历到存在未读标志的存储地址时，将读写数据写入初始存储地址的上一存储地址中。
可见，本申请实施例所提供的数据读写装置，预先为缓存中数据存储器的各个数据存储地址设置读写标志位，用于标志对应的存储数据是否已经发生过读写操作，由此，在数据读写过程中，面对读写数据未命中缓存且缓存中数据存储器不存在空闲存储地址的情况下，可以从数据存储器的初始存储地址开始遍历，直至遍历到存在未读标志的存储地址，说明该存储地址中所存储的数据信息从未被读取过，使用率较低，此时，则可以直接将读写数据写入至该存在 未读标志的存储地址中；当无法遍历到存在未读标志的存储地址时，则可以直接将读写数据写入初始存储地址的上一存储地址中，也即遍历到的数据存储器中的最后一个存储地址，以有效保证将读写数据存储至缓存。可见，该种实现方式可以在有效保证较高缓存命中率的同时，提高数据读写效率。
在本申请的一个实施例中，该数据读写装置还可包括缓存命中判断模块，用于将读写数据输入设置于缓存中的内容可寻址存储器；当接收到内容可寻址存储器根据读写数据反馈的地址信息时，确定读写数据命中缓存；当未接收到内容可寻址存储器根据读写数据反馈的地址信息时，确定读写数据未命中缓存。
在本申请的一个实施例中，该数据读写装置还可包括地址信息存储模块，用于在将读写数据写入存在未读标志的存储地址中之后，或将读写数据写入初始存储地址的上一存储地址中之后，将读写数据在数据存储器中的存储地址和在主存中的存储地址一同更新至内容可寻址存储器。
在本申请的一个实施例中，该数据读写装置还可包括空闲存储地址判断模块，用于从数据存储器的初始存储地址开始遍历；当遍历到存在未写标志的存储地址时，确定数据存储器存在空闲存储地址，并将存在未写标志的存储地址作为空闲存储地址；当未遍历到存在未写标志的存储地址时，确定数据存储器不存在空闲存储地址。
在本申请的一个实施例中，该数据读写装置还可包括第一标志位设置模块，用于在将读写数据写入存在未读标志的存储地址中之后，或将读写数据写入初始存储地址的上一存储地址中之后，为读写数据在数据存储器中的存储地址设置已写标志和未读标志。
在本申请的一个实施例中，该数据读写装置还可包括第二标志位设置模块，用于当读写数据命中缓存时，若读写数据具体为读数据，则为读数据在数据存储器中的存储地址设置已读标志；若读写数据具体为写数据，则为写数据在数据存储器中的存储地址设置已写标志。
在本申请的一个实施例中，该数据读写装置还可包括第三数据写入模块，用于当读写数据未命中缓存，且数据存储器存在空闲存储地址时，将读写数据写入空闲存储地址。
对于本申请实施例提供的装置的介绍请参照上述方法实施例，本申请实施例在此不做赘述。
本申请实施例还提供了一种数据读写设备，请参考图4，图4为本申请实施例所提供的一种数据读写设备的结构示意图，该数据读写设备可包括：
存储器，用于存储计算机程序；
处理器，用于执行计算机程序时可实现如上述任意一种数据读写方法的步骤。
如图4所示，为数据读写设备的组成结构示意图，数据读写设备可以包括：处理器10、存储器11、通信接口12和通信总线13。处理器10、存储器 11、通信接口12均通过通信总线13完成相互间的通信。
在本申请实施例中，处理器10可以为中央处理器(Central Processing Unit，CPU)、特定应用集成电路、数字信号处理器、现场可编程门阵列或者其他可编程逻辑器件等。
处理器10可以调用存储器11中存储的程序，处理器10可以执行数据读写方法的实施例中的操作。
存储器11中用于存放一个或者一个以上程序，程序可以包括程序代码，程序代码包括计算机操作指令，在本申请实施例中，存储器11中至少存储有用于实现以下功能的程序：
根据数据读写请求确定读写数据；
当读写数据未命中缓存，且设置于缓存中的数据存储器不存在空闲存储地址时，从数据存储器的初始存储地址开始遍历；
当遍历到存在未读标志的存储地址时，将读写数据写入存在未读标志的存储地址中；
当未遍历到存在未读标志的存储地址时，将读写数据写入初始存储地址的上一存储地址中。
在一种可能的实现方式中，存储器11可包括存储程序区和存储数据区，其中，存储程序区可存储操作系统，以及至少一个功能所需的应用程序等；存储数据区可存储使用过程中所创建的数据。
此外，存储器11可以包括高速随机存取存储器，还可以包括非易失性存储器，例如至少一个磁盘存储器件或其他易失性固态存储器件。
通信接口12可以为通信模块的接口，用于与其他设备或者系统连接。
当然，需要说明的是，图4所示的结构并不构成对本申请实施例中数据读写设备的限定，在实际应用中数据读写设备可以包括比图4所示的更多或更少的部件，或者组合某些部件。
本申请还提供了一种计算机可读存储介质，该计算机可读存储介质上存储有计算机程序，计算机程序被处理器执行时可实现如上述任意一种数据读写方法的步骤。
该计算机可读存储介质可以包括：U盘、移动硬盘、只读存储器(Read-Only Memory，ROM)、随机存取存储器(Random Access Memory，RAM)、磁碟或者光盘等各种可以存储程序代码的介质。
对于本申请提供的计算机可读存储介质的介绍请参照上述方法实施例，本申请在此不做赘述。
说明书中各个实施例采用递进的方式描述，每个实施例重点说明的都是与其他实施例的不同之处，各个实施例之间相同相似部分互相参见即可。对于实施例公开的装置而言，由于其与实施例公开的方法相对应，所以描述的比较简单，相关之处参见方法部分说明即可。
专业人员还可以进一步意识到，结合本文中所公开的实施例描述的各示例的单元及算法步骤，能够以电子硬件、计算机软件或者二者的结合来实现，为了清楚地说明硬件和软件的可互换性，在上述说明中已经按照功能一般性地描述了各示例的组成及步骤。这些功能究竟以硬件还是软件方式来执行，取决于技术方案的特定应用和设计约束条件。专业技术人员可以对每个特定的应用来使用不同方法来实现所描述的功能，但是这种实现不应认为超出本申请的范围。
结合本文中所公开的实施例描述的方法或算法的步骤可以直接用硬件、处理器执行的软件模块，或者二者的结合来实施。软件模块可以置于随机存储器(RAM)、内存、只读存储器(ROM，Read-Only Memory)、电可编程ROM、电可擦除可编程ROM、寄存器、硬盘、可移动磁盘、CD-ROM或技术领域内所公知的任意其它形式的存储介质中。
以上对本申请所提供的技术方案进行了详细介绍。本文中应用了具体个例对本申请的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本申请的方法及其核心思想。应当指出，对于本技术领域的普通技术人员来说，在不脱离本申请原理的前提下，还可以对本申请进行若干改进和修饰，这些改进和修饰也落入本申请的保护范围内。

Claims (20)

  1. 一种数据读写方法，其特征在于，包括：
    根据数据读写请求确定读写数据；
    当所述读写数据未命中缓存，且设置于所述缓存中的数据存储器不存在空闲存储地址时，从所述数据存储器的初始存储地址开始遍历；
    当遍历到存在未读标志的存储地址时，将所述读写数据写入存在所述未读标志的存储地址中；
    当未遍历到存在未读标志的存储地址时，将所述读写数据写入所述初始存储地址的上一存储地址中。
  2. 根据权利要求1所述的数据读写方法，其特征在于，判断所述读写数据是否命中所述缓存，包括：
    将所述读写数据输入设置于所述缓存中的内容可寻址存储器；
    当接收到所述内容可寻址存储器根据所述读写数据反馈的地址信息时，确定所述读写数据命中所述缓存；
    当未接收到所述内容可寻址存储器根据所述读写数据反馈的地址信息时，确定所述读写数据未命中所述缓存。
  3. 根据权利要求2所述的数据读写方法，其特征在于，所述确定所述读写数据命中所述缓存之后，还包括：
    在所述读写数据为写数据的情况下，将独热码CAM_B_rd_data转换为二进制信息并连接至DATA_RAM的B端口的RAM_B_rd_addr，其中，所述CAM_B_rd_data为CAM的B端口读数据，所述CAM为所述内容可寻址存储器，所述RAM_B_rd_addr为RAM的B端口读地址，所述数据存储器包括所述RAM；
    将RAM_B_rd_addr_en拉高，将RAM_B_rd_data数据读出，其中，所述RAM_B_rd_addr_en为所述RAM的B端口读使能，所述RAM_B_rd_data为所述RAM的B端口读数据；
    将中央处理器CPU发送的写数据部分代替RAM_B_rd_data中对应的部分，其他部分保持不变，写标志位置为1，读标志位置为0，并将该新生成的信号赋给所述DATA_RAM的A端口的写数据RAM_A_wr_data信号，同时将RAM_A_wr_addr_en拉高，并将所述B端口的地址赋给所述A端口，把数据和标志位写入数据RAM中，其中，所述RAM_A_wr_data为所述RAM的A端口写数据，所述RAM_A_wr_addr_en为所述RAM的A端口写使能。
  4. 根据权利要求2所述的数据读写方法，其特征在于，所述确定所述读写数据命中所述缓存之后，还包括：
    在所述读写数据为读数据的情况下，将独热码CAM_B_rd_data转换为二进制信息并连接至所述DATA_RAM的所述B端口的所述RAM_B_rd_addr，其中，所述CAM_B_rd_data为CAM的B端口读数据，所述CAM为所述内容可寻址存储器，所述RAM_B_rd_addr为RAM的B端口读地址，所述数据存储器包括所述RAM；
    将所述RAM_B_rd_addr_en拉高，将所述RAM_B_rd_data数据读出，然后返回给中央处理器CPU，其中，所述RAM_B_rd_addr_en为所述RAM的B端口读使能，所述RAM_B_rd_data为所述RAM的B端口读数据；
    将读出的数据缓存行cache line保持不变，写标志位置为1，读标志位置为1，并将该新生成的信号赋给所述DATA_RAM的所述A端口的写数据所述RAM_A_wr_data信号，同时将所述RAM_A_wr_addr_en拉高，并将所述B端口的地址赋给所述A端口，把数据和标志位写入数据RAM中，其中，所述RAM_A_wr_data为所述RAM的A端口写数据，所述RAM_A_wr_addr_en为所述RAM的A端口写使能。
  5. 根据权利要求2所述的数据读写方法，其特征在于，所述将所述读写数据输入设置于所述缓存中的内容可寻址存储器，包括：
    将Cpu_addr连接到所述数据存储器的B端口的读地址端CAM_B_rd_addr，其中，所述Cpu_addr为中央处理器CPU的指令执行地址，所述CAM_B_rd_addr为CAM的B端口读地址，所述CAM为所述内容可寻址存储器；
    将CAM_B_rd_addr_en拉高进行读操作，在CAM_B_rd_data端口获得所述读写数据在所述数据存储器中独热码的存储地址ram_addr_one_hot，其中，所述CAM_B_rd_addr_en为所述CAM的B端口读使能。
  6. 根据权利要求2所述的数据读写方法，其特征在于，所述将所述读写数据写入存在所述未读标志的存储地址中之后，或所述将所述读写数据写入所述初始存储地址的上一存储地址中之后，还包括：
    将所述读写数据在所述数据存储器中的存储地址和在主存中的存储地址一同更新至所述内容可寻址存储器。
  7. 根据权利要求1至6任意一项所述的数据读写方法，其特征在于，判断所述数据存储器是否存在所述空闲存储地址，包括：
    从所述数据存储器的初始存储地址开始遍历；
    当遍历到存在未写标志的存储地址时，确定所述数据存储器存在所述空闲存储地址，并将所述存在未写标志的存储地址作为所述空闲存储地址；
    当未遍历到存在未写标志的存储地址时，确定所述数据存储器不存在所述空闲存储地址。
  8. 根据权利要求7所述的数据读写方法，其特征在于，在从所述数据存储器的初始存储地址开始遍历之前，还包括：
    为所述数据存储器中的各个存储地址设置读写标志位，其中，所述读写标志位包括读标志位和写标志位，所述读标志位用于设定已读标志或者未读标志，所述写标志位用于设定已写标志或者所述未写标志，所述已读标志用于表示所对应的存储地址中所存储的数据信息已经被读取过，所述未读标志用于表示对应的存储地址所存储的数据信息在写入之后并未被读取过，所述已写标志用于表示所对应的存储地址存储有数据信息，所述未写标志用于表示对应的存储地址为空闲存储地址。
  9. 根据权利要求7所述的数据读写方法，其特征在于，所述将所述读 写数据写入存在所述未读标志的存储地址中之后，或所述将所述读写数据写入所述初始存储地址的上一存储地址中之后，还包括：
    为所述读写数据在所述数据存储器中的存储地址设置已写标志和未读标志。
  10. 根据权利要求1所述的数据读写方法，其特征在于，当所述读写数据命中所述缓存时，所述方法还包括：
    若所述读写数据具体为读数据，则为所述读数据在所述数据存储器中的存储地址设置已读标志；
    若所述读写数据具体为写数据，则为所述写数据在所述数据存储器中的存储地址设置已写标志。
  11. 根据权利要求1所述的数据读写方法，其特征在于，还包括：
    当所述读写数据未命中所述缓存，且所述数据存储器存在所述空闲存储地址时，将所述读写数据写入所述空闲存储地址。
  12. 根据权利要求11所述的数据读写方法，其特征在于，在将所述读写数据写入所述空闲存储地址之前，还包括：
    在所述读写数据为写数据的情况下，将data_ram_next_addr加1，其中，所述data_ram_next_addr为下一次写入地址；
    将所述data_ram_next_addr连接到RAM_B_rd_addr，并将RAM_B_rd_addr_en拉高进行读操作，addr_cnt_rd也进行加1操作，其中，所述RAM_B_rd_addr为RAM的B端口读地址，所述数据存储器包括所述RAM，所述RAM_B_rd_addr_en为所述RAM的B端口读使能，所述addr_cnt_rd为读地址搜索次数；
    判断此时的写标志位RAM_B_rd_data[line_size]的取值，其中，所述RAM_B_rd_data为所述RAM的B端口读数据；
    在所述写标志位的取值为1的情况下，再次执行对所述data_ram_next_addr加1的操作；
    在所述写标志位的取值为0时，将所述data_ram_next_addr确定为写入所述读写数据的所述空闲存储地址。
  13. 根据权利要求11所述的数据读写方法，其特征在于，在将所述读写数据写入所述空闲存储地址之前，还包括：
    在所述读写数据为读数据的情况下，将data_ram_next_addr_rd加1；
    将所述data_ram_next_addr_rd连接到所述RAM_B_rd_addr，并将所述RAM_B_rd_addr_en拉高进行读操作，所述addr_cnt_rd也进行加1操作，其中，所述RAM_B_rd_addr为RAM的B端口读地址，所述数据存储器包括所述RAM，所述RAM_B_rd_addr_en为所述RAM的B端口读使能，所述addr_cnt_rd为读地址搜索次数；
    判断此时的所述写标志位RAM_B_rd_data[line_size]的取值，其中，所述RAM_B_rd_data为所述RAM的B端口读数据；
    在所述写标志位的取值为1的情况下，再次执行对所述data_ram_next_addr_rd加1的操作；
    在所述写标志位的取值为0时，将所述data_ram_next_addr_rd确定为写入所述读写数据的所述空闲存储地址。
  14. 根据权利要求11所述的数据读写方法，其特征在于，在所述将所述读写数据写入所述空闲存储地址之后，所述方法还包括：
    将内容可寻址存储器的A端口的写使能和写数据置为1，同时将写地址按如下赋值：
    CAM_A_wr_addr＝{Cpu_addr，data_ram_next_addr_one_rd}；
    data_ram_next_addr_one_rd为data_ram_next_addr_rd的独热码地址，data_ram_next_addr_one_rd＝16‘b1<<data_ram_next_addr_rd，其中，高位为CPU发送的地址，低位为需要替换的所述读写数据在所述内容可寻址存储器的存储独热码地址，所述CAM_A_wr_addr为CAM的A端口写地址，所述CAM为所述内容可寻址存储器，所述Cpu_addr为中央处理器CPU的指令执行地址。
  15. 根据权利要求1所述的数据读写方法，其特征在于，在从所述数据存储器的初始存储地址开始遍历之前，所述方法还包括：
    判断所述读写数据是否命中所述缓存；
    在所述读写数据命中所述缓存的情况下，对所述缓存中进行数据读写；
    在所述读写数据未命中所述缓存的情况下，判断所述数据存储器中是否存在空闲地址；在所述数据存储器中存在所述空闲地址的情况下，将所述读写数据写入所述空闲地址；在所述数据存储器中不存在所述空闲地址的情况下，从所述数据存储器的初始存储地址开始遍历，查询存在未读标志的存储地址，其中，所述初始存储地址为预先设定的存储地址。
  16. 根据权利要求1所述的数据读写方法，其特征在于，所述将所述读写数据写入存在所述未读标志的存储地址中，包括：
    在所述读写数据为读数据的情况下，向主存获取所述读数据；将所述读数据写入存在所述未读标志的存储地址；
    在所述读写数据为写数据的情况下，将所述写数据写入存在所述未读标志的存储地址和主存中。
  17. 根据权利要求1所述的数据读写方法，其特征在于，所述将所述读写数据写入所述初始存储地址的上一存储地址中，包括：
    在所述读写数据为读数据的情况下，向主存获取所述读数据；将所述读数据写入所述初始存储地址的上一存储地址中；
    在所述读写数据为写数据的情况下，将所述写数据写入所述初始存储地址的上一存储地址和主存中。
  18. 一种数据读写装置，其特征在于，包括：
    读写数据确定模块，被设置为根据数据读写请求确定读写数据；
    存储地址遍历模块，被设置为当所述读写数据未命中缓存，且设置于所述缓存中的数据存储器不存在空闲存储地址时，从所述数据存储器的初始存储地址开始遍历；
    第一数据写入模块，被设置为当遍历到存在未读标志的存储地址时，将 所述读写数据写入存在所述未读标志的存储地址中；
    第二数据写入模块，被设置为当未遍历到存在未读标志的存储地址时，将所述读写数据写入所述初始存储地址的上一存储地址中。
  19. 一种数据读写设备，其特征在于，包括：
    存储器，被设置为存储计算机程序；
    处理器，被设置为执行所述计算机程序时实现如权利要求1至17任一项所述的数据读写方法的步骤。
  20. 一种计算机可读存储介质，其特征在于，所述计算机可读存储介质上存储有计算机程序，所述计算机程序被处理器执行时实现如权利要求1至17任一项所述的数据读写方法的步骤。
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