WO2023155317A1 - 一种esd保护电路、检波电路及相关电子装置 - Google Patents

一种esd保护电路、检波电路及相关电子装置 Download PDF

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Publication number
WO2023155317A1
WO2023155317A1 PCT/CN2022/093997 CN2022093997W WO2023155317A1 WO 2023155317 A1 WO2023155317 A1 WO 2023155317A1 CN 2022093997 W CN2022093997 W CN 2022093997W WO 2023155317 A1 WO2023155317 A1 WO 2023155317A1
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Prior art keywords
parasitic diode
switch
type transistor
esd protection
parasitic
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PCT/CN2022/093997
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English (en)
French (fr)
Inventor
杨博新
王程左
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深圳市汇顶科技股份有限公司
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Publication of WO2023155317A1 publication Critical patent/WO2023155317A1/zh

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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
    • H02H9/00—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection

Definitions

  • the present application relates to a circuit, in particular to an ESD protection circuit, a detection circuit and related electronic devices.
  • detection circuits are often used to detect the amplitude of the wave signal generated by the sensor to achieve the purpose of sensing variables. Since the sensing plate of the sensor is usually exposed outside, it is easily damaged by static electricity during wafer manufacturing, subsequent packaging, and reprocessing, resulting in damage to the chip circuit (such as the detection circuit), affecting the detection performance of the detection circuit, and reducing the quality of the chip. Rate.
  • ESD Electro -Static Discharge (electrostatic discharge) protection circuit
  • GGNMOS gate-grounded NMOS, gate-grounded N-type transistors
  • GDPMOS gate-to-drain PMOS, gate-to-drain P-type transistors
  • ESD protection circuit has a large area and will introduce a large parasitic capacitance, thereby separating part of the signal volume and affecting the accuracy of the detection results of the detection circuit.
  • the present application provides an ESD protection circuit, a detection circuit and related electronic devices, which can effectively solve the problem that other devices need to be introduced into the existing detection circuit.
  • an ESD protection circuit including a window selection switch, the window selection switch has two parasitic diodes, wherein the cathode of one of the parasitic diodes is coupled to the power supply of the detection circuit, and the other is The anode of the parasitic diode is grounded, and the anode of the one parasitic diode is coupled to the cathode of the other parasitic diode.
  • the window selection switch includes a first switch and a second switch, the first switch is coupled between the reference voltage and the input terminal of the ESD protection circuit, and the second switch is coupled Connected between the input terminal and the output terminal of the ESD protection circuit.
  • the first switch includes a first parasitic diode and a second parasitic diode
  • the cathode of the first parasitic diode is coupled to the power supply of the detection circuit
  • the anode of the first parasitic diode is coupled to the cathode of the second parasitic diode.
  • the first switch includes a first P-type transistor and a first N-type transistor, the first P-type transistor and the first N-type transistor are arranged in parallel, and the first parasitic diode Parasitic on the first P-type transistor, the substrate of the first P-type transistor is coupled to the power supply of the detection circuit, the second parasitic diode is parasitic on the first N-type transistor, and the first The substrate of the N-type transistor is grounded.
  • the second switch includes a third parasitic diode and a fourth parasitic diode, the cathode of the third parasitic diode is coupled to the power supply of the detection circuit, and the anode of the fourth parasitic diode grounded, and the anode of the third parasitic diode is coupled to the cathode of the fourth parasitic diode.
  • the second switch includes a second P-type transistor and a second N-type transistor, the second P-type transistor and the second N-type transistor are arranged in parallel, and the third parasitic diode Parasitic on the second P-type transistor, the substrate of the second P-type transistor is coupled to the power supply of the detection circuit, the fourth parasitic diode is parasitic on the second N-type transistor, and the second The substrate of the N-type transistor is grounded.
  • a protection resistor is further included, and the protection resistor is coupled between the input end of the ESD protection circuit and the window selection switch.
  • it further includes: a grounding switch, one end of the grounding switch is coupled to the input end of the ESD protection circuit, and the other end is grounded, the grounding switch includes a fifth parasitic diode, and the fifth parasitic The anode of the diode is grounded, and the cathode of the fifth parasitic diode is coupled to the input terminal of the ESD protection circuit.
  • the grounding switch includes a third N-type transistor, the fifth parasitic diode is parasitic to the third N-type transistor, and a substrate of the third N-type transistor is grounded.
  • a detection circuit which is used to detect the amplitude of the received signal of the receiving circuit
  • the detection circuit includes an ESD protection circuit, including a window selection switch, and the window selection switch has two parasitic diodes, one of which is the The negative pole of the parasitic diode is coupled to the power supply of the detection circuit, the positive pole of the other parasitic diode is grounded, and the positive pole of the one parasitic diode is coupled to the negative pole of the other parasitic diode;
  • the operational amplifier has a positive terminal, Negative terminal and output terminal; Integrating capacitor, coupled between the output terminal of the operational amplifier and the negative terminal; Reset switch, set in parallel with the integrating capacitor; Window selection switch of the ESD protection circuit It is used for switching the sampling mode and the non-sampling mode during the signal detection process of the detection circuit.
  • the window selection switch includes a first switch and a second switch, the first switch is coupled between the reference voltage and the output terminal of the receiving circuit, and the second switch is coupled to Between the output terminal of the receiving circuit and the negative terminal of the operational amplifier.
  • the first switch includes a first parasitic diode and a second parasitic diode
  • the cathode of the first parasitic diode is coupled to the power supply of the detection circuit
  • the anode of the first parasitic diode is coupled to the cathode of the second parasitic diode.
  • the first switch includes a first P-type transistor and a first N-type transistor, the first P-type transistor and the first N-type transistor are arranged in parallel, and the first parasitic diode Parasitic on the first P-type transistor, the substrate of the first P-type transistor is coupled to the power supply of the detection circuit, the second parasitic diode is parasitic on the first N-type transistor, and the first The substrate of the N-type transistor is grounded.
  • the second switch includes a third parasitic diode and a fourth parasitic diode, the cathode of the third parasitic diode is coupled to the power supply of the detection circuit, and the anode of the fourth parasitic diode grounded, and the anode of the third parasitic diode is coupled to the cathode of the fourth parasitic diode.
  • the second switch includes a second P-type transistor and a second N-type transistor, the second P-type transistor and the second N-type transistor are arranged in parallel, and the third parasitic diode Parasitic on the second P-type transistor, the substrate of the second P-type transistor is coupled to the power supply of the detection circuit, the fourth parasitic diode is parasitic on the second N-type transistor, and the second The substrate of the N-type transistor is grounded.
  • a protection resistor is further included, and the protection resistor is coupled between the input end of the ESD protection circuit and the window selection switch.
  • the ESD protection circuit further includes a grounding switch, one end of the grounding switch is coupled to the input end of the ESD protection circuit, and the other end is grounded, and the grounding switch includes a fifth parasitic A diode, the anode of the fifth parasitic diode is grounded, and the cathode of the fifth parasitic diode is coupled to the input end of the ESD protection circuit.
  • the signal detection process of the detection circuit includes a reset phase, a receiving phase, and a general phase.
  • the reset phase the reset switch is turned on and the second switch is turned off, so The output terminal of the operational amplifier outputs a reference voltage; in the receiving stage, the ground switch is turned on, the reset switch, the first switch and the second switch are all off, and the receiving circuit receives The received signal is generated after the input signal.
  • the reset switch is non-conductive, and the received signal includes a plurality of waves with a period T, and the detection circuit is in a period T corresponding to a first specific wave among the plurality of waves.
  • the time with T*R is set as the sampling mode, and the time with T*(1-R) is set as the non-sampling mode, wherein R is greater than 0 and less than 1; and the detection circuit corresponds to In the period T of the second specific wave among the plurality of waves, the time of T*R is set as the sampling mode, and the time of T*(1-R) is set as the non-sampling mode, wherein: in the sampling mode, the first switch is not turned on and the second switch is turned on, so that the amplitude change of the received signal during the sampling mode is reflected in a specific ratio and accumulated in the operational amplifier and in the non-sampling mode, the first switch is turned on and the second switch is not turned on, so that the amplitude of the received signal generated by the receiving circuit in the non-sampling mode Changes are not reflected and accumulated at the output terminal of the operational amplifier, so that the voltage at the output terminal of the operational amplifier remains unchanged in the non-sampling mode.
  • the grounding switch includes a third N-type transistor, the fifth parasitic diode is parasitic to the third N-type transistor, and a substrate of the third N-type transistor is grounded.
  • a related electronic device including the wave detector described in the above second aspect or various implementations thereof.
  • the beneficial effect of the embodiment of the present application is that: the ESD protection circuit provided by the embodiment of the present application can realize the discharge of electrostatic charge by switching its own parasitic diode, which can prevent electronic devices from being broken down, and does not require Additional devices such as diodes, GGNMOS or GDPMOS are added as ESD protection circuits, which will not introduce large parasitic capacitance and will not divert the signal volume, thus ensuring the accuracy of the detection results of the detection circuit.
  • Fig. 1 a is the schematic diagram of the first embodiment of the ESD protection circuit of the present application
  • FIG. 1b is a schematic diagram of an equivalent circuit of the ESD protection circuit of FIG. 1;
  • Figure 2a is a schematic cross-sectional view of a P-type transistor
  • Figure 2b is a schematic cross-sectional view of an N-type transistor
  • Fig. 3 a is the schematic diagram of the second embodiment of the ESD protection circuit of the present application.
  • Fig. 3b is a schematic diagram of an equivalent circuit of the ESD protection circuit of Fig. 3a;
  • Fig. 4 a is the schematic diagram of the third embodiment of the ESD protection circuit of the present application.
  • FIG. 4b is a schematic diagram of an equivalent circuit of the ESD protection circuit of FIG. 4a;
  • Fig. 5 a is the schematic diagram of the 4th embodiment of the ESD protection circuit of the present application.
  • Fig. 5b is a schematic diagram of an equivalent circuit of the ESD protection circuit of Fig. 5a;
  • Fig. 6 is the schematic diagram that comprises the detection circuit of the ESD protection circuit of Fig. 5 a;
  • FIG. 7 is a timing chart of the operation of the detection circuit of FIG. 6 .
  • the ESD protection circuit provided in the embodiment of the present application is a part of the detection circuit, and its function is to provide electrostatic protection for the detection circuit.
  • the ESD protection circuit includes a window selection switch. Different from ordinary switches, the window selection switch in the embodiment of the present application has a positive charge discharge parasitic diode and a negative charge discharge parasitic diode, wherein the negative pole of the positive charge discharge parasitic diode and the detector The power supply of the circuit is coupled, the anode of the negative charge discharging parasitic diode is grounded, and the positive electrode of the positive charge discharging parasitic diode is coupled to the negative electrode of the negative charge discharging parasitic diode.
  • the positive/negative charge input at the input terminal will be released through the above two parasitic diodes to avoid the breakdown of related electronic devices, which is similar to the existing technology that requires additional devices such as diodes, GGNMOS or GDPMOS as ESD protection circuits.
  • the ESD protection circuit of the embodiment of the present application uses the parasitic diode of the switch itself as the electrostatic discharge path, avoiding the generation of large parasitic capacitance, and will not divert part of the signal volume, and will not affect the performance of the sensor. Therefore, the accuracy of the detection result of the detection circuit is guaranteed.
  • the sensor signal will flow through the parasitic capacitance, which will affect the transmission speed of the sensor signal, but the ESD protection circuit of the embodiment of the present application does not have a parasitic capacitance, and will not affect the transmission speed of the sensor signal .
  • FIG. 1a is a schematic diagram of a first embodiment of the ESD protection circuit 100 of the present application
  • FIG. 1b is a schematic diagram of an equivalent circuit of the ESD protection circuit 100 of FIG. 1a.
  • the ESD protection circuit 100 is a part of the detection circuit, and its function is to provide electrostatic protection for the detection circuit.
  • the ESD protection circuit 100 includes a first switch 101, a second switch 102 and a protection resistor 103, the first switch 101 and the second switch 102 form a window selection switch, and the first switch 101 is coupled to the input of the reference voltage Vcm and the ESD protection circuit 100 Between the terminals Rx, the second switch 102 is coupled between the input terminal RX and the output terminal RX out of the ESD protection circuit 100, and the protection resistor 103 is coupled with the first switch 101 and the second switch 102, as shown in FIG. 1a, The coupling node of the first switch 101 and the second switch 102 is defined as RX in , and the protection resistor 103 is coupled between the input terminal RX of the ESD protection circuit 100 and the node RX in .
  • the first switch 101 is controlled by the first signal ck1, ck1_N, and the first signal ck1, ck1_N is a complementary enabling signal, which can synchronously control whether the first switch 101 is turned on or not, and the second switch 102 is controlled by the second signal ck2 .
  • the first switch 101 is a complementary switch with two parasitic diodes
  • the second switch 102 is a common switch without parasitic diodes.
  • the first switch 101 includes a first parasitic diode 1011 and a second parasitic diode 1012, wherein the first parasitic diode 1011 is a positive charge discharge parasitic diode, and the second parasitic diode 1012 is The negative charge discharges the parasitic diode, the cathode of the first parasitic diode 1011 is coupled to the power supply of the detection circuit, the anode of the second parasitic diode 1012 is grounded, and the anode of the first parasitic diode 1011 is coupled to the cathode of the second parasitic diode 1012 .
  • protection resistor 103 Due to the existence of the protection resistor 103, when positive charges flow through the protection resistor 103, there will be a large voltage difference between the two ends of the protection resistor 103, so that the voltage of the node RX in will not be pulled up rapidly, so the electrons behind the node RX in The device will not bear a large voltage to avoid breakdown.
  • the second parasitic diode 1012 when the potential of the input terminal RX of the ESD protection circuit 100 drops rapidly and the accumulated negative charge cannot be discharged in time, since the anode of the second parasitic diode 1012 is grounded, the second parasitic diode 1012 will be turned on, and the negative charge will pass through the protection circuit.
  • the resistor 103 flows from the cathode of the second parasitic diode 1012 to the anode, and finally flows to the ground, so as to discharge the negative charge of the RX node.
  • the positive/negative charge input at the input terminal RX will be discharged through the first parasitic diode 1011 and the second parasitic diode 1012 of the first switch 101, so as to avoid the breakdown of related electronic devices, which is different from the existing technology that requires additional diodes Compared with devices such as GGNMOS or GDPMOS used as the ESD protection circuit, the ESD protection circuit of the embodiment of the present application uses the parasitic diode of the switch itself as the electrostatic discharge path, avoiding the generation of large parasitic capacitance, and will not divert part of the signal volume , it will not affect the performance of the sensor.
  • the sensor signal will flow through the parasitic capacitance, which will affect the transmission speed of the sensor signal, but the ESD protection circuit of the embodiment of the present application does not have a parasitic capacitance, and will not affect the transmission speed of the sensor signal .
  • the protection resistor 103 is coupled between the input terminal Rx of the ESD protection circuit 100 and the node RX in . It should be noted that, in other embodiments according to the present application, the protection resistor 103 may be connected in series on the path where the first switch 101 is located, that is, coupled between the node RX in and the first switch. The protection resistor 103 may also be connected in series on the path where the second switch 102 is located, that is, coupled between the node Rx_in and the second switch 102 . The setting method of the protection resistor 103 depends on specific application conditions.
  • the first switch 101 is a complementary switch, which includes a first P-type transistor 111 and a first N-type transistor 112, and the first P-type transistor 111 and the first N-type transistor 112 are arranged in parallel, Both the first P-type transistor 111 and the first N-type transistor 112 are field effect MOS transistors, the first parasitic diode 1011 is parasitic on the first P-type transistor 111, and the substrate of the first P-type transistor 111 is coupled to the power supply of the detection circuit , the second parasitic diode 1012 is parasitic on the first N-type transistor 112, and the substrate of the first N-type transistor 112 is grounded.
  • FIG. 2 a is a schematic cross-sectional view of the first P-type transistor 111 .
  • the P-type transistor 111 is a PNP type field effect transistor.
  • the P-type transistor 111 includes a source 1111, a drain 1112, a gate 1113 and a substrate 1114.
  • the source 1111 and the drain 1112 are connected to the P-type semiconductor, and the substrate 1114 is connected to the P-type semiconductor.
  • a silicon dioxide insulating layer is provided between the metal gate of the gate 1113 and the N-type semiconductor.
  • the positrons of the source 1111 and the drain 1112 of the P-type semiconductor are attracted and rush to the gate 1113, but due to the barrier of the oxide film, the positrons The positrons gather in the N-type semiconductor between the two P channels, thereby forming a current and making the source 1111 and the drain 1112 conduct. It is conceivable that there is a trench between the two P-type semiconductors, and the establishment of the gate voltage is equivalent to building a bridge between them. The size of the bridge is determined by the magnitude of the gate voltage.
  • the input voltage is used to control the output current of the first P-type transistor 111 .
  • the source 1111 is usually connected with the substrate 1114, so no parasitic diode will be formed between the source 1111 and the substrate 1114, and a PN junction will be formed between the drain 1112 and the substrate 1114 , that is, the first parasitic diode 1011 is formed, the drain 1112 is the anode of the first parasitic diode 1011 , and the substrate 1114 is the cathode of the first parasitic diode 1011 .
  • the substrate 1114 of the first parasitic diode 1011 is coupled to the power supply of the detection circuit.
  • the current of the power supply of the detection circuit cannot flow from the substrate 1114 flows into the drain 1111, and when the potential of the input terminal RX of the ESD protection circuit 100 rises to a positive value and reaches a certain level (greater than the potential of the detection circuit power supply), since the substrate 1114 is coupled with the power supply of the detection circuit, The first parasitic diode 1011 will be turned on, and the positive charge will flow from the anode to the cathode of the first parasitic diode 1011 through the protection resistor 103 , and finally flow to the power supply of the detection circuit, thereby discharging the positive charge of the RX node.
  • protection resistor 103 Due to the existence of the protection resistor 103, when positive charges flow through the protection resistor 103, there will be a large voltage difference between the two ends of the protection resistor 103, so the electronic device behind the node RX in will not bear a large voltage to avoid breakdown .
  • FIG. 2 b is a schematic cross-sectional view of the first N-type transistor 112 .
  • the working principle of the first N-type transistor 112 is similar to that of the first P-type transistor 111 , and will not be repeated here.
  • the output current of the first N-type transistor 112 can be controlled by controlling the input voltage of the gate 1123, and no parasitic diode will be formed between the source 1121 and the substrate 1124, and a PN junction will be formed between the drain 1122 and the substrate 1124 , that is, the second parasitic diode 1012 is formed, the drain 1122 is the cathode of the second parasitic diode 1012 , and the substrate 1124 is the anode of the second parasitic diode 1012 .
  • the substrate 1124 of the first N-type transistor 112 is grounded. Due to the directivity of the second parasitic diode 1012, when the potential of the input terminal RX of the ESD protection circuit 100 drops rapidly, the accumulated negative charge cannot When discharging in time, because the substrate 1124 of the second parasitic diode 1012 is grounded, the second parasitic diode 1011 will be turned on, and the negative charge will flow from the negative pole of the second parasitic diode 1011 to the positive pole through the protection resistor 103, and finally flow to the ground. Thus, the negative charge of the RX node is released.
  • the positive/negative charge input at the input terminal RX will be discharged through the first parasitic diode 1011 and the second parasitic diode 1012 of the first switch 101, so as to avoid the breakdown of related electronic devices, which is different from the existing technology that requires additional diodes Compared with devices such as GGNMOS or GDPMOS (gate-to-drain) used as the ESD protection circuit, the ESD protection circuit of the embodiment of the present application uses the parasitic diode of the switch itself as the electrostatic discharge path to avoid generating a large parasitic capacitance.
  • Fig. 3a is the schematic diagram of the second embodiment of the ESD protection circuit 200 of the present application
  • Fig. 3b is the schematic diagram of the equivalent circuit of the ESD protection circuit 200 of Fig. 3a
  • the protection circuit 100 is that the first switch 201 of the ESD protection circuit 200 of this embodiment is an ordinary switch, while the second switch 202 has a parasitic diode, as shown in Figure 3a and Figure 3b, the second switch 202 includes a third parasitic diode Diode 2021 and the fourth parasitic diode 2022, wherein, the third parasitic diode 2021 is a positive charge discharge parasitic diode, the fourth parasitic diode 2022 is a negative charge discharge parasitic diode, the negative pole of the third parasitic diode 2021 is coupled to the power supply of the detection circuit connected, the anode of the fourth parasitic diode 2022 is grounded, the anode of the third parasitic diode 2021 is coupled to the cathode of the fourth parasitic diode 2022, the structure and working principle of the third parasitic diode 2021 and the fourth parasitic diode 2022 refer to the above, here I won't go into details.
  • FIG. 4a is a schematic diagram of a third embodiment of the ESD protection circuit 300 of the present application
  • FIG. 4b is a schematic diagram of an equivalent circuit of the ESD protection circuit 300 of FIG. 4a.
  • the first switch 301 and the second switch 302 of the ESD protection circuit 300 of FIG. 4a both have parasitic diodes.
  • the first switch 301 of the ESD protection circuit 300 includes a first parasitic diode 3011 and a second parasitic diode 3012, wherein the first parasitic diode 3011 is a positive charge discharge parasitic diode, and the second parasitic diode 3012 is a negative charge discharge parasitic diode.
  • the cathode of the first parasitic diode 3011 is coupled to the power supply of the detection circuit
  • the anode of the second parasitic diode 3012 is grounded
  • the anode of the first parasitic diode 3011 is coupled to the cathode of the second parasitic diode 3012.
  • the second switch 302 of the ESD protection circuit 300 includes a third parasitic diode 3021 and a fourth parasitic diode 3022 , wherein the third parasitic diode 3021 is a positive charge discharge parasitic diode, and the second parasitic diode 3022 is a negative charge discharge parasitic diode. 4a and 4b, the cathode of the third parasitic diode 3021 is coupled to the power supply of the detection circuit, the anode of the fourth parasitic diode 3022 is grounded, and the anode of the third parasitic diode 3021 is coupled to the cathode of the fourth parasitic diode 3022.
  • protection resistor 303 Due to the existence of the protection resistor 303, when positive charges flow through the protection resistor 303, there will be a large voltage difference between the two ends of the protection resistor 303, so that the voltage of the node RX in will not be pulled up rapidly, so the electrons behind the node RX in The device will not bear a large voltage to avoid breakdown.
  • the protection resistor 303 Due to the existence of the protection resistor 303, when the positive charge flows through the protection resistor 303, there will be a large voltage difference between the two ends of the protection resistor 303, so that the voltage of the node RX in will not be pulled down rapidly, so the electrons behind the node RX in The device will not bear a large voltage to avoid breakdown.
  • the protection resistor 303 is coupled between the input terminal Rx of the ESD protection circuit 300 and the node RX in . It should be noted that, in other embodiments according to the present application, the protection resistor 303 may be connected in series on the path where the first switch 301 is located, that is, coupled between the node RX in and the first switch 301 . The protection resistor 303 may also be connected in series on the path where the second switch 302 is located, that is, coupled between the node RX in and the second switch 302 . The setting method of the protection resistor 303 depends on specific application conditions.
  • the first switch 301 includes a first P-type transistor 311 and a first N-type transistor 312, the first P-type transistor 311 and the first N-type transistor 312 are arranged in parallel, and the first parasitic diode 3011 Parasitic on the first P-type transistor 311, the substrate of the first P-type transistor 311 is coupled to the power supply of the detection circuit, the second parasitic diode 3012 is parasitic on the first N-type transistor 312, and the substrate of the first N-type transistor 312 is grounded .
  • the second switch 302 includes a second P-type transistor 321 and a second N-type transistor 322, the second P-type transistor 321 and the second N-type transistor 322 are arranged in parallel, the third parasitic diode 3021 is parasitic on the second P-type transistor 321, and the second P-type transistor 321 is parasitic on the second P-type transistor 321.
  • the substrate of the second P-type transistor 321 is coupled to the power supply of the detection circuit, the fourth parasitic diode 3022 is parasitic on the second N-type transistor 322 , and the substrate of the second N-type transistor 322 is grounded.
  • FIG. 5a is a schematic diagram of a fourth embodiment of the ESD protection circuit 400 of the present application
  • FIG. 5b is a schematic diagram of an equivalent circuit of the ESD protection circuit 400 of FIG. 5a.
  • the ESD protection circuit 400 of FIG. 5 a further includes a grounding switch 404 .
  • One end of the ground switch 404 is coupled to the input end RX of the ESD protection circuit 400 , and the other end is grounded.
  • the first switch 401 of the ESD protection circuit 400 includes a first parasitic diode 4011 and a second parasitic diode 4012, wherein the first parasitic diode 4011 is a positive charge discharge parasitic diode, and the second parasitic diode 4012 is a negative charge discharge parasitic diode.
  • the cathode of the first parasitic diode 4011 is coupled to the power supply of the detection circuit
  • the anode of the second parasitic diode 4012 is grounded
  • the anode of the first parasitic diode 4011 is coupled to the cathode of the second parasitic diode 4012 .
  • the second switch 402 of the ESD protection circuit 400 includes a third parasitic diode 4021 and a fourth parasitic diode 4022 , wherein the third parasitic diode 4021 is a positive charge discharge parasitic diode, and the fourth parasitic diode 4022 is a negative charge discharge parasitic diode.
  • the cathode of the third parasitic diode 4021 is coupled to the power supply of the detection circuit
  • the anode of the fourth parasitic diode 4022 is grounded
  • the anode of the third parasitic diode 4021 is coupled to the cathode of the fourth parasitic diode 4022 .
  • the grounding switch 404 of the ESD protection circuit 400 includes a fifth parasitic diode 4041 , and the anode of the fifth parasitic diode 4041 is grounded.
  • the grounding switch 404 is a large-sized N-type transistor, so it can better realize the grounding effect and can serve as an electrostatic discharge channel.
  • the fifth parasitic diode 4041 of the grounding switch 404 constitutes a primary ESD protection circuit
  • the first parasitic diode 4011 and the second parasitic diode 4012 of the first switch 401 constitutes a third parasitic diode 4021 and the second switch 402
  • the fourth parasitic diode 4022 constitutes a secondary ESD protection circuit.
  • the input terminal RX of the ESD protection circuit is exposed outside the chip, and it is easy to accumulate charges.
  • the potential of the input terminal RX will become a negative value. It will be discharged to the ground through the fifth parasitic diode 4041.
  • the voltage at the input terminal RX drops rapidly and the fifth parasitic diode 4041 cannot discharge in time, since the anodes of the second parasitic diode 4012 and the fourth parasitic diode 4022 are grounded, the second parasitic diode 4012 and the fourth parasitic diode 4022 will be turned on , the negative charges will flow from the negative poles of the second parasitic diode 4012 and the fourth parasitic diode 4022 to the positive poles through the protection resistor 403, and finally flow to the ground, so as to discharge the negative charges of the RX node.
  • the ESD protection circuit of the embodiment of the present application uses the parasitic diode of the switch itself as the electrostatic discharge path to avoid large parasitic capacitance and will not affect the sensor signal It will not affect the performance of the sensor if the transmission speed is high or part of the semaphore is separated.
  • first parasitic diode 4011 and the third parasitic diode 4021 are parasitic on the P-type transistor
  • the second parasitic diode 4012 , the fourth parasitic diode 4022 and the fifth parasitic diode 4041 are parasitic on the N-type transistor.
  • the protection resistor 403 is coupled between the input terminal Rx of the ESD protection circuit 100 and the node RX in .
  • the setting method of the protection resistor 403 can be determined according to specific application conditions.
  • Fig. 6 is a schematic diagram of a detection circuit 60 including the ESD protection circuit of Fig. 5a and Fig. 5b.
  • the detection circuit 60 is used to judge the magnitude of the received signal Vs on the node RX ini of the receiving circuit 61 .
  • the detection circuit 60 includes an ESD protection circuit 62, an operational amplifier 601, a capacitor unit 602 and a reset switch 603, and the operational amplifier 601, the capacitor unit 602 and the reset switch 603 constitute an integrating circuit.
  • the ESD protection circuit 62 includes a first switch 621, a second switch 622, a grounding switch 623 and a protection resistor 624.
  • the first switch 621 and the second switch 622 constitute a window selection switch.
  • the first switch 621, the second switch 622 and Both the grounding switches 623 are coupled to the protection resistor 624 .
  • the operational amplifier 601 has a positive terminal (+), a negative terminal (-) and an output terminal.
  • the capacitor unit 602 is coupled between the output terminal of the operational amplifier 601 and the negative terminal ( ⁇ ).
  • the reset switch 603 is arranged in parallel with the capacitor unit 602 .
  • the first switch 621 is coupled between the reference voltage Vcm and the node RX in , where the node RX in is the input end of the window selection switch.
  • the reference voltage Vcm is provided by the digital-to-analog converter DAC and the operational amplifier OPA1.
  • the second switch 622 is coupled between the node RX in and the negative terminal ( ⁇ ) of the operational amplifier 106
  • the ground switch 623 is coupled between the input node RX and ground.
  • the positive terminal (+) of the operational amplifier 601 is coupled to the reference voltage Vcm.
  • the reset switch 603 is controlled by the signal rst, the first switch 621 is controlled by the signal ck1, the second switch 621 is controlled by the signal ck2, and the grounding switch 621 is controlled by the signal ck3.
  • the first switch 621 and the second switch 622 are complementary switches, the first switch 621 and the second switch 622 respectively have two parasitic diodes, the first switch 621 and the second switch 622 are both It is formed by connecting P-type transistors and N-type transistors in parallel, and the substrates of the P-type transistors are all connected to the power supply of the detection circuit 60, while the substrates of the N-type transistors are all grounded.
  • the reset switch 603 and the ground switch 623 can be implemented using N-type transistors, and the substrate of the ground switch 624 is grounded.
  • the detector circuit 60 of the embodiment of the present application uses the parasitic diode of the switch itself of the ESD protection circuit as an electrostatic discharge path to avoid large parasitic capacitance. It will not affect the transmission speed of the sensor signal or take away part of the signal volume, and will not affect the performance of the sensor.
  • the receiving circuit 61 equivalently includes a receiving resistor 611 and a receiving capacitor 612 .
  • the receiving resistor 611 is coupled to the receiving capacitor 612 .
  • the receiving signal Vs is received by the receiving capacitor 612 after passing through the receiving resistor 611 .
  • the capacitance value of the capacitor unit 602 is CI, and the capacitance value of the receiving capacitor 612 is CS.
  • the detection circuit 61 shown in FIG. 6 includes the ESD protection circuit shown in FIG. 5a and FIG. 5b.
  • the detection circuit 61 may include The ESD protection circuit of the first embodiment shown in Figure 1b, the second embodiment shown in Figure 3a and Figure 3b or the third embodiment shown in Figure 4a and Figure 4b, the electrostatic discharge mode of each of the above ESD protection circuits is as above described in the text and will not be repeated here.
  • FIG. 7 is a timing diagram of an embodiment of the operation of the detector circuit in FIG. 6 .
  • the received signal Vs includes a plurality of sinusoidal waves with a period T (eg, time point T3 to time point T5 ).
  • the detection circuit 60 of the present application can be used to sample the amplitude of the received signal Vs. Since the amplitude of the received signal Vs may be very small, in order to increase the sensitivity of the detection circuit 60, the detection circuit 60 will integrate multiple cycles of the received signal Vs Amplitude sampling is performed in the same way, and the sampling results of multiple cycles are accumulated.
  • the detection circuit 60 of the present application is not only applicable to the case of a sine wave.
  • it can also be applied to the triangular wave or trapezoidal wave. As long as the slope of the rising edge from the trough to the peak of the above wave is less than 90 degrees, and the slope of the falling edge from the peak to the trough is greater than -90 degrees.
  • Vs represents the received signal at the node RX ini
  • RX represents the signal at the RX node
  • V out represents the output signal of the detection circuit 60 .
  • the detection circuit 60 Before the time point T1, the detection circuit 60 enters the reset phase.
  • the signal rst In the reset phase, the signal rst is at a high voltage level to turn on the reset switch 603, the signal ck1 is at a low voltage level to make the first switch 622 non-conductive, and the signal ck2 is at a low voltage level to make the second switch 623 is not conducting, the signal ck3 is at a low voltage level so that the grounding switch 624 is not conducting, and since the operational amplifier 601 forms negative feedback, the output terminal and the negative terminal (-) voltage of the operational amplifier 601 will be limited to be the same as the positive terminal (+) voltage , that is, the reference voltage Vcm. And the voltage at both ends of the capacitor unit 602 is the same so that the capacitor value is reset to zero.
  • the signal ck1 may be at a high voltage level to turn on the first switch 622 , so as to reset the receiving capacitor 612 of the receiving circuit 61 by the way.
  • the detection circuit 60 is used to detect the ultrasonic signal sent by the ultrasonic fingerprint recognition chip.
  • the lower plate of the piezoelectric material of the ultrasonic fingerprint recognition chip needs to be grounded or connected to a fixed level, that is, ESD protection
  • the input terminal RX of the circuit 62 is grounded or connected to a fixed level, at this time, the piezoelectric material will emit ultrasonic waves.
  • the detection circuit 60 provided in this application is not limited to detecting the ultrasonic signal sent by the ultrasonic fingerprint chip.
  • the received signal is in the receiving stage between the time point T1 and the time point T2, the signal ck3 is at a high voltage level to turn on the grounding switch 623, reset the switch 603, the first switch 621 and the second
  • the two switches 622 are both non-conductive, the input terminal RX of the ESD protection circuit 62 is grounded, and the ultrasonic signal sent by the ultrasonic fingerprint identification chip is received by the detection circuit 60 .
  • time points T3 and T5 are aligned with two consecutive valleys of the received signal Vs; time points T4 and time point T6 are aligned with two consecutive peaks of the received signal Vs.
  • the time length from the time point T3 to the time point T5 is equal to the period T of the received signal Vs.
  • the first switch 621 and the second switch 622 need to be switched according to the frequency of the received signal Vs.
  • the signal ck1 is at a low voltage level so that the first switch 621 is not turned on.
  • the second switch 622 is turned on, and the detection circuit 60 enters the sampling mode.
  • the first switch 621 is turned on and the second switch 622 is not turned on, so that the detection circuit 60 enters the non-sampling mode. Therefore, for two consecutive cycles starting from the time point T3, half of the time (T*0.5) detection circuit 60 in each cycle is in the sampling mode, and the other half of the time (T*0.5) detection circuit 60 is in the sampling mode. The non-sampling mode.
  • the voltage change of the received signal Vs is reflected in a specific ratio and accumulated at the output terminal of the operational amplifier 601 , and contributes to ⁇ Vout.
  • ⁇ Vout is proportional to the amplitude VA of the received signal Vs, the detection function can be realized, and the voltage Vout at the output terminal of the operational amplifier 601 will increase by ⁇ Vout every time the process of sampling mode is repeated, and the sampling mode can be repeated K times for K cycles, Make the output voltage continuously increase.
  • ⁇ Vout is obtained by the following formula (1):
  • K is an integer
  • K in FIG. 7 is 2 for illustrative purposes only.
  • the scope of K is not limited in the present application, as long as it is an integer greater than 0.
  • K can be increased, for example, in the range of 100 to 1000 orders of magnitude.
  • N signals can also be integrated, and K cycles of the signals can be sampled and integrated for K times, so as to further improve the sensitivity of the detection circuit 60 .
  • ⁇ Vout is obtained by the following formula (2):
  • K and N are integers, and the scope of K and N is not limited in the present application, as long as they are integers greater than 0.
  • the magnitude of the integration result depends on the signal quantity of the received signal VS. If an additional ESD protection circuit is introduced, a large parasitic capacitance will be introduced. Due to the limited bandwidth of the integrating circuit, a part of the signal quantity will be consumed by the parasitic capacitance, resulting in a deviation in the integration result.
  • the detection circuit 60 of the present application uses the parasitic diodes of the window selection switches 621 and 622 as the ESD discharge channel, thereby providing the function of electrostatic discharge without sacrificing the performance of the sensor circuit itself without introducing an additional discharge path .
  • the voltage change of the received signal Vs is not reflected and accumulated at the output terminal of the operational amplifier 601 , so that the voltage Vout at the output terminal of the operational amplifier 601 remains unchanged in the non-sampling mode.
  • the received signal Vs falls from a peak to a valley, but because the first switch 621 is turned on and the second switch 622 is not turned on, the voltage change of the received signal Vs is - 2*VA does not affect the voltage Vout at the output of the operational amplifier 601 . Therefore, the accumulated amount of the voltage Vout from the voltage change of the received signal Vs from the time point T3 to the time point T4 will not be offset.
  • the sampling mode of the timing diagram described in FIG. 7 is performed when the received signal VS rises from the trough to the peak.
  • the sampling mode can also be set to perform when the received signal VS falls from the peak to the trough. Or it can be set to start after a period of time after the peak of the received signal Vs and end before the trough arrives. It can also be set to start after a period of time after the trough of the received signal Vs and end before the peak. , is not limited here.
  • the present application also proposes an electronic device including a detection circuit 60 .
  • the electronic devices include but are not limited to mobile communication equipment, ultra-mobile personal computer equipment, portable entertainment equipment and other electronic equipment with data interaction functions.
  • the characteristic of mobile communication equipment is that it has mobile communication functions, and its main goal is to provide voice and data communication.
  • Such terminals include: smart phones (such as iPhone), multimedia phones, feature phones, and low-end phones.
  • Ultra-mobile personal computer devices belong to the category of personal computers, which have computing and processing functions, and generally have mobile Internet access features.
  • Such terminals include: PDA, MID and UMPC equipment, such as iPad.
  • Portable entertainment devices can display and play multimedia content.
  • Such devices include: audio and video players (such as iPod), handheld game consoles, e-books, as well as smart toys and portable car navigation devices.

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Abstract

提供了一种ESD保护电路（400），用于保护检波电路，包括窗口选择开关，窗口选择开关具有两个寄生二极管，其中一个寄生二极管的负极与检波电路的电源耦接，另一个寄生二极管的正极接地，一个寄生二极管的正极与另一个寄生二极管的负极耦接。提供的ESD保护电路（400）能够有效解决现有的检波电路中需额外引入其他器件的问题。还提供一种检波电路和相关电子装置。

Description

一种ESD保护电路、检波电路及相关电子装置
相关申请的交叉引用
本申请基于申请号为“2022101387976”、申请日为2022年02月15日的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此以引入方式并入本申请。
技术领域
本申请涉及一种电路，尤其涉及一种ESD保护电路、检波电路及相关电子装置。
背景技术
现代电子传感技术中，经常使用检波电路对传感器产生的波信号的幅度进行检测，以达到感测变量的目的。而由于传感器的感应极板通常裸露在外面，在晶圆制造以及后续封装、再加工流程中容易遭受静电损坏，导致芯片电路(例如检波电路)损毁，影响检波电路的检测性能，会降低芯片良率。
现有的技术中通常需要额外加入二极管、GGNMOS(gate-grounded NMOS，栅接地N型晶体管)或者GDPMOS(gate-to-drain PMOS，栅极接漏极P型晶体管)等器件来作为ESD(Electro-Static Discharge，静电释放)保护电路，但是这种ESD保护电路的面积较大，会引入较大的寄生电容，从而分走一部分信号量，影响检波电路的检测结果准确性。
发明内容
本申请提供一种ESD保护电路、检波电路和相关电子装置，能够有效解决现有的检波电路中需额外引入其他器件的问题。
第一方面，提供了一种ESD保护电路，包括窗口选择开关，所述窗口选择开关具有两个寄生二极管，其中一个所述寄生二极管的负极与所述检波电路的电源耦接，另一个所述寄生二极管的正极接地，所述一个寄生二极管的正极与所述另一个寄生二极管的负极耦接。
在一些可能的实现方式中，所述窗口选择开关包括第一开关和第二开关，所述第一开关耦接在参考电压和所述ESD保护电路的输入端之间，所述第二开关耦接在所述ESD保护电路的输入端和输出端之间。
在一些可能的实现方式中，所述第一开关包括第一寄生二极管和第二寄生二极管，所述第一寄生二极管的负极与所述检波电路的电源耦接，所述第二寄生二极管的正极接地，所述第一寄生二极管的正极与所述第二寄生二极管的负极耦接。
在一些可能的实现方式中，所述第一开关包括第一P型晶体管和第一N型晶体管，所述第一P型晶体管和所述第一N型晶体管并联设置，所述第一寄生二极管寄生于所述第一P型晶体管，所述第一P型晶体管的衬底与所述检波电路的电源耦接，所述第二寄生二极管寄生于所述第一N型晶体管，所述第一N型晶体管的衬底接地。
在一些可能的实现方式中，所述第二开关包括第三寄生二极管和第四寄生二极管，所述第三寄生二极管的负极与所述检波电路的电源耦接，所述第四 寄生二极管的正极接地，所述第三寄生二极管的正极与所述第四寄生二极管的负极耦接。
在一些可能的实现方式中，所述第二开关包括第二P型晶体管和第二N型晶体管，所述第二P型晶体管和所述第二N型晶体管并联设置，所述第三寄生二极管寄生于所述第二P型晶体管，所述第二P型晶体管的衬底与所述检波电路的电源耦接，所述第四寄生二极管寄生于所述第二N型晶体管，所述第二N型晶体管的衬底接地。
在一些可能的实现方式中，还包括保护电阻，所述保护电阻耦接在所述ESD保护电路的输入端和所述窗口选择开关之间。
在一些可能的实现方式中，还包括：接地开关，所述接地开关的一端耦接所述ESD保护电路的输入端，另一端接地，所述接地开关包括第五寄生二极管，所述第五寄生二极管的正极接地，所述第五寄生二极管的负极耦接所述ESD保护电路的输入端。
在一些可能的实现方式中，所述接地开关包括第三N型晶体管，所述第五寄生二极管寄生于所述第三N型晶体管，所述第三N型晶体管的衬底接地。
第二方面，提供一种检波电路，用来检测接收电路的接收信号的幅度，所述检波电路包括ESD保护电路，包括窗口选择开关，所述窗口选择开关具有两个寄生二极管，其中一个所述寄生二极管的负极与所述检波电路的电源耦接，另一个所述寄生二极管的正极接地，所述一个寄生二极管的正极与所述另一个寄生二极管的负极耦接；运算放大器，具有正端、负端与输出端；积分电容，耦接于所述运算放大器的所述输出端与所述负端之间；重置开关，与所述积分电容并联设置；所述ESD保护电路的窗口选择开关用于在所述检波电路的信号 检测过程中切换采样模式和非采样模式。
在一些可能的实现方式中，所述窗口选择开关包括第一开关和第二开关，所述第一开关耦接在参考电压和所述接收电路的输出端之间、所述第二开关耦接在所述接收电路的输出端和所述运算放大器的负端之间。
在一些可能的实现方式中，所述第一开关包括第一寄生二极管和第二寄生二极管，所述第一寄生二极管的负极与所述检波电路的电源耦接，所述第二寄生二极管的正极接地，所述第一寄生二极管的正极与所述第二寄生二极管的负极耦接。
在一些可能的实现方式中，所述第一开关包括第一P型晶体管和第一N型晶体管，所述第一P型晶体管和所述第一N型晶体管并联设置，所述第一寄生二极管寄生于所述第一P型晶体管，所述第一P型晶体管的衬底与所述检波电路的电源耦接，所述第二寄生二极管寄生于所述第一N型晶体管，所述第一N型晶体管的衬底接地。
在一些可能的实现方式中，所述第二开关包括第三寄生二极管和第四寄生二极管，所述第三寄生二极管的负极与所述检波电路的电源耦接，所述第四寄生二极管的正极接地，所述第三寄生二极管的正极与所述第四寄生二极管的负极耦接。
在一些可能的实现方式中，所述第二开关包括第二P型晶体管和第二N型晶体管，所述第二P型晶体管和所述第二N型晶体管并联设置，所述第三寄生二极管寄生于所述第二P型晶体管，所述第二P型晶体管的衬底与所述检波电路的电源耦接，所述第四寄生二极管寄生于所述第二N型晶体管，所述第二N型晶体管的衬底接地。
在一些可能的实现方式中，还包括保护电阻，所述保护电阻耦接在所述ESD保护电路的输入端和所述窗口选择开关之间。
在一些可能的实现方式中，还包括：所述ESD保护电路还包括接地开关，所述接地开关的一端耦接所述ESD保护电路的输入端，另一端接地，所述接地开关包括第五寄生二极管，所述第五寄生二极管的正极接地，所述第五寄生二极管的负极耦接所述ESD保护电路的输入端。
在一些可能的实现方式中，所述检波电路的信号检测过程包括重置阶段、接收阶段和一般阶段，在重置阶段，所述重置开关导通及所述第二开关不导通，所述运算放大器的所述输出端输出参考电压；在接收阶段，所述接地开关导通，所述重置开关、所述第一开关且所述第二开关均不导通，所述接收电路接收所述输入信号后产生所述接收信号。在所述一般阶段，所述重置开关不导通，以及所述接收信号包含周期为T的多个波，所述检波电路在对应所述多个波中的第一特定波的周期T中，有T*R的时间被设置为所述采样模式，以及有T*(1-R)的时间被设置为所述非采样模式，其中R大于0且小于1；以及所述检波电路在对应所述多个波中的第二特定波的周期T中，有T*R的时间被设置为所述采样模式，以及有T*(1-R)的时间被设置为所述非采样模式，其中：在所述采样模式，所述第一开关不导通且所述第二开关导通，使所述接收信号在所述采样模式期间的幅度改变依特定比例反应且累加在所述运算放大器的所述输出端；以及在所述非采样模式，所述第一开关导通且所述第二开关不导通，使所述接收电路产生的所述接收信号在所述非采样模式的幅度改变不反应且不累加在所述运算放大器的所述输出端，使所述运算放大器的所述输出端的电压在所述非采样模式维持不变。
在一些可能的实现方式中，所述接地开关包括第三N型晶体管，所述第五寄生二极管寄生于所述第三N型晶体管，所述第三N型晶体管的衬底接地。
第三方面，提供了一种相关电子装置，包括上述第二方面或其各实现方式所述的检波器。
与现有技术相比，本申请实施例的有益效果在于：本申请实施例提供的ESD保护电路能够通过开关自身寄生的二极管来实现静电电荷的泄放，能够防止电子器件被击穿，并且无需额外加入二极管、GGNMOS或者GDPMOS等器件来作为ESD保护电路，不会引入较大的寄生电容，不会分走信号量，从而保证检波电路检测结果的准确性。
附图说明
图1a是本申请的ESD保护电路的第一实施例的示意图；
图1b是图1的ESD保护电路的等效电路的示意图；
图2a是P型晶体管的剖面示意图；
图2b是N型晶体管的剖面示意图；
图3a是本申请的ESD保护电路的第二实施例的示意图；
图3b是图3a的ESD保护电路的等效电路的示意图；
图4a是本申请的ESD保护电路的第三实施例的示意图；
图4b是图4a的ESD保护电路的等效电路的示意图；
图5a是本申请的ESD保护电路的第四实施例的示意图；
图5b是图5a的ESD保护电路的等效电路的示意图；
图6是包括图5a的ESD保护电路的检波电路的示意图；
图7是图6的检波电路操作的时序图。
具体实施方式
下面将结合附图，对本申请中的技术方案进行描述。
本申请实施例提供的ESD保护电路，是检波电路的一部分，其作用是为检波电路提供静电保护。该ESD保护电路包括窗口选择开关，与普通的开关不同，本申请实施例的窗口选择开关具有正电荷泄放寄生二极管和负电荷泄放寄生二极管，其中，正电荷泄放寄生二极管的负极与检波电路的电源耦接，负电荷泄放寄生二极管的正极接地，正电荷泄放寄生二极管的正极与负电荷泄放寄生二极管的负极耦接。
当ESD保护电路的输入端的电势升高为正值，并达到一定程度(大于检波电路电源的电势)时，由于正电荷泄放寄生二极管的负极与检波电路的电源耦接，该寄生二极管会导通，正电荷会从该寄生二极管的正极流向负极，并最终流向检波电路的电源，从而将正电荷泄放掉。
当ESD保护电路的输入端的电势迅速降低，积累的负电荷不能及时泄放时，由于负电荷泄放寄生二极管的正极接地，该寄生二极管会导通，负电荷从该寄生二极管的负极流向正极，并最终流向大地，从而将负电荷泄放掉。
综上，输入端输入的正/负电荷会通过上述两个寄生二极管泄放掉，避免相关电子器件被击穿，与现有技术需要额外加入二极管、GGNMOS或者GDPMOS等器件来作为ESD保护电路相比，本申请实施例的ESD保护电路利用开关自身寄生的二极管来作为静电泄放通路，避免产生较大的寄生电容，不会分走一部分信号量，也就不会对传感器的性能产生影响，从而保证检波电路 检测结果的准确性。此外，由于寄生电容的存在，传感器信号会流经该寄生电容，会影响传感器信号的传输速度，而本申请实施例的ESD保护电路不存在寄生电容，则不会对传感器信号的传输速度产生影响。
以下对本申请的多个实施例进行论述。
参见图1a和图1b，图1a是本申请的ESD保护电路100的第一实施例的示意图，图1b是图1a的ESD保护电路100的等效电路的示意图。ESD保护电路100作为检波电路的一部分，其作用是为检波电路提供静电保护。ESD保护电路100包括第一开关101、第二开关102和保护电阻103，第一开关101和第二开关102构成窗口选择开关，第一开关101耦接在参考电压Vcm和ESD保护电路100的输入端Rx之间，第二开关102耦接在ESD保护电路100的输入端RX和输出端RX out之间，保护电阻103与第一开关101、第二开关102耦接，如图1a所示，第一开关101、第二开关102的耦接节点定义为RX in，保护电阻103耦接在ESD保护电路100的输入端RX和节点RX in之间。其中，第一开关101受第一信号ck1、ck1_N控制，第一信号ck1、ck1_N是互补使能信号，可以同步控制第一开关101的导通与否，第二开关102受第二信号ck2控制。
进一步地，第一开关101为互补开关，具有两个寄生二极管，而第二开关102为普通开关，不具有寄生二极管。具体地，如图1a和图1b所示，第一开关101包括第一寄生二极管1011和第二寄生二极管1012，其中，第一寄生二极管1011为正电荷泄放寄生二极管，第二寄生二极管1012为负电荷泄放寄生二极管，第一寄生二极管1011的负极与检波电路的电源耦接，第二寄生二极管1012的正极接地，第一寄生二极管1011的正极与第二寄生二极管1012的负极耦接。
参见图1a和图1b，当ESD保护电路100的输入端RX的电势升高为正值，并达到一定程度(大于检波电路电源的电势)时，由于第一寄生二极管1011的负极与检波电路的电源耦接，第一寄生二极管1011会导通，正电荷会经由保护电阻103，从第一寄生二极管1011的正极流向负极，并最终流向检波电路的电源，从而将Rx节点的正电荷泄放掉。由于保护电阻103的存在，正电荷在流过保护电阻103时，保护电阻103两端会存在较大的电压差，使得节点RX in的电压不会被迅速拉高，故节点RX in后的电子器件不会承担较大的电压，避免被击穿。
此外，当ESD保护电路100的输入端RX的电势迅速降低，积累的负电荷不能及时泄放时，由于第二寄生二极管1012的正极接地，第二寄生二极管1012会导通，负电荷会经由保护电阻103，从第二寄生二极管1012的负极流向正极，并最终流向大地，从而将RX节点的负电荷泄放掉。由于保护电阻103的存在，负电荷在流过保护电阻103时，保护电阻103两端会存在较大的电压差，使得节点RX in的电压不会被迅速拉低，故节点RX in后的电子器件不会承担较大的电压，避免被击穿。
综上，输入端RX输入的正/负电荷会通过第一开关101的第一寄生二极管1011和第二寄生二极管1012泄放掉，避免相关电子器件被击穿，与现有技术需要额外加入二极管、GGNMOS或者GDPMOS等器件来作为ESD保护电路相比，本申请实施例的ESD保护电路利用开关自身寄生的二极管来作为静电泄放通路，避免产生较大的寄生电容，不会分走一部分信号量，也就不会对传感器的性能产生影响。此外，由于寄生电容的存在，传感器信号会流经该寄生电容，会影响传感器信号的传输速度，而本申请实施例的ESD保护电路不存在 寄生电容，则不会对传感器信号的传输速度产生影响。
如图1a所示，保护电阻103耦接在ESD保护电路100的输入端Rx和节点RX in之间。需要说明的是，在根据本申请的其他实施例中，保护电阻103可以串联在第一开关101所在的通路上，也就是耦接在节点RX in和第一开关之间。保护电阻103也可以串联在第二开关102所在的通路上，也就是耦接在节点Rx_ in和第二开关102之间。保护电阻103的设置方式根据具体应用情况而定。
在根据本申请的一个实施例中，第一开关101为互补开关，其包括第一P型晶体管111和第一N型晶体管112，第一P型晶体管111和第一N型晶体管112并联设置，第一P型晶体管111和第一N型晶体管112均为场效应MOS管，第一寄生二极管1011寄生于第一P型晶体管111，第一P型晶体管111的衬底与检波电路的电源耦接，第二寄生二极管1012寄生于第一N型晶体管112，第一N型晶体管112的衬底接地。
参见图2a和图2b，现在介绍第一P型晶体管111和第一N型晶体管112的工作原理。
参见图2a，图2a是第一P型晶体管111的剖面示意图。P型晶体管111是PNP型场效应管，P型晶体管111包括源极1111、漏极1112、栅极1113和衬底1114，源极1111和漏极1112接到P型半导体上，衬底1114接到N型半导体上，栅极1113的金属栅极与N型半导体沟通之间设置有二氧化硅绝缘层。当负电压加在栅极1113上时，由于电场的作用，此时P型半导体的源极1111和漏极1112的正电子被吸引出来而涌向栅极1113，但由于氧化膜的阻挡，使得正电子聚集在两个P沟道之间的N型半导体中，从而形成电流，使源极1111和漏极1112之间导通。可以想象的是，两个P型半导体之间为一条沟，栅极电 压的建立相当于为它们之间搭了一座桥梁，该桥的大小由栅压的大小决定，因此可以通过控制栅极1113的输入电压来控制第一P型晶体管111的输出电流。
为了避免阈值电压的偏移，源极1111通常会与衬底1114连接在一起，因此源极1111和衬底1114之间不会形成寄生二极管，而在漏极1112和衬底1114会形成PN结，也就是会形成第一寄生二极管1011，漏极1112为第一寄生二极管1011的正极，衬底1114为第一寄生二极管1011的负极。
在根据本申请的实施例中，第一寄生二极管1011的衬底1114与检波电路的电源耦接，正常情况下，由于第一寄生二极管1011的方向性，检波电路的电源的电流无法从衬底1114流入漏极1111，而当ESD保护电路100的输入端RX的电势升高为正值，并达到一定程度(大于检波电路电源的电势)时，由于衬底1114与检波电路的电源耦接，第一寄生二极管1011会导通，正电荷会经由保护电阻103，从第一寄生二极管1011的正极流向负极，并最终流向检波电路的电源，从而将RX节点的正电荷泄放掉。由于保护电阻103的存在，正电荷在流过保护电阻103时，保护电阻103两端会存在较大的电压差，故节点RX in后的电子器件不会承担较大的电压，避免被击穿。
参见图2b，图2b是第一N型晶体管112的剖面示意图，第一N型晶体管112的工作原理与第一P型晶体管111的工作原理类似，在此不做赘述。第一N型晶体管112的输出电流可以通过控制栅极1123的输入电压来控制，源极1121和衬底1124之间亦不会形成寄生二极管，而在漏极1122和衬底1124会形成PN结，也就是会形成第二寄生二极管1012，漏极1122为第二寄生二极管1012的负极，衬底1124为第二寄生二极管1012的正极。
在根据本申请的实施例中，第一N型晶体管112的衬底1124接地，由 于第二寄生二极管1012的方向性，当ESD保护电路100的输入端RX的电势迅速降低，积累的负电荷不能及时泄放时，由于第二寄生二极管1012的衬底1124接地，第二寄生二极管1011会导通，负电荷会经由保护电阻103，从第二寄生二极管1011的负极流向正极，并最终流向大地，从而将RX节点的负电荷泄放掉。由于保护电阻103的存在，负电荷在流过保护电阻103时，保护电阻103两端会存在较大的电压差，故节点RX in后的电子器件不会承担较大的电压，避免被击穿。
综上，输入端RX输入的正/负电荷会通过第一开关101的第一寄生二极管1011和第二寄生二极管1012泄放掉，避免相关电子器件被击穿，与现有技术需要额外加入二极管、GGNMOS或者GDPMOS(gate-to-drain等器件来作为ESD保护电路相比，本申请实施例的ESD保护电路利用开关自身寄生的二极管来作为静电泄放通路，避免产生较大的寄生电容，不会分走一部分信号量，也就不会对传感器的性能产生影响。此外，由于寄生电容的存在，传感器信号会流经该寄生电容，会影响传感器信号的传输速度，而本申请实施例的ESD保护电路不存在寄生电容，则不会对传感器信号的传输速度产生影响。
参见图3a和图3b，图3a是本申请的ESD保护电路200的第二实施例的示意图，图3b是图3a的ESD保护电路200的等效电路的示意图，与图1a和图1b的ESD保护电路100不同的是，本实施例的ESD保护电路200的第一开关201为普通开关，而第二开关202具有寄生二极管，如图3a和图3b所示，第二开关202包括第三寄生二极管2021和第四寄生二极管2022，其中，第三寄生二极管2021为正电荷泄放寄生二极管，第四寄生二极管2022为负电荷泄放寄生二极管，第三寄生二极管2021的负极与检波电路的电源耦接，第四寄生 二极管2022的正极接地，第三寄生二极管2021的正极耦接第四寄生二极管2022的负极，第三寄生二极管2021和第四寄生二极管2022的结构和工作原理参照上文，在此不做赘述。
参见图4a和图4b，图4a是本申请的ESD保护电路300的第三实施例的示意图，图4b是图4a的ESD保护电路300的等效电路的示意图。与图1a的ESD保护电路100和图2a的ESD保护电路200不同的是，图4a的ESD保护电路300的第一开关301和第二开关302均具有寄生二极管。
具体地，ESD保护电路300的第一开关301包括第一寄生二极管3011和第二寄生二极管3012，其中，第一寄生二极管3011为正电荷泄放寄生二极管，第二寄生二极管3012为负电荷泄放寄生二极管。如图4a和图4b所示，第一寄生二极管3011的负极与检波电路的电源耦接，第二寄生二极管3012的正极接地,第一寄生二极管3011的正极耦接第二寄生二极管3012的负极。ESD保护电路300的第二开关302包括第三寄生二极管3021和第四寄生二极管3022其中，第三寄生二极管3021为正电荷泄放寄生二极管，第二寄生二极管3022为负电荷泄放寄生二极管。如图4a和图4b所示，第三寄生二极管3021的负极与检波电路的电源耦接，第四寄生二极管3022的正极接地,第三寄生二极管3021的正极耦接第四寄生二极管3022的负极。
参见图4a和图4b，当ESD保护电路300的输入端RX的电势升高为正值，并达到一定程度(大于检波电路电源的电势)时，由于第一寄生二极管3011和第三寄生二极管3021的负极与检波电路的电源耦接，第一寄生二极管3011和第三寄生二极管3021会导通，正电荷会经由保护电阻303，从第一寄生二极管3011和第三寄生二极管3021的正极流向负极，并最终流向检波电路的电源， 从而将RX节点的正电荷泄放掉。由于保护电阻303的存在，正电荷在流过保护电阻303时，保护电阻303两端会存在较大的电压差，使得节点RX in的电压不会被迅速拉高，故节点RX in后的电子器件不会承担较大的电压，避免被击穿。
此外，当ESD保护电路300的输入端RX的电势迅速降低，积累的负电荷不能及时泄放时，由于第二寄生二极管3012和第四寄生二极管3022的正极接地，第二寄生二极管3012和第四寄生二极管3022会导通，负电荷会经由保护电阻303，从第二寄生二极管3012和第四寄生二极管3022的负极流向正极，并最终流向大地，从而将RX节点的负电荷泄放掉。由于保护电阻303的存在，正电荷在流过保护电阻303时，保护电阻303两端会存在较大的电压差，使得节点RX in的电压不会被迅速拉低，故节点RX in后的电子器件不会承担较大的电压，避免被击穿。
如图4a和图4b所示，保护电阻303耦接在ESD保护电路300的输入端Rx和节点RX in之间。需要说明的是，在根据本申请的其他实施例中，保护电阻303可以串联在第一开关301所在的通路上，也就是耦接在节点RX in和第一开关301之间。保护电阻303也可以串联在第二开关302所在的通路上，也就是耦接在节点RX in和第二开关302之间。保护电阻303的设置方式根据具体应用情况而定。
在根据本申请的一个实施例中，第一开关301包括第一P型晶体管311和第一N型晶体管312，第一P型晶体管311和第一N型晶体管312并联设置，第一寄生二极管3011寄生于第一P型晶体管311，第一P型晶体管311的衬底与检波电路的电源耦接，第二寄生二极管3012寄生于第一N型晶体管312，第一N型晶体管312的衬底接地。第二开关302包括第二P型晶体管321和第二 N型晶体管322，第二P型晶体管321和第二N型晶体管322并联设置，第三寄生二极管3021寄生于第二P型晶体管321，第二P型晶体管321的衬底与检波电路的电源耦接，第四寄生二极管3022寄生于第二N型晶体管322，第二N型晶体管322的衬底接地。
第一P型晶体管311、第一N型晶体管312、第二P型晶体管321和第二N型晶体管322的工作原理参照上文所述，在此不做赘述。
参见图5a和图5b，图5a是本申请的ESD保护电路400的第四实施例的示意图，图5b是图5a的ESD保护电路400的等效电路的示意图。与图4a的ESD保护电路400不同的是，图5a的ESD保护电路400还包括接地开关404。接地开关404的一端耦接ESD保护电路400的输入端RX，另一端接地。
ESD保护电路400的第一开关401包括第一寄生二极管4011和第二寄生二极管4012，其中，第一寄生二极管4011为正电荷泄放寄生二极管，第二寄生二极管4012为负电荷泄放寄生二极管。如图5a和图5b所示，第一寄生二极管4011的负极与检波电路的电源耦接，第二寄生二极管4012的正极接地，第一寄生二极管4011的正极和第二寄生二极管4012的负极耦接。ESD保护电路400的第二开关402包括第三寄生二极管4021和第四寄生二极管4022，其中，第三寄生二极管4021为正电荷泄放寄生二极管，第四寄生二极管4022为负电荷泄放寄生二极管。如图5a和图5b所示，第三寄生二极管4021的负极与检波电路的电源耦接，第四寄生二极管4022的正极接地，第三寄生二极管4021的正极和第四寄生二极管4022的负极耦接。ESD保护电路400的接地开关404包括第五寄生二极管4041，该第五寄生二极管4041的正极接地。
一般地，接地开关404为大尺寸的N型晶体管，因而能够更好地实现接 地效果，并且能够充当静电泄放通道。
参见图5a和图5b，接地开关404的第五寄生二极管4041构成初级ESD保护电路，第一开关401的第一寄生二极管4011和第二寄生二极管4012、第二开关402的第三寄生二极管4021和第四寄生二极管4022构成次级ESD保护电路。通常ESD保护电路的输入端RX裸露在芯片外，容易积累电荷，当ESD保护电路400的输入端RX积累的正电荷达到一定程度，电势升高为正值，并达到一定程度时，接地开关404的第五寄生二极管4041会反向导通，正电荷会通过第五寄生二极管4041泄放掉到大地。当输入端RX的电压迅速升高，超过检波电路的电源电压，并且第五寄生二极管4041无法及时泄放，由于第一寄生二极管4011和第三寄生二极管4021的负极与检波电路的电源耦接，第一寄生二极管4011和第三寄生二极管4021会导通，正电荷会经由保护电阻403，从第一寄生二极管4011和第三寄生二极管4021的正极流向负极，并最终流向检波电路的电源，从而将RX节点的正电荷泄放掉。由于保护电阻403的存在，正电荷在流过保护电阻403时，保护电阻403两端会存在较大的电压差，使得节点RX in的电压不会被迅速拉高，故节点RX in后的电子器件不会承担较大的电压，避免被击穿。
此外，当ESD保护电路400的输入端RX积累负电荷到一定程度，输入端RX的电势会变为负值，并达到一定程度时，接地开关404的第五寄生二极管4041会导通，负电荷会通过第五寄生二极管4041泄放掉到大地。当输入端RX的电压迅速降低，并且第五寄生二极管4041无法及时泄放，由于第二寄生二极管4012和第四寄生二极管4022的正极接地，第二寄生二极管4012和第四寄生二极管4022会导通，负电荷会经由保护电阻403，从第二寄生二极管4012 和第四寄生二极管4022的负极流向正极，并最终流向检大地，从而将RX节点的负电荷泄放掉。由于保护电阻403的存在，负电荷在流过保护电阻403时，保护电阻403两端会存在较大的电压差，使得节点RX in的电压不会被迅速拉低，故节点RX in后的电子器件不会承担较大的电压，避免被击穿。
综上，输入端RX累积的正/负电荷会通过第一开关401、第二开关402和/或接地开关404的寄生二极管泄放掉，避免相关电子器件被击穿，与现有技术需要额外加入二极管、GGNMOS或者GDPMOS等器件来作为ESD保护电路相比，本申请实施例的ESD保护电路利用开关自身寄生的二极管来作为静电泄放通路，避免产生较大的寄生电容，不会影响传感器信号的传输速度或者分走一部分信号量，也就不会对传感器的性能产生影响。
进一步地，第一寄生二极管4011、第三寄生二极管4021寄生在P型晶体管上，第二寄生二极管4012、第四寄生二极管4022和第五寄生二极管4041寄生在N型晶体管上。具体工作原理，可以参考上文所述，在此不做赘述。
如图5a和图5b所示，保护电阻403耦接在ESD保护电路100的输入端Rx和节点RX in之间。如上文所述，保护电阻403的设置方式可以根据具体应用情况而定。
参见图6，图6是包括图5a和图5b的ESD保护电路的检波电路60的示意图。检波电路60用来判断接收电路61的在节点RX ini上的接收信号Vs的幅度。
如图6所示，检波电路60包括ESD保护电路62、运算放大器601、电容单元602和重置开关603,运算放大器601、电容单元602和重置开关603构成积分电路。
具体地，ESD保护电路62包括第一开关621、第二开关622和接地开关623和保护电阻624，第一开关621、第二开关622构成窗口选择开关，第一开关621、第二开关622和接地开关623均与保护电阻624耦接。运算放大器601具有正端(+)、负端(-)与输出端。电容单元602耦接于运算放大器601的输出端与负端(-)之间。重置开关603与电容单元602并联设置。第一开关621耦接于参考电压Vcm及节点RX in之间，此处的节点RX in是窗口选择开关的输入端。如图6所示，参考电压Vcm由数模转换器DAC和运算放大器OPA1提供。第二开关622耦接于节点RX in与运算放大器106的负端(-)之间，接地开关623耦接于输入节点RX与地之间。运算放大器601的正端(+)耦接于参考电压Vcm。其中重置开关603受信号rst控制，第一开关621受信号ck1控制，第二开关621受信号ck2控制，接地开关621受信号ck3控制。
在本实施例中，如上文所述，第一开关621、第二开关622为互补开关，第一开关621、第二开关622分别有两个寄生二极管，第一开关621和第二开关622均由P型晶体管和N型晶体管并联设置而成，并且P型晶体管的衬底都接检波电路60的电源，而N型晶体管的衬底均接地。重置开关603和接地开关623可以使用N型晶体管来实现，并且接地开关624的衬底接地。
如上所述，输入端RX累积的正/负电荷会通过第一开关621、第二开关622和/或接地开关623的寄生二极管泄放掉，避免相关电子器件被击穿，与现有技术需要额外加入二极管、GGNMOS或者GDPMOS等器件来作为ESD保护电路相比，本申请实施例的检波电路60通过ESD保护电路的开关自身寄生的二极管来作为静电泄放通路，避免产生较大的寄生电容，不会影响传感器信号的传输速度或者分走一部分信号量，也就不会对传感器的性能产生影响。
接收电路61等效地包含接收电阻611及接收电容612。接收电阻611与接收电容612耦接。接收信号Vs流经接收电阻611后，由接收电容612接收。其中电容单元602的电容值为CI，接收电容612的电容值为CS。
需要说明的是，图6示出的检波电路61包括的是如图5a和图5b所示的ESD保护电路，在本申请的检波电路的其他实施例中，检波电路61可以包括如图1a和图1b所示的第一实施例、图3a和图3b所示的第二实施例或图4a和图4b所示的第三实施例的ESD保护电路，以上各ESD保护电路的静电释放方式如上文所述，在此不做赘述。
参见图7，图7为图6的检波电路操作上的一个实施例的时序图。接收信号Vs包含周期为T(例如时间点T3至时间点T5)的正弦波的多个波。本申请的检波电路60可用来对接收信号Vs的幅度进行采样，由于接收信号Vs的幅度可能很小，因此为了增加检波电路60的灵敏度，检波电路60会针对多个周期的接收信号Vs以积分的方式进行幅度采样，并将多个周期的采样结果累积起来。本申请的检波电路60不仅适用于正弦波样态的情况。在某些实施例中，还可以适用于三角波或梯型波等样态。只要上述波的波谷升至波峰的上升沿的斜率小于90度，及波峰降至波谷的下降沿的斜率大于-90度即可。
在图7中，Vs表示节点RX ini处的接收信号，RX表示RX节点处的信号，V out表示检波电路60的输出信号。
在时间点T1之前，检波电路60进入重置阶段。在所述重置阶段，信号rst为高电压电平使重置开关603导通，信号ck1为低电压电平使第一开关622不导通，信号ck2为低电压电平使第二开关623不导通，信号ck3为低电压电平使接地开关624不导通，由于运算放大器601形成负反馈，运算放大器601 的输出端及负端(-)电压会被限制和正端(+)电压相同，即参考电压Vcm。且电容单元602两端电压相同使其电容值被清零。此外，在所述重置阶段，信号ck1可以为高电压电平使第一开关622导通，以顺便对接收电路61的接收电容612进行重置。
在本申请的一个实施例中，检波电路60用于对超声波指纹识别芯片发出的超声波信号进行检测，超声波指纹识别芯片的压电材料的下极板需要接地或者接到固定电平，即ESD保护电路62的输入端RX接地或者接到固定电平，此时，压电材料会发射超声波。当然，本申请提供的检波电路60不限于检测超声波指纹芯片发出的超声波信号。
如图7所示，在所接收的信号在时间点T1及时间点T2之间为接收阶段，信号ck3为高电压电平使接地开关623导通，重置开关603、第一开关621且第二开关622均不导通，ESD保护电路62的输入端RX接地，超声波指纹识别芯片发出的超声波信号，检波电路60的收到该信号Vs。
在时间点T2及时间点T7之间为一般阶段，重置开关603和接地开关623不导通。在图7所示的操作实施例中，时间点T3、时间点T5对齐接收信号Vs的连续两个波谷；时间点T4及时间点T6对齐接收信号Vs的连续两个波峰。时间点T3至时间点T5的时间长度等于接收信号Vs的周期T。
具体来说，在所述一般阶段若要对接收信号Vs进行幅度的采样，第一开关621和第二开关622需要依据接收信号Vs的频率进行开关。在图7所示的操作实施例中，在时间点T3至时间点T4之间的时间以及时间点T5至时间点T6之间的时间，信号ck1为低电压电平使第一开关621不导通，信号ck2为高电压电平使第二开关622导通，使检波电路60进入采样模式。在一般阶段 的其余时间，第一开关621导通且第二开关622不导通，使检波电路60进入非采样模式。因此，对时间点T3开始的连续两个周期来说，各周期中有一半的时间(T*0.5)检波电路60在所述采样模式，以及另一半的时间(T*0.5)检波电路60在所述非采样模式。
在图7中，虽然时间点T7的波谷的幅度略小于对应时间点T5的波谷的幅度，但是时间点T6至时间点T7之间的时间处于非采样模式，不会对输出的电压产生影响。
如图7所示，在每次采样模式中，接收信号Vs的电压改变量会依特定比例反应且累加在运算放大器601的输出端，并贡献ΔVout。以时间点T3至时间点T4之间的时间为例，若接收信号Vs的幅度为VA，接收信号Vs由波谷升至波峰，即接收信号Vs在时间点T3至时间点T4的电压改变量为2*VA，则ΔVout＝-2*VA*CS/CI，使运算放大器601的输出端的电压Vout由参考电压VCM往上累积。由于ΔVout和接收信号Vs的幅度VA正比，因此可以实现检波作用，并且每重复一次采样模式的过程，运算放大器601的输出端的电压Vout都会增加ΔVout，可以重复针对K个周期进行K次采样模式，使输出电压，不断累积上升。此时，ΔVout通过如下公式(1)获得：
Figure PCTCN2022093997-appb-000001
经过多次积分，以提高检波电路60的灵敏度。其中K为整数，图7中K为2仅为示意，本申请不限制K的范围，只要为大于0的整数即可。但为体现本申请的优势，K可以被提高，例如在100到1000的数量级范围。
此外，还可以N个信号进行积分，并且对其中信号中的K个周期进行K 次采样、积分，以进一步提高提高检波电路60的灵敏度。此时，ΔVout通过如下公式(2)获得：
Figure PCTCN2022093997-appb-000002
其中K、N为整数，本申请不限制K、N的范围，只要为大于0的整数即可。
在上述过程中，积分结果大小取决接收信号VS的信号量大小。若引入额外的ESD保护电路，将会引入较大的寄生电容。由于积分电路有限的带宽，导致一部分信号量会被寄生电容消耗掉，造成积分结果产生偏差。本申请的检波电路60采用窗口选择开关621、622寄生的二极管作为ESD泄放通道，从而在不引入额外泄放通路的基本上，既提供了静电释放的功能，又不牺牲传感器电路本身的性能。
在每次非采样模式中，接收信号Vs的电压改变量不会反应且不会累加在运算放大器601的输出端，使运算放大器601的输出端的电压Vout在所述非采样模式维持不变。以时间点T4至时间点T5之间的时间为例，接收信号Vs由波峰降至波谷，但因第一开关621导通且第二开关622不导通，因此接收信号Vs的电压改变量-2*VA不会影响运算放大器601的输出端的电压Vout。因此不会抵销掉时间点T3至时间点T4收信号Vs的电压改变量对电压Vout累加的量。
图7描述的时序图的采样模式是接收信号VS在波谷升至波峰的时间进行，在本申请的其他实施例中，采样模式也可以设置为在接收信号VS在波峰降至波谷的时间进行，或者设置为从接收信号Vs的波峰之后一段时间才开始进行，并在波谷来到之前便结束，还可以设置为从接收信号Vs的波谷之后一 段时间才开始进行，并在波峰来到之前便结束，在此不作限定。
本申请还提出一种包含检波电路60的电子装置。具体的，所述电子装置包括但不限于移动通信设备、超移动个人计算机设备、便携式娱乐设备和其他具有数据交互功能的电子设备。移动通信设备的特点是具备移动通信功能，并且以提供话音、数据通信为主要目标。这类终端包括：智能手机(例如iPhone)、多媒体手机、功能性手机，以及低端手机等。超移动个人计算机设备属于个人计算机的范畴，有计算和处理功能，一般也具备移动上网特性。这类终端包括：PDA、MID和UMPC设备等，例如iPad。便携式娱乐设备可以显示和播放多媒体内容。该类设备包括：音频、视频播放器(例如iPod)，掌上游戏机，电子书，以及智能玩具和便携式车载导航设备。
应理解，本申请实施例中的具体的例子只是为了帮助本领域技术人员更好地理解本申请实施例，而非限制本申请实施例的范围，本领域技术人员可以在上述实施例的基础上进行各种改进和变形，而这些改进或者变形均落在本申请的保护范围内。
以上所述，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以所述权利要求的保护范围为准。

Claims (20)

  1. 一种ESD保护电路，用于保护检波电路，其特征在于，包括窗口选择开关，所述窗口选择开关具有正电荷泄放寄生二极管和负电荷泄放寄生二极管，所述正电荷泄放寄生二极管的负极与所述检波电路的电源耦接，所述负电荷泄放寄生二极管的正极接地，所述正电荷泄放寄生二极管的正极与所述负电荷泄放寄生二极管的负极耦接。
  2. 如权利要求1所述的ESD保护电路，其特征在于，所述窗口选择开关包括第一开关和第二开关，所述第一开关耦接在参考电压和所述ESD保护电路的输入端之间，所述第二开关耦接在所述ESD保护电路的输入端和输出端之间。
  3. 如权利要求2所述的ESD保护电路，其特征在于，所述第一开关包括第一寄生二极管和第二寄生二极管，所述正电荷泄放寄生二极管包括所述第一寄生二极管，所述负电荷泄放寄生二极管包括所述第二寄生二极管。
  4. 如权利要求3所述的ESD保护电路，其特征在于，所述第一开关包括第一P型晶体管和第一N型晶体管，所述第一P型晶体管和所述第一N型晶体管并联设置，所述第一寄生二极管寄生于所述第一P型晶体管，所述第一P型晶体管的衬底与所述检波电路的电源耦接，所述第二寄生二极管寄生于所述第一N型晶体管，所述第一N型晶体管的衬底接地。
  5. 如权利要求2或3所述的ESD保护电路，其特征在于，所述第二开关包括第三寄生二极管和第四寄生二极管，所述正电荷泄放寄生二极管包括所述第三寄生二极管，所述负电荷泄放寄生二极管包括所述第四寄生二极管。
  6. 如权利要求5所述的ESD保护电路，其特征在于，所述第二开关包括第二P型晶体管和第二N型晶体管，所述第二P型晶体管和所述第二N型晶体管并联设置，所述第三寄生二极管寄生于所述第二P型晶体管，所述第二P型晶体管的衬底与所述检波电路的电源耦接，所述第四寄生二极管寄生于所述第二 N型晶体管，所述第二N型晶体管的衬底接地。
  7. 如权利要求1至4任一项所述的ESD保护电路，其特征在于，还包括保护电阻，所述保护电阻耦接在所述ESD保护电路的输入端和所述窗口选择开关之间。
  8. 如权利要求7所述的ESD保护电路，其特征在于，还包括：
    接地开关，所述接地开关的一端耦接所述ESD保护电路的输入端，另一端接地，所述接地开关包括第五寄生二极管，所述第五寄生二极管的正极接地，所述第五寄生二极管的负极耦接所述ESD保护电路的输入端。
  9. 如权利要求8所述的ESD保护电路，其特征在于，所述接地开关包括第三N型晶体管，所述第五寄生二极管寄生于所述第三N型晶体管，所述第三N型晶体管的衬底接地。
  10. 一种检波电路，用来检测接收电路的接收信号的幅度，其特征在于，所述检波电路包括：
    ESD保护电路，包括窗口选择开关，所述窗口选择开关具有正电荷泄放寄生二极管和负电荷泄放寄生二极管，所述正电荷泄放寄生二极管的负极与所述检波电路的电源耦接，所述负电荷泄放寄生二极管的正极接地，所述正电荷泄放寄生二极管的正极与所述负电荷泄放寄生二极管的负极耦接；
    运算放大器，具有正端、负端与输出端；
    积分电容，耦接于所述运算放大器的所述输出端与所述负端之间；
    重置开关，与所述积分电容并联设置；
    所述ESD保护电路的窗口选择开关用于在所述检波电路的信号检测过程中切换采样模式和非采样模式。
  11. 如权利要求10所述的检波电路，其特征在于，所述窗口选择开关包括第一开关和第二开关，所述第一开关耦接在参考电压和所述接收电路的输出端之间、所述第二开关耦接在所述接收电路的输出端和所述运算放大器的负端之间。
  12. 如权利要求11所述的检波电路，其特征在于，所述第一开关包括第一寄生二极管和第二寄生二极管，所述第一开关包括第一寄生二极管和第二寄生二极管，所述正电荷泄放寄生二极管包括所述第一寄生二极管，所述负电荷泄放寄生二极管包括所述第二寄生二极管。
  13. 如权利要求12所述的检波电路，其特征在于，所述第一开关包括第一P型晶体管和第一N型晶体管，所述第一P型晶体管和所述第一N型晶体管并联设置，所述第一寄生二极管寄生于所述第一P型晶体管，所述第一P型晶体管的衬底与所述检波电路的电源耦接，所述第二寄生二极管寄生于所述第一N型晶体管，所述第一N型晶体管的衬底接地。
  14. 如权利要求11或12所述的检波电路，其特征在于，所述第二开关包括第三寄生二极管和第四寄生二极管，所述正电荷泄放寄生二极管包括所述第三寄生二极管，所述负电荷泄放寄生二极管包括所述第四寄生二极管。
  15. 如权利要求14所述的检波电路，其特征在于，所述第二开关包括第二P型晶体管和第二N型晶体管，所述第二P型晶体管和所述第二N型晶体管并联设置，所述第三寄生二极管寄生于所述第二P型晶体管，所述第二P型晶体管的衬底与所述检波电路的电源耦接，所述第四寄生二极管寄生于所述第二N型晶体管，所述第二N型晶体管的衬底接地。
  16. 如权利要求10至13任一项所述的检波电路，其特征在于，还包括保护电阻，所述保护电阻耦接在所述ESD保护电路的输入端和所述窗口选择开关之间。
  17. 如权利要求16所述的检波电路，其特征在于，还包括：
    所述ESD保护电路还包括接地开关，所述接地开关的一端耦接所述ESD保护电路的输入端，另一端接地，所述接地开关包括第五寄生二极管，所述第五寄生二极管的正极接地，所述第五寄生二极管的负极耦接所述ESD保护电路的输入端。
  18. 如权利要求17所述的检波电路，其特征在于，所述检波电路的信号检 测过程包括重置阶段、接收阶段和一般阶段，在所述重置阶段，所述重置开关导通及所述第二开关不导通，所述运算放大器的所述输出端输出参考电压；
    在所述接收阶段，所述接地开关导通，所述重置开关、所述第一开关且所述第二开关均不导通，所述接收电路接收所述输入信号后产生所述接收信号；
    在所述一般阶段，所述重置开关不导通，以及所述接收信号包含周期为T的多个波，所述检波电路在对应所述多个波中的第一特定波的周期T中，有T*R的时间被设置为所述采样模式，以及有T*(1-R)的时间被设置为所述非采样模式，其中R大于0且小于1；以及所述检波电路在对应所述多个波中的第二特定波的周期T中，有T*R的时间被设置为所述采样模式，以及有T*(1-R)的时间被设置为所述非采样模式，其中：
    在所述采样模式，所述第一开关不导通且所述第二开关导通，使所述接收信号在所述采样模式期间的幅度改变依特定比例反应且累加在所述运算放大器的所述输出端；以及
    在所述非采样模式，所述第一开关导通且所述第二开关不导通，使所述接收电路产生的所述接收信号在所述非采样模式的幅度改变不反应且不累加在所述运算放大器的所述输出端，使所述运算放大器的所述输出端的电压在所述非采样模式维持不变。
  19. 如权利要求17所述的检波电路，其特征在于，所述接地开关包括第三N型晶体管，所述第五寄生二极管寄生于所述第三N型晶体管，所述第三N型晶体管的衬底接地。
  20. 一种电子装置，其特征在于，包括：
    如权利要求10至19中任一项所述的检波电路。
PCT/CN2022/093997 2022-02-15 2022-05-19 一种esd保护电路、检波电路及相关电子装置 WO2023155317A1 (zh)

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