WO2023145497A1 - Transistor à effet de champ, son procédé de production et cible de pulvérisation pour la production d'un transistor à effet de champ - Google Patents

Transistor à effet de champ, son procédé de production et cible de pulvérisation pour la production d'un transistor à effet de champ Download PDF

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WO2023145497A1
WO2023145497A1 PCT/JP2023/000903 JP2023000903W WO2023145497A1 WO 2023145497 A1 WO2023145497 A1 WO 2023145497A1 JP 2023000903 W JP2023000903 W JP 2023000903W WO 2023145497 A1 WO2023145497 A1 WO 2023145497A1
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field effect
effect transistor
target material
additive
oxide semiconductor
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PCT/JP2023/000903
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Japanese (ja)
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成紀 徳地
享祐 寺村
亮 白仁田
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三井金属鉱業株式会社
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Priority to JP2023521467A priority Critical patent/JP7364824B1/ja
Priority to KR1020247011009A priority patent/KR20240087785A/ko
Priority to CN202380013886.0A priority patent/CN118056282A/zh
Publication of WO2023145497A1 publication Critical patent/WO2023145497A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
    • C23C14/06—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the coating material
    • C23C14/08—Oxides
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
    • C23C14/22—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the process of coating
    • C23C14/34—Sputtering
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
    • C23C14/22—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the process of coating
    • C23C14/34—Sputtering
    • C23C14/3407—Cathode assembly for sputtering apparatus, e.g. Target
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
    • H01L21/2003—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy characterised by the substrate
    • H01L21/2015—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy characterised by the substrate the substrate being of crystalline semiconductor material, e.g. lattice adaptation, heteroepitaxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66969—Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78603—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the insulating substrate or support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel

Definitions

  • the present invention relates to a field effect transistor and its manufacturing method.
  • the present invention also relates to a sputtering target material for manufacturing field effect transistors.
  • TFTs thin film transistors
  • FPDs flat panel displays
  • IGZO Oxide semiconductors typified by -Zn composite oxides (hereinafter also referred to as “IGZO”) have attracted attention and are being put to practical use.
  • IGZO has the advantage of exhibiting high field effect mobility and low leakage current.
  • FPDs have become more sophisticated, materials have been proposed that exhibit field effect mobility higher than that of IGZO.
  • a flexible display which is one of the FPDs, has been attracting attention in recent years as it is possible to develop a wide range of applications due to its thin, light, and flexible functions.
  • a flexible organic EL display (OLED) using an organic EL as a display element does not require a backlight, and therefore is theoretically suitable for a flexible display.
  • a flexible base material is one of the important components that make up a flexible display.
  • Plastic films such as polyethylene terephthalate and polyethylene naphthalate are suitable as substrates for flexible displays because they are thin, lightweight, and have excellent flexibility.
  • plastic films have a problem with heat resistance.
  • post-annealing is required after film formation to improve electrical properties. should be done at low temperature.
  • post-annealing a film made of IGZO at a low temperature lowers the resistance of the film, making it difficult for the film to function as a semiconductor. Therefore, Patent Literature 1 proposes a technique for preventing the occurrence of low resistance caused by post-annealing at a low temperature in the production of an IGZO-based oxide semiconductor thin film.
  • the present invention provides a field effect transistor comprising a base material having a glass transition point of 250° C. or less or a base material used in a flexible wiring board, and an oxide semiconductor layer provided on the base material,
  • the oxide semiconductor layer is composed of an oxide containing an indium (In) element, a zinc (Zn) element and an additive element (X),
  • the additive element (X) is at least one element selected from tantalum (Ta) element, strontium (Sr) element and niobium (Nb) element
  • the present invention provides a field effect transistor in which the atomic ratio of each element satisfies all of the formulas (1) to (3) (X in the formula is the sum of the content ratios of the additive elements). 0.4 ⁇ (In+X)/(In+Zn+X) ⁇ 0.8 (1) 0.2 ⁇ Zn/(In+Zn+X) ⁇ 0.6 (2) 0.001 ⁇ X/(In+Zn+X) ⁇ 0.015 (3)
  • the present invention uses a sputtering target material made of an oxide containing an indium (In) element, a zinc (Zn) element, and an additive element (X) (the additive element (X) is a tantalum (Ta) element, a strontium (Sr) and a niobium (Nb) element.), in an atmosphere having an oxygen concentration of 21 vol% or more and 49 vol% or less, a base material used for a flexible wiring board or a glass transition temperature of 250°C or less. Sputtering a base material having points to form an oxide semiconductor derived from the target material, The present invention provides a method for manufacturing a field effect transistor, including a step of annealing the oxide semiconductor at 50° C. or higher and 250° C. or lower.
  • the present invention is composed of an oxide containing an indium (In) element, a zinc (Zn) element and an additive element (X),
  • the additive element (X) is at least one element selected from tantalum (Ta) element, strontium (Sr) element and niobium (Nb) element,
  • a sputtering target material for producing a field effect transistor comprising a base material used for a flexible wiring board or a base material having a glass transition point of 250° C. or lower and an oxide semiconductor layer derived from the sputtering target material. It provides. 0.4 ⁇ (In+X)/(In+Zn+X) ⁇ 0.8 (1) 0.2 ⁇ Zn/(In+Zn+X) ⁇ 0.6 (2) 0.001 ⁇ X/(In+Zn+X) ⁇ 0.015 (3)
  • FIG. 1 is a schematic diagram showing the structure of the field effect transistor of the present invention.
  • 2 is a scanning electron microscope image of the target material obtained in Example 1.
  • FIG. 1 is a schematic diagram showing the structure of the field effect transistor of the present invention.
  • the present invention relates to a field effect transistor (hereinafter also referred to as "FET").
  • An FET of the present invention includes a substrate and an oxide semiconductor layer provided on the substrate.
  • the FET of the present invention preferably includes a step of forming an oxide semiconductor layer on a base material by a sputtering method, and a step of post-annealing after forming the oxide semiconductor layer to improve electrical characteristics. and manufactured by a method comprising:
  • the conventional oxide semiconductor layer must be treated at a high temperature, and the base material with low heat resistance deforms or melts. can't get it to work.
  • a material that does not have sufficiently high heat resistance such as a material used for a flexible wiring board, or a material with a low glass transition point (for example, a material with a glass transition point of 250° C. or less), can be used as the base material.
  • a material with a low glass transition point for example, a material with a glass transition point of 250° C. or less
  • the film can be annealed at a relatively low temperature, so that the oxide semiconductor layer can be formed.
  • FIG. 1 schematically shows one embodiment of the FET of the present invention.
  • the FET having the structure shown in the drawing is an example of the embodiment of the present invention, and needless to say, the FET of the present invention is not limited to the structure shown in the drawing.
  • the FET 1 shown in the figure is formed on one surface of the substrate 10 .
  • a channel layer 20, a source electrode 30 and a drain electrode 31 are arranged on one surface of the substrate 10, and a gate insulating film 40 is formed so as to cover them.
  • a gate electrode 50 is arranged on the gate insulating film 40 .
  • a protective layer 60 is arranged on the uppermost portion.
  • the channel layer 20 is composed of an oxide semiconductor layer.
  • the "oxide semiconductor layer provided on the base material” as used in the present invention means (i) an oxide semiconductor layer via one or more layers provided in contact with the surface of the base material. and (ii) the oxide semiconductor layer is provided in contact with the surface of the substrate.
  • the oxide semiconductor layer in the FET of the present invention contains indium (In) element, zinc ( Zn) element and an additive element (X).
  • the additive element (X) consists of at least one element selected from tantalum (Ta) element, strontium (Sr) element and niobium (Nb) element.
  • the oxide semiconductor layer of the present invention contains In, Zn, and an additive element (X) as metal elements constituting the layer. Or, inevitably, trace elements may be included. Trace elements include, for example, elements contained in organic additives described later and media raw materials such as ball mills that are mixed during the production of the target material.
  • Examples of trace elements contained in the oxide semiconductor layer of the present invention include Fe, Cr, Ni, Al, Si, W, Zr, Na, Mg, K, Ca, Ti, Y, Ga, Sn, Ba, La, Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, Lu, Pb and the like.
  • Their content is usually 100 ppm by mass (hereinafter also referred to as “ppm”) or less with respect to the total mass of oxides containing In, Zn and X contained in the oxide semiconductor layer of the present invention. is preferred, more preferably 80 ppm or less, and still more preferably 50 ppm or less.
  • the total amount of these trace elements is preferably 500 ppm or less, more preferably 300 ppm or less, still more preferably 100 ppm or less.
  • the oxide semiconductor layer of the present invention contains a trace element, the total mass also includes the mass of the trace element.
  • the atomic ratio of the metal elements constituting it is within a specific range from the viewpoint of improving the performance of the FET of the present invention.
  • the atomic ratio represented by the following formula (1) is satisfied (X in the formula is the sum of the content ratios of the additive elements.
  • Zn preferably satisfies the atomic ratio represented by the following formula (2).
  • X preferably satisfies the atomic ratio represented by the following formula (3). 0.001 ⁇ X/(In+Zn+X) ⁇ 0.015 (3)
  • the FET of the present invention has high field effect mobility, low leakage current, and is close to 0V. It indicates the threshold voltage. From the viewpoint of making these advantages even more remarkable, it is more preferable that In and X satisfy the following formulas (1-2) to (1-6).
  • the additive element (X) one or more selected from Ta, Sr and Nb are used as described above. Each of these elements can be used alone, or two or more of them can be used in combination.
  • the use of Ta as the additive element (X) is advantageous from the viewpoint of the overall performance of the FET of the present invention and the economics of manufacturing the sputtering target material used when manufacturing the oxide semiconductor layer by sputtering. It is preferable from the point of view of sex.
  • Preferably only Ta is used. However, three types of Ta, Sr and Nb may be used.
  • the FET of the present invention satisfies the following equation (4) with respect to the atomic ratio of In to X. It is preferable from the point of further increasing the field effect mobility of the physical semiconductor device and from the point of exhibiting a threshold voltage close to 0V. 0.970 ⁇ In/(In+X) ⁇ 0.999 (4)
  • the atomic ratio of In to X is determined by the following formulas (4-2) to (4-4). More preferably. 0.980 ⁇ In/(In+X) ⁇ 0.997 (4-2) 0.990 ⁇ In/(In+X) ⁇ 0.995 (4-3) 0.990 ⁇ In/(In+X) ⁇ 0.993 (4-4)
  • the oxide semiconductor layer in the FET of the present invention contains In, Zn, the additive element X, and oxygen, and may contain other elements in addition, from the viewpoint of further increasing the field effect mobility of the FET.
  • the oxide semiconductor layer preferably contains In, Zn, an additive element X, and oxygen, and the remainder is composed of unavoidable impurities.
  • the ratio of each metal contained in the oxide semiconductor layer of the present invention is measured by, for example, X-ray photoelectron spectroscopy (XPS) or ICP emission spectrometry.
  • XPS X-ray photoelectron spectroscopy
  • ICP emission spectrometry ICP emission spectrometry
  • the field effect mobility (cm 2 /Vs) of the TFT of the present invention is preferably 20 cm 2 /Vs or more, more preferably 30 cm 2 /Vs or more, and 50 cm 2 /Vs or more. more preferably 60 cm 2 /Vs or more, even more preferably 70 cm 2 /Vs or more, even more preferably 80 cm 2 /Vs or more, 100 cm 2 /Vs or more is particularly preferred.
  • a higher value of the field effect mobility is preferable from the standpoint of improving the functionality of the FPD.
  • the oxide semiconductor layer in the FET of the present invention preferably has an amorphous structure.
  • the substrate in the FET of the present invention is composed of a material used for flexible wiring boards or composed of a material having a glass transition point of 250° C. or lower.
  • the use of substrates composed of these materials is advantageous in that flexible displays, for example, can be easily manufactured using the FETs of the present invention.
  • a material constituting the base material a resin base material is preferable. Or two or more types are mentioned.
  • these resin substrates are made of a material having a glass transition point of 250° C. or less. These materials are for example in the form of films.
  • materials constituting the base material include polyethylene naphthalate (PEN), polyethylene terephthalate (PET), polyphenylene sulfide (PPS), polyetheretherketone (PEEK), polystyrene (PS), polyethersulfone ( PES), polycarbonate (PC), triacetyl cellulose (TAC), polybutylene terephthalate (PBT), polysilane, polysiloxane, polysilazane, polycarbosilane, polyacrylate , polymethacrylate, polymethylacrylate, polyethylacrylate, polyethylmethacrylate, cycloolefin copolymer (COC), cycloolefin polymer (COP), polyethylene (PE), polypropylene (PP ), polymethyl methacrylate (PMMA), polyacetal (POM), polytetrafluoroethylene (PTFE), polyvinyl chloride (PVC), polyvinylidene fluoride (PV
  • the material used for the flexible wiring board in other words, the heat resistance is sufficiently high.
  • An oxide semiconductor layer with high field-effect mobility can be successfully formed even with a base material made of a material that does not have a high field-effect mobility. From this point of view, it is possible to use a material having a glass transition point of preferably 250° C. or lower, more preferably 200° C. or lower, and even more preferably 180° C. or lower as the base material.
  • the glass transition point of the material constituting the substrate is preferably 0° C. or higher, more preferably 25° C. or higher, and 80° C. or higher. is more preferably 85° C. or higher, and even more preferably 90° C. or higher.
  • the method for measuring the glass transition point of the substrate is as described below.
  • the glass transition point is determined by the DTA method in accordance with JIS-K-7121-1987 (method for measuring transition temperature of plastics).
  • STA 2500 Regulus manufactured by NETZSCH is typically used to measure the midpoint glass transition temperature.
  • the base material of the FET of the present invention preferably has a thickness of 1 ⁇ m or more and 500 ⁇ m or less, more preferably 1 ⁇ m or more and 300 ⁇ m or less, and even more preferably 1 ⁇ m or more and 100 ⁇ m or less. .
  • the base material in the FET of the present invention preferably has a thermal expansion coefficient of 5 ppm/° C. or more and 80 ppm/° C. or less, more preferably 5 ppm/° C. or more and 50 ppm/° C. or less. ° C. or more and 20 ppm/° C. or less is more preferable.
  • a semiconductor device including the FET of the present invention is also provided.
  • semiconductor device refers to all devices that can function by utilizing semiconductor characteristics.
  • electro-optical devices, semiconductor circuits, and electronic devices are all semiconductor devices.
  • the semiconductor device of the present invention is useful as a thin film transistor used for FPD.
  • the FET of the present invention can be manufactured using a known photolithography method. Particularly when manufacturing the oxide semiconductor layer of the present invention, a sputtering target material described later is used and sputtering is performed under the following conditions. be able to.
  • a sputtering target material described later is used and sputtering is performed under the following conditions. be able to.
  • the sputtering method for example, a DC sputtering method can be used.
  • the temperature of the substrate during sputtering can be set to, for example, 10° C. or higher and 250° C. or lower.
  • Sputtering may also be performed at a substrate temperature that does not exceed the glass transition point of the substrate.
  • the ultimate vacuum degree during sputtering can be set to less than 0.001 Pa, for example.
  • the sputtering gas for example, a mixed gas of Ar and O 2 can be used.
  • the O 2 gas concentration in the sputtering gas can be set to 21 vol% or more and 49 vol% or less, particularly 22 vol% or more and 45 vol% or less.
  • the sputtering gas pressure can be set to, for example, 0.1 Pa or more and 3 Pa or less.
  • Sputtering power can be set to, for example, 0.1 W/cm 2 or more and 10 W/cm 2 or less.
  • an oxide semiconductor layer can be successfully manufactured on even a substrate composed of a material that does not have sufficiently high heat resistance.
  • the oxide semiconductor layer is preferably annealed.
  • the purpose of the annealing treatment is to impart desired performance to the oxide semiconductor layer.
  • the temperature of the annealing treatment is preferably 50° C. or higher and 250° C. or lower, more preferably 80° C. or higher and 200° C. or lower, even more preferably 100° C. or higher and 180° C. or lower. °C or higher and 150 °C or lower is even more preferable.
  • the annealing time is preferably 1 minute or more and 180 minutes or less, more preferably 2 minutes or more and 120 minutes or less, and even more preferably 3 minutes or more and 60 minutes or less.
  • the annealing atmosphere is preferably an oxygen atmosphere including atmospheric pressure.
  • Annealing treatment for the oxide semiconductor layer can be performed immediately after the oxide semiconductor layer is formed. Alternatively, one or more layers may be formed after the oxide semiconductor layer is formed, and then annealing treatment may be performed.
  • a sputtering target material is at least one element selected from tantalum (Ta) element, strontium (Sr) element and niobium (Nb) element). That is, this sputtering target material is provided on a base material used for a flexible wiring board or a base material having a glass transition point of 250° C.
  • the sputtering target material for manufacturing FETs is also referred to as "the target material of the present invention" for convenience.
  • a sputtering target material for FET manufacturing in which the atomic ratio of each element satisfies all of the following formulas (1) to (3) (X in the formula is the sum of the content ratios of the additive elements.) should be used. 0.4 ⁇ (In+X)/(In+Zn+X) ⁇ 0.8 (1) 0.2 ⁇ Zn/(In+Zn+X) ⁇ 0.6 (2) 0.001 ⁇ X/(In+Zn+X) ⁇ 0.015 (3)
  • the atomic ratio of each element constituting the target material preferably further satisfies the formula (4). 0.970 ⁇ In/(In+X) ⁇ 0.999 (4)
  • the target material of the present invention is composed of oxides containing In, Zn and X as described above.
  • This oxide can be an In oxide, a Zn oxide or an X oxide.
  • this oxide may be a composite oxide of any two or more elements selected from the group consisting of In, Zn and X.
  • Specific examples of composite oxides include In—Zn composite oxide, Zn—Ta composite oxide, In—Ta composite oxide, In—Nb composite oxide, Zn—Nb composite oxide, In—Sr composite oxide Examples include oxides, Zn--Sr composite oxides, In--Zn--Ta composite oxides, In--Zn--Nb composite oxides, and In--Zn--Sr composite oxides, but are not limited to these.
  • the target material of the present invention particularly includes an In 2 O 3 phase, which is an In oxide, and a Zn 3 In 2 O 6 phase, which is a composite oxide of In and Zn. It is preferable from the viewpoint of increasing resistance and reducing resistance.
  • the fact that the target material of the present invention contains the In 2 O 3 phase and the Zn 3 In 2 O 6 phase can be confirmed by X-ray diffraction (hereinafter also referred to as “ XRD ”) measurement of the target material of the present invention. It can be determined by whether three phases and a Zn3In2O6 phase are observed .
  • the In 2 O 3 phase in the present invention may contain a trace amount of Zn element.
  • both the In2O3 phase and the Zn3In2O6 phase preferably contain the additive element (X).
  • the additive element (X) when the additive element (X) is homogeneously dispersed throughout the target material, the additive element (X) is uniformly contained in the oxide semiconductor formed from the target material of the present invention. A fine oxide semiconductor film can be obtained.
  • the inclusion of the additional element (X) in both the In 2 O 3 phase and the Zn 3 In 2 O 6 phase can be measured by, for example, energy dispersive X-ray spectroscopy (hereinafter also referred to as “EDX”). can.
  • EDX energy dispersive X-ray spectroscopy
  • the fact that the In 2 O 3 phase has a crystal grain size that satisfies a specific range indicates the density and strength of the target material of the present invention. It is preferable from the viewpoint of increasing the resistance and reducing the resistance.
  • the crystal grain size of the In 2 O 3 phase is preferably 3.0 ⁇ m or less, more preferably 2.7 ⁇ m or less, and even more preferably 2.5 ⁇ m or less. The smaller the crystal grain size, the better, and although the lower limit is not particularly defined, it is usually 0.1 ⁇ m or more.
  • the crystal grain size of the Zn 3 In 2 O 6 phase also satisfies a specific range. It is preferable from the viewpoint of increasing the density and strength of the material and reducing the resistance.
  • the crystal grain size of the Zn 3 In 2 O 6 phase is preferably 3.9 ⁇ m or less, more preferably 3.5 ⁇ m or less, even more preferably 3.0 ⁇ m or less, It is more preferably 2.5 ⁇ m or less, even more preferably 2.3 ⁇ m or less, particularly preferably 2.0 ⁇ m or less, and most preferably 1.9 ⁇ m or less.
  • a target material may be manufactured by the method described later.
  • the crystal grain size of the In 2 O 3 phase and the crystal grain size of the Zn 3 In 2 O 6 phase are measured by observing the target material of the present invention with a scanning electron microscope (hereinafter also referred to as “SEM”). be done. A specific measuring method will be described in detail in Examples described later.
  • the target material of the present invention contains In, Zn, the additive element X and oxygen, and may contain other elements in addition. From the viewpoint of increasing the cost, it is preferable that the target material contains In, Zn, the additive element X, and oxygen, and the remainder consists of unavoidable impurities.
  • an oxide powder which is a raw material of a target material
  • the compact is fired to obtain a target material composed of a sintered compact.
  • methods hitherto known in the art such as slip casting, can be employed.
  • a slurry similar to that used in the casting method is spray-dried to obtain a dry powder.
  • the resulting dry powder is filled into a mold and subjected to CIP molding.
  • the firing temperature is preferably 1200° C. or higher and 1600° C. or lower, more preferably 1300° C. or higher and 1500° C. or lower, and still more preferably 1350° C. or higher and 1450° C. or lower.
  • the firing time is preferably from 1 hour to 100 hours, more preferably from 2 hours to 50 hours, and even more preferably from 3 hours to 30 hours.
  • the heating rate is preferably 5°C/hour or more and 500°C/hour or less, more preferably 10°C/hour or more and 200°C/hour or less, and 20°C/hour or more and 100°C/hour or less. is more preferred.
  • a phase of In and Zn composite oxides such as Zn 5 In 2 O 8
  • Zn 5 In 2 O 8 a phase of In and Zn composite oxides, such as Zn 5 In 2 O 8
  • the raw material powder contains In 2 O 3 powder and ZnO powder
  • Zn 5 In 2 O 8 phase is generated, volume diffusion proceeds and densification is promoted, so it is preferable to reliably generate the Zn 5 In 2 O 8 phase.
  • the temperature to be maintained is not necessarily limited to one specific temperature, but may be a temperature range with a certain width.
  • a specific temperature selected from the range of 1000 ° C. or higher and 1250 ° C. or lower is T (° C.)
  • T ⁇ 10 ° C. preferably T ⁇ 5°C, more preferably T ⁇ 3°C, still more preferably T ⁇ 1°C.
  • the time for maintaining this temperature range is preferably 1 hour or more and 40 hours or less, more preferably 2 hours or more and 20 hours or less.
  • the target material obtained in this way can be processed to a predetermined size by grinding or the like.
  • a sputtering target is obtained by joining this to a base material.
  • shape of the target material there is no particular limitation on the shape of the target material, and conventionally known shapes such as a flat plate shape and a cylindrical shape can be adopted.
  • the present invention further discloses the following field effect transistors, methods for manufacturing the same, and sputtering target materials for manufacturing field effect transistors.
  • a field effect transistor comprising a substrate having a glass transition point of 250° C.
  • the oxide semiconductor layer is composed of an oxide containing an indium (In) element, a zinc (Zn) element and an additive element (X),
  • the additive element (X) is at least one element selected from tantalum (Ta) element, strontium (Sr) element and niobium (Nb) element,
  • a field effect transistor in which the atomic ratio of each element satisfies all of the formulas (1) to (3) (X in the formula is the sum of the content ratios of the additive elements).
  • a field effect transistor comprising a substrate used in a flexible wiring board and an oxide semiconductor layer provided on the substrate,
  • the oxide semiconductor layer is composed of an oxide containing an indium (In) element, a zinc (Zn) element and an additive element (X),
  • the additive element (X) is at least one element selected from tantalum (Ta) element, strontium (Sr) element and niobium (Nb) element,
  • a field effect transistor in which the atomic ratio of each element satisfies all of the formulas (1) to (3) (X in the formula is the sum of the content ratios of the additive elements).
  • the base material is polyethylene naphthalate (PEN), polyethylene terephthalate (PET), polyphenylene sulfide (PPS), polyetheretherketone (PEEK), polystyrene (PS), polyethersulfone (PES), polycarbonate ( PC), triacetyl cellulose (TAC), cycloolefin polymer (COP), the field effect transistor according to any one of [1] to [8].
  • the additive element (X) is a tantalum (Ta) element, a strontium (Sr) element and At least one element selected from niobium (Nb) elements
  • a base material used for a flexible wiring board or a glass transition point of 250 ° C. or less in an atmosphere having an oxygen concentration of 21 vol% or more and 49 vol% or less Sputtering is performed on a base material having, to form an oxide semiconductor derived from the target material, A method of manufacturing a field effect transistor, comprising a step of annealing the oxide semiconductor at 50° C. or higher and 250° C. or lower.
  • the additive element (X) is a tantalum (Ta) element or a niobium (Nb) element.
  • the additive element (X) is at least one element selected from tantalum (Ta) element, strontium (Sr) element and niobium (Nb) element, A sputtering target material in which the atomic ratio of each element satisfies all of formulas (1) to (3), A sputtering target material for producing a field effect transistor, comprising: a base material used for a flexible wiring board or a base material having a glass transition point of 250° C.
  • the crystal grain size of the In 2 O 3 phase is 0.1 ⁇ m or more and 3.0 ⁇ m or less;
  • Example 1 In 2 O 3 powder, ZnO powder, and Ta 2 O 5 powder were prepared using target materials in which the atomic ratios of In, Zn, and Ta were as shown in Table 1 below.
  • FET 1 shown in FIG. 1 was fabricated by photolithography. In fabricating the FET 1, a polyethylene naphthalate film (Teonex (registered trademark) manufactured by Toyobo Co., Ltd.) (glass transition point: 155° C.) was used as the base material 10 .
  • Mo thin films were formed on the base material 10 as the source electrode 30 and the drain electrode 31 using a DC sputtering apparatus, and using the target material obtained by the above method, sputtering film formation was performed under the following conditions.
  • ⁇ Deposition device DC sputtering device SML-464 manufactured by Tokki Co., Ltd. ⁇ Ultimate vacuum: less than 1 ⁇ 10 ⁇ 4 Pa ⁇ Sputtering gas: Ar/O 2 mixed gas ⁇ Sputtering gas pressure: 0.4 Pa - O2 gas concentration: as shown in Table 1 below. ⁇ Substrate temperature: room temperature ⁇ Sputtering power: 3 W/cm 2 Next, a SiOx thin film was formed as the gate insulating film 40 under the following conditions. ⁇ Deposition device: plasma CVD device PD-2202L manufactured by Samco Co., Ltd.
  • XPS is a measuring method capable of measuring the photoelectron energy generated by irradiating the sample surface with X-rays and analyzing the constituent elements of the sample and their electronic states. Therefore, the composition of each element shown in Table 1 is the same between the channel layer 20 and the target material.
  • Example 2 to 12 and Comparative Examples 1 to 15 In Example 1, raw material powders were mixed so that the atomic ratios of In, Zn, and Ta or In, Zn, and Nb were the values shown in Tables 1 and 2 below to produce target materials. Sputtering was performed under the conditions shown in Tables 1 and 2 below. FET 1 was obtained in the same manner as in Example 1 except for these.
  • SEM images were obtained by randomly photographing 10 fields of BSE-COMP images in a range of 87.5 ⁇ m ⁇ 125 ⁇ m at a magnification of 1000 times.
  • the obtained SEM image was analyzed by image processing software: ImageJ 1.51k (http://imageJ.nih.gov/ij/, provider: National Institutes of Health (NIH)).
  • image processing software ImageJ 1.51k (http://imageJ.nih.gov/ij/, provider: National Institutes of Health (NIH)).
  • the specific procedure is as follows.
  • the sample used for taking the SEM image was subjected to thermal etching at 1100° C. for 1 hour and observed by SEM to obtain an image showing the grain boundaries shown in FIG.
  • the obtained image was drawn along the grain boundaries of the In 2 O 3 phase (area A that looks white in FIG. 2).
  • the ratio of the area of the In 2 O 3 phase to the total area was calculated by performing grain analysis on the BSE-COMP image without grain boundaries before thermal etching.
  • the arithmetic mean value of all particles calculated in 10 fields of view was taken as the In 2 O 3 phase area ratio.
  • the Zn 3 In 2 O 6 phase area ratio was calculated.
  • the field-effect mobility is the channel mobility obtained from the change in the drain current with respect to the gate voltage when the drain voltage is constant in the saturation region of the MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) operation.
  • MOSFET Metal-Oxide-Semiconductor Field-Effect Transistor
  • the SS value is the gate voltage required to increase the drain current by one order of magnitude near the threshold voltage, and the smaller the value, the better the transfer characteristics.
  • the threshold voltage is the voltage when a positive voltage is applied to the drain electrode and either positive or negative voltage is applied to the gate electrode, and the drain current flows to 1 nA.
  • the value is preferably close to 0V. .
  • it is more preferably ⁇ 2 V or higher, even more preferably ⁇ 1 V or higher, and even more preferably 0 V or higher. Further, it is more preferably 3 V or less, even more preferably 2 V or less, and even more preferably 1 V or less. Specifically, it is more preferably -2 V or more and 3 V or less, more preferably -1 V or more and 2 V or less, and even more preferably 0 V or more and 1 V or less.
  • FET 1 obtained in each example exhibits excellent transfer characteristics on a substrate used for a flexible wiring board or a substrate having a glass transition point of 250°C or lower. I know it shows.
  • the field effect mobility ⁇ , the threshold voltage Vth, and the SS value were all poor, and good transfer characteristics could not be obtained.
  • the term "defective" means that the channel layer became conductive or insulating, resulting in poor transfer characteristics and failure to function as a field effect transistor.
  • the present inventor confirmed by EDX measurement that the additive element (X) was contained in both the In 2 O 3 phase and the Zn 3 In 2 O 6 phase in the target material of the example. has confirmed.
  • the field effect transistor which has high field effect mobility, although it is formed on the base material with low heat resistance, and its manufacturing method are provided.
  • a sputtering target material suitable for manufacturing such a field effect transistor is provided.
  • sputtering is performed using the target material according to the present invention, it is possible to have a high field effect mobility even if post-annealing is performed at a low temperature after sputtering compared to the case of using a conventional target material. Therefore, it is possible to suppress the generation of defective products that do not exhibit sufficient field-effect mobility, and furthermore, it is possible to reduce the generation of waste. That is, it becomes possible to reduce the energy cost in disposing of those wastes.
  • the low-temperature post-annealing process itself can reduce energy costs during manufacturing. This will lead to sustainable management and efficient use of natural resources, as well as achieving decarbonization (carbon neutrality).

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Abstract

La présente invention concerne un transistor à effet de champ qui comprend un matériau de base qui a une température de transition vitreuse de 250 °C ou moins et une couche semi-conductrice d'oxyde qui est prévue sur le matériau de base. La couche semi-conductrice d'oxyde est conçue à partir d'un oxyde qui contient de l'indium élémentaire (In), du zinc élémentaire (Zn) et un élément additif (X). L'élément additif (X) est composé d'au moins un élément qui est choisi parmi le tantale élémentaire (Ta), le strontium élémentaire (Sr) et le niobium élémentaire (Nb). Les rapports atomiques entre éléments satisfont l'ensemble des formules (1) à (3). (1) : 0,4 ≤ (In + X)/(In + Zn + X) ≤ 0,8, (2) : 0,2 ≤ Zn/(In + Zn + X) ≤ 0,6, (3) : 0,001 ≤ X/(In + Zn + X) ≤ 0,015
PCT/JP2023/000903 2022-01-31 2023-01-16 Transistor à effet de champ, son procédé de production et cible de pulvérisation pour la production d'un transistor à effet de champ WO2023145497A1 (fr)

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KR1020247011009A KR20240087785A (ko) 2022-01-31 2023-01-16 전계 효과 트랜지스터 및 그 제조 방법 그리고 전계 효과 트랜지스터 제조용 스퍼터링 타깃재
CN202380013886.0A CN118056282A (zh) 2022-01-31 2023-01-16 场效应晶体管及其制造方法以及场效应晶体管制造用溅射靶材

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WO2012091126A1 (fr) * 2010-12-28 2012-07-05 株式会社神戸製鋼所 Oxyde pour couche de semi-conducteur de transistor à film mince, cible de pulvérisation et transistor à film mince
WO2014061272A1 (fr) * 2012-10-19 2014-04-24 出光興産株式会社 Cible de pulvérisation cathodique
WO2022030455A1 (fr) * 2020-08-05 2022-02-10 三井金属鉱業株式会社 Matériau cible de pulvérisation cathodique et semi-conducteur oxyde

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JP5679417B2 (ja) 2010-08-25 2015-03-04 富士フイルム株式会社 酸化物半導体薄膜の製造方法および該製造方法により作製された酸化物半導体薄膜、薄膜トランジスタ、並びに薄膜トランジスタを備えた装置
JP6809527B2 (ja) * 2016-03-18 2021-01-06 株式会社リコー 電界効果型トランジスタ、表示素子、画像表示装置、及びシステム

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Publication number Priority date Publication date Assignee Title
WO2012091126A1 (fr) * 2010-12-28 2012-07-05 株式会社神戸製鋼所 Oxyde pour couche de semi-conducteur de transistor à film mince, cible de pulvérisation et transistor à film mince
WO2014061272A1 (fr) * 2012-10-19 2014-04-24 出光興産株式会社 Cible de pulvérisation cathodique
WO2022030455A1 (fr) * 2020-08-05 2022-02-10 三井金属鉱業株式会社 Matériau cible de pulvérisation cathodique et semi-conducteur oxyde

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