WO2023145497A1 - Field effect transistor, method for producing same, and sputtering target for production of field effect transistor - Google Patents

Field effect transistor, method for producing same, and sputtering target for production of field effect transistor Download PDF

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Publication number
WO2023145497A1
WO2023145497A1 PCT/JP2023/000903 JP2023000903W WO2023145497A1 WO 2023145497 A1 WO2023145497 A1 WO 2023145497A1 JP 2023000903 W JP2023000903 W JP 2023000903W WO 2023145497 A1 WO2023145497 A1 WO 2023145497A1
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Prior art keywords
field effect
effect transistor
target material
additive
oxide semiconductor
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PCT/JP2023/000903
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French (fr)
Japanese (ja)
Inventor
成紀 徳地
享祐 寺村
亮 白仁田
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三井金属鉱業株式会社
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Application filed by 三井金属鉱業株式会社 filed Critical 三井金属鉱業株式会社
Priority to JP2023521467A priority Critical patent/JP7364824B1/en
Priority to CN202380013886.0A priority patent/CN118056282A/en
Publication of WO2023145497A1 publication Critical patent/WO2023145497A1/en

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    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
    • C23C14/06—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the coating material
    • C23C14/08—Oxides
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
    • C23C14/22—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the process of coating
    • C23C14/34—Sputtering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
    • H01L21/2003—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy characterised by the substrate
    • H01L21/2015—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy characterised by the substrate the substrate being of crystalline semiconductor material, e.g. lattice adaptation, heteroepitaxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film

Definitions

  • the present invention relates to a field effect transistor and its manufacturing method.
  • the present invention also relates to a sputtering target material for manufacturing field effect transistors.
  • TFTs thin film transistors
  • FPDs flat panel displays
  • IGZO Oxide semiconductors typified by -Zn composite oxides (hereinafter also referred to as “IGZO”) have attracted attention and are being put to practical use.
  • IGZO has the advantage of exhibiting high field effect mobility and low leakage current.
  • FPDs have become more sophisticated, materials have been proposed that exhibit field effect mobility higher than that of IGZO.
  • a flexible display which is one of the FPDs, has been attracting attention in recent years as it is possible to develop a wide range of applications due to its thin, light, and flexible functions.
  • a flexible organic EL display (OLED) using an organic EL as a display element does not require a backlight, and therefore is theoretically suitable for a flexible display.
  • a flexible base material is one of the important components that make up a flexible display.
  • Plastic films such as polyethylene terephthalate and polyethylene naphthalate are suitable as substrates for flexible displays because they are thin, lightweight, and have excellent flexibility.
  • plastic films have a problem with heat resistance.
  • post-annealing is required after film formation to improve electrical properties. should be done at low temperature.
  • post-annealing a film made of IGZO at a low temperature lowers the resistance of the film, making it difficult for the film to function as a semiconductor. Therefore, Patent Literature 1 proposes a technique for preventing the occurrence of low resistance caused by post-annealing at a low temperature in the production of an IGZO-based oxide semiconductor thin film.
  • the present invention provides a field effect transistor comprising a base material having a glass transition point of 250° C. or less or a base material used in a flexible wiring board, and an oxide semiconductor layer provided on the base material,
  • the oxide semiconductor layer is composed of an oxide containing an indium (In) element, a zinc (Zn) element and an additive element (X),
  • the additive element (X) is at least one element selected from tantalum (Ta) element, strontium (Sr) element and niobium (Nb) element
  • the present invention provides a field effect transistor in which the atomic ratio of each element satisfies all of the formulas (1) to (3) (X in the formula is the sum of the content ratios of the additive elements). 0.4 ⁇ (In+X)/(In+Zn+X) ⁇ 0.8 (1) 0.2 ⁇ Zn/(In+Zn+X) ⁇ 0.6 (2) 0.001 ⁇ X/(In+Zn+X) ⁇ 0.015 (3)
  • the present invention uses a sputtering target material made of an oxide containing an indium (In) element, a zinc (Zn) element, and an additive element (X) (the additive element (X) is a tantalum (Ta) element, a strontium (Sr) and a niobium (Nb) element.), in an atmosphere having an oxygen concentration of 21 vol% or more and 49 vol% or less, a base material used for a flexible wiring board or a glass transition temperature of 250°C or less. Sputtering a base material having points to form an oxide semiconductor derived from the target material, The present invention provides a method for manufacturing a field effect transistor, including a step of annealing the oxide semiconductor at 50° C. or higher and 250° C. or lower.
  • the present invention is composed of an oxide containing an indium (In) element, a zinc (Zn) element and an additive element (X),
  • the additive element (X) is at least one element selected from tantalum (Ta) element, strontium (Sr) element and niobium (Nb) element,
  • a sputtering target material for producing a field effect transistor comprising a base material used for a flexible wiring board or a base material having a glass transition point of 250° C. or lower and an oxide semiconductor layer derived from the sputtering target material. It provides. 0.4 ⁇ (In+X)/(In+Zn+X) ⁇ 0.8 (1) 0.2 ⁇ Zn/(In+Zn+X) ⁇ 0.6 (2) 0.001 ⁇ X/(In+Zn+X) ⁇ 0.015 (3)
  • FIG. 1 is a schematic diagram showing the structure of the field effect transistor of the present invention.
  • 2 is a scanning electron microscope image of the target material obtained in Example 1.
  • FIG. 1 is a schematic diagram showing the structure of the field effect transistor of the present invention.
  • the present invention relates to a field effect transistor (hereinafter also referred to as "FET").
  • An FET of the present invention includes a substrate and an oxide semiconductor layer provided on the substrate.
  • the FET of the present invention preferably includes a step of forming an oxide semiconductor layer on a base material by a sputtering method, and a step of post-annealing after forming the oxide semiconductor layer to improve electrical characteristics. and manufactured by a method comprising:
  • the conventional oxide semiconductor layer must be treated at a high temperature, and the base material with low heat resistance deforms or melts. can't get it to work.
  • a material that does not have sufficiently high heat resistance such as a material used for a flexible wiring board, or a material with a low glass transition point (for example, a material with a glass transition point of 250° C. or less), can be used as the base material.
  • a material with a low glass transition point for example, a material with a glass transition point of 250° C. or less
  • the film can be annealed at a relatively low temperature, so that the oxide semiconductor layer can be formed.
  • FIG. 1 schematically shows one embodiment of the FET of the present invention.
  • the FET having the structure shown in the drawing is an example of the embodiment of the present invention, and needless to say, the FET of the present invention is not limited to the structure shown in the drawing.
  • the FET 1 shown in the figure is formed on one surface of the substrate 10 .
  • a channel layer 20, a source electrode 30 and a drain electrode 31 are arranged on one surface of the substrate 10, and a gate insulating film 40 is formed so as to cover them.
  • a gate electrode 50 is arranged on the gate insulating film 40 .
  • a protective layer 60 is arranged on the uppermost portion.
  • the channel layer 20 is composed of an oxide semiconductor layer.
  • the "oxide semiconductor layer provided on the base material” as used in the present invention means (i) an oxide semiconductor layer via one or more layers provided in contact with the surface of the base material. and (ii) the oxide semiconductor layer is provided in contact with the surface of the substrate.
  • the oxide semiconductor layer in the FET of the present invention contains indium (In) element, zinc ( Zn) element and an additive element (X).
  • the additive element (X) consists of at least one element selected from tantalum (Ta) element, strontium (Sr) element and niobium (Nb) element.
  • the oxide semiconductor layer of the present invention contains In, Zn, and an additive element (X) as metal elements constituting the layer. Or, inevitably, trace elements may be included. Trace elements include, for example, elements contained in organic additives described later and media raw materials such as ball mills that are mixed during the production of the target material.
  • Examples of trace elements contained in the oxide semiconductor layer of the present invention include Fe, Cr, Ni, Al, Si, W, Zr, Na, Mg, K, Ca, Ti, Y, Ga, Sn, Ba, La, Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, Lu, Pb and the like.
  • Their content is usually 100 ppm by mass (hereinafter also referred to as “ppm”) or less with respect to the total mass of oxides containing In, Zn and X contained in the oxide semiconductor layer of the present invention. is preferred, more preferably 80 ppm or less, and still more preferably 50 ppm or less.
  • the total amount of these trace elements is preferably 500 ppm or less, more preferably 300 ppm or less, still more preferably 100 ppm or less.
  • the oxide semiconductor layer of the present invention contains a trace element, the total mass also includes the mass of the trace element.
  • the atomic ratio of the metal elements constituting it is within a specific range from the viewpoint of improving the performance of the FET of the present invention.
  • the atomic ratio represented by the following formula (1) is satisfied (X in the formula is the sum of the content ratios of the additive elements.
  • Zn preferably satisfies the atomic ratio represented by the following formula (2).
  • X preferably satisfies the atomic ratio represented by the following formula (3). 0.001 ⁇ X/(In+Zn+X) ⁇ 0.015 (3)
  • the FET of the present invention has high field effect mobility, low leakage current, and is close to 0V. It indicates the threshold voltage. From the viewpoint of making these advantages even more remarkable, it is more preferable that In and X satisfy the following formulas (1-2) to (1-6).
  • the additive element (X) one or more selected from Ta, Sr and Nb are used as described above. Each of these elements can be used alone, or two or more of them can be used in combination.
  • the use of Ta as the additive element (X) is advantageous from the viewpoint of the overall performance of the FET of the present invention and the economics of manufacturing the sputtering target material used when manufacturing the oxide semiconductor layer by sputtering. It is preferable from the point of view of sex.
  • Preferably only Ta is used. However, three types of Ta, Sr and Nb may be used.
  • the FET of the present invention satisfies the following equation (4) with respect to the atomic ratio of In to X. It is preferable from the point of further increasing the field effect mobility of the physical semiconductor device and from the point of exhibiting a threshold voltage close to 0V. 0.970 ⁇ In/(In+X) ⁇ 0.999 (4)
  • the atomic ratio of In to X is determined by the following formulas (4-2) to (4-4). More preferably. 0.980 ⁇ In/(In+X) ⁇ 0.997 (4-2) 0.990 ⁇ In/(In+X) ⁇ 0.995 (4-3) 0.990 ⁇ In/(In+X) ⁇ 0.993 (4-4)
  • the oxide semiconductor layer in the FET of the present invention contains In, Zn, the additive element X, and oxygen, and may contain other elements in addition, from the viewpoint of further increasing the field effect mobility of the FET.
  • the oxide semiconductor layer preferably contains In, Zn, an additive element X, and oxygen, and the remainder is composed of unavoidable impurities.
  • the ratio of each metal contained in the oxide semiconductor layer of the present invention is measured by, for example, X-ray photoelectron spectroscopy (XPS) or ICP emission spectrometry.
  • XPS X-ray photoelectron spectroscopy
  • ICP emission spectrometry ICP emission spectrometry
  • the field effect mobility (cm 2 /Vs) of the TFT of the present invention is preferably 20 cm 2 /Vs or more, more preferably 30 cm 2 /Vs or more, and 50 cm 2 /Vs or more. more preferably 60 cm 2 /Vs or more, even more preferably 70 cm 2 /Vs or more, even more preferably 80 cm 2 /Vs or more, 100 cm 2 /Vs or more is particularly preferred.
  • a higher value of the field effect mobility is preferable from the standpoint of improving the functionality of the FPD.
  • the oxide semiconductor layer in the FET of the present invention preferably has an amorphous structure.
  • the substrate in the FET of the present invention is composed of a material used for flexible wiring boards or composed of a material having a glass transition point of 250° C. or lower.
  • the use of substrates composed of these materials is advantageous in that flexible displays, for example, can be easily manufactured using the FETs of the present invention.
  • a material constituting the base material a resin base material is preferable. Or two or more types are mentioned.
  • these resin substrates are made of a material having a glass transition point of 250° C. or less. These materials are for example in the form of films.
  • materials constituting the base material include polyethylene naphthalate (PEN), polyethylene terephthalate (PET), polyphenylene sulfide (PPS), polyetheretherketone (PEEK), polystyrene (PS), polyethersulfone ( PES), polycarbonate (PC), triacetyl cellulose (TAC), polybutylene terephthalate (PBT), polysilane, polysiloxane, polysilazane, polycarbosilane, polyacrylate , polymethacrylate, polymethylacrylate, polyethylacrylate, polyethylmethacrylate, cycloolefin copolymer (COC), cycloolefin polymer (COP), polyethylene (PE), polypropylene (PP ), polymethyl methacrylate (PMMA), polyacetal (POM), polytetrafluoroethylene (PTFE), polyvinyl chloride (PVC), polyvinylidene fluoride (PV
  • the material used for the flexible wiring board in other words, the heat resistance is sufficiently high.
  • An oxide semiconductor layer with high field-effect mobility can be successfully formed even with a base material made of a material that does not have a high field-effect mobility. From this point of view, it is possible to use a material having a glass transition point of preferably 250° C. or lower, more preferably 200° C. or lower, and even more preferably 180° C. or lower as the base material.
  • the glass transition point of the material constituting the substrate is preferably 0° C. or higher, more preferably 25° C. or higher, and 80° C. or higher. is more preferably 85° C. or higher, and even more preferably 90° C. or higher.
  • the method for measuring the glass transition point of the substrate is as described below.
  • the glass transition point is determined by the DTA method in accordance with JIS-K-7121-1987 (method for measuring transition temperature of plastics).
  • STA 2500 Regulus manufactured by NETZSCH is typically used to measure the midpoint glass transition temperature.
  • the base material of the FET of the present invention preferably has a thickness of 1 ⁇ m or more and 500 ⁇ m or less, more preferably 1 ⁇ m or more and 300 ⁇ m or less, and even more preferably 1 ⁇ m or more and 100 ⁇ m or less. .
  • the base material in the FET of the present invention preferably has a thermal expansion coefficient of 5 ppm/° C. or more and 80 ppm/° C. or less, more preferably 5 ppm/° C. or more and 50 ppm/° C. or less. ° C. or more and 20 ppm/° C. or less is more preferable.
  • a semiconductor device including the FET of the present invention is also provided.
  • semiconductor device refers to all devices that can function by utilizing semiconductor characteristics.
  • electro-optical devices, semiconductor circuits, and electronic devices are all semiconductor devices.
  • the semiconductor device of the present invention is useful as a thin film transistor used for FPD.
  • the FET of the present invention can be manufactured using a known photolithography method. Particularly when manufacturing the oxide semiconductor layer of the present invention, a sputtering target material described later is used and sputtering is performed under the following conditions. be able to.
  • a sputtering target material described later is used and sputtering is performed under the following conditions. be able to.
  • the sputtering method for example, a DC sputtering method can be used.
  • the temperature of the substrate during sputtering can be set to, for example, 10° C. or higher and 250° C. or lower.
  • Sputtering may also be performed at a substrate temperature that does not exceed the glass transition point of the substrate.
  • the ultimate vacuum degree during sputtering can be set to less than 0.001 Pa, for example.
  • the sputtering gas for example, a mixed gas of Ar and O 2 can be used.
  • the O 2 gas concentration in the sputtering gas can be set to 21 vol% or more and 49 vol% or less, particularly 22 vol% or more and 45 vol% or less.
  • the sputtering gas pressure can be set to, for example, 0.1 Pa or more and 3 Pa or less.
  • Sputtering power can be set to, for example, 0.1 W/cm 2 or more and 10 W/cm 2 or less.
  • an oxide semiconductor layer can be successfully manufactured on even a substrate composed of a material that does not have sufficiently high heat resistance.
  • the oxide semiconductor layer is preferably annealed.
  • the purpose of the annealing treatment is to impart desired performance to the oxide semiconductor layer.
  • the temperature of the annealing treatment is preferably 50° C. or higher and 250° C. or lower, more preferably 80° C. or higher and 200° C. or lower, even more preferably 100° C. or higher and 180° C. or lower. °C or higher and 150 °C or lower is even more preferable.
  • the annealing time is preferably 1 minute or more and 180 minutes or less, more preferably 2 minutes or more and 120 minutes or less, and even more preferably 3 minutes or more and 60 minutes or less.
  • the annealing atmosphere is preferably an oxygen atmosphere including atmospheric pressure.
  • Annealing treatment for the oxide semiconductor layer can be performed immediately after the oxide semiconductor layer is formed. Alternatively, one or more layers may be formed after the oxide semiconductor layer is formed, and then annealing treatment may be performed.
  • a sputtering target material is at least one element selected from tantalum (Ta) element, strontium (Sr) element and niobium (Nb) element). That is, this sputtering target material is provided on a base material used for a flexible wiring board or a base material having a glass transition point of 250° C.
  • the sputtering target material for manufacturing FETs is also referred to as "the target material of the present invention" for convenience.
  • a sputtering target material for FET manufacturing in which the atomic ratio of each element satisfies all of the following formulas (1) to (3) (X in the formula is the sum of the content ratios of the additive elements.) should be used. 0.4 ⁇ (In+X)/(In+Zn+X) ⁇ 0.8 (1) 0.2 ⁇ Zn/(In+Zn+X) ⁇ 0.6 (2) 0.001 ⁇ X/(In+Zn+X) ⁇ 0.015 (3)
  • the atomic ratio of each element constituting the target material preferably further satisfies the formula (4). 0.970 ⁇ In/(In+X) ⁇ 0.999 (4)
  • the target material of the present invention is composed of oxides containing In, Zn and X as described above.
  • This oxide can be an In oxide, a Zn oxide or an X oxide.
  • this oxide may be a composite oxide of any two or more elements selected from the group consisting of In, Zn and X.
  • Specific examples of composite oxides include In—Zn composite oxide, Zn—Ta composite oxide, In—Ta composite oxide, In—Nb composite oxide, Zn—Nb composite oxide, In—Sr composite oxide Examples include oxides, Zn--Sr composite oxides, In--Zn--Ta composite oxides, In--Zn--Nb composite oxides, and In--Zn--Sr composite oxides, but are not limited to these.
  • the target material of the present invention particularly includes an In 2 O 3 phase, which is an In oxide, and a Zn 3 In 2 O 6 phase, which is a composite oxide of In and Zn. It is preferable from the viewpoint of increasing resistance and reducing resistance.
  • the fact that the target material of the present invention contains the In 2 O 3 phase and the Zn 3 In 2 O 6 phase can be confirmed by X-ray diffraction (hereinafter also referred to as “ XRD ”) measurement of the target material of the present invention. It can be determined by whether three phases and a Zn3In2O6 phase are observed .
  • the In 2 O 3 phase in the present invention may contain a trace amount of Zn element.
  • both the In2O3 phase and the Zn3In2O6 phase preferably contain the additive element (X).
  • the additive element (X) when the additive element (X) is homogeneously dispersed throughout the target material, the additive element (X) is uniformly contained in the oxide semiconductor formed from the target material of the present invention. A fine oxide semiconductor film can be obtained.
  • the inclusion of the additional element (X) in both the In 2 O 3 phase and the Zn 3 In 2 O 6 phase can be measured by, for example, energy dispersive X-ray spectroscopy (hereinafter also referred to as “EDX”). can.
  • EDX energy dispersive X-ray spectroscopy
  • the fact that the In 2 O 3 phase has a crystal grain size that satisfies a specific range indicates the density and strength of the target material of the present invention. It is preferable from the viewpoint of increasing the resistance and reducing the resistance.
  • the crystal grain size of the In 2 O 3 phase is preferably 3.0 ⁇ m or less, more preferably 2.7 ⁇ m or less, and even more preferably 2.5 ⁇ m or less. The smaller the crystal grain size, the better, and although the lower limit is not particularly defined, it is usually 0.1 ⁇ m or more.
  • the crystal grain size of the Zn 3 In 2 O 6 phase also satisfies a specific range. It is preferable from the viewpoint of increasing the density and strength of the material and reducing the resistance.
  • the crystal grain size of the Zn 3 In 2 O 6 phase is preferably 3.9 ⁇ m or less, more preferably 3.5 ⁇ m or less, even more preferably 3.0 ⁇ m or less, It is more preferably 2.5 ⁇ m or less, even more preferably 2.3 ⁇ m or less, particularly preferably 2.0 ⁇ m or less, and most preferably 1.9 ⁇ m or less.
  • a target material may be manufactured by the method described later.
  • the crystal grain size of the In 2 O 3 phase and the crystal grain size of the Zn 3 In 2 O 6 phase are measured by observing the target material of the present invention with a scanning electron microscope (hereinafter also referred to as “SEM”). be done. A specific measuring method will be described in detail in Examples described later.
  • the target material of the present invention contains In, Zn, the additive element X and oxygen, and may contain other elements in addition. From the viewpoint of increasing the cost, it is preferable that the target material contains In, Zn, the additive element X, and oxygen, and the remainder consists of unavoidable impurities.
  • an oxide powder which is a raw material of a target material
  • the compact is fired to obtain a target material composed of a sintered compact.
  • methods hitherto known in the art such as slip casting, can be employed.
  • a slurry similar to that used in the casting method is spray-dried to obtain a dry powder.
  • the resulting dry powder is filled into a mold and subjected to CIP molding.
  • the firing temperature is preferably 1200° C. or higher and 1600° C. or lower, more preferably 1300° C. or higher and 1500° C. or lower, and still more preferably 1350° C. or higher and 1450° C. or lower.
  • the firing time is preferably from 1 hour to 100 hours, more preferably from 2 hours to 50 hours, and even more preferably from 3 hours to 30 hours.
  • the heating rate is preferably 5°C/hour or more and 500°C/hour or less, more preferably 10°C/hour or more and 200°C/hour or less, and 20°C/hour or more and 100°C/hour or less. is more preferred.
  • a phase of In and Zn composite oxides such as Zn 5 In 2 O 8
  • Zn 5 In 2 O 8 a phase of In and Zn composite oxides, such as Zn 5 In 2 O 8
  • the raw material powder contains In 2 O 3 powder and ZnO powder
  • Zn 5 In 2 O 8 phase is generated, volume diffusion proceeds and densification is promoted, so it is preferable to reliably generate the Zn 5 In 2 O 8 phase.
  • the temperature to be maintained is not necessarily limited to one specific temperature, but may be a temperature range with a certain width.
  • a specific temperature selected from the range of 1000 ° C. or higher and 1250 ° C. or lower is T (° C.)
  • T ⁇ 10 ° C. preferably T ⁇ 5°C, more preferably T ⁇ 3°C, still more preferably T ⁇ 1°C.
  • the time for maintaining this temperature range is preferably 1 hour or more and 40 hours or less, more preferably 2 hours or more and 20 hours or less.
  • the target material obtained in this way can be processed to a predetermined size by grinding or the like.
  • a sputtering target is obtained by joining this to a base material.
  • shape of the target material there is no particular limitation on the shape of the target material, and conventionally known shapes such as a flat plate shape and a cylindrical shape can be adopted.
  • the present invention further discloses the following field effect transistors, methods for manufacturing the same, and sputtering target materials for manufacturing field effect transistors.
  • a field effect transistor comprising a substrate having a glass transition point of 250° C.
  • the oxide semiconductor layer is composed of an oxide containing an indium (In) element, a zinc (Zn) element and an additive element (X),
  • the additive element (X) is at least one element selected from tantalum (Ta) element, strontium (Sr) element and niobium (Nb) element,
  • a field effect transistor in which the atomic ratio of each element satisfies all of the formulas (1) to (3) (X in the formula is the sum of the content ratios of the additive elements).
  • a field effect transistor comprising a substrate used in a flexible wiring board and an oxide semiconductor layer provided on the substrate,
  • the oxide semiconductor layer is composed of an oxide containing an indium (In) element, a zinc (Zn) element and an additive element (X),
  • the additive element (X) is at least one element selected from tantalum (Ta) element, strontium (Sr) element and niobium (Nb) element,
  • a field effect transistor in which the atomic ratio of each element satisfies all of the formulas (1) to (3) (X in the formula is the sum of the content ratios of the additive elements).
  • the base material is polyethylene naphthalate (PEN), polyethylene terephthalate (PET), polyphenylene sulfide (PPS), polyetheretherketone (PEEK), polystyrene (PS), polyethersulfone (PES), polycarbonate ( PC), triacetyl cellulose (TAC), cycloolefin polymer (COP), the field effect transistor according to any one of [1] to [8].
  • the additive element (X) is a tantalum (Ta) element, a strontium (Sr) element and At least one element selected from niobium (Nb) elements
  • a base material used for a flexible wiring board or a glass transition point of 250 ° C. or less in an atmosphere having an oxygen concentration of 21 vol% or more and 49 vol% or less Sputtering is performed on a base material having, to form an oxide semiconductor derived from the target material, A method of manufacturing a field effect transistor, comprising a step of annealing the oxide semiconductor at 50° C. or higher and 250° C. or lower.
  • the additive element (X) is a tantalum (Ta) element or a niobium (Nb) element.
  • the additive element (X) is at least one element selected from tantalum (Ta) element, strontium (Sr) element and niobium (Nb) element, A sputtering target material in which the atomic ratio of each element satisfies all of formulas (1) to (3), A sputtering target material for producing a field effect transistor, comprising: a base material used for a flexible wiring board or a base material having a glass transition point of 250° C.
  • the crystal grain size of the In 2 O 3 phase is 0.1 ⁇ m or more and 3.0 ⁇ m or less;
  • Example 1 In 2 O 3 powder, ZnO powder, and Ta 2 O 5 powder were prepared using target materials in which the atomic ratios of In, Zn, and Ta were as shown in Table 1 below.
  • FET 1 shown in FIG. 1 was fabricated by photolithography. In fabricating the FET 1, a polyethylene naphthalate film (Teonex (registered trademark) manufactured by Toyobo Co., Ltd.) (glass transition point: 155° C.) was used as the base material 10 .
  • Mo thin films were formed on the base material 10 as the source electrode 30 and the drain electrode 31 using a DC sputtering apparatus, and using the target material obtained by the above method, sputtering film formation was performed under the following conditions.
  • ⁇ Deposition device DC sputtering device SML-464 manufactured by Tokki Co., Ltd. ⁇ Ultimate vacuum: less than 1 ⁇ 10 ⁇ 4 Pa ⁇ Sputtering gas: Ar/O 2 mixed gas ⁇ Sputtering gas pressure: 0.4 Pa - O2 gas concentration: as shown in Table 1 below. ⁇ Substrate temperature: room temperature ⁇ Sputtering power: 3 W/cm 2 Next, a SiOx thin film was formed as the gate insulating film 40 under the following conditions. ⁇ Deposition device: plasma CVD device PD-2202L manufactured by Samco Co., Ltd.
  • XPS is a measuring method capable of measuring the photoelectron energy generated by irradiating the sample surface with X-rays and analyzing the constituent elements of the sample and their electronic states. Therefore, the composition of each element shown in Table 1 is the same between the channel layer 20 and the target material.
  • Example 2 to 12 and Comparative Examples 1 to 15 In Example 1, raw material powders were mixed so that the atomic ratios of In, Zn, and Ta or In, Zn, and Nb were the values shown in Tables 1 and 2 below to produce target materials. Sputtering was performed under the conditions shown in Tables 1 and 2 below. FET 1 was obtained in the same manner as in Example 1 except for these.
  • SEM images were obtained by randomly photographing 10 fields of BSE-COMP images in a range of 87.5 ⁇ m ⁇ 125 ⁇ m at a magnification of 1000 times.
  • the obtained SEM image was analyzed by image processing software: ImageJ 1.51k (http://imageJ.nih.gov/ij/, provider: National Institutes of Health (NIH)).
  • image processing software ImageJ 1.51k (http://imageJ.nih.gov/ij/, provider: National Institutes of Health (NIH)).
  • the specific procedure is as follows.
  • the sample used for taking the SEM image was subjected to thermal etching at 1100° C. for 1 hour and observed by SEM to obtain an image showing the grain boundaries shown in FIG.
  • the obtained image was drawn along the grain boundaries of the In 2 O 3 phase (area A that looks white in FIG. 2).
  • the ratio of the area of the In 2 O 3 phase to the total area was calculated by performing grain analysis on the BSE-COMP image without grain boundaries before thermal etching.
  • the arithmetic mean value of all particles calculated in 10 fields of view was taken as the In 2 O 3 phase area ratio.
  • the Zn 3 In 2 O 6 phase area ratio was calculated.
  • the field-effect mobility is the channel mobility obtained from the change in the drain current with respect to the gate voltage when the drain voltage is constant in the saturation region of the MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) operation.
  • MOSFET Metal-Oxide-Semiconductor Field-Effect Transistor
  • the SS value is the gate voltage required to increase the drain current by one order of magnitude near the threshold voltage, and the smaller the value, the better the transfer characteristics.
  • the threshold voltage is the voltage when a positive voltage is applied to the drain electrode and either positive or negative voltage is applied to the gate electrode, and the drain current flows to 1 nA.
  • the value is preferably close to 0V. .
  • it is more preferably ⁇ 2 V or higher, even more preferably ⁇ 1 V or higher, and even more preferably 0 V or higher. Further, it is more preferably 3 V or less, even more preferably 2 V or less, and even more preferably 1 V or less. Specifically, it is more preferably -2 V or more and 3 V or less, more preferably -1 V or more and 2 V or less, and even more preferably 0 V or more and 1 V or less.
  • FET 1 obtained in each example exhibits excellent transfer characteristics on a substrate used for a flexible wiring board or a substrate having a glass transition point of 250°C or lower. I know it shows.
  • the field effect mobility ⁇ , the threshold voltage Vth, and the SS value were all poor, and good transfer characteristics could not be obtained.
  • the term "defective" means that the channel layer became conductive or insulating, resulting in poor transfer characteristics and failure to function as a field effect transistor.
  • the present inventor confirmed by EDX measurement that the additive element (X) was contained in both the In 2 O 3 phase and the Zn 3 In 2 O 6 phase in the target material of the example. has confirmed.
  • the field effect transistor which has high field effect mobility, although it is formed on the base material with low heat resistance, and its manufacturing method are provided.
  • a sputtering target material suitable for manufacturing such a field effect transistor is provided.
  • sputtering is performed using the target material according to the present invention, it is possible to have a high field effect mobility even if post-annealing is performed at a low temperature after sputtering compared to the case of using a conventional target material. Therefore, it is possible to suppress the generation of defective products that do not exhibit sufficient field-effect mobility, and furthermore, it is possible to reduce the generation of waste. That is, it becomes possible to reduce the energy cost in disposing of those wastes.
  • the low-temperature post-annealing process itself can reduce energy costs during manufacturing. This will lead to sustainable management and efficient use of natural resources, as well as achieving decarbonization (carbon neutrality).

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Abstract

The present invention provides a field effect transistor which comprises a base material that has a glass transition temperature of 250°C or less and an oxide semiconductor layer that is provided on the base material. The oxide semiconductor layer is configured from an oxide that contains elemental indium (In), elemental zinc (Zn) and an additive element (X). The additive element (X) is composed of at least one element that is selected from among elemental tantalum (Ta), elemental strontium (Sr) and elemental niobium (Nb). The atomic ratios of the elements satisfy all of formulae (1) to (3). (1): 0.4 ≤ (In + X)/(In + Zn + X) ≤ 0.8 (2): 0.2 ≤ Zn/(In + Zn + X) ≤ 0.6 (3): 0.001 ≤ X/(In + Zn + X) ≤ 0.015

Description

電界効果トランジスタ及びその製造方法並びに電界効果トランジスタ製造用スパッタリングターゲット材FIELD EFFECT TRANSISTOR, MANUFACTURING METHOD THEREOF, AND SPUTTERING TARGET MATERIAL FOR MANUFACTURING FIELD EFFECT TRANSISTOR
　本発明は電界効果トランジスタ及びその製造方法に関する。また本発明は、電界効果トランジスタ製造用スパッタリングターゲット材に関する。 The present invention relates to a field effect transistor and its manufacturing method. The present invention also relates to a sputtering target material for manufacturing field effect transistors.
　フラットパネルディスプレイ（以下「ＦＰＤ」ともいう。）に使用される薄膜トランジスタ（以下「ＴＦＴ」ともいう。）の技術分野においては、ＦＰＤの高機能化に伴い、従来のアモルファスシリコンに代わってＩｎ－Ｇａ－Ｚｎ複合酸化物（以下「ＩＧＺＯ」ともいう。）に代表される酸化物半導体が注目されており、実用化が進んでいる。ＩＧＺＯは、高い電界効果移動度と低いリーク電流を示すという利点を有する。近年ではＦＰＤの更なる高機能化が進むに従い、ＩＧＺＯが示す電界効果移動度よりも更に高い電界効果移動度を示す材料が提案されている。 In the technical field of thin film transistors (hereinafter also referred to as "TFTs") used in flat panel displays (hereinafter also referred to as "FPDs"), In--Ga is being used in place of conventional amorphous silicon as FPDs become more functional. Oxide semiconductors typified by -Zn composite oxides (hereinafter also referred to as “IGZO”) have attracted attention and are being put to practical use. IGZO has the advantage of exhibiting high field effect mobility and low leakage current. In recent years, as FPDs have become more sophisticated, materials have been proposed that exhibit field effect mobility higher than that of IGZO.
　ＦＰＤの一つであるフレキシブルディスプレイは、薄い、軽い、柔軟であるといった機能により幅広い応用展開が可能であるとして近年注目されている。特に表示素子に有機ＥＬを使用したフレキシブル有機ＥＬディスプレイ（ＯＬＥＤ）はバックライトを必要としないことから、原理的にフレキシブルディスプレイに適している。 A flexible display, which is one of the FPDs, has been attracting attention in recent years as it is possible to develop a wide range of applications due to its thin, light, and flexible functions. In particular, a flexible organic EL display (OLED) using an organic EL as a display element does not require a backlight, and therefore is theoretically suitable for a flexible display.
　フレキシブルディスプレイを構成する重要な部材の一つとして、柔軟性のある基材が挙げられる。フレキシブルディスプレイに使用される基材としては、ポリエチレンテレフタレート及びポリエチレンナフタレートなどのプラスチックフィルムが、薄く、軽量であり、しかも柔軟性に優れることから適している。しかしプラスチックフィルムは耐熱性に課題がある。基材上にＴＦＴを形成するためには、成膜後に、電気特性改善のためにポストアニール処理が求められるところ、プラスチックフィルムのような耐熱性の低い基材を用いた場合にはポストアニール処理を低温で行う必要がある。しかしＩＧＺＯからなる膜を、低温でポストアニール処理すると、当該膜が低抵抗化を起こし、半導体として機能させることが難しくなる。そこで特許文献１においては、ＩＧＺＯ系酸化物半導体薄膜の製造において、低温でのポストアニール処理に起因する低抵抗化が起こらないようにする技術が提案されている。 A flexible base material is one of the important components that make up a flexible display. Plastic films such as polyethylene terephthalate and polyethylene naphthalate are suitable as substrates for flexible displays because they are thin, lightweight, and have excellent flexibility. However, plastic films have a problem with heat resistance. In order to form a TFT on a substrate, post-annealing is required after film formation to improve electrical properties. should be done at low temperature. However, post-annealing a film made of IGZO at a low temperature lowers the resistance of the film, making it difficult for the film to function as a semiconductor. Therefore, Patent Literature 1 proposes a technique for preventing the occurrence of low resistance caused by post-annealing at a low temperature in the production of an IGZO-based oxide semiconductor thin film.
特開２０１２－０４９２０９号JP 2012-049209
　特許文献１に記載の技術によれば、低温でポストアニール処理を行ってもＩＧＺＯ系薄膜の低抵抗化は防止されるが、ポストアニール処理後の薄膜は、その電界効果移動度が低いことから、該薄膜を上述したＯＬＥＤを駆動させるための半導体として用いるには不十分である。
　したがって本発明の課題は、前述した従来技術が有する種々の欠点を解消し得る電界効果トランジスタ及びその製造方法を提供することにある。 According to the technique described in Patent Document 1, even if the post-annealing treatment is performed at a low temperature, the resistance of the IGZO-based thin film is prevented from being lowered. , the thin film is not sufficient to be used as a semiconductor for driving the OLED described above.
SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide a field effect transistor and a method of manufacturing the same that can overcome the various drawbacks of the prior art.
　本発明は、２５０℃以下のガラス転移点を有する基材又はフレキシブル配線板に用いられる基材と、該基材上に設けられた酸化物半導体層とを備えた、電界効果トランジスタであって、
　前記酸化物半導体層は、インジウム（Ｉｎ）元素、亜鉛（Ｚｎ）元素及び添加元素（Ｘ）を含む酸化物から構成され、
　添加元素（Ｘ）はタンタル（Ｔａ）元素、ストロンチウム（Ｓｒ）元素及びニオブ（Ｎｂ）元素から選ばれる少なくとも１種の元素であり、
　各元素の原子比が式（１）ないし（３）の全てを満たす電界効果トランジスタ（式中のＸは、前記添加元素の含有比の総和とする。）を提供するものである。
　　　０．４≦（Ｉｎ＋Ｘ）／（Ｉｎ＋Ｚｎ＋Ｘ）≦０．８　（１）
　　　０．２≦Ｚｎ／（Ｉｎ＋Ｚｎ＋Ｘ）≦０．６　　　　　（２）
　　　０．００１≦Ｘ／（Ｉｎ＋Ｚｎ＋Ｘ）≦０．０１５　　（３） The present invention provides a field effect transistor comprising a base material having a glass transition point of 250° C. or less or a base material used in a flexible wiring board, and an oxide semiconductor layer provided on the base material,
The oxide semiconductor layer is composed of an oxide containing an indium (In) element, a zinc (Zn) element and an additive element (X),
The additive element (X) is at least one element selected from tantalum (Ta) element, strontium (Sr) element and niobium (Nb) element,
The present invention provides a field effect transistor in which the atomic ratio of each element satisfies all of the formulas (1) to (3) (X in the formula is the sum of the content ratios of the additive elements).
0.4≦(In+X)/(In+Zn+X)≦0.8 (1)
0.2≦Zn/(In+Zn+X)≦0.6 (2)
0.001≦X/(In+Zn+X)≦0.015 (3)
　また本発明は、インジウム（Ｉｎ）元素、亜鉛（Ｚｎ）元素及び添加元素（Ｘ）を含む酸化物からなるスパッタリングターゲット材を用い（添加元素（Ｘ）はタンタル（Ｔａ）元素、ストロンチウム（Ｓｒ）元素及びニオブ（Ｎｂ）元素から選ばれる少なくとも１種の元素である。）、酸素濃度が２１ｖｏｌ％以上４９ｖｏｌ％以下である雰囲気下に、フレキシブル配線板に用いられる基材又は２５０℃以下のガラス転移点を有する基材に対してスパッタリングを行い、前記ターゲット材に由来する酸化物半導体を形成し、
　前記酸化物半導体を５０℃以上２５０℃以下でアニール処理する、工程を有する電界効果トランジスタの製造方法を提供するものである。 In addition, the present invention uses a sputtering target material made of an oxide containing an indium (In) element, a zinc (Zn) element, and an additive element (X) (the additive element (X) is a tantalum (Ta) element, a strontium (Sr) and a niobium (Nb) element.), in an atmosphere having an oxygen concentration of 21 vol% or more and 49 vol% or less, a base material used for a flexible wiring board or a glass transition temperature of 250°C or less. Sputtering a base material having points to form an oxide semiconductor derived from the target material,
The present invention provides a method for manufacturing a field effect transistor, including a step of annealing the oxide semiconductor at 50° C. or higher and 250° C. or lower.
　更に本発明は、インジウム（Ｉｎ）元素、亜鉛（Ｚｎ）元素及び添加元素（Ｘ）を含む酸化物から構成され、
　添加元素（Ｘ）はタンタル（Ｔａ）元素、ストロンチウム（Ｓｒ）元素及びニオブ（Ｎｂ）元素から選ばれる少なくとも１種の元素であり、
　各元素の原子比が式（１）ないし（３）の全てを満たすスパッタリングターゲット材であって、
　フレキシブル配線板に用いられる基材又は２５０℃以下のガラス転移点を有する基材上に設けられ且つ前記スパッタリングターゲット材に由来する酸化物半導体層、を備えた電界効果トランジスタの製造用スパッタリングターゲット材を提供するものである。
　　　０．４≦（Ｉｎ＋Ｘ）／（Ｉｎ＋Ｚｎ＋Ｘ）≦０．８　（１）
　　　０．２≦Ｚｎ／（Ｉｎ＋Ｚｎ＋Ｘ）≦０．６　　　　　（２）
　　　０．００１≦Ｘ／（Ｉｎ＋Ｚｎ＋Ｘ）≦０．０１５　　（３） Furthermore, the present invention is composed of an oxide containing an indium (In) element, a zinc (Zn) element and an additive element (X),
The additive element (X) is at least one element selected from tantalum (Ta) element, strontium (Sr) element and niobium (Nb) element,
A sputtering target material in which the atomic ratio of each element satisfies all of formulas (1) to (3),
A sputtering target material for producing a field effect transistor, comprising a base material used for a flexible wiring board or a base material having a glass transition point of 250° C. or lower and an oxide semiconductor layer derived from the sputtering target material. It provides.
0.4≦(In+X)/(In+Zn+X)≦0.8 (1)
0.2≦Zn/(In+Zn+X)≦0.6 (2)
0.001≦X/(In+Zn+X)≦0.015 (3)
図１は、本発明の電界効果トランジスタの構造を示す模式図である。FIG. 1 is a schematic diagram showing the structure of the field effect transistor of the present invention. 図２は、実施例１で得られたターゲット材の走査型電子顕微鏡像である。2 is a scanning electron microscope image of the target material obtained in Example 1. FIG.
　以下本発明を、その好ましい実施形態に基づき説明する。本発明は電界効果トランジスタ（以下「ＦＥＴ」ともいう。）に関するものである。本発明のＦＥＴは、基材と、該基材上に設けられた酸化物半導体層とを備えて構成されている。
　本発明のＦＥＴは、後述するとおり、好適には、スパッタリング法によって基材上に酸化物半導体層を形成する工程と、酸化物半導体層を形成した後に、電気特性改善のためにポストアニールする工程と、を備えた方法によって製造される。一般に、酸化物半導体層を形成後に、ポストアニールする場合、従来の酸化物半導体層は、高温で処理しなければならないため、耐熱性の低い基材が変形ないし溶融してしまうことから、素子として機能させることができない。しかし本発明によれば、耐熱性が十分に高くない材料、例えばフレキシブル配線板に用いられる材料や、ガラス転移点が低い材料（例えば２５０℃以下のガラス転移点を有する材料）を基材として用いた場合であっても、スパッタリングによって膜を形成した後、比較的低い温度によってアニールすることが可能となることから、酸化物半導体層を形成することが可能である。 The present invention will be described below based on its preferred embodiments. The present invention relates to a field effect transistor (hereinafter also referred to as "FET"). An FET of the present invention includes a substrate and an oxide semiconductor layer provided on the substrate.
As will be described later, the FET of the present invention preferably includes a step of forming an oxide semiconductor layer on a base material by a sputtering method, and a step of post-annealing after forming the oxide semiconductor layer to improve electrical characteristics. and manufactured by a method comprising: In general, when performing post-annealing after forming an oxide semiconductor layer, the conventional oxide semiconductor layer must be treated at a high temperature, and the base material with low heat resistance deforms or melts. can't get it to work. However, according to the present invention, a material that does not have sufficiently high heat resistance, such as a material used for a flexible wiring board, or a material with a low glass transition point (for example, a material with a glass transition point of 250° C. or less), can be used as the base material. Even in the case where the film is formed by sputtering, the film can be annealed at a relatively low temperature, so that the oxide semiconductor layer can be formed.
　図１には、本発明のＦＥＴの一実施形態が模式的に示されている。なお、同図に示す構造のＦＥＴは、本発明の実施形態の一例であり、本発明のＦＥＴが同図に示す構造のものに限定されないことは言うまでもない。
　同図に示すＦＥＴ１は、基材１０の一面に形成されている。基材１０の一面にはチャネル層２０、ソース電極３０及びドレイン電極３１が配置されており、これを覆うようにゲート絶縁膜４０が形成されている。ゲート絶縁膜４０上には、ゲート電極５０が配置されている。そして最も上部に保護層６０が配置されている。この構造を有するＦＥＴ１において、例えばチャネル層２０が、酸化物半導体層から構成されている。したがって、本発明にいう「基材上に設けられた酸化物半導体層」とは、（ｉ）基材の表面に接して設けられた別の一又は二以上の層を介して酸化物半導体層が設けられている場合と、（ｉｉ）酸化物半導体層が、基材の表面に接して設けられている場合との双方を包含する。 FIG. 1 schematically shows one embodiment of the FET of the present invention. The FET having the structure shown in the drawing is an example of the embodiment of the present invention, and needless to say, the FET of the present invention is not limited to the structure shown in the drawing.
The FET 1 shown in the figure is formed on one surface of the substrate 10 . A channel layer 20, a source electrode 30 and a drain electrode 31 are arranged on one surface of the substrate 10, and a gate insulating film 40 is formed so as to cover them. A gate electrode 50 is arranged on the gate insulating film 40 . A protective layer 60 is arranged on the uppermost portion. In the FET 1 having this structure, for example, the channel layer 20 is composed of an oxide semiconductor layer. Therefore, the "oxide semiconductor layer provided on the base material" as used in the present invention means (i) an oxide semiconductor layer via one or more layers provided in contact with the surface of the base material. and (ii) the oxide semiconductor layer is provided in contact with the surface of the substrate.
　本発明のＦＥＴにおける酸化物半導体層（以下、本発明のＦＥＴにおける酸化物半導体層のことを便宜的に「本発明の酸化物半導体層」ともいう。）は、インジウム（Ｉｎ）元素、亜鉛（Ｚｎ）元素及び添加元素（Ｘ）を含む酸化物から構成されるものである。添加元素（Ｘ）はタンタル（Ｔａ）元素、ストロンチウム（Ｓｒ）元素及びニオブ（Ｎｂ）元素から選ばれる少なくとも一つの元素からなる。本発明の酸化物半導体層は、これを構成する金属元素としてＩｎ、Ｚｎ及び添加元素（Ｘ）を含むものであるが、本発明の効果を損なわない範囲で、これらの元素の他に、意図的に又は不可避的に、微量元素を含んでいてもよい。微量元素としては、例えば後述する有機添加物に含まれる元素やターゲット材製造時に混入するボールミル等のメディア原料が挙げられる。本発明の酸化物半導体層に含まれる微量元素としては、例えばＦｅ、Ｃｒ、Ｎｉ、Ａｌ、Ｓｉ、Ｗ、Ｚｒ、Ｎａ、Ｍｇ、Ｋ、Ｃａ、Ｔｉ、Ｙ、Ｇａ、Ｓｎ、Ｂａ、Ｌａ、Ｃｅ、Ｐｒ、Ｎｄ、Ｐｍ、Ｓｍ、Ｅｕ、Ｇｄ、Ｔｂ、Ｄｙ、Ｈｏ、Ｅｒ、Ｔｍ、Ｙｂ、Ｌｕ及びＰｂ等が挙げられる。それらの含有量は、本発明の酸化物半導体層が含む、Ｉｎ、Ｚｎ及びＸを含む酸化物の合計質量に対して、各々通常１００質量ｐｐｍ（以下「ｐｐｍ」ともいう。）以下であることが好ましく、より好ましくは８０ｐｐｍ以下、更に好ましくは５０ｐｐｍ以下である。これらの微量元素の合計量は５００ｐｐｍ以下であることが好ましく、より好ましくは３００ｐｐｍ以下、更に好ましくは１００ｐｐｍ以下である。本発明の酸化物半導体層に微量元素が含まれる場合は、前記合計質量には微量元素の質量も含まれる。 The oxide semiconductor layer in the FET of the present invention (hereinafter, the oxide semiconductor layer in the FET of the present invention is also referred to as the “oxide semiconductor layer of the present invention” for convenience) contains indium (In) element, zinc ( Zn) element and an additive element (X). The additive element (X) consists of at least one element selected from tantalum (Ta) element, strontium (Sr) element and niobium (Nb) element. The oxide semiconductor layer of the present invention contains In, Zn, and an additive element (X) as metal elements constituting the layer. Or, inevitably, trace elements may be included. Trace elements include, for example, elements contained in organic additives described later and media raw materials such as ball mills that are mixed during the production of the target material. Examples of trace elements contained in the oxide semiconductor layer of the present invention include Fe, Cr, Ni, Al, Si, W, Zr, Na, Mg, K, Ca, Ti, Y, Ga, Sn, Ba, La, Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, Lu, Pb and the like. Their content is usually 100 ppm by mass (hereinafter also referred to as “ppm”) or less with respect to the total mass of oxides containing In, Zn and X contained in the oxide semiconductor layer of the present invention. is preferred, more preferably 80 ppm or less, and still more preferably 50 ppm or less. The total amount of these trace elements is preferably 500 ppm or less, more preferably 300 ppm or less, still more preferably 100 ppm or less. When the oxide semiconductor layer of the present invention contains a trace element, the total mass also includes the mass of the trace element.
　本発明の酸化物半導体層は、これを構成する金属元素、すなわちＩｎ、Ｚｎ及びＸの原子比が特定の範囲であることが、本発明のＦＥＴの性能が向上する点から好ましい。
　具体的には、Ｉｎ及びＸに関しては以下の式（１）で表される原子比を満たすことが好ましい（式中のＸは、前記添加元素の含有比の総和とする。以下、式（２）及び（３）についても同じである。）。
　　　０．４≦（Ｉｎ＋Ｘ）／（Ｉｎ＋Ｚｎ＋Ｘ）≦０．８　（１）
　Ｚｎに関しては以下の式（２）で表される原子比を満たすことが好ましい。
　　　０．２≦Ｚｎ／（Ｉｎ＋Ｚｎ＋Ｘ）≦０．６　　　　　（２）
　Ｘに関しては以下の式（３）で表される原子比を満たすことが好ましい。
　　　０．００１≦Ｘ／（Ｉｎ＋Ｚｎ＋Ｘ）≦０．０１５　　（３） In the oxide semiconductor layer of the present invention, it is preferable that the atomic ratio of the metal elements constituting it, that is, In, Zn and X, is within a specific range from the viewpoint of improving the performance of the FET of the present invention.
Specifically, with respect to In and X, it is preferable that the atomic ratio represented by the following formula (1) is satisfied (X in the formula is the sum of the content ratios of the additive elements. Hereinafter, the formula (2 ) and (3).).
0.4≦(In+X)/(In+Zn+X)≦0.8 (1)
Zn preferably satisfies the atomic ratio represented by the following formula (2).
0.2≦Zn/(In+Zn+X)≦0.6 (2)
X preferably satisfies the atomic ratio represented by the following formula (3).
0.001≦X/(In+Zn+X)≦0.015 (3)
　酸化物半導体層におけるＩｎ、Ｚｎ及びＸの原子比が前記の式（１）ないし（３）の全てを満たすことで、本発明のＦＥＴは、高い電界効果移動度、低いリーク電流及び０Ｖに近いしきい電圧を示すものとなる。これらの利点を一層顕著なものとする観点から、Ｉｎ及びＸに関しては下記の式（１－２）ないし（１－６）を満たすことが更に好ましい。
　　　０．４３≦（Ｉｎ＋Ｘ）／（Ｉｎ＋Ｚｎ＋Ｘ）≦０．７９　（１－２）
　　　０．４８≦（Ｉｎ＋Ｘ）／（Ｉｎ＋Ｚｎ＋Ｘ）≦０．７８　（１－３）
　　　０．５３≦（Ｉｎ＋Ｘ）／（Ｉｎ＋Ｚｎ＋Ｘ）≦０．７５　（１－４）
　　　０．５４≦（Ｉｎ＋Ｘ）／（Ｉｎ＋Ｚｎ＋Ｘ）≦０．７４　（１－５）
　　　０．５８≦（Ｉｎ＋Ｘ）／（Ｉｎ＋Ｚｎ＋Ｘ）≦０．７０　（１－６） When the atomic ratio of In, Zn, and X in the oxide semiconductor layer satisfies all of the above formulas (1) to (3), the FET of the present invention has high field effect mobility, low leakage current, and is close to 0V. It indicates the threshold voltage. From the viewpoint of making these advantages even more remarkable, it is more preferable that In and X satisfy the following formulas (1-2) to (1-6).
0.43≦(In+X)/(In+Zn+X)≦0.79 (1-2)
0.48≦(In+X)/(In+Zn+X)≦0.78 (1-3)
0.53≦(In+X)/(In+Zn+X)≦0.75 (1-4)
0.54≦(In+X)/(In+Zn+X)≦0.74 (1-5)
0.58≦(In+X)/(In+Zn+X)≦0.70 (1-6)
　前記と同様の観点から、Ｚｎに関しては下記の式（２－２）ないし（２－６）を満たすことが更に好ましく、Ｘに関しては下記の式（３－２）ないし（３－５）を満たすことが更に好ましい。 From the same viewpoint as above, it is more preferable that Zn satisfies the following formulas (2-2) to (2-6), and X satisfies the following formulas (3-2) to (3-5). is more preferred.
　　　０．２１≦Ｚｎ／（Ｉｎ＋Ｚｎ＋Ｘ）≦０．５７　　　　（２－２）
　　　０．２２≦Ｚｎ／（Ｉｎ＋Ｚｎ＋Ｘ）≦０．５２　　　　（２－３）
　　　０．２５≦Ｚｎ／（Ｉｎ＋Ｚｎ＋Ｘ）≦０．４７　　　　（２－４）
　　　０．２６≦Ｚｎ／（Ｉｎ＋Ｚｎ＋Ｘ）≦０．４６　　　　（２－５）
　　　０．３０≦Ｚｎ／（Ｉｎ＋Ｚｎ＋Ｘ）≦０．４２　　　　（２－６）
　　　０．００１５≦Ｘ／（Ｉｎ＋Ｚｎ＋Ｘ）≦０．０１３　　（３－２）
　　　０．００２＜Ｘ／（Ｉｎ＋Ｚｎ＋Ｘ）≦０．０１２　　　（３－３）
　　　０．００２５≦Ｘ／（Ｉｎ＋Ｚｎ＋Ｘ）≦０．０１０　　（３－４）
　　　０．００３≦Ｘ／（Ｉｎ＋Ｚｎ＋Ｘ）≦０．００９　　　（３－５） 0.21≦Zn/(In+Zn+X)≦0.57 (2-2)
0.22≦Zn/(In+Zn+X)≦0.52 (2-3)
0.25≦Zn/(In+Zn+X)≦0.47 (2-4)
0.26≦Zn/(In+Zn+X)≦0.46 (2-5)
0.30≦Zn/(In+Zn+X)≦0.42 (2-6)
0.0015≦X/(In+Zn+X)≦0.013 (3-2)
0.002<X/(In+Zn+X)≦0.012 (3-3)
0.0025≦X/(In+Zn+X)≦0.010 (3-4)
0.003≦X/(In+Zn+X)≦0.009 (3-5)
　添加元素（Ｘ）は、上述のとおりＴａ、Ｓｒ及びＮｂから選択される１種以上が用いられる。これらの元素は、それぞれ単独で用いることができ、あるいは２種以上を組み合わせて用いることもできる。特に添加元素（Ｘ）としてＴａを用いることが、本発明のＦＥＴの総合的な性能の観点、及び酸化物半導体層をスパッタリング法によって製造するときに用いられるスパッタリングターゲット材を製造する上での経済性の点から好ましい。
　これらの添加元素のうち、Ｔａ、Ｓｒ及びＮｂのいずれか１種類を用いることが、本発明の所期の効果が十分に奏される点から好ましく、特に好ましくはＴａ又はＮｂのみを用い、とりわけ好ましくはＴａのみを用いる。ただしＴａ、Ｓｒ及びＮｂの３種類を用いてもよい。 As the additive element (X), one or more selected from Ta, Sr and Nb are used as described above. Each of these elements can be used alone, or two or more of them can be used in combination. In particular, the use of Ta as the additive element (X) is advantageous from the viewpoint of the overall performance of the FET of the present invention and the economics of manufacturing the sputtering target material used when manufacturing the oxide semiconductor layer by sputtering. It is preferable from the point of view of sex.
Among these additive elements, it is preferable to use any one of Ta, Sr and Nb from the viewpoint that the desired effect of the present invention is sufficiently exhibited, and it is particularly preferable to use only Ta or Nb. Preferably only Ta is used. However, three types of Ta, Sr and Nb may be used.
　本発明のＦＥＴは、上述の（１）ないし（３）の関係に加えて、ＩｎとＸとの原子比に関して以下の式（４）を満たすことが、本発明のターゲット材から形成される酸化物半導体素子の電界効果移動度を一層高める点、及び０Ｖに近いしきい電圧を示す点から好ましい。
　　　０．９７０≦Ｉｎ／（Ｉｎ＋Ｘ）≦０．９９９　（４） In addition to the relationships (1) to (3) above, the FET of the present invention satisfies the following equation (4) with respect to the atomic ratio of In to X. It is preferable from the point of further increasing the field effect mobility of the physical semiconductor device and from the point of exhibiting a threshold voltage close to 0V.
0.970≦In/(In+X)≦0.999 (4)
　式（４）から明らかなとおり、本発明のＦＥＴにおいては、Ｉｎの量に対して極めて少量のＸを用いることで、ＦＥＴの電界効果移動度が高くなる。このことは本発明者が初めて見いだしたものである。 As is clear from the formula (4), in the FET of the present invention, the use of an extremely small amount of X relative to the amount of In increases the field effect mobility of the FET. This fact was found by the inventor for the first time.
　本発明のＦＥＴの電界効果移動度が一層高くなる観点、及び０Ｖに近いしきい電圧を示す観点から、ＩｎとＸとの原子比は以下の式（４－２）ないし（４－４）を満たすことが更に好ましい。
　　　０．９８０≦Ｉｎ／（Ｉｎ＋Ｘ）≦０．９９７　（４－２）
　　　０．９９０≦Ｉｎ／（Ｉｎ＋Ｘ）≦０．９９５　（４－３）
　　　０．９９０＜Ｉｎ／（Ｉｎ＋Ｘ）≦０．９９３　（４－４） From the viewpoint of further increasing the field effect mobility of the FET of the present invention and from the viewpoint of exhibiting a threshold voltage close to 0 V, the atomic ratio of In to X is determined by the following formulas (4-2) to (4-4). More preferably.
0.980≦In/(In+X)≦0.997 (4-2)
0.990≦In/(In+X)≦0.995 (4-3)
0.990<In/(In+X)≦0.993 (4-4)
　本発明のＦＥＴにおける酸化物半導体層は、Ｉｎ、Ｚｎ、添加元素Ｘ及び酸素を含み、それに加えて他の元素を含んでいてもよいが、ＦＥＴの電界効果移動度が一層高くなる観点からは、前記酸化物半導体層は、Ｉｎ、Ｚｎ、添加元素Ｘ及び酸素を含み、残部不可避不純物からなることが好ましい。 The oxide semiconductor layer in the FET of the present invention contains In, Zn, the additive element X, and oxygen, and may contain other elements in addition, from the viewpoint of further increasing the field effect mobility of the FET. , the oxide semiconductor layer preferably contains In, Zn, an additive element X, and oxygen, and the remainder is composed of unavoidable impurities.
　本発明の酸化物半導体層に含まれる各金属の割合は、例えばＸ線光電子分光法（ＸＰＳ：Ｘ－Ｒａｙ　Ｐｈｏｔｏｅｌｅｃｔｒｏｎ　Ｓｐｅｃｔｒｏｓｃｏｐｙ）や、ＩＣＰ発光分光測定によって測定される。 The ratio of each metal contained in the oxide semiconductor layer of the present invention is measured by, for example, X-ray photoelectron spectroscopy (XPS) or ICP emission spectrometry.
　本発明のＦＥＴの電界効果移動度の値が大きいことは、該ＦＥＴの伝達特性が良好となることに起因するＦＰＤの高機能化の点から好ましい。詳細には本発明のＴＦＴは、その電界効果移動度（ｃｍ２／Ｖｓ）が、２０ｃｍ２／Ｖｓ以上であることが好ましく、３０ｃｍ２／Ｖｓ以上であることが更に好ましく、５０ｃｍ２／Ｖｓ以上であることがより好ましく、６０ｃｍ２／Ｖｓ以上であることが一層好ましく、７０ｃｍ２／Ｖｓ以上であることが更に一層好ましく、８０ｃｍ２／Ｖｓ以上であることがより一層好ましく、１００ｃｍ２／Ｖｓ以上であることが特に好ましい。電界効果移動度の値は大きければ大きいほど、ＦＰＤの高機能化の点から好ましいが、電界効果移動度が２００ｃｍ２／Ｖｓ程度に高ければ、十分に満足すべき程度の性能が得られる。
　電界効果移動度を更に高める観点から、本発明のＦＥＴにおける酸化物半導体層はアモルファス構造を有することが好ましい。 A large value of the field effect mobility of the FET of the present invention is preferable from the viewpoint of enhancing the functionality of the FPD due to the favorable transfer characteristics of the FET. Specifically, the field effect mobility (cm 2 /Vs) of the TFT of the present invention is preferably 20 cm 2 /Vs or more, more preferably 30 cm 2 /Vs or more, and 50 cm 2 /Vs or more. more preferably 60 cm 2 /Vs or more, even more preferably 70 cm 2 /Vs or more, even more preferably 80 cm 2 /Vs or more, 100 cm 2 /Vs or more is particularly preferred. A higher value of the field effect mobility is preferable from the standpoint of improving the functionality of the FPD.
From the viewpoint of further increasing the field effect mobility, the oxide semiconductor layer in the FET of the present invention preferably has an amorphous structure.
　本発明のＦＥＴにおける基材は、フレキシブル配線板に用いられる材料から構成されているか又は２５０℃以下のガラス転移点を有する材料から構成されている。これらの材料から構成される基材を用いることは、本発明のＦＥＴを用いて例えばフレキシブルディスプレイを容易に製造できる点から有利である。
　基材を構成する材料としては、樹脂基材が好ましく、例えばポリエステル系高分子、シリコーン系高分子、アクリル系高分子、ポリオレフィン系高分子、及びこれらの共重合体からなる群より選択される一種又は二種以上が挙げられる。またこれら樹脂基材は２５０℃以下のガラス転移点を有する材料から構成されていることがより好ましい。これらの材料は例えばフィルムの形態をしている。 The substrate in the FET of the present invention is composed of a material used for flexible wiring boards or composed of a material having a glass transition point of 250° C. or lower. The use of substrates composed of these materials is advantageous in that flexible displays, for example, can be easily manufactured using the FETs of the present invention.
As a material constituting the base material, a resin base material is preferable. Or two or more types are mentioned. Moreover, it is more preferable that these resin substrates are made of a material having a glass transition point of 250° C. or less. These materials are for example in the form of films.
　基材を構成する材料の具体例としては、ポリエチレンナフタレート（ＰＥＮ）、ポリエチレンテレフタレート（ＰＥＴ）、ポリフェニレンスルファイド（ＰＰＳ）、ポリエーテルエーテルケトン（ＰＥＥＫ）、ポリスチレン（ＰＳ）、ポリエーテルサルフォン（ＰＥＳ）、ポリカーボネート（ＰＣ）、トリアセチルセルロース（ＴＡＣ）、ポリブチレンテレフタレート（ＰＢＴ）、ポリシラン（ｐｏｌｙｓｉｌａｎｅ）、ポリシロキサン（ｐｏｌｙｓｉｌｏｘａｎｅ）、ポリシラザン（ｐｏｌｙｓｉｌａｚａｎｅ）、ポリカルボシラン（ｐｏｌｙｃａｒｂｏｓｉｌａｎｅ）、ポリアクリレート（ｐｏｌｙａｃｒｙｌａｔｅ）、ポリメタクリレート（ｐｏｌｙｍｅｔｈａｃｒｙｌａｔｅ）、ポリメチルアクリレート（ｐｏｌｙｍｅｔｈｙｌａｃｒｙｌａｔｅ）、ポリエチルアクリレート（ｐｏｌｙｅｔｈｙｌａｃｒｙｌａｔｅ）、ポリエチルメタクリレート（ｐｏｌｙｅｔｈｙｌｍｅｔａｃｒｙｌａｔｅ）、シクロオレフィンコポリマー（ＣＯＣ）、シクロオレフィンポリマー（ＣＯＰ）、ポリエチレン（ＰＥ）、ポリプロピレン（ＰＰ）、ポリメチルメタクリレート（ＰＭＭＡ）、ポリアセタール（ＰＯＭ）、ポリテトラフルオロエチレン（ＰＴＦＥ）、ポリ塩化ビニル（ＰＶＣ）、ポリビニリデンフルオライド（ＰＶＤＦ）、パーフルオロアルキル高分子（ＰＦＡ）及びスチレンアクリルニトリルコポリマー（ＳＡＮ）などが挙げられる。これらの材料は一種を単独で用いることができ、あるいは二種以上を組み合わせて用いることができる。 Specific examples of materials constituting the base material include polyethylene naphthalate (PEN), polyethylene terephthalate (PET), polyphenylene sulfide (PPS), polyetheretherketone (PEEK), polystyrene (PS), polyethersulfone ( PES), polycarbonate (PC), triacetyl cellulose (TAC), polybutylene terephthalate (PBT), polysilane, polysiloxane, polysilazane, polycarbosilane, polyacrylate , polymethacrylate, polymethylacrylate, polyethylacrylate, polyethylmethacrylate, cycloolefin copolymer (COC), cycloolefin polymer (COP), polyethylene (PE), polypropylene (PP ), polymethyl methacrylate (PMMA), polyacetal (POM), polytetrafluoroethylene (PTFE), polyvinyl chloride (PVC), polyvinylidene fluoride (PVDF), perfluoroalkyl polymer (PFA) and styrene acrylnitrile copolymer (SAN). These materials can be used singly or in combination of two or more.
　本発明によれば、基材上への酸化物半導体層の形成に、後述するターゲット材を用いたスパッタリング法を用いることで、フレキシブル配線板に用いられる材料、換言すれば耐熱性が十分に高くない材料から構成される基材であっても、電界効果移動度が高い酸化物半導体層を首尾よく形成できる。この観点から、基材として、ガラス転移点が好ましくは２５０℃以下、更に好ましくは２００℃以下、一層好ましくは１８０℃以下である材料から構成されるものを用いることが可能である。一方で、アニール工程における最低限の耐熱性保持の観点から、典型的には、基材を構成する材料のガラス転移点は０℃以上が好ましく、２５℃以上がより好ましく、８０℃以上であることが更に好ましく、８５℃以上であることが一層好ましく、９０℃以上であることが更に一層好ましい。基材のガラス転移点の測定方法は以下に述べるとおりである。 According to the present invention, by using a sputtering method using a target material to be described later for forming an oxide semiconductor layer on a base material, the material used for the flexible wiring board, in other words, the heat resistance is sufficiently high. An oxide semiconductor layer with high field-effect mobility can be successfully formed even with a base material made of a material that does not have a high field-effect mobility. From this point of view, it is possible to use a material having a glass transition point of preferably 250° C. or lower, more preferably 200° C. or lower, and even more preferably 180° C. or lower as the base material. On the other hand, from the viewpoint of maintaining minimum heat resistance in the annealing step, typically, the glass transition point of the material constituting the substrate is preferably 0° C. or higher, more preferably 25° C. or higher, and 80° C. or higher. is more preferably 85° C. or higher, and even more preferably 90° C. or higher. The method for measuring the glass transition point of the substrate is as described below.
〔ガラス転移点の測定法〕
　本発明において、ガラス転移点はＪＩＳ－Ｋ－７１２１－１９８７（プラスチックの転移温度測定方法）に準拠し、ＤＴＡ法により求める。測定装置としては、典型的には、ＮＥＴＺＳＣＨ社製ＳＴＡ　２５００　Ｒｅｇｕｌｕｓ等を用いて、中間点ガラス転移温度を測定する。 [Measurement method of glass transition point]
In the present invention, the glass transition point is determined by the DTA method in accordance with JIS-K-7121-1987 (method for measuring transition temperature of plastics). As a measuring device, STA 2500 Regulus manufactured by NETZSCH is typically used to measure the midpoint glass transition temperature.
　本発明のＦＥＴにおける基材は、フレキシブル性を高める観点から、その厚みが１μｍ以上５００μｍ以下であることが好ましく、１μｍ以上３００μｍ以下であることが更に好ましく、１μｍ以上１００μｍ以下であることが一層好ましい。
　同様の観点から、本発明のＦＥＴにおける基材は、熱膨張係数が、５ｐｐｍ／℃以上８０ｐｐｍ／℃以下であることが好ましく、５ｐｐｍ／℃以上５０ｐｐｍ／℃以下であることが更に好ましく、５ｐｐｍ／℃以上２０ｐｐｍ／℃以下であることが一層好ましい。 From the viewpoint of enhancing flexibility, the base material of the FET of the present invention preferably has a thickness of 1 μm or more and 500 μm or less, more preferably 1 μm or more and 300 μm or less, and even more preferably 1 μm or more and 100 μm or less. .
From the same point of view, the base material in the FET of the present invention preferably has a thermal expansion coefficient of 5 ppm/° C. or more and 80 ppm/° C. or less, more preferably 5 ppm/° C. or more and 50 ppm/° C. or less. ° C. or more and 20 ppm/° C. or less is more preferable.
　本発明によれば、本発明のＦＥＴを備えた半導体装置も提供される。本明細書において半導体装置とは、半導体特性を利用することで機能し得る装置全般のことであり、例えば電気光学装置、半導体回路及び電子機器はすべて半導体装置である。特に本発明の半導体装置は、ＦＰＤに用いられる薄膜トランジスタとして有用である。 According to the present invention, a semiconductor device including the FET of the present invention is also provided. In this specification, the term "semiconductor device" refers to all devices that can function by utilizing semiconductor characteristics. For example, electro-optical devices, semiconductor circuits, and electronic devices are all semiconductor devices. In particular, the semiconductor device of the present invention is useful as a thin film transistor used for FPD.
　次に、本発明のＦＥＴの好適な製造方法について説明する。本発明のＦＥＴは、公知のフォトリソグラフィー法を用いて製造することができ、特に本発明の酸化物半導体層を製造する場合には、後述するスパッタリングターゲット材を用い、以下の条件でスパッタリングを行うことができる。
　スパッタリング法については、例えばＤＣスパッタリング法を用いることができる。
　スパッタリング時の基材の温度は、例えば１０℃以上２５０℃以下に設定することができる。また基材のガラス転移点を超えない基材温度でスパッタリングをしてもよい。
　スパッタリング時の到達真空度は例えば０．００１Ｐａ未満に設定することができる。
　スパッタガス（雰囲気）としては例えばＡｒとＯ２との混合ガスを用いることができる。この場合、スパッタガスにおけるＯ２ガス濃度は２１ｖｏｌ％以上４９ｖｏｌ％以下、特に２２ｖｏｌ％以上４５ｖｏｌ％以下に設定することができる。Ｏ２ガス濃度をこの範囲に設定することで、スパッタ層を首尾よく半導体化することができる。
　スパッタガス圧は例えば０．１Ｐａ以上３Ｐａ以下に設定することができる。
　スパッタリング電力は例えば０．１Ｗ／ｃｍ２以上１０Ｗ／ｃｍ２以下に設定することができる。 Next, a preferred method for manufacturing the FET of the present invention will be described. The FET of the present invention can be manufactured using a known photolithography method. Particularly when manufacturing the oxide semiconductor layer of the present invention, a sputtering target material described later is used and sputtering is performed under the following conditions. be able to.
As for the sputtering method, for example, a DC sputtering method can be used.
The temperature of the substrate during sputtering can be set to, for example, 10° C. or higher and 250° C. or lower. Sputtering may also be performed at a substrate temperature that does not exceed the glass transition point of the substrate.
The ultimate vacuum degree during sputtering can be set to less than 0.001 Pa, for example.
As the sputtering gas (atmosphere), for example, a mixed gas of Ar and O 2 can be used. In this case, the O 2 gas concentration in the sputtering gas can be set to 21 vol% or more and 49 vol% or less, particularly 22 vol% or more and 45 vol% or less. By setting the O 2 gas concentration within this range, the sputtered layer can be successfully converted to a semiconductor.
The sputtering gas pressure can be set to, for example, 0.1 Pa or more and 3 Pa or less.
Sputtering power can be set to, for example, 0.1 W/cm 2 or more and 10 W/cm 2 or less.
　以上の条件でスパッタリングを行うことで、耐熱性が十分に高くない材料から構成される基材であっても、その上に酸化物半導体層を首尾よく製造できる。 By performing sputtering under the above conditions, an oxide semiconductor layer can be successfully manufactured on even a substrate composed of a material that does not have sufficiently high heat resistance.
　スパッタリング法によって酸化物半導体層が形成されたら、該酸化物半導体層をアニール処理することが好ましい。アニール処理の目的は、該酸化物半導体層に所期の性能を付与することにある。この目的のために、アニール処理の温度は５０℃以上２５０℃以下であることが好ましく、８０℃以上２００℃以下であることが更に好ましく、１００℃以上１８０℃以下であることが一層好ましく、１００℃以上１５０℃以下であることがより一層好ましい。アニール処理の時間は、１分以上１８０分以下であることが好ましく、２分以上１２０分以下であることが更に好ましく、３分以上６０分以下であることが一層好ましい。アニールの雰囲気は、大気圧を含む酸素雰囲気などであることが好ましい。
　酸化物半導体層に対するアニール処理は、該酸化物半導体層の形成直後に行うことができる。あるいは、酸化物半導体層を形成した後に更に別の層を一又は二以上形成し、その後にアニール処理を行ってもよい。 After the oxide semiconductor layer is formed by a sputtering method, the oxide semiconductor layer is preferably annealed. The purpose of the annealing treatment is to impart desired performance to the oxide semiconductor layer. For this purpose, the temperature of the annealing treatment is preferably 50° C. or higher and 250° C. or lower, more preferably 80° C. or higher and 200° C. or lower, even more preferably 100° C. or higher and 180° C. or lower. °C or higher and 150 °C or lower is even more preferable. The annealing time is preferably 1 minute or more and 180 minutes or less, more preferably 2 minutes or more and 120 minutes or less, and even more preferably 3 minutes or more and 60 minutes or less. The annealing atmosphere is preferably an oxygen atmosphere including atmospheric pressure.
Annealing treatment for the oxide semiconductor layer can be performed immediately after the oxide semiconductor layer is formed. Alternatively, one or more layers may be formed after the oxide semiconductor layer is formed, and then annealing treatment may be performed.
　スパッタリング法によって本発明の酸化物半導体層を製造する場合、理論的には、スパッタリングに用いるターゲット材の組成がそのまま酸化物半導体層の組成に反映される。つまりターゲット材に由来する酸化物半導体層が形成される。したがって、上述した組成を有する本発明の酸化物半導体層を形成するためには、インジウム（Ｉｎ）元素、亜鉛（Ｚｎ）元素及び添加元素（Ｘ）を含む酸化物からなるスパッタリングターゲット材（添加元素（Ｘ）はタンタル（Ｔａ）元素、ストロンチウム（Ｓｒ）元素及びニオブ（Ｎｂ）元素から選ばれる少なくとも１種の元素である。）を用いればよい。すなわち、このスパッタリングターゲット材は、フレキシブル配線板に用いられる基材又は２５０℃以下のガラス転移点を有する基材上に設けられ且つ該スパッタリングターゲット材に由来する酸化物半導体層を備えたＦＥＴの製造に好適に用いられるものである。以下の説明では、ＦＥＴ製造用のスパッタリングターゲット材のことを便宜的に「本発明のターゲット材」ともいう。 When the oxide semiconductor layer of the present invention is manufactured by a sputtering method, the composition of the target material used for sputtering is theoretically directly reflected in the composition of the oxide semiconductor layer. That is, an oxide semiconductor layer derived from the target material is formed. Therefore, in order to form the oxide semiconductor layer of the present invention having the composition described above, a sputtering target material (additive element (X) is at least one element selected from tantalum (Ta) element, strontium (Sr) element and niobium (Nb) element). That is, this sputtering target material is provided on a base material used for a flexible wiring board or a base material having a glass transition point of 250° C. or less, and is provided on the base material, and is used in the manufacture of an FET having an oxide semiconductor layer derived from the sputtering target material. It is preferably used for In the following description, the sputtering target material for manufacturing FETs is also referred to as "the target material of the present invention" for convenience.
　具体的には、各元素の原子比が以下の式（１）ないし（３）の全てを満たすＦＥＴ製造用スパッタリングターゲット材（式中のＸは、前記添加元素の含有比の総和とする。）を用いればよい。
　　　０．４≦（Ｉｎ＋Ｘ）／（Ｉｎ＋Ｚｎ＋Ｘ）≦０．８　（１）
　　　０．２≦Ｚｎ／（Ｉｎ＋Ｚｎ＋Ｘ）≦０．６　　　　　（２）
　　　０．００１≦Ｘ／（Ｉｎ＋Ｚｎ＋Ｘ）≦０．０１５　　（３） Specifically, a sputtering target material for FET manufacturing in which the atomic ratio of each element satisfies all of the following formulas (1) to (3) (X in the formula is the sum of the content ratios of the additive elements.) should be used.
0.4≦(In+X)/(In+Zn+X)≦0.8 (1)
0.2≦Zn/(In+Zn+X)≦0.6 (2)
0.001≦X/(In+Zn+X)≦0.015 (3)
　前記ＦＥＴ製造用スパッタリングターゲット材は、該ターゲット材を構成する各元素の原子比が、式（４）を更に満たすことが好適である。
　　　０．９７０≦Ｉｎ／（Ｉｎ＋Ｘ）≦０．９９９　（４） In the sputtering target material for manufacturing FETs, the atomic ratio of each element constituting the target material preferably further satisfies the formula (4).
0.970≦In/(In+X)≦0.999 (4)
　前記の式（１）－（４）の好ましい範囲は、本発明の酸化物半導体層について上述した範囲、すなわち式（１－２）から（４－４）と同じである。 The preferred ranges of the above formulas (1) to (4) are the same as the ranges described above for the oxide semiconductor layer of the present invention, that is, the formulas (1-2) to (4-4).
　本発明のターゲット材は、上述したとおりＩｎ、Ｚｎ及びＸを含む酸化物から構成されている。この酸化物は、Ｉｎの酸化物、Ｚｎの酸化物又はＸの酸化物であり得る。あるいはこの酸化物は、Ｉｎ、Ｚｎ及びＸからなる群から選択される任意の２種以上の元素の複合酸化物であり得る。複合酸化物の具体的な例としては、Ｉｎ－Ｚｎ複合酸化物、Ｚｎ－Ｔａ複合酸化物、Ｉｎ－Ｔａ複合酸化物、Ｉｎ－Ｎｂ複合酸化物、Ｚｎ－Ｎｂ複合酸化物、Ｉｎ－Ｓｒ複合酸化物、Ｚｎ－Ｓｒ複合酸化物、Ｉｎ－Ｚｎ－Ｔａ複合酸化物、Ｉｎ－Ｚｎ－Ｎｂ複合酸化物、Ｉｎ－Ｚｎ－Ｓｒ複合酸化物等が挙げられるが、これらに限られるものではない。 The target material of the present invention is composed of oxides containing In, Zn and X as described above. This oxide can be an In oxide, a Zn oxide or an X oxide. Alternatively, this oxide may be a composite oxide of any two or more elements selected from the group consisting of In, Zn and X. Specific examples of composite oxides include In—Zn composite oxide, Zn—Ta composite oxide, In—Ta composite oxide, In—Nb composite oxide, Zn—Nb composite oxide, In—Sr composite oxide Examples include oxides, Zn--Sr composite oxides, In--Zn--Ta composite oxides, In--Zn--Nb composite oxides, and In--Zn--Sr composite oxides, but are not limited to these.
　本発明のターゲット材は、特にＩｎの酸化物であるＩｎ２Ｏ３相及びＩｎとＺｎとの複合酸化物であるＺｎ３Ｉｎ２Ｏ６相を含むことが、該ターゲット材の密度及び強度を高め且つ抵抗を低減させる観点から好ましい。本発明のターゲット材がＩｎ２Ｏ３相及びＺｎ３Ｉｎ２Ｏ６相を含むことは、本発明のターゲット材を対象としたＸ線回折（以下「ＸＲＤ」ともいう。）測定によってＩｎ２Ｏ３相及びＺｎ３Ｉｎ２Ｏ６相が観察されるか否かによって判断できる。なお、本発明におけるＩｎ２Ｏ３相は微量にＺｎ元素を含み得る。 The target material of the present invention particularly includes an In 2 O 3 phase, which is an In oxide, and a Zn 3 In 2 O 6 phase, which is a composite oxide of In and Zn. It is preferable from the viewpoint of increasing resistance and reducing resistance. The fact that the target material of the present invention contains the In 2 O 3 phase and the Zn 3 In 2 O 6 phase can be confirmed by X-ray diffraction (hereinafter also referred to as “ XRD ”) measurement of the target material of the present invention. It can be determined by whether three phases and a Zn3In2O6 phase are observed . In addition, the In 2 O 3 phase in the present invention may contain a trace amount of Zn element.
　詳細には、Ｘ線源としてＣｕＫα線を用いたＸＲＤ測定においてＩｎ２Ｏ３相は２θ＝３０．３８°以上３０．７８°以下の範囲にメインピークが観察される。Ｚｎ３Ｉｎ２Ｏ６相は２θ＝３４．００°以上３４．４０°以下の範囲にメインピークが観察される。 Specifically, in the XRD measurement using CuKα rays as an X-ray source, the In 2 O 3 phase has a main peak in the range of 2θ=30.38° or more and 30.78° or less. The Zn 3 In 2 O 6 phase has a main peak in the range of 2θ=34.00° to 34.40°.
　更に本発明のターゲット材においては、Ｉｎ２Ｏ３相及びＺｎ３Ｉｎ２Ｏ６相の双方に添加元素（Ｘ）が含まれることが好ましい。とりわけ、ターゲット材全体に均質に添加元素（Ｘ）が分散して含まれると、本発明のターゲット材から形成される酸化物半導体に一様に添加元素（Ｘ）が含まれることになり、均質な酸化物半導体膜を得ることができる。Ｉｎ２Ｏ３相及びＺｎ３Ｉｎ２Ｏ６相の双方に添加元素（Ｘ）が含まれることは、例えばエネルギー分散型Ｘ線分光法（以下「ＥＤＸ」ともいう。）などにより測定することができる。 Further, in the target material of the present invention, both the In2O3 phase and the Zn3In2O6 phase preferably contain the additive element (X). In particular, when the additive element (X) is homogeneously dispersed throughout the target material, the additive element (X) is uniformly contained in the oxide semiconductor formed from the target material of the present invention. A fine oxide semiconductor film can be obtained. The inclusion of the additional element (X) in both the In 2 O 3 phase and the Zn 3 In 2 O 6 phase can be measured by, for example, energy dispersive X-ray spectroscopy (hereinafter also referred to as “EDX”). can.
　ＸＲＤ測定によって本発明のターゲット材にＩｎ２Ｏ３相が観察される場合、Ｉｎ２Ｏ３相はその結晶粒のサイズが特定の範囲を満たすことが、本発明のターゲット材の密度及び強度を高め且つ抵抗を低減させる点から好ましい。詳細には、Ｉｎ２Ｏ３相の結晶粒のサイズは、３．０μｍ以下であることが好ましく、２．７μｍ以下であることが更に好ましく、２．５μｍ以下であることが一層好ましい。結晶粒のサイズは小さいほど好ましく下限値は特に定めるものではないが、通常０．１μｍ以上である。 When an In 2 O 3 phase is observed in the target material of the present invention by XRD measurement, the fact that the In 2 O 3 phase has a crystal grain size that satisfies a specific range indicates the density and strength of the target material of the present invention. It is preferable from the viewpoint of increasing the resistance and reducing the resistance. Specifically, the crystal grain size of the In 2 O 3 phase is preferably 3.0 μm or less, more preferably 2.7 μm or less, and even more preferably 2.5 μm or less. The smaller the crystal grain size, the better, and although the lower limit is not particularly defined, it is usually 0.1 μm or more.
　ＸＲＤ測定によって本発明のターゲット材にＺｎ３Ｉｎ２Ｏ６相が観察される場合、Ｚｎ３Ｉｎ２Ｏ６相に関しても、その結晶粒のサイズが特定の範囲を満たすことが、本発明のターゲット材の密度及び強度を高め且つ抵抗を低減させる点から好ましい。詳細には、Ｚｎ３Ｉｎ２Ｏ６相の結晶粒のサイズは、３．９μｍ以下であることが好ましく、３．５μｍ以下であることがより好ましく、３．０μｍ以下であることが更に好ましく、２．５μｍ以下であることが一層好ましく、２．３μｍ以下であることが更に一層好ましく、２．０μｍ以下であることが特に好ましく、１．９μｍ以下であることがとりわけ好ましい。結晶粒のサイズは小さいほど好ましく下限値は特に定めるものではないが、通常０．１μｍ以上である。 When the Zn 3 In 2 O 6 phase is observed in the target material of the present invention by XRD measurement, it is confirmed that the crystal grain size of the Zn 3 In 2 O 6 phase also satisfies a specific range. It is preferable from the viewpoint of increasing the density and strength of the material and reducing the resistance. Specifically, the crystal grain size of the Zn 3 In 2 O 6 phase is preferably 3.9 μm or less, more preferably 3.5 μm or less, even more preferably 3.0 μm or less, It is more preferably 2.5 μm or less, even more preferably 2.3 μm or less, particularly preferably 2.0 μm or less, and most preferably 1.9 μm or less. The smaller the crystal grain size, the better, and although the lower limit is not particularly defined, it is usually 0.1 μm or more.
　Ｉｎ２Ｏ３相の結晶粒のサイズ及びＺｎ３Ｉｎ２Ｏ６相の結晶粒のサイズを上述した範囲に設定するには、例えば後述する方法によってターゲット材を製造すればよい。
　Ｉｎ２Ｏ３相の結晶粒のサイズ及びＺｎ３Ｉｎ２Ｏ６相の結晶粒のサイズは、本発明のターゲット材を走査型電子顕微鏡（以下「ＳＥＭ」ともいう。）によって観察することで測定される。具体的な測定方法は後述する実施例において詳述する。 In order to set the crystal grain size of the In 2 O 3 phase and the crystal grain size of the Zn 3 In 2 O 6 phase within the above ranges, for example, a target material may be manufactured by the method described later.
The crystal grain size of the In 2 O 3 phase and the crystal grain size of the Zn 3 In 2 O 6 phase are measured by observing the target material of the present invention with a scanning electron microscope (hereinafter also referred to as “SEM”). be done. A specific measuring method will be described in detail in Examples described later.
　本発明のターゲット材は、Ｉｎ、Ｚｎ、添加元素Ｘ及び酸素を含み、それに加えて他の元素を含んでいてもよいが、前記ターゲット材を用いて製造されるＦＥＴの電界効果移動度が一層高くなる観点からは、前記ターゲット材は、Ｉｎ、Ｚｎ、添加元素Ｘ及び酸素を含み、残部不可避不純物からなることが好ましい。 The target material of the present invention contains In, Zn, the additive element X and oxygen, and may contain other elements in addition. From the viewpoint of increasing the cost, it is preferable that the target material contains In, Zn, the additive element X, and oxygen, and the remainder consists of unavoidable impurities.
　次に、本発明のターゲット材の好適な製造方法について説明する。本製造方法においては、ターゲット材の原料となる酸化物粉末を所定の形状に成形して成形体を得て、この成形体を焼成することで、焼結体からなるターゲット材を得る。成形体を得るには、当該技術分野においてこれまで知られている方法、例えば鋳込み成形法を採用することができる。特にＣＩＰ成形法を採用することが、緻密なターゲット材を製造し得る点から好ましい。 Next, a suitable method for manufacturing the target material of the present invention will be described. In this manufacturing method, an oxide powder, which is a raw material of a target material, is formed into a predetermined shape to obtain a compact, and the compact is fired to obtain a target material composed of a sintered compact. To obtain the molded body, methods hitherto known in the art, such as slip casting, can be employed. In particular, it is preferable to adopt the CIP molding method from the point of being able to manufacture a dense target material.
　ＣＩＰ成形法においては、鋳込み成形法において用いたスラリーと同様のスラリーを噴霧乾燥して乾燥粉末を得る。得られた乾燥粉末を型に充填してＣＩＰ成形を行う。 In the CIP molding method, a slurry similar to that used in the casting method is spray-dried to obtain a dry powder. The resulting dry powder is filled into a mold and subjected to CIP molding.
　このようにして成形体が得られたら、次にこれを焼成する。成形体の焼成は一般に酸素含有雰囲気中で行うことができる。特に大気雰囲気中で焼成することが簡便である。焼成温度は１２００℃以上１６００℃以下であることが好ましく、１３００℃以上１５００℃以下であることが更に好ましく、１３５０℃以上１４５０℃以下であることが一層好ましい。焼成時間は、１時間以上１００時間以下であることが好ましく、２時間以上５０時間以下であることが更に好ましく、３時間以上３０時間以下であることが一層好ましい。昇温速度は５℃／時間以上５００℃／時間以下であることが好ましく、１０℃／時間以上２００℃／時間以下であることが更に好ましく、２０℃／時間以上１００℃／時間以下であることが一層好ましい。 After the compact is obtained in this way, it is then fired. Firing of the compact can generally be carried out in an oxygen-containing atmosphere. In particular, firing in an air atmosphere is convenient. The firing temperature is preferably 1200° C. or higher and 1600° C. or lower, more preferably 1300° C. or higher and 1500° C. or lower, and still more preferably 1350° C. or higher and 1450° C. or lower. The firing time is preferably from 1 hour to 100 hours, more preferably from 2 hours to 50 hours, and even more preferably from 3 hours to 30 hours. The heating rate is preferably 5°C/hour or more and 500°C/hour or less, more preferably 10°C/hour or more and 200°C/hour or less, and 20°C/hour or more and 100°C/hour or less. is more preferred.
　成形体の焼成においては、焼成過程においてＩｎとＺｎとの複合酸化物、例えばＺｎ５Ｉｎ２Ｏ８の相が生成する温度を一定時間維持することが、焼結の促進及び緻密なターゲット材の生成の観点から好ましい。詳細には、原料粉末にＩｎ２Ｏ３粉及びＺｎＯ粉が含まれている場合、昇温に従いこれらが反応してＺｎ５Ｉｎ２Ｏ８の相が生成し、その後Ｚｎ４Ｉｎ２Ｏ７の相へ変化し、Ｚｎ３Ｉｎ２Ｏ６の相へと変化する。特にＺｎ５Ｉｎ２Ｏ８の相が生成する際に体積拡散が進み緻密化が促進されることから、Ｚｎ５Ｉｎ２Ｏ８の相を確実に生成させることが好ましい。このような観点から、焼成の昇温過程において、温度を１０００℃以上１２５０℃以下の範囲で一定時間維持することが好ましく、１０５０℃以上１２００℃以下の範囲で一定時間維持することが更に好ましい。維持する温度は、必ずしもある特定の一点の温度に限られるものではなく、ある程度の幅を有する温度範囲であってもよい。具体的には、１０００℃以上１２５０℃以下の範囲から選ばれるある特定の温度をＴ（℃）とするとき、１０００℃以上１２５０℃以下の範囲に含まれる限り、例えばＴ±１０℃であってもよく、好ましくはＴ±５℃であり、より好ましくはＴ±３℃であり、更に好ましくはＴ±１℃である。この温度範囲を維持する時間は、好ましくは１時間以上４０時間以下であり、更に好ましくは２時間以上２０時間以下である。 In sintering the compact, maintaining the temperature at which a phase of In and Zn composite oxides, such as Zn 5 In 2 O 8 , is generated during the sintering process for a certain period of time promotes sintering and produces a dense target material. It is preferable from the production point of view. Specifically, when the raw material powder contains In 2 O 3 powder and ZnO powder, as the temperature rises, these react to form a Zn 5 In 2 O 8 phase, and then a Zn 4 In 2 O 7 phase. phase to Zn 3 In 2 O 6 . In particular, when the Zn 5 In 2 O 8 phase is generated, volume diffusion proceeds and densification is promoted, so it is preferable to reliably generate the Zn 5 In 2 O 8 phase. From this point of view, it is preferable to maintain the temperature in the range of 1000° C. or higher and 1250° C. or lower for a certain period of time, and more preferably to maintain the temperature in the range of 1050° C. or higher and 1200° C. or lower for a certain period of time. The temperature to be maintained is not necessarily limited to one specific temperature, but may be a temperature range with a certain width. Specifically, when a specific temperature selected from the range of 1000 ° C. or higher and 1250 ° C. or lower is T (° C.), as long as it is included in the range of 1000 ° C. or higher and 1250 ° C. or lower, for example, T ± 10 ° C. preferably T±5°C, more preferably T±3°C, still more preferably T±1°C. The time for maintaining this temperature range is preferably 1 hour or more and 40 hours or less, more preferably 2 hours or more and 20 hours or less.
　このようにして得られたターゲット材は、研削加工などにより、所定の寸法に加工することができる。これを基材に接合することでスパッタリングターゲットが得られる。ターゲット材の形状に特に制限はなく、従来公知の形状、例えば平板型及び円筒形などを採用することができる。 The target material obtained in this way can be processed to a predetermined size by grinding or the like. A sputtering target is obtained by joining this to a base material. There is no particular limitation on the shape of the target material, and conventionally known shapes such as a flat plate shape and a cylindrical shape can be adopted.
　以上、本発明をその好ましい実施形態に基づき説明したが、本発明は前記実施形態に制限されない。 Although the present invention has been described above based on its preferred embodiments, the present invention is not limited to the above embodiments.
　上述した実施形態に関し、本発明は更に以下の電界効果トランジスタ及びその製造方法並びに電界効果トランジスタ製造用スパッタリングターゲット材を開示する。
〔１〕　２５０℃以下のガラス転移点を有する基材と、該基材上に設けられた酸化物半導体層とを備えた、電界効果トランジスタであって、
　前記酸化物半導体層は、インジウム（Ｉｎ）元素、亜鉛（Ｚｎ）元素及び添加元素（Ｘ）を含む酸化物から構成され、
　添加元素（Ｘ）はタンタル（Ｔａ）元素、ストロンチウム（Ｓｒ）元素及びニオブ（Ｎｂ）元素から選ばれる少なくとも１種の元素であり、
　各元素の原子比が式（１）ないし（３）の全てを満たす電界効果トランジスタ（式中のＸは、前記添加元素の含有比の総和とする。）。
　　　０．４≦（Ｉｎ＋Ｘ）／（Ｉｎ＋Ｚｎ＋Ｘ）≦０．８　（１）
　　　０．２≦Ｚｎ／（Ｉｎ＋Ｚｎ＋Ｘ）≦０．６　　　　　（２）
　　　０．００１≦Ｘ／（Ｉｎ＋Ｚｎ＋Ｘ）≦０．０１５　　（３） In relation to the above-described embodiments, the present invention further discloses the following field effect transistors, methods for manufacturing the same, and sputtering target materials for manufacturing field effect transistors.
[1] A field effect transistor comprising a substrate having a glass transition point of 250° C. or less and an oxide semiconductor layer provided on the substrate,
The oxide semiconductor layer is composed of an oxide containing an indium (In) element, a zinc (Zn) element and an additive element (X),
The additive element (X) is at least one element selected from tantalum (Ta) element, strontium (Sr) element and niobium (Nb) element,
A field effect transistor in which the atomic ratio of each element satisfies all of the formulas (1) to (3) (X in the formula is the sum of the content ratios of the additive elements).
0.4≦(In+X)/(In+Zn+X)≦0.8 (1)
0.2≦Zn/(In+Zn+X)≦0.6 (2)
0.001≦X/(In+Zn+X)≦0.015 (3)
〔２〕　フレキシブル配線板に用いられる基材と、該基材上に設けられた酸化物半導体層とを備えた、電界効果トランジスタであって、
　前記酸化物半導体層は、インジウム（Ｉｎ）元素、亜鉛（Ｚｎ）元素及び添加元素（Ｘ）を含む酸化物から構成され、
　添加元素（Ｘ）はタンタル（Ｔａ）元素、ストロンチウム（Ｓｒ）元素及びニオブ（Ｎｂ）元素から選ばれる少なくとも１種の元素であり、
　各元素の原子比が式（１）ないし（３）の全てを満たす電界効果トランジスタ（式中のＸは、前記添加元素の含有比の総和とする。）。
　　　０．４≦（Ｉｎ＋Ｘ）／（Ｉｎ＋Ｚｎ＋Ｘ）≦０．８　（１）
　　　０．２≦Ｚｎ／（Ｉｎ＋Ｚｎ＋Ｘ）≦０．６　　　　　（２）
　　　０．００１≦Ｘ／（Ｉｎ＋Ｚｎ＋Ｘ）≦０．０１５　　（３）
〔３〕　前記添加元素（Ｘ）が、タンタル（Ｔａ）元素又はニオブ（Ｎｂ）元素である、〔１〕又は〔２〕に記載の電界効果トランジスタ。
〔４〕　前記添加元素（Ｘ）が、タンタル（Ｔａ）元素である、〔３〕に記載の電界効果トランジスタ。
〔５〕　前記酸化物半導体層を構成する各元素の原子比が、式（４）を更に満たす、〔１〕ないし〔４〕のいずれか一に記載の電界効果トランジスタ。
　　　０．９７０≦Ｉｎ／（Ｉｎ＋Ｘ）≦０．９９９　（４）
〔６〕　前記電界効果トランジスタの電界効果移動度が２０ｃｍ２／Ｖｓ以上である、〔１〕ないし〔５〕のいずれか一に記載の電界効果トランジスタ。 [2] A field effect transistor comprising a substrate used in a flexible wiring board and an oxide semiconductor layer provided on the substrate,
The oxide semiconductor layer is composed of an oxide containing an indium (In) element, a zinc (Zn) element and an additive element (X),
The additive element (X) is at least one element selected from tantalum (Ta) element, strontium (Sr) element and niobium (Nb) element,
A field effect transistor in which the atomic ratio of each element satisfies all of the formulas (1) to (3) (X in the formula is the sum of the content ratios of the additive elements).
0.4≦(In+X)/(In+Zn+X)≦0.8 (1)
0.2≦Zn/(In+Zn+X)≦0.6 (2)
0.001≦X/(In+Zn+X)≦0.015 (3)
[3] The field effect transistor according to [1] or [2], wherein the additive element (X) is a tantalum (Ta) element or a niobium (Nb) element.
[4] The field effect transistor according to [3], wherein the additive element (X) is a tantalum (Ta) element.
[5] The field effect transistor according to any one of [1] to [4], wherein the atomic ratio of each element constituting the oxide semiconductor layer further satisfies formula (4).
0.970≦In/(In+X)≦0.999 (4)
[6] The field effect transistor according to any one of [1] to [5], wherein the field effect transistor has a field effect mobility of 20 cm 2 /Vs or more.
〔７〕　前記電界効果トランジスタの電界効果移動度が３０ｃｍ２／Ｖｓ以上である、〔６〕に記載の電界効果トランジスタ。
〔８〕　前記電界効果トランジスタの電界効果移動度が５０ｃｍ２／Ｖｓ以上である、〔７〕に記載の電界効果トランジスタ。
〔９〕　前記基材がポリエチレンナフタレート（ＰＥＮ）、ポリエチレンテレフタレート（ＰＥＴ）、ポリフェニレンスルファイド（ＰＰＳ）、ポリエーテルエーテルケトン（ＰＥＥＫ）、ポリスチレン（ＰＳ）、ポリエーテルサルフォン（ＰＥＳ）、ポリカーボネート（ＰＣ）、トリアセチルセルロース（ＴＡＣ）、シクロオレフィンポリマー（ＣＯＰ）である、〔１〕ないし〔８〕のいずれか一に記載の電界効果トランジスタ。
〔１０〕　インジウム（Ｉｎ）元素、亜鉛（Ｚｎ）元素及び添加元素（Ｘ）を含む酸化物からなるスパッタリングターゲット材を用い（添加元素（Ｘ）はタンタル（Ｔａ）元素、ストロンチウム（Ｓｒ）元素及びニオブ（Ｎｂ）元素から選ばれる少なくとも１種の元素である。）、酸素濃度が２１ｖｏｌ％以上４９ｖｏｌ％以下である雰囲気下に、フレキシブル配線板に用いられる基材又は２５０℃以下のガラス転移点を有する基材に対してスパッタリングを行い、前記ターゲット材に由来する酸化物半導体を形成し、
　前記酸化物半導体を５０℃以上２５０℃以下でアニール処理する、工程を有する電界効果トランジスタの製造方法。
〔１１〕　前記添加元素（Ｘ）が、タンタル（Ｔａ）元素又はニオブ（Ｎｂ）元素である、〔１０〕に記載の製造方法。 [7] The field effect transistor according to [6], wherein the field effect transistor has a field effect mobility of 30 cm 2 /Vs or more.
[8] The field effect transistor according to [7], wherein the field effect transistor has a field effect mobility of 50 cm 2 /Vs or more.
[9] The base material is polyethylene naphthalate (PEN), polyethylene terephthalate (PET), polyphenylene sulfide (PPS), polyetheretherketone (PEEK), polystyrene (PS), polyethersulfone (PES), polycarbonate ( PC), triacetyl cellulose (TAC), cycloolefin polymer (COP), the field effect transistor according to any one of [1] to [8].
[10] Using a sputtering target material made of an oxide containing an indium (In) element, a zinc (Zn) element and an additive element (X) (the additive element (X) is a tantalum (Ta) element, a strontium (Sr) element and At least one element selected from niobium (Nb) elements), and a base material used for a flexible wiring board or a glass transition point of 250 ° C. or less in an atmosphere having an oxygen concentration of 21 vol% or more and 49 vol% or less. Sputtering is performed on a base material having, to form an oxide semiconductor derived from the target material,
A method of manufacturing a field effect transistor, comprising a step of annealing the oxide semiconductor at 50° C. or higher and 250° C. or lower.
[11] The production method according to [10], wherein the additive element (X) is a tantalum (Ta) element or a niobium (Nb) element.
〔１２〕　前記添加元素（Ｘ）が、タンタル（Ｔａ）元素である、〔１１〕に記載の製造方法。
〔１３〕　前記ターゲット材における各元素の原子比が式（１）ないし（３）の全てを満たす、〔１０〕ないし〔１２〕のいずれか一に記載の製造方法（式中のＸは、前記添加元素の含有比の総和とする。）。
　　　０．４≦（Ｉｎ＋Ｘ）／（Ｉｎ＋Ｚｎ＋Ｘ）≦０．８　（１）
　　　０．２≦Ｚｎ／（Ｉｎ＋Ｚｎ＋Ｘ）≦０．６　　　　　（２）
　　　０．００１≦Ｘ／（Ｉｎ＋Ｚｎ＋Ｘ）≦０．０１５　　（３）
〔１４〕　インジウム（Ｉｎ）元素、亜鉛（Ｚｎ）元素及び添加元素（Ｘ）を含む酸化物から構成され、
　添加元素（Ｘ）はタンタル（Ｔａ）元素、ストロンチウム（Ｓｒ）元素及びニオブ（Ｎｂ）元素から選ばれる少なくとも１種の元素であり、
　各元素の原子比が式（１）ないし（３）の全てを満たすスパッタリングターゲット材であって、
　フレキシブル配線板に用いられる基材又は２５０℃以下のガラス転移点を有する基材上に設けられ且つ前記スパッタリングターゲット材に由来する酸化物半導体層、を備えた電界効果トランジスタの製造用スパッタリングターゲット材。
　　　０．４≦（Ｉｎ＋Ｘ）／（Ｉｎ＋Ｚｎ＋Ｘ）≦０．８　（１）
　　　０．２≦Ｚｎ／（Ｉｎ＋Ｚｎ＋Ｘ）≦０．６　　　　　（２）
　　　０．００１≦Ｘ／（Ｉｎ＋Ｚｎ＋Ｘ）≦０．０１５　　（３）
〔１５〕　前記添加元素（Ｘ）が、タンタル（Ｔａ）元素又はニオブ（Ｎｂ）元素である、〔１４〕に記載のスパッタリングターゲット材。
〔１６〕　前記添加元素（Ｘ）が、タンタル（Ｔａ）元素である、〔１５〕に記載のスパッタリングターゲット材。 [12] The production method according to [11], wherein the additive element (X) is a tantalum (Ta) element.
[13] The manufacturing method according to any one of [10] to [12], wherein the atomic ratio of each element in the target material satisfies all of formulas (1) to (3) (wherein X is the sum of the content ratios of the additive elements).
0.4≦(In+X)/(In+Zn+X)≦0.8 (1)
0.2≦Zn/(In+Zn+X)≦0.6 (2)
0.001≦X/(In+Zn+X)≦0.015 (3)
[14] composed of an oxide containing an indium (In) element, a zinc (Zn) element and an additive element (X),
The additive element (X) is at least one element selected from tantalum (Ta) element, strontium (Sr) element and niobium (Nb) element,
A sputtering target material in which the atomic ratio of each element satisfies all of formulas (1) to (3),
A sputtering target material for producing a field effect transistor, comprising: a base material used for a flexible wiring board or a base material having a glass transition point of 250° C. or lower and an oxide semiconductor layer derived from the sputtering target material.
0.4≦(In+X)/(In+Zn+X)≦0.8 (1)
0.2≦Zn/(In+Zn+X)≦0.6 (2)
0.001≦X/(In+Zn+X)≦0.015 (3)
[15] The sputtering target material according to [14], wherein the additive element (X) is a tantalum (Ta) element or a niobium (Nb) element.
[16] The sputtering target material according to [15], wherein the additive element (X) is a tantalum (Ta) element.
〔１７〕　前記電界効果トランジスタの製造用スパッタリングターゲット材がＩｎ２Ｏ３相及びＺｎ３Ｉｎ２Ｏ６相を含む、〔１４〕ないし〔１６〕のいずれか一に記載の電界効果トランジスタの製造用スパッタリングターゲット材。
〔１８〕　Ｉｎ２Ｏ３相及びＺｎ３Ｉｎ２Ｏ６相の双方に添加元素（Ｘ）が含まれる、〔１７〕に記載の電界効果トランジスタの製造用スパッタリングターゲット材。
〔１９〕　Ｉｎ２Ｏ３相の結晶粒のサイズが０．１μｍ以上３．０μｍ以下であり、
　Ｚｎ３Ｉｎ２Ｏ６相の結晶粒のサイズが０．１μｍ以上３．９μｍ以下である、〔１７〕又は〔１８〕に記載の電界効果トランジスタの製造用スパッタリングターゲット材。
〔２０〕　〔１〕ないし〔９〕のいずれか一に記載の電界効果トランジスタを用いた半導体装置。 [17] The method for producing a field effect transistor according to any one of [14] to [16], wherein the sputtering target material for producing a field effect transistor contains an In 2 O 3 phase and a Zn 3 In 2 O 6 phase. Sputtering target material.
[18] The sputtering target material for producing a field effect transistor according to [17], wherein both the In 2 O 3 phase and the Zn 3 In 2 O 6 phase contain the additional element (X).
[19] the crystal grain size of the In 2 O 3 phase is 0.1 μm or more and 3.0 μm or less;
A sputtering target material for producing a field effect transistor according to [17] or [18], wherein the Zn 3 In 2 O 6 phase has a crystal grain size of 0.1 μm or more and 3.9 μm or less.
[20] A semiconductor device using the field effect transistor according to any one of [1] to [9].
　以下、実施例により本発明を更に詳細に説明する。しかしながら本発明の範囲は、かかる実施例に制限されない。 The present invention will be described in more detail below with reference to examples. However, the scope of the invention is not limited to such examples.
　　〔実施例１〕
　Ｉｎ２Ｏ３粉末と、ＺｎＯ粉末と、Ｔａ２Ｏ５粉末とを、ＩｎとＺｎとＴａとの原子比が、以下の表１に示す値となるようにしたターゲット材を用いて、図１に示すＦＥＴ１をフォトリソグラフィー法により作製した。
　ＦＥＴ１の作製においては、基材１０としてポリエチレンナフタレートフィルム（東洋紡株式会社製テオネックス（登録商標））（ガラス転移点：１５５℃）を用いた。基材１０上に、ソース電極３０及びドレイン電極３１としてＭｏ薄膜を、ＤＣスパッタリング装置を用いて成膜し、上述の方法で得られたターゲット材を使用して、下記の条件でスパッタリング成膜を行い、厚さ約３０ｎｍのチャネル層２０を成膜した。
　・成膜装置：ＤＣスパッタリング装置トッキ株式会社製ＳＭＬ－４６４
　・到達真空度：１×１０－４Ｐａ未満
　・スパッタガス：Ａｒ／Ｏ２混合ガス
　・スパッタガス圧：０．４Ｐａ
　・Ｏ２ガス濃度：以下の表１に示すとおり。
　・基材温度：室温
　・スパッタリング電力：３Ｗ／ｃｍ２
　次に、ゲート絶縁膜４０としてＳｉＯｘ薄膜を下記の条件で成膜した。
　・成膜装置：プラズマＣＶＤ装置サムコ株式会社製ＰＤ－２２０２Ｌ
　・成膜ガス：ＳｉＨ４／Ｎ２Ｏ／Ｎ２混合ガス
　・成膜圧力：１１０Ｐａ
　・基材温度：１５０℃
　次に、ゲート電極５０としてＭｏ薄膜を、前記ＤＣスパッタリング装置を用いて成膜した。
　保護層６０として、ＳｉＯｘ薄膜を、前記プラズマＣＶＤ装置を用いて成膜した。最後に、１５０℃でアニール処理を実施した。アニール処理の時間は６０分とした。このようにしてＦＥＴ１を製造した。
　得られたＦＥＴ１におけるチャネル層２０の組成がターゲット材の組成と同じであることを、Ｘ線光電子分光法（ＸＰＳ：Ｘ－ＲａｙＰｈｏｔｏｅｌｅｃｔｒｏｎ Ｓｐｅｃｔｒｏｓｃｏｐｙ）によって確認している（以下の実施例及び比較例についても同じである。）。ＸＰＳは、試料表面にＸ線を照射することで生じる光電子エネルギーを測定し、試料の構成元素と、その電子状態を分析できる測定方法である。したがって、表１に示す各元素の組成は、チャネル層２０とターゲット材とで同一である。 [Example 1]
In 2 O 3 powder, ZnO powder, and Ta 2 O 5 powder were prepared using target materials in which the atomic ratios of In, Zn, and Ta were as shown in Table 1 below. FET 1 shown in FIG. 1 was fabricated by photolithography.
In fabricating the FET 1, a polyethylene naphthalate film (Teonex (registered trademark) manufactured by Toyobo Co., Ltd.) (glass transition point: 155° C.) was used as the base material 10 . Mo thin films were formed on the base material 10 as the source electrode 30 and the drain electrode 31 using a DC sputtering apparatus, and using the target material obtained by the above method, sputtering film formation was performed under the following conditions. to form a channel layer 20 having a thickness of about 30 nm.
・Deposition device: DC sputtering device SML-464 manufactured by Tokki Co., Ltd.
・Ultimate vacuum: less than 1×10 −4 Pa ・Sputtering gas: Ar/O 2 mixed gas ・Sputtering gas pressure: 0.4 Pa
- O2 gas concentration: as shown in Table 1 below.
・Substrate temperature: room temperature ・Sputtering power: 3 W/cm 2
Next, a SiOx thin film was formed as the gate insulating film 40 under the following conditions.
・Deposition device: plasma CVD device PD-2202L manufactured by Samco Co., Ltd.
・Deposition gas: SiH 4 /N 2 O/N 2 mixed gas ・Deposition pressure: 110 Pa
・Substrate temperature: 150°C
Next, a Mo thin film was formed as the gate electrode 50 using the DC sputtering apparatus.
A SiOx thin film was deposited as the protective layer 60 using the plasma CVD apparatus. Finally, an annealing treatment was performed at 150°C. The annealing treatment time was 60 minutes. Thus, FET1 was manufactured.
It was confirmed by X-ray photoelectron spectroscopy (XPS) that the composition of the channel layer 20 in the obtained FET 1 was the same as that of the target material (also for the following examples and comparative examples). are the same.). XPS is a measuring method capable of measuring the photoelectron energy generated by irradiating the sample surface with X-rays and analyzing the constituent elements of the sample and their electronic states. Therefore, the composition of each element shown in Table 1 is the same between the channel layer 20 and the target material.
　　〔実施例２ないし１２及び比較例１ないし１５〕
　実施例１において、ＩｎとＺｎとＴａ、又はＩｎとＺｎとＮｂとの原子比が、以下の表１及び表２に示す値となるように各原料粉末を混合してターゲット材を製造した。また、スパッタリングを、以下の表１及び表２に示す条件で行った。これら以外は実施例１と同様にしてＦＥＴ１を得た。 [Examples 2 to 12 and Comparative Examples 1 to 15]
In Example 1, raw material powders were mixed so that the atomic ratios of In, Zn, and Ta or In, Zn, and Nb were the values shown in Tables 1 and 2 below to produce target materials. Sputtering was performed under the conditions shown in Tables 1 and 2 below. FET 1 was obtained in the same manner as in Example 1 except for these.
〔評価１〕
　実施例及び比較例で得られたターゲット材についてＳＥＭ観察を行い、以下の方法でＩｎ２Ｏ３相の結晶粒のサイズ及びＺｎ３Ｉｎ２Ｏ６相の結晶粒のサイズを測定した。それらの結果を以下の表１及び表２に示す。
　日立ハイテクノロジーズ製の走査型電子顕微鏡ＳＵ３５００を用いて、ターゲット材の表面をＳＥＭ観察するとともに、結晶の構成相や結晶形状の評価を行った。
　具体的には、ターゲット材を切断して得られた切断面を、エメリー紙＃１８０、＃４００、＃８００、＃１０００、＃２０００を用いて段階的に研磨し、最後にバフ研磨して鏡面に仕上げた。鏡面仕上げ面をＳＥＭ観察した。結晶形状の評価では、倍率１０００倍、８７．５μｍ×１２５μｍの範囲のＢＳＥ－ＣＯＭＰ像を無作為に１０視野撮影しＳＥＭ像を得た。
　得られたＳＥＭ像を、画像処理ソフトウェア：ＩｍａｇｅＪ　１．５１ｋ（ｈｔｔｐ：／／ｉｍａｇｅＪ．ｎｉｈ．ｇｏｖ／ｉｊ／、提供元：アメリカ国立衛生研究所（ＮＩＨ：Ｎａｔｉｏｎａｌ　Ｉｎｓｔｉｔｕｔｅｓ　ｏｆ　Ｈｅａｌｔｈ））によって解析した。具体的な手順は以下のとおりである。
　ＳＥＭ像撮影時に用いたサンプルを、１１００℃で１時間サーマルエッチングを施し、ＳＥＭ観察を行うことで図２に示す粒界が現れた画像を得た。得られた画像に対し、先ずＩｎ２Ｏ３相（図２中、白く見える領域Ａ）の粒界に沿って描画を行った。すべての描画が完了した後、粒子解析を実施（Ａｎａｌｙｚｅ→Ａｎａｌｙｚｅ　Ｐａｒｔｉｃｌｅｓ）して、各粒子における面積を得た。その後、得られた各粒子における面積から、面積円相当径を算出した。１０視野において算出された全粒子の面積円相当径の算術平均値を、Ｉｎ２Ｏ３相の結晶粒のサイズとした。続いてＺｎ３Ｉｎ２Ｏ６相の粒界に沿って描画を行い、同様に解析を施すことによって得られた各粒子における面積から、面積円相当径を算出した。１０視野において算出された全粒子の面積円相当径の算術平均値を、Ｚｎ３Ｉｎ２Ｏ６相の結晶粒のサイズとした。
　また、サーマルエッチング前の粒界のないＢＳＥ－ＣＯＭＰ像について、粒子解析を行うことで総面積におけるＩｎ２Ｏ３相の面積の比率を算出した。１０視野において算出された全粒子のそれらの算術平均値を、Ｉｎ２Ｏ３相面積率とした。また１００からＩｎ２Ｏ３相面積率を差し引くことで、Ｚｎ３Ｉｎ２Ｏ６相面積率を算出した。 [Evaluation 1]
The target materials obtained in Examples and Comparative Examples were observed with an SEM, and the crystal grain size of the In 2 O 3 phase and the crystal grain size of the Zn 3 In 2 O 6 phase were measured by the following method. The results are shown in Tables 1 and 2 below.
Using a scanning electron microscope SU3500 manufactured by Hitachi High-Technologies Corporation, the surface of the target material was observed by SEM, and the constituent phases and crystal shape of the crystal were evaluated.
Specifically, the cut surface obtained by cutting the target material is polished in stages using #180, #400, #800, #1000, and #2000 emery papers, and finally buffed to a mirror finish. Finished to The mirror-finished surface was observed by SEM. In the evaluation of the crystal shape, SEM images were obtained by randomly photographing 10 fields of BSE-COMP images in a range of 87.5 μm×125 μm at a magnification of 1000 times.
The obtained SEM image was analyzed by image processing software: ImageJ 1.51k (http://imageJ.nih.gov/ij/, provider: National Institutes of Health (NIH)). The specific procedure is as follows.
The sample used for taking the SEM image was subjected to thermal etching at 1100° C. for 1 hour and observed by SEM to obtain an image showing the grain boundaries shown in FIG. First, the obtained image was drawn along the grain boundaries of the In 2 O 3 phase (area A that looks white in FIG. 2). After all plots were completed, particle analysis was performed (Analyze→Analyze Particles) to obtain the area at each particle. After that, the equivalent circle diameter was calculated from the area of each particle obtained. The arithmetic average value of the area equivalent circle diameters of all particles calculated in 10 fields of view was taken as the size of the crystal grains of the In 2 O 3 phase. Subsequently, drawing was performed along the grain boundaries of the Zn 3 In 2 O 6 phase, and the equivalent circle diameter was calculated from the area of each grain obtained by performing the same analysis. The arithmetic average value of the equivalent circle diameters of all particles calculated in 10 fields of view was taken as the size of the crystal grains of the Zn 3 In 2 O 6 phase.
In addition, the ratio of the area of the In 2 O 3 phase to the total area was calculated by performing grain analysis on the BSE-COMP image without grain boundaries before thermal etching. The arithmetic mean value of all particles calculated in 10 fields of view was taken as the In 2 O 3 phase area ratio. By subtracting the In 2 O 3 phase area ratio from 100, the Zn 3 In 2 O 6 phase area ratio was calculated.
〔評価２〕
　実施例及び比較例で得られたＦＥＴ１について、ドレイン電圧Ｖｄ＝５Ｖでの伝達特性の測定を行った。測定した伝達特性は、電界効果移動度μ（ｃｍ２／Ｖｓ）、ＳＳ（Ｓｕｂｔｈｒｅｓｈｏｌｄ　Ｓｗｉｎｇ）値（Ｖ／ｄｅｃ）及びしきい電圧Ｖｔｈ（Ｖ）である。伝達特性は、Ａｇｉｌｅｎｔ　Ｔｅｃｈｎｏｌｏｇｉｅｓ株式会社製Ｓｅｍｉｃｏｎｄｕｃｔｏｒ　Ｄｅｖｉｃｅ　Ａｎａｌｙｚｅｒ　Ｂ１５００Ａによって測定した。測定結果を表１及び表２に示す。なお表に示していないが、各実施例で得られたＦＥＴ１のチャネル層２０がアモルファス構造であることをＸＲＤ測定によって本発明者は確認している。
　電界効果移動度とは、ＭＯＳＦＥＴ（Ｍｅｔａｌ－Ｏｘｉｄｅ－Ｓｅｍｉｃｏｎｄｕｃｔｏｒ　Ｆｉｅｌｄ－Ｅｆｆｅｃｔ　Ｔｒａｎｓｉｓｔｏｒ）動作の飽和領域において、ドレイン電圧を一定としたときのゲート電圧に対するドレイン電流の変化から求めたチャネル移動度のことであり、値が大きいほど伝達特性が良好である。
　ＳＳ値とは、しきい電圧近傍でドレイン電流を１桁上昇させるのに必要なゲート電圧のことであり、値が小さいほど伝達特性が良好である。
　しきい電圧とは、ドレイン電極に正電圧をかけ、ゲート電極に正負いずれかの電圧をかけたときにドレイン電流が流れ、１ｎＡとなった場合の電圧であり、値が０Ｖに近いことが好ましい。詳細には、－２Ｖ以上であることが更に好ましく、－１Ｖ以上であることが一層好ましく、０Ｖ以上であることが更に一層好ましい。また、３Ｖ以下であることが更に好ましく、２Ｖ以下であることが一層好ましく、１Ｖ以下であることが更に一層好ましい。具体的には、－２Ｖ以上３Ｖ以下であることが更に好ましく、－１Ｖ以上２Ｖ以下であることが一層好ましく、０Ｖ以上１Ｖ以下であることが更に一層好ましい。 [Evaluation 2]
For the FET1 obtained in the example and the comparative example, the transfer characteristics were measured at the drain voltage Vd=5V. The measured transfer characteristics are field effect mobility μ (cm 2 /Vs), SS (Subthreshold Swing) value (V/dec) and threshold voltage Vth (V). The transfer characteristics were measured with a Semiconductor Device Analyzer B1500A manufactured by Agilent Technologies. Tables 1 and 2 show the measurement results. Although not shown in the table, the present inventor confirmed by XRD measurement that the channel layer 20 of the FET 1 obtained in each example had an amorphous structure.
The field-effect mobility is the channel mobility obtained from the change in the drain current with respect to the gate voltage when the drain voltage is constant in the saturation region of the MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) operation. , the larger the value, the better the transfer characteristic.
The SS value is the gate voltage required to increase the drain current by one order of magnitude near the threshold voltage, and the smaller the value, the better the transfer characteristics.
The threshold voltage is the voltage when a positive voltage is applied to the drain electrode and either positive or negative voltage is applied to the gate electrode, and the drain current flows to 1 nA. The value is preferably close to 0V. . Specifically, it is more preferably −2 V or higher, even more preferably −1 V or higher, and even more preferably 0 V or higher. Further, it is more preferably 3 V or less, even more preferably 2 V or less, and even more preferably 1 V or less. Specifically, it is more preferably -2 V or more and 3 V or less, more preferably -1 V or more and 2 V or less, and even more preferably 0 V or more and 1 V or less.
Figure JPOXMLDOC01-appb-T000001
Figure JPOXMLDOC01-appb-T000001
Figure JPOXMLDOC01-appb-T000002
Figure JPOXMLDOC01-appb-T000002
　表１及び表２に示す結果から明らかなとおり、各実施例で得られたＦＥＴ１は、フレキシブル配線板に用いられる基材又は２５０℃以下のガラス転移点を有する基材上で優れた伝達特性を示していることが分かる。一方、比較例では電界効果移動度μ、しきい電圧Ｖｔｈ、ＳＳ値のいずれもが不良であり、良好な伝達特性が得られなかった。「不良」とは、チャネル層が導体化又は絶縁化してしまい、良好な伝達特性が得られず、電界効果トランジスタとして機能しなかったことを意味する。
　なお、表に示していないが、実施例のターゲット材においては、Ｉｎ２Ｏ３相及びＺｎ３Ｉｎ２Ｏ６相の双方に添加元素（Ｘ）が含まれることを、ＥＤＸ測定によって本発明者は確認している。 As is clear from the results shown in Tables 1 and 2, FET 1 obtained in each example exhibits excellent transfer characteristics on a substrate used for a flexible wiring board or a substrate having a glass transition point of 250°C or lower. I know it shows. On the other hand, in the comparative example, the field effect mobility μ, the threshold voltage Vth, and the SS value were all poor, and good transfer characteristics could not be obtained. The term "defective" means that the channel layer became conductive or insulating, resulting in poor transfer characteristics and failure to function as a field effect transistor.
Although not shown in the table, the present inventor confirmed by EDX measurement that the additive element (X) was contained in both the In 2 O 3 phase and the Zn 3 In 2 O 6 phase in the target material of the example. has confirmed.
　本発明によれば、耐熱性の低い基材上に形成されていながらも、高い電界効果移動度を有する電界効果トランジスタ及びその製造方法が提供される。また本発明によれば、そのような電界効果トランジスタの製造に好適なスパッタリングターゲット材が提供される。
　本発明に係るターゲット材を用いてスパッタリングを行うと、従来のターゲット材を用いた場合に比較して、スパッタリング後に低温でポストアニール処理しても、高い電界効果移動度を有することが可能であることから、十分な電界効果移動度を示さない不良品の発生を抑制することができ、延いては、廃棄物の発生を低減することができる。つまり、それら廃棄物の処分におけるエネルギーコストを削減することが可能となる。また低温でのポストアニール工程自体が製造時のエネルギーコストを低減することも可能としている。このことは天然資源の持続可能な管理及び効率的な利用、並びに脱炭素（カーボンニュートラル）化を達成することにつながる。 ADVANTAGE OF THE INVENTION According to this invention, the field effect transistor which has high field effect mobility, although it is formed on the base material with low heat resistance, and its manufacturing method are provided. Further, according to the present invention, a sputtering target material suitable for manufacturing such a field effect transistor is provided.
When sputtering is performed using the target material according to the present invention, it is possible to have a high field effect mobility even if post-annealing is performed at a low temperature after sputtering compared to the case of using a conventional target material. Therefore, it is possible to suppress the generation of defective products that do not exhibit sufficient field-effect mobility, and furthermore, it is possible to reduce the generation of waste. That is, it becomes possible to reduce the energy cost in disposing of those wastes. In addition, the low-temperature post-annealing process itself can reduce energy costs during manufacturing. This will lead to sustainable management and efficient use of natural resources, as well as achieving decarbonization (carbon neutrality).

Claims (20)

  1. 　２５０℃以下のガラス転移点を有する基材と、該基材上に設けられた酸化物半導体層とを備えた、電界効果トランジスタであって、
    　前記酸化物半導体層は、インジウム（Ｉｎ）元素、亜鉛（Ｚｎ）元素及び添加元素（Ｘ）を含む酸化物から構成され、
    　添加元素（Ｘ）はタンタル（Ｔａ）元素、ストロンチウム（Ｓｒ）元素及びニオブ（Ｎｂ）元素から選ばれる少なくとも１種の元素であり、
    　各元素の原子比が式（１）ないし（３）の全てを満たす電界効果トランジスタ（式中のＸは、前記添加元素の含有比の総和とする。）。
    　　　０．４≦（Ｉｎ＋Ｘ）／（Ｉｎ＋Ｚｎ＋Ｘ）≦０．８　（１）
    　　　０．２≦Ｚｎ／（Ｉｎ＋Ｚｎ＋Ｘ）≦０．６　　　　　（２）
    　　　０．００１≦Ｘ／（Ｉｎ＋Ｚｎ＋Ｘ）≦０．０１５　　（３）     A field effect transistor comprising a substrate having a glass transition point of 250° C. or less and an oxide semiconductor layer provided on the substrate,
    The oxide semiconductor layer is composed of an oxide containing an indium (In) element, a zinc (Zn) element and an additive element (X),
    The additive element (X) is at least one element selected from tantalum (Ta) element, strontium (Sr) element and niobium (Nb) element,
    A field effect transistor in which the atomic ratio of each element satisfies all of the formulas (1) to (3) (X in the formula is the sum of the content ratios of the additive elements).
    0.4≦(In+X)/(In+Zn+X)≦0.8 (1)
    0.2≦Zn/(In+Zn+X)≦0.6 (2)
    0.001≦X/(In+Zn+X)≦0.015 (3)
  2. 　フレキシブル配線板に用いられる基材と、該基材上に設けられた酸化物半導体層とを備えた、電界効果トランジスタであって、
    　前記酸化物半導体層は、インジウム（Ｉｎ）元素、亜鉛（Ｚｎ）元素及び添加元素（Ｘ）を含む酸化物から構成され、
    　添加元素（Ｘ）はタンタル（Ｔａ）元素、ストロンチウム（Ｓｒ）元素及びニオブ（Ｎｂ）元素から選ばれる少なくとも１種の元素であり、
    　各元素の原子比が式（１）ないし（３）の全てを満たす電界効果トランジスタ（式中のＸは、前記添加元素の含有比の総和とする。）。
    　　　０．４≦（Ｉｎ＋Ｘ）／（Ｉｎ＋Ｚｎ＋Ｘ）≦０．８　（１）
    　　　０．２≦Ｚｎ／（Ｉｎ＋Ｚｎ＋Ｘ）≦０．６　　　　　（２）
    　　　０．００１≦Ｘ／（Ｉｎ＋Ｚｎ＋Ｘ）≦０．０１５　　（３）     A field effect transistor comprising a substrate used in a flexible wiring board and an oxide semiconductor layer provided on the substrate,
    The oxide semiconductor layer is composed of an oxide containing an indium (In) element, a zinc (Zn) element and an additive element (X),
    The additive element (X) is at least one element selected from tantalum (Ta) element, strontium (Sr) element and niobium (Nb) element,
    A field effect transistor in which the atomic ratio of each element satisfies all of the formulas (1) to (3) (X in the formula is the sum of the content ratios of the additive elements).
    0.4≦(In+X)/(In+Zn+X)≦0.8 (1)
    0.2≦Zn/(In+Zn+X)≦0.6 (2)
    0.001≦X/(In+Zn+X)≦0.015 (3)
  3. 　前記添加元素（Ｘ）が、タンタル（Ｔａ）元素又はニオブ（Ｎｂ）元素である、請求項１又は２に記載の電界効果トランジスタ。 The field effect transistor according to claim 1 or 2, wherein the additive element (X) is a tantalum (Ta) element or a niobium (Nb) element.
  4. 　前記添加元素（Ｘ）が、タンタル（Ｔａ）元素である、請求項３に記載の電界効果トランジスタ。 The field effect transistor according to claim 3, wherein the additive element (X) is a tantalum (Ta) element.
  5. 　前記酸化物半導体層を構成する各元素の原子比が、式（４）を更に満たす、請求項１又は２に記載の電界効果トランジスタ。
    　　　０．９７０≦Ｉｎ／（Ｉｎ＋Ｘ）≦０．９９９　（４）     3. The field effect transistor according to claim 1, wherein the atomic ratio of each element constituting said oxide semiconductor layer further satisfies formula (4).
    0.970≦In/(In+X)≦0.999 (4)
  6. 　前記電界効果トランジスタの電界効果移動度が２０ｃｍ２／Ｖｓ以上である、請求項１又は２に記載の電界効果トランジスタ。 3. The field effect transistor according to claim 1, wherein said field effect transistor has a field effect mobility of 20 cm <2> /Vs or more.
  7. 　前記電界効果トランジスタの電界効果移動度が３０ｃｍ２／Ｖｓ以上である、請求項６に記載の電界効果トランジスタ。 7. The field effect transistor according to claim 6, wherein said field effect transistor has a field effect mobility of 30 cm <2> /Vs or more.
  8. 　前記電界効果トランジスタの電界効果移動度が５０ｃｍ２／Ｖｓ以上である、請求項７に記載の電界効果トランジスタ。 8. The field effect transistor according to claim 7, wherein said field effect transistor has a field effect mobility of 50 cm <2> /Vs or more.
  9. 　前記基材がポリエチレンナフタレート（ＰＥＮ）、ポリエチレンテレフタレート（ＰＥＴ）、ポリフェニレンスルファイド（ＰＰＳ）、ポリエーテルエーテルケトン（ＰＥＥＫ）、ポリスチレン（ＰＳ）、ポリエーテルサルフォン（ＰＥＳ）、ポリカーボネート（ＰＣ）、トリアセチルセルロース（ＴＡＣ）、シクロオレフィンポリマー（ＣＯＰ）である、請求項１又は２に記載の電界効果トランジスタ。 The base material is polyethylene naphthalate (PEN), polyethylene terephthalate (PET), polyphenylene sulfide (PPS), polyetheretherketone (PEEK), polystyrene (PS), polyethersulfone (PES), polycarbonate (PC), 3. The field effect transistor according to claim 1, which is triacetyl cellulose (TAC), cycloolefin polymer (COP).
  10. 　インジウム（Ｉｎ）元素、亜鉛（Ｚｎ）元素及び添加元素（Ｘ）を含む酸化物からなるスパッタリングターゲット材を用い（添加元素（Ｘ）はタンタル（Ｔａ）元素、ストロンチウム（Ｓｒ）元素及びニオブ（Ｎｂ）元素から選ばれる少なくとも１種の元素である。）、酸素濃度が２１ｖｏｌ％以上４９ｖｏｌ％以下である雰囲気下に、フレキシブル配線板に用いられる基材又は２５０℃以下のガラス転移点を有する基材に対してスパッタリングを行い、前記ターゲット材に由来する酸化物半導体を形成し、
    　前記酸化物半導体を５０℃以上２５０℃以下でアニール処理する、工程を有する電界効果トランジスタの製造方法。     Using a sputtering target material composed of an oxide containing indium (In) element, zinc (Zn) element and additive element (X) (additional element (X) is tantalum (Ta) element, strontium (Sr) element and niobium (Nb) ) is at least one element selected from elements.), a substrate used for a flexible wiring board or a substrate having a glass transition point of 250 ° C. or less in an atmosphere having an oxygen concentration of 21 vol% or more and 49 vol% or less to form an oxide semiconductor derived from the target material,
    A method of manufacturing a field effect transistor, comprising a step of annealing the oxide semiconductor at 50° C. or higher and 250° C. or lower.
  11. 　前記添加元素（Ｘ）が、タンタル（Ｔａ）元素又はニオブ（Ｎｂ）元素である、請求項１０に記載の製造方法。 The manufacturing method according to claim 10, wherein the additive element (X) is a tantalum (Ta) element or a niobium (Nb) element.
  12. 　前記添加元素（Ｘ）が、タンタル（Ｔａ）元素である、請求項１１に記載の製造方法。 The manufacturing method according to claim 11, wherein the additive element (X) is a tantalum (Ta) element.
  13. 　前記ターゲット材における各元素の原子比が式（１）ないし（３）の全てを満たす、請求項１０ないし１２のいずれか一項に記載の製造方法（式中のＸは、前記添加元素の含有比の総和とする。）。
    　　　０．４≦（Ｉｎ＋Ｘ）／（Ｉｎ＋Ｚｎ＋Ｘ）≦０．８　（１）
    　　　０．２≦Ｚｎ／（Ｉｎ＋Ｚｎ＋Ｘ）≦０．６　　　　　（２）
    　　　０．００１≦Ｘ／（Ｉｎ＋Ｚｎ＋Ｘ）≦０．０１５　　（３）     The manufacturing method according to any one of claims 10 to 12, wherein the atomic ratio of each element in the target material satisfies all of formulas (1) to (3) (X in the formula is the content of the additive element sum of ratios).
    0.4≦(In+X)/(In+Zn+X)≦0.8 (1)
    0.2≦Zn/(In+Zn+X)≦0.6 (2)
    0.001≦X/(In+Zn+X)≦0.015 (3)
  14. 　インジウム（Ｉｎ）元素、亜鉛（Ｚｎ）元素及び添加元素（Ｘ）を含む酸化物から構成され、
    　添加元素（Ｘ）はタンタル（Ｔａ）元素、ストロンチウム（Ｓｒ）元素及びニオブ（Ｎｂ）元素から選ばれる少なくとも１種の元素であり、
    　各元素の原子比が式（１）ないし（３）の全てを満たすスパッタリングターゲット材であって、
    　フレキシブル配線板に用いられる基材又は２５０℃以下のガラス転移点を有する基材上に設けられ且つ前記スパッタリングターゲット材に由来する酸化物半導体層、を備えた電界効果トランジスタの製造用スパッタリングターゲット材。
    　　　０．４≦（Ｉｎ＋Ｘ）／（Ｉｎ＋Ｚｎ＋Ｘ）≦０．８　（１）
    　　　０．２≦Ｚｎ／（Ｉｎ＋Ｚｎ＋Ｘ）≦０．６　　　　　（２）
    　　　０．００１≦Ｘ／（Ｉｎ＋Ｚｎ＋Ｘ）≦０．０１５　　（３）     Consists of an oxide containing an indium (In) element, a zinc (Zn) element and an additive element (X),
    The additive element (X) is at least one element selected from tantalum (Ta) element, strontium (Sr) element and niobium (Nb) element,
    A sputtering target material in which the atomic ratio of each element satisfies all of formulas (1) to (3),
    A sputtering target material for producing a field effect transistor, comprising: a base material used for a flexible wiring board or a base material having a glass transition point of 250° C. or lower and an oxide semiconductor layer derived from the sputtering target material.
    0.4≦(In+X)/(In+Zn+X)≦0.8 (1)
    0.2≦Zn/(In+Zn+X)≦0.6 (2)
    0.001≦X/(In+Zn+X)≦0.015 (3)
  15. 　前記添加元素（Ｘ）が、タンタル（Ｔａ）元素又はニオブ（Ｎｂ）元素である、請求項１４に記載のスパッタリングターゲット材。 The sputtering target material according to claim 14, wherein the additive element (X) is a tantalum (Ta) element or a niobium (Nb) element.
  16. 　前記添加元素（Ｘ）が、タンタル（Ｔａ）元素である、請求項１５に記載のスパッタリングターゲット材。 The sputtering target material according to claim 15, wherein the additive element (X) is a tantalum (Ta) element.
  17. 　前記電界効果トランジスタの製造用スパッタリングターゲット材がＩｎ２Ｏ３相及びＺｎ３Ｉｎ２Ｏ６相を含む、請求項１４ないし１６のいずれか一項に記載の電界効果トランジスタの製造用スパッタリングターゲット材。 The sputtering target material for manufacturing a field effect transistor according to any one of claims 14 to 16, wherein the sputtering target material for manufacturing a field effect transistor comprises an In2O3 phase and a Zn3In2O6 phase .
  18. 　Ｉｎ２Ｏ３相及びＺｎ３Ｉｎ２Ｏ６相の双方に添加元素（Ｘ）が含まれる、請求項１７に記載の電界効果トランジスタの製造用スパッタリングターゲット材。 18. The sputtering target material for producing a field effect transistor according to claim 17, wherein both the In2O3 phase and the Zn3In2O6 phase contain the additional element (X).
  19. 　Ｉｎ２Ｏ３相の結晶粒のサイズが０．１μｍ以上３．０μｍ以下であり、
    　Ｚｎ３Ｉｎ２Ｏ６相の結晶粒のサイズが０．１μｍ以上３．９μｍ以下である、請求項１７に記載の電界効果トランジスタの製造用スパッタリングターゲット材。     The crystal grain size of the In 2 O 3 phase is 0.1 μm or more and 3.0 μm or less,
    18. The sputtering target material for producing a field effect transistor according to claim 17, wherein the Zn3In2O6 phase has a crystal grain size of 0.1 [mu ] m or more and 3.9 [mu]m or less.
  20. 　請求項１又は２に記載の電界効果トランジスタを用いた半導体装置。 A semiconductor device using the field effect transistor according to claim 1 or 2.
PCT/JP2023/000903 2022-01-31 2023-01-16 Field effect transistor, method for producing same, and sputtering target for production of field effect transistor WO2023145497A1 (en)

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WO2012091126A1 (en) * 2010-12-28 2012-07-05 株式会社神戸製鋼所 Oxide for semiconductor layer of thin film transistor, sputtering target, and thin-film transistor
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