CN118056282A - Field effect transistor, method for manufacturing the same, and sputtering target for manufacturing the field effect transistor - Google Patents

Field effect transistor, method for manufacturing the same, and sputtering target for manufacturing the field effect transistor Download PDF

Info

Publication number
CN118056282A
CN118056282A CN202380013886.0A CN202380013886A CN118056282A CN 118056282 A CN118056282 A CN 118056282A CN 202380013886 A CN202380013886 A CN 202380013886A CN 118056282 A CN118056282 A CN 118056282A
Authority
CN
China
Prior art keywords
field effect
effect transistor
additive
substrate
oxide semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202380013886.0A
Other languages
Chinese (zh)
Inventor
德地成纪
寺村享祐
白仁田亮
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsui Mining and Smelting Co Ltd
Original Assignee
Mitsui Mining and Smelting Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsui Mining and Smelting Co Ltd filed Critical Mitsui Mining and Smelting Co Ltd
Publication of CN118056282A publication Critical patent/CN118056282A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
    • C23C14/06—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the coating material
    • C23C14/08—Oxides
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
    • C23C14/22—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the process of coating
    • C23C14/34—Sputtering
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
    • C23C14/22—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the process of coating
    • C23C14/34—Sputtering
    • C23C14/3407—Cathode assembly for sputtering apparatus, e.g. Target
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
    • H01L21/2003—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy characterised by the substrate
    • H01L21/2015—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy characterised by the substrate the substrate being of crystalline semiconductor material, e.g. lattice adaptation, heteroepitaxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66969—Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78603—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the insulating substrate or support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Chemical & Material Sciences (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Organic Chemistry (AREA)
  • Metallurgy (AREA)
  • Mechanical Engineering (AREA)
  • Materials Engineering (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Manufacturing & Machinery (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Physical Deposition Of Substances That Are Components Of Semiconductor Devices (AREA)
  • Thin Film Transistor (AREA)
  • Physical Vapour Deposition (AREA)

Abstract

The invention relates to a field effect transistor comprising: a substrate having a glass transition temperature of 250 ℃ or less; and an oxide semiconductor layer provided over the substrate. The oxide semiconductor layer is formed of an oxide containing indium (In) element, zinc (Zn) element, and additive element (X). The additive element (X) is at least one element selected from tantalum (Ta) element, strontium (Sr) element, and niobium (Nb) element. The atomic ratio of each element satisfies all of the formulas (1) to (3). (in+X)/(in+Zn+X) is more than or equal to 0.4 and less than or equal to 0.8 (1); zn/(in+Zn+X) is more than or equal to 0.2 and less than or equal to 0.6 (2); X/(In+Zn+X) is more than or equal to 0.001 and less than or equal to 0.015 (3).

Description

Field effect transistor, method for manufacturing the same, and sputtering target for manufacturing the field effect transistor
Technical Field
The invention relates to a field effect transistor and a manufacturing method thereof. The present invention also relates to a sputtering target for manufacturing a field effect transistor.
Background
In the field of thin film transistors (hereinafter also referred to as "TFTs") used In flat panel displays (hereinafter also referred to as "FPDs"), oxide semiconductors typified by In-Ga-Zn composite oxides (hereinafter also referred to as "IGZO") have been attracting attention and have been put to practical use In place of conventional amorphous silicon (hereinafter also referred to as "amorphous silicon") with the increase In functionality of FPDs. IGZO has the advantage of exhibiting high field effect mobility and low leakage current. In recent years, with the development of higher functionalization of FPDs, materials exhibiting higher field effect mobility than that shown by IGZO have been proposed.
A flexible display, which is one of the FPDs, has been attracting attention in recent years because of its functions such as thinness, lightness, and softness, and thus has been widely used. In particular, flexible organic EL displays (OLEDs) using organic EL as display elements are suitable for flexible displays in principle because no backlight is required.
One of important members constituting a flexible display is a substrate having flexibility. As a base material used for a flexible display, a plastic film of polyethylene terephthalate, polyethylene naphthalate, or the like is suitable because of its thinness, light weight, and excellent flexibility. However, plastic films have problems in heat resistance. In order to form a TFT on a substrate, post-annealing treatment is required to improve electrical characteristics after film formation, and as a result, when a substrate having low heat resistance such as a plastic film is used, post-annealing treatment at a low temperature is required. However, if a film made of IGZO is subjected to post-annealing treatment at a low temperature, the film becomes low in resistance, and becomes difficult to function as a semiconductor. Accordingly, patent document 1 proposes a technique for manufacturing an IGZO-based oxide semiconductor thin film, in which low resistance due to a post-annealing treatment at a low temperature does not occur.
Prior art literature
Patent literature
Patent document 1: japanese patent application laid-open No. 2012-049209
Disclosure of Invention
According to the technique described in patent document 1, even if the post-annealing treatment is performed at a low temperature, the IGZO thin film can be prevented from becoming low in resistance, but the thin film after the post-annealing treatment is insufficient for use as a semiconductor for driving the OLED described above because of its low field effect mobility.
Accordingly, an object of the present invention is to provide a field effect transistor and a method for manufacturing the same, which can eliminate various drawbacks of the prior art.
The present invention provides a field effect transistor, comprising: a substrate having a glass transition temperature of 250 ℃ or less or a substrate for a flexible wiring board; and an oxide semiconductor layer provided over the substrate, wherein the oxide semiconductor layer is formed of an oxide containing indium (In) element, zinc (Zn) element, and an additive element (X) which is at least one element selected from tantalum (Ta) element, strontium (Sr) element, and niobium (Nb) element, and an atomic ratio of each element satisfies all of formulas (1) to (3) (X In the formulas is set as a sum of the content ratios of the additive elements).
0.4≤(In+X)/(In+Zn+X)≤0.8 (1)
0.2≤Zn/(In+Zn+X)≤0.6 (2)
0.001≤X/(In+Zn+X)≤0.015 (3)
The present invention also provides a method for manufacturing a field effect transistor, comprising: using a sputtering target material formed of an oxide containing indium (In) element, zinc (Zn) element, and an additive element (X) which is at least one element selected from tantalum (Ta) element, strontium (Sr) element, and niobium (Nb) element, sputtering a substrate for a flexible wiring board or a substrate having a glass transition temperature of 250 ℃ or less In an atmosphere having an oxygen concentration of 21 to 49% by volume, forming an oxide semiconductor from the target material, and annealing the oxide semiconductor at 50 to 250 ℃.
Further, the present invention provides a sputtering target for manufacturing a field effect transistor, which is formed of an oxide containing indium (In) element, zinc (Zn) element, and an additive element (X) which is at least one element selected from tantalum (Ta) element, strontium (Sr) element, and niobium (Nb) element, and In which the atomic ratio of each element satisfies all of formulas (1) to (3), wherein the field effect transistor includes an oxide semiconductor layer provided on a substrate for a flexible wiring board or a substrate having a glass transition temperature of 250 ℃ or less and derived from the sputtering target.
0.4≤(In+X)/(In+Zn+X)≤0.8 (1)
0.2≤Zn/(In+Zn+X)≤0.6 (2)
0.001≤X/(In+Zn+X)≤0.015 (3)
Drawings
Fig. 1 is a schematic diagram showing the structure of a field effect transistor of the present invention.
Fig. 2 is a scanning electron microscope image of the target material obtained in example 1.
Detailed Description
Hereinafter, the present invention will be described based on preferred embodiments thereof. The present invention relates to a field effect transistor (hereinafter also referred to as "FET"). The FET of the present invention is constituted by a substrate and an oxide semiconductor layer provided on the substrate.
As described later, the FET of the present invention is preferably manufactured by a method including the steps of: forming an oxide semiconductor layer on a substrate by a sputtering method; and a step of post-annealing for improving the electrical characteristics after the oxide semiconductor layer is formed. In general, when post annealing is performed after forming an oxide semiconductor layer, the conventional oxide semiconductor layer must be processed at a high temperature, and therefore a substrate having low heat resistance is deformed or melted, and therefore cannot function as an element. However, according to the present invention, even when a material having insufficient heat resistance, for example, a material for a flexible wiring board or a material having a low glass transition temperature (for example, a material having a glass transition temperature of 250 ℃ or lower) is used as a base material, annealing can be performed at a relatively low temperature after forming a film by sputtering, and thus an oxide semiconductor layer can be formed.
One embodiment of the FET of the present invention is schematically shown in fig. 1. The FET having the structure shown in the drawing is an example of the embodiment of the present invention, and the FET of the present invention is not limited to the structure shown in the drawing.
The FET1 shown in the figure is formed on one side of a substrate 10. A channel layer 20, a source electrode 30, and a drain electrode 31 are arranged on one surface of the substrate 10, and a gate insulating film 40 is formed so as to cover them. A gate electrode 50 is disposed on the gate insulating film 40. A protective layer 60 is disposed at the uppermost portion. In the FET1 having this structure, for example, the channel layer 20 is formed of an oxide semiconductor layer. Therefore, the "oxide semiconductor layer provided over a substrate" in the present invention includes both of the following cases: (i) An oxide semiconductor layer is provided through one or more layers provided in contact with the surface of the substrate; and (ii) a case where the oxide semiconductor layer is provided in contact with the surface of the substrate.
The oxide semiconductor layer In the FET of the present invention (hereinafter, for convenience, the oxide semiconductor layer In the FET of the present invention is also referred to as "the oxide semiconductor layer of the present invention") is formed of an oxide containing indium (In) element, zinc (Zn) element, and an additive element (X). The additive element (X) is formed of at least one element selected from the group consisting of tantalum (Ta) element, strontium (Sr) element, and niobium (Nb) element. The oxide semiconductor layer of the present invention contains In, zn, and an additive element (X) as metal elements constituting the same, but trace elements may be intentionally or inevitably contained In addition to these elements within a range that does not impair the effects of the present invention. Examples of the trace elements include elements contained in an organic additive described later, and medium materials such as a ball mill mixed during the production of a target. Examples of the trace elements contained in the oxide semiconductor layer of the present invention include Fe, cr, ni, al, si, W, zr, na, mg, K, ca, ti, Y, ga, sn, ba, la, ce, pr, nd, pm, sm, eu, gd, tb, dy, ho, er, tm, yb, lu and Pb. The content of these is preferably 100 mass ppm (hereinafter also referred to as "ppm") or less, more preferably 80ppm or less, and still more preferably 50ppm or less, based on the total mass of the oxides containing In, zn, and X contained In the oxide semiconductor layer of the present invention. The total amount of these trace elements is preferably 500ppm or less, more preferably 300ppm or less, and still more preferably 100ppm or less. When the trace element is contained in the oxide semiconductor layer of the present invention, the total mass contains the trace element.
The oxide semiconductor layer of the present invention is preferably In a specific range of atomic ratios of In, zn, and X, which are metal elements constituting the oxide semiconductor layer, in terms of improving performance of the FET of the present invention.
Specifically, it is preferable that the atomic ratio represented by the following formula (1) be satisfied for In and X (X In the formula is the sum of the content ratios of the above-mentioned additional elements; the same applies to the following formulas (2) and (3)).
0.4≤(In+X)/(In+Zn+X)≤0.8 (1)
The Zn preferably satisfies an atomic ratio represented by the following formula (2).
0.2≤Zn/(In+Zn+X)≤0.6 (2)
Regarding X, it is preferable that the atomic ratio represented by the following formula (3) is satisfied.
0.001≤X/(In+Zn+X) ≤0.015 (3)
The FET of the present invention exhibits high field-effect mobility, low leakage current, and a threshold voltage close to 0V by the atomic ratio of In, zn, and X In the oxide semiconductor layer satisfying all of the above formulas (1) to (3). From the viewpoint of making these advantages more remarkable, regarding In and X, it is more preferable that the following formulas (1-2) to (1-6) are satisfied.
0.43≤(In+X)/(In+Zn+X)≤0.79 (1-2)
0.48≤(In+X)/(In+Zn+X)≤0.78 (1-3)
0.53≤(In+X)/(In+Zn+X)≤0.75 (1-4)
0.54≤(In+X)/(In+Zn+X)≤0.74 (1-5)
0.58≤(In+X)/(In+Zn+X)≤0.70 (1-6)
From the same viewpoints as described above, the formulae (2-2) to (2-6) below are more preferably satisfied for Zn, and the formulae (3-2) to (3-5) below are more preferably satisfied for X.
0.21≤Zn/(In+Zn+X)≤0.57 (2-2)
0.22≤Zn/(In+Zn+X)≤0.52 (2-3)
0.25≤Zn/(In+Zn+X)≤0.47 (2-4)
0.26≤Zn/(In+Zn+X)≤0.46 (2-5)
0.30≤Zn/(In+Zn+X)≤0.42 (2-6)
0.0015≤X/(In+Zn+X)≤0.013 (3-2)
0.002＜X/(In+Zn+X)≤0.012 (3-3)
0.0025≤X/(In+Zn+X)≤0.010 (3-4)
0.003≤X/(In+Zn+X)≤0.009 (3-5)
As described above, the additive element (X) is 1 or more selected from Ta, sr and Nb. These elements may be used each alone, or 2 or more kinds may be used in combination. From the viewpoint of the overall performance of the FET of the present invention and the economical point of view of the sputtering target used in producing the oxide semiconductor layer by sputtering, ta is particularly preferably used as the additive element (X).
Among these additional elements, from the viewpoint of sufficiently obtaining the desired effect of the present invention, it is preferable to use any one of Ta, sr and Nb, and it is particularly preferable to use only Ta or Nb, and it is particularly preferable to use only Ta. However, three of Ta, sr, and Nb may be used.
In the FET of the present invention, from the viewpoint of further improving the field-effect mobility of the oxide semiconductor element formed from the target of the present invention and the viewpoint of exhibiting a threshold voltage close to 0V, it is preferable that the atomic ratio of In to X satisfies the following formula (4) In addition to the relationships of (1) to (3) described above.
0.970≤In/(In+X)≤0.999 (4)
As is clear from the formula (4), in the FET of the present invention, the field effect mobility of the FET is improved by using a very small amount of X relative to the amount of In. This was first discovered by the inventors of the present invention.
From the standpoint of further improving the field effect mobility of the FET of the present invention and showing a threshold voltage close to 0V, the atomic ratio of In to X further preferably satisfies the following formulas (4-2) to (4-4).
0.980≤In/(In+X)≤0.997 (4-2)
0.990≤In/(In+X)≤0.995 (4-3)
0.990＜In/(In+X)≤0.993 (4-4)
The oxide semiconductor layer In the FET of the present invention preferably contains In, zn, additive element X, and oxygen, but may contain other elements, and the oxide semiconductor layer is preferably composed of In, zn, additive element X, and oxygen, and the remainder is formed of unavoidable impurities, from the viewpoint of further improving the field effect mobility of the FET.
The proportion of each metal contained in the oxide semiconductor layer of the present invention is measured by, for example, X-ray photoelectron spectroscopy (XPS: X-Ray Photoelectron Spectroscopy) or ICP emission spectrometry.
The fact that the FET of the present invention has a large value of field-effect mobility is preferable from the viewpoint of high functionality of the FPD due to the improvement of the transmission characteristics of the FET. In detail, the TFT of the present invention preferably has a field effect mobility (cm 2/Vs) of 20cm 2/Vs or more, more preferably 30cm 2/Vs or more, still more preferably 50cm 2/Vs or more, still more preferably 60cm 2/Vs or more, still more preferably 70cm 2/Vs or more, still more preferably 80cm 2/Vs or more, and particularly preferably 100cm 2/Vs or more. The larger the value of the field-effect mobility is, the more preferable from the viewpoint of high functionalization of the FPD, but if the field-effect mobility is as high as about 200cm 2/Vs, a sufficiently satisfactory degree of performance can be obtained.
The oxide semiconductor layer in the FET of the present invention preferably has an amorphous structure from the viewpoint of further improving the field-effect mobility.
The substrate in the FET of the present invention is made of a material for a flexible wiring board or a material having a glass transition temperature of 250 ℃ or less. The use of substrates made of these materials is advantageous in that the FETs of the present invention can be easily manufactured, for example, for flexible displays.
The material constituting the base material is preferably a resin base material, and examples thereof include one or more selected from polyester-based polymers, silicone-based polymers, acrylic-based polymers, polyolefin-based polymers, and copolymers thereof. In addition, these resin substrates are more preferably made of a material having a glass transition temperature of 250 ℃ or less. These materials, for example, take on the form of films.
Specific examples of the material constituting the base material include polyethylene naphthalate (PEN), polyethylene terephthalate (PET), polyphenylene sulfide (PPS), polyether ether ketone (PEEK), polystyrene (PS), polyether sulfone (PES), polycarbonate (PC), triacetyl cellulose (TAC), polybutylene terephthalate (PBT), polysilane (polysilane), polysiloxane (polysiloxane), polysilazane (polysilazane), polycarbosilane (polycarbosilane), polyacrylate (polyacrylate), polymethacrylate (polymethacrylate), polymethyl acrylate (polymethylacrylate), polyethyl acrylate (polyethylacrylate), polyethyl methacrylate (polyethylmetacrylate), cyclic Olefin Copolymer (COC), cyclic Olefin Polymer (COP), polyethylene (PE), polypropylene (PP), polymethyl methacrylate (PMMA), polyacetal (POM), polytetrafluoroethylene (PTFE), polyvinyl chloride (PVC), polyvinylidene fluoride (PVDF), perfluoroalkyl Polymer (PFA), and styrene-acrylonitrile copolymer (SAN). These materials may be used singly or two or more of them may be used in combination.
According to the present invention, by using a sputtering method using a target material described later for forming an oxide semiconductor layer over a substrate, an oxide semiconductor layer having high field effect mobility can be smoothly formed even with a substrate made of a material for a flexible wiring board, in other words, a material having insufficient heat resistance. From this viewpoint, as the substrate, a substrate made of a material having a glass transition temperature of preferably 250 ℃ or less, more preferably 200 ℃ or less, and still more preferably 180 ℃ or less can be used. On the other hand, from the viewpoint of minimum heat resistance maintenance in the annealing step, the glass transition temperature of the material constituting the base material is typically preferably 0 ℃ or higher, more preferably 25 ℃ or higher, still more preferably 80 ℃ or higher, still more preferably 85 ℃ or higher, still more preferably 90 ℃ or higher. The method for measuring the glass transition temperature of the substrate is as follows.
[ Measurement of glass transition temperature ]
In the present invention, the glass transition temperature is determined by the DTA method in accordance with JIS-K-7121-1987 (method for measuring the transition temperature of plastics). As a measurement device, typically, the intermediate point glass transition temperature is measured using STA 2500Regulus manufactured by NETZSCH corporation.
The substrate in the FET of the present invention preferably has a thickness of 1 μm to 500 μm, more preferably 1 μm to 300 μm, and even more preferably 1 μm to 100 μm, from the viewpoint of improving flexibility.
From the same viewpoint, the substrate in the FET of the present invention preferably has a thermal expansion coefficient of 5 ppm/DEG C to 80 ppm/DEG C, more preferably 5 ppm/DEG C to 50 ppm/DEG C, and still more preferably 5 ppm/DEG C to 20 ppm/DEG C.
According to the present invention, there is also provided a semiconductor device including the FET of the present invention. In the present specification, the semiconductor device refers to all devices that can function by utilizing semiconductor characteristics, and for example, all of an electro-optical device, a semiconductor circuit, and an electronic apparatus are semiconductor devices. In particular, the semiconductor device of the present invention is useful as a thin film transistor used for an FPD.
Next, a preferred method of manufacturing the FET of the present invention will be described. The FET of the present invention can be manufactured by a known photolithography method, and particularly in the case of manufacturing the oxide semiconductor layer of the present invention, sputtering can be performed under the following conditions using a sputtering target material described later.
As the sputtering method, for example, a DC sputtering method can be used.
The temperature of the substrate during sputtering can be set to, for example, 10 to 250 ℃. In addition, sputtering may be performed at a substrate temperature not exceeding the glass transition temperature of the substrate.
The reaching vacuum degree at the time of sputtering may be set to be lower than 0.001Pa, for example.
As the sputtering gas (atmosphere), for example, a mixed gas of Ar and O 2 can be used. In this case, the O 2 gas concentration in the sputtering gas may be set to 21 to 49% by volume, particularly 22 to 45% by volume. By setting the O 2 gas concentration to this range, the sputtered layer can be smoothly semiconductorized.
The sputtering gas pressure can be set to, for example, 0.1Pa to 3Pa.
The sputtering power can be set to 0.1W/cm 2～10W/cm2, for example.
By performing sputtering under the above conditions, an oxide semiconductor layer can be smoothly manufactured over a substrate made of a material having insufficient heat resistance.
Preferably, after the oxide semiconductor layer is formed by a sputtering method, the oxide semiconductor layer is annealed. The purpose of the annealing treatment is to impart desired properties to the oxide semiconductor layer. For this purpose, the temperature of the annealing treatment is preferably 50 to 250 ℃, more preferably 80 to 200 ℃, still more preferably 100 to 180 ℃, still more preferably 100 to 150 ℃. The annealing treatment time is preferably 1 to 180 minutes, more preferably 2 to 120 minutes, and still more preferably 3 to 60 minutes. The annealing atmosphere is preferably an oxygen atmosphere containing atmospheric pressure or the like.
The annealing treatment for the oxide semiconductor layer may be performed immediately after the oxide semiconductor layer is formed. Alternatively, one or more additional layers may be further formed after the oxide semiconductor layer is formed, and then annealing treatment may be performed.
In the case of manufacturing the oxide semiconductor layer of the present invention by a sputtering method, theoretically, the composition of a target for sputtering is reflected in the composition of the oxide semiconductor layer as it is. Namely, an oxide semiconductor layer derived from the target is formed. Therefore, in order to form the oxide semiconductor layer of the present invention having the above-described composition, a sputtering target formed of an oxide containing indium (In) element, zinc (Zn) element, and an additive element (X) (the additive element (X) is at least one element selected from tantalum (Ta) element, strontium (Sr) element, and niobium (Nb) element) may be used. That is, the sputtering target is suitably used in the manufacture of FETs including an oxide semiconductor layer which is provided on a substrate for a flexible wiring board or a substrate having a glass transition temperature of 250 ℃ or less and is derived from the sputtering target. In the following description, a sputtering target for FET fabrication is also referred to as "target of the present invention" as a matter of convenience.
Specifically, a sputtering target for FET production (in the formula, X is set to the sum of the content ratios of the above-described additional elements) is used as long as the atomic ratios of the elements satisfy all of the following formulas (1) to (3).
0.4≤(In+X)/(In+Zn+X)≤0.8 (1)
0.2≤Zn/(In+Zn+X)≤0.6 (2)
0.001≤X/(In+Zn+X)≤0.015 (3)
The sputtering target for FET production preferably satisfies the formula (4) in terms of atomic ratio of each element constituting the target.
0.970≤In/(In+X)≤0.999 (4)
The preferable ranges of the above-mentioned formulas (1) to (4) are the same as those described for the oxide semiconductor layer of the present invention, namely formulas (1-2) to (4-4).
The target of the present invention is formed of an oxide containing In, zn, and X as described above. The oxide may be an oxide of In, an oxide of Zn or an oxide of X. Or the oxide may be a composite oxide of any 2 or more elements selected from In, zn, and X. Specific examples of the composite oxide include, but are not limited to, in-Zn composite oxide, zn-Ta composite oxide, in-Nb composite oxide, zn-Nb composite oxide, in-Sr composite oxide, zn-Sr composite oxide, in-Zn-Ta composite oxide, in-Zn-Nb composite oxide, in-Zn-Sr composite oxide, and the like.
The target of the present invention particularly preferably contains an In 2O3 phase as an oxide of In and a Zn 3In2O6 phase as a composite oxide of In and Zn from the viewpoint of increasing the density and strength of the target and reducing the resistance. The target of the present invention can be judged by the following means that the target contains In 2O3 phase and Zn 3In2O6 phase: whether or not In 2O3 phase and Zn 3In2O6 phase are observable is determined by X-ray diffraction (hereinafter also referred to as "XRD") of the target material of the present invention. In 2O3 phase In the present invention may contain a trace amount of Zn element.
Specifically, in the XRD measurement using cukα rays as the X-ray source, the In 2O3 phase was observed as a main peak In the range of 2θ=30.38 ° to 30.78 °. The Zn 3In2O6 phase was observed as a main peak in the range 2θ=34.00° to 34.40 °.
Further, in the target material of the present invention, it is preferable that both In 2O3 phase and Zn 3In2O6 phase contain an additive element (X). In particular, if the additive element (X) is uniformly dispersed and contained in the entire target, the additive element (X) is uniformly contained in the oxide semiconductor formed from the target of the present invention, and a uniform oxide semiconductor film can be obtained. The inclusion of the additive element (X) In both the In 2O3 phase and the Zn 3In2O6 phase can be measured by, for example, an energy dispersive X-ray spectrometry (hereinafter also referred to as "EDX") or the like.
In the case where In 2O3 phase is observed In the target of the present invention by XRD measurement, in 2O3 phase preferably has a grain size satisfying a specific range from the viewpoint of increasing the density and strength of the target of the present invention and reducing the resistance. Specifically, the grain size of the In 2O3 phase is preferably 3.0 μm or less, more preferably 2.7 μm or less, and even more preferably 2.5 μm or less. The smaller the crystal grain size, the more preferable, the lower limit is not particularly limited, but is usually 0.1 μm or more.
When the Zn 3In2O6 phase is observed in the target of the present invention by XRD measurement, it is preferable that the size of crystal grains of the Zn 3In2O6 phase satisfies a specific range from the viewpoints of increasing the density and strength of the target of the present invention and reducing the electric resistance. Specifically, the size of the crystal grains of the Zn 3In2O6 phase is preferably 3.9 μm or less, more preferably 3.5 μm or less, still more preferably 3.0 μm or less, still more preferably 2.5 μm or less, still more preferably 2.3 μm or less, particularly preferably 2.0 μm or less, and particularly preferably 1.9 μm or less. The smaller the crystal grain size, the more preferable, the lower limit is not particularly limited, but is usually 0.1 μm or more.
In order to set the grain size of the In 2O3 phase and the grain size of the Zn 3In2O6 phase within the above-described ranges, a target material may be manufactured by a method described later, for example.
The size of the crystal grains of the In 2O3 phase and the size of the crystal grains of the Zn 3In2O6 phase were measured by observing the target of the present invention by a scanning electron microscope (hereinafter also referred to as "SEM"). Specific measurement methods will be described in detail in examples described later.
The target of the present invention may contain other elements In addition to In, zn, the additive element X, and oxygen, but from the viewpoint of further improving the field effect mobility of the FET fabricated using the target, the target preferably contains In, zn, the additive element X, and oxygen, and the remainder is formed of unavoidable impurities.
Next, a preferred method for producing the target of the present invention will be described. In the present manufacturing method, an oxide powder that is a raw material of a target is formed into a predetermined shape to obtain a compact, and the compact is fired to obtain a target formed of a sintered body. For obtaining the shaped body, methods known to date in the art, such as cast molding, can be employed. In particular, CIP molding is preferably used in order to manufacture a dense target.
In the CIP molding method, the same slurry as that used in the casting molding method is spray-dried to obtain a dry powder. The obtained dry powder was filled into a mold to perform CIP molding.
After the molded article is obtained in this way, it is then fired. The firing of the molded article can be generally performed in an oxygen-containing atmosphere. In particular, it is convenient to perform the firing in an air atmosphere. The firing temperature is preferably 1200 to 1600 ℃, more preferably 1300 to 1500 ℃, still more preferably 1350 to 1450 ℃. The firing time is preferably 1 to 100 hours, more preferably 2 to 50 hours, and still more preferably 3 to 30 hours. The heating rate is preferably 5 to 500 ℃/hr, more preferably 10 to 200 ℃/hr, still more preferably 20 to 100 ℃/hr.
In the firing of the compact, it is preferable to maintain the temperature of the phase at which the composite oxide of In and Zn, for example Zn 5In2O8, is formed for a certain period of time during the firing, from the viewpoint of promoting the firing and the formation of a dense target. Specifically, when In 2O3 powder and ZnO powder are contained In the raw material powder, the raw material powder reacts with the temperature rise to form a Zn 5In2O8 phase, which is then converted into a Zn 4In2O7 phase and into a Zn 3In2O6 phase. In particular, from the viewpoint of promoting densification by the progress of volume diffusion in the formation of the Zn 5In2O8 phase, it is preferable to reliably form the Zn 5In2O8 phase. From such a viewpoint, the temperature is preferably maintained in the range of 1000 to 1250 ℃ for a certain period of time, and more preferably in the range of 1050 to 1200 ℃ for a certain period of time during the firing temperature increase. The temperature to be maintained is not necessarily limited to a specific point, and may be a temperature range having a certain magnitude. Specifically, when a specific temperature selected from the range of 1000 to 1250 ℃ is set to T (°c), the temperature may be, for example, t±10 ℃, preferably t±5 ℃, more preferably t±3 ℃, and even more preferably t±1 ℃ as long as the temperature is included in the range of 1000 to 1250 ℃. The time for maintaining this temperature range is preferably 1 to 40 hours, more preferably 2 to 20 hours.
The target material thus obtained can be processed into a predetermined size by grinding or the like. By bonding this to a substrate, a sputtering target is obtained. The shape of the target is not particularly limited, and conventionally known shapes, for example, flat plate shape, cylindrical shape, and the like can be used.
The present invention has been described above based on preferred embodiments thereof, but the present invention is not limited to the above embodiments.
In the above embodiments, the present invention further discloses the following field effect transistor, a method for manufacturing the same, and a sputtering target for manufacturing the field effect transistor.
[1] A field effect transistor, comprising: a substrate having a glass transition temperature of 250 ℃ or less; and an oxide semiconductor layer provided over the substrate, wherein the oxide semiconductor layer is formed of an oxide containing indium (In) element, zinc (Zn) element, and an additive element (X) which is at least one element selected from tantalum (Ta) element, strontium (Sr) element, and niobium (Nb) element, and an atomic ratio of each element satisfies all of formulas (1) to (3) (X In the formulas is set as a sum of the content ratios of the additive elements).
0.4≤(In+X)/(In+Zn+X)≤0.8 (1)
0.2≤Zn/(In+Zn+X)≤0.6 (2)
0.001≤X/(In+Zn+X)≤0.015 (3)
[2] A field effect transistor, comprising: a substrate for a flexible wiring board; and an oxide semiconductor layer provided over the substrate, wherein the oxide semiconductor layer is formed of an oxide containing indium (In) element, zinc (Zn) element, and an additive element (X) which is at least one element selected from tantalum (Ta) element, strontium (Sr) element, and niobium (Nb) element, and an atomic ratio of each element satisfies all of formulas (1) to (3) (X In the formulas is set as a sum of the content ratios of the additive elements).
0.4≤(In+X)/(In+Zn+X)≤0.8 (1)
0.2≤Zn/(In+Zn+X)≤0.6 (2)
0.001≤X/(In+Zn+X)≤0.015 (3)
[3] The field effect transistor according to [1] or [2], wherein the additive element (X) is tantalum (Ta) element or niobium (Nb) element.
[4] The field effect transistor according to [3], wherein the additive element (X) is a tantalum (Ta) element.
[5] The field-effect transistor according to any one of [1] to [4], wherein an atomic ratio of each element constituting the oxide semiconductor layer also satisfies formula (4).
0.970≤In/(In+X)≤0.999 (4)
[6] The field-effect transistor according to any one of [1] to [5], wherein a field-effect mobility of the field-effect transistor is 20cm 2/Vs or more.
[7] The field effect transistor according to [6], wherein a field effect mobility of the field effect transistor is 30cm 2/Vs or more.
[8] The field effect transistor according to [7], wherein a field effect mobility of the field effect transistor is 50cm 2/Vs or more.
[9] The field-effect transistor according to any one of [1] to [8], wherein the base material is polyethylene naphthalate (PEN), polyethylene terephthalate (PET), polyphenylene sulfide (PPS), polyether ether ketone (PEEK), polystyrene (PS), polyether sulfone (PES), polycarbonate (PC), triacetyl cellulose (TAC), cyclic Olefin Polymer (COP).
[10] A method for manufacturing a field effect transistor includes the steps of: using a sputtering target material formed of an oxide containing indium (In) element, zinc (Zn) element, and an additive element (X) which is at least one element selected from tantalum (Ta) element, strontium (Sr) element, and niobium (Nb) element, sputtering a substrate for a flexible wiring board or a substrate having a glass transition temperature of 250 ℃ or less In an atmosphere having an oxygen concentration of 21 to 49% by volume, forming an oxide semiconductor from the target material, and annealing the oxide semiconductor at 50 to 250 ℃.
[11] The production method according to [10], wherein the additive element (X) is tantalum (Ta) or niobium (Nb).
[12] The production method according to [11], wherein the additive element (X) is a tantalum (Ta) element.
[13] The production method according to any one of [10] to [12], wherein an atomic ratio of each element in the target satisfies all of formulas (1) to (3) (X in the formulas is a sum of the content ratios of the additive elements).
0.4≤(In+X)/(In+Zn+X)≤0.8 (1)
0.2≤Zn/(In+Zn+X)≤0.6 (2)
0.001≤X/(In+Zn+X)≤0.015 (3)
[14] A sputtering target for manufacturing a field effect transistor, which is formed of an oxide containing indium (In) element, zinc (Zn) element, and an additive element (X) which is at least one element selected from tantalum (Ta) element, strontium (Sr) element, and niobium (Nb) element, wherein the atomic ratio of each element satisfies all of formulas (1) to (3), wherein the field effect transistor includes an oxide semiconductor layer provided on a substrate for a flexible wiring board or a substrate having a glass transition temperature of 250 ℃ or less and derived from the sputtering target.
0.4≤(In+X)/(In+Zn+X)≤0.8 (1)
0.2≤Zn/(In+Zn+X)≤0.6 (2)
0.001≤X/(In+Zn+X)≤0.015 (3)
[15] The sputtering target according to [14], wherein the additive element (X) is tantalum (Ta) or niobium (Nb).
[16] The sputtering target according to [15], wherein the additive element (X) is tantalum (Ta).
[17] The sputtering target for manufacturing a field effect transistor according to any one of [14] to [16], wherein the sputtering target for manufacturing a field effect transistor comprises an In 2O3 phase and a Zn 3In2O6 phase.
[18] The sputtering target for manufacturing a field effect transistor according to [17], wherein the additive element (X) is contained In both the In 2O3 phase and the Zn 3In2O6 phase.
[19] The sputtering target for manufacturing a field effect transistor according to [17] or [18], wherein the size of crystal grains of the In 2O3 phase is 0.1 μm to 3.0 μm and the size of crystal grains of the Zn 3In2O6 phase is 0.1 μm to 3.9 μm.
[20] A semiconductor device using the field effect transistor described in any one of [1] to [9 ].
Examples
The present invention will be described in more detail with reference to examples. The scope of the invention is not limited by this example.
Example 1
The FET1 shown In fig. 1 was produced by photolithography using a target material In which the atomic ratios of In, zn, and Ta of In 2O3 powder, znO powder, and Ta 2O5 powder were set to values shown In table 1 below.
In the production of the FET1, a polyethylene naphthalate film (Teonex (registered trademark) manufactured by Toyo Kabushiki Kaisha) was used as the base material 10 (glass transition temperature: 155 ℃ C.). A Mo thin film was formed on the substrate 10 as the source electrode 30 and the drain electrode 31 by using a DC sputtering apparatus, and a channel layer 20 having a thickness of about 30nm was formed by performing sputtering film formation under the following conditions using the target material obtained by the above method.
Film forming apparatus: SML-464 manufactured by DC sputtering apparatus Tokki Co., ltd
Reach vacuum: below 1X 10 -4 Pa
Sputtering gas: ar/O 2 mixed gas
Sputtering gas pressure: 0.4Pa
O 2 gas concentration: as shown in table 1 below.
Substrate temperature: room temperature
Sputtering power: 3W/cm 2
Next, as the gate insulating film 40, a SiOx thin film was formed under the following conditions.
Film forming apparatus: PD-2202L manufactured by Samco Co., ltd
Film forming gas: siH 4/N2O/N2 mixed gas
Film formation pressure: 110Pa
Substrate temperature: 150 DEG C
Next, as the gate electrode 50, a Mo thin film was formed using the DC sputtering apparatus described above.
As the protective layer 60, a SiOx thin film was formed using the above-described plasma CVD apparatus. Finally, an annealing treatment was performed at 150 ℃. The time of the annealing treatment was set to 60 minutes. The FET1 is manufactured in this way.
The composition of the channel layer 20 in the obtained FET1 was confirmed to be the same as that of the target material (the same applies to the following examples and comparative examples) by X-ray photoelectron spectroscopy (XPS: X-Ray Photoelectron Spectroscopy). XPS is the following measurement method: the photoelectron energy generated by irradiating the surface of the sample with X-rays is measured, and the constituent elements and the electronic state of the sample can be analyzed. Accordingly, the composition of each element shown in table 1 is the same in the channel layer 20 and the target.
Examples 2 to 12 and comparative examples 1 to 15
In example 1, the respective raw material powders were mixed so that the atomic ratios of In, zn and Ta or In, zn and Nb became the values shown In table 1 and table 2 below, and a target material was produced. Sputtering was performed under the conditions shown in tables 1 and 2 below. Except for this, FET1 was obtained in the same manner as in example 1.
[ Evaluation 1]
The targets obtained In examples and comparative examples were subjected to SEM observation, and the sizes of the crystal grains of In 2O3 phase and the crystal grains of Zn 3In2O6 phase were measured by the following methods. The results are shown in tables 1 and 2 below.
SEM observation was performed on the surface of the target material using a scanning electron microscope SU3500 manufactured by hitachi high technology, and at the same time, the structural phase and crystal shape of the crystal were evaluated.
Specifically, the cut surface obtained by cutting the target material is polished in stages using sandpaper #180, #400, #800, #1000, and #2000, and finally polished to finish the cut surface to a mirror surface. SEM observation was performed on the mirror finished surface. In the evaluation of the crystal shape, BSE-COMP images were randomly taken in a range of 1000 times magnification and 87.5 μm×125 μm for 10 fields of view, and SEM images were obtained.
For the obtained SEM image, image processing software was used: imageJ 1.51k (http:// ImageJ.nih.gov/ij/, provider: national institute of health (NIH: national Institutes of Health)) was analyzed. The specific steps are as follows.
SEM observation was performed by performing thermal etching at 1100 ℃ for 1 hour on a sample used at the time of SEM image photographing, thereby obtaining an image showing grain boundaries as shown in fig. 2. The resulting image was first depicted along the grain boundaries of the In 2O3 phase (area a that appears white In fig. 2). After all the drawing was completed, particle analysis (analysis→ Analyze Particles) was performed to obtain the area of each particle. Then, from the area of each particle obtained, the area equivalent circle diameter was calculated. The arithmetic average of the area equivalent diameter of all particles calculated In 10 fields of view was taken as the size of the crystal grains of the In 2O3 phase. Next, drawing was performed along the grain boundary of Zn 3In2O6 phase, and the area equivalent diameter was calculated from the area of each particle obtained by the same analysis. The arithmetic average of the area equivalent diameter of all particles calculated in 10 fields was taken as the size of the crystal grains of Zn 3In2O6 phase.
In addition, for the BSE-COMP image without grain boundary before thermal etching, the ratio of the area of In 2O3 phase In the total area was calculated by performing particle analysis. These arithmetic averages of all particles calculated In 10 fields of view were taken as the In 2O3 phase area ratio. The In 2O3 phase area ratio was subtracted from 100 to calculate the Zn 3In2O6 phase area ratio.
[ Evaluation 2]
For the FET1 obtained in the examples and comparative examples, the transmission characteristics at the drain voltage vd=5v were measured. The measured transmission characteristics are field effect mobility μ (cm 2/Vs), SS (subthreshold swing; subthreshold Swing) value (V/dec) and threshold voltage Vth (V). The transmission characteristics were measured by using a semiconductor device analyzer (Semiconductor Device Analyzer) B1500A manufactured by Agilent Technologies corporation. The measurement results are shown in tables 1 and 2. Although not shown in the table, the inventors of the present invention confirmed that the channel layer 20 of the FET1 obtained in each example had an amorphous structure by XRD measurement.
The field effect mobility is channel mobility obtained from a change in drain current with respect to a gate voltage when a drain voltage is constant in a saturation region in which a MOSFET (Metal-Oxide semiconductor field effect transistor; metal-Oxide-Semiconductor Field-Effect Transistor) operates, and the larger the value, the better the transmission characteristics.
The SS value is a gate voltage required to raise the leakage current by 1 bit around the threshold voltage, and the smaller the value, the better the transmission characteristics.
The threshold voltage is a voltage when a drain current flows to 1nA when a positive voltage is applied to the drain electrode and a positive or negative voltage is applied to the gate electrode, and is preferably approximately 0V. More specifically, it is more preferably-2V or more, still more preferably-1V or more, still more preferably 0V or more. Further, the voltage is more preferably 3V or less, still more preferably 2V or less, still more preferably 1V or less. Specifically, it is more preferably from-2V to 3V, still more preferably from-1V to 2V, and still more preferably from 0V to 1V.
TABLE 1
TABLE 2
As is clear from the results shown in tables 1 and 2, the FET1 obtained in each example exhibited excellent transmission characteristics on a substrate for a flexible wiring board or a substrate having a glass transition temperature of 250 ℃ or less. On the other hand, in the comparative example, the field-effect mobility μ, the threshold voltage Vth, and the SS value were all poor, and good transmission characteristics were not obtained. The term "defect" means that the channel layer is made conductive or insulating, and does not have good transfer characteristics, and does not function as a field effect transistor.
Although not shown in the table, the inventors of the present invention confirmed by EDX measurement that: in the target material of the example, the additive element (X) was contained In both the In 2O3 phase and the Zn 3In2O6 phase.
Industrial applicability
According to the present invention, a field effect transistor having high field effect mobility and formed on a substrate having low heat resistance and a method for manufacturing the same are provided. Further, according to the present invention, a sputtering target suitable for manufacturing such a field effect transistor is provided.
If sputtering is performed using the target of the present invention, the target can have a high field effect mobility even when post-annealing is performed at a low temperature after sputtering, and therefore, the occurrence of defective products that do not exhibit sufficient field effect mobility can be suppressed, or even the occurrence of waste can be reduced, as compared with the case where a conventional target is used. That is, the energy cost in disposing of these wastes can be reduced. In addition, the post-annealing process itself at low temperature can reduce the energy cost at the time of manufacture. This results in sustainable management and efficient utilization of natural resources and implementation of decarbonization (carbon neutralization).

Claims (20)

1. A field effect transistor, comprising: a substrate having a glass transition temperature of 250 ℃ or less; and an oxide semiconductor layer provided on the substrate,
Wherein the oxide semiconductor layer is formed of an oxide containing indium, i.e., in element, zinc, i.e., zn element, and additive element X,
The additive element X is at least one element selected from the group consisting of tantalum, namely Ta element, strontium, namely Sr element, and niobium, namely Nb element,
The atomic ratio of each element satisfies all of the formulas (1) to (3), wherein X is set as the sum of the content ratios of the additive elements,
0.4≤(In+X)/(In+Zn+X)≤0.8 (1)
0.2≤Zn/(In+Zn+X)≤0.6 (2)
0.001≤X/(In+Zn+X)≤0.015 (3)。
2. A field effect transistor, comprising: a substrate for a flexible wiring board; and an oxide semiconductor layer provided on the substrate,
Wherein the oxide semiconductor layer is formed of an oxide containing indium, i.e., in element, zinc, i.e., zn element, and additive element X,
The additive element (X) is at least one element selected from the group consisting of Ta element, sr element and Nb element,
The atomic ratio of each element satisfies all of the formulas (1) to (3), wherein X is set as the sum of the content ratios of the additive elements,
0.4≤(In+X)/(In+Zn+X)≤0.8 (1)
0.2≤Zn/(In+Zn+X)≤0.6 (2)
0.001≤X/(In+Zn+X)≤0.015 (3)。
3. The field effect transistor according to claim 1 or 2, wherein the additive element X is tantalum or niobium or Nb element.
4. A field effect transistor according to claim 3 wherein the additive element X is tantalum, ta.
5. The field-effect transistor according to claim 1 or 2, wherein an atomic ratio of each element constituting the oxide semiconductor layer also satisfies formula (4),
0.970≤In/(In+X)≤0.999 (4)。
6. The field effect transistor according to claim 1 or 2, wherein the field effect mobility of the field effect transistor is 20cm 2/Vs or more.
7. The field effect transistor of claim 6, wherein the field effect transistor has a field effect mobility of 30cm 2/Vs or more.
8. The field effect transistor of claim 7, wherein the field effect transistor has a field effect mobility of 50cm 2/Vs or more.
9. The field effect transistor according to claim 1 or 2, wherein the substrate is polyethylene naphthalate, PEN, polyethylene terephthalate, PET, polyphenylene sulfide, PPS, polyetheretherketone, PS, polyethersulfone, PES, polycarbonate, PC, triacetyl cellulose, TAC, cyclic olefin polymer, COP.
10. A method for manufacturing a field effect transistor includes the steps of: using a sputtering target formed of an oxide containing indium, i.e., in element, zinc, i.e., zn element, and an additive element X, which is at least one element selected from tantalum, i.e., ta element, strontium, i.e., sr element, and niobium, i.e., nb element, sputtering a substrate for a flexible wiring board or a substrate having a glass transition temperature of 250 ℃ or less In an atmosphere having an oxygen concentration of 21 to 49% by volume to form an oxide semiconductor from the target,
And annealing the oxide semiconductor at 50-250 ℃.
11. The production method according to claim 10, wherein the additive element X is tantalum or niobium or Nb.
12. The manufacturing method according to claim 11, wherein the additive element X is tantalum, ta element.
13. The production method according to any one of claims 10 to 12, wherein an atomic ratio of each element in the target satisfies all of formulas (1) to (3), wherein X is set as a sum of the content ratios of the additive elements,
0.4≤(In+X)/(In+Zn+X)≤0.8 (1)
0.2≤Zn/(In+Zn+X)≤0.6 (2)
0.001≤X/(In+Zn+X)≤0.015 (3)。
14. A sputtering target for manufacturing a field effect transistor, which is formed of an oxide containing indium, i.e., an In element, zinc, i.e., a Zn element, and an additive element X,
The additive element X is at least one element selected from the group consisting of tantalum, namely Ta element, strontium, namely Sr element, and niobium, namely Nb element,
The atomic ratio of each element satisfies all of the formulas (1) to (3),
Wherein the field effect transistor includes an oxide semiconductor layer provided on a substrate for a flexible wiring board or a substrate having a glass transition temperature of 250 ℃ or less and derived from the sputtering target,
0.4≤(In+X)/(In+Zn+X)≤0.8 (1)
0.2≤Zn/(In+Zn+X)≤0.6 (2)
0.001≤X/(In+Zn+X)≤0.015 (3)。
15. The sputter target of claim 14, wherein the additive element X is tantalum or niobium or Nb element.
16. The sputter target of claim 15, wherein the additive element X is tantalum, ta.
17. The sputtering target for manufacturing a field effect transistor according to any one of claims 14 to 16, wherein the sputtering target for manufacturing a field effect transistor comprises an In 2O3 phase and a Zn 3In2O6 phase.
18. The sputtering target for manufacturing a field effect transistor according to claim 17, wherein the additive element X is contained In both of the In 2O3 phase and the Zn 3In2O6 phase.
19. The sputtering target for manufacturing a field effect transistor according to claim 17, wherein a crystal grain size of the In 2O3 phase is 0.1 μm to 3.0 μm and a crystal grain size of the Zn 3In2O6 phase is 0.1 μm to 3.9 μm.
20. A semiconductor device using the field effect transistor according to claim 1 or 2.
CN202380013886.0A 2022-01-31 2023-01-16 Field effect transistor, method for manufacturing the same, and sputtering target for manufacturing the field effect transistor Pending CN118056282A (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2022013647 2022-01-31
JP2022-013647 2022-01-31
PCT/JP2023/000903 WO2023145497A1 (en) 2022-01-31 2023-01-16 Field effect transistor, method for producing same, and sputtering target for production of field effect transistor

Publications (1)

Publication Number Publication Date
CN118056282A true CN118056282A (en) 2024-05-17

Family

ID=87471323

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202380013886.0A Pending CN118056282A (en) 2022-01-31 2023-01-16 Field effect transistor, method for manufacturing the same, and sputtering target for manufacturing the field effect transistor

Country Status (5)

Country Link
JP (1) JP7364824B1 (en)
KR (1) KR20240087785A (en)
CN (1) CN118056282A (en)
TW (1) TWI846271B (en)
WO (1) WO2023145497A1 (en)

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5679417B2 (en) 2010-08-25 2015-03-04 富士フイルム株式会社 Manufacturing method of oxide semiconductor thin film, oxide semiconductor thin film manufactured by the manufacturing method, thin film transistor, and device including thin film transistor
KR20130097809A (en) * 2010-12-28 2013-09-03 가부시키가이샤 고베 세이코쇼 Oxide for semiconductor layer of thin film transistor, sputtering target, and thin-film transistor
JP5947697B2 (en) * 2012-10-19 2016-07-06 出光興産株式会社 Sputtering target
JP6809527B2 (en) * 2016-03-18 2021-01-06 株式会社リコー Field effect transistors, display elements, image display devices, and systems
KR20230017294A (en) * 2020-08-05 2023-02-03 미쓰이금속광업주식회사 Sputtering target material and oxide semiconductor

Also Published As

Publication number Publication date
WO2023145497A1 (en) 2023-08-03
JPWO2023145497A1 (en) 2023-08-03
TW202334468A (en) 2023-09-01
KR20240087785A (en) 2024-06-19
JP7364824B1 (en) 2023-10-18
TWI846271B (en) 2024-06-21

Similar Documents

Publication Publication Date Title
Zheng et al. All-sputtered, flexible, bottom-gate IGZO/Al 2 O 3 bi-layer thin film transistors on PEN fabricated by a fully room temperature process
KR101312774B1 (en) Semiconductor thin film and method for manufacturing same, and thin film transistor
AU2005302962B2 (en) Amorphous oxide and field effect transistor
JPWO2009034953A1 (en) Thin film transistor
KR20080053362A (en) Semiconductor device
US10480061B2 (en) Sputtering target
Pan et al. Electrical and Reliability Characteristics of High-$\kappa~{\rm HoTiO} _ {3}~\alpha $-InGaZnO Thin-Film Transistors
US20170037505A1 (en) Sputtering target, oxide semiconducting film, and method for making the same
Bukke et al. Effect of Hf alloy in ZrO x gate insulator for solution processed a-IZTO thin film transistors
CN112335058B (en) Oxide semiconductor thin film, thin film transistor, method for manufacturing thin film transistor, and sputtering target
CN118056282A (en) Field effect transistor, method for manufacturing the same, and sputtering target for manufacturing the field effect transistor
CN116636014A (en) Method for manufacturing tellurium-based semiconductor device, tellurium-based semiconductor device manufactured thereby, and thin film transistor
Jung et al. Balanced Performance Enhancements of a‐InGaZnO Thin Film Transistors by Using All‐Amorphous Dielectric Multilayers Sandwiching High‐k CaCu3Ti4O12
TWI520224B (en) Method for producing field-effect transistor, method for producing display device, method for producing x-ray imaging device, and method for producing optical sensor
Choi et al. Dual-gate InGaZnO thin-film transistors with organic polymer as a dielectric layer
CN118140007A (en) Sputtering target and method for producing oxide semiconductor
Hur et al. P‐154: Late‐News Poster: High‐Performance Indium‐Gallium Oxide Thin‐Film‐Transistors via Plasma‐Enhanced Atomic‐Layer‐Deposition
WO2023199722A1 (en) Oxide semiconductor film, thin-film transistor, sputtering target, and oxide sintered body
Pan et al. Impact of Ti Content on Structural and Electrical Characteristics of High-$\kappa $ Yb2TiO5 $\alpha $-InZnSnO Thin-Film Transistors
TWI850971B (en) Sputtering target and method for manufacturing oxide semiconductor
Cho et al. Low Energy Electron Beam Activated IGZO-based Thin Film Transistor
JP2023157846A (en) Oxide semiconductor film, thin-film transistor, sputtering target, and sintered oxide
CN118159686A (en) Sputtering target
김성민 Study on the Zn-Sn-O field effect transistors for the application to transparent and flexible display devices
Kulkarni et al. Indium tungsten oxide thin films for flexible high-performance transistors and neuromorphic electronics

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication