WO2023143632A1 - 基于数据比较进行时钟门控的触发单元 - Google Patents

基于数据比较进行时钟门控的触发单元 Download PDF

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Publication number
WO2023143632A1
WO2023143632A1 PCT/CN2023/080589 CN2023080589W WO2023143632A1 WO 2023143632 A1 WO2023143632 A1 WO 2023143632A1 CN 2023080589 W CN2023080589 W CN 2023080589W WO 2023143632 A1 WO2023143632 A1 WO 2023143632A1
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Prior art keywords
clock
data
edge
signal
trigger
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PCT/CN2023/080589
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English (en)
French (fr)
Inventor
宋卫权
陈向东
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杭州士兰微电子股份有限公司
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Publication of WO2023143632A1 publication Critical patent/WO2023143632A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/33—Design verification, e.g. functional simulation or model checking
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/027—Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
    • H03K3/037—Bistable circuits

Definitions

  • the present invention relates to integrated circuit technology, and more particularly, to a trigger unit for clock gating based on data comparison.
  • EDA Electronic design automation software
  • the standard cell library is the basic part in the back-end design process of the integrated circuit chip.
  • Optimized library cells can improve circuit performance and reduce power consumption.
  • gate circuits are used to pass multiple signals through combinational logic to generate logic operation results, and edge triggers are used to store the logic operation results.
  • gate circuits can be divided into AND gates, OR gates, NOT gates, NAND gates, OR gates, AND-OR gates, XOR gates, etc.
  • the logic operation result of the gate circuit is, for example, a pulse signal, and a steady-state level signal corresponding to a logic state is generated based on the pulse signal.
  • the edge trigger is an information storage device with memory function, which is used to store the result of memory logic operation.
  • the edge trigger is the most basic logic unit in various sequential digital circuit modules, and is an important unit circuit in digital circuit modules.
  • the edge trigger 110 is triggered on a rising edge or a falling edge of a clock signal, allowing input data to be transferred from an input terminal to an output terminal to obtain output data.
  • the edge flip-flop 110 is, for example, a D-type flip-flop.
  • a D-type flip-flop transmits on the trigger edge of a clock signal. Data will be output, and the data will remain unchanged until the next trigger edge.
  • the power consumption of the edge trigger includes static power consumption and dynamic power consumption.
  • the static power consumption is mainly caused by the leakage current
  • the dynamic power consumption is mainly caused by the signal inversion power consumption.
  • the inversion of the data signal of the edge trigger will cause additional data power consumption in the combinational logic of the subsequent stage, and the inversion of the clock signal will also generate the clock power consumption of the edge trigger itself.
  • the object of the present invention is to provide a trigger unit for clock gating based on data comparison, which enables the clock inversion of the edge trigger only in the clock cycle of input data inversion, so as to improve circuit performance and reduce power consumption.
  • a trigger unit including: an edge trigger, including a data input end, a clock input end, and a first data output end; and a clock gating circuit, including a first input end, a second input end, a clock input end terminal and output terminal, wherein, the first input terminal of the clock gating circuit receives the input data of the edge trigger, the second input terminal receives the output data of the edge trigger, and the clock input terminal receives the first clock signal , the output terminal is coupled to the clock input terminal of the edge trigger to provide a second clock signal, and the clock gating circuit enables or shields the first clock according to a data comparison result between the input data and the output data signal to generate the second clock signal, the second clock signal provides the trigger edge of the edge trigger, the clock gating circuit in the clock cycle of the input data inversion, the first clock signal replicating the second clock signal, maintaining the second clock signal at a predetermined level during a clock cycle in which the input data remains unchanged.
  • the clock period of the first clock signal includes consecutive first level phases and second level phases, and the input data is inverted during the first level phase of the first clock signal.
  • the predetermined level is the level of the first level stage, and the second clock signal provides a trigger edge in a clock cycle next to the clock cycle of input data inversion.
  • the starting edge of the first level phase is a rising edge.
  • the clock gating circuit includes: an exclusive OR gate, including a first input terminal, a second input terminal and an output terminal, and the first input terminal and the second input terminal respectively receive the edge Input data and output data of the flip-flop, the output end provides the first clock control signal; or gate, including the first input end, the second input end and the output end, the first input end receives the first clock signal and a NOT gate, comprising an input terminal and an output terminal, the NOT gate is connected between the output terminal of the XOR gate and the second input terminal of the OR gate, wherein the NOT gate controls the first clock The control signal is inverted and provided to the second input terminal of the OR gate, and the output terminal of the OR gate provides the second clock signal.
  • an exclusive OR gate including a first input terminal, a second input terminal and an output terminal, and the first input terminal and the second input terminal respectively receive the edge Input data and output data of the flip-flop, the output end provides the first clock control signal
  • gate including the first input end, the second input end and the output end, the first
  • the OR gate further includes a third input terminal, and the third input terminal receives an inversion signal of the second clock control signal.
  • the clock gating circuit when the second clock control signal is valid, the clock gating circuit enables the data comparison function, and when the second clock control signal is invalid, the clock gating circuit disables the data comparison function.
  • the starting edge of the first level phase is a falling edge.
  • the clock gating circuit includes: an exclusive OR gate, including a first input terminal, a second input terminal and an output terminal, the first input terminal and the second input terminal respectively receive the input data and output data, the output terminal provides a first clock control signal; and an AND gate, including a first input terminal, a second input terminal and an output terminal, the first input terminal receives the first clock signal, so The second input end receives the first clock control signal, and the output end provides the second clock signal.
  • the AND gate further includes a third input terminal, and the third input terminal receives a second clock control signal.
  • the clock gating circuit when the second clock control signal is valid, the clock gating circuit enables the data comparison function, and when the second clock control signal is invalid, the clock gating circuit disables the data comparison function.
  • the data input terminal of the edge trigger receives an inverted signal of its own output data as input data.
  • the edge trigger further includes a second data output terminal, and the first data output terminal and the second data output terminal of the edge trigger respectively provide the output data of the edge trigger and the inversion of the output data.
  • phase signal wherein the data input terminal of the edge trigger and the second data output terminal are coupled to each other to receive an inversion signal of its output data.
  • each of the first clock control signal and the second clock control signal is high The level indicates an active state, and the low level indicates an invalid state.
  • the edge trigger receives the input data at the data input terminal at the trigger edge and transmits it to the first data output terminal.
  • the clock gating circuit copies the first clock signal into the second clock signal during the clock cycle when the input data is inverted, and copies the first clock signal into the second clock signal during the clock cycle when the input data remains unchanged.
  • the two clock signals are maintained at predetermined levels. Therefore, the clock gating circuit enables the transmission of the clock signal only in one clock period when the input data of the edge trigger is flipped, thereby minimizing the dynamic power consumption of the edge flip-flop due to the clock flip. Further, the clock gating circuit only provides a trigger edge in the next clock period when the input data of the edge trigger is flipped, so that the dynamic power consumption of the edge trigger due to data transmission can be minimized.
  • the edge trigger prevents the data from entering the downstream digital circuit during most of the clock cycles when the input data remains unchanged, thus avoiding additional data power consumption caused by the inversion of the data signal of the subsequent combinatorial logic.
  • the trigger unit utilizing the circuit characteristics of the clock gating circuit in the inversion period of the clock control signal, even if the clock gating circuit omits an additional latch, the glitch of the clock signal generated by the clock gating circuit can be eliminated, and The number of logic elements of the clock gating circuit is reduced and the power consumption of the clock gating circuit is reduced. Since the working power consumption of the clock gating circuit itself is low, the power consumption increased by the power consumption of the clock gating circuit itself is much smaller than the power consumption reduced by the edge trigger due to the clock gating.
  • any number of edge flip-flops in the trigger unit can form a flip-flop group that shares a clock gating circuit.
  • the flip-flop group contains any number of edge flip-flops, eg one, two, or many, the flip-flop unit always achieves power reduction.
  • the minimum delay and the maximum delay of the signal delay of the input data of the edge trigger are set in the first level stage of the clock signal, which can avoid the occurrence of burrs in the clock signal of the edge trigger and cause the edge Triggers are not working properly. Even if the circuit design of the clock gating circuit is simplified in the trigger unit, the clock inversion and data transmission of the edge trigger can still be reliably disabled to reduce dynamic power consumption.
  • the circuit design of the trigger unit is simplified and the layout area is reduced, and it can be used as a library unit of a standard cell library together with the existing edge trigger design. applications to improve the performance and design efficiency of digital circuits.
  • the data input terminal of the edge trigger receives an inverted signal of its own output data as input data.
  • the edge trigger includes a first data output terminal and a second data output terminal, respectively providing the output data of the edge trigger and an inversion signal of the output data, and the data input terminal of the edge trigger is connected to the second data output terminals are coupled to each other.
  • the pre-stage logic circuit only needs to provide input data to the clock gating circuit in the trigger unit, and does not need to provide input data to the edge trigger in the trigger unit, which can reduce the load pressure on the pre-stage logic circuit.
  • the edge trigger does not need to receive any input data from the outside, so it can reduce the adverse effect of the signal delay fluctuation of the external input data on the working stability of the edge trigger.
  • FIG. 1 shows a schematic circuit diagram of an edge trigger in an integrated circuit.
  • FIG. 2 shows a waveform diagram of an edge trigger in an integrated circuit.
  • Fig. 3 shows a schematic circuit diagram of a trigger unit according to the prior art.
  • FIG. 4 shows a schematic circuit diagram of another trigger unit according to the prior art.
  • FIG. 5 shows a schematic circuit diagram of a clock gating circuit in the trigger unit shown in FIG. 4 .
  • FIG. 6 shows a waveform diagram of a clock gating circuit in the trigger unit shown in FIG. 4 .
  • Fig. 7 shows a schematic circuit diagram of a trigger unit according to the first embodiment of the present invention.
  • FIG. 8 shows a schematic circuit diagram of a clock gating circuit in the trigger unit shown in FIG. 7 .
  • FIG. 9 shows a schematic circuit diagram of another clock gating circuit in the trigger unit shown in FIG. 7 .
  • FIG. 10 shows a waveform diagram of the clock gating circuit shown in FIG. 8 .
  • FIG. 11 shows a waveform diagram of the clock gating circuit shown in FIG. 9 .
  • Fig. 12 shows a schematic circuit diagram of a trigger unit according to a second embodiment of the present invention.
  • FIG. 13 shows a schematic circuit diagram of a clock gating circuit in the trigger unit shown in FIG. 12 .
  • Fig. 14 shows a schematic circuit diagram of a trigger unit according to a third embodiment of the present invention.
  • FIG. 15 shows a schematic circuit diagram of a clock gating circuit in the trigger unit shown in FIG. 14 .
  • the invention can be embodied in various forms, some examples of which are described below.
  • the descriptions of the following embodiments all take the edge trigger triggered by the rising edge as an example for illustration.
  • Fig. 3 shows a schematic circuit diagram of a trigger unit according to the prior art.
  • the trigger unit 100 includes an edge trigger 110 and a data selector 120 .
  • the data selector 120 is used for gating the input data Di of the edge flip-flop 110 .
  • the edge flip-flop 110 is, for example, a D-type flip-flop.
  • the edge flip-flop 110 includes a data input terminal, a data output terminal and a clock input terminal.
  • the data selector 120 includes a control terminal, a first data input terminal, a second data input terminal and an output terminal.
  • the control terminal of the data selector 120 receives the data control signal EN, the first data input terminal receives the input data Di of the edge trigger 110, the second data input terminal receives the output data Do of the edge trigger 120, and the output terminal provides the selected data Ds .
  • a data input terminal of the edge trigger 110 receives selected data Ds, a clock input terminal receives a clock signal CLK, and a data output terminal provides output data Do.
  • the edge flip-flop 110 On a trigger edge, such as a rising edge, of the clock signal CLK, the edge flip-flop 110 transmits input data from the data input end to the data output end. Therefore, the signal level corresponding to the output data of the data output terminal of the edge trigger 110 depends on the signal level of the input data at the data input terminal before the rising edge of the clock signal CLK, and one clock after the rising edge of the clock signal CLK remain unchanged throughout the cycle.
  • the data output terminal of the edge trigger 110 may include two complementary output terminals.
  • the data selector 120 provides the input data Di to the input end of the edge flip-flop 110 when the data control signal EN is valid, and when the data control signal EN is invalid, the data selector 120 connects the first input end and the output end of the edge flip-flop 110 are connected to each other, thus shielding the edge Input data for flip-flop 110.
  • the data selector 120 will also keep the output data of the edge flip-flop 110 unchanged, so the data reception of the edge flip-flop 110 can be disabled.
  • the data selector 120 controls the data reception of the edge trigger 110 according to the state of the data control signal EN.
  • the edge trigger 110 cannot receive the input data, but maintains the output data unchanged, thereby preventing the input data from entering the digital circuit of the subsequent stage, and avoiding the input data of the subsequent stage.
  • Data signal toggling in combinational logic generates additional data power consumption.
  • the data selector 120 cannot disable the clock inversion of the edge flip-flop 110 .
  • the clock input terminal of the edge trigger 110 always receives the clock signal CLK. Data is transmitted at the triggering edge of the clock signal CLK, so the dynamic power consumption of the edge trigger 110 due to the inversion of the clock signal CLK cannot be reduced.
  • FIG. 4 shows a schematic circuit diagram of another trigger unit according to the prior art.
  • the trigger unit 200 includes an edge trigger 110 and a clock gating circuit 130 .
  • the clock gating circuit 130 is used for gating the clock signal CK of the edge trigger 110 .
  • the edge flip-flop 110 is, for example, a D-type flip-flop.
  • the edge flip-flop 110 includes a data input terminal, a data output terminal and a clock input terminal.
  • the clock gating circuit 130 includes an input terminal, an output terminal and a control terminal.
  • the input end of the clock gating circuit 130 receives the clock signal CLK, the output end provides the clock signal CK, and the control end receives the clock control signal EN.
  • the data input end of the edge trigger 110 receives input data Di, the clock input end receives a clock signal CK, and the data output end provides output data Do.
  • the edge flip-flop 110 On a trigger edge, such as a rising edge, of the clock signal CK, the edge flip-flop 110 transmits input data from the data input terminal to the data output terminal. Therefore, the signal level corresponding to the output data of the data output terminal of the edge trigger 110 depends on the signal level of the input data at the data input terminal before the trigger edge of the clock signal CK arrives, and one clock after the trigger edge of the clock signal CK remain unchanged throughout the cycle.
  • the data output terminal of the edge trigger 110 may include two complementary output terminals.
  • the clock gating circuit 130 performs a combinational logic operation on the input data Di, the output data Do and the clock signal CLK to generate the clock signal CK of the edge flip-flop 110 .
  • the clock gating circuit 130 controls the signal EN according to the The state controls the transmission of the clock signal.
  • the clock gating circuit 130 copies the clock signal CLK into a clock signal CK, and the clock signal CK is provided to the clock input terminal of the edge trigger 110, and the clock signal EN remains invalid.
  • the clock gating circuit 130 shields the clock signal CLK and maintains the clock signal CK at a predetermined level.
  • the clock signal CK In the case that the clock signal CK is maintained at a predetermined level, the clock signal CK cannot provide the trigger edge of the edge trigger 110, so the clock inversion and data transmission of the edge trigger 110 can be disabled, thereby reducing the frequency of the edge trigger 110 caused by the clock signal. Dynamic power consumption caused by CK flipping and dynamic power consumption caused by data transmission. Furthermore, the edge trigger 110 prevents data from entering into subsequent digital circuits, thus avoiding additional data power consumption caused by inversion of data signals of subsequent combinational logic.
  • FIG. 5 shows a schematic circuit diagram of a clock gating circuit in the trigger unit shown in FIG. 4 .
  • the clock gating circuit 130 and the edge trigger 110 together constitute a trigger unit, and the clock gating circuit 130 provides the clock signal CK to the edge trigger 110 .
  • the clock gating circuit 130 includes a latch 131 and an AND gate 132 .
  • the latch 131 latches the clock control signal EN in the first level phase T1 of the clock signal CLK, transmits the clock control signal EN in the second level phase T2 of the clock signal CLK, and the AND gate pairs the latch signal EN_a and the clock
  • the signal CLK performs logic AND operation to generate the clock signal CK.
  • the latch 131 includes a first input terminal, a second input terminal and an output terminal.
  • the AND gate 132 includes a first input terminal, a second input terminal and an output terminal.
  • a first input terminal of the latch 131 receives a clock signal CLK, and a second input terminal receives a clock control signal EN.
  • the first input end of the AND gate 132 receives the clock signal CLK, the second input end is connected to the output end of the latch 131 , and the output end provides the clock signal CK.
  • the clock control signal EN is described as an example where a high level indicates an active state and a low level indicates an invalid state.
  • Each clock cycle of the clock signal CLK includes continuous first level phase T1 and second level phase T2 between adjacent rising edges, and the first level phase T1 and the second level phase T2 respectively have a high level and low level.
  • the clock signal CK provides the triggering edge of the edge trigger 110, and the edge trigger 110 transmits the input data from the input terminal to the output terminal on the triggering edge.
  • the input data Di and the clock control signal EN each exist relative to the clock
  • the signal delay Td of the signal edge Areas between the minimum delay Tdmin and the maximum delay Tdmax of the signal delay Td are indicated by hatching, respectively.
  • the signal delay Td of the clock control signal EN varies between a minimum delay Tdmin and a maximum delay Tdmax.
  • the minimum delay Tdmin and the maximum delay Tdmax are respectively located in the first level stage T1 and the second level stage T2, and the inversion of the clock control signal EN may occur in the first level stage of the clock signal CLK T1 may also occur in the second level phase T2 of the clock signal CLK.
  • the clock signal CLK reaches the first rising edge, and the clock control signal EN is valid.
  • the clock control signal EN turns from an active state to an inactive state.
  • the signal level of the latch signal EN_a at the output terminal of the latch 131 remains at the previous state, ie, the high level.
  • the latch 131 transmits the clock control signal EN from the input terminal to the output terminal.
  • the latch signal EN_a is a replica of the clock signal CLK in the clock period when the clock control signal is inverted. If the signal delay Td of the clock control signal EN is greater than the first level phase T1 of the clock signal CLK, a glitch occurs in the latch signal EN_a during the second level phase T2 of the clock signal CLK.
  • the clock signal CK is a logical AND operation result of the clock signal CLK and the latch signal EN_a, and the logical AND operation can eliminate the glitch of the latch signal EN_a in the second level stage T2 of the clock signal CLK.
  • the clock gating circuit 130 duplicates the clock signal CLK as the clock signal CK and provides the rising edge of the clock signal CK, the signal level of the output data Do of the edge trigger 110 is the same as the signal level of the time t0
  • the signal level of the input data Di is consistent, for example, the low level shown in FIG. 6 .
  • the clock signal CLK reaches the second rising edge, and the clock control signal EN becomes invalid.
  • the clock control signal EN remains inactive.
  • the signal level of the latch signal EN_a at the output terminal of the latch 131 remains at the previous state, ie, low level.
  • the latch 131 transmits the clock control signal EN from the input terminal to the output terminal.
  • the clock control signal EN maintains a low level state, so EN_a also Keep the low level, and the clock signal CK is also kept low through the AND operation of the clock signal CLK and the latch signal EN_a.
  • the clock signal CLK reaches the third rising edge, and the clock control signal EN becomes invalid.
  • the clock control signal EN is switched from an inactive state to an active state.
  • the signal level of the latch signal EN_a at the output terminal of the latch 131 remains at the previous state, ie, low level.
  • the latch 131 transmits the clock control signal EN from the input terminal to the output terminal.
  • the latch signal EN_a is a replica of the clock signal CLK in the clock period when the clock control signal is inverted. If the signal delay Td of the clock control signal EN is greater than the first level phase T1 of the clock signal CLK, a glitch occurs in the latch signal EN_a during the second level phase T2 of the clock signal CLK.
  • the clock signal CK is a logical AND operation result of the clock signal CLK and the latch signal EN_a, and the logical AND operation can eliminate the glitch of the latch signal EN_a in the second level phase T2 of the clock signal CLK.
  • the clock gating circuit 130 shields the clock signal CLK and does not provide the rising edge of the clock signal CK, and the signal level of the output data Do of the edge trigger 110 is the same as that of the previous clock cycle.
  • the signal level is consistent, for example, the low level shown in Figure 6.
  • the clock signal CLK reaches the fourth rising edge, and the clock control signal EN is valid.
  • the clock control signal EN maintains an active state.
  • the signal level of the latch signal EN_a at the output terminal of the latch 131 remains at the previous state, ie, the high level.
  • the latch 131 transmits the clock control signal EN from the input terminal to the output terminal.
  • the clock control signal EN maintains a high level state, therefore, the latch signal EN_a also maintains a high level, and the clock signal CK is ANDed by the clock signal CLK and the latch signal EN_a, therefore, the clock signal CK is Replicated version of the clock signal CLK.
  • the clock gating circuit 130 copies the clock signal CLK into the clock signal CK and provides the rising edge of the clock signal CK, and the signal level of the output data Do of the edge trigger 110 is the same as the signal level of the time t3
  • the signal levels of the input data Di are consistent, for example, the high level shown in FIG. 5 .
  • the aforementioned clock gating circuit 130 controls the transmission of the clock signal according to the state of the clock control signal EN.
  • the clock gating circuit 130 replicates the clock signal CLK into a clock signal CK.
  • the clock signal CK provides the trigger edge of the edge trigger 110
  • the clock gating circuit 130 allows the clock inversion and data transmission of the edge trigger 110
  • the output data Do provided by the edge trigger 110 is the input data Di of the current trigger edge.
  • the clock gating circuit 130 shields the clock signal CLK and maintains the clock signal CK at a predetermined level. At this time, the clock signal CK fails to provide the trigger edge of the edge trigger 110, the clock gating circuit 130 disables the clock inversion and data transmission of the edge trigger 110, and the edge trigger 110 maintains the input data Di of the previous trigger edge, so it can The dynamic power consumption of the edge trigger 110 is reduced.
  • the aforementioned clock gating circuit 130 has low requirements on the timing of the clock control signal EN. If it is desired to disable data transmission at the predetermined time, the clock control signal EN can be turned over from the valid state to the invalid state in the last full clock cycle before the predetermined time, and the clock control can be completed in the last clock cycle starting from the predetermined time The toggle action of signal EN from inactive state to active state.
  • the clock gating circuit 130 includes a latch 131 for eliminating possible glitches in the clock signal CK of the edge trigger 110 .
  • the clock gating circuit 130 can provide a clock signal CK for a plurality of edge flip-flops 110 in the flip-flop group. If the clock gating circuit 130 is used, then the restriction on the circuit design is that the number of edge triggers in the trigger group is no less than 3 to 8, so as to ensure that the working power consumption of the clock gating circuit 130 of the trigger unit 200 is less than The power consumption of the number of edge flip-flops 110 is reduced due to the clock gating circuit 130 .
  • the signal delay of the input data of the edge trigger 110 It may be possible to set them both at the same level stage of the clock signal CLK by design, and based on the comparison of the input data and output data of the edge trigger 110 , a correspondingly delayed clock control signal EN_a can be obtained.
  • the inventors have designed the clock gating circuits 330 and 430 based on data comparison described in detail below, and combined the clock control signal EN obtained based on data comparison with a redesigned logic circuit. The same function as the clock gating circuit 130 can be obtained.
  • the clock gating circuit 330 and the clock gating circuit 430 can be used for a redesigned trigger cell. Therefore, the power consumption of the integrated circuit can be further reduced, the cost of the trigger unit can be reduced, and the power consumption of the clock gating circuit itself can be reduced, thereby breaking through the above-mentioned limitation in circuit design.
  • Fig. 7 shows a schematic circuit diagram of a trigger unit according to the first embodiment of the present invention.
  • the trigger unit 300 includes an edge trigger 110 and a clock gating circuit 330 .
  • the clock gating circuit 330 is used for gating the clock signal CK of the edge trigger 110 .
  • the edge flip-flop 110 is, for example, a D-type flip-flop.
  • the edge flip-flop 110 includes a data input terminal, a data output terminal and a clock input terminal.
  • the clock gating circuit 330 includes a first input terminal, a second input terminal, a clock input terminal, and a clock output terminal.
  • a first input terminal of the clock gating circuit 330 receives input data Di, a second input terminal receives output data Do, a clock input terminal receives a clock signal CLK, and a clock output terminal provides a clock signal CK.
  • the data input end of the edge trigger 110 receives input data Di, the clock input end receives a clock signal CK, and the data output end provides output data Do.
  • the edge flip-flop 110 On a trigger edge, such as a rising edge, of the clock signal CK, the edge flip-flop 110 transmits input data from the data input terminal to the data output terminal. Therefore, the signal level corresponding to the output data of the data output terminal of the edge trigger 110 depends on the signal level of the input data at the data input terminal before the trigger edge of the clock signal CK arrives, and one clock after the trigger edge of the clock signal CK remain unchanged throughout the cycle.
  • the data output terminal of the edge trigger 110 may include two complementary output terminals.
  • the clock gating circuit 330 performs a combinational logic operation on the input data Di, the output data Do and the clock signal CLK to generate the clock signal CK of the edge flip-flop 110 .
  • the above-mentioned clock gating circuit 330 is based on the input data Di and the output of the edge trigger 110
  • the data comparison of the data Do generates the clock control signal EN_a, and the transmission of the clock signal is controlled according to the state of the clock control signal EN_a.
  • the clock gating circuit 330 maintains the clock signal CK at a predetermined level. During the clock period when the input data Di is inverted, the clock gating circuit 330 copies the clock signal CLK into the clock signal CK. Therefore, the clock gating circuit 330 enables the transmission of the clock signal CLK only in one clock cycle when the input data Di of the edge flip-flop 110 is flipped, thereby minimizing the dynamic power consumption of the edge flip-flop 110 caused by the flip of the clock signal CK. Further, the clock gating circuit 330 only provides a trigger edge in the next clock period when the input data Di of the edge trigger 110 is flipped, so that the dynamic power consumption of the edge trigger 110 due to data transmission can be minimized.
  • edge trigger 110 prevents the data from entering the subsequent digital circuit during most clock cycles when the input data Di remains unchanged, thus avoiding additional data power consumption caused by inversion of the data signal of the subsequent combinatorial logic.
  • FIG. 8 shows a schematic circuit diagram of a clock gating circuit in the trigger unit shown in FIG. 7 .
  • the clock gating circuit 330 and the edge trigger 110 together constitute a trigger unit, and the clock gating circuit 330 provides the clock signal CK to the edge trigger 110 .
  • the clock gating circuit 330 includes an exclusive OR gate 331 , a NOT gate 332 and an OR gate 333 .
  • the clock control signal EN_a is generated based on the comparison of the input data Di and the output data Do of the edge trigger 110, and the clock signal CK is a logical OR operation of the clock signal CLK and the inversion signal EN_b of the clock control signal EN_a result.
  • the XOR gate 331 includes a first input terminal, a second input terminal and an output terminal.
  • the NOT gate 332 includes an input terminal and an output terminal.
  • the OR gate 333 includes a first input terminal, a second input terminal and an output terminal.
  • the first data input terminal of the XOR gate 331 receives the input data Di of the edge trigger 110
  • the second data input terminal receives the output data Do of the edge trigger 110
  • the output terminal provides the clock control signal EN_a.
  • the NOT gate 332 is connected between the output terminal of the exclusive OR gate 331 and the second input terminal of the OR gate 331 for generating an inverted signal EN_b of the clock control signal EN_a.
  • the first input terminal of the OR gate 333 receives the clock signal CLK.
  • the second input terminal of the OR gate 333 receives the inverted signal EN_b of the clock control signal EN_a via the NOT gate 332 .
  • the output terminal of the OR gate 333 provides the clock signal CK.
  • an edge trigger triggered by a rising edge is taken as an example, and the clock control signal EN_a is described as an example where a high level indicates an active state and a low level indicates an inactive state.
  • clock Each clock cycle of the signal CLK includes continuous first level phase T1 and second level phase T2 between adjacent rising edges, the first level phase T1 and the second level phase T2 have high level and low level respectively level.
  • the clock signal CK provides a rising edge as a triggering edge of the edge trigger 110 , and the edge trigger 110 transmits input data from the input terminal to the output terminal on the triggering edge.
  • the input data Di of the edge trigger 110 has a signal delay Td relative to the edge of the clock signal. Areas between the minimum delay Tdmin and the maximum delay Tdmax of the signal delay Td are indicated by hatching, respectively.
  • the signal delay Td of the input data Di of the edge trigger 110 varies between a minimum delay Tdmin and a maximum delay Tdmax.
  • the clock control signal EN_a of the clock gating circuit is obtained based on the data comparison between the input data Di and the output data Do of the edge trigger 110, and the signal delay Td of the clock control signal EN_a is approximately the same as the signal delay Td of the input data Di same.
  • the signal delay Td of the input data Di of the edge trigger 110 can be calculated and set, so that the minimum delay Tdmin and the maximum delay Tdmax of the signal delay Td are within the range of the selected second of the clock signal CLK In a level stage T1.
  • the signal delay Td of the clock control signal EN_a is within the range of the minimum delay Tdmin and the maximum delay Tdmax of the first level phase T1 of the clock signal CLK.
  • the inversion of the clock control signal EN_a can only occur in the first level phase T1 of the clock signal CLK.
  • the starting edge of the first level stage T1 is a rising edge.
  • the clock signal CLK reaches the first rising edge, and the clock signal CK maintains the high level of the previous clock cycle.
  • the clock control signal EN_a is a logical exclusive OR operation result of the input data Di and the output data Do of the edge flip-flop 110 .
  • the signal level of the input data Di of the edge trigger 110 is flipped from low level to high level after a signal delay Td, and the signal level of the output data Do is always low level.
  • the clock control signal EN_a switches from low level to high level through the signal delay Td
  • the inverted signal EN_b of the clock control signal EN_a switches from high level to low level through the signal delay Td.
  • the clock signal CK is a logical OR operation result of the inversion signal EN_b of the clock control signal EN_a and the clock signal CLK.
  • the clock signal CK is a duplicate version of the clock signal CLK.
  • the signal delay Td is located in the first level stage T1 of the clock signal CLK, and the combinational logic operation can eliminate the possible generation of the clock signal CK due to the signal delay Td glitches.
  • the clock gating circuit 330 copies the clock signal CLK into the clock signal CK. Since the level state of the clock signal CK in the previous clock cycle was high, the clock signal CK fails to provide the trigger edge, ie, the rising edge, of the edge trigger 110 .
  • the signal level of the output data Do of the edge trigger 110 is consistent with the signal level of the input data Di of the previous trigger edge of the clock signal CK, for example, the low level shown in FIG. 10 .
  • the clock signal CLK reaches the second rising edge, and the clock signal CK turns from the low level in the second level stage of the previous clock cycle to the high level.
  • the clock control signal EN_a is a logical exclusive OR operation result of the input data Di and the output data Do of the edge flip-flop 110 .
  • the signal level of the input data Di remains high, and the signal level of the output data Do is always high.
  • the clock control signal EN_a flips from high level to low level at time t1 and is always at low level in the clock cycle starting at time t1, and the inversion signal EN_b of the clock control signal EN_a is at time t1 It is always high level in the clock cycle starting from t1.
  • the clock signal CK is a logical OR operation result of the inversion signal EN_b of the clock control signal EN_a and the clock signal CLK. Therefore, at time t1 , the clock signal CK is switched from low level to high level and maintained at high level in the clock period starting from time t1 .
  • the clock gating circuit 330 maintains the clock signal CK at a high level. Since the level state of the second level stage of the previous clock cycle of the clock signal CK is low level, the clock signal CK provides the trigger edge of the edge trigger 110 , that is, the rising edge.
  • the signal level of the output data Do of the edge trigger 110 is consistent with the signal level of the input data Di of the trigger edge of the current clock cycle of the clock signal CK, for example, the high level shown in FIG. 10 .
  • the clock signal CLK reaches the third rising edge, and the clock signal CK maintains the high level of the previous clock cycle.
  • the clock control signal EN_a is the input data Di and output data of the edge trigger 110
  • the logical XOR operation result of Do In the entire clock cycle starting from time t2, the signal level of the input data Di of the edge trigger 110 is turned from high level to low level after a signal delay Td, and the signal level of the output data Do is always in the entire clock cycle is high level.
  • the clock control signal EN_a switches from low level to high level through the signal delay Td
  • the inverted signal EN_b of the clock control signal EN_a switches from high level to low level through the signal delay Td.
  • the clock signal CK is a logical OR operation result of the inversion signal EN_b of the clock control signal EN_a and the clock signal CLK.
  • the clock signal CK is a replica version of the clock signal CLK.
  • the signal delay Td is located in the first level stage T1 of the clock signal CLK, and the combinational logic operation can eliminate the possible generation of the clock signal CK due to the signal delay Td glitches.
  • the clock gating circuit 330 copies the clock signal CLK into the clock signal CK. Since the level state of the clock signal CK in the previous clock cycle was high, the clock signal CK fails to provide the trigger edge, ie, the rising edge, of the edge trigger 110 .
  • the signal level of the output data Do of the edge trigger 110 is consistent with the signal level of the input data Di of the previous trigger edge of the clock signal CK, for example, the high level shown in FIG. 10 .
  • the clock signal CLK reaches the fourth rising edge, and the clock signal CK turns from the low level of the second level stage of the previous clock cycle to the high level.
  • the clock control signal EN_a is a logical exclusive OR operation result of the input data Di and the output data Do of the edge flip-flop 110 .
  • the signal level of the input data Di remains low, and the signal level of the output data Do is always low.
  • the clock control signal EN_a flips from high level to low level at time t3 and is always at low level in the clock cycle starting at time t3, and the inversion signal EN_b of the clock control signal EN_a is at time t3 It is always high level in the clock cycle starting from t3.
  • the clock signal CK is a logical OR operation result of the inversion signal EN_b of the clock control signal EN_a and the clock signal CLK. Therefore, at time t3 , the clock signal CK is switched from low level to high level and remains at high level in the clock period starting from time t3 .
  • the clock gating circuit 330 will clock The signal CK maintains a high level. Since the level state of the second level stage of the previous clock cycle of the clock signal CK is low level, the clock signal CK provides the trigger edge of the edge trigger 110 , that is, the rising edge. The signal level of the output data Do of the edge trigger 110 is consistent with the signal level of the input data Di of the trigger edge of the current clock cycle of the clock signal CK, for example, the low level shown in FIG. 10 .
  • the above-mentioned clock gating circuit 330 generates the clock control signal EN_a based on the data comparison between the input data Di and the output data Do of the edge flip-flop 110 , and controls the transmission of the clock signal according to the state of the clock control signal EN_a.
  • the clock gating circuit 330 shields the clock signal CLK and maintains the clock signal CK at a high level. Therefore, the clock gating circuit 330 can disable clock inversion and data transmission of the edge trigger 110 , thereby reducing dynamic power consumption of the edge trigger 110 due to clock inversion and data transmission.
  • the clock gating circuit 330 replicates the clock signal CLK as the clock signal CK, and provides the triggering edge of the edge trigger in the next clock cycle, therefore, the clock gating circuit 330 can enable the clock inversion of the edge trigger 110 in a single clock cycle, and The data transmission of the edge flip-flop 110 is enabled in a single clock cycle, thereby reducing the dynamic power consumption of the edge flip-flop 110 due to clock inversion and data transmission.
  • a latch is omitted. Even if there is a signal delay Td in the input data Di of the edge trigger 110, as long as the minimum delay Tdmin and the maximum delay Tdmax of the signal delay Td of the input data Di of the edge trigger 110 are set in the first level stage of the clock signal CLK, The glitch of the clock signal CK of the edge trigger 110 can be eliminated.
  • the clock gating circuit 330 In the circuit design of the trigger unit, the clock gating circuit 330 only needs to set the signal delay of the input data Di of the edge trigger 110, thus, the circuit structure and circuit design of the trigger unit can be simplified.
  • the hardware logic that the clock gating circuit 330 uses is less, and its own work Low power consumption.
  • any number of edge flip-flops 110 can share the clock gating circuit 330 to form a flip-flop group.
  • the increased power consumption due to the power consumption of the clock gating circuit 330 itself is much smaller than the reduced power consumption of the edge trigger 110 due to clock gating, therefore, the trigger unit Power reduction can always be achieved.
  • FIG. 9 shows a schematic circuit diagram of another clock gating circuit in the trigger unit shown in FIG. 7 .
  • the clock gating circuit 430 and the edge trigger 110 together constitute a trigger unit, and the clock gating circuit 430 provides the clock signal CK to the edge trigger 110 .
  • the clock gating circuit 430 includes an exclusive OR gate 431 and an AND gate 433 .
  • the clock control signal EN_a is generated based on the comparison of the input data Di and the output data Do of the edge trigger 110
  • the clock signal CK is a logical AND operation result of the clock signal CLK and the clock control signal EN_a.
  • the XOR gate 431 includes a first input terminal, a second input terminal and an output terminal.
  • the AND gate 433 includes a first input terminal, a second input terminal and an output terminal.
  • the first data input terminal of the XOR gate 431 receives the input data Di of the edge trigger 110
  • the second data input terminal receives the output data Do of the edge trigger 110
  • the output terminal provides the clock control signal EN_a.
  • the first input terminal of the AND gate 433 receives the clock signal CLK.
  • the second input terminal of the AND gate 433 is connected to the output terminal of the exclusive OR gate 431 to receive the clock control signal EN_a.
  • the output terminal of the AND gate 433 provides the clock signal CK.
  • an edge trigger triggered by a falling edge is taken as an example, and the clock control signal EN is described as an example where a high level indicates an active state and a low level indicates an invalid state.
  • Each clock cycle of the clock signal CLK includes continuous first level phase T1 and second level phase T2 between adjacent falling edges, and the first level phase T1 and the second level phase T2 respectively have a low level and high level.
  • the clock signal CK provides a falling edge as a trigger edge of the edge trigger 110 , and the edge trigger 110 transmits input data from the input terminal to the output terminal on the trigger edge.
  • the input data Di of the edge trigger 110 has a signal delay Td relative to the edge of the clock signal. Areas between the minimum delay Tdmin and the maximum delay Tdmax of the signal delay Td are indicated by hatching, respectively.
  • the signal delay Td of the input data Di of the edge trigger 110 varies between a minimum delay Tdmin and a maximum delay Tdmax.
  • the data comparison of the clock gating circuit obtains the clock control signal EN_a, and the signal delay Td of the clock control signal EN_a is approximately the same as the signal delay Td of the input data Di.
  • the signal delay Td of the input data Di of the edge trigger 110 can be calculated and set, so that the minimum delay Tdmin and the maximum delay Tdmax of the signal delay Td are within the range of the selected second of the clock signal CLK In a level stage T1.
  • the signal delay Td of the clock control signal EN_a is within the range of the minimum delay Tdmin and the maximum delay Tdmax of the first level phase T1 of the clock signal CLK.
  • the inversion of the clock control signal EN_a can only occur in the first level phase T1 of the clock signal CLK.
  • the starting edge of the first level stage T1 is a falling edge.
  • the clock signal CLK reaches the first falling edge, and the clock signal CK maintains the low level of the previous clock cycle.
  • the clock control signal EN_a is a logical exclusive OR operation result of the input data Di and the output data Do of the edge flip-flop 110 .
  • the signal level of the input data Di of the edge trigger 110 is flipped from low level to high level after a signal delay Td, and the signal level of the output data Do is always low level.
  • the clock control signal EN_a switches from low level to high level via the signal delay Td, and the clock control signal EN_a switches from low level to high level via the signal delay Td.
  • the clock signal CK is a logical AND operation result of the clock control signal EN_a and the clock signal CLK. During one clock cycle starting at instant t0, the clock signal CK is a replica version of the clock signal CLK. Although there is a signal delay Td in the clock control signal EN_a, the signal delay Td is located in the first level phase T1 of the clock signal CLK, and combinatorial logic operations can eliminate possible glitches in the clock signal CK due to the signal delay Td.
  • the clock gating circuit 430 copies the clock signal CLK into the clock signal CK. Since the level state of the clock signal CK in the previous clock period is low, the clock signal CK fails to provide the trigger edge, ie, the falling edge, of the edge trigger 110 .
  • the signal level of the output data Do of the edge trigger 110 is consistent with the signal level of the input data Di of the previous trigger edge of the clock signal CK, for example, the low level shown in FIG. 11 .
  • the clock signal CLK reaches the second falling edge, and the clock signal CK
  • the high level transition of the second level stage of the clock cycle is low level.
  • the clock control signal EN_a is a logical exclusive OR operation result of the input data Di and the output data Do of the edge flip-flop 110 .
  • the signal level of the input data Di remains high, and the signal level of the output data Do is always high.
  • the clock control signal EN_a is switched from high level to low level at time t1 and is always at low level in the clock period starting from time t1 .
  • the clock signal CK is a logical AND operation result of the clock control signal EN_a and the clock signal CLK. Therefore, at time t1 , the clock signal CK is switched from high level to low level and maintained at low level in the clock period starting from time t1 .
  • the clock gating circuit 430 maintains the clock signal CK at a low level. Since the level state of the second level stage of the previous clock cycle of the clock signal CK is high level, the clock signal CK provides the trigger edge of the edge trigger 110 , ie, the falling edge.
  • the signal level of the output data Do of the edge trigger 110 is consistent with the signal level of the input data Di of the trigger edge of the current clock cycle of the clock signal CK, for example, the high level shown in FIG. 11 .
  • the clock signal CLK reaches the third falling edge, and the clock signal CK maintains the low level of the previous clock cycle.
  • the clock control signal EN_a is a logical exclusive OR operation result of the input data Di and the output data Do of the edge flip-flop 110 .
  • the signal level of the input data Di of the edge trigger 110 flips from high level to low level after a signal delay Td, and the signal level of the output data Do is always in the entire clock cycle is high level.
  • the clock control signal EN_a toggles from low level to high level via the signal delay Td.
  • the clock signal CK is a logical AND operation result of the clock control signal EN_a and the clock signal CLK.
  • the clock signal CK is a replica version of the clock signal CLK.
  • the signal delay Td is located in the first level phase T1 of the clock signal CLK, and combinatorial logic operations can eliminate possible glitches in the clock signal CK due to the signal delay Td.
  • the clock gating circuit 430 copies the clock signal CLK into the clock signal CK. Due to the power of the previous clock cycle of the clock signal CK The flat state is a low level, and the clock signal CK fails to provide the trigger edge of the edge trigger 110 , that is, the falling edge.
  • the signal level of the output data Do of the edge trigger 110 is consistent with the signal level of the input data Di of the previous trigger edge of the clock signal CK, for example, the high level shown in FIG. 11 .
  • the clock signal CLK reaches the fourth falling edge, and the clock signal CK turns from the high level in the second level stage of the previous clock cycle to the low level.
  • the clock control signal EN_a is a logical exclusive OR operation result of the input data Di and the output data Do of the edge flip-flop 110 .
  • the signal level of the input data Di remains low, and the signal level of the output data Do is always low.
  • the clock control signal EN_a is switched from high level to low level at time t3 and is always at low level in the clock period starting from time t3.
  • the clock signal CK is a logical AND operation result of the clock control signal EN_a and the clock signal CLK. Therefore, at time t3, the clock signal CK is switched from high level to low level and maintained at low level in the clock period starting from time t3.
  • the clock gating circuit 430 maintains the clock signal CK at a low level. Since the level state of the second level stage of the previous clock cycle of the clock signal CK is high level, the clock signal CK provides the trigger edge of the edge trigger 110 , that is, the falling edge.
  • the signal level of the output data Do of the edge trigger 110 is consistent with the signal level of the input data Di of the trigger edge of the current clock cycle of the clock signal CK, for example, the low level shown in FIG. 11 .
  • the aforementioned clock gating circuit 430 generates the clock control signal EN_a based on the data comparison between the input data Di and the output data Do of the edge flip-flop 110 , and controls the transmission of the clock signal according to the state of the clock control signal EN_a.
  • the clock gating circuit 430 shields the clock signal CLK and keeps the clock signal CK at a low level. Therefore, the clock gating circuit 430 can disable clock inversion and data transmission of the edge trigger 110 , thereby reducing dynamic power consumption of the edge trigger 110 due to clock inversion and data transmission.
  • the clock gating circuit 430 replicates the clock signal CLK as the clock signal CK, and provides the triggering edge of the edge trigger in the next clock cycle, therefore, the clock gating circuit 430 can enable the clock inversion of the edge trigger 110 in a single clock cycle, and The data transmission of the edge flip-flop 110 is enabled in a single clock cycle, thereby reducing the dynamic power consumption of the edge flip-flop 110 due to clock inversion and data transmission.
  • a latch is omitted. Even if there is a signal delay Td in the input data Di of the edge trigger 110, as long as the minimum delay Tdmin and the maximum delay Tdmax of the signal delay Td of the input data Di of the edge trigger 110 are set in the first level stage of the clock signal CLK, The glitch of the clock signal CK of the edge trigger 110 can be eliminated.
  • the clock gating circuit 430 In the circuit design of the trigger unit, the clock gating circuit 430 only needs to set the signal delay of the input data Di of the edge trigger 110, thus, the circuit structure and circuit design of the trigger unit can be simplified.
  • the clock gating circuit 430 uses less hardware logic, and its own power consumption is lower.
  • any number of edge flip-flops 110 can share the clock gating circuit 430 to form a flip-flop group.
  • the increased power consumption due to the power consumption of the clock gating circuit 430 itself is much smaller than the reduced power consumption of the edge flip-flops 110 due to clock gating, therefore, the trigger unit Power reduction can always be achieved.
  • Fig. 12 shows a schematic circuit diagram of a trigger unit according to a second embodiment of the present invention.
  • the trigger unit 500 includes an edge trigger 110 and a clock gating circuit 530 .
  • the clock gating circuit 530 is used for gating the clock signal CK of the edge trigger 110 .
  • the edge flip-flop 110 is, for example, a D-type flip-flop.
  • the edge flip-flop 110 includes a data input terminal, a data output terminal and a clock input terminal.
  • the clock gating circuit 530 includes a first input terminal, a second input terminal, a clock input terminal, a clock output terminal, and a control terminal.
  • the first input terminal of the clock gating circuit 530 receives the input data Di
  • the second input terminal receives the output data Do
  • the control terminal receives the second clock control signal EN
  • the clock input terminal receives the clock signal CLK
  • the clock output terminal provides the clock signal CK.
  • the data input end receives input data Di
  • the clock input end receives a clock signal CK
  • the data output end provides output data Do.
  • the edge flip-flop 110 On a trigger edge, such as a rising edge, of the clock signal CK, the edge flip-flop 110 transmits input data from the data input terminal to the data output terminal. Therefore, the signal level corresponding to the output data of the data output terminal of the edge trigger 110 depends on the signal level of the input data at the data input terminal before the trigger edge of the clock signal CK arrives, and one clock after the trigger edge of the clock signal CK remain unchanged throughout the cycle.
  • the data output terminal of the edge trigger 110 may include two complementary output terminals.
  • the clock gating circuit 530 performs a combinational logic operation on the input data Di, the output data Do, the second clock control signal EN and the clock signal CLK to generate the clock signal CK of the edge trigger 110 .
  • the above-mentioned clock gating circuit 530 generates the first clock control signal EN_a based on the data comparison between the input data Di and the output data Do of the edge trigger 110, and according to the state of the first clock control signal EN_a and the received second clock control signal EN Controls the transmission of the clock signal.
  • the second clock control signal EN includes, for example, an active phase of a plurality of clock cycles and an inactive phase of a plurality of clock cycles.
  • the clock gating circuit 530 disables the data comparison, and the clock gating circuit 530 copies the clock signal CLK into the clock signal CK.
  • the second clock control signal EN is invalid, the clock gating circuit 530 enables data comparison, and controls the transmission of the clock signal according to the comparison.
  • the clock gating circuit 530 In the case that the clock gating circuit 530 enables the data comparison, the clock gating circuit 530 maintains the clock signal CK at a predetermined level during the clock period in which the input data Di remains unchanged. During the clock period when the input data Di is inverted, the clock gating circuit 530 copies the clock signal CLK into the clock signal CK. Therefore, the clock gating circuit 530 enables the transmission of the clock signal CLK only in one clock cycle when the input data Di of the edge flip-flop 110 is flipped, thereby minimizing the dynamic power consumption of the edge flip-flop 110 caused by the flip of the clock signal CK. Further, the clock gating circuit 530 provides a trigger edge only in the next clock period when the input data Di of the edge trigger 110 is flipped, so that the dynamic power consumption of the edge trigger 110 due to data transmission can be minimized.
  • edge trigger 110 maintains constant most of the clock cycles of the input data Di Periodically prevent data from entering the subsequent digital circuit, thus avoiding the additional data power consumption caused by the inversion of the data signal of the subsequent combinational logic.
  • FIG. 13 shows a schematic circuit diagram of a clock gating circuit in the trigger unit shown in FIG. 12 .
  • the clock gating circuit 530 and the edge trigger 110 together constitute a trigger unit, and the clock gating circuit 530 provides the clock signal CK to the edge trigger 110 .
  • the clock gating circuit 530 includes an XOR gate 331 , a NOT gate 332 , an OR gate 533 , and a NOT gate 534 .
  • the clock control signal EN_a is generated based on the comparison of the input data Di and the output data Do of the edge trigger 110.
  • the clock signal CK is the clock signal CLK, the inversion signal EN_b of the first clock control signal EN_a, And the logic OR operation result of the received second clock control signal EN.
  • the XOR gate 331 includes a first input terminal, a second input terminal and an output terminal.
  • the NOT gates 332 and 534 include input terminals and output terminals, respectively.
  • the AND gate 533 includes a first input terminal, a second input terminal, a third input terminal and an output terminal.
  • the first data input terminal of the XOR gate 331 receives the input data Di of the edge trigger 110
  • the second data input terminal receives the output data Do of the edge trigger 110
  • the output terminal provides the first clock control signal EN_a.
  • the NOT gate 332 is connected between the output terminal of the exclusive OR gate 331 and the second input terminal of the OR gate 331 for generating an inverted signal EN_b of the first clock control signal EN_a.
  • the first input end of the OR gate 533 receives the clock signal CLK.
  • the second input terminal of the OR gate 533 receives the inverted signal EN_b of the first clock control signal EN_a via the NOT gate 332 .
  • the third input terminal of the OR gate 533 receives the inverted signal EN_c of the second clock control signal EN via the NOT gate 534 .
  • the output terminal of the OR gate 533 provides the clock signal CK.
  • the working principle of the clock gating circuit 530 used in the trigger unit according to the second embodiment is basically the same as that of the clock gating circuit 330 used in the trigger unit according to the first embodiment, and will not be described in detail here.
  • a latch is omitted.
  • the clock gating circuit 530 enables or disables the data comparison function according to the received second clock control signal EN.
  • the clock gating circuit 530 enables the data comparison function, and when the second clock control signal EN is not valid, the clock gating circuit 530 disables the data comparison function.
  • the clock gating circuit 530 In the circuit design of the trigger unit, the clock gating circuit 530 only needs to set the signal delay of the input data Di of the edge trigger 110, thus, the circuit structure and circuit design of the trigger unit can be simplified.
  • the clock gating circuit 530 uses less hardware logic, and its own power consumption is lower.
  • any number of edge flip-flops 110 can share the clock gating circuit 530 to form a flip-flop group.
  • the increased power consumption due to the power consumption of the clock gating circuit 530 itself is much smaller than the reduced power consumption of the edge flip-flops 110 due to clock gating. Therefore, the trigger unit Power reduction can always be achieved.
  • Fig. 14 shows a schematic circuit diagram of a trigger unit according to a third embodiment of the present invention.
  • the trigger unit 600 includes an edge trigger 210 and a clock gating circuit 630 .
  • the clock gating circuit 630 is used for gating the clock signal CK of the edge trigger 210 .
  • the edge flip-flop 210 is, for example, a D-type flip-flop.
  • the edge flip-flop 210 includes a data input terminal, a first data output terminal, a second data output terminal and a clock input terminal.
  • the clock gating circuit 630 includes a first input terminal, a second input terminal, a clock input terminal, and a clock output terminal.
  • a first input terminal of the clock gating circuit 630 receives input data Di, a second input terminal receives output data Do, a clock input terminal receives a clock signal CLK, and a clock output terminal provides a clock signal CK.
  • the data input end of the edge trigger 210 receives the input data Di, the clock input end receives the clock signal CK, the first data output end provides the output data Do, and the second data output end provides the inversion signal Dn of the output data Do.
  • the first data output terminal and the second data output terminal of the edge trigger 210 are two complementary output terminals.
  • the data input end of the edge flip-flop 210 is connected to the second data output end, therefore, the edge flip-flop 210 always uses the inverted signal Dn of its own output data Do as input data.
  • the edge flip-flop 210 On a triggering edge, such as a rising edge, of the clock signal CK, the edge flip-flop 210 transmits input data from the data input terminal to the data output terminal. Therefore, the signal level corresponding to the output data of the data output terminal of the edge trigger 210 depends on the signal level of the input data at the data input terminal before the trigger edge of the clock signal CK arrives, and at the trigger edge of the clock signal CK remains unchanged for one clock cycle after the edge.
  • the clock gating circuit 630 performs a combinational logic operation on the input data Di, the output data Do and the clock signal CLK to generate the clock signal CK of the edge flip-flop 210 .
  • the aforementioned clock gating circuit 630 generates the clock control signal EN_a based on the data comparison between the input data Di and the output data Do of the edge flip-flop 210 , and controls the transmission of the clock signal according to the state of the clock control signal EN_a.
  • the clock gating circuit 630 maintains the clock signal CK at a predetermined level. During the clock period when the input data Di is inverted, the clock gating circuit 630 copies the clock signal CLK into the clock signal CK. Therefore, the clock gating circuit 630 enables the transmission of the clock signal CLK only in one clock cycle when the input data Di of the edge flip-flop 210 is flipped, thereby minimizing the dynamic power consumption of the edge flip-flop 210 caused by the flip-flop of the clock signal CK.
  • the clock gating circuit 630 only provides a triggering edge in the next clock period when the input data Di of the edge trigger 210 is flipped, so that the dynamic power consumption of the edge trigger 210 due to data transmission can be minimized.
  • the edge flip-flop 210 provides the inversion signal of the output data Do as input data from the input terminal to the output terminal. Further, the edge trigger 210 prevents data from entering into subsequent digital circuits at other times, thus avoiding additional data power consumption caused by inversion of data signals of subsequent combinational logic.
  • FIG. 15 shows a schematic circuit diagram of a clock gating circuit in the trigger unit shown in FIG. 14 .
  • the clock gating circuit 630 and the edge trigger 210 together constitute a trigger unit, and the clock gating circuit 630 provides the clock signal CK to the edge trigger 210 .
  • the clock gating circuit 630 includes an exclusive OR gate 331 , a NOT gate 332 and an OR gate 533 .
  • the clock control signal EN_a is generated based on the comparison of the input data Di and the output data Do of the edge trigger 210
  • the clock signal CK is the logic OR operation of the clock signal CLK and the inversion signal EN_b of the clock control signal EN_a result.
  • the working principle of the clock gating circuit 630 used in the trigger unit according to the third embodiment is basically the same as that of the clock gating circuit 330 used in the trigger unit according to the first embodiment, and will not be described in detail here.
  • the working principle of the edge trigger 210 in the trigger unit according to the third embodiment is basically the same as that of the edge trigger 110 used in the flip-flop according to the first embodiment The basics are the same, and only the main differences between the two are described here.
  • the input data Di received by the trigger unit 600 according to the third embodiment is only used for clock gating, and the edge flip-flop 210 generates input data based on its own output data Dn, so the edge flip-flop 210 does not need to receive any input data from the outside.
  • the data input terminal of the edge trigger is coupled to the second data output terminal to receive the inversion signal Dn of the output data as input data.
  • a latch is omitted. Even if there is a signal delay Td in the input data Di of the edge trigger 210, as long as the minimum delay Tdmin and the maximum delay Tdmax of the signal delay Td of the input data Di of the edge trigger 210 are set in the first level stage of the clock signal CLK, The glitch of the clock signal CK of the edge trigger 210 can be eliminated.
  • the edge trigger 210 generates input data based on its own output data Dn, so the edge trigger 210 does not need to receive any input data from the outside, thereby reducing the adverse effect of the signal delay fluctuation of the external input data on the working stability of the edge trigger 210 .
  • the clock gating circuit 630 only needs to set the signal delay of the input data Di of the edge trigger 210, thus, the circuit structure and circuit design of the trigger unit can be simplified.
  • the clock gating circuit 630 uses less hardware logic, and its own power consumption is lower.
  • any number of edge flip-flops 210 can share the clock gating circuit 630 to form a flip-flop group.
  • the increased power consumption due to the power consumption of the clock gating circuit 630 itself is much smaller than the reduced power consumption of the edge flip-flops 210 due to clock gating. Therefore, the trigger unit Power reduction can always be achieved.
  • the flip-flop triggered on the rising edge and the falling edge of the clock signal is taken as an example for illustration, and the edge trigger in the trigger unit is only an example of a structure.
  • the present invention is not limited thereto. It can be understood that other edge triggers, such as edge triggers with a reset function, can also be technically improved by applying the present invention.

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Abstract

一种基于数据比较进行时钟门控的触发单元。该触发单元包括：边沿触发器和时钟门控电路，时钟门控电路根据输入数据和输出数据的数据比较结果启用或屏蔽第一时钟信号以产生第二时钟信号，第二时钟信号提供边沿触发器的触发边沿，时钟门控电路在输入数据翻转的时钟周期中，将第一时钟信号复制为第二时钟信号，在输入数据维持不变的时钟周期中，将第二时钟信号维持为预定电平。该触发单元仅在输入数据翻转的时钟周期中启用边沿触发器的时钟翻转，因而可以提高电路性能和降低功耗。

Description

基于数据比较进行时钟门控的触发单元
本申请要求了申请日为2022年1月28日、申请号为202210107334.3、名称为“基于数据比较进行时钟门控的触发单元”的中国发明申请的优先权，并且通过参照上述中国发明申请的全部说明书、权利要求、附图和摘要的方式，将其引用于本申请。
技术领域
本发明涉及集成电路技术，更具体地，涉及基于数据比较进行时钟门控的触发单元。
背景技术
电子设计自动化软件(EDA)是集成电路的功能设计、综合、验证、物理设计等流程的重要工具。在数字电路设计EDA中，标准单元库是集成电路芯片后端设计过程中的基础部分。采用预先设计好的优化的库单元进行自动逻辑综合和版图布局布线，可以提高设计效率。经过优化的库单元可以提高电路性能和降低功耗。
在集成电路的数字部分中，采用门电路将多个信号经过组合逻辑产生逻辑运算结果，采用边沿触发器存储逻辑运算结果。按照逻辑运算的不同，门电路可以分为与门、或门、非门、与非门、或门、与或门、异或门等。门电路的逻辑运算结果例如是脉冲信号，基于脉冲信号产生与逻辑状态相对应的稳态电平信号。
边沿触发器是具有记忆功能的信息存储器件，用于存储记忆逻辑运算结果。例如，边沿触发器是构成多种时序数字电路模块中的最基本逻辑单元，在数字电路模块中是一种重要的单元电路。参见图1和图2，根据边沿触发器的类型，边沿触发器110在时钟信号的上升沿或下降沿触发，允许输入数据从输入端传输到输出端以获得输出数据。边沿触发器110例如是D型触发器。例如，D型触发器在时钟信号的触发边沿传 输数据，在下一次触发边沿前维持数据不变。
边沿触发器的功耗包括静态功耗和动态功耗，其中，静态功耗主要由泄漏电流引起，动态功耗主要由信号翻转功耗引起。边沿触发器的数据信号翻转导致后级组合逻辑产生附加的数据功耗，时钟信号的翻转也会产生边沿触发器自身的时钟功耗。
因此，期望对数字电路EDA标准单元库中的边沿触发器进行优化设计，进一步降低边沿触发器的动态功耗。
发明内容
鉴于上述问题，本发明的目的在于提供基于数据比较进行时钟门控的触发单元，仅在输入数据翻转的时钟周期中启用边沿触发器的时钟翻转，以提高电路性能和降低功耗。
根据本发明，提供一种触发单元，包括：边沿触发器，包括数据输入端、时钟输入端和第一数据输出端；以及时钟门控电路，包括第一输入端、第二输入端、时钟输入端和输出端，其中，所述时钟门控电路的第一输入端接收所述边沿触发器的输入数据，第二输入端接收所述边沿触发器的输出数据，时钟输入端接收第一时钟信号，输出端与所述边沿触发器的时钟输入端耦接以提供第二时钟信号，所述时钟门控电路根据所述输入数据和所述输出数据的数据比较结果启用或屏蔽所述第一时钟信号以产生所述第二时钟信号，所述第二时钟信号提供所述边沿触发器的触发边沿，所述时钟门控电路在所述输入数据翻转的时钟周期中，将所述第一时钟信号复制为所述第二时钟信号，在所述输入数据维持不变的时钟周期中，将所述第二时钟信号维持为预定电平。
优选地，所述第一时钟信号的时钟周期包括连续的第一电平阶段和第二电平阶段，所述输入数据在所述第一时钟信号的第一电平阶段翻转。
优选地，所述预定电平为所述第一电平阶段的电平，所述第二时钟信号在输入数据翻转的时钟周期的下一个时钟周期提供触发边沿。
优选地，所述第一电平阶段的开始边沿为上升沿。
优选地，所述时钟门控电路包括：异或门，包括第一输入端、第二输入端和输出端，所述第一输入端和所述第二输入端分别接收所述边沿 触发器的输入数据和输出数据，所述输出端提供第一时钟控制信号；或门，包括第一输入端、第二输入端和输出端，所述第一输入端接收所述第一时钟信号；以及非门，包括输入端和输出端，所述非门连接在所述异或门的输出端和所述或门的第二输入端之间，其中，所述非门将所述第一时钟控制信号反相后提供至所述或门的第二输入端，所述或门的输出端提供所述第二时钟信号。
优选地，所述或门还包括第三输入端，所述第三输入端接收第二时钟控制信号的反相信号。
优选地，在所述第二时钟控制信号有效时，所述时钟门控电路启用数据比较功能，在所述第二时钟控制信号无效时，所述时钟门控电路禁用数据比较功能。
优选地，所述第一电平阶段的开始边沿为下降沿。
优选地，所述时钟门控电路包括：异或门，包括第一输入端、第二输入端和输出端，所述第一输入端和所述第二输入端分别接收所述边沿触发器的输入数据和输出数据，所述输出端提供第一时钟控制信号；以及与门，包括第一输入端、第二输入端和输出端，所述第一输入端接收所述第一时钟信号，所述第二输入端接收所述第一时钟控制信号，所述输出端提供所述第二时钟信号。
优选地，所述与门还包括第三输入端，所述第三输入端接收第二时钟控制信号。
优选地，在所述第二时钟控制信号有效时，所述时钟门控电路启用数据比较功能，在所述第二时钟控制信号无效时，所述时钟门控电路禁用数据比较功能。
优选地，所述边沿触发器的数据输入端接收自身的输出数据的反相信号作为输入数据。
优选地，所述边沿触发器还包括第二数据输出端，所述边沿触发器的第一数据输出端和第二数据输出端分别提供所述边沿触发器的输出数据和所述输出数据的反相信号，其中，所述边沿触发器的数据输入端与所述第二数据输出端彼此耦接以接收自身的输出数据的反相信号。
优选地，所述第一时钟控制信号和所述第二时钟控制信号各自的高 电平表示有效状态，低电平表示无效状态。
优选地，所述边沿触发器在所述触发边沿接收所述数据输入端的输入数据并传送至所述第一数据输出端。
根据本发明的实施例，在触发单元中，时钟门控电路在输入数据翻转的时钟周期中，将第一时钟信号复制为第二时钟信号，在输入数据维持不变的时钟周期中，将第二时钟信号维持为预定电平。因此，时钟门控电路仅在边沿触发器的输入数据翻转的一个时钟周期中启用时钟信号的传输，因而可以最小化边沿触发器因时钟翻转产生的动态功耗。进一步地，时钟门控电路仅在边沿触发器的输入数据翻转的下一个时钟周期提供一个触发边沿，因而可以最小化边沿触发器因数据传输产生的动态功耗。
进一步地，边沿触发器在输入数据维持不变的大多数时钟周期阻止数据进入后级数字电路中，因而可以避免后级组合逻辑的数据信号翻转产生附加的数据功耗。
在触发单元中，利用时钟门控电路在时钟控制信号翻转周期中的电路特性，即使时钟门控电路省去了附加的锁存器，也可以消除时钟门控电路产生的时钟信号的毛刺，以及减少时钟门控电路的逻辑元件数量和降低时钟门控电路的功耗。由于时钟门控电路自身的工作功耗较低，时钟门控电路本身的功耗而增加的功耗远小于边沿触发器因时钟门控而减少的功耗。
进一步地，触发单元中的任意数量的边沿触发器可以组成共用时钟门控电路的触发器组。对于触发器组包含任意数量的边沿触发器的情形，例如，一个，两个，或多个，触发单元始终可以实现功耗降低。
进一步地，在数字电路设计中将边沿触发器的输入数据的信号延迟的最小延迟和最大延迟设置在时钟信号的第一电平阶段中，可以避免边沿触发器的时钟信号中出现毛刺而导致边沿触发器不能正常工作。即使在触发单元中简化了时钟门控电路的电路设计，也仍然可以可靠地禁用边沿触发器的时钟翻转和数据传输，以降低动态功耗。
进一步地，该触发单元的电路设计简化且版图布局面积减小，可以与现有的边沿触发器设计一起作为标准单元库的库单元，在不同的条件 下应用以提高数字电路的性能和设计效率。
在优选的实施例中，边沿触发器的数据输入端接收自身的输出数据的反相信号作为输入数据。边沿触发器包括第一数据输出端和第二数据输出端，分别提供所述边沿触发器的输出数据和所述输出数据的反相信号，边沿触发器的数据输入端与所述第二数据输出端彼此耦接。一方面，前级逻辑电路仅仅需要向触发单元中的时钟门控电路提供输入数据，而无需向触发单元中的边沿触发器提供输入数据，可以减轻前级逻辑电路的负载压力。另一方面，边沿触发器无需从外部接收任何输入数据，因而可以减少外部的输入数据的信号延迟波动对边沿触发器的工作稳定性的不利影响。
附图说明
通过以下参照附图对本发明实施例的描述，本发明的上述以及其他目的、特征和优点将更为清楚。
图1示出集成电路中的边沿触发器的示意性电路图。
图2示出集成电路中的边沿触发器的波形图。
图3示出根据现有技术的一种触发单元的示意性电路图。
图4示出根据现有技术的另一种触发单元的示意性电路图。
图5示出图4所示触发单元中的时钟门控电路的示意性电路图。
图6示出图4所示触发单元中的时钟门控电路的波形图。
图7示出根据本发明第一实施例的触发单元的示意性电路图。
图8示出图7所示触发单元中的一种时钟门控电路的示意性电路图。
图9示出图7所示触发单元中的另一种时钟门控电路的示意性电路图。
图10示出图8所示时钟门控电路的波形图。
图11示出图9所示时钟门控电路的波形图。
图12示出根据本发明第二实施例的触发单元的示意性电路图。
图13示出图12所示触发单元中的时钟门控电路的示意性电路图。
图14示出根据本发明第三实施例的触发单元的示意性电路图。
图15示出图14所示触发单元中的时钟门控电路的示意性电路图。
具体实施方式
以下将参照附图更详细地描述本发明。在各个附图中，相同的元件采用类似的附图标记来表示。为了清楚起见，附图中的各个部分没有按比例绘制。此外，可能未示出某些公知的部分。
在下文中描述了本发明的许多特定的细节，例如器件的结构、材料、尺寸、处理工艺和技术，以便更清楚地理解本发明。但正如本领域的技术人员能够理解的那样，可以不按照这些特定的细节来实现本发明。
本发明可以各种形式呈现，以下将描述其中一些示例。为表述方便，以下实施例的描述均以上升沿触发的边沿触发器为例进行说明。
图3示出根据现有技术的一种触发单元的示意性电路图。触发单元100包括边沿触发器110和数据选择器120。数据选择器120用于边沿触发器110的输入数据Di的门控。在本实施例中，边沿触发器110例如为D型触发器。
边沿触发器110包括数据输入端、数据输出端和时钟输入端。数据选择器120包括控制端、第一数据输入端、第二数据输入端、输出端。数据选择器120的控制端接收数据控制信号EN，第一数据输入端接收边沿触发器110的输入数据Di，第二数据输入端接收边沿触发器120的输出数据Do，输出端提供选定数据Ds。边沿触发器110的数据输入端接收选定数据Ds，时钟输入端接收时钟信号CLK，数据输出端提供输出数据Do。
在时钟信号CLK的触发边沿，例如上升沿，边沿触发器110将输入数据从数据输入端传送至数据输出端。因而，边沿触发器110的数据输出端的输出数据相对应的信号电平取决于时钟信号CLK的上升沿到来之前数据输入端的输入数据的信号电平，并且在时钟信号CLK的上升沿之后的一个时钟周期中维持不变。边沿触发器110的数据输出端可以包括两个互补输出端。
数据选择器120在数据控制信号EN有效时将输入数据Di提供至边沿触发器110的输入端，在数据控制信号EN无效时，数据选择器120将边沿触发器110的第一输入端与输出端之间彼此连接，从而屏蔽边沿 触发器110的输入数据。数据选择器120也将维持边沿触发器110的输出数据不变，因而可以禁用边沿触发器110的数据接收。
在上述的触发单元中，数据选择器120根据数据控制信号EN的状态控制边沿触发器110的数据接收。
在数据选择器120禁用边沿触发器110的数据接收的情形下，边沿触发器110不能接收输入数据，而是维持输出数据不变，因而可以阻止输入数据进入后级数字电路中，可以避免后级组合逻辑的数据信号翻转产生附加的数据功耗。
然而，数据选择器120不能禁用边沿触发器110的时钟翻转。边沿触发器110的时钟输入端始终接收时钟信号CLK。在时钟信号CLK的触发边沿传输数据，因而不能降低边沿触发器110因时钟信号CLK翻转产生的动态功耗。
图4示出根据现有技术的另一种触发单元的示意性电路图。触发单元200包括边沿触发器110和时钟门控电路130。时钟门控电路130用于边沿触发器110时钟信号CK的门控。在本实施例中，边沿触发器110例如为D型触发器。
边沿触发器110包括数据输入端、数据输出端和时钟输入端。时钟门控电路130包括输入端、输出端和控制端。时钟门控电路130的输入端接收时钟信号CLK，输出端提供时钟信号CK，控制端接收时钟控制信号EN。边沿触发器110的数据输入端接收输入数据Di，时钟输入端接收时钟信号CK，数据输出端提供输出数据Do。
在时钟信号CK的触发边沿，例如上升沿，边沿触发器110将输入数据从数据输入端传送至数据输出端。因而，边沿触发器110的数据输出端的输出数据相对应的信号电平取决于时钟信号CK的触发边沿到来之前数据输入端的输入数据的信号电平，并且在时钟信号CK的触发边沿之后的一个时钟周期中维持不变。边沿触发器110的数据输出端可以包括两个互补输出端。
时钟门控电路130对输入数据Di、输出数据Do和时钟信号CLK进行组合逻辑运算以产生边沿触发器110的时钟信号CK。
在上述的触发单元中，时钟门控电路130根据时钟控制信号EN的 状态控制时钟信号的传输。
在时钟控制信号EN维持有效的时钟周期中，时钟门控电路130将时钟信号CLK复制为时钟信号CK，时钟信号CK提供至边沿触发器110的时钟输入端，在时钟控制信号EN维持无效的时钟周期中，时钟门控电路130屏蔽时钟信号CLK，以及将时钟信号CK维持为预定电平。
在时钟信号CK维持为预定电平的情形下，时钟信号CK不能提供边沿触发器110的触发边沿，因此可以禁用边沿触发器110的时钟翻转和数据传输，因而可以降低边沿触发器110因时钟信号CK翻转产生的动态功耗以及因数据传输产生的动态功耗。进一步地，边沿触发器110阻止数据进入后级数字电路中，因而可以避免后级组合逻辑的数据信号翻转产生附加的数据功耗。
图5示出图4所示触发单元中的时钟门控电路的示意性电路图。参见图4，时钟门控电路130和边沿触发器110共同组成触发单元，时钟门控电路130向边沿触发器110提供时钟信号CK。
时钟门控电路130包括锁存器131和与门132。锁存器131在时钟信号CLK的第一电平阶段T1对时钟控制信号EN进行锁存，在时钟信号CLK的第二电平阶段T2传输时钟控制信号EN，与门对锁存信号EN_a和时钟信号CLK进行逻辑与运算以产生时钟信号CK。
锁存器131包括第一输入端、第二输入端和输出端。与门132包括第一输入端、第二输入端和输出端。锁存器131的第一输入端接收时钟信号CLK，第二输入端接收时钟控制信号EN。与门132的第一输入端接收时钟信号CLK，第二输入端与锁存器131的输出端相连接，输出端提供时钟信号CK。
以上升沿触发的边沿触发器为例，时钟控制信号EN以高电平表示有效状态、低电平表示无效状态为例进行说明。时钟信号CLK的每个时钟周期包括相邻上升沿之间的连续的第一电平阶段T1和第二电平阶段T2，第一电平阶段T1和第二电平阶段T2分别具有高电平和低电平。时钟信号CK提供边沿触发器110的触发边沿，边沿触发器110在触发边沿将输入数据从输入端传送至输出端。
参见图6，输入数据Di和时钟控制信号EN各自存在着相对于时钟 信号边沿的信号延迟Td。信号延迟Td的最小延迟Tdmin和最大延迟Tdmax之间的区域分别采用阴影部分表示。时钟控制信号EN的信号延迟Td在最小延迟Tdmin和最大延迟Tdmax之间变化。
如图6所示，最小延迟Tdmin和最大延迟Tdmax分别位于第一电平阶段T1和第二电平阶段T2中，时钟控制信号EN的翻转动作既可能发生在时钟信号CLK的第一电平阶段T1，也可能发生在时钟信号CLK的第二电平阶段T2。
在时刻t0，时钟信号CLK到达第一个上升沿，时钟控制信号EN有效。在时刻t0开始的一个时钟周期中，时钟控制信号EN从有效状态翻转为无效状态。在时钟信号CLK的第一电平阶段T1，锁存器131的输出端的锁存信号EN_a信号电平保持为前一状态，即，高电平。在时钟信号CLK的第二电平阶段T2，锁存器131将时钟控制信号EN从输入端传送至输出端。
如果时钟控制信号EN的信号延迟Td小于等于时钟信号CLK的第一电平阶段T1，则在时钟控制信号翻转的时钟周期中，锁存信号EN_a是时钟信号CLK的复制版本。如果时钟控制信号EN的信号延迟Td大于时钟信号CLK的第一电平阶段T1，则在时钟信号CLK的第二电平阶段T2，锁存信号EN_a中出现毛刺。时钟信号CK是时钟信号CLK和锁存信号EN_a的逻辑与运算结果，该逻辑与运算可以消除锁存信号EN_a在时钟信号CLK第二电平阶段T2的毛刺。
因此，在时刻t0开始的一个时钟周期中，时钟门控电路130将时钟信号CLK复制为时钟信号CK且提供时钟信号CK的上升沿，边沿触发器110的输出数据Do的信号电平与时刻t0的输入数据Di的信号电平一致，例如图6所示的低电平。
在时刻t1，时钟信号CLK到达第二个上升沿，时钟控制信号EN无效。在时刻t1开始的一个时钟周期中，时钟控制信号EN维持无效状态。在时钟信号CLK的第一电平阶段T1，锁存器131的输出端的锁存信号EN_a信号电平保持为前一状态，即，低电平。在时钟信号CLK的第二电平阶段T2，锁存器131将时钟控制信号EN从输入端传送至输出端。在这个时钟周期内，时钟控制信号EN维持低电平状态，因此EN_a也 保持低电平，时钟信号CK经时钟信号CLK和锁存信号EN_a的与运算，结果也保持低电平。
在时刻t2，时钟信号CLK到达第三个上升沿，时钟控制信号EN无效。在时刻t2开始的一个时钟周期中，时钟控制信号EN从无效状态翻转为有效状态。在时钟信号CLK的第一电平阶段T1，锁存器131的输出端的锁存信号EN_a信号电平保持为前一状态，即，低电平。在时钟信号CLK的第二电平阶段T2，锁存器131将时钟控制信号EN从输入端传送至输出端。如果时钟控制信号EN的信号延迟Td小于等于时钟信号CLK的第一电平阶段T1，则在时钟控制信号翻转的时钟周期中，锁存信号EN_a是时钟信号CLK的复制版本。如果时钟控制信号EN的信号延迟Td大于时钟信号CLK的第一电平阶段T1，则在时钟信号CLK的第二电平阶段T2，锁存信号EN_a中出现毛刺。时钟信号CK是时钟信号CLK和锁存信号EN_a的逻辑与运算结果，该逻辑与运算可以消除锁存信号EN_a在时钟信号CLK第二电平阶段T2的毛刺。
因此，在时刻t1开始的两个时钟周期中，时钟门控电路130屏蔽时钟信号CLK且未提供时钟信号CK的上升沿，边沿触发器110的输出数据Do的信号电平与上一时钟周期的信号电平一致，例如图6所示的低电平。
在时刻t3，时钟信号CLK到达第四个上升沿，时钟控制信号EN有效。在时刻t3开始的一个时钟周期中，时钟控制信号EN维持有效状态。在时钟信号CLK的第一电平阶段T1，锁存器131的输出端的锁存信号EN_a信号电平保持为前一状态，即，高电平。在时钟信号CLK的第二电平阶段T2，锁存器131将时钟控制信号EN从输入端传送至输出端。在这个时钟周期内，时钟控制信号EN维持高电平状态，因此，锁存信号EN_a也维持高电平，时钟信号CK经时钟信号CLK和锁存信号EN_a的与运算，因此，时钟信号CK是时钟信号CLK的复制版本。
因此，在时刻t3开始的一个时钟周期中，时钟门控电路130将时钟信号CLK复制为时钟信号CK且提供时钟信号CK的上升沿，边沿触发器110的输出数据Do的信号电平与时刻t3的输入数据Di的信号电平一致，例如图5所示的高电平。
上述的时钟门控电路130根据时钟控制信号EN的状态控制时钟信号的传输。
在时钟控制信号EN从有效状态翻转至无效状态的时钟周期中，时钟门控电路130将时钟信号CLK复制为时钟信号CK。此时，时钟信号CK提供边沿触发器110的触发边沿，时钟门控电路130允许边沿触发器110的时钟翻转和数据传输，边沿触发器110提供的输出数据Do为当前触发边沿的输入数据Di。
在时钟控制信号EN从无效状态翻转至有效状态的时钟周期中，时钟门控电路130屏蔽时钟信号CLK，以及将时钟信号CK维持为预定电平。此时，时钟信号CK未能提供边沿触发器110的触发边沿，时钟门控电路130禁用边沿触发器110的时钟翻转和数据传输，边沿触发器110维持前一触发边沿的输入数据Di，因而可以降低边沿触发器110的动态功耗。
上述的时钟门控电路130对时钟控制信号EN的时序要求不高。如果希望在预定时刻禁用数据传输，则可以在预定时刻之前的最后一个整时钟周期中完成时钟控制信号EN从有效状态至无效状态的翻转动作，在预定时刻开始的最后一个时钟周期中完成时钟控制信号EN从无效状态至有效状态的翻转动作。
本发明人注意到，在数字电路EDA的标准单元库中提供的触发单元使用上述的时钟门控电路130。时钟门控电路130包括锁存器131，用于消除边沿触发器110的时钟信号CK中可能出现的毛刺。
然而，在锁存器131中使用的硬件逻辑较多，导致时钟门控电路130自身的工作功耗过高。时钟门控电路130自身的工作功耗甚至有可能超过边沿触发器因时钟门控而减少的功耗。在触发单元中，时钟门控电路130可以为触发器组中的多个边沿触发器110提供时钟信号CK。如果使用时钟门控电路130，则在电路设计上的限制是触发器组中的边沿触发器数量不少于3～8个，才能确保触发单元200的时钟门控电路130自身的工作功耗小于若干个边沿触发器110因时钟门控电路130而减少的功耗。
进一步地，本发明人注意到，边沿触发器110的输入数据的信号延 迟有可能可以通过设计设置为二者均位于时钟信号CLK的同一电平阶段中，基于边沿触发器110的输入数据和输出数据的比较，可以获得相应延迟的时钟控制信号EN_a。
本发明人设计了下文详细描述的基于数据比较的时钟门控电路330和430，将基于数据比较获得的时钟控制信号EN与重新设计的逻辑电路相结合，在未使用锁存器的情形下也可以获得与时钟门控电路130相同的功能。
在数字电路EDA的标准单元库中，可以将时钟门控电路330和时钟门控电路430用于重新设计的触发单元。因此，可以进一步降低集成电路功耗，降低触发单元的成本且减小时钟门控电路自身的功耗，从而突破上述电路设计上的限制。
图7示出根据本发明第一实施例的触发单元的示意性电路图。触发单元300包括边沿触发器110和时钟门控电路330。时钟门控电路330用于边沿触发器110时钟信号CK的门控。在本实施例中，边沿触发器110例如为D型触发器。
边沿触发器110包括数据输入端、数据输出端和时钟输入端。时钟门控电路330包括第一输入端、第二输入端、时钟输入端、以及时钟输出端。时钟门控电路330的第一输入端接收输入数据Di，第二输入端接收输出数据Do，时钟输入端接收时钟信号CLK，时钟输出端提供时钟信号CK。边沿触发器110的数据输入端接收输入数据Di，时钟输入端接收时钟信号CK，数据输出端提供输出数据Do。
在时钟信号CK的触发边沿，例如上升沿，边沿触发器110将输入数据从数据输入端传送至数据输出端。因而，边沿触发器110的数据输出端的输出数据相对应的信号电平取决于时钟信号CK的触发边沿到来之前数据输入端的输入数据的信号电平，并且在时钟信号CK的触发边沿之后的一个时钟周期中维持不变。边沿触发器110的数据输出端可以包括两个互补输出端。
时钟门控电路330对输入数据Di、输出数据Do和时钟信号CLK进行组合逻辑运算以产生边沿触发器110的时钟信号CK。
上述的时钟门控电路330基于边沿触发器110的输入数据Di和输出 数据Do的数据比较产生时钟控制信号EN_a，以及根据时钟控制信号EN_a的状态控制时钟信号的传输。
在输入数据Di维持不变的时钟周期中，时钟门控电路330将时钟信号CK维持为预定电平。在输入数据Di翻转的时钟周期中，时钟门控电路330将时钟信号CLK复制为时钟信号CK。因此，时钟门控电路330仅在边沿触发器110的输入数据Di翻转的一个时钟周期中启用时钟信号CLK的传输，因而可以最小化边沿触发器110因时钟信号CK翻转产生的动态功耗。进一步地，时钟门控电路330仅在边沿触发器110的输入数据Di翻转的下一个时钟周期提供一个触发边沿，因而可以最小化边沿触发器110因数据传输产生的动态功耗。
进一步地，边沿触发器110在输入数据Di维持不变的大多数时钟周期阻止数据进入后级数字电路中，因而可以避免后级组合逻辑的数据信号翻转产生附加的数据功耗。
图8示出图7所示触发单元中的一种时钟门控电路的示意性电路图。参见图7，时钟门控电路330和边沿触发器110共同组成触发单元，时钟门控电路330向边沿触发器110提供时钟信号CK。
时钟门控电路330包括异或门331、非门332及或门333。在时钟门控电路330中，基于边沿触发器110的输入数据Di和输出数据Do的比较产生时钟控制信号EN_a，时钟信号CK是时钟信号CLK和时钟控制信号EN_a的反相信号EN_b的逻辑或运算结果。
异或门331包括第一输入端、第二输入端和输出端。非门332包括输入端和输出端。或门333包括第一输入端、第二输入端和输出端。异或门331的第一数据输入端接收边沿触发器110的输入数据Di，第二数据输入端接收边沿触发器110的输出数据Do，输出端提供时钟控制信号EN_a。非门332连接在异或门331的输出端和或门331的第二输入端之间，用于产生时钟控制信号EN_a的反相信号EN_b。或门333的第一输入端接收时钟信号CLK。或门333的第二输入端经由非门332接收时钟控制信号EN_a的反相信号EN_b。或门333的输出端提供时钟信号CK。
在本实施例中，以上升沿触发的边沿触发器为例，时钟控制信号EN_a以高电平表示有效状态、低电平表示无效状态为例进行说明。时钟 信号CLK的每个时钟周期包括相邻上升沿之间的连续的第一电平阶段T1和第二电平阶段T2，第一电平阶段T1和第二电平阶段T2分别具有高电平和低电平。时钟信号CK提供上升沿作为边沿触发器110的触发边沿，边沿触发器110在触发边沿将输入数据从输入端传送至输出端。
参见图10，边沿触发器110的输入数据Di存在着相对于时钟信号边沿的信号延迟Td。信号延迟Td的最小延迟Tdmin和最大延迟Tdmax之间的区域分别采用阴影部分表示。边沿触发器110的输入数据Di的信号延迟Td在最小延迟Tdmin和最大延迟Tdmax之间变化。
在本实施例中，基于边沿触发器110的输入数据Di和输出数据Do的数据比较获得时钟门控电路的时钟控制信号EN_a，时钟控制信号EN_a的信号延迟Td与输入数据Di的信号延迟Td大致相同。
采用优化的电路设计和电路仿真，可以计算并设置边沿触发器110的输入数据Di的信号延迟Td，使得信号延迟Td的最小延迟Tdmin和最大延迟Tdmax的范围内位于时钟信号CLK的选定的第一电平阶段T1中。
相应地，时钟控制信号EN_a的信号延迟Td的最小延迟Tdmin和最大延迟Tdmax的范围内位于时钟信号CLK的第一电平阶段T1中。时钟控制信号EN_a的翻转动作仅可能发生在时钟信号CLK的第一电平阶段T1。第一电平阶段T1的开始边沿为上升沿。
在时刻t0，时钟信号CLK到达第一个上升沿，时钟信号CK维持为前一时钟周期的高电平。
时钟控制信号EN_a是边沿触发器110的输入数据Di和输出数据Do的逻辑异或运算结果。在时刻t0开始的时钟周期中，边沿触发器110的输入数据Di的信号电平经由信号延迟Td后从低电平翻转为高电平，输出数据Do的信号电平在整个时钟周期中始终为低电平。作为逻辑异或运算的结果，时钟控制信号EN_a经由信号延迟Td从低电平翻转为高电平，时钟控制信号EN_a的反相信号EN_b经由信号延迟Td从高电平翻转为低电平。
时钟信号CK是时钟控制信号EN_a的反相信号EN_b和时钟信号CLK的逻辑或运算结果。在时刻t0开始的一个时钟周期中，时钟信号 CK是时钟信号CLK的复制版本。尽管时钟控制信号EN_a的反相信号EN_b存在着信号延迟Td，然而，该信号延迟Td位于时钟信号CLK的第一电平阶段T1中，利用组合逻辑运算可以消除时钟信号CK由于信号延迟Td可能产生的毛刺。
因此，在时刻t0开始的一个时钟周期中，时钟门控电路330将时钟信号CLK复制为时钟信号CK。由于时钟信号CK的前一时钟周期的电平状态为高电平，时钟信号CK未能提供边沿触发器110的触发边沿，即，上升沿。边沿触发器110的输出数据Do的信号电平与时钟信号CK的前一个触发边沿的输入数据Di的信号电平一致，例如图10所示的低电平。
在时刻t1，时钟信号CLK到达第二个上升沿，时钟信号CK从前一时钟周期的第二电平阶段的低电平翻转为高电平。
时钟控制信号EN_a是边沿触发器110的输入数据Di和输出数据Do的逻辑异或运算结果。在时刻t1开始的一个时钟周期中，输入数据Di的信号电平维持为高电平，输出数据Do的信号电平则始终为高电平。作为逻辑异或运算的结果，时钟控制信号EN_a在时刻t1从高电平翻转为低电平且在时刻t1开始的时钟周期中始终为低电平，时钟控制信号EN_a的反相信号EN_b在时刻t1开始的时钟周期中始终为高电平。
时钟信号CK是时钟控制信号EN_a的反相信号EN_b和时钟信号CLK的逻辑或运算结果。因此，在时刻t1，时钟信号CK从低电平翻转为高电平且在时刻t1开始的时钟周期中维持为高电平。
因此，在时刻t1开始的一个时钟周期中，时钟门控电路330将时钟信号CK维持为高电平。由于时钟信号CK的前一时钟周期的第二电平阶段的电平状态为低电平，时钟信号CK提供边沿触发器110的触发边沿，即，上升沿。边沿触发器110的输出数据Do的信号电平与时钟信号CK的当前时钟周期的触发边沿的输入数据Di的信号电平一致，例如图10所示的高电平。
在时刻t2，时钟信号CLK到达第三个上升沿，时钟信号CK维持前一时钟周期的高电平。
时钟控制信号EN_a是边沿触发器110的输入数据Di和输出数据 Do的逻辑异或运算结果。在时刻t2开始的整个时钟周期中，边沿触发器110的输入数据Di的信号电平经由信号延迟Td后从高电平翻转为低电平，输出数据Do的信号电平在整个时钟周期中始终为高电平。作为逻辑异或运算的结果，时钟控制信号EN_a经由信号延迟Td从低电平翻转为高电平，时钟控制信号EN_a的反相信号EN_b经由信号延迟Td从高电平翻转为低电平。
时钟信号CK是时钟控制信号EN_a的反相信号EN_b和时钟信号CLK的逻辑或运算结果。因此，在时刻t2开始的一个时钟周期中，时钟信号CK是时钟信号CLK的复制版本。尽管时钟控制信号EN_a的反相信号EN_b存在着信号延迟Td，然而，该信号延迟Td位于时钟信号CLK的第一电平阶段T1中，利用组合逻辑运算可以消除时钟信号CK由于信号延迟Td可能产生的毛刺。
因此，在时刻t2开始的一个时钟周期中，时钟门控电路330将时钟信号CLK复制为时钟信号CK。由于时钟信号CK的前一时钟周期的电平状态为高电平，时钟信号CK未能提供边沿触发器110的触发边沿，即，上升沿。边沿触发器110的输出数据Do的信号电平与时钟信号CK的前一个触发边沿的输入数据Di的信号电平一致，例如图10所示的高电平。
在时刻t3，时钟信号CLK到达第四个上升沿，时钟信号CK从前一时钟周期的第二电平阶段的低电平翻转为高电平。
时钟控制信号EN_a是边沿触发器110的输入数据Di和输出数据Do的逻辑异或运算结果。在时刻t3开始的一个时钟周期中，输入数据Di的信号电平维持为低电平，输出数据Do的信号电平则始终为低电平。作为逻辑异或运算的结果，时钟控制信号EN_a在时刻t3从高电平翻转为低电平且在时刻t3开始的时钟周期中始终为低电平，时钟控制信号EN_a的反相信号EN_b在时刻t3开始的时钟周期中始终为高电平。
时钟信号CK是时钟控制信号EN_a的反相信号EN_b和时钟信号CLK的逻辑或运算结果。因此，在时刻t3，时钟信号CK从低电平翻转为高电平且在时刻t3开始的时钟周期中维持为高电平。
因此，在时刻t3开始的一个时钟周期中，时钟门控电路330将时钟 信号CK维持为高电平。由于时钟信号CK的前一时钟周期的第二电平阶段的电平状态为低电平，时钟信号CK提供边沿触发器110的触发边沿，即，上升沿。边沿触发器110的输出数据Do的信号电平与时钟信号CK的当前时钟周期的触发边沿的输入数据Di的信号电平一致，例如图10所示的低电平。
上述的时钟门控电路330基于边沿触发器110的输入数据Di和输出数据Do的数据比较产生时钟控制信号EN_a，以及根据时钟控制信号EN_a的状态控制时钟信号的传输。
在连续的时钟周期中，如果边沿触发器110的输入数据Di维持不变，则边沿触发器110的输出数据Do将维持不变。边沿触发器110的输入数据Di和输出数据Do彼此相同。时钟门控电路330屏蔽时钟信号CLK，将时钟信号CK维持为高电平状态。因此，时钟门控电路330可以禁用边沿触发器110的时钟翻转和数据传输，因而可以降低边沿触发器110因时钟翻转和数据传输产生的动态功耗。
在连续的时钟周期中，如果边沿触发器110的输入数据Di翻转，则在输入数据Di翻转的时钟周期中，边沿触发器110的输入数据Di经过信号延迟后翻转，输入数据Di和Do从彼此相同变成彼此不同。时钟门控电路330将时钟信号CLK复制为时钟信号CK，以及在下一时钟周期提供边沿触发器的触发边沿，因此，时钟门控电路330可以在单个时钟周期启用边沿触发器110的时钟翻转，以及在单个时钟周期启用边沿触发器110的数据传输，因而可以降低边沿触发器110因时钟翻转和数据传输产生的动态功耗。
根据本实施例的时钟门控电路330，与图5所示的时钟门控电路130相比省去了锁存器。即使边沿触发器110的输入数据Di存在着信号延迟Td，只要将边沿触发器110的输入数据Di的信号延迟Td的最小延迟Tdmin和最大延迟Tdmax设置在时钟信号CLK的第一电平阶段中，就可以消除边沿触发器110的时钟信号CK的毛刺。
在触发单元的电路设计中，时钟门控电路330仅仅需要设置边沿触发器110的输入数据Di的信号延迟，因而，可以简化触发单元的电路结构和电路设计。时钟门控电路330使用的硬件逻辑较少，并且自身的工 作功耗较低。
在触发单元中，任意数量的边沿触发器110可以共用时钟门控电路330从而组成触发器组。对于触发器组包含任意数量的边沿触发器110的情形，因时钟门控电路330本身的功耗而增加的功耗远小于边沿触发器110因时钟门控而减少的功耗，因此，触发单元始终可以实现功耗降低。
图9示出图7所示触发单元中的另一种时钟门控电路的示意性电路图。参见图7，时钟门控电路430和边沿触发器110共同组成触发单元，时钟门控电路430向边沿触发器110提供时钟信号CK。
时钟门控电路430包括异或门431及与门433。在时钟门控电路430中，基于边沿触发器110的输入数据Di和输出数据Do的比较产生时钟控制信号EN_a，时钟信号CK是时钟信号CLK和时钟控制信号EN_a的逻辑与运算结果。
异或门431包括第一输入端、第二输入端和输出端。与门433包括第一输入端、第二输入端和输出端。异或门431的第一数据输入端接收边沿触发器110的输入数据Di，第二数据输入端接收边沿触发器110的输出数据Do，输出端提供时钟控制信号EN_a。与门433的第一输入端接收时钟信号CLK。与门433的第二输入端连接至异或门431的输出端以接收时钟控制信号EN_a。与门433的输出端提供时钟信号CK。
在本实施例中，以下降沿触发的边沿触发器为例，时钟控制信号EN以高电平表示有效状态、低电平表示无效状态为例进行说明。时钟信号CLK的每个时钟周期包括相邻下降沿之间的连续的第一电平阶段T1和第二电平阶段T2，第一电平阶段T1和第二电平阶段T2分别具有低电平和高电平。时钟信号CK提供下降沿作为边沿触发器110的触发边沿，边沿触发器110在触发边沿将输入数据从输入端传送至输出端。
参见图11，边沿触发器110的输入数据Di存在着相对于时钟信号边沿的信号延迟Td。信号延迟Td的最小延迟Tdmin和最大延迟Tdmax之间的区域分别采用阴影部分表示。边沿触发器110的输入数据Di的信号延迟Td在最小延迟Tdmin和最大延迟Tdmax之间变化。
在本实施例中，基于边沿触发器110的输入数据Di和输出数据Do 的数据比较获得时钟门控电路的时钟控制信号EN_a，时钟控制信号EN_a的信号延迟Td与输入数据Di的信号延迟Td大致相同。
采用优化的电路设计和电路仿真，可以计算并设置边沿触发器110的输入数据Di的信号延迟Td，使得信号延迟Td的最小延迟Tdmin和最大延迟Tdmax的范围内位于时钟信号CLK的选定的第一电平阶段T1中。
相应地，时钟控制信号EN_a的信号延迟Td的最小延迟Tdmin和最大延迟Tdmax的范围内位于时钟信号CLK的第一电平阶段T1中。时钟控制信号EN_a的翻转动作仅可能发生在时钟信号CLK的第一电平阶段T1。第一电平阶段T1的开始边沿为下降沿。
在时刻t0，时钟信号CLK到达第一个下降沿，时钟信号CK维持为前一时钟周期的低电平。
时钟控制信号EN_a是边沿触发器110的输入数据Di和输出数据Do的逻辑异或运算结果。在时刻t0开始的时钟周期中，边沿触发器110的输入数据Di的信号电平经由信号延迟Td后从低电平翻转为高电平，输出数据Do的信号电平在整个时钟周期中始终为低电平。作为逻辑异或运算的结果，时钟控制信号EN_a经由信号延迟Td从低电平翻转为高电平，时钟控制信号EN_a经由信号延迟Td从低电平翻转为高电平。
时钟信号CK是时钟控制信号EN_a和时钟信号CLK的逻辑与运算结果。在时刻t0开始的一个时钟周期中，时钟信号CK是时钟信号CLK的复制版本。尽管时钟控制信号EN_a存在着信号延迟Td，然而，该信号延迟Td位于时钟信号CLK的第一电平阶段T1中，利用组合逻辑运算可以消除时钟信号CK由于信号延迟Td可能产生的毛刺。
因此，在时刻t0开始的一个时钟周期中，时钟门控电路430将时钟信号CLK复制为时钟信号CK。由于时钟信号CK的前一时钟周期的电平状态为低电平，时钟信号CK未能提供边沿触发器110的触发边沿，即，下降沿。边沿触发器110的输出数据Do的信号电平与时钟信号CK的前一个触发边沿的输入数据Di的信号电平一致，例如图11所示的低电平。
在时刻t1，时钟信号CLK到达第二个下降沿，时钟信号CK从前一 时钟周期的第二电平阶段的高电平翻转为低电平。
时钟控制信号EN_a是边沿触发器110的输入数据Di和输出数据Do的逻辑异或运算结果。在时刻t1开始的一个时钟周期中，输入数据Di的信号电平维持为高电平，输出数据Do的信号电平则始终为高电平。作为逻辑异或运算的结果，时钟控制信号EN_a在时刻t1从高电平翻转为低电平且在时刻t1开始的时钟周期中始终为低电平。
时钟信号CK是时钟控制信号EN_a和时钟信号CLK的逻辑与运算结果。因此，在时刻t1，时钟信号CK从高电平翻转为低电平且在时刻t1开始的时钟周期中维持为低电平。
因此，在时刻t1开始的一个时钟周期中，时钟门控电路430将时钟信号CK维持为低电平。由于时钟信号CK的前一时钟周期的第二电平阶段的电平状态为高电平，时钟信号CK提供边沿触发器110的触发边沿，即，下降沿。边沿触发器110的输出数据Do的信号电平与时钟信号CK的当前时钟周期的触发边沿的输入数据Di的信号电平一致，例如图11所示的高电平。
在时刻t2，时钟信号CLK到达第三个下降沿，时钟信号CK维持前一时钟周期的低电平。
时钟控制信号EN_a是边沿触发器110的输入数据Di和输出数据Do的逻辑异或运算结果。在时刻t2开始的整个时钟周期中，边沿触发器110的输入数据Di的信号电平经由信号延迟Td后从高电平翻转为低电平，输出数据Do的信号电平在整个时钟周期中始终为高电平。作为逻辑异或运算的结果，时钟控制信号EN_a经由信号延迟Td从低电平翻转为高电平。
时钟信号CK是时钟控制信号EN_a和时钟信号CLK的逻辑与运算结果。因此，在时刻t2开始的一个时钟周期中，时钟信号CK是时钟信号CLK的复制版本。尽管时钟控制信号EN_a存在着信号延迟Td，然而，该信号延迟Td位于时钟信号CLK的第一电平阶段T1中，利用组合逻辑运算可以消除时钟信号CK由于信号延迟Td可能产生的毛刺。
因此，在时刻t2开始的一个时钟周期中，时钟门控电路430将时钟信号CLK复制为时钟信号CK。由于时钟信号CK的前一时钟周期的电 平状态为低电平，时钟信号CK未能提供边沿触发器110的触发边沿，即，下降沿。边沿触发器110的输出数据Do的信号电平与时钟信号CK的前一个触发边沿的输入数据Di的信号电平一致，例如图11所示的高电平。
在时刻t3，时钟信号CLK到达第四个下降沿，时钟信号CK从前一时钟周期的第二电平阶段的高电平翻转为低电平。
时钟控制信号EN_a是边沿触发器110的输入数据Di和输出数据Do的逻辑异或运算结果。在时刻t3开始的一个时钟周期中，输入数据Di的信号电平维持为低电平，输出数据Do的信号电平则始终为低电平。作为逻辑异或运算的结果，时钟控制信号EN_a在时刻t3从高电平翻转为低电平且在时刻t3开始的时钟周期中始终为低电平。
时钟信号CK是时钟控制信号EN_a和时钟信号CLK的逻辑与运算结果。因此，在时刻t3，时钟信号CK从高电平翻转为低电平且在时刻t3开始的时钟周期中维持为低电平。
因此，在时刻t3开始的一个时钟周期中，时钟门控电路430将时钟信号CK维持为低电平。由于时钟信号CK的前一时钟周期的第二电平阶段的电平状态为高电平，时钟信号CK提供边沿触发器110的触发边沿，即，下降沿。边沿触发器110的输出数据Do的信号电平与时钟信号CK的当前时钟周期的触发边沿的输入数据Di的信号电平一致，例如图11所示的低电平。
上述的时钟门控电路430基于边沿触发器110的输入数据Di和输出数据Do的数据比较产生时钟控制信号EN_a，以及根据时钟控制信号EN_a的状态控制时钟信号的传输。
在连续的时钟周期中，如果边沿触发器110的输入数据Di维持不变，则边沿触发器110的输出数据Do将维持不变。边沿触发器110的输入数据Di和输出数据Do彼此相同。时钟门控电路430屏蔽时钟信号CLK，将时钟信号CK维持为低电平状态。因此，时钟门控电路430可以禁用边沿触发器110的时钟翻转和数据传输，因而可以降低边沿触发器110因时钟翻转和数据传输产生的动态功耗。
在连续的时钟周期中，如果边沿触发器110的输入数据Di翻转，则 在输入数据Di翻转的时钟周期中，边沿触发器110的输入数据Di经过信号延迟后翻转，输入数据Di和Do从彼此相同变成彼此不同。时钟门控电路430将时钟信号CLK复制为时钟信号CK，以及在下一时钟周期提供边沿触发器的触发边沿，因此，时钟门控电路430可以在单个时钟周期启用边沿触发器110的时钟翻转，以及在单个时钟周期启用边沿触发器110的数据传输，因而可以降低边沿触发器110因时钟翻转和数据传输产生的动态功耗。
根据本实施例的时钟门控电路430，与图5所示的时钟门控电路130相比省去了锁存器。即使边沿触发器110的输入数据Di存在着信号延迟Td，只要将边沿触发器110的输入数据Di的信号延迟Td的最小延迟Tdmin和最大延迟Tdmax设置在时钟信号CLK的第一电平阶段中，就可以消除边沿触发器110的时钟信号CK的毛刺。
在触发单元的电路设计中，时钟门控电路430仅仅需要设置边沿触发器110的输入数据Di的信号延迟，因而，可以简化触发单元的电路结构和电路设计。时钟门控电路430使用的硬件逻辑较少，并且自身的工作功耗较低。
在触发单元中，任意数量的边沿触发器110可以共用时钟门控电路430从而组成触发器组。对于触发器组包含任意数量的边沿触发器110的情形，因时钟门控电路430本身的功耗而增加的功耗远小于边沿触发器110因时钟门控而减少的功耗，因此，触发单元始终可以实现功耗降低。
图12示出根据本发明第二实施例的触发单元的示意性电路图。触发单元500包括边沿触发器110和时钟门控电路530。时钟门控电路530用于边沿触发器110时钟信号CK的门控。在本实施例中，边沿触发器110例如为D型触发器。
边沿触发器110包括数据输入端、数据输出端和时钟输入端。时钟门控电路530包括第一输入端、第二输入端、时钟输入端、时钟输出端、以及控制端。时钟门控电路530的第一输入端接收输入数据Di，第二输入端接收输出数据Do，控制端接收第二时钟控制信号EN，时钟输入端接收时钟信号CLK，时钟输出端提供时钟信号CK。边沿触发器110的 数据输入端接收输入数据Di，时钟输入端接收时钟信号CK，数据输出端提供输出数据Do。
在时钟信号CK的触发边沿，例如上升沿，边沿触发器110将输入数据从数据输入端传送至数据输出端。因而，边沿触发器110的数据输出端的输出数据相对应的信号电平取决于时钟信号CK的触发边沿到来之前数据输入端的输入数据的信号电平，并且在时钟信号CK的触发边沿之后的一个时钟周期中维持不变。边沿触发器110的数据输出端可以包括两个互补输出端。
时钟门控电路530对输入数据Di、输出数据Do、第二时钟控制信号EN和时钟信号CLK进行组合逻辑运算以产生边沿触发器110的时钟信号CK。
上述的时钟门控电路530基于边沿触发器110的输入数据Di和输出数据Do的数据比较产生第一时钟控制信号EN_a，以及根据第一时钟控制信号EN_a和接收的第二时钟控制信号EN的状态控制时钟信号的传输。
第二时钟控制信号EN例如包括多个时钟周期的有效阶段和多个时钟周期的无效阶段。在第二时钟控制信号EN有效时，时钟门控电路530禁用数据比较，时钟门控电路530将时钟信号CLK复制为时钟信号CK。在第二时钟控制信号EN无效时，时钟门控电路530启用数据比较，根据比较控制时钟信号的传输。
在时钟门控电路530启用数据比较的情形下，在输入数据Di维持不变的时钟周期中，时钟门控电路530将时钟信号CK维持为预定电平。在输入数据Di翻转的时钟周期中，时钟门控电路530将时钟信号CLK复制为时钟信号CK。因此，时钟门控电路530仅在边沿触发器110的输入数据Di翻转的一个时钟周期中启用时钟信号CLK的传输，因而可以最小化边沿触发器110因时钟信号CK翻转产生的动态功耗。进一步地，时钟门控电路530仅在边沿触发器110的输入数据Di翻转的下一个时钟周期提供一个触发边沿，因而可以最小化边沿触发器110因数据传输产生的动态功耗。
进一步地，边沿触发器110在输入数据Di维持不变的大多数时钟周 期阻止数据进入后级数字电路中，因而可以避免后级组合逻辑的数据信号翻转产生附加的数据功耗。
图13示出图12所示触发单元中的时钟门控电路的示意性电路图。参见图12，时钟门控电路530和边沿触发器110共同组成触发单元，时钟门控电路530向边沿触发器110提供时钟信号CK。
时钟门控电路530包括异或门331、非门332、或门533、及非门534。在时钟门控电路530中，基于边沿触发器110的输入数据Di和输出数据Do的比较产生时时钟控制信号EN_a，时钟信号CK是时钟信号CLK、第一时钟控制信号EN_a的反相信号EN_b、以及接收的第二时钟控制信号EN逻辑或运算结果。
异或门331包括第一输入端、第二输入端和输出端。非门332和534分别包括输入端和输出端。与门533包括第一输入端、第二输入端、第三输入端和输出端。异或门331的第一数据输入端接收边沿触发器110的输入数据Di，第二数据输入端接收边沿触发器110的输出数据Do，输出端提供第一时钟控制信号EN_a。非门332连接在异或门331的输出端和或门331的第二输入端之间，用于产生第一时钟控制信号EN_a的反相信号EN_b。或门533的第一输入端接收时钟信号CLK。或门533的第二输入端经由非门332接收第一时钟控制信号EN_a的反相信号EN_b。或门533的第三输入端经由非门534接收第二时钟控制信号EN的反相信号EN_c。或门533的输出端提供时钟信号CK。
根据第二实施例的触发单元中使用的时钟门控电路530的工作原理与根据第一实施例的触发单元中使用的时钟门控电路330的工作原理基本相同，在此不再详述。
根据本实施例的时钟门控电路530，与图5所示的时钟门控电路130相比省去了锁存器。时钟门控电路530根据接收的第二时钟控制信号EN启用或禁用数据比较功能。在第二时钟控制信号EN有效时，时钟门控电路530启用数据比较功能，在第二时钟控制信号EN元效时，时钟门控电路530禁用数据比较功能。在启用数据比较功能的情形下，即使边沿触发器110的输入数据Di存在着信号延迟Td，只要将边沿触发器110的输入数据Di的信号延迟Td的最小延迟Tdmin和最大延迟Tdmax设 置在时钟信号CLK的第一电平阶段中，就可以消除边沿触发器110的时钟信号CK的毛刺。
在触发单元的电路设计中，时钟门控电路530仅仅需要设置边沿触发器110的输入数据Di的信号延迟，因而，可以简化触发单元的电路结构和电路设计。时钟门控电路530使用的硬件逻辑较少，并且自身的工作功耗较低。
在触发单元中，任意数量的边沿触发器110可以共用时钟门控电路530从而组成触发器组。对于触发器组包含任意数量的边沿触发器110的情形，因时钟门控电路530本身的功耗而增加的功耗远小于边沿触发器110因时钟门控而减少的功耗，因此，触发单元始终可以实现功耗降低。
图14示出根据本发明第三实施例的触发单元的示意性电路图。触发单元600包括边沿触发器210和时钟门控电路630。时钟门控电路630用于边沿触发器210时钟信号CK的门控。在本实施例中，边沿触发器210例如为D型触发器。
边沿触发器210包括数据输入端、第一数据输出端、第二数据输出端和时钟输入端。时钟门控电路630包括第一输入端、第二输入端、时钟输入端、时钟输出端。时钟门控电路630的第一输入端接收输入数据Di，第二输入端接收输出数据Do，时钟输入端接收时钟信号CLK，时钟输出端提供时钟信号CK。边沿触发器210的数据输入端接收输入数据Di，时钟输入端接收时钟信号CK，第一数据输出端提供输出数据Do、第二数据输出端提供输出数据Do的反相信号Dn。
在本实施例中，边沿触发器210的第一数据输出端和第二数据输出端是两个互补输出端。边沿触发器210的数据输入端与第二数据输出端连接，因此，边沿触发器210始终将自身的输出数据Do的反相信号Dn作为输入数据。
在时钟信号CK的触发边沿，例如上升沿，边沿触发器210将输入数据从数据输入端传送至数据输出端。因而，边沿触发器210的数据输出端的输出数据相对应的信号电平取决于时钟信号CK的触发边沿到来之前数据输入端的输入数据的信号电平，并且在时钟信号CK的触发边 沿之后的一个时钟周期中维持不变。
时钟门控电路630对输入数据Di、输出数据Do和时钟信号CLK进行组合逻辑运算以产生边沿触发器210的时钟信号CK。
上述的时钟门控电路630基于边沿触发器210的输入数据Di和输出数据Do的数据比较产生时钟控制信号EN_a，以及根据时钟控制信号EN_a的状态控制时钟信号的传输。
在输入数据Di维持不变的时钟周期中，时钟门控电路630将时钟信号CK维持为预定电平。在输入数据Di翻转的时钟周期中，时钟门控电路630将时钟信号CLK复制为时钟信号CK。因此，时钟门控电路630仅在边沿触发器210的输入数据Di翻转的一个时钟周期中启用时钟信号CLK的传输，因而可以最小化边沿触发器210因时钟信号CK翻转产生的动态功耗。进一步地，时钟门控电路630仅在边沿触发器210的输入数据Di翻转的下一个时钟周期提供一个触发边沿，因而可以最小化边沿触发器210因数据传输产生的动态功耗。在时钟信号CK的触发边沿，边沿触发器210将输出数据Do的反相信号作为输入数据从输入端提供至输出端。进一步地，边沿触发器210在其他时间阻止数据进入后级数字电路中，因而可以避免后级组合逻辑的数据信号翻转产生附加的数据功耗。
图15示出图14所示触发单元中的时钟门控电路的示意性电路图。参见图14，时钟门控电路630和边沿触发器210共同组成触发单元，时钟门控电路630向边沿触发器210提供时钟信号CK。
时钟门控电路630包括异或门331、非门332及或门533。在时钟门控电路630中，基于边沿触发器210的输入数据Di和输出数据Do的比较产生时钟控制信号EN_a，时钟信号CK是时钟信号CLK、以及时钟控制信号EN_a的反相信号EN_b逻辑或运算结果。
根据第三实施例的触发单元中使用的时钟门控电路630的工作原理与根据第一实施例的触发单元中使用的时钟门控电路330的工作原理基本相同，在此不再详述。
进一步地，根据第三实施例的触发单元中的边沿触发器210的工作原理与根据第一实施例的触发器中使用的边沿触发器110的工作原理基 本相同，在此仅描述二者的主要区别。
根据第三实施例的触发单元600接收的输入数据Di仅仅用于时钟门控，边沿触发器210基于自身的输出数据Dn产生输入数据，因此边沿触发器210无需从外部接收任何输入数据。例如，所述边沿触发器的数据输入端耦接至第二数据输出端以接收所述输出数据的反相信号Dn作为输入数据。
根据本实施例的时钟门控电路630，与图5所示的时钟门控电路130相比省去了锁存器。即使边沿触发器210的输入数据Di存在着信号延迟Td，只要将边沿触发器210的输入数据Di的信号延迟Td的最小延迟Tdmin和最大延迟Tdmax设置在时钟信号CLK的第一电平阶段中，就可以消除边沿触发器210的时钟信号CK的毛刺。
边沿触发器210基于自身的输出数据Dn产生输入数据，因此边沿触发器210无需从外部接收任何输入数据，因而可以减少外部的输入数据的信号延迟波动对边沿触发器210的工作稳定性的不利影响。
时钟门控电路630仅仅需要设置边沿触发器210的输入数据Di的信号延迟，因而，可以简化触发单元的电路结构和电路设计。时钟门控电路630使用的硬件逻辑较少，并且自身的工作功耗较低。
在触发单元中，任意数量的边沿触发器210可以共用时钟门控电路630从而组成触发器组。对于触发器组包含任意数量的边沿触发器210的情形，因时钟门控电路630本身的功耗而增加的功耗远小于边沿触发器210因时钟门控而减少的功耗，因此，触发单元始终可以实现功耗降低。
在上述的触发单元中，以在时钟信号的上升沿触发和下降沿触发的触发器为例进行说明，触发单元内的边沿触发器仅示例了一种结构。然而，本发明不限于此。可以理解，其他的边沿触发器，例如带复位功能的边沿触发器，也可应用本实用新型进行技术改善。
应当说明的是，在本文中，诸如第一和第二等之类的关系术语仅仅用来将一个实体或者操作与另一个实体或操作区分开来，而不一定要求或者暗示这些实体或操作之间存在任何这种实际的关系或者顺序。而且，术语“包括”、“包含”或者其任何其他变体意在涵盖非排他性的包含，从 而使得包括一系列要素的过程、方法、物品或者设备不仅包括那些要素，而且还包括没有明确列出的其他要素，或者是还包括为这种过程、方法、物品或者设备所固有的要素。在没有更多限制的情况下，由语句“包括一个……”限定的要素，并不排除在包括所述要素的过程、方法、物品或者设备中还存在另外的相同要素。
依照本发明的实施例如上文所述，这些实施例并没有详尽叙述所有的细节，也不限制该发明仅为所述的具体实施例。显然，根据以上描述，可作很多的修改和变化。本说明书选取并具体描述这些实施例，是为了更好地解释本发明的原理和实际应用，从而使所属技术领域技术人员能很好地利用本发明以及在本发明基础上的修改使用。本发明仅受权利要求书及其全部范围和等效物的限制。

Claims (16)

  1. 一种触发单元，包括：
    边沿触发器，包括数据输入端、时钟输入端和第一数据输出端；以及
    时钟门控电路，包括第一输入端、第二输入端、时钟输入端和输出端，
    其中，所述时钟门控电路的第一输入端接收所述边沿触发器的输入数据，第二输入端接收所述边沿触发器的输出数据，时钟输入端接收第一时钟信号，输出端与所述边沿触发器的时钟输入端耦接以提供第二时钟信号，
    所述时钟门控电路根据所述输入数据和所述输出数据的数据比较结果启用或屏蔽所述第一时钟信号以产生所述第二时钟信号，所述第二时钟信号提供所述边沿触发器的触发边沿，
    所述时钟门控电路在所述输入数据翻转的时钟周期中，将所述第一时钟信号复制为所述第二时钟信号，在所述输入数据维持不变的时钟周期中，将所述第二时钟信号维持为预定电平。
  2. 根据权利要求1所述的触发单元，其中，所述第一时钟信号的时钟周期包括连续的第一电平阶段和第二电平阶段，所述输入数据在所述第一时钟信号的第一电平阶段翻转。
  3. 根据权利要求2所述的触发单元，其中，所述预定电平为所述第一电平阶段的电平，所述第二时钟信号在输入数据翻转的时钟周期的下一个时钟周期提供触发边沿。
  4. 根据权利要求2所述的触发单元，其中，所述第一电平阶段的开始边沿为上升沿。
  5. 根据权利要求4所述的触发单元，其中，所述时钟门控电路包括：
    异或门，包括第一输入端、第二输入端和输出端，所述第一输入端和所述第二输入端分别接收所述边沿触发器的输入数据和输出数据，所述输出端提供第一时钟控制信号；
    或门，包括第一输入端、第二输入端和输出端，所述第一输入端接 收所述第一时钟信号；以及
    非门，包括输入端和输出端，所述非门连接在所述异或门的输出端和所述或门的第二输入端之间，
    其中，所述非门将所述第一时钟控制信号反相后提供至所述或门的第二输入端，所述或门的输出端提供所述第二时钟信号。
  6. 根据权利要求5所述的触发单元，其中，所述或门还包括第三输入端，所述第三输入端接收第二时钟控制信号的反相信号。
  7. 根据权利要求6所述的触发单元，其中，在所述第二时钟控制信号有效时，所述时钟门控电路启用数据比较功能，在所述第二时钟控制信号无效时，所述时钟门控电路禁用数据比较功能。
  8. 根据权利要求2所述的触发单元，其中，所述第一电平阶段的开始边沿为下降沿。
  9. 根据权利要求8所述的触发单元，其中，所述时钟门控电路包括：
    异或门，包括第一输入端、第二输入端和输出端，所述第一输入端和所述第二输入端分别接收所述边沿触发器的输入数据和输出数据，所述输出端提供第一时钟控制信号；以及
    与门，包括第一输入端、第二输入端和输出端，所述第一输入端接收所述第一时钟信号，所述第二输入端接收所述第一时钟控制信号，所述输出端提供所述第二时钟信号。
  10. 根据权利要求9所述的触发单元，其中，所述与门还包括第三输入端，所述第三输入端接收第二时钟控制信号。
  11. 根据权利要求10所述的触发单元，其中，在所述第二时钟控制信号有效时，所述时钟门控电路启用数据比较功能，在所述第二时钟控制信号无效时，所述时钟门控电路禁用数据比较功能。
  12. 根据权利要求5或9所述的触发单元，其中，所述边沿触发器的数据输入端接收自身的输出数据的反相信号作为输入数据。
  13. 根据权利要求12所述的触发单元，其中，所述边沿触发器还包括第二数据输出端，所述边沿触发器的第一数据输出端和第二数据输出端分别提供所述边沿触发器的输出数据和所述输出数据的反相信号，
    其中，所述边沿触发器的数据输入端与所述第二数据输出端彼此耦 接以接收自身的输出数据的反相信号。
  14. 根据权利要求6或10所述的触发单元，其中，所述第一时钟控制信号和所述第二时钟控制信号各自的高电平表示有效状态，低电平表示无效状态。
  15. 根据权利要求1所述的触发单元，其中，所述边沿触发器在所述触发边沿接收所述数据输入端的输入数据并传送至所述第一数据输出端。
  16. 根据权利要求1所述的触发单元，其中，所述触发单元作为数字电路EDA的标准单元库中的库单元。
PCT/CN2023/080589 2022-01-28 2023-03-09 基于数据比较进行时钟门控的触发单元 WO2023143632A1 (zh)

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