WO2023143214A1 - Procédé de traitement de signal et circuit de traitement de signal - Google Patents

Procédé de traitement de signal et circuit de traitement de signal Download PDF

Info

Publication number
WO2023143214A1
WO2023143214A1 PCT/CN2023/072480 CN2023072480W WO2023143214A1 WO 2023143214 A1 WO2023143214 A1 WO 2023143214A1 CN 2023072480 W CN2023072480 W CN 2023072480W WO 2023143214 A1 WO2023143214 A1 WO 2023143214A1
Authority
WO
WIPO (PCT)
Prior art keywords
signal
pulse
ramp
analog
signal processing
Prior art date
Application number
PCT/CN2023/072480
Other languages
English (en)
Chinese (zh)
Inventor
杨晓风
Original Assignee
深圳市九天睿芯科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 深圳市九天睿芯科技有限公司 filed Critical 深圳市九天睿芯科技有限公司
Publication of WO2023143214A1 publication Critical patent/WO2023143214A1/fr

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/124—Sampling or signal conditioning arrangements specially adapted for A/D converters
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/06—Continuously compensating for, or preventing, undesired influence of physical parameters
    • H03M1/0617—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence

Definitions

  • the present application relates to the technical field of Internet of Things equipment and analog-to-digital converters, and in particular, to a signal processing method and a signal processing circuit.
  • the features of the analog signal are first extracted through the analog signal processing module, and the features of the extracted analog signal are transmitted to an analog-to-digital converter (analog to digital converter, ADC) for analog-to-digital conversion , and then, the analog-to-digital converter inputs the digitized features obtained after the analog-to-digital conversion to the neural network accelerator for processing, and finally obtains the recognition result.
  • ADC analog to digital converter
  • the energy intensity of analog signals in different frequency bands is a key signal characteristic of speech recognition systems or other recognition systems.
  • the method of rectifying the analog signal in the existing technical solution is to rectify the current or voltage, and output all positive-phase signals.
  • the existing rectification scheme will change the waveform of the analog signal when performing feature extraction on the analog signal, which will easily lead to signal distortion.
  • the present application provides a signal processing method and a signal processing circuit, which can ensure that the signal is not distorted when performing feature extraction on an analog signal.
  • the embodiment of the present application provides a signal processing method, including the following steps:
  • a pulse signal is output according to the comparison result.
  • the reference signal is input every first time interval, and the first time interval is A preset multiple of the duration of a single input of the reference signal, and the preset multiple is an integer greater than or equal to 1.
  • the reference signal is a ladder-shaped ramp signal, and the duration of a single input of the ramp signal is calculated as follows:
  • the number of steps of the ramp signal and the second time interval between each step are determined, and the second time interval is multiplied by the number of steps to obtain a single input duration of the ramp signal.
  • the comparing the analog signal with the reference signal includes:
  • the common-mode voltage value of the analog signal is calculated, and the voltage value of the ramp signal increases positively with the lowest value of the common-mode voltage value.
  • An embodiment of the present application provides a signal processing method, including the above-mentioned signal processing method, and further includes the following steps:
  • the pulse signal is integrated.
  • said integrating said pulse signal includes:
  • each quantized pulse width of the pulse signal is superimposed to obtain a total quantized pulse width.
  • the frequency of the clock signal is set to be at least twice the frequency of the pulse signal.
  • an embodiment of the present application provides a signal processing circuit, including a signal generator and a comparator, wherein,
  • the signal generator is used to generate a reference signal and send the reference signal to the comparator;
  • the comparator is used to receive an analog signal and a reference signal; compare the analog signal with the The reference signal is compared; the pulse signal is output according to the comparison result.
  • the signal generator is further configured to: generate a reference signal every first time interval, the first time interval is a preset multiple of a single input duration of the reference signal, and the preset The multiple is an integer greater than or equal to 1.
  • the reference signal is a stepped ramp signal
  • the signal generator is further configured to: determine the number of steps of the ramp signal and a second time interval between each step, and convert the second The second time interval is multiplied by the step number to obtain the duration of a single input of the ramp signal.
  • the comparator is also configured to output a low level when no ramp signal is detected; when an input ramp signal is detected, calculate the common-mode voltage value of the analog signal;
  • the signal generator is further configured to positively increase the voltage value of the ramp signal with the lowest value of the common mode voltage value.
  • the signal processing circuit further includes a digital integrator configured to: receive the pulse signal and integrate the pulse signal.
  • said digital integrator is also used for:
  • each quantized pulse width of the pulse signal is superimposed to obtain a total quantized pulse width.
  • the frequency of the clock signal is set to be at least twice the frequency of the pulse signal.
  • the signal processing method after receiving an analog signal and a reference signal, compares the analog signal with the reference signal, and outputs Pulse signal. It can be seen that this embodiment only compares the analog signal with the reference signal, and outputs the rectified pulse signal according to the comparison result.
  • signal instead of rectifying the negative signal of the analog signal into a positive signal or rectifying the positive signal of the analog signal into a negative signal through a half-bridge or full-bridge rectifier and analog signal processing methods such as amplification, filtering, modulation, and demodulation.
  • analog signal processing methods such as amplification, filtering, modulation, and demodulation.
  • the features of the analog signal are extracted, so that the process of rectification, integration and feature extraction of the analog signal can be completed without changing the waveform of the analog signal. Therefore, the embodiment of the present application can ensure that the signal is not distorted when performing feature extraction on the analog signal.
  • FIG. 1 is a schematic flowchart of a signal processing method provided in an embodiment of the present application
  • FIG. 2 is a schematic diagram of a signal waveform in an application scenario of a signal processing method provided by an embodiment of the present application
  • FIG. 3 is a schematic diagram of a signal waveform in another application scenario of the signal processing method provided by the embodiment of the present application;
  • FIG. 4 is a schematic structural diagram of a signal processing circuit provided by an embodiment of the present application.
  • FIG. 5 is a schematic diagram of a signal processing principle of a signal processing circuit provided in an embodiment of the present application.
  • FIG. 1 is a schematic flowchart of the signal processing method provided in an embodiment of the present application.
  • the signal processing methods include:
  • S101 Receive an analog signal and a reference signal.
  • the analog signal and the reference signal may be received simultaneously, or the reference signal may be received intermittently when the analog signal is received.
  • the period of the reference signal may be set, and the reference signal may be received according to the set period.
  • the existing rectification technology scheme When the existing rectification technology scheme extracts the features of the original signal, multiple channels (generally greater than 10 channels) are required for parallel processing to extract the features of multiple frequency bands. Therefore, the existing rectification technology scheme needs multiple rectifiers, and multiple rectifiers It will take up more chip area and increase the cost, which is not conducive to the application in miniaturized and miniaturized Internet of Things devices; at the same time, the existing technical solutions use rectifiers with multiple channels to extract multi-band features, but rectifiers with different channels Due to the chip manufacturing process, there will be a mismatch between them, which will reduce the recognition rate of the neural network algorithm.
  • the reference signal is input every first time interval
  • the first time interval is a preset multiple of the duration of a single input of the reference signal
  • the preset multiple is greater than or equal to 1 an integer of .
  • the first time interval (that is, the sampling interval) is T
  • the time point of the ramp signal input is T0
  • the time point of the next ramp signal input is T0+T
  • the duration of a single input of the ramp signal is set as TR.
  • the comparator used to perform the comparison between the analog signal and the ramp signal can be chained by n channel signals Therefore, the embodiment of the present application only needs one ramp generator and one comparator to realize the rectification of L channel signals.
  • the time interval of each input of the ramp signal is set as the first time interval (ie, the sampling interval), and when the first time interval is greater than the duration of a single input of the ramp signal, the Input the time between the end time point of the ramp signal and the start time point of the next input ramp signal to receive and compare the analog signal of another channel. Therefore, this embodiment samples and rectifies multi-channel input signals (i.e., analog signals) by sharing one ramp signal generator and one comparator, without requiring multiple rectifiers, reducing chip area, and avoiding Matching problems between rectifiers.
  • the received analog signals are different types of analog signals in different application scenarios, including but not limited to voice signals, photoelectric signals, and bioelectric signals.
  • the reference signal can generally use a signal generator to set a desired type of signal. It can be understood that the waveform of the reference signal can also be a triangular wave, a sawtooth wave, a trapezoidal wave, or a stepped ramp.
  • the analog signal is compared with the reference signal to obtain a comparison result.
  • the voltage value of the analog signal when the voltage value of the analog signal is greater than the voltage value of the reference signal, it corresponds to the high level of the pulse signal, and when the voltage value of the analog signal is less than or equal to the voltage value of the reference signal, it corresponds to the low level of the pulse signal. level; or, when the voltage value of the analog signal is greater than the voltage value of the reference signal, it corresponds to the low level of the pulse signal, and when the voltage value of the analog signal is less than or equal to the voltage value of the reference signal, it corresponds to the pulse signal high level.
  • the reference signal is a triangle wave
  • the signal processing method includes:
  • a pulse signal is output according to the comparison result.
  • the voltage value of the analog signal when the voltage value of the analog signal is greater than the voltage value of the triangle wave, it corresponds to the high level of the pulse signal, and when the voltage value of the analog signal is less than or equal to the voltage value of the triangle wave, it corresponds to the low level of the pulse signal ; Or, when the voltage value of the analog signal is greater than the voltage value of the triangular wave, the corresponding low level of the pulse signal, when the voltage value of the analog signal is less than or equal to the voltage value of the triangular wave, the corresponding high level of the pulse signal flat.
  • the reference signal is a sawtooth wave
  • the signal processing method includes:
  • a pulse signal is output according to the comparison result.
  • the voltage value of the analog signal when the voltage value of the analog signal is greater than the voltage value of the sawtooth wave, it corresponds to the high level of the pulse signal, and when the voltage value of the analog signal is less than or equal to the voltage value of the sawtooth wave, it corresponds to the low level of the pulse signal. level; or, when the voltage value of the analog signal is greater than the voltage value of the sawtooth wave, it corresponds to the low level of the pulse signal, and when the voltage value of the analog signal is less than or equal to the voltage value of the sawtooth wave, it corresponds to the pulse signal high level.
  • the reference signal is a stepped ramp signal
  • the signal processing method includes:
  • a pulse signal is output according to the comparison result.
  • the reference signal is a ladder-shaped ramp signal, and the duration of a single input of the ramp signal is calculated as follows:
  • the number of steps of the ramp signal and the second time interval between each step are determined, and the second time interval is multiplied by the number of steps to obtain a single input duration of the ramp signal.
  • a ramp signal generator is used to generate a stepped ramp signal.
  • the step time interval of each step of the ramp signal is set to T STEP , and the voltage difference of each step is set to V STEP , If the number of steps of the ramp signal is set to K, then the ramp generator has a total of K steps.
  • the duration of a single input of the ramp signal be TR, and the calculation formula is as follows:
  • comparing the analog signal with the reference signal includes:
  • the common mode voltage value of the analog signal is calculated, and the voltage value of the ramp signal increases positively with the lowest value of the common mode voltage value.
  • the energy intensity of the signal in different frequency bands is the key signal characteristic of the speech recognition system or other recognition systems, taking the speech recognition system as an example, when the input analog signal When it is a voice signal, in order to obtain the signal energy of different frequency bands, it is necessary to perform half-wave or full-wave rectification on the input voice signal and output a full positive-phase signal.
  • T0 is taken as the input time point of the analog signal and the ramp signal.
  • the ramp signal increases from the lowest value of the common-mode voltage value of the analog signal.
  • the analog signal and the ramp signal When the voltage value of the analog signal is greater than the voltage value of the ramp signal, a high level is output, and when the voltage value of the analog signal is less than or equal to the voltage value of the ramp signal, a low level is output. Because the ramp signal increases positively from the common mode voltage value, when the voltage value of the analog signal is less than or equal to the common mode voltage value, that is, the voltage value of the analog signal is less than or equal to the voltage value of the ramp signal, so at this time The output of the comparator is low level and there is no pulse output.
  • the Vin+ signal of the analog signal will be converted into a high-level signal corresponding to different pulse widths according to the signal amplitude. Regardless of the signal amplitude of the Vin- signal, the Vin- signal will be converted into a low-level signal, and the total output pulse width signal obtained at this time will be the amplitude integral of the full positive-phase signal.
  • FIG. 2 is a schematic diagram of a signal waveform in an application scenario of the signal processing method provided by the embodiment of the present application.
  • the specific rectification process is as follows: the rectification process starts from T0, and the ladder-shaped ramp signal increases from the common-mode voltage value of the input signal (such as an analog signal) VIN. When the voltage value of the ramp signal exceeds When the voltage value of the analog signal is changed, the voltage output by the comparator changes from high level to low level.
  • ⁇ t0 is the pulse width obtained by dividing the part where VIN is greater than the common-mode voltage value by the slope of the ramp signal during the T0 period of the input signal
  • ⁇ t2 is the pulse width obtained by dividing the part where VIN is greater than the common-mode voltage value by the ramp wave during the T2 period of the input signal. The slope of the signal gives the pulse width.
  • the input pulse signal of this program is the comparison result of the reference signal and the analog signal, which is equivalent to sampling from the analog signal, and then outputting a sampling signal, without directly changing the analog signal to output another waveform change after the analog signal.
  • this embodiment only compares the analog signal with the reference signal, and outputs the rectified pulse signal according to the comparison result, without the need for half-bridge or full-bridge rectifiers and analog signals such as amplification, filtering, modulation, and demodulation.
  • analog signals such as amplification, filtering, modulation, and demodulation.
  • the signal processing method further includes:
  • the pulse signal is integrated by a digital integration method.
  • This embodiment can complete the complete process of rectification, feature extraction and analog-to-digital conversion of the analog signal, while avoiding changing the analog signal and ensuring that the output signal is not distorted.
  • the above-mentioned integration of the pulse signal by a digital integration method includes:
  • FIG. 3 is a schematic diagram of signal waveforms in another application scenario of the signal processing method provided by the embodiment of the present application.
  • the total length of the pulse width of the pulse signal is counted as the integral working period TM.
  • the width of each pulse will be quantified by the rising edge of the clock, and the corresponding quantized pulses are respectively recorded as N1, N2, ... NH.
  • each quantized pulse width of the pulse signal is superimposed to obtain a quantized total pulse width.
  • this embodiment quantizes the pulse signal within the set integral working period TM, the longer the integral working time TM, the closer the output result is to the ideal half-wave rectifier and integrator result, and the The higher the frequency of the clock signal, the higher the quantization accuracy.
  • the present application provides various specific embodiments of setting the integral working time or setting the frequency of the clock signal on demand, and no examples are given here.
  • the frequency of the clock signal is set to be at least twice the frequency of the pulse signal.
  • the frequency of the clock signal is less than twice the frequency of the pulse signal, the digital signal obtained after integration cannot reflect the pulse signal, so the frequency of the clock signal is set to be at least twice the frequency of the pulse signal , and the frequency of the clock signal is three times, four times, or even ten times the frequency of the pulse signal, the error between the digital signal obtained after integration and the pulse signal will be multiplied, the higher the frequency of the clock signal, the quantized The higher the accuracy of the pulse signal.
  • the present application also provides a signal processing circuit, please refer to FIG. 4 , which is a schematic structural diagram of the signal processing circuit provided by the embodiment of the present application.
  • the signal processing circuit includes a signal generator 201 and a comparator 202 , wherein the signal generator 201 is used to generate a reference signal and send the reference signal to the comparator 202 .
  • the comparator 202 is used for receiving an analog signal and a reference signal; comparing the analog signal with the reference signal; and outputting a pulse signal according to the comparison result.
  • the voltage value of the analog signal when the voltage value of the analog signal is greater than the voltage value of the reference signal, it corresponds to the high level of the pulse signal, and when the voltage value of the analog signal is less than or equal to the voltage value of the reference signal, it corresponds to the low level of the pulse signal. level; or, when the voltage value of the analog signal is greater than the voltage value of the reference signal, it corresponds to the low level of the pulse signal, and when the voltage value of the analog signal is less than or equal to the voltage value of the reference signal, the The high level of the signal should be pulsed.
  • the signal generator 201 is also used for:
  • the reference signal is generated every first time interval, and the first time interval is a preset multiple of a single input duration of the reference signal, and the preset multiple is an integer greater than or equal to 1.
  • the time interval of each input of the ramp signal is set as the first time interval (ie, the sampling interval), and when the first time interval is greater than the duration of a single input of the ramp signal, the Input the time between the end time point of the ramp signal and the start time point of the next input ramp signal to receive and compare the analog signal of another channel. Therefore, this embodiment samples and rectifies multi-channel input signals (i.e., analog signals) by sharing one ramp signal generator 201 and one comparator 202, without requiring multiple rectifiers, reducing chip area, and avoiding A matching problem arises between the rectifiers of the channels.
  • the first time interval ie, the sampling interval
  • the reference signal generated by the signal generator 201 is a stepped ramp signal, and the signal generator 201 is also used for:
  • the number of steps of the ramp signal and the second time interval between each step are determined, and the second time interval is multiplied by the number of steps to obtain a single input duration of the ramp signal.
  • a ramp signal generator is used to generate a stepped ramp signal.
  • the step time interval of each step of the ramp signal is set to T STEP , and the voltage difference of each step is set to V STEP , If the number of steps of the ramp signal is set to K, then the ramp generator has a total of K steps.
  • the duration of a single input of the ramp signal be TR, and the calculation formula is as follows:
  • the comparator 202 is also used to output a low level when no ramp signal is detected; and to calculate the common-mode voltage of the analog signal when an input ramp signal is detected value;
  • the signal generator 201 is further configured to positively increase the voltage value of the ramp signal with the lowest value of the common mode voltage value.
  • the energy intensity of signals in different frequency bands is a key signal feature of a speech recognition system or other recognition systems, taking a speech recognition system as an example, when the input analog signal is a speech signal, in order to obtain signals of different frequency bands Energy, it is necessary to perform half-wave or full-wave rectification on the input voice signal and output a full positive phase signal.
  • FIG. 4 is a schematic structural diagram of a signal processing circuit provided by an embodiment of the present application.
  • the signal processing circuit includes a signal generator 201, a comparator 202 and a digital integrator 203, wherein,
  • the signal generator 201 is used to generate a reference signal and send the reference signal to the comparator 202;
  • the comparator 202 is used to receive an analog signal and a reference signal; compare the analog signal with the reference signal; output a pulse signal according to the comparison result;
  • the digital integrator 203 is used for receiving the pulse signal and integrating the pulse signal.
  • This embodiment can complete the complete process of rectification, feature extraction and analog-to-digital conversion of the analog signal, while avoiding changing the analog signal and ensuring that the output signal is not distorted.
  • FIG. 5 is a schematic diagram of a signal processing principle of a signal processing circuit provided in an embodiment of the present application.
  • the signal generator 201 generates a reference signal V RAMP , and the reference signal V RAMP and the analog signal V IN are input to the comparator 202 ; the reference signal V RAMP and the analog signal V IN are input to the comparator 202 After the comparison, a pulse signal is output according to the comparison result; the pulse signal and the clock signal are input to the digital integrator 203; the pulse signal is integrated by the digital integrator 203 to obtain a digital signal and finally output the digital signal.
  • the digital integrator 203 is also used for:
  • each quantized pulse width of the pulse signal is superimposed to obtain a quantized total pulse width.
  • this embodiment quantizes the pulse signal within the set integral working period TM, the longer the integral working time TM, the closer the output result is to the ideal half-wave rectifier and integrator result, and the The higher the frequency of the clock signal, the higher the quantization accuracy.
  • the present application provides various specific embodiments of setting the integral working time or setting the frequency of the clock signal on demand, and no examples are given here.
  • the frequency of the clock signal is set to be at least twice the frequency of the pulse signal.
  • the frequency of the clock signal is less than twice the frequency of the pulse signal, the digital signal obtained after integration cannot reflect the pulse signal, so the frequency of the clock signal is set to be at least twice the frequency of the pulse signal , and the frequency of the clock signal is three times, four times, or even ten times the frequency of the pulse signal, the error between the digital signal obtained after integration and the pulse signal will be multiplied, the higher the frequency of the clock signal, the quantized The higher the accuracy of the pulse signal.
  • each part of the present application may be realized by hardware, software, firmware or a combination thereof.
  • various steps or methods may be implemented by software or firmware stored in memory and executed by a suitable instruction execution system.
  • a suitable instruction execution system For example, if implemented in hardware, as in another embodiment, it can be implemented by any one or combination of the following techniques known in the art: Discrete logic circuits, ASICs with suitable combinational logic gates, programmable gate arrays (PGA), Field Programmable Gate Array (FPGA), etc.
  • each functional unit in each embodiment of the present application may be integrated into one processing module, each unit may exist separately physically, or two or more units may be integrated into one module.
  • the above-mentioned integrated modules can be implemented in the form of hardware or in the form of software function modules. If the integrated modules are realized in the form of software function modules and sold or used as independent products, they can also be stored in a computer-readable storage medium.
  • the storage medium may be a read-only memory, a magnetic disk or an optical disk, and the like.

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Analogue/Digital Conversion (AREA)

Abstract

La présente invention concerne un procédé de traitement de signal et un circuit de traitement de signal. Le procédé de traitement de signal comprend les étapes suivantes consistant à : recevoir un signal analogique et un signal de référence ; comparer le signal analogique au signal de référence ; et délivrer en sortie un signal d'impulsion en fonction d'un résultat de comparaison. La présente demande peut garantir qu'un signal n'est pas déformé lorsqu'un signal analogique est soumis à une extraction de caractéristiques.
PCT/CN2023/072480 2022-01-26 2023-01-17 Procédé de traitement de signal et circuit de traitement de signal WO2023143214A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202210098229.8 2022-01-26
CN202210098229.8A CN114430274A (zh) 2022-01-26 2022-01-26 一种信号处理方法及信号处理电路

Publications (1)

Publication Number Publication Date
WO2023143214A1 true WO2023143214A1 (fr) 2023-08-03

Family

ID=81313651

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2023/072480 WO2023143214A1 (fr) 2022-01-26 2023-01-17 Procédé de traitement de signal et circuit de traitement de signal

Country Status (2)

Country Link
CN (1) CN114430274A (fr)
WO (1) WO2023143214A1 (fr)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114430274A (zh) * 2022-01-26 2022-05-03 深圳市九天睿芯科技有限公司 一种信号处理方法及信号处理电路

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5574456A (en) * 1993-07-26 1996-11-12 Samsung Electronics Co., Ltd. Signal processing method and apparatus therefor
CN101888225A (zh) * 2009-05-12 2010-11-17 震一科技股份有限公司 控制输出准位的转换装置
CN104300985A (zh) * 2013-11-28 2015-01-21 中国航空工业集团公司洛阳电光设备研究所 一种基于脉冲计数的积分式ad转换电路及方法
CN107643445A (zh) * 2017-06-16 2018-01-30 华东师范大学 基于高速比较器和rc积分电路的幅度测量方法及系统
US20190363727A1 (en) * 2017-02-24 2019-11-28 Teledyne Dalsa B.V. Analog-to-digital converter and electronic device comprising the same
CN114430274A (zh) * 2022-01-26 2022-05-03 深圳市九天睿芯科技有限公司 一种信号处理方法及信号处理电路

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4094460B2 (ja) * 2003-03-18 2008-06-04 松下電器産業株式会社 アナログ信号レベル検出回路
CN103296904B (zh) * 2012-02-29 2015-05-13 上海莱狮半导体科技有限公司 功率因数校正恒流控制器及控制方法
CN104811151B (zh) * 2014-01-28 2018-04-10 意法半导体研发(深圳)有限公司 用于减少放大器中的削波的设备和方法
EP3422570B1 (fr) * 2017-06-30 2020-11-25 Nxp B.V. Circuit amplificateur
CN111756376B (zh) * 2020-06-24 2023-08-15 苏州瑞迈斯科技有限公司 信号采样装置、系统及方法

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5574456A (en) * 1993-07-26 1996-11-12 Samsung Electronics Co., Ltd. Signal processing method and apparatus therefor
CN101888225A (zh) * 2009-05-12 2010-11-17 震一科技股份有限公司 控制输出准位的转换装置
CN104300985A (zh) * 2013-11-28 2015-01-21 中国航空工业集团公司洛阳电光设备研究所 一种基于脉冲计数的积分式ad转换电路及方法
US20190363727A1 (en) * 2017-02-24 2019-11-28 Teledyne Dalsa B.V. Analog-to-digital converter and electronic device comprising the same
CN107643445A (zh) * 2017-06-16 2018-01-30 华东师范大学 基于高速比较器和rc积分电路的幅度测量方法及系统
CN114430274A (zh) * 2022-01-26 2022-05-03 深圳市九天睿芯科技有限公司 一种信号处理方法及信号处理电路

Also Published As

Publication number Publication date
CN114430274A (zh) 2022-05-03

Similar Documents

Publication Publication Date Title
US8742740B2 (en) Digital peak input voltage detector for a power converter controller
US9287889B2 (en) System and method for dynamic path-mismatch equalization in time-interleaved ADC
CN103296904B (zh) 功率因数校正恒流控制器及控制方法
CN110611431B (zh) 有源钳位反激变换器的原边调节控制系统及控制方法
US11070091B2 (en) Wireless power transfer based on transmitter coil voltage sensing
WO2023143214A1 (fr) Procédé de traitement de signal et circuit de traitement de signal
US11711015B2 (en) Switching converter with quasi-resonant control and control method thereof
US9685970B1 (en) Analog-to-digital converting system and converting method
CN106992686A (zh) 一种连续和非连续模式恒压恒流控制电路及开关电源
CN112671239B (zh) 返驰式电源供应电路及其中的二次侧控制电路及控制方法
TWI811910B (zh) 隔離式開關變換器及其控制器和控制方法
TWI614511B (zh) 測試方法及系統
CN108303579B (zh) 一种电压检测电路和方法
US10033283B2 (en) Knee point detection for power converter control
US20160226293A1 (en) Demodulation circuit and wireless charging device having the same
CN111413538B (zh) 无线充电接收侧无桥拓扑电流过零点检测电路及检测方法
CN206743109U (zh) 一种连续和非连续模式恒压恒流控制电路及开关电源
US6891407B2 (en) Analog signal level detecting apparatus
TWI786620B (zh) 升壓控制電路
CN111726179B (zh) 接收信号强度检测电路及方法
US20120013312A1 (en) Power Control Device and Method thereof
Daying et al. A Constant Current Digital Control Method for Primary-Side Regulation Half-Bridge LLC Resonant Converter
TWI450071B (zh) 功率因素校正裝置及其校正方法
CN112885339A (zh) 语音唤醒系统及语音识别系统
JPH09148851A (ja) オーディオ用スイッチング電源

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 23746096

Country of ref document: EP

Kind code of ref document: A1