WO2023143214A1

WO2023143214A1 - Signal processing method and signal processing circuit

Info

Publication number: WO2023143214A1
Application number: PCT/CN2023/072480
Authority: WO
Inventors: 杨晓风
Original assignee: 深圳市九天睿芯科技有限公司
Priority date: 2022-01-26
Filing date: 2023-01-17
Publication date: 2023-08-03
Also published as: CN114430274A

Abstract

The present invention discloses a signal processing method and a signal processing circuit. The signal processing method comprises the following steps: receiving an analog signal and a reference signal; comparing the analog signal with the reference signal; and outputting a pulse signal according to a comparison result. The present application can ensure that a signal is not distorted when an analog signal is subjected to feature extraction.

Description

A signal processing method and signal processing circuit

This application claims the priority of the Chinese patent application with the application number 202210098229.8 and the title of the invention "a signal processing method and signal processing circuit" submitted to the China Patent Office on January 26, 2022, the entire contents of which are incorporated herein by reference. Applying.

technical field

The present application relates to the technical field of Internet of Things equipment and analog-to-digital converters, and in particular, to a signal processing method and a signal processing circuit.

Background technique

In the application scenarios of the Internet of Things, whether it is wearable devices, smart home devices or sensors, there is a strong demand for low power consumption. Among them, in the speech recognition system or other recognition systems, the features of the analog signal are first extracted through the analog signal processing module, and the features of the extracted analog signal are transmitted to an analog-to-digital converter (analog to digital converter, ADC) for analog-to-digital conversion , and then, the analog-to-digital converter inputs the digitized features obtained after the analog-to-digital conversion to the neural network accelerator for processing, and finally obtains the recognition result. In particular, the energy intensity of analog signals in different frequency bands is a key signal characteristic of speech recognition systems or other recognition systems. In order to obtain the energy intensity of signals in different frequency bands, it is usually necessary to perform half-wave or full-wave rectification, integration and quantization on the analog signal. The method of rectifying the analog signal in the existing technical solution is to rectify the current or voltage, and output all positive-phase signals. The existing rectification scheme will change the waveform of the analog signal when performing feature extraction on the analog signal, which will easily lead to signal distortion.

Contents of the invention

In view of the above technical problems, the present application provides a signal processing method and a signal processing circuit, which can ensure that the signal is not distorted when performing feature extraction on an analog signal.

The embodiment of the present application provides a signal processing method, including the following steps:

Receive analog signals and reference signals;

comparing the analog signal with the reference signal;

A pulse signal is output according to the comparison result.

Optionally, the reference signal is input every first time interval, and the first time interval is A preset multiple of the duration of a single input of the reference signal, and the preset multiple is an integer greater than or equal to 1.

Optionally, the reference signal is a ladder-shaped ramp signal, and the duration of a single input of the ramp signal is calculated as follows:

The number of steps of the ramp signal and the second time interval between each step are determined, and the second time interval is multiplied by the number of steps to obtain a single input duration of the ramp signal.

Optionally, the comparing the analog signal with the reference signal includes:

When no ramp signal is detected, output low level;

When the input ramp signal is detected, the common-mode voltage value of the analog signal is calculated, and the voltage value of the ramp signal increases positively with the lowest value of the common-mode voltage value.

An embodiment of the present application provides a signal processing method, including the above-mentioned signal processing method, and further includes the following steps:

The pulse signal is integrated.

Optionally, said integrating said pulse signal includes:

Set the integral working hours;

receiving the pulse signal and clock signal;

Using the pulse rising edge of the clock signal, quantizing the pulse number of the pulse signal into a digital signal;

output the digital signal.

Optionally, within the integration working period, each quantized pulse width of the pulse signal is superimposed to obtain a total quantized pulse width.

Optionally, the frequency of the clock signal is set to be at least twice the frequency of the pulse signal.

In addition, an embodiment of the present application provides a signal processing circuit, including a signal generator and a comparator, wherein,

The signal generator is used to generate a reference signal and send the reference signal to the comparator;

The comparator is used to receive an analog signal and a reference signal; compare the analog signal with the The reference signal is compared; the pulse signal is output according to the comparison result.

Optionally, the signal generator is further configured to: generate a reference signal every first time interval, the first time interval is a preset multiple of a single input duration of the reference signal, and the preset The multiple is an integer greater than or equal to 1.

Optionally, the reference signal is a stepped ramp signal, and the signal generator is further configured to: determine the number of steps of the ramp signal and a second time interval between each step, and convert the second The second time interval is multiplied by the step number to obtain the duration of a single input of the ramp signal.

Optionally, the comparator is also configured to output a low level when no ramp signal is detected; when an input ramp signal is detected, calculate the common-mode voltage value of the analog signal;

The signal generator is further configured to positively increase the voltage value of the ramp signal with the lowest value of the common mode voltage value.

Optionally, the signal processing circuit further includes a digital integrator configured to: receive the pulse signal and integrate the pulse signal.

Optionally, for said integrating said pulse signal, said digital integrator is also used for:

Set the integral working hours;

receiving the pulse signal and clock signal;

output the digital signal.

Compared with the prior art, the embodiment of the present application has the following beneficial effects:

In the signal processing method and signal processing circuit provided in the embodiments of the present application, the signal processing method, after receiving an analog signal and a reference signal, compares the analog signal with the reference signal, and outputs Pulse signal. It can be seen that this embodiment only compares the analog signal with the reference signal, and outputs the rectified pulse signal according to the comparison result. signal, instead of rectifying the negative signal of the analog signal into a positive signal or rectifying the positive signal of the analog signal into a negative signal through a half-bridge or full-bridge rectifier and analog signal processing methods such as amplification, filtering, modulation, and demodulation. The features of the analog signal are extracted, so that the process of rectification, integration and feature extraction of the analog signal can be completed without changing the waveform of the analog signal. Therefore, the embodiment of the present application can ensure that the signal is not distorted when performing feature extraction on the analog signal.

Instructions attached

The present invention will be further described below in conjunction with accompanying drawing:

FIG. 1 is a schematic flowchart of a signal processing method provided in an embodiment of the present application;

FIG. 2 is a schematic diagram of a signal waveform in an application scenario of a signal processing method provided by an embodiment of the present application;

FIG. 3 is a schematic diagram of a signal waveform in another application scenario of the signal processing method provided by the embodiment of the present application;

FIG. 4 is a schematic structural diagram of a signal processing circuit provided by an embodiment of the present application;

FIG. 5 is a schematic diagram of a signal processing principle of a signal processing circuit provided in an embodiment of the present application.

Detailed ways

The following will clearly and completely describe the technical solutions in the embodiments of the application with reference to the drawings in the embodiments of the application. Apparently, the described embodiments are only some of the embodiments of the application, not all of them. Based on the embodiments in this application, all other embodiments obtained by persons of ordinary skill in the art without creative efforts fall within the protection scope of this application.

The present application provides a signal processing method, please refer to FIG. 1 , and FIG. 1 is a schematic flowchart of the signal processing method provided in an embodiment of the present application. The signal processing methods include:

S101. Receive an analog signal and a reference signal.

When receiving the analog signal and the reference signal, the analog signal and the reference signal may be received simultaneously, or the reference signal may be received intermittently when the analog signal is received. During specific operations, the period of the reference signal may be set, and the reference signal may be received according to the set period.

When the existing rectification technology scheme extracts the features of the original signal, multiple channels (generally greater than 10 channels) are required for parallel processing to extract the features of multiple frequency bands. Therefore, the existing rectification technology scheme needs multiple rectifiers, and multiple rectifiers It will take up more chip area and increase the cost, which is not conducive to the application in miniaturized and miniaturized Internet of Things devices; at the same time, the existing technical solutions use rectifiers with multiple channels to extract multi-band features, but rectifiers with different channels Due to the chip manufacturing process, there will be a mismatch between them, which will reduce the recognition rate of the neural network algorithm.

Optionally, in an embodiment, the reference signal is input every first time interval, the first time interval is a preset multiple of the duration of a single input of the reference signal, and the preset multiple is greater than or equal to 1 an integer of .

Specifically, taking T0 as the input time point of the analog signal and the ramp signal, the first time interval (that is, the sampling interval) is T, and the time point of the ramp signal input is T0, then the time point of the next ramp signal input is T0+T, and the duration of a single input of the ramp signal is set as TR. When the first time interval T is n times the duration TR of a single input (n is greater than or equal to 1), the comparator used to perform the comparison between the analog signal and the ramp signal can be chained by n channel signals Therefore, the embodiment of the present application only needs one ramp generator and one comparator to realize the rectification of L channel signals.

It can be understood that the time interval of each input of the ramp signal is set as the first time interval (ie, the sampling interval), and when the first time interval is greater than the duration of a single input of the ramp signal, the Input the time between the end time point of the ramp signal and the start time point of the next input ramp signal to receive and compare the analog signal of another channel. Therefore, this embodiment samples and rectifies multi-channel input signals (i.e., analog signals) by sharing one ramp signal generator and one comparator, without requiring multiple rectifiers, reducing chip area, and avoiding Matching problems between rectifiers.

In specific application scenarios, the received analog signals are different types of analog signals in different application scenarios, including but not limited to voice signals, photoelectric signals, and bioelectric signals. Signal. The reference signal can generally use a signal generator to set a desired type of signal. It can be understood that the waveform of the reference signal can also be a triangular wave, a sawtooth wave, a trapezoidal wave, or a stepped ramp.

S102. Compare the analog signal with the reference signal.

In this step, the analog signal is compared with the reference signal to obtain a comparison result. Wherein, when the voltage value of the analog signal is greater than the voltage value of the reference signal, it corresponds to the high level of the pulse signal, and when the voltage value of the analog signal is less than or equal to the voltage value of the reference signal, it corresponds to the low level of the pulse signal. level; or, when the voltage value of the analog signal is greater than the voltage value of the reference signal, it corresponds to the low level of the pulse signal, and when the voltage value of the analog signal is less than or equal to the voltage value of the reference signal, it corresponds to the pulse signal high level.

Optionally, in an embodiment, the reference signal is a triangle wave, and the signal processing method includes:

Receive the analog signal and the triangle wave;

comparing the analog signal with the triangle wave;

A pulse signal is output according to the comparison result.

Wherein, when the voltage value of the analog signal is greater than the voltage value of the triangle wave, it corresponds to the high level of the pulse signal, and when the voltage value of the analog signal is less than or equal to the voltage value of the triangle wave, it corresponds to the low level of the pulse signal ; Or, when the voltage value of the analog signal is greater than the voltage value of the triangular wave, the corresponding low level of the pulse signal, when the voltage value of the analog signal is less than or equal to the voltage value of the triangular wave, the corresponding high level of the pulse signal flat.

Optionally, in an embodiment, the reference signal is a sawtooth wave, and the signal processing method includes:

Receive the analog signal and the sawtooth wave;

comparing the analog signal to the sawtooth wave;

A pulse signal is output according to the comparison result.

Wherein, when the voltage value of the analog signal is greater than the voltage value of the sawtooth wave, it corresponds to the high level of the pulse signal, and when the voltage value of the analog signal is less than or equal to the voltage value of the sawtooth wave, it corresponds to the low level of the pulse signal. level; or, when the voltage value of the analog signal is greater than the voltage value of the sawtooth wave, it corresponds to the low level of the pulse signal, and when the voltage value of the analog signal is less than or equal to the voltage value of the sawtooth wave, it corresponds to the pulse signal high level.

Optionally, in a preferred embodiment, the reference signal is a stepped ramp signal, and the signal processing method includes:

receiving the analog signal and the stepped ramp signal;

comparing the analog signal with the stepped ramp signal;

A pulse signal is output according to the comparison result.

Wherein, when the voltage value of the analog signal is greater than the voltage value of the ladder-shaped ramp signal, corresponding to the high level of the pulse signal, when the voltage value of the analog signal is less than or equal to the voltage value of the ladder-shaped ramp signal , corresponding to the low level of the pulse signal; or, when the voltage value of the analog signal is greater than the voltage value of the stepped ramp signal, corresponding to the low level of the pulse signal, when the voltage value of the analog signal is less than or When it is equal to the voltage value of the ladder-shaped ramp signal, it corresponds to the high level of the pulse signal.

Wherein, the reference signal is a ladder-shaped ramp signal, and the duration of a single input of the ramp signal is calculated as follows:

In a specific embodiment, a ramp signal generator is used to generate a stepped ramp signal. When setting, the step time interval of each step of the ramp signal is set to T _STEP , and the voltage difference of each step is set to V _STEP , If the number of steps of the ramp signal is set to K, then the ramp generator has a total of K steps. Let the duration of a single input of the ramp signal be TR, and the calculation formula is as follows:

TR＝K·T _STEP

In this preferred embodiment, by selecting a ladder-shaped ramp signal and calculating the duration of a single input of the ramp signal through the above calculation method, it is beneficial to control the input of the ramp signal according to the calculated duration of the single input. It makes it possible to more accurately set the duration of a single input of the ramp signal through the software.

Optionally, in an embodiment, comparing the analog signal with the reference signal includes:

When no ramp signal is detected, output low level;

When the input ramp signal is detected, the common mode voltage value of the analog signal is calculated, and the voltage value of the ramp signal increases positively with the lowest value of the common mode voltage value.

It can be understood that since the energy intensity of the signal in different frequency bands is the key signal characteristic of the speech recognition system or other recognition systems, taking the speech recognition system as an example, when the input analog signal When it is a voice signal, in order to obtain the signal energy of different frequency bands, it is necessary to perform half-wave or full-wave rectification on the input voice signal and output a full positive-phase signal.

In this embodiment, T0 is taken as the input time point of the analog signal and the ramp signal. Starting from T0, the ramp signal increases from the lowest value of the common-mode voltage value of the analog signal. At the same time, the analog signal and the When the voltage value of the analog signal is greater than the voltage value of the ramp signal, a high level is output, and when the voltage value of the analog signal is less than or equal to the voltage value of the ramp signal, a low level is output. Because the ramp signal increases positively from the common mode voltage value, when the voltage value of the analog signal is less than or equal to the common mode voltage value, that is, the voltage value of the analog signal is less than or equal to the voltage value of the ramp signal, so at this time The output of the comparator is low level and there is no pulse output. It can be seen that in this process, the Vin+ signal of the analog signal will be converted into a high-level signal corresponding to different pulse widths according to the signal amplitude. Regardless of the signal amplitude of the Vin- signal, the Vin- signal will be converted into a low-level signal, and the total output pulse width signal obtained at this time will be the amplitude integral of the full positive-phase signal.

Please refer to FIG. 2. FIG. 2 is a schematic diagram of a signal waveform in an application scenario of the signal processing method provided by the embodiment of the present application. As shown in Figure 2, the specific rectification process is as follows: the rectification process starts from T0, and the ladder-shaped ramp signal increases from the common-mode voltage value of the input signal (such as an analog signal) VIN. When the voltage value of the ramp signal exceeds When the voltage value of the analog signal is changed, the voltage output by the comparator changes from high level to low level. Because the ramp signal increases from the common-mode voltage value of the input signal VIN, when the input signal VIN is less than the common-mode voltage value of the input signal VIN, the comparator has no pulse output, and the comparator outputs at T0+T time Pulse is 0. Among them, Δt0 is the pulse width obtained by dividing the part where VIN is greater than the common-mode voltage value by the slope of the ramp signal during the T0 period of the input signal, and Δt2 is the pulse width obtained by dividing the part where VIN is greater than the common-mode voltage value by the ramp wave during the T2 period of the input signal. The slope of the signal gives the pulse width.

S103. Outputting a pulse signal according to the comparison result.

In speech recognition systems or other recognition systems, in order to obtain the energy intensity of signals in different frequency bands, it is usually necessary to perform half-wave or full-wave rectification, integration and quantization on analog signals. Among them, the existing technical solutions rectify the input analog signal through a full-bridge or half-bridge rectifier, or through analog signal processing methods such as amplification, filtering, modulation and demodulation, and as a result, the waveform of the rectified analog signal will change. , for example, one of the rectification methods is that the input analog signal is positive A sine wave, through the rectification method, all the anti-phase sine waves of the sine wave are rectified into full positive-phase sine waves. Since the waveform of the rectified analog signal changes, the rectified analog signal is also distorted, resulting in inaccurate extracted features.

However, through the above steps, it can be obtained that the input pulse signal of this program is the comparison result of the reference signal and the analog signal, which is equivalent to sampling from the analog signal, and then outputting a sampling signal, without directly changing the analog signal to output another waveform change after the analog signal.

It can be seen that this embodiment only compares the analog signal with the reference signal, and outputs the rectified pulse signal according to the comparison result, without the need for half-bridge or full-bridge rectifiers and analog signals such as amplification, filtering, modulation, and demodulation. By rectifying the negative signal of the analog signal into a positive signal or rectifying the positive signal of the analog signal into a negative signal, the characteristics of the analog signal can be extracted, so that the analog signal can be processed without changing the waveform of the analog signal. The process of rectification and feature extraction. Therefore, the embodiment of the present application can ensure that the signal is not distorted when performing feature extraction on the analog signal.

Optionally, in an embodiment, in order to realize digital signal output, the signal processing method further includes:

The pulse signal is integrated by a digital integration method.

This embodiment can complete the complete process of rectification, feature extraction and analog-to-digital conversion of the analog signal, while avoiding changing the analog signal and ensuring that the output signal is not distorted.

Optionally, in an embodiment, in order to integrate the pulse signal, the above-mentioned integration of the pulse signal by a digital integration method includes:

Set the integral working hours;

receiving the pulse signal and clock signal;

output the digital signal.

Please refer to FIG. 3 . FIG. 3 is a schematic diagram of signal waveforms in another application scenario of the signal processing method provided by the embodiment of the present application. The total length of the pulse width of the pulse signal is counted as the integral working period TM. In the time period of the integral working period TM, if the pulse signal is received in total H pulses, the width of each pulse will be quantified by the rising edge of the clock, and the corresponding quantized pulses are respectively recorded as N1, N2, ... NH.

Optionally, in an embodiment, within the integration working period, each quantized pulse width of the pulse signal is superimposed to obtain a quantized total pulse width.

The details are as follows: Let the integral working period be TM, after the pulse signal is quantized, each pulse of the pulse signal is recorded as N1, N2, ... NH, then the total pulse width after quantization is recorded as NSUM, and the calculation as follows:

NSUM＝N1+N2+...+NH

It can be understood that this embodiment quantizes the pulse signal within the set integral working period TM, the longer the integral working time TM, the closer the output result is to the ideal half-wave rectifier and integrator result, and the The higher the frequency of the clock signal, the higher the quantization accuracy.

Based on this, the present application provides various specific embodiments of setting the integral working time or setting the frequency of the clock signal on demand, and no examples are given here.

Preferably, the frequency of the clock signal is set to be at least twice the frequency of the pulse signal.

It can be understood that when the frequency of the clock signal is less than twice the frequency of the pulse signal, the digital signal obtained after integration cannot reflect the pulse signal, so the frequency of the clock signal is set to be at least twice the frequency of the pulse signal , and the frequency of the clock signal is three times, four times, or even ten times the frequency of the pulse signal, the error between the digital signal obtained after integration and the pulse signal will be multiplied, the higher the frequency of the clock signal, the quantized The higher the accuracy of the pulse signal.

The present application also provides a signal processing circuit, please refer to FIG. 4 , which is a schematic structural diagram of the signal processing circuit provided by the embodiment of the present application. The signal processing circuit includes a signal generator 201 and a comparator 202 , wherein the signal generator 201 is used to generate a reference signal and send the reference signal to the comparator 202 .

The comparator 202 is used for receiving an analog signal and a reference signal; comparing the analog signal with the reference signal; and outputting a pulse signal according to the comparison result. Wherein, when the voltage value of the analog signal is greater than the voltage value of the reference signal, it corresponds to the high level of the pulse signal, and when the voltage value of the analog signal is less than or equal to the voltage value of the reference signal, it corresponds to the low level of the pulse signal. level; or, when the voltage value of the analog signal is greater than the voltage value of the reference signal, it corresponds to the low level of the pulse signal, and when the voltage value of the analog signal is less than or equal to the voltage value of the reference signal, the The high level of the signal should be pulsed.

In this embodiment, only by comparing the analog signal with the reference signal, and outputting the rectified pulse signal according to the comparison result, there is no need for half-bridge or full-bridge rectifiers and analog signal processing methods such as amplification, filtering, modulation, and demodulation. By rectifying the negative signal of the analog signal into a positive signal or rectifying the positive signal of the analog signal into a negative signal, the characteristics of the analog signal can be extracted, so that the rectification and feature extraction of the analog signal can be completed without changing the waveform of the analog signal the process of. Therefore, the embodiment of the present application can ensure that the signal is not distorted when performing feature extraction on the analog signal.

Optionally, in an embodiment, the signal generator 201 is also used for:

The reference signal is generated every first time interval, and the first time interval is a preset multiple of a single input duration of the reference signal, and the preset multiple is an integer greater than or equal to 1.

It can be understood that the time interval of each input of the ramp signal is set as the first time interval (ie, the sampling interval), and when the first time interval is greater than the duration of a single input of the ramp signal, the Input the time between the end time point of the ramp signal and the start time point of the next input ramp signal to receive and compare the analog signal of another channel. Therefore, this embodiment samples and rectifies multi-channel input signals (i.e., analog signals) by sharing one ramp signal generator 201 and one comparator 202, without requiring multiple rectifiers, reducing chip area, and avoiding A matching problem arises between the rectifiers of the channels.

Optionally, in an embodiment, the reference signal generated by the signal generator 201 is a stepped ramp signal, and the signal generator 201 is also used for:

TR＝K·T _STEP

In this preferred embodiment, by selecting a ladder-shaped ramp signal and calculating the duration of a single input of the ramp signal through the above calculation method, it is beneficial to control the input of the ramp signal according to the calculation method. The calculated duration of a single input enables the software to more accurately set the duration of a single input of the ramp signal.

Optionally, in one embodiment, the comparator 202 is also used to output a low level when no ramp signal is detected; and to calculate the common-mode voltage of the analog signal when an input ramp signal is detected value;

The signal generator 201 is further configured to positively increase the voltage value of the ramp signal with the lowest value of the common mode voltage value.

It can be understood that since the energy intensity of signals in different frequency bands is a key signal feature of a speech recognition system or other recognition systems, taking a speech recognition system as an example, when the input analog signal is a speech signal, in order to obtain signals of different frequency bands Energy, it is necessary to perform half-wave or full-wave rectification on the input voice signal and output a full positive phase signal.

Please refer to FIG. 4 . FIG. 4 is a schematic structural diagram of a signal processing circuit provided by an embodiment of the present application. Optionally, in an embodiment, the signal processing circuit includes a signal generator 201, a comparator 202 and a digital integrator 203, wherein,

The signal generator 201 is used to generate a reference signal and send the reference signal to the comparator 202;

The comparator 202 is used to receive an analog signal and a reference signal; compare the analog signal with the reference signal; output a pulse signal according to the comparison result;

The digital integrator 203 is used for receiving the pulse signal and integrating the pulse signal.

Please refer to FIG. 5 . FIG. 5 is a schematic diagram of a signal processing principle of a signal processing circuit provided in an embodiment of the present application. In the signal processing circuit, the signal generator 201 generates a reference signal V _RAMP , and the reference signal V _RAMP and the analog signal V _IN are input to the comparator 202 ; the reference signal V _RAMP and the analog signal V _IN are input to the comparator 202 After the comparison, a pulse signal is output according to the comparison result; the pulse signal and the clock signal are input to the digital integrator 203; the pulse signal is integrated by the digital integrator 203 to obtain a digital signal and finally output the digital signal.

Optionally, in an embodiment, the digital integrator 203 is also used for:

Set the integral working hours;

receiving the pulse signal and clock signal;

output the digital signal.

NSUM＝N1+N2+...+NH

It should be understood that each part of the present application may be realized by hardware, software, firmware or a combination thereof. In the embodiments described above, various steps or methods may be implemented by software or firmware stored in memory and executed by a suitable instruction execution system. For example, if implemented in hardware, as in another embodiment, it can be implemented by any one or combination of the following techniques known in the art: Discrete logic circuits, ASICs with suitable combinational logic gates, programmable gate arrays (PGA), Field Programmable Gate Array (FPGA), etc.

In addition, each functional unit in each embodiment of the present application may be integrated into one processing module, each unit may exist separately physically, or two or more units may be integrated into one module. The above-mentioned integrated modules can be implemented in the form of hardware or in the form of software function modules. If the integrated modules are realized in the form of software function modules and sold or used as independent products, they can also be stored in a computer-readable storage medium. The storage medium may be a read-only memory, a magnetic disk or an optical disk, and the like.

The above description is the preferred implementation mode of the present application. It should be pointed out that for those of ordinary skill in the art, without departing from the principle of the application, some improvements and modifications can also be made, and these improvements and modifications are also considered For the scope of protection of this application.

The above embodiments are provided only for the purpose of describing the present invention, not to limit the scope of the present invention. The scope of the invention is defined by the appended claims. Various equivalent replacements and modifications made without departing from the spirit and principle of the present invention shall fall within the scope of the present invention.

Claims

A signal processing method is characterized in that, comprising the steps of:

Receive analog signals and reference signals;

comparing the analog signal with the reference signal;

A pulse signal is output according to the comparison result.
The signal processing method according to claim 1, wherein the reference signal is input every first time interval, the first time interval is a preset multiple of a single input duration of the reference signal, and the preset Let the multiple be an integer greater than or equal to 1.
The signal processing method according to claim 2, wherein the reference signal is a ladder-shaped ramp signal, and the duration of a single input of the ramp signal is calculated as follows:

The number of steps of the ramp signal and the second time interval between each step are determined, and the second time interval is multiplied by the number of steps to obtain a single input duration of the ramp signal.
The signal processing method according to claim 3, wherein the comparing the analog signal with the reference signal comprises:

When no ramp signal is detected, output low level;

When the input ramp signal is detected, the common-mode voltage value of the analog signal is calculated, and the voltage value of the ramp signal increases positively with the lowest value of the common-mode voltage value.
The signal processing method according to any one of claims 1 to 4, further comprising the following steps:

The pulse signal is integrated.
The signal processing method according to claim 5, wherein said integrating said pulse signal comprises:

Set the integral working hours;

receiving the pulse signal and clock signal;

Using the pulse rising edge of the clock signal, quantizing the pulse number of the pulse signal into a digital signal;

output the digital signal.
The signal processing method according to claim 6, characterized in that, within the integral working period, each quantized pulse width of the pulse signal is superimposed to obtain the total quantized pulse width.
The signal processing method according to claim 6, wherein the frequency of the clock signal is set to be at least twice the frequency of the pulse signal.
A signal processing circuit, characterized in that it includes a signal generator and a comparator, wherein,

The signal generator is used to generate a reference signal and send the reference signal to the comparator;

The comparator is used to receive an analog signal and a reference signal; compare the analog signal with the reference signal; and output a pulse signal according to the comparison result.
The signal processing circuit according to claim 9, wherein the signal generator is also used for:

The reference signal is generated every first time interval, the first time interval is a preset multiple of a single input duration of the reference signal, and the preset multiple is an integer greater than or equal to 1.
The signal processing circuit according to claim 10, wherein the reference signal is a stepped ramp signal, and the signal generator is also used for:

The number of steps of the ramp signal and the second time interval between each step are determined, and the second time interval is multiplied by the number of steps to obtain a single input duration of the ramp signal.
The signal processing circuit according to claim 11, wherein,

The comparator is also used to output a low level when no ramp signal is detected; when an input ramp signal is detected, calculate the common-mode voltage value of the analog signal;

The signal generator is further configured to positively increase the voltage value of the ramp signal with the lowest value of the common mode voltage value.
The signal processing circuit according to any one of claims 9 to 12, further comprising a digital integrator for:

The pulse signal is received and integrated.
The signal processing circuit according to claim 13, wherein, for said integrating said pulse signal, said digital integrator is further used for:

Set the integral working hours;

receiving the pulse signal and clock signal;

Using the pulse rising edge of the clock signal, quantizing the pulse number of the pulse signal into a digital signal;

output the digital signal.
The signal processing circuit according to claim 14, characterized in that, within the integral working period, each quantized pulse width of the pulse signal is superimposed to obtain a total quantized pulse width.
The signal processing circuit according to claim 14, wherein the frequency of the clock signal is set to be at least twice the frequency of the pulse signal.
A chip, characterized by comprising the signal processing circuit according to any one of claims 9-16.