WO2023140091A1 - リニア電源装置、および電源システム - Google Patents

リニア電源装置、および電源システム Download PDF

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Publication number
WO2023140091A1
WO2023140091A1 PCT/JP2022/048559 JP2022048559W WO2023140091A1 WO 2023140091 A1 WO2023140091 A1 WO 2023140091A1 JP 2022048559 W JP2022048559 W JP 2022048559W WO 2023140091 A1 WO2023140091 A1 WO 2023140091A1
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Prior art keywords
current
power supply
linear power
mirror
transistor
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Ceased
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PCT/JP2022/048559
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English (en)
French (fr)
Japanese (ja)
Inventor
浩樹 猪上
充弘 渡邉
勇武 岩橋
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Rohm Co Ltd
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Rohm Co Ltd
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Priority to JP2023575177A priority Critical patent/JPWO2023140091A1/ja
Priority to DE112022005666.5T priority patent/DE112022005666T5/de
Priority to CN202280088245.7A priority patent/CN118541657A/zh
Publication of WO2023140091A1 publication Critical patent/WO2023140091A1/ja
Priority to US18/769,545 priority patent/US20240370046A1/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10—Regulating voltage or current 
    • G05F1/46—Regulating voltage or current  wherein the variable actually regulated by the final control device is DC
    • G05F1/56—Regulating voltage or current  wherein the variable actually regulated by the final control device is DC using semiconductor devices in series with the load as final control devices
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10—Regulating voltage or current 
    • G05F1/46—Regulating voltage or current  wherein the variable actually regulated by the final control device is DC
    • G05F1/56—Regulating voltage or current  wherein the variable actually regulated by the final control device is DC using semiconductor devices in series with the load as final control devices
    • G05F1/575—Regulating voltage or current  wherein the variable actually regulated by the final control device is DC using semiconductor devices in series with the load as final control devices characterised by the feedback circuit
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10—Regulating voltage or current 
    • G05F1/46—Regulating voltage or current  wherein the variable actually regulated by the final control device is DC
    • G05F1/56—Regulating voltage or current  wherein the variable actually regulated by the final control device is DC using semiconductor devices in series with the load as final control devices
    • G05F1/561—Voltage to current converters
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10—Regulating voltage or current 
    • G05F1/46—Regulating voltage or current  wherein the variable actually regulated by the final control device is DC
    • G05F1/56—Regulating voltage or current  wherein the variable actually regulated by the final control device is DC using semiconductor devices in series with the load as final control devices
    • G05F1/59—Regulating voltage or current  wherein the variable actually regulated by the final control device is DC using semiconductor devices in series with the load as final control devices including plural semiconductor devices as final control devices for a single load
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
    • G05F3/02—Regulating voltage or current
    • G05F3/08—Regulating voltage or current wherein the variable is DC
    • G05F3/10—Regulating voltage or current wherein the variable is DC using uncontrolled devices with non-linear characteristics
    • G05F3/16—Regulating voltage or current wherein the variable is DC using uncontrolled devices with non-linear characteristics being semiconductor devices
    • G05F3/20—Regulating voltage or current wherein the variable is DC using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
    • G05F3/26—Current mirrors
    • G05F3/262—Current mirrors using field-effect transistors only

Definitions

  • the present disclosure relates to linear power supplies and power supply systems.
  • linear power supply devices that can generate a desired output voltage from an input voltage are installed in various applications (vehicle equipment, industrial equipment, office equipment, digital home appliances, portable equipment, etc.).
  • Some linear power supply devices use two linear power supply devices and commonly connect the output terminals for outputting the output voltage of each linear power supply device to a common load (for example, Patent Document 1). That is, such linear power supplies are connected in parallel to a common load.
  • the purpose of such a linear power supply is to disperse heat by distributing the load current to the output current output from the output terminals, and to increase the load current based on the output current output from each output terminal.
  • an object of the present disclosure is to provide a linear power supply device that can effectively perform parallel operation regardless of variations in linear power supply devices in parallel connection applications.
  • a linear power supply is an output transistor having a first end configured to be connectable to an input voltage application end, and a second end configured to be connectable to the first feedback resistor among a first feedback resistor, a second feedback resistor, and a third feedback resistor connected in series; a first error amplifier configured to receive a reference voltage and a feedback voltage generated at a first node to which the second feedback resistor and the third feedback resistor are connected, and configured to drive a control end of the output transistor; an output terminal connected to a second end of the output transistor; a current transmitting/receiving terminal; a first mirror transistor configured to generate a first mirror current of the current flowing through the output transistor; a second mirror transistor configured to generate a second mirror current of the current flowing through the output transistor; a switch circuit that switches between outputting the first mirror current from the current transmission/reception terminal to the outside or receiving the external mirror current from the outside via the current transmission/reception terminal, based on a switching signal; a comparison unit that compare
  • linear power supply device in parallel connection applications, it is possible to effectively perform parallel operation regardless of variations in the linear power supply device.
  • FIG. 1 is a diagram showing the configuration of a power supply system according to a comparative example.
  • FIG. 2 is a diagram showing the configuration of the power supply system according to the first embodiment.
  • FIG. 3 is a diagram showing an operation example in the power supply system according to the first embodiment.
  • FIG. 4 is a diagram showing waveform examples of the output current and the load current.
  • FIG. 5 is a diagram showing the configuration of a linear power supply device according to the second embodiment.
  • FIG. 6 is a diagram showing the configuration of a linear power supply according to the third embodiment.
  • FIG. 7 is a diagram showing the configuration of a linear power supply according to the fourth embodiment.
  • FIG. 8 is a diagram showing the configuration of a power supply system according to the fifth embodiment.
  • FIG. 9 is a diagram showing the configuration of a power supply system according to the sixth embodiment.
  • FIG. 10 is a diagram showing waveform examples of the output current and the load current in the power supply system according to the sixth embodiment.
  • FIG. 1 is a diagram showing the configuration of a power supply system 50 according to a comparative example.
  • the power supply system 50 includes a linear power supply 10A, a linear power supply 10B, and resistors Ra and Rb.
  • Power supply system 50 supplies load current Iout to load RL using two linear power supplies 10A and 10B.
  • the linear power supply devices 10A and 10B are linear regulators that step down the input voltage Vin to generate desired output voltages VoA and VoB, respectively.
  • the linear power supply device 10A and the linear power supply device 10B are ICs (Integrated Circuits) having the same configuration, and the corresponding components are shown with the same reference numerals as "A" or "B".
  • the configuration of the linear power supply device 10A will be representatively described below.
  • the linear power supply 10A is an IC that includes an output transistor M10A, resistors R11A and 12A, and an error amplifier AP10A, which are integrated on one chip.
  • the source of the output transistor M10A configured as a PMOS transistor (P-channel MOSFET (metal-oxide-semiconductor field-effect transistor)) is connected to the input end of the input voltage Vin.
  • the drain of the output transistor M10A and the first end of the resistor R11A are commonly connected to the output terminal ToA for outputting the output voltage VoA.
  • a second end of the resistor R11A is connected to a first end of the resistor R12A.
  • a second end of the resistor R12A is connected to the ground terminal.
  • the inverting input terminal (-) of the error amplifier AP10A is connected to the application terminal of the reference voltage VrefA.
  • the output terminal of the error amplifier AP10A is connected to the gate of the output transistor M10A.
  • the ON resistance value of the output transistor M10B is continuously controlled so that the output voltage VoB matches its target value.
  • the output terminal ToA is connected to the first end of the resistor Ra provided outside the linear power supply devices 10A and 10B.
  • the output terminal ToB is connected to the first terminal of the resistor Rb provided outside the linear power supply devices 10A and 10B.
  • a second end of each of resistors Ra and Rb is commonly connected to a load RL. Therefore, the linear power supplies 10A and 10B are connected in parallel to a common load RL.
  • the output voltages VoA and VoB of the linear power supply devices 10A and 10B are set to be the same, the output voltages may vary from the standard values due to variations in the linear power supply devices. For example, there is a variation of ⁇ 2% with respect to the standard value of 5V. Such variations are caused by, for example, variations in reference voltages, feedback voltages, threshold voltages of output transistors, and input offset voltages of error amplifiers.
  • this comparative example when two linear power supply devices are connected in parallel and used, parallel operation is possible even when there is variation in the output voltage.
  • this comparative example has problems that loss and heat generation occur due to the resistors Ra and Rb and that the output currents IoutA and IoutB are not uniform. Further, when the load current Iout changes, the output voltage Vo changes due to the voltage drop caused by the resistors Ra and Rb, which poses a problem in the regulator function.
  • FIG. 2 is a diagram showing the configuration of the power supply system 5 according to the first embodiment.
  • the power supply system 5 includes a linear power supply 1A and a linear power supply 1B.
  • a power supply system 5 supplies a load current Iout to a load RL using two linear power supplies 1A and 1B.
  • the linear power supply devices 1A and 1B are linear regulators that step down the input voltage Vin to generate desired output voltages VoA and VoB, respectively.
  • the linear power supply device 1A and the linear power supply device 1B are ICs having the same configuration, and corresponding constituent elements are indicated by the same reference numerals with "A” or "B” attached.
  • the configuration of the linear power supply 1A will be representatively described below.
  • the linear power supply 1A includes an output transistor M1A, mirror transistors M2A, M3A, PMOS transistors PM1A, PM2A, NMOS transistors (N-channel MOSFETs) NM1A, NM2A, NM3A, NM4A, feedback resistors R1A, R2A, R3A, R4A, an error amplifier AP1A, and an inverter IV1A.
  • the linear power supply 1A also has external terminals such as an output terminal ToA, a current transmission/reception terminal TiA, and an enable terminal TeA in order to establish electrical connection with the outside.
  • the source of the output transistor M1A configured as a PMOS transistor is connected to the application terminal of the input voltage Vin.
  • the drain of output transistor M1A is connected to the first end of feedback resistor R1A.
  • a second end of the feedback resistor R1A is connected to a first end of the feedback resistor R2A.
  • the second end of feedback resistor R2A is connected to the first end of feedback resistor R3A.
  • a second end of the feedback resistor R3A is connected to a first end of the feedback resistor R4A.
  • a second end of the feedback resistor R4A is connected to ground.
  • the inverting input terminal (-) of the error amplifier AP1A is connected to the application terminal of the reference voltage VrefA.
  • the output terminal of the error amplifier AP1A is connected to the gate of the output transistor M1A.
  • the drain of the NMOS transistor NM4A is connected to the first end of the feedback resistor R4A.
  • the source of NMOS transistor NM4A is connected to the second end of feedback resistor R4A.
  • a gate of the NMOS transistor NM4A is connected to the enable terminal TeA.
  • ENA enable signal
  • the source of the mirror transistor M2A configured as a PMOS transistor is connected to the application terminal of the input voltage Vin.
  • the drain of mirror transistor M2A is connected to the source of PMOS transistor PM1A.
  • the drain of the PMOS transistor PM1A is connected to the drain of the NMOS transistor NM1A.
  • a node where the drain of the PMOS transistor PM1A and the drain of the NMOS transistor NM1A are connected is connected to the current transmission/reception terminal TiA.
  • a gate of the PMOS transistor PM1A and a gate of the NMOS transistor NM1A are connected to the output terminal of the inverter IV1A.
  • the input end of the inverter IV1A is connected to the enable terminal TeA.
  • the gate of mirror transistor M2A is connected to the output terminal of error amplifier AP1A.
  • the PMOS transistor PM1A When the enable signal ENA is at high level, the PMOS transistor PM1A is turned on and the NMOS transistor NM1A is turned off. In this case, a mirror current of the current flowing through the output transistor M1A flows through the mirror transistor M2A.
  • the mirror current is, for example, several hundredths or several thousandths of the current flowing through the output transistor M1A.
  • the mirror current flows through the PMOS transistor PM1A in the ON state and is output to the outside via the current transmission/reception terminal TiA.
  • the switch circuit SWA composed of the PMOS transistor PM1A and the NMOS transistor NM1A switches between externally outputting the mirror current from the current transmitting/receiving terminal TiA and inputting the mirror current externally input via the current transmitting/receiving terminal TiA to the current mirror circuit CMA.
  • the current mirror circuit CMA has an input-side NMOS transistor NM2A and an output-side NMOS transistor NM3A.
  • the drain and gate of NMOS transistor NM2A are shorted.
  • the drain of NMOS transistor NM2A is connected to the source of NMOS transistor NM1A.
  • the gate of NMOS transistor NM2A and the gate of NMOS transistor NM3A are connected.
  • the source of the NMOS transistor NM2A and the source of the NMOS transistor NM3A are commonly connected to the ground terminal.
  • the source of the mirror transistor M3A configured as a PMOS transistor is connected to the application terminal of the input voltage Vin.
  • the drain of mirror transistor M3A is connected to the source of PMOS transistor PM2A.
  • the drain of the PMOS transistor PM2A is connected to the drain of the NMOS transistor NM3A.
  • a gate of the PMOS transistor PM2A is connected to the enable terminal TeA.
  • the gate of mirror transistor M3A is connected to the output terminal of error amplifier AP1A.
  • the PMOS transistor PM2A When the enable signal ENA is at high level, the PMOS transistor PM2A is turned off, and the mirror current Im3A of the current flowing through the output transistor M1A does not flow through the mirror transistor M3A.
  • the enable signal ENA when the enable signal ENA is at low level, the PMOS transistor PM2A is turned on, and the mirror current Im3A of the current flowing through the output transistor M1A flows through the mirror transistor M3A.
  • the mirror current Im3A is, for example, several hundredths or several thousandths of the current flowing through the output transistor M1A.
  • the mirror current Im3A flows through the ON-state PMOS transistor PM2A and into the node N1A where the PMOS transistor PM2A and the NMOS transistor NM3A are connected.
  • the current IcmA mirrored and output by the current mirror circuit CMA and the mirror current Im3A are compared at the node N1A.
  • the current IcmA is larger than the mirror current Im3A, the current is drawn to the node N1A side from the node N2A where the resistors R1A and R2A are connected.
  • current IcmA is smaller than mirror current Im3A, current is injected to node N2A.
  • Feedback voltage VfbA is adjusted according to current extraction/injection to node N2A, and output voltage VoA is controlled.
  • the output terminal ToA of the linear power supply 1A and the output terminal ToB of the linear power supply 1B are commonly connected to the load RL. That is, the linear power supplies 1A and 1B are connected in parallel to a common load RL. Further, a current transmitting/receiving terminal TiA in the linear power supply 1A and a current transmitting/receiving terminal TiB in the linear power supply 1B are connected for transmitting/receiving the mirror current.
  • the linear power supply 1A is set as the master
  • the linear power supply 1B is set as the slave.
  • the NMOS transistor NM4A in the linear power supply 1A is turned on, and the NMOS transistor NM4B in the linear power supply 1B is turned off. Therefore, feedback resistor R4A is bypassed and feedback resistor R4B is not bypassed. Since the feedback resistor R4B is not bypassed, the output voltage VoB is controlled to a lower target value than when bypassed.
  • the feedback resistors R4A and R4B may be set to have resistance values equal to or greater than the voltage difference between the maximum value and the minimum value due to variations in the output voltage. Thus, even if the output voltages VoA and VoB vary, the output voltage VoB can be set lower than VoA.
  • the PMOS transistor PM1A is on and the NMOS transistor NM1A is off, so the mirror transistor M2A outputs the mirror current Im2A from the current transmission/reception terminal TiA to the outside.
  • the linear power supply 1B the PMOS transistor PM1B is off and the NMOS transistor NM1B is on, so the mirror current Im2A flows through the NMOS transistor NM1B via the current transmission/reception terminal TiB from the outside.
  • the mirror current Im2A flowing through the NMOS transistor NM2B on the input side is mirrored by the current mirror circuit CMB to become the current IcmB flowing through the NMOS transistor NM3B on the output side.
  • the PMOS transistor PM2B is on, the mirror current Im3B by the mirror transistor M3B does not flow, so the difference current In2B is drawn from the node N2B to the node N1B side. Therefore, the feedback voltage VfbB is adjusted and the output voltage VoB rises.
  • the differential current In2B increases and the output voltage VoB increases. Then, when the output voltage VoB reaches VoA, the output current IoutB starts to be output from the output terminal ToB in the linear power supply 1B (timing t1 in FIG. 4). That is, the parallel operation of the linear power supply devices 1A and 1B is started.
  • the mirror current Im3B also starts to flow, and depending on the magnitude relationship between the current IcmB and the mirror current Im3B, extraction or injection of the differential current In2B is performed. Therefore, the feedback voltage VfbB is adjusted, and the output current IoutB is controlled so as to approach IoutA.
  • the output currents IoutA and IoutB are also saturated. In FIG. 4, the output currents IoutA and IoutB do not match at saturation, but the accuracy of the current mirror circuit CMB, the offset of the error amplifier AP1B, etc., allow the output currents IoutA and IoutB to match at saturation.
  • the master side outputs mirror current information to the outside, and the slave side receives the mirror current information.
  • the current mirror circuit compares the mirror current information of the current flowing through its own output transistor with the received mirror current information, extracts and injects the difference current that is the result of the comparison, and corrects the output voltage.
  • the linear power supply devices 1A and 1B can also be used alone by setting the enable signals ENA and ENB to high level.
  • the linear power supply may be provided with a logic configuration for setting the linear power supply as a master by setting the enable signals ENA and ENB to low level. In this case, the linear power supply can be used alone by setting the enable signals ENA and ENB to low level.
  • FIG. 5 is a diagram showing the configuration of a linear power supply device 1A according to the second embodiment.
  • the first embodiment (FIG. 2), all the feedback resistors are built inside the IC, but the second embodiment is a modification of the first embodiment regarding the feedback resistors.
  • the difference from the first embodiment (FIG. 2) of the linear power supply device 1A shown in FIG. 5 is that a resistance terminal TrA is provided.
  • a second end of the feedback resistor R3A is connected to the resistor terminal TrA.
  • a first end of a feedback resistor R4A arranged outside the linear power supply 1A is connected to the resistor terminal TrA. That is, in this embodiment, the feedback resistor R4A can be externally attached.
  • the feedback resistor R4A is connected to the resistance terminal Tr, and when the linear power supply is set as the master, the resistance terminal Tr is connected to the ground terminal. Therefore, in this embodiment, the bypass NMOS transistor NM4B is not required.
  • the feedback resistors R1A, R2A, R3A, and R4A may be externally attached to the linear power supply device.
  • FIG. 6 is a diagram showing the configuration of a linear power supply 1A according to the third embodiment.
  • the difference between the configuration shown in FIG. 6 and the first embodiment (FIG. 2) is that the mirror transistors M2A and M3A are shared by the mirror transistor M2A. That is, in the configuration shown in FIG. 6, the drain of the mirror transistor M2A is connected to the sources of the PMOS transistors PM1A and PM2A.
  • the linear power supply 1A when the linear power supply 1A is set as the master, the mirror current flowing through the mirror transistor M2A is output to the outside via the PMOS transistor PM1A and the current transmission/reception terminal TiA. Further, when the linear power supply 1A is set as a slave, the mirror current flowing through the mirror transistor M2A flows through the PMOS transistor PM2A to the current mirror circuit CMA side. According to this embodiment, the number of elements can be reduced.
  • the mirror ratios can be set individually, so that the output currents IoutA and IoutB can be intentionally shifted from being equal.
  • FIG. 7 is a diagram showing the configuration of a linear power supply device 1A according to the fourth embodiment.
  • the difference between the configuration shown in FIG. 7 and the first embodiment (FIG. 2) is that a circuit including an error amplifier AP2A is used instead of the current mirror circuit CMA as a comparison section for comparing mirror currents when set as a slave.
  • a circuit including an error amplifier AP2A is used instead of the current mirror circuit CMA as a comparison section for comparing mirror currents when set as a slave.
  • a linear power supply 1A shown in FIG. 7 has an error amplifier AP2A and sense resistors Rs1A and Rs2A.
  • the source of NMOS transistor NM1A is connected to the first end of sense resistor Rs1A.
  • a second end of the sense resistor Rs1A is connected to the ground end.
  • the drain of PMOS transistor PM2A is connected to the first end of sense resistor Rs2A.
  • a second end of the sense resistor Rs2A is connected to the ground end.
  • the inverting input terminal (-) of the error amplifier AP2A is connected to the first terminal of the sense resistor Rs1A.
  • a non-inverting input terminal (+) of the error amplifier AP2A is connected to a first terminal of the sense resistor Rs2A.
  • the output terminal of the error amplifier AP2A is connected to the node N2A.
  • the mirror current Im2B (mirror current sent from the linear power supply 1B) flowing through the NMOS transistor NM1A from the outside via the current transmission/reception terminal TiA is converted into the voltage Vs1A by the sense resistor Rs1A.
  • mirror current Im3A flowing through PMOS transistor PM2A by mirror transistor M3A is converted to voltage Vs2A by sense resistor Rs2A.
  • the error amplifier AP2A extracts/injects a current In2A to/from the node N2A based on the difference between the input voltages Vs1A and Vs2A. According to this embodiment, the output current IoutA can be controlled more accurately.
  • FIG. 8 is a diagram showing the configuration of the power supply system 5 according to the fifth embodiment.
  • the configuration shown in FIG. 8 differs from the first embodiment (FIG. 2) in that the linear power supply devices 1A and 1B are provided with sense resistors Rs3A and Rs3B, offset comparators CMP1A and CMP1B, constant current sources CI1A and CI1B, and constant current sources CI2A and CI2B.
  • a first end of the sense resistor Rs3A is connected to a node where the PMOS transistor PM1A and the NMOS transistor NM1A are connected.
  • a second end of the sense resistor Rs3A is connected to the current transmission/reception terminal TiA.
  • a first input terminal of the offset comparator CMP1A is connected to a first terminal of the sense resistor Rs3A.
  • a second input terminal of the offset comparator CMP1A is connected to a second terminal of the sense resistor Rs3A.
  • Constant current source CI1A is connected to the first end of sense resistor Rs3A.
  • Constant current source CI2A is connected to the second end of sense resistor Rs3A.
  • a comparison signal CpoutA which is the output of the offset comparator CMP1A, is input to the inverter IV1A.
  • the load current Iout begins to flow, and a mirror current flows to the outside from the current transmitting/receiving terminal TiA or TiB of the linear power supply 1A or 1B, whichever of the output currents IoutA and IoutB flows first.
  • the mirror current flows from the outside into the current transmitting/receiving terminal TiA or TiB of the linear power supply 1A or 1B, whichever of the output currents IoutA and IoutB does not flow, and the mirror current flows through the sense resistor Rs3A or Rs3B in the linear power supply 1A or 1B.
  • the comparison signal CpoutA or CpoutB output from the offset comparator CMP1A or CMP1B in the linear power supply 1A or 1B, whichever of the output currents IoutA and IoutB does not flow, is switched to low level. Therefore, of the output currents IoutA and IoutB, the linear power supply 1A or 1B, which is not flowing, is set as the slave.
  • the constant current sources CI2A and CI2B have a constant current value N times (N>1) the constant current values of the constant current sources CI1A and CI2A, respectively. This prevents the comparison signal CpoutA or CpoutB from switching to a low level unless a certain amount of current flows into the current transmitting/receiving terminal TiA or TiB from the outside, thereby suppressing erroneous operation and setting as a slave when the load current Iout does not flow.
  • master/slave setting is possible without providing external terminals for inputting the enable signals ENA and ENB.
  • FIG. 9 is a diagram showing the configuration of a power supply system 5 according to the sixth embodiment.
  • the power supply system 5 includes a linear power supply 1A, a linear power supply 1B, and a linear power supply 1C.
  • Power supply system 5 supplies load current Iout to load RL using three linear power supplies 1A, 1B, and 1C.
  • the circuit configurations of the linear power supply devices 1A, 1B, 1C are similar to the linear power supply devices 1A, 1B of the first embodiment (FIG. 2) described above.
  • the linear power supply 1A is set as the master, and the linear power supplies 1B and 1C are set as slaves.
  • the output terminals ToB and ToC of the linear power supply devices 1B and 1C are commonly connected to the output terminal ToA of the linear power supply device 1A.
  • Current transmission/reception terminals TiB and TiC in the linear power supply devices 1B and 1C are commonly connected to a current transmission/reception terminal TiA in the linear power supply device 1A.
  • FIG. 10 is a diagram showing waveform examples of the output currents IoutA, IoutB, IoutC and the load current Iout in the power supply system 5 according to the present embodiment.
  • the output currents IoutB and IoutC are not output from the output terminals ToB and ToC of the linear power supply devices 1B and 1C set as slaves at the beginning, and the load current Iout is supplied only by the output current IoutA output from the output terminal ToA of the linear power supply device 1A set as the master.
  • the output currents IoutB and IoutC rise, and the parallel operation of the linear power supply devices 1A, 1B and 1C is performed.
  • the output current IoutA is controlled to about 1/2 of the load current Iout, and the output currents IoutB and IoutC are further controlled to about 1/2 each of the output current IoutA.
  • linear power supply units set as slaves may be connected to one linear power supply unit set as the master.
  • linear power supply device having a configuration according to an embodiment other than the first embodiment to the present embodiment.
  • the linear power supply device (1A) is an output transistor (M1A) having a first end configured to be connectable to an application end of an input voltage (Vin) and a second end configured to be connectable to the first feedback resistor in a first feedback resistor (R1A), a second feedback resistor (R2A), and a third feedback resistor (R3A) connected in series; a first error amplifier (AP1A) configured to receive a feedback voltage (VfbA) generated at a first node to which the second feedback resistor and the third feedback resistor are connected and a reference voltage (VrefA), and configured to be able to drive the control end of the output transistor; an output terminal (ToA) connected to the second end of the output transistor; a current transmitting/receiving terminal (TiA); a first mirror transistor (M2A) configured to generate a first mirror current (Im2A) of the current flowing through the output transistor; a second mirror transistor (
  • a configuration including a fourth feedback resistor (R4A) that is configured to be connectable to the third feedback resistor (R3A) and a bypass switch (NM4A) that switches whether to bypass the fourth feedback resistor based on the switching signal (ENA) may be provided (second configuration, FIG. 2).
  • the third feedback resistor (R3A) and a resistor terminal (TrA) may be provided, and a fourth feedback resistor (R4A) or a ground terminal may be connected to the resistor terminal (third configuration, FIG. 5).
  • an external terminal (TeA) configured to allow the switching signal (ENA) to be input may be provided (fourth configuration, FIG. 2).
  • the first mirror transistor (M2A) and the second mirror transistor (M3A) may be configured separately (fifth configuration, FIG. 2).
  • the first mirror transistor and the second mirror transistor may be the same transistor (M2A) (sixth configuration, FIG. 6).
  • the switch circuit may a PMOS transistor (PM1A) including a source connected to the first mirror transistor (M2A) and a gate driven based on the switching signal (ENA);
  • PMOS transistor PM1A
  • NMOS transistor NM1A
  • CMA comparator
  • the comparator may be a current mirror circuit (CMA) that mirrors and outputs the input external mirror current (eighth configuration, FIG. 2).
  • CMA current mirror circuit
  • the comparison unit includes a first sense resistor (Rs1A) for current/voltage conversion of the external mirror current to a first voltage (Vs1A); a second sense resistor (Rs2A) for current/voltage conversion of the second mirror current (Im3A) to a second voltage (Vs2A); A second error amplifier (AP2A) that extracts current from the second node (N2A) or injects current into the second node based on the difference between the first voltage and the second voltage (ninth configuration, FIG. 7).
  • Rs1A first sense resistor
  • Rs2A second sense resistor
  • Im3A second mirror current
  • Vs2A second voltage
  • a second error amplifier (AP2A) that extracts current from the second node (N2A) or injects current into the second node based on the difference between the first voltage and the second voltage (ninth configuration, FIG. 7).
  • a sense resistor having a first end connected to the switch circuit (SWA) and a second end connected to the current transmission/reception terminal (TiA), an offset comparator (CMP1A) having input terminals connected to both ends of the sense resistor and capable of outputting the switching signal (CpoutA), and a first constant current source (CI1A) connected to the first end of the sense resistor.
  • a second constant current source (CI2A) connected to the second end of the sense resistor, wherein the constant current value of the second constant current source is a natural number multiple greater than 1 of the constant current value of the first constant current source (tenth configuration, FIG. 8).
  • the power supply system (5) includes two linear power supply devices (1A, 1B) having any one of the first to tenth configurations, the output terminals (ToA, ToB) of the two linear power supply devices can be commonly connected to a load (RL), and the current transmission/reception terminals (TiA, TiB) of the two linear power supply devices can be connected to each other (eleventh configuration).
  • the power supply system (5) is one master linear power supply (1A), which is the linear power supply having any one of the first to tenth configurations and is set as a master for outputting the first mirror current from the current transmitting/receiving terminal to the outside; two or more slave linear power supply devices (1B, 1C), which are the linear power supply devices having any one of the first to tenth configurations and are set as slaves to which the external mirror current is input from the outside via the current transmission/reception terminals; with the output terminals (ToB, ToC) of the two or more slave linear power supply devices are commonly connected to the output terminal (ToA) of the master linear power supply device,
  • the current transmission/reception terminals (TiB, TiC) of the two or more slave linear power supply units are commonly connected to the current transmission/reception terminal (TiA) of the master linear power supply unit (twelfth configuration, FIG. 9).
  • the present disclosure can be used for power supply systems installed in various devices.

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  • Continuous-Control Power Sources That Use Transistors (AREA)
PCT/JP2022/048559 2022-01-19 2022-12-28 リニア電源装置、および電源システム Ceased WO2023140091A1 (ja)

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DE112022005666.5T DE112022005666T5 (de) 2022-01-19 2022-12-28 Linearstromversorgungsvorrichtung und stromversorgungssystem
CN202280088245.7A CN118541657A (zh) 2022-01-19 2022-12-28 线性电源装置以及电源系统
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JPS54104947U (https=) * 1978-01-09 1979-07-24
JPH10260743A (ja) * 1997-03-18 1998-09-29 Sharp Corp 直流安定化電源
JP2020004214A (ja) * 2018-06-29 2020-01-09 ローム株式会社 リニアレギュレータ
US20200042026A1 (en) * 2018-07-31 2020-02-06 Analog Devices Global Unlimited Company Load-dependent control of parallel regulators

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JP4989254B2 (ja) 2007-02-21 2012-08-01 株式会社 日立東日本ソリューションズ 信用リスク計算装置、および、信用リスク計算方法
JP5771429B2 (ja) * 2010-05-28 2015-08-26 ローム株式会社 スイッチング電源装置
US8842225B2 (en) * 2012-05-14 2014-09-23 Rohm Co., Ltd. Switching power supply device
JP6023468B2 (ja) * 2012-05-23 2016-11-09 ローム株式会社 スイッチング電源装置
US10003265B2 (en) * 2014-07-28 2018-06-19 Rohm Co., Ltd. Switching power supply device
JP6328072B2 (ja) * 2015-04-10 2018-05-23 ローム株式会社 オン時間設定回路、電源制御ｉｃ、スイッチング電源装置

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JPS54104947U (https=) * 1978-01-09 1979-07-24
JPH10260743A (ja) * 1997-03-18 1998-09-29 Sharp Corp 直流安定化電源
JP2020004214A (ja) * 2018-06-29 2020-01-09 ローム株式会社 リニアレギュレータ
US20200042026A1 (en) * 2018-07-31 2020-02-06 Analog Devices Global Unlimited Company Load-dependent control of parallel regulators

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