WO2023134129A1 - 一种保护pcie卡电源的方法、电路、装置及介质 - Google Patents

一种保护pcie卡电源的方法、电路、装置及介质 Download PDF

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Publication number
WO2023134129A1
WO2023134129A1 PCT/CN2022/102095 CN2022102095W WO2023134129A1 WO 2023134129 A1 WO2023134129 A1 WO 2023134129A1 CN 2022102095 W CN2022102095 W CN 2022102095W WO 2023134129 A1 WO2023134129 A1 WO 2023134129A1
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WO
WIPO (PCT)
Prior art keywords
mos transistor
power supply
prsnt
voltage
signal
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Ceased
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PCT/CN2022/102095
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English (en)
French (fr)
Inventor
陈三霞
刘铁军
计晶
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Suzhou Wave Intelligent Technology Co Ltd
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Suzhou Wave Intelligent Technology Co Ltd
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Priority to US18/697,441 priority Critical patent/US12314107B2/en
Publication of WO2023134129A1 publication Critical patent/WO2023134129A1/zh
Anticipated expiration legal-status Critical
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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/32—Means for protecting converters other than automatic disconnection
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/28—Supervision thereof, e.g. detecting power-supply failure by out of limits supervision
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/266—Arrangements to supply power to external peripherals either directly from the computer or under computer control, e.g. supply of power through the communication port, computer controlled power-strips
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4063—Device-to-bus coupling
    • G06F13/4068—Electrical coupling
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
    • H02H9/00—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection
    • H02H9/02—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess current
    • H02H9/025—Current limitation using field effect transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
    • H10D89/60—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD]
    • H10D89/601—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs
    • H10D89/811—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs using FETs as protective elements
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F2213/0026—PCI express
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02T—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO TRANSPORTATION
    • Y02T90/00—Enabling technologies or technologies with a potential or indirect contribution to GHG emissions mitigation
    • Y02T90/10—Technologies relating to charging of electric vehicles
    • Y02T90/16—Information or communication technologies improving the operation of electric vehicles
    • Y02T90/167—Systems integrating technologies related to power network operation and communication or information technologies for supporting the interoperability of electric or hybrid vehicles, i.e. smartgrids as interface for battery charging of electric vehicles [EV] or hybrid vehicles [HEV]
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y04—INFORMATION OR COMMUNICATION TECHNOLOGIES HAVING AN IMPACT ON OTHER TECHNOLOGY AREAS
    • Y04S—SYSTEMS INTEGRATING TECHNOLOGIES RELATED TO POWER NETWORK OPERATION, COMMUNICATION OR INFORMATION TECHNOLOGIES FOR IMPROVING THE ELECTRICAL POWER GENERATION, TRANSMISSION, DISTRIBUTION, MANAGEMENT OR USAGE, i.e. SMART GRIDS
    • Y04S30/00—Systems supporting specific end-user applications in the sector of transportation
    • Y04S30/10—Systems supporting the interoperability of electric or hybrid vehicles
    • Y04S30/12—Remote or cooperative charging

Definitions

  • the present application relates to the field of board card hardware design, in particular to a method, circuit, device and medium for protecting the power supply of a PCIE card.
  • PCIE Peripheral Component Interconnect Express
  • the hot-swappable chip controls the instantaneous current generated when the PCIE card is plugged in with power to achieve power protection when plugged in with power.
  • installing a hot-swappable chip on the PCIE card will increase the design cost of the PCIE card.
  • the present application provides a circuit for protecting the power supply of a PCIE card, including: a first MOS transistor, a second MOS transistor, a controller, a first resistor, and a second resistor;
  • the first end of the first resistor is connected to the first power supply, and the second end of the first resistor is connected to the source of the second MOS transistor;
  • the first end of the second resistor is connected to the first power supply, and the second end of the second resistor is connected to the gate of the second MOS transistor;
  • the drain of the second MOS transistor is connected to the PRSNT# pin, and the source of the second MOS transistor is connected to the controller, which is used to respond to the PRSNT# signal generated by grounding the PRSNT# pin in response to all PCIE cards being inserted into the server slot transmitted to the controller;
  • the first end of the controller is connected to the common end of the first resistor and the second MOS tube, and the second end of the controller is connected to the first MOS tube, for responding to the fact that the PCIE cards are not fully inserted into the server slot, according to the first
  • the EV_PRSNT signal generated by the power supply during the release of electric energy turns off the first MOS tube, and in response to all PCIE cards being inserted into the server slot, the first MOS tube is turned on according to the PRSNT# signal;
  • the source of the first MOS transistor is connected to the second power supply for transmitting electric energy released by the second power supply.
  • the controller includes a current pump, a first voltage comparator, a second voltage comparator, and a third MOS tube;
  • the current pump is connected to the grid of the first MOS tube, and is used to charge the grid of the first MOS tube in response to the PCIE card being fully inserted into the server slot;
  • the non-inverting input end of the first voltage comparator is connected with the drain of the first MOS transistor, the inverting input end of the first voltage comparator is connected with the source electrode of the first MOS transistor, the output end of the first voltage comparator is connected with the third The gate connection of the MOS transistor is used to output the first voltage signal to the third MOS transistor according to the voltage difference between the drain voltage and the source voltage of the first MOS transistor;
  • the noninverting input terminal of the second voltage comparator is connected to the common terminal of the first resistor and the second MOS transistor, the inverting input terminal of the second voltage comparator is grounded, and the output terminal of the second voltage comparator is connected to the gate of the third MOS transistor. pole connection, for outputting the second voltage signal to the third MOS transistor according to the EV_PRSNT signal, and outputting the third voltage signal to the third MOS transistor according to the PRSNT# signal;
  • the drain of the third MOS transistor is connected to the first MOS transistor, and the source of the third MOS transistor is connected to the second power supply.
  • the application also provides a method for protecting the PCIE card power supply, which is applied to a circuit for protecting the PCIE card power supply, the method comprising:
  • a PRSNT# signal is generated according to the grounded PRSNT# pin;
  • the controller is controlled to turn off the first MOS transistor according to the EV_PRSNT signal.
  • controlling the turn-on and turn-off of the second MOS transistor includes:
  • the on and off of the second MOS transistor is controlled according to the PRSNT# signal, the voltage of the first power supply, the voltage across the first resistor and the voltage across the second resistor; wherein, the resistance of the first resistor is smaller than that of the second resistor.
  • the control controller in response to the fact that the PCIE cards are not fully inserted into the server slot, before the control controller turns off the first MOS tube, it also includes:
  • the electrical energy released by the second power source charges the controller.
  • charging the load with the electric energy released by the second power source includes:
  • the electric energy released by the second power supply is controlled to charge the load through the body diode of the first MOS transistor.
  • the application also provides a device for protecting the power supply of the PCIE card, which is applied to a circuit for protecting the power supply of the PCIE card, including:
  • the first control module is used to control the first power supply and the second power supply to release electric energy in response to not all PCIE cards being inserted into the server slot;
  • the second control module is used to control the controller to turn off the first MOS transistor according to the EV_PRSNT signal generated by the first power supply during the release of electric energy;
  • the charging module is used to charge the load with the electric energy released by the second power supply;
  • a generating module configured to generate a PRSNT# signal according to a grounded PRSNT# pin in response to all insertions of the PCIE cards into the server slot;
  • the third control module is used to control the turn-on and turn-off of the second MOS transistor
  • the fourth control module is configured to control the controller to turn on the first MOS transistor according to the PRSNT# signal flowing through the second MOS transistor.
  • the application also provides a device for protecting the power supply of the PCIE card, which is applied to a circuit for protecting the power supply of the PCIE card, including:
  • the processor is used for implementing the steps of the above method for protecting the power supply of the PCIE card when executing the computer program.
  • the present application also provides a computer-readable storage medium, on which a computer program is stored, and when the computer program is executed by a processor, the steps of the above-mentioned method for protecting the PCIE card power supply are implemented.
  • Fig. 1 is the structural diagram of a kind of protection circuit of PCIE card power supply provided by the application;
  • Fig. 2 is a flow chart of a method for protecting the PCIE card power supply provided by the application
  • Fig. 3 is a structural diagram of a device for protecting a PCIE card power supply provided by the present application
  • FIG. 4 is a structural diagram of another device for protecting a power supply of a PCIE card provided by the present application.
  • the core of the application is to provide a method for protecting the power supply of the PCIE card, which is used to suppress the surge current when the PCIE card is plugged in and out, protect the PCIE card, and reduce the cost of the PCIE card.
  • FIG. 1 is a structural diagram of a circuit for protecting a PCIE card power supply provided by the present application.
  • the circuit for protecting a PCIE card power supply shown in FIG. 1 will be described below.
  • the circuit for protecting the power supply of the PCIE card includes a first MOS transistor Q1, a second MOS transistor Q2, a controller 1, a first resistor R1 and a second resistor R2; the first end of the first resistor R1 is connected to the first power supply, and the first The second end of the resistor R1 is connected to the source of the second MOS transistor Q2; the first end of the second resistor R2 is connected to the first power supply, and the second end of the second resistor R2 is connected to the gate of the second MOS transistor Q2;
  • the drain of the second MOS transistor Q2 is connected to the PRSNT# pin, and the source of the second MOS transistor Q2 is connected to the controller 1, which is used to ground the PRSNT# pin when all PCIE cards are inserted into the server slot.
  • the PRSNT# signal is transmitted to the controller 1; the first end of the controller 1 is connected to the common end of the first resistor R1 and the second MOS transistor Q2, and the second end of the controller 1 is connected to the first MOS transistor Q1 for When the PCIE cards are not fully inserted into the server slots, turn off the first MOS transistor Q1 according to the EV_PRSNT signal generated by the first power supply during the release of electric energy, and turn on the first MOS transistor Q1 according to the PRSNT# signal when all the PCIE cards are inserted into the server slots.
  • a MOS transistor Q1; the source of the first MOS transistor Q1 is connected to the second power supply for transmitting the electric energy released by the second power supply.
  • the length of the PRSNT# pin is shorter.
  • the first power supply and the second power supply Both power supplies will release electric energy, and the PRSNT# signal generated by the PRSNT# pin will always be in a high level state under the pull-up action of the first resistor R1.
  • the EV_PRSNT signal generated by the first power supply during the release of electric energy is also at high state.
  • the controller 1 Since the controller 1 turns off the first MOS transistor Q1 when receiving a high level and turns on the first MOS transistor Q1 when receiving a low level, the controller 1 will keep the first MOS transistor Q1 off according to the received EV_PRSNT signal At this time, the second power supply on the gold finger will charge the load through the body diode of the first MOS transistor Q1.
  • the PRSNT# pin When the PRSNT# pin is inserted into the preset position in the server slot, it is considered that the PCIE card is fully inserted into the server slot, and the PRSNT# pin will be connected to the ground by the short-circuit wire of the PCIE card.
  • the PRSNT# pin generates
  • the PRSNT# signal is at low level
  • the source voltage of the second MOS transistor Q2 is the turn-on voltage of the body diode of the second MOS transistor Q2, and the gate voltage is still high under the pull-up effect of the second resistor R2 Therefore, the gate voltage of the second MOS transistor Q2 will be greater than its source voltage; when the voltage difference between the gate voltage and the source voltage of the second MOS transistor Q2 is greater than its own turn-on voltage, the second MOS transistor Q2
  • the transistor Q2 is turned on, and the EV_PRSNT signal in the high-level state will be pulled down to ground by the PRSNT# signal flowing through the second MOS transistor Q2.
  • the voltage signal received by the controller 1 at this time is the PRSNT in the low-level state. #Signal. Since the PRSNT# signal is at a low level, the controller 1 will turn on the first MOS transistor Q1 according to the PRSNT# signal, and at this time the second power supply can directly charge the load. Since the second power supply has already precharged the load through the body diode of the first MOS transistor Q1 when the PCIE cards are not fully inserted into the server slot, therefore, when the first MOS transistor Q1 is turned on, the load when the PCIE card is inserted can be effectively reduced. Inrush current.
  • the preset position in this embodiment can be the top position of the pins when all the PRSNT# pins are inserted into the server slot, or the top position of the pins when all the PRSNT# pins are inserted into the server slot.
  • the two thirds are set according to the actual situation, which is not limited in this embodiment.
  • the two PRSNT# pins in this embodiment, which are respectively located at the two ends of the PCIE gold finger, and the two PRSNT# pins are connected together, and its common end is connected to the The drain of the second MOS transistor Q2 is connected.
  • the PRSNT# pin will reach the preset position in the server slot, and then will be connected to the ground by the short-circuit line of the PCIE card, so that the PRSNT# signal generated by it becomes low level.
  • the number of PRSNT# pins is not limited to two, and the position of the PRSNT# pin is not limited to the two ends of the PCIE golden finger, which can be set according to the actual situation. This embodiment does not limit the number and position of the PRSNT# pin .
  • the PRSNT# pin When the gold finger of the PCIE card is charged and pulled out, because the PRSNT# pin is short, it will leave the server slot first.
  • the PRSNT# pin leaves the preset position of the server slot, the PRSNT# signal returns to the high level under the pull-up action of the first resistor R1, and the second MOS transistor Q2 at this time does not satisfy the gate voltage and source voltage.
  • the voltage difference of the electrode voltage is greater than its turn-on voltage, the second MOS transistor Q2 is turned off, and the EV_PRSNT signal also returns to a high level under the pull-up action of the first resistor R1, and the controller 1 turns off the first MOS transistor according to the EV_PRSNT signal Transistor Q1, so as to realize the directional turn-off of the body diode of the first MOS transistor Q1, which can effectively suppress the surge current generated when the PCIE card is pulled out with power on.
  • the high level and the low level are relative, and the high level in this application refers to the high voltage state when it is relatively low.
  • the EV_PRSNT signal in this embodiment is high The low level state of the PRSNT# signal generated by the PRSNT# pin being grounded, the voltage of the EV_PRSNT signal is higher.
  • This embodiment describes the circuit for protecting the PCIE card power supply, the circuit includes a first MOS tube, a second MOS tube, a controller, a first resistor and a second resistor; the first end of the first resistor is connected to the first power supply , the second end is connected to the source of the second MOS transistor; the first end of the second resistor is connected to the first power supply, and the second end is connected to the gate of the second MOS transistor; the drain of the second MOS transistor is connected to PRSNT# Pin connection, the source is connected to the controller, which is used to transmit the PRSNT# signal generated by grounding the PRSNT# pin to the controller when all the PCIE cards are inserted into the server slot; the first end of the controller is connected to the first resistor It is connected to the common end of the second MOS tube, and the second end is connected to the first MOS tube, which is used to turn off the first MOS tube, and when the PCIE card is fully inserted into the server slot, the first MOS tube is turned on according to the PR
  • the second power supply precharges the load through the body diode of the first MOS tube, so it can effectively reduce the load when all the PCIE cards are inserted into the server slot.
  • slot that is, the surge current generated when the first MOS tube is turned on; when the PCIE card is not fully pulled out, the load is disconnected from the second power supply by turning off the first MOS tube, so as to suppress the charging when the PCIE card is pulled out
  • the surge current generated effectively protects the power supply of the PCIE card.
  • the controller 1 includes a current pump, a first voltage comparator, a second voltage comparator, and a third MOS tube; the current pump is connected to the gate of the first MOS tube Q1, and is used for when all PCIE cards are inserted into the server slot, Charge the gate of the first MOS transistor Q1; the non-inverting input terminal of the first voltage comparator is connected to the drain of the first MOS transistor Q1, and the inverting input terminal of the first voltage comparator is connected to the source of the first MOS transistor Q1 connected, the output terminal of the first voltage comparator is connected to the gate of the third MOS transistor, and is used to output the first voltage signal to the third MOS transistor according to the voltage difference between the drain voltage and the source voltage of the first MOS transistor Q1; The noninverting input terminal of the second voltage comparator is connected to the common terminal of the first resistor R1 and the second MOS transistor Q2, the inverting input terminal of the second voltage comparator is grounded, and the output terminal of the second voltage comparator is connected to the third MO
  • the gate connection of the gate is used to output the second voltage signal to the third MOS transistor according to the EV_PRSNT signal, and output the third voltage signal to the third MOS transistor according to the PRSNT# signal; the drain of the third MOS transistor is connected to the first MOS transistor Q1 connected, and the source of the third MOS transistor is connected to the second power supply.
  • the first MOS transistor Q1 When the PCIE card is just inserted into the server slot, the first MOS transistor Q1 is turned off, and the electric energy released by the second power supply charges the load through the body diode of the first MOS transistor Q1.
  • the controller 1 receives at this moment is the PRSNT# signal in a low level state.
  • the current pump After the controller 1 receives the PRSNT# signal, the current pump will charge the gate of the first MOS transistor Q1 until the gate voltage of the first MOS transistor Q1 is greater than its source voltage, and the first MOS transistor Q1 is turned on. At this time The second power supply can charge the load through the first MOS transistor Q1.
  • the first voltage comparator will collect the drain voltage and source voltage of the first MOS transistor Q1, and according to the drain voltage and source voltage of the first MOS transistor Q1 The voltage difference of the electrode voltage outputs the first voltage signal to the third MOS transistor. If the voltage difference between the drain voltage and the source voltage of the first MOS transistor Q1 exceeds the threshold voltage, it is considered that a surge current is generated.
  • the first The first voltage signal output by the voltage comparator to the gate of the third MOS transistor is at a high level, and the third MOS transistor is turned on, so that the gate of the first MOS transistor Q1 is connected to the source, that is, the gate of the first MOS transistor Q1 is connected to the source.
  • the gate voltage is equal to the source voltage, therefore, the first MOS transistor Q1 is turned off, realizing the disconnection of the second power supply from the load, which can effectively suppress the generated surge current; if the drain voltage of the first MOS transistor Q1 and If the voltage difference of the source voltage does not exceed the threshold voltage, the first voltage signal output to the gate of the third MOS transistor is low level.
  • the threshold voltage is taken as 30mV, when the drain voltage of the first MOS transistor Q1 collected by the first voltage comparator and When the voltage difference of the source voltage is greater than 30mV, the first voltage signal output by the first voltage comparator to the gate of the third MOS transistor is at a high level.
  • the threshold voltage is not limited to 30mV, and an appropriate threshold voltage can be selected according to actual conditions, which is not limited in this embodiment.
  • the non-inverting input terminal of the second voltage comparator will receive the EV_PRSNT signal generated by the first power supply to release the electric energy.
  • the second voltage signal output by the gate is at a high level.
  • the third MOS transistor is turned on, and the gate of the first MOS transistor Q1 is connected to the source, which does not meet the conduction condition of the first MOS transistor Q1.
  • the first MOS transistor Q1 is turned off.
  • the PRSNT# signal received by the non-inverting input end of the second voltage comparator is low level, so the third voltage signal output to the gate of the third MOS transistor is low level, At this time, the gate voltage of the third MOS transistor is not greater than its source voltage, which does not meet the conduction condition of the third MOS transistor, and the third MOS transistor is turned off; since the controller 1 receives the PRSNT# signal, the current pump will Charge the gate of the first MOS transistor Q1, so when the gate voltage of the first MOS transistor Q1 is greater than its source voltage, the first MOS transistor Q1 is turned on, realizing the conduction when all PCIE cards are inserted into the server slot. Pass through the first MOS tube Q1.
  • the output terminal of the first voltage comparator and the output terminal of the second voltage comparator are connected to the gate of the third MOS transistor through a NOT gate circuit, that is to say, as long as the first voltage comparator and the second voltage comparator There is an output terminal in the comparator that outputs a high level, and the voltage signal received by the gate of the third MOS transistor is a high level. At this time, the third MOS transistor will be turned on, and the first MOS transistor Q1 will be turned off. .
  • the controller includes a current pump, a first voltage comparator, a second voltage comparator and a third MOS tube; the current pump is connected to the gate of the first MOS tube for When all the PCIE cards are inserted into the server slot, the gate of the first MOS tube is charged; the non-inverting input terminal of the first voltage comparator is connected to the drain of the first MOS tube, and the inverting input terminal of the first voltage comparator It is connected to the source of the first MOS transistor, and the output terminal of the first voltage comparator is connected to the gate of the third MOS transistor, which is used to send the voltage to the third MOS transistor according to the voltage difference between the drain voltage and the source voltage of the first MOS transistor.
  • the tube outputs the first voltage signal; the noninverting input terminal of the second voltage comparator is connected to the common terminal of the first resistor and the second MOS tube, the inverting input terminal of the second voltage comparator is grounded, and the output terminal of the second voltage comparator It is connected to the gate of the third MOS transistor, and is used to output the second voltage signal to the third MOS transistor according to the EV_PRSNT signal, and output the third voltage signal to the third MOS transistor according to the PRSNT# signal; the drain of the third MOS transistor is connected to the third MOS transistor.
  • the first MOS transistor is connected, and the source of the third MOS transistor is connected to the second power supply.
  • the second voltage comparator outputs a corresponding voltage signal to the third MOS transistor according to the EV_PRSNT signal and the PRSNT# signal, and turns off the first MOS transistor by turning on the third MOS transistor, and turns off the third MOS transistor by turning off the third MOS transistor.
  • the first MOS transistor is turned on, so as to control the turn-on and turn-off of the first MOS transistor.
  • the first voltage comparator monitors the drain voltage and source voltage of the first MOS transistor, and when the voltage difference between the drain voltage and the source voltage of the first MOS transistor is greater than the threshold voltage, it outputs a high voltage to the third MOS transistor. level of the first voltage signal to turn off the first MOS transistor, effectively suppressing the surge current and protecting the power supply of the PCIE card.
  • FIG. 2 is a flowchart of a method for protecting a PCIE card power supply provided by the present application, and the method is applied to the circuit for protecting a PCIE card power supply in the above-mentioned embodiment. As shown in Figure 2, the method includes:
  • S2 Control the controller to turn off the first MOS tube according to the EV_PRSNT signal generated by the first power supply during the release of electric energy;
  • S5 Control the conduction of the second MOS transistor, and control the controller to conduct the first MOS transistor according to the PRSNT# signal flowing through the second MOS transistor;
  • S7 Control the controller to turn off the first MOS transistor according to the EV_PRSNT signal.
  • the PCIE card when the PCIE card is not fully inserted into the server slot, the PCIE card first controls the discharge of the first power supply and the second power supply. At this time, the controller will receive the EV_PRSNT signal generated when the first power supply releases electric energy.
  • the EV_PRSNT signal is at a high level under the action of the pull-up resistor.
  • the controller when the controller receives a high-level voltage signal, it will turn off the external MOS tube. Therefore, the PCIE card will be turned off by the controller.
  • the first MOS transistor enables the electric energy released by the second power supply to charge the load only through the body diode of the first MOS transistor.
  • the PRSNT# pin When the PCIE cards are all inserted into the server slots, the PRSNT# pin will be connected to the ground by the short-circuit wire of the PCIE card, and a PRSNT# signal will be generated. At this time, the PCIE card will control the conduction of the second MOS tube, and the PRSNT# signal will flow through the first Two MOS transistors pull down the EV_PRSNT signal to ground, so that the voltage signal received by the controller is no longer the EV_PRSNT signal in the high level state, but the PRSNT# signal in the low level state, and the controller will turn on the first A MOS tube, since the first MOS tube is enabled to start working, the second power supply can charge the load normally through the first MOS tube.
  • the controller When the PCIE card is not fully pulled out, because the PRSNT# pin is short, it will be disconnected from the short-circuit line first, so the second MOS tube will be turned off. At this time, the controller still receives the high level signal According to the EV_PRSNT signal, the controller will turn off the first MOS tube to disconnect the load and the power supply.
  • This embodiment proposes a method for protecting the PCIE card power supply, which is applied to the circuit for protecting the PCIE card power supply mentioned in the above-mentioned embodiments.
  • the method controls the first power supply and the second The power supply releases the electric energy, and then controls the controller to turn off the first MOS tube according to the EV_PRSNT signal generated by the first power supply during the release of electric energy, and then charges the load with the electric energy released by the second power supply;
  • all the PCIE cards are inserted into the server slot , generate the PRSNT# signal according to the grounded PRSNT# pin, and then control the second MOS transistor to conduct, and control the controller to conduct the first MOS transistor according to the PRSNT# signal flowing through the second MOS transistor; if the PCIE card is not completely pulled out , the second MOS transistor is controlled to be turned off, and the controller is controlled to turn off the first MOS transistor according to the EV_PRSNT signal.
  • the second power supply charges the load through the body diode of the first MOS tube, and reduces the surge current when the PCIE card is inserted through pre-charging.
  • the load is disconnected from the second power supply by turning off the first MOS tube, and the surge current generated when the PCIE card is pulled out with power is suppressed, thereby realizing hot-swapping protection.
  • this embodiment provides a supplementary description of the steps of controlling the turn-on and turn-off of the second MOS transistor, and the steps include:
  • the on and off of the second MOS transistor is controlled according to the PRSNT# signal, the voltage of the first power supply, the voltage across the first resistor and the voltage across the second resistor; wherein, the resistance of the first resistor is smaller than that of the second resistor.
  • the gate voltage of the second MOS transistor is the voltage difference between the voltage of the first power supply and the voltage across the second resistor
  • the source voltage of the second MOS transistor is the voltage difference between the voltage of the first power supply and the voltage across the first resistor. Voltage difference.
  • the conduction condition of the transistor when all the PCIE cards are inserted into the server slot, affected by the pull-down effect of the PRSNT# signal, the source voltage of the second MOS transistor will decrease at this time, and when the source voltage of the second MOS transistor decreases
  • the second MOS transistor is turned on; correspondingly, when the PCIE card is pulled out, the source voltage of the second MOS transistor will be increases, and when the increase does not meet its conduction condition, the second MOS tube is turned off.
  • this embodiment describes the steps of controlling the turn-on and turn-off of the second MOS transistor in detail, so that the controller can control the first MOS transistor according to different voltage signals received in the turn-on and turn-off states of the second MOS transistor. Tube on and off.
  • the electric energy released by the second power supply will provide a voltage input for the current pump in the controller, so as to supply the first MOS tube when all the PCIE cards are inserted into the server slots. of the grid charge.
  • the first voltage comparator in the controller will collect the electric energy released by the second power supply, and output the first voltage signal to the third MOS transistor according to the voltage difference between the drain voltage and the source voltage of the first MOS transistor.
  • the output first voltage signal is at a high level, and the third MOS transistor is turned on, so that the gate voltage of the first MOS transistor is equal to the source voltage, Turning off the first MOS tube effectively prevents damage to the power supply caused by a surge current generated when the second power supply just releases electric energy.
  • the step of charging the load by the electric energy released by the second power supply includes: controlling the electric energy released by the second power supply The load is charged through the body diode of the first MOS transistor.
  • the electric energy released by the second power supply can only charge the load through the body diode of the first MOS transistor, that is, at this time the second The electric energy released by the power supply is limited to charge the load in the low current mode, that is, pre-charge is performed when the PCIE card is not fully inserted into the server slot, and the surge current when the PCIE card is inserted is reduced by pre-charging, which effectively protects the The power supply of the PCIE card.
  • the method for protecting the power supply of the PCIE card is described in detail, and the present application also provides embodiments corresponding to the device for protecting the power supply of the PCIE card. It should be noted that this application describes the embodiments of the device part from two perspectives, one is based on the perspective of functional modules, and the other is based on the perspective of hardware.
  • FIG. 3 is a structural diagram of a device for protecting a power supply of a PCIE card provided by the present application. As shown in Figure 3, the device is applied to the circuit for protecting the PCIE card power supply in the foregoing embodiments, including:
  • the first control module 10 is used to control the first power supply and the second power supply to release electric energy when the PCIE card is not fully inserted into the server slot;
  • the second control module 11 is used to control the controller to turn off the first MOS transistor according to the EV_PRSNT signal generated by the first power supply during the release of electric energy;
  • the charging module 12 is used to charge the load with the electric energy released by the second power supply;
  • the third control module 14 is used to control the turn-on and turn-off of the second MOS transistor
  • the fourth control module 15 is configured to control the controller to turn on the first MOS transistor according to the PRSNT# signal flowing through the second MOS transistor.
  • the device for protecting the power supply of the PCIE card when the PCIE card is not fully inserted in the server slot, controls the first power supply and the second power supply to release electric energy through the first control module; then, according to the first power supply when releasing electric energy
  • the EV_PRSNT signal generated in the second control module controls the controller to turn off the first MOS tube; then the charging module charges the load through the electric energy released by the second power supply; when all the PCIE cards are inserted into the server slot, according to the grounded PRSNT
  • the # pin generates the PRSNT# signal through the generation module; the third control module controls the turn-on and turn-off of the second MOS tube; and then controls the controller to turn on through the fourth control module according to the PRSNT# signal flowing through the second MOS tube The first MOS tube.
  • the charging module charges the load with the electric energy released by the second power supply. Since the first MOS tube is turned off, the electric energy released by the second power supply can only be low-pass at this time.
  • the current mode charges the load through the body diode of the first MOS tube, and effectively reduces the surge current when the PCIE card is inserted through the pre-charging method; when the PCIE card is not completely pulled out, the load and the The second power supply is disconnected, which suppresses the surge current generated when the PCIE card is pulled out with power on, and realizes hot-swapping protection.
  • Fig. 4 is a structural diagram of a device for protecting a PCIE card power supply provided in another embodiment of the present application, which is applied to the circuit for protecting a PCIE card power supply in the above-mentioned embodiment, as shown in Fig. 4 , the protection for a PCIE card power supply Devices include:
  • memory 20 for storing computer programs
  • the processor 21 is configured to implement the steps of the method for protecting the power supply of the PCIE card mentioned in the above-mentioned embodiments when executing the computer program.
  • the device for protecting the power supply of the PCIE card provided in this embodiment may include, but is not limited to, a smart phone, a tablet computer, a notebook computer or a desktop computer, and the like.
  • the processor 21 may include one or more processing cores, such as a 4-core processor, an 8-core processor, and the like.
  • the processor 21 can adopt at least one hardware form in a digital signal processor (Digital Signal Processor, DSP), a field programmable gate array (Field-Programmable Gate Array, FPGA), and a programmable logic array (Programmable Logic Array, PLA). to fulfill.
  • DSP Digital Signal Processor
  • FPGA Field-Programmable Gate Array
  • PLA programmable logic array
  • Processor 21 may also include a main processor and a coprocessor, and the main processor is a processor for processing data in a wake-up state, also known as a central processing unit (Central Processing Unit, CPU); the coprocessor is Low-power processor for processing data in standby state.
  • CPU Central Processing Unit
  • the processor 21 may be integrated with a graphics processor (Graphics Processing Unit, GPU), and the GPU is used for rendering and drawing the content that needs to be displayed on the display screen.
  • the processor 21 may also include an artificial intelligence (Artificial Intelligence, AI) processor, and the AI processor is used to process computing operations related to machine learning.
  • AI Artificial Intelligence
  • Memory 20 may include one or more computer-readable storage media, which may be non-transitory.
  • the memory 20 may also include high-speed random access memory, and non-volatile memory, such as one or more magnetic disk storage devices, flash memory storage devices.
  • the memory 20 is at least used to store the following computer program 201, wherein, after the computer program is loaded and executed by the processor 21, the relevant steps of the method for protecting the PCIE card power disclosed in any of the foregoing embodiments can be implemented.
  • the resources stored in the memory 20 may also include the operating system 202, etc., and the storage method may be temporary storage or permanent storage.
  • the operating system 202 may include Windows, Unix, Linux and so on.
  • the device for protecting the power supply of the PCIE card may further include a display screen 22 , an input/output interface 23 , a communication interface 24 , a power supply 25 and a communication bus 26 .
  • FIG. 4 does not constitute a limitation to the device for protecting the power supply of the PCIE card, and may include more or less components than shown in the figure.
  • the device for protecting the power supply of the PCIE card provided by the embodiment of the present application includes a memory and a processor.
  • the processor executes the program stored in the memory, it can implement the above method for protecting the power supply of the PCIE card, and the effect is the same as above.
  • the present application also provides an embodiment corresponding to a computer-readable storage medium.
  • a computer program is stored on the computer-readable storage medium, and when the computer program is executed by the processor, the steps of the method for protecting the power supply of the PCIE card as described in the above method embodiments are implemented.
  • the methods in the above embodiments are implemented in the form of software function units and sold or used as independent products, they can be stored in a computer-readable storage medium.
  • the technical solution of the present application is essentially or the part that contributes to the prior art or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium , executing all or part of the steps of the methods described in the various embodiments of the present application.
  • the aforementioned storage media include: U disk, mobile hard disk, read-only memory (Read-Only Memory, ROM), random access memory (Random Access Memory, RAM), magnetic disk or optical disc and other media that can store program codes. .
  • the computer-readable storage medium provided by the present application includes the above-mentioned method for protecting the power supply of the PCIE card, and the effect is the same as above.

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Abstract

本申请公开了一种保护PCIE卡电源的方法、电路、装置及介质，主要涉及板卡硬件设计领域。该方法在PCIE卡未全部插入服务器插槽中时，控制第一电源和第二电源释放电能，根据第一电源在释放电能中产生的EV_PRSNT信号控制控制器关断第一MOS管，通过第二电源释放的电能为负载充电；在全部插入时，根据接地的PRSNT#引脚产生PRSNT#信号，控制第二MOS管导通，根据PRSNT#信号控制控制器导通第一MOS管；在未全部拔出时，控制第二MOS管关断，根据EV_PRSNT信号控制控制器关断第一MOS管。相较于传统的通过热插拔芯片保护PCIE卡电源的方法，该方法不需要使用热插拔芯片，降低了PCIE卡的成本。

Description

一种保护PCIE卡电源的方法、电路、装置及介质
相关申请的交叉引用
本申请要求于2022年1月13日提交中国专利局，申请号为202210034523.2，申请名称为“一种保护PCIE卡电源的方法、电路、装置及介质”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及板卡硬件设计领域，特别是涉及一种保护PCIE卡电源的方法、电路、装置及介质。
背景技术
近年来一种高速串行计算机扩展总线标准(Peripheral Component Interconnect Express，PCIE)卡运用越来越广，其以PCIE接口的形式插入服务器主板，从而达到特定功能的应用成为了趋势，优势在于可通过PCIE金手指，直接插入台式机或服务器的PCIE插槽中调试使用，简易灵活，开发成本低。在设计PCIE卡时，其自身需要有一定的电源保护电路，来防止带电插拔对自身和服务器产生不可逆的影响。
当前通过在PCIE卡上安装热插拔芯片，由热插拔芯片控制PCIE卡带电拔插时产生的瞬间电流实现带电插拔时的电源保护。但是，在PCIE卡上安装热插拔芯片会增加PCIE卡的设计成本。
由此可见，如何降低PCIE卡的成本是本领域技术人员亟待解决的问题。
发明内容
根据第一方面，本申请提供一种保护PCIE卡电源的电路，包括：第一MOS管、第二MOS管、控制器、第一电阻和第二电阻；
第一电阻的第一端与第一电源连接，第一电阻的第二端与第二MOS管的源极连接；
第二电阻的第一端与第一电源连接，第二电阻的第二端与第二MOS管的栅极连接；
第二MOS管的漏极与PRSNT#引脚连接，第二MOS管的源极与控制器连接，用于响应于PCIE卡全部插入服务器插槽中，将PRSNT#引脚接地产生的PRSNT#信号传输至控制器；
控制器的第一端与第一电阻和第二MOS管的公共端连接，控制器的第二端与第一MOS管连接，用于响应于PCIE卡未全部插入服务器插槽中，根据第一电源在释放电能中产生的EV_PRSNT信号关断第一MOS管，以及响应于PCIE卡全部插入服务器插槽中，根据PRSNT#信号导通第一MOS管；
第一MOS管的源极与第二电源连接，用于传输第二电源释放的电能。
在一些实施方式中，控制器包括电流泵、第一电压比较器、第二电压比较器和第三MOS管；
电流泵与第一MOS管的栅极连接，用于响应于PCIE卡全部插入服务器插槽中，为第一MOS管的栅极充电；
第一电压比较器的同相输入端与第一MOS管的漏极连接，第一电压比较器的反相输入端与第一MOS管的源极连接，第一电压比较器的输出端与第三MOS管的栅极连接，用于根据第一MOS管的漏极电压和源极电压的电压差向第三MOS管输出第一电压信号；
第二电压比较器的同相输入端与第一电阻和第二MOS管的公共端连接，第二电压比较器的反相输入端接地，第二电压比较器的输出端与第三MOS管的栅极连接，用于根据EV_PRSNT信号向第三MOS管输出第二电压信号，以及根据PRSNT#信号向第三MOS管输出第三电压信号；
第三MOS管的漏极与第一MOS管连接，第三MOS管的源极与第二电源连接。
根据第二方面，本申请还提供一种保护PCIE卡电源的方法，应用于保护PCIE卡电源的电路，该方法包括：
响应于PCIE卡未全部插入服务器插槽中，控制第一电源和第二电源释放电能；
根据第一电源在释放电能中产生的EV_PRSNT信号控制控制器关断第一MOS管；
通过第二电源释放的电能为负载充电；
响应于PCIE卡全部插入服务器插槽中，根据接地的PRSNT#引脚产生PRSNT#信号；
控制第二MOS管导通，根据流过第二MOS管的PRSNT#信号控制控制器导通第一MOS管；
响应于未全部拔出PCIE卡，控制第二MOS管关断；并且
根据EV_PRSNT信号控制控制器关断第一MOS管。
在一些实施方式中，控制第二MOS管的导通与关断包括：
根据PRSNT#信号、第一电源的电压、第一电阻两端电压和第二电阻两端电压控制第二MOS管的导通与关断；其中，第一电阻的阻值小于第二电阻。
在一些实施方式中，响应于PCIE卡未全部插入服务器插槽中，则在控制控制器关断第一MOS管之前，还包括：
通过第二电源释放的电能为控制器充电。
在一些实施方式中，通过第二电源释放的电能为负载充电包括：
控制第二电源释放的电能通过第一MOS管的体二极管为负载充电。
根据第三方面，本申请还提供一种保护PCIE卡电源的装置，应用于保护PCIE卡电源的电路，包括：
第一控制模块，用于响应于PCIE卡未全部插入服务器插槽中，控制第一电源和第二电源释放电能；
第二控制模块，用于根据第一电源在释放电能中产生的EV_PRSNT信号控制控制器关断第一MOS管；
充电模块，用于通过第二电源释放的电能为负载充电；
产生模块，用于响应于PCIE卡全部插入服务器插槽中，根据接地的PRSNT#引脚产生PRSNT#信号；
第三控制模块，用于控制第二MOS管的导通与关断；
第四控制模块，用于根据流过第二MOS管的PRSNT#信号控制控制器导通第一MOS管。
根据第四方面，本申请还提供一种保护PCIE卡电源的装置，应用于保护PCIE卡电源的电路，包括：
存储器，用于存储计算机程序；
处理器，用于执行计算机程序时实现上述保护PCIE卡电源的方法的步骤。
根据第五方面，本申请还提供一种计算机可读存储介质，该计算机可读存储介质上存储有计算机程序，计算机程序被处理器执行时实现上述保护PCIE卡电源的方法的步骤。
本申请的一个或多个实施例的细节在下面的附图和描述中提出。本申请的其它特征和优点将从说明书、附图以及权利要求书变得明显。
附图说明
为了更清楚地说明本申请实施例，下面将对实施例中所需要使用的附图做简单的介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本申请提供的一种保护PCIE卡电源的电路的结构图；
图2为本申请提供的一种保护PCIE卡电源的方法的流程图；
图3为本申请提供的一种保护PCIE卡电源的装置的结构图；
图4为本申请提供的另一种保护PCIE卡电源的装置的结构图。
具体实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部实施例。基于本申请中的实施例，本领域普通技术人员在没有做出创造性劳动前提下，所获得的所有其他实施例，都属于本申请保护范围。
本申请的核心是提供一种保护PCIE卡电源的方法，用于在PCIE卡带电插拔时抑制浪涌电流，保护PCIE卡，能够降低PCIE卡的成本。
为了使本技术领域的人员更好地理解本申请方案，下面结合附图和具体实施方式对本申请作进一步的详细说明。
图1为本申请提供的一种保护PCIE卡电源的电路的结构图，下面对图1所示的保护PCIE卡电源的电路进行说明。
保护PCIE卡电源的电路，包括第一MOS管Q1、第二MOS管Q2、控制器1、第一电阻R1和第二电阻R2；第一电阻R1的第一端与第一电源连接，第一电阻R1的第二端与第二MOS管Q2的源极连接；第二电阻R2的第一端与第一电源连接，第二电阻R2的第二端与第二MOS管Q2的栅极连接；第二MOS管Q2的漏极与PRSNT#引脚连接，第二MOS管Q2的源极与控制器1连接，用于在PCIE卡全部插入服务器插槽中时，将PRSNT#引脚接地产生的PRSNT#信号传输至控制器1；控制器1的第一端与第一电阻R1和第二MOS管Q2的公共端连接，控制器1的第二端与第一MOS管Q1连接，用于在PCIE卡未全部插入服务器插槽中时，根据第一电源在释放电能中产生的EV_PRSNT信号关断第一MOS管Q1，以及在PCIE卡全部插入服务器插槽中时，根据PRSNT#信号导通第一MOS管Q1；第一MOS管Q1的源极与第二电源连接，用于传输第二电源释放的电 能。
如图1所示，相较于PCIE卡上的电源引脚，PRSNT#引脚的长度较短。在本实施例中，当PCIE卡插入到服务器插槽中且PRSNT#引脚未插入到服务器插槽中的预设位置时，认为PCIE卡未全部插入到服务器插槽中，第一电源和第二电源均会释放电能，PRSNT#引脚产生的PRSNT#信号会在第一电阻R1的上拉作用下一直处于高电平状态，对应地，第一电源在释放电能中产生的EV_PRSNT信号也处于高电平状态。由于控制器1在接收到高电平时关断第一MOS管Q1、接收到低电平时开启第一MOS管Q1，因此，控制器1会根据接收到的EV_PRSNT信号使得第一MOS管Q1保持关断，此时金手指上的第二电源会通过第一MOS管Q1的体二极管对负载进行充电。当PRSNT#引脚插入到服务器插槽中的预设位置时，认为PCIE卡全部插入到服务器插槽，PRSNT#引脚会被PCIE卡的短路线连接到地，此时PRSNT#引脚产生的PRSNT#信号为低电平，第二MOS管Q2的源极电压为第二MOS管Q2的体二极管的导通电压，而其栅极电压在第二电阻R2的上拉作用下仍为高电平，因此，第二MOS管Q2的栅极电压会大于其源极电压；当第二MOS管Q2的栅极电压与源极电压之间的电压差大于其自身的开启电压时，第二MOS管Q2导通，处于高电平状态的EV_PRSNT信号会被流过第二MOS管Q2的PRSNT#信号下拉接地，也就是说，此时控制器1接收的电压信号为处于低电平状态的PRSNT#信号。由于PRSNT#信号为低电平，控制器1根据该PRSNT#信号会导通第一MOS管Q1，此时第二电源能够直接为负载充电。由于在PCIE卡未全部插入服务器插槽时，第二电源已经通过第一MOS管Q1的体二极管对负载进行预充电，因此，在第一MOS管Q1导通时能够有效降低插入PCIE卡时的浪涌电流。需要说明的是，本实施例中的预设位置可以为PRSNT#引脚全部插入服务器插槽时的引脚顶端位置，也可以为PRSNT#引脚全部插入服务器插槽时的引脚顶端位置的三分之二处，根据实际情况设置，本实施例对此不做限制。
此外，为保证能够准确感知PCIE卡的插入情况，本实施例中设置PRSNT#引脚为两个，分别位于PCIE金手指的两端，且两个PRSNT#引脚连接在一起，其公共端与第二MOS管Q2的漏极连接。当PCIE卡全部插入服务器插槽中时，至少存在一个PRSNT#引脚会到达服务器插槽中的预设位置，进而会被PCIE卡的短路线连接到地，使得其产生的PRSNT#信号变为低电平。显然，PRSNT#引脚的数量不限于两个，PRSNT#引脚的位置也不限于PCIE金手指的两端，可根据实际情况设置，本实施例对PRSNT#引脚的数量和位置不做限制。
当PCIE卡的金手指被带电拔出时，由于PRSNT#引脚较短，所以会最先离开服务器 插槽。当PRSNT#引脚离开服务器插槽的预设位置时，PRSNT#信号在第一电阻R1的上拉作用下重新回到高电平，此时的第二MOS管Q2不满足栅极电压与源极电压的电压差大于其开启电压，第二MOS管Q2关断，EV_PRSNT信号也在第一电阻R1的上拉作用下回到高电平，控制器1根据该EV_PRSNT信号会关断第一MOS管Q1，以实现第一MOS管Q1的体二极管的方向关断，能够有效抑制带电拔出PCIE卡时产生的浪涌电流。需要说明的是，高电平和低电平是相对的，本申请中的高电平为相对于低电平时的高电压状态，例如，本实施例中的EV_PRSNT信号为高电平是指相对于PRSNT#引脚接地产生的PRSNT#信号的低电平状态，EV_PRSNT信号的电压更高。
本实施例对保护PCIE卡电源的电路进行了说明，该电路包括第一MOS管、第二MOS管、控制器、第一电阻和第二电阻；第一电阻的第一端与第一电源连接，第二端与第二MOS管的源极连接；第二电阻的第一端与第一电源连接，第二端与第二MOS管的栅极连接；第二MOS管的漏极与PRSNT#引脚连接，源极与控制器连接，用于在PCIE卡全部插入服务器插槽中时，将PRSNT#引脚接地产生的PRSNT#信号传输至控制器；控制器的第一端与第一电阻和第二MOS管的公共端连接，第二端与第一MOS管连接，用于在PCIE卡未全部插入服务器插槽中时，根据第一电源在释放电能中产生的EV_PRSNT信号关断第一MOS管，以及在PCIE卡全部插入服务器插槽中时，根据PRSNT#信号导通第一MOS管；第一MOS管的源极与第二电源连接，用于传输第二电源释放的电能。由于在PCIE卡未全部插入服务器插槽时，关断了第一MOS管，使得第二电源通过第一MOS管的体二极管对负载进行了预充电，因此能够有效降低在PCIE卡全部插入服务器插槽，也就是第一MOS管导通时产生的浪涌电流；在未全部拔出PCIE卡时，通过关断第一MOS管将负载与第二电源断开，实现抑制带电拔出PCIE卡时产生的浪涌电流，有效保护了PCIE卡的电源。
由于在上述实施例中未对控制器1的结构进行说明，本实施例对此作补充说明。
控制器1包括电流泵、第一电压比较器、第二电压比较器和第三MOS管；电流泵与第一MOS管Q1的栅极连接，用于在PCIE卡全部插入服务器插槽中时，为第一MOS管Q1的栅极充电；第一电压比较器的同相输入端与第一MOS管Q1的漏极连接，第一电压比较器的反相输入端与第一MOS管Q1的源极连接，第一电压比较器的输出端与第三MOS管的栅极连接，用于根据第一MOS管Q1的漏极电压和源极电压的电压差向第三MOS管输出第一电压信号；第二电压比较器的同相输入端与第一电阻R1和第二MOS管Q2的公共端连接，第二电压比较器的反相输入端接地，第二电压比较器的输出端与第三MOS管的栅极连接，用于根据EV_PRSNT信号向第三MOS管输出第二电压信号，以及 根据PRSNT#信号向第三MOS管输出第三电压信号；第三MOS管的漏极与第一MOS管Q1连接，第三MOS管的源极与第二电源连接。
在PCIE卡刚插入服务器插槽中时，第一MOS管Q1关断，第二电源释放的电能通过第一MOS管Q1的体二极管为负载充电。随着PCIE卡的进一步插入，当PCIE卡全部插入服务器插槽中时，此时控制器1接收的为处于低电平状态的PRSNT#信号。控制器1接收到PRSNT#信号后，电流泵会为第一MOS管Q1的栅极充电，直至第一MOS管Q1的栅极电压大于其源极电压，第一MOS管Q1导通，此时第二电源可通过第一MOS管Q1为负载充电。此外，为防止第一MOS管Q1导通时产生浪涌电流，第一电压比较器会采集第一MOS管Q1的漏极电压和源极电压，根据第一MOS管Q1的漏极电压和源极电压的电压差向第三MOS管输出第一电压信号，若第一MOS管Q1的漏极电压和源极电压的电压差超过了阈值电压，则认为产生了浪涌电流，此时第一电压比较器向第三MOS管的栅极输出的第一电压信号为高电平，第三MOS管导通，使得第一MOS管Q1的栅极与源极相连，即第一MOS管Q1的栅极电压与源极电压相等，因此，第一MOS管Q1关断，实现了将第二电源与负载断开，能够有效抑制产生的浪涌电流；若第一MOS管Q1的漏极电压和源极电压的电压差未超过阈值电压，则其向第三MOS管的栅极输出的第一电压信号为低电平，此时认为未产生浪涌电流，无法根据该第一电压信号打开第三MOS管。需要说明的是，本实施例中设置的是一个30mV的反向电压保护点，也就是说，阈值电压取为30mV，当第一电压比较器采集到的第一MOS管Q1的漏极电压和源极电压的电压差大于30mV时，第一电压比较器向第三MOS管的栅极输出的第一电压信号为高电平。显然，阈值电压不限于30mV，根据实际情况可以取合适的阈值电压，本实施例对此不做限制。
另外，当PCIE卡未全部插入服务器插槽中时，第二电压比较器的同相输入端会接收第一电源释放电能产生的EV_PRSNT信号，由于EV_PRSNT信号为高电平，因此向第三MOS管的栅极输出的第二电压信号为高电平，此时第三MOS管导通，第一MOS管Q1的栅极与源极相连，不满足第一MOS管Q1的导通条件，实现了在PCIE卡未全部插入服务器插槽中时关断第一MOS管Q1。当PCIE卡全部插入服务器插槽中时，第二电压比较器的同相输入端接收的PRSNT#信号为低电平，因此向第三MOS管的栅极输出的第三电压信号为低电平，此时第三MOS管的栅极电压不大于其源极电压，不满足第三MOS管的导通条件，第三MOS管关断；由于控制器1在接收到PRSNT#信号后，电流泵会为第一MOS管Q1的栅极充电，因此当第一MOS管Q1的栅极电压大于其源极电压时，第一MOS管Q1导通，实现了在PCIE卡全部插入服务器插槽中时导通第一MOS管Q1。 需要说明的是，第一电压比较器的输出端和第二电压比较器的输出端通过非门电路与第三MOS管的栅极连接，也就是说，只要第一电压比较器和第二电压比较器中存在一个输出端输出的是高电平，第三MOS管的栅极接收到的电压信号就为高电平，此时第三MOS管会导通，第一MOS管Q1会关断。
本实施例对控制器的结构进行了详细说明，控制器包括电流泵、第一电压比较器、第二电压比较器和第三MOS管；电流泵与第一MOS管的栅极连接，用于在PCIE卡全部插入服务器插槽中时，为第一MOS管的栅极充电；第一电压比较器的同相输入端与第一MOS管的漏极连接，第一电压比较器的反相输入端与第一MOS管的源极连接，第一电压比较器的输出端与第三MOS管的栅极连接，用于根据第一MOS管的漏极电压和源极电压的电压差向第三MOS管输出第一电压信号；第二电压比较器的同相输入端与第一电阻和第二MOS管的公共端连接，第二电压比较器的反相输入端接地，第二电压比较器的输出端与第三MOS管的栅极连接，用于根据EV_PRSNT信号向第三MOS管输出第二电压信号，以及根据PRSNT#信号向第三MOS管输出第三电压信号；第三MOS管的漏极与第一MOS管连接，第三MOS管的源极与第二电源连接。本实施例中，第二电压比较器根据EV_PRSNT信号和PRSNT#信号向第三MOS管输出对应的电压信号，通过导通第三MOS管实现关断第一MOS管，通过关断第三MOS关实现导通第一MOS管，以实现控制第一MOS管的导通与关断。此外，第一电压比较器监测第一MOS管漏极电压和源极电压，在第一MOS管的漏极电压和源极电压的电压差大于阈值电压时，会向第三MOS管输出为高电平的第一电压信号，以关断第一MOS管，有效抑制了浪涌电流，保护了PCIE卡电源。
图2为本申请提供的一种保护PCIE卡电源的方法的流程图，该方法应用于上述实施例中的保护PCIE卡电源的电路。如图2所示，该方法包括：
S1：在PCIE卡未全部插入服务器插槽中时，控制第一电源和第二电源释放电能；
S2：根据第一电源在释放电能中产生的EV_PRSNT信号控制控制器关断第一MOS管；
S3：通过第二电源释放的电能为负载充电；
S4：在PCIE卡全部插入服务器插槽中时，根据接地的PRSNT#引脚产生PRSNT#信号；
S5：控制第二MOS管导通，根据流过第二MOS管的PRSNT#信号控制控制器导通第一MOS管；
S6：在未全部拔出PCIE卡时，控制第二MOS管关断；
S7：根据EV_PRSNT信号控制控制器关断第一MOS管。
在本实施例中，当PCIE卡未全部插入服务器插槽中时，PCIE卡先控制第一电源和第二电源放电，此时控制器会接收到第一电源释放电能时产生的EV_PRSNT信号，由于EV_PRSNT信号在上拉电阻的作用下为高电平，而在上述实施例中提到控制器接收到高电平的电压信号时会关断外部MOS管，因此，PCIE卡会通过控制器关断第一MOS管，使得第二电源释放的电能只能通过第一MOS管的体二极管为负载充电。当PCIE卡全部插入服务器插槽中时，PRSNT#引脚会被PCIE卡的短路线连接到地，产生PRSNT#信号，此时PCIE卡会控制第二MOS管导通，PRSNT#信号流过第二MOS管将EV_PRSNT信号下拉接地，使得控制器接收的电压信号不再为处于高电平状态的EV_PRSNT信号，而是处于低电平状态的PRSNT#信号，控制器根据PRSNT#信号会导通第一MOS管，由于第一MOS管被使能开始工作，因此，第二电源能够通过第一MOS管为负载正常充电。在未全部拔出PCIE卡时，由于PRSNT#引脚较短，会与短路线先断开，因此第二MOS管会被关断，此时控制器接收到的仍为处于高电平状态的EV_PRSNT信号，根据EV_PRSNT信号控制器会关断第一MOS管，以断开负载和电源。
本实施例提出一种保护PCIE卡电源的方法，应用于上述实施例中提到的保护PCIE卡电源的电路，该方法在PCIE卡未全部插入服务器插槽中时，控制第一电源和第二电源释放电能，然后，根据第一电源在释放电能中产生的EV_PRSNT信号控制控制器关断第一MOS管，再通过第二电源释放的电能为负载充电；在PCIE卡全部插入服务器插槽中时，根据接地的PRSNT#引脚产生PRSNT#信号，再控制第二MOS管导通，根据流过第二MOS管的PRSNT#信号控制控制器导通第一MOS管；在未全部拔出PCIE卡时，控制第二MOS管关断，根据EV_PRSNT信号控制控制器关断第一MOS管。该方法在PCIE卡未全部插入服务器插槽中时，第二电源通过第一MOS管的体二极管为负载充电，通过预充电的方式降低插入PCIE卡时的浪涌电流，在未全部拔出PCIE卡时，通过关断第一MOS管将负载与第二电源断开，抑制带电拔出PCIE卡时产生的浪涌电流，实现了热插拔保护。
在上述实施例的基础上，本实施例对控制第二MOS管的导通与关断的步骤进行补充说明，该步骤包括：
根据PRSNT#信号、第一电源的电压、第一电阻两端电压和第二电阻两端电压控制第二MOS管的导通与关断；其中，第一电阻的阻值小于第二电阻。
具体地，第二MOS管的栅极电压为第一电源的电压与第二电阻两端电压的电压差，第二MOS管的源极电压为第一电源的电压与第一电阻两端电压的电压差。当PCIE卡未 全部插入服务器插槽中时，由于第一电阻的阻值小于第二电阻的阻值，因此，此时第二MOS管的源极电压大于其栅极电压，不满足第二MOS管的导通条件；当PCIE卡全部插入服务器插槽中时，受PRSNT#信号下拉作用的影响，此时第二MOS管的源极电压会减小，当第二MOS管的源极电压减小至其栅极电压与源极电压的电压差大于第二MOS管自身的开启电压时，第二MOS管导通；对应地，在拔出PCIE卡时，第二MOS管的源极电压会增大，当增大至不满足其导通条件时，第二MOS管被关断。
由于在第二MOS管关断时，控制器接收的电压信号为处于高电平状态的EV_PRSNT信号，在第二MOS管导通时，控制器接收的电压信号为处于低电平状态的PRSNT#信号，因此本实施例对控制第二MOS管的导通与关断的步骤进行详细说明，以便于控制器根据在第二MOS管导通与关断状态下接收的不同电压信号控制第一MOS管的导通与关断。
在上述实施例的基础上，若PCIE卡未全部插入服务器插槽中，则在控制控制器关断第一MOS管之前，还包括：通过第二电源释放的电能为控制器充电。
具体地，当PCIE卡未全部插入服务器插槽中时，第二电源释放的电能会为控制器中的电流泵提供电压输入，以便于在PCIE卡全部插入服务器插槽中时为第一MOS管的栅极充电。此外，控制器中的第一电压比较器会采集第二电源释放的电能，根据第一MOS管漏极电压和源极电压的电压差向第三MOS管输出第一电压信号，在第一MOS管漏极电压和源极电压的电压差超过阈值电压时，输出的第一电压信号为高电平，第三MOS管会导通，使得第一MOS管的栅极电压与源极电压相等，关断第一MOS管，有效防止了在第二电源刚释放电能时就产生浪涌电流对电源造成损伤。
在上述实施例的基础上，当PCIE卡未全部插入服务器插槽中时，第二电源会释放电能，此时通过第二电源释放的电能为负载充电的步骤包括：控制第二电源释放的电能通过第一MOS管的体二极管为负载充电。
在PCIE卡未全部插入服务器插槽中时，由于第一MOS管被关断，因此第二电源释放的电能只能通过第一MOS管的体二极管为负载充电，也就是说，此时第二电源释放的电能被限制在低通流模式为负载进行充电，即在PCIE卡未全部插入服务器插槽中时进行预充电，通过预充电的方式降低插入PCIE卡时的浪涌电流，有效保护了PCIE卡的电源。
在上述实施例中，对于保护PCIE卡电源的方法进行了详细描述，本申请还提供保护PCIE卡电源的装置对应的实施例。需要说明的是，本申请从两个角度对装置部分的实施例进行描述，一种是基于功能模块的角度，另一种是基于硬件的角度。
图3为本申请提供的一种保护PCIE卡电源的装置的结构图。如图3所示，该装置应用于上述实施例中的保护PCIE卡电源的电路，包括：
第一控制模块10，用于在PCIE卡未全部插入服务器插槽中时，控制第一电源和第二电源释放电能；
第二控制模块11，用于根据第一电源在释放电能中产生的EV_PRSNT信号控制控制器关断第一MOS管；
充电模块12，用于通过第二电源释放的电能为负载充电；
产生模块13，用于在PCIE卡全部插入服务器插槽中时，根据接地的PRSNT#引脚产生PRSNT#信号；
第三控制模块14，用于控制第二MOS管的导通与关断；
第四控制模块15，用于根据流过第二MOS管的PRSNT#信号控制控制器导通第一MOS管。
由于装置部分的实施例与方法部分的实施例相互对应，因此装置部分的实施例请参见方法部分的实施例的描述，这里暂不赘述。
本实施例所提供的保护PCIE卡电源的装置，在PCIE卡未全部插入服务器插槽中时，通过第一控制模块控制第一电源和第二电源释放电能；然后，根据第一电源在释放电能中产生的EV_PRSNT信号通过第二控制模块控制控制器关断第一MOS管；再由充电模块通过第二电源释放的电能为负载充电；在PCIE卡全部插入服务器插槽中时，根据接地的PRSNT#引脚通过产生模块产生PRSNT#信号；通过第三控制模块控制第二MOS管的导通与关断；再根据流过第二MOS管的PRSNT#信号通过第四控制模块控制控制器导通第一MOS管。该装置在PCIE卡未全部插入服务器插槽中时，由充电模块通过第二电源释放的电能为负载充电，由于第一MOS管被关断，此时第二电源释放的电能只能以低通流模式通过第一MOS管的体二极管为负载充电，通过预充电的方式有效降低了插入PCIE卡时的浪涌电流；在未全部拔出PCIE卡时，通过关断第一MOS管将负载与第二电源断开，抑制带电拔出PCIE卡时产生的浪涌电流，实现了热插拔保护。
图4为本申请另一实施例提供的一种保护PCIE卡电源的装置的结构图，其应用于上述实施例中的保护PCIE卡电源的电路，如图4所示，该保护PCIE卡电源的装置包括：
存储器20，用于存储计算机程序；
处理器21，用于执行计算机程序时实现如上述实施例中所提到的保护PCIE卡电源的方法的步骤。
本实施例提供的保护PCIE卡电源的装置可以包括但不限于智能手机、平板电脑、笔 记本电脑或台式电脑等。
其中，处理器21可以包括一个或多个处理核心，比如4核心处理器、8核心处理器等。处理器21可以采用数字信号处理器(Digital Signal Processor，DSP)、现场可编程门阵列(Field－Programmable Gate Array，FPGA)、可编程逻辑阵列(Programmable Logic Array，PLA)中的至少一种硬件形式来实现。处理器21也可以包括主处理器和协处理器，主处理器是用于对在唤醒状态下的数据进行处理的处理器，也称中央处理器(Central Processing Unit，CPU)；协处理器是用于对在待机状态下的数据进行处理的低功耗处理器。在一些实施例中，处理器21可以在集成有图像处理器(Graphics Processing Unit，GPU)，GPU用于负责显示屏所需要显示的内容的渲染和绘制。一些实施例中，处理器21还可以包括人工智能(Artificial Intelligence，AI)处理器，该AI处理器用于处理有关机器学习的计算操作。
存储器20可以包括一个或多个计算机可读存储介质，该计算机可读存储介质可以是非暂态的。存储器20还可包括高速随机存取存储器，以及非易失性存储器，比如一个或多个磁盘存储设备、闪存存储设备。本实施例中，存储器20至少用于存储以下计算机程序201，其中，该计算机程序被处理器21加载并执行之后，能够实现前述任一实施例公开的保护PCIE卡电源的方法的相关步骤。另外，存储器20所存储的资源还可以包括操作系统202等，存储方式可以是短暂存储或者永久存储。其中，操作系统202可以包括Windows、Unix、Linux等。
在一些实施例中，保护PCIE卡电源的装置还可包括有显示屏22、输入输出接口23、通信接口24、电源25以及通信总线26。
本领域技术人员可以理解，图4中示出的结构并不构成对该保护PCIE卡电源的装置的限定，可以包括比图示更多或更少的组件。
本申请实施例提供的保护PCIE卡电源的装置，包括存储器和处理器，处理器在执行存储器存储的程序时，能够实现上述保护PCIE卡电源的方法，效果同上。
最后，本申请还提供一种计算机可读存储介质对应的实施例。计算机可读存储介质上存储有计算机程序，计算机程序被处理器执行时实现如上述方法实施例中记载的保护PCIE卡电源的方法的步骤。
可以理解的是，如果上述实施例中的方法以软件功能单元的形式实现并作为独立的产品销售或使用时，可以存储在一个计算机可读取存储介质中。基于这样的理解，本申请的技术方案本质上或者说对现有技术做出贡献的部分或者该技术方案的全部或部分可以以软件产品的形式体现出来，该计算机软件产品存储在一个存储介质中，执行本申请 各个实施例所述方法的全部或部分步骤。而前述的存储介质包括：U盘、移动硬盘、只读存储器(Read-Only Memory，ROM)、随机存取存储器(Random Access Memory，RAM)、磁碟或者光盘等各种可以存储程序代码的介质。
本申请提供的计算机可读存储介质包括上述提到的保护PCIE卡电源的方法，效果同上。
以上对本申请所提供的保护PCIE卡电源的方法、电路、装置及介质进行了详细介绍。说明书中各个实施例采用递进的方式描述，每个实施例重点说明的都是与其他实施例的不同之处，各个实施例之间相同相似部分互相参见即可。对于实施例公开的装置而言，由于其与实施例公开的方法相对应，所以描述的比较简单，相关之处参见方法部分说明即可。应当指出，对于本技术领域的普通技术人员来说，在不脱离本申请原理的前提下，还可以对本申请进行若干改进和修饰，这些改进和修饰也落入本申请权利要求的保护范围内。
还需要说明的是，在本说明书中，诸如第一和第二等之类的关系术语仅仅用来将一个实体或者操作与另一个实体或操作区分开来，而不一定要求或者暗示这些实体或操作之间存在任何这种实际的关系或者顺序。而且，术语“包括”、“包含”或者其任何其他变体意在涵盖非排他性的包含，从而使得包括一系列要素的过程、方法、物品或者设备不仅包括那些要素，而且还包括没有明确列出的其他要素，或者是还包括为这种过程、方法、物品或者设备所固有的要素。在没有更多限制的情况下，由语句“包括一个……”限定的要素，并不排除在包括所述要素的过程、方法、物品或者设备中还存在另外的相同要素。

Claims (9)

  1. 一种保护PCIE卡电源的电路，其特征在于，包括：第一MOS管、第二MOS管、控制器、第一电阻和第二电阻；
    所述第一电阻的第一端与第一电源连接，所述第一电阻的第二端与所述第二MOS管的源极连接；
    所述第二电阻的第一端与所述第一电源连接，所述第二电阻的第二端与所述第二MOS管的栅极连接；
    所述第二MOS管的漏极与PRSNT#引脚连接，所述第二MOS管的源极与所述控制器连接，用于响应于PCIE卡全部插入服务器插槽中，将所述PRSNT#引脚接地产生的PRSNT#信号传输至所述控制器；
    所述控制器的第一端与所述第一电阻和所述第二MOS管的公共端连接，所述控制器的第二端与所述第一MOS管连接，用于响应于所述PCIE卡未全部插入所述服务器插槽中，根据所述第一电源在释放电能中产生的EV_PRSNT信号关断所述第一MOS管，以及响应于所述PCIE卡全部插入所述服务器插槽中，根据所述PRSNT#信号导通所述第一MOS管；
    所述第一MOS管的源极与第二电源连接，用于传输所述第二电源释放的所述电能。
  2. 根据权利要求1所述的保护PCIE卡电源的电路，其特征在于，所述控制器包括电流泵、第一电压比较器、第二电压比较器和第三MOS管；
    所述电流泵与所述第一MOS管的栅极连接，用于响应于所述PCIE卡全部插入所述服务器插槽中，为所述第一MOS管的栅极充电；
    所述第一电压比较器的同相输入端与所述第一MOS管的漏极连接，所述第一电压比较器的反相输入端与所述第一MOS管的源极连接，所述第一电压比较器的输出端与所述第三MOS管的栅极连接，用于根据所述第一MOS管的漏极电压和源极电压的电压差向所述第三MOS管输出第一电压信号；
    所述第二电压比较器的同相输入端与所述第一电阻和所述第二MOS管的所述公共端连接，所述第二电压比较器的反相输入端接地，所述第二电压比较器的输出端与所述第三MOS管的栅极连接，用于根据所述EV_PRSNT信号向所述第三MOS管输出第二电压信号，以及根据所述PRSNT#信号向所述第三MOS管输出第三电压信号；
    所述第三MOS管的漏极与所述第一MOS管连接，所述第三MOS管的源极与所述第二电源连接。
  3. 一种保护PCIE卡电源的方法，其特征在于，应用于权利要求1-2任一项所述的保护PCIE卡电源的电路，所述方法包括：
    响应于所述PCIE卡未全部插入服务器插槽中，控制第一电源和第二电源释放电能；
    根据所述第一电源在释放所述电能中产生的EV_PRSNT信号控制控制器关断第一MOS管；
    通过所述第二电源释放的所述电能为负载充电；
    响应于所述PCIE卡全部插入所述服务器插槽中，根据接地的PRSNT#引脚产生PRSNT#信号；
    控制第二MOS管导通，根据流过所述第二MOS管的所述PRSNT#信号控制所述控制器导通所述第一MOS管；
    响应于未全部拔出所述PCIE卡，控制所述第二MOS管关断；并且
    根据所述EV_PRSNT信号控制所述控制器关断所述第一MOS管。
  4. 根据权利要求3所述的保护PCIE卡电源的方法，其特征在于，控制所述第二MOS管的导通与关断包括：
    根据所述PRSNT#信号、所述第一电源的电压、第一电阻两端所述电压和第二电阻两端所述电压控制所述第二MOS管的导通与关断；其中，所述第一电阻的阻值小于所述第二电阻。
  5. 根据权利要求3所述的保护PCIE卡电源的方法，其特征在于，响应于所述PCIE卡未全部插入所述服务器插槽中，则在控制所述控制器关断所述第一MOS管之前，还包括：
    通过所述第二电源释放的所述电能为所述控制器充电。
  6. 根据权利要求3所述的保护PCIE卡电源的方法，其特征在于，所述通过所述第二电源释放的所述电能为负载充电包括：
    控制所述第二电源释放的所述电能通过所述第一MOS管的体二极管为所述负载充电。
  7. 一种保护PCIE卡电源的装置，其特征在于，应用于权利要求1-2任一项所述的保护PCIE卡电源的电路，包括：
    第一控制模块，用于响应于PCIE卡未全部插入服务器插槽中响应于，控制第一电源和第二电源释放电能；
    第二控制模块，用于根据所述第一电源在释放所述电能中产生的EV_PRSNT信号控制控制器关断第一MOS管；
    充电模块，用于通过所述第二电源释放的所述电能为负载充电；
    产生模块，用于响应于所述PCIE卡全部插入所述服务器插槽中响应于，根据接地的PRSNT#引脚产生PRSNT#信号；
    第三控制模块，用于控制第二MOS管的导通与关断；
    第四控制模块，用于根据流过所述第二MOS管的所述PRSNT#信号控制所述控制器导通所述第一MOS管。
  8. 一种保护PCIE卡电源的计算机设备，其特征在于，应用于权利要求1-2任一项所述的保护PCIE卡电源的电路，包括：
    存储器，用于存储计算机可读指令；
    处理器，用于执行所述计算机可读指令时实现如权利要求3至6任一项所述的保护PCIE卡电源的方法的步骤。
  9. 一种计算机可读存储介质，其特征在于，所述计算机可读存储介质上存储有计算机可读指令，所述计算机可读指令被处理器执行时实现如权利要求3至6任一项所述的保护PCIE卡电源的方法的步骤。
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