WO2023134024A1 - 半导体结构及其形成方法 - Google Patents

半导体结构及其形成方法 Download PDF

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Publication number
WO2023134024A1
WO2023134024A1 PCT/CN2022/084281 CN2022084281W WO2023134024A1 WO 2023134024 A1 WO2023134024 A1 WO 2023134024A1 CN 2022084281 W CN2022084281 W CN 2022084281W WO 2023134024 A1 WO2023134024 A1 WO 2023134024A1
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type doped
metal layer
doped region
chip
region
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PCT/CN2022/084281
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English (en)
French (fr)
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章恒嘉
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长鑫存储技术有限公司
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Publication of WO2023134024A1 publication Critical patent/WO2023134024A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/38—Cooling arrangements using the Peltier effect

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  • the present disclosure relates to the field of semiconductors, in particular to a semiconductor structure and a method for forming the same.
  • Temperature changes have an impact on the chip's working state and circuit performance.
  • the chip When the chip is working, only a part of the input power is output as useful work, and a lot of electric energy is converted into heat energy, which increases the temperature of the components in the chip.
  • the allowable working temperature of components is limited. If the actual temperature exceeds the allowable temperature of components, the performance of components will deteriorate or even burn out. This is true for transistors, resistors, capacitors, transformers, printed circuit boards, and memory.
  • thermocontrol devices can be used to control the temperature of the chip, the temperature control efficiency is not high, and the package of the temperature control device and the chip makes the volume of the whole device larger.
  • Some embodiments of the present disclosure provide a semiconductor structure, including:
  • a semiconductor substrate comprising a chip region and a temperature control region surrounding the chip region;
  • the Peltier device located in the temperature control area includes several P-type doped regions arranged alternately along the boundary direction of the chip area and A number of N-type doped regions; a first-end metal layer and a second-end metal layer located on the side away from the chip region of the N-type doped region and P-type doped region, and the first-end metal layer is electrically connected to the The plurality of N-type doped regions, the second terminal metal layer is electrically connected to the plurality of P-type doped regions; the semiconductor substrate located on the side of the N-type doped region and the P-type doped region close to the chip region The third terminal metal layer, the third terminal metal layer is electrically connected to the N-type doped region and the P-type doped region.
  • Some embodiments of the present disclosure also provide a method for forming a semiconductor structure, including:
  • a semiconductor substrate comprising a chip region and a temperature control region surrounding the chip region;
  • a Peltier device is formed in the temperature control area, including:
  • first-end metal layer and a second-end metal layer Forming a first-end metal layer and a second-end metal layer on the side away from the chip area of the N-type doped region and the P-type doped region, the first-end metal layer is electrically connected to the plurality of N-type doped region, the second terminal metal layer is electrically connected to the plurality of P-type doped regions;
  • a third terminal metal layer in the semiconductor substrate on the side of the N-type doped region and the P-type doped region close to the chip region, and the third terminal metal layer is electrically connected to the N-type doped region and the P-type doped region. P-type doped region.
  • FIGS. 1-7 are schematic structural diagrams of semiconductor devices in some embodiments of the present disclosure.
  • 12-13 are schematic structural diagrams of semiconductor devices in some other embodiments.
  • FIG. 2-FIG. 7, FIG. 3 and FIG. 6 are partial enlarged structural schematic diagrams of the Peltier device in FIG. 2, and FIG. Schematic diagram of the cross-sectional structure
  • Figure 5 is a schematic diagram of the cross-sectional structure of Figure 3 along the direction of the cutting line CD
  • Figure 7 is a schematic diagram of the cross-sectional structure of Figure 6 along the direction of the cutting line AB, including:
  • a semiconductor substrate 100 comprising a chip region 101 and a temperature control region 102 surrounding the chip region 101;
  • the Peltier device 104 located in the temperature control area 102 includes several semiconductor substrates 100 located in the temperature control area 102 and arranged alternately along the boundary direction of the chip area 101 P-type doped region 105 and several N-type doped regions 106 (refer to FIG. 3 and FIG. 5 ); Layer 107 (refer to FIG. 3, for convenience of illustration, the second terminal metal layer 112 is not shown in FIG. 3) and the second terminal metal layer 112 (refer to FIG.
  • the first terminal metal layer layer 107 is electrically connected to the plurality of N-type doped regions 106, and the second terminal metal layer 112 is electrically connected to the plurality of P-type doped regions 105;
  • Type doped region 106 and P-type doped region 105 are close to the third terminal metal layer 111 in the semiconductor substrate 100 on the chip region 101 side (refer to FIG. 3 and FIG. 4 ), and the third terminal metal layer 111 is electrically connected to In the N-type doped region 106 and the P-type doped region 105 .
  • the material of the semiconductor substrate 100 can be silicon (Si), germanium (Ge), or silicon germanium (GeSi), silicon carbide (SiC); it can also be silicon on insulator (SOI), germanium on insulator (GOI); Or it can also be other materials, such as III-V group compounds such as gallium arsenide.
  • the material of the semiconductor substrate 100 is silicon.
  • the chip area 101 is an area containing a semiconductor chip or an integrated circuit, and the semiconductor chip may be a sensor chip, a memory chip or a chip with other functions.
  • the temperature control area 102 surrounds the chip area 101 and is in contact with the peripheral edge of the chip area, and the Peltier device 104 in the temperature control area 102 controls the chip by semiconductor cooling effect.
  • the temperature of the region 101 is maintained so that the temperature of the chip region 101 is maintained at a predetermined temperature to prevent performance degradation of semiconductor chips or integrated circuits in the chip region 101 due to excessive temperature.
  • the number of the N-type doped region and the P-type doped region is at least one, and when the number of the N-type doped region and the P-type doped region is multiple, the A plurality of N-type doped regions and P-type doped regions are alternately arranged along the boundary extending direction of the chip region.
  • the N-type doped region and the P-type doped region are formed by ion implantation.
  • N-type impurity ions are implanted into several discrete first regions in the semiconductor substrate 100 in the temperature control region 102 to form several N-type doped regions, and several discrete first regions in the semiconductor substrate 100 in the temperature control region 102
  • the second region is implanted with P-type impurity ions to form several P-type doped regions.
  • the impurity ions implanted by the ion implantation are P-type impurity ions, and the P-type impurity ions are one or more of boron ions, gallium ions or indium ions.
  • the forming process of the N-type doped region 106 and the P-type doped region 105 may also include: forming a groove in the temperature control region 102; filling the groove with tellurium bismuth telluride material; doping the bismuth telluride material to form an N-type doped region 106 and a P-type doped region 105 .
  • the third terminal metal layer 111 is a strip-shaped metal layer, and the strip-shaped metal layer 111 is electrically connected to all the N-type doped regions 106 and the P-type doped region 105.
  • the Peltier device 104 When the Peltier device 104 is cooling, a voltage is applied to the first-end metal layer 107 and the second-end metal layer 112 (specifically, the first-end metal layer 107 is connected to the positive pole of the power supply, and the The second terminal metal layer 112 is connected to the negative pole of the power supply), the N-type doped region and the P-type doped region are connected to one end of the third terminal metal layer 111 as a cold terminal, and the third terminal metal layer 111 absorbs the The heat generated in the chip region, in this disclosure, because the third terminal metal layer 111 is located in the semiconductor substrate 100 on the side of the N-type doped region 106 and the P-type doped region 105 close to the chip region 101, it passes through the second The three-terminal metal layer 111 can directly absorb the heat generated by the components and devices formed in the semiconductor substrate in the chip area laterally, thereby improving the efficiency of temperature control, and because the Peltier device 104 is located in the temperature control area 102 around the chip area 101 ,
  • the third terminal metal layer 111 may be a material selected from W, Al, Cu, Ag, Au, Pt, Ni, Ti, TiN, TaN, Ta, TaC, TaSiN, WN, Wsi
  • the semiconductor substrate 100 on the side of the N-type doped region 106 and the P-type doped region 105 close to the chip region 101 has exposed the N-type doped region 106 and the P-type doped region.
  • the first groove 121 (refer to FIG. 9 ) on the sidewall surface of the side wall near the chip region 101 of 105 is filled with the third terminal metal layer 111 .
  • the first end metal layer 107 and the second end metal layer 112 are located in different layers (it should be noted that, for the convenience of illustration, only the first end metal layer is shown in FIG. 3 107, the second terminal metal layer 112 is not shown, only the second terminal metal layer 112 is shown in FIG. 7, and the first terminal metal layer 107 is not shown).
  • the first metal layer 107 is located below the second metal layer 112, the first metal layer 107 is the lower or front layer, and the second metal layer 112 is the upper or When layer.
  • the first metal layer is located above the second metal layer, the first metal layer is the upper layer or the current layer, and the second metal layer is the lower layer or the front layer.
  • the first terminal metal layer 107 and the second terminal metal layer 112 can be W, Al, Cu, Ag, Au, Pt, Ni, Ti, TiN, TaN, Ta, TaC, TaSiN A single-layer structure formed by one material among WN, Wsi, or a laminated structure formed by two or more materials in the group formed by the above-mentioned materials.
  • the first terminal metal layer 107 (refer to FIG. 3 ) and the second terminal metal layer 112 (refer to FIG. 6 ) both include several tooth-shaped portions (108 or 113) and the body portion (109 or 114) connected to the several toothed portions (108 or 113), the body portion (109 or 114) and the corresponding N-type doped region 106 and P-type doped region 105
  • the first terminal metal layer 107 and the second-end metal layer 112 are used as hot ends, the heat dissipation area per unit volume is larger, which improves the heat dissipation efficiency.
  • the first terminal metal layer 107 (refer to FIG.
  • the second terminal metal layer 112 (refer to FIG. 1 ) includes several tooth-shaped portions 108 protruding away from the chip area 101 and a body portion 109 connected to the several tooth-shaped portions 108, the body The portion 109 is electrically connected to the corresponding N-type doped region 106 , and in some embodiments, the body portion 109 is electrically connected to the corresponding N-type doped region 106 through the connecting portion 110 .
  • the second terminal metal layer 112 (refer to FIG.
  • the body portion 114 includes several tooth-shaped portions 113 protruding away from the chip area 101 and a body portion 114 connected to the several tooth-shaped portions 113, the body portion 114 is connected to The corresponding P-type doped regions 105 are electrically connected, and in some embodiments, the body portion 114 is electrically connected to the corresponding P-type doped regions 105 through the connecting portion 115 .
  • the first-end metal layer 107 is located under the second-end metal layer 112, and the first-end metal layer 107 is located under the N-type doped
  • the impurity region 106 and the P-type doped region 105 are in the semiconductor substrate 100 on the side away from the chip region 101 .
  • the semiconductor structure further includes a dielectric layer 118 , and the first terminal metal layer 107 and the second terminal metal layer 112 are separated by the dielectric layer 118 .
  • the dielectric layer 118 is silicon oxide, silicon nitride, silicon oxynitride, FSG (fluorine-doped silicon dioxide), BSG (boron-doped silicon dioxide), PSG (phosphorus-doped silicon dioxide Silicon) or BPSG (boron-phosphorus-doped silicon dioxide), a single-layer structure formed by one of the low dielectric constant materials, or a stacked structure formed by two or more materials in the group consisting of the above materials .
  • the semiconductor structure further includes a plurality of first connection metal pads 116 and a first metal plug 117 connected to the upper surface of each of the first connection metal pads 116, the first The connection metal pad 116 is located in the semiconductor substrate 100 on the side of the P-type doped region 105 away from the chip region 101 and is electrically connected to the side of the P-type doped region 105 far away from the chip region 101.
  • the second terminal The metal layer 112 is connected to the corresponding first connection metal pad 116 through the first metal plug 117 located in the dielectric layer 118, so as to be electrically connected to the side of the corresponding P-type doped region 105 away from the chip region 101. connect.
  • the Peltier device 104 in the temperature control area 102 can be located on one or more sides of the boundary of the chip area, so that the chip can be aligned from one direction or multiple directions. zone for temperature control.
  • the Peltier device 104 in the temperature control area 102 surrounds the chip area 101 along the boundary direction of the chip area 101, so that the chip area 101 can be controlled from around the chip area 101. Direct temperature control in the lateral direction can better control the temperature of the chip area 101 .
  • the semiconductor structure further includes a guard ring device, the guard ring device includes several layers of metal layers and metal plugs connecting the metal layers of adjacent layers, the guard ring device is arranged on the between the Ertier device and the semiconductor chip, and around the semiconductor chip.
  • the temperature control region 102 can also serve as a guard ring region, and the semiconductor structure further includes a guard ring device, and the guard ring device includes several metal layers and metal layers connecting adjacent metal layers.
  • the protection ring device is arranged on the Peltier device and surrounds the chip area, so as to realize temperature control and protection of the semiconductor chip in the chip area in one area.
  • the guard ring device (seal ring, also known as a seal ring device, guard ring device) can also block water vapor penetration or, for example, acid-containing substances,
  • the chemical damage caused by the diffusion of pollution sources such as alkalis plays a role in protecting semiconductor chips.
  • the guard ring device has a multi-layer structure, including several layers of metal layers and metal plugs connecting adjacent layers of metal layers, and a dielectric layer isolating several layers of metal layers and corresponding metal plugs.
  • the dielectric layer For multi-layer structure.
  • FIGS. 9 is a schematic cross-sectional structure diagram of FIG. 8 along the cutting line AB
  • FIG. 11 is a schematic cross-sectional structure diagram of FIG. 112
  • the first terminal metal layer 107 is not shown, only the first terminal metal layer 107 is shown in FIG. 10, and the second terminal metal layer 112 is not shown), the first terminal metal layer 107 is located layer 112 (refer to FIG.
  • the semiconductor structure further includes a dielectric layer 118 (refer to FIG. 11), and the first terminal metal layer 107 and the second terminal metal layer 112 are separated by the dielectric layer 118.
  • the semiconductor structure further includes a plurality of second connection metal pads 126 and a second metal plug 127 connected to the upper surface of each of the second connection metal pads 126, the second The connecting metal pad 126 is located in the semiconductor substrate 100 on the side of the N-type doped region 106 away from the chip region 101 and is electrically connected to the side of the N-type doped region 106 far away from the chip region 101.
  • the first end The metal layer 107 is connected to the corresponding second connection metal pad 126 through the second metal plug 127 located in the dielectric layer 118, so as to be electrically connected to the side of the corresponding N-type doped region 106 away from the chip region 101. connect.
  • the third The terminal metal layer includes several third terminal metal layers (111a, 111b, 111c) spaced in sequence, and each third terminal metal layer (111a, 111b, 111c) is electrically connected to at least one pair of adjacent N-type doped regions 106 and a P-type doped region 105 .
  • a method for forming a semiconductor structure including:
  • a semiconductor substrate 100 is provided, and the semiconductor substrate 100 includes a chip region 101 and a temperature control region 102 surrounding the chip region 101 .
  • the semiconductor substrate 100 is a wafer, and the semiconductor substrate 100 includes a plurality of chip regions 101 arranged in rows and columns, each chip region 100 is surrounded by a temperature control region surrounding the chip region 101 102 , between the temperature control zones 102 is a kerf zone 103 .
  • the temperature control area 102 is subsequently used to form a Peltier device, the chip area 101 is subsequently used to form a semiconductor chip, and the dicing line area 103 is subsequently used as a dicing line for dividing a wafer.
  • a Peltier device 104 is formed in the temperature control area, including:
  • N-type doped regions 106 and several P-type doped regions 105 arranged alternately along the boundary direction of the chip region 101 are formed in the semiconductor substrate 100 located in the temperature control region 102 .
  • the N-type doped region and the P-type doped region are formed by ion implantation.
  • N-type impurity ions are implanted into several discrete first regions in the semiconductor substrate 100 in the temperature control region 102 to form several N-type doped regions, and several discrete first regions in the semiconductor substrate 100 in the temperature control region 102
  • the second region is implanted with P-type impurity ions to form several P-type doped regions.
  • the impurity ions implanted by the ion implantation are P-type impurity ions, and the P-type impurity ions are one or more of boron ions, gallium ions or indium ions.
  • the forming process of the N-type doped region 106 and the P-type doped region 105 may also include: forming a groove in the temperature control region 102; filling the groove with tellurium bismuth telluride material; doping the bismuth telluride material to form an N-type doped region 106 and a P-type doped region 105 .
  • the first terminal metal layer 107 and the second terminal metal layer 112 located on the side away from the chip region 101 of the N-type doped region 106 and the P-type doped region 105 are formed, and the first terminal The metal layer 107 is electrically connected to the plurality of N-type doped regions 106 , and the second terminal metal layer 112 is electrically connected to the plurality of P-type doped regions 105 .
  • the first terminal metal layer 107 is located below the second terminal metal layer 112, and the forming process of the first terminal metal layer 107 and the second terminal metal layer 112 includes: A comb-shaped second groove is formed in the semiconductor substrate on the side of the N-type doped region 106 away from the chip region, and the second groove exposes the number of N-type doped regions 106 away from the chip region.
  • a plurality of third grooves are formed in the semiconductor substrate on the side away from the chip of each of the P-type doped regions 105, and each of the third grooves correspondingly exposes one of the The P-type doped region 105 is far away from the sidewall surface of the chip; the metal is filled in the comb-shaped second groove to form the first terminal metal layer 107 (refer to Fig. 3 and Fig. 4 ), and in the plurality of third Metal is filled in the trench to form a number of first connection metal pads 116 (refer to FIG. 3 and FIG. 5 ); a dielectric layer 118 is formed on the semiconductor substrate 100 (refer to FIG.
  • first connection metal pads 116 are connected to the plurality of first metal plugs 117 ; and the second terminal metal layer 112 connected to the plurality of first metal plugs 117 is formed on the dielectric layer 118 .
  • the first terminal metal layer 107 is located above the second terminal metal layer 112, and the The forming process includes: forming a comb-shaped fourth groove in the semiconductor substrate on the side of the P-type doped region 105 away from the chip region, the fourth groove exposing the plurality of P-type doped regions.
  • the groove correspondingly exposes a side wall surface of the N-type doped region 106 away from the chip; filling metal in the comb-shaped fourth groove forms the second terminal metal layer 112 (refer to FIGS. 8-9 ), filling metal in the plurality of fifth trenches to form a plurality of second connection metal pads 126 (refer to FIG. 8 ); form a dielectric layer 118 on the semiconductor substrate 100 (refer to FIG.
  • the dielectric layer A plurality of second metal plugs 127 connected to corresponding second connection metal pads 126 are formed in the dielectric layer 118 ; and a first terminal metal layer 107 connected to the plurality of second metal plugs 127 is formed on the dielectric layer 118 .
  • a third terminal metal layer 111 located in the semiconductor substrate 100 on the side of the N-type doped region 106 and the P-type doped region 105 close to the chip region 101 is formed, and the third terminal metal layer 111 is formed.
  • the layer 111 is electrically connected to the N-type doped region 106 and the P-type doped region 105 .
  • the forming process of the third terminal metal layer 111 includes: forming a first groove 121, the first groove 121 exposes the side wall surface of the N-type doped region 106 and the P-type doped region 105 close to the chip region 101; in the first groove 121 The middle filling metal forms the third terminal metal layer 111 .
  • the third terminal metal layer 111 is formed synchronously with the first terminal metal layer 107 or the second terminal metal layer 112 on the same layer, specifically, when the first terminal metal layer 107 is located on the second terminal metal layer When the layer 112 is a lower layer, the third terminal metal layer 111 is formed synchronously with the first terminal metal layer 107 . When the second terminal metal layer 112 is located under the first terminal metal layer 107 , the third terminal metal layer 111 is formed synchronously with the second terminal metal layer 112 .
  • it also includes: forming a semiconductor chip in the chip region 101, forming a guard ring device surrounding the semiconductor chip between the Peltier device and the semiconductor chip, and the guard ring device includes Several layers of metal layers and metal plugs connecting metal layers of adjacent layers.
  • the manufacturing process of the Peltier device and the semiconductor chip can be integrated, for example, the formation process of the first terminal metal layer 107 or the second terminal metal layer 112 located on the upper layer can be the same as that of the bottom layer when manufacturing the semiconductor chip.
  • the metal line process is carried out synchronously, the formation process of the N-type doped region 106 and the P-type doped region 105 can be carried out synchronously with the related doping process in the semiconductor chip, and the process of forming the trench in the temperature control region can be carried out with the chip
  • the process of forming trenches in the region is performed simultaneously.
  • the wafer can be diced along the dicing line area to form several independent chips.

Abstract

一种半导体器件及其形成方法，所述半导体器件包括：半导体衬底，所述半导体衬底包括芯片区和围绕芯片区的控温区；位于所述控温区的珀尔帖器件，所述珀尔帖器件包括位于所述控温区的半导体衬底中且沿着所述芯片区边界方向交替排布的若干P型掺杂区和若干N型掺杂区；位于所述N型掺杂区和P型掺杂区远离芯片区一侧的第一端金属层和第二端金属层，所述第一端金属层电连接于所述若干N型掺杂区，所述第二端金属层电连接于所述若干P型掺杂区；位于所述N型掺杂区和P型掺杂区靠近芯片区一侧的半导体衬底中的第三端金属层，所述第三端金属层电连接于所述N型掺杂区与P型掺杂区。

Description

半导体结构及其形成方法
相关申请引用说明
本公开要求于2022年01月12日递交的中国专利申请号202210030628.0，申请名为“半导体结构及其形成方法”的优先权，其全部内容以引用的形式附录于此。
技术领域
本公开涉及半导体领域，尤其涉及一种半导体结构及其形成方法。
背景技术
温度变化对芯片的工作装态、电路性能有影响。芯片在工作时，输入功率只有一部分作有用功输出，还有很多的电能转化成热能，使芯片中元器件温度升高。而元器件允许的工作温度都是有限的，如果实际温度超过了元器件的允许温度，则元器件的性能会变坏，甚至烧毁。晶体管、电阻、电容、变压器、印制电路板、存储器都是如此。
现有虽然可以使用一些控温器件对芯片的温度进行控制，但是控温效率不高，并且控温器件与芯片的集合封装在一起使得整个器件的体积会较大。
发明内容
本公开一些实施例提供了一种半导体结构，包括：
半导体衬底，所述半导体衬底包括芯片区和围绕芯片区的控温区；
位于所述控温区的珀尔帖器件，所述珀尔帖器件包括位于所述控温区的半导体衬底中且沿着所述芯片区边界方向交替排布的若干P型掺杂区和若干N型掺杂区；位于所述N型掺杂区和P型掺杂区远离芯片区一侧的第一端金属层和第二端金属层，所述第一端金属层电连接于所述若干N型掺杂区，所述第二端金属层电连接于所述若干P型掺杂区；位于所述N型掺杂区和P型掺杂区靠近芯片区一侧的半导体衬底中的第三端金属层，所述第三端金属层电连接于所述N型掺杂区与P型掺杂区。
本公开一些实施例还提供了一种半导体结构的形成方法，包括：
提供半导体衬底，所述半导体衬底包括芯片区和围绕芯片区的控温区；
在所述控温区形成珀尔帖器件，包括：
在位于所述控温区的半导体衬底中形成沿着所述芯片区边界方向交替排布的若干P型掺杂区和若干N型掺杂区；
形成位于所述N型掺杂区和P型掺杂区远离芯片区一侧的第一端金属层和第二端金属层，所述第一端金属层电连接于所述若干N型掺杂区，所述第二端金属层电连接于所述若干P型掺杂区；
形成位于所述N型掺杂区和P型掺杂区靠近芯片区一侧的半导体衬底中的第三端金属层，所述第三端金属层电连接于所述N型掺杂区与P型掺杂区。
附图说明
图1-图7为本公开一些实施例中半导体器件的结构示意图；
图8-图11为另一些实施例中半导体器件的结构示意图；
图12-图13为又一些实施例中半导体器件的结构示意图。
具体实施方式
下面结合附图对本公开的具体实施方式做详细的说明。在详述本公开实施例时，为便于说明，示意图会不依一般比例作局部放大，而且所述示意图只是示例，其在此不应限制本公开的保护范围。此外，在实际制作中应包含长度、宽度及深度的三维空间尺寸。
本公开一些实施例提供了一种半导体器件，参考图2-图7，图3和图6为图2中的珀尔帖器件的部分放大结构示意图，图4为图3沿切割线AB方向的剖面结构示意图，图5为图3沿切割线CD方向的剖面结构示意图，图7为图6沿切割线AB方向的剖面结构示意图，包括：
半导体衬底100，所述半导体衬底100包括芯片区101和围绕芯片区101的控温区102；
位于所述控温区102的珀尔帖器件104，所述珀尔帖器件104包括位于所述控温区102的半导体衬底100中且沿着所述芯片区101边界方向交替排布的若干P型掺杂区105和若干N型掺杂区106(参考图3和图5)；位于所述N型掺杂区106和P型掺杂区105远离芯片区101一侧的第一端金属层107(参考图3，为方便示意，图3中未示出第二端金属层112)和第二端金属层112(参考图6，为方便示意，图6中未示出第一端金属层107)，所述第一端金属层107电连接于所述若干N型掺杂区106，所述第二端金属层112电连接于所 述若干P型掺杂区105；位于所述N型掺杂区106和P型掺杂区105靠近芯片区101一侧的半导体衬底100中的第三端金属层111(参考图3和图4)，所述第三端金属层111电连接于所述N型掺杂区106与P型掺杂区105。
所述半导体衬底100的材料可以为硅(Si)、锗(Ge)、或硅锗(GeSi)、碳化硅(SiC)；也可以是绝缘体上硅(SOI)，绝缘体上锗(GOI)；或者还可以为其它的材料，例如砷化镓等Ⅲ-Ⅴ族化合物。本实施例中，所述半导体衬底100的材料为硅。
所述芯片区101中为包含半导体芯片或集成电路的区域，所述半导体芯片可以为传感器芯片、存储器芯片或者具有其他功能的芯片。所述控温区102围绕所述芯片区101并与所述芯片区四周边缘接触，所述控温区102的珀尔帖器件104，所述珀尔帖器件104通过半导体制冷效应控制所述芯片区101的温度，以使得所述芯片区101的温度保持在预定的温度，防止芯片区101中的半导体芯片或集成电路因温度过高而性能下降。
参考图3和图5，所述N型掺杂区和P型掺杂区的数量为至少为一个，所述N型掺杂区和P型掺杂区的数量均为多个时，所述多个所述N型掺杂区和P型掺杂区沿着芯片区的边界延伸方向交替排布。
在一些实施例中，所述N型掺杂区和P型掺杂区通过离子注入工艺形成。具体的，向控温区102的半导体衬底100中的若干分立的第一区域注入N型杂质离子，形成若干N型掺杂区，向控温区102的半导体衬底100中的若干分立的第二区域注入P型杂质离子，形成若干P型掺杂区。所述离子注入注入的杂质离子为P型的杂质离子，所述P型的杂质离子为硼离子、镓离子或铟离子一种或几种。在另一些实施例中，所述N型掺杂区106和P型掺杂区105的形成过程还可以包括：在所述控温区102中形成凹槽；在所述凹槽中填充满碲化铋材料；对所述碲化铋材料进行掺杂，形成N型掺杂区106和P型掺杂区105。
本实施例中，参考图3和图4，所述第三端金属层111为长条形的金属层，所述长条形的金属层111电连接于所有的所述N型掺杂区106和所述P型掺杂区105。所述珀尔帖器件104在进行制冷时，在所述第一端金属层107和所述第二端金属层112上施加电压(具体的，将第一端金属层107接电源的正极，将所述第二端金属层112接电源的负极)，所述N型掺杂区和P型掺杂区连接 第三端金属层111的一端作为冷端，通过第三端金属层111吸收所述芯片区产生的热量，本公开中由于第三端金属层111是位于所述N型掺杂区106和P型掺杂区105靠近芯片区101一侧的半导体衬底100中的，因而通过第三端金属层111可以横向直接吸收芯片区的半导体衬底中形成的元器件产生的热量，从而提高温度控制的效率，并且由于珀尔帖器件104是位于芯片区101周围的控温区102中，后续可以与芯片区101形成的半导体芯片一体封装，不会占据太大的体积。
在一些实施例中，所述第三端金属层111可以为W、Al、Cu、Ag、Au、Pt、Ni、Ti、TiN、TaN、Ta、TaC、TaSiN、WN、Wsi中的一种材料所形成的单层结构或者为上述材料所组成群组中的两种以上材料所形成的叠层结构。
在一些实施例中，所述N型掺杂区106和P型掺杂区105靠近芯片区101一侧的半导体衬底100中具有暴露出所述N型掺杂区106和P型掺杂区105的靠近芯片区101的一侧侧壁表面的第一沟槽121(参考图9)，所述第三端金属层111填充满所述第一沟槽。
参考图3-图7，所述第一端金属层107和所述第二端金属层112位于不同的层(需要说明的是，为了方便示意，图3中仅示出了第一端金属层107，未示出第二端金属层112，图7中仅示出了第二端金属层112，未示出第一端金属层107)。本实施例中，所述第一端金属层107位于所述第二端金属层112的下方，所述第一端金属层107为下层或前层，所述第二端金属层112为上层或当层。在其他一些实施例中，第一端金属层位于所述第二端金属层的上方，所述第一端金属层为上层或当层，所述第二端金属层为下层或前层。
在一些实施例中，所述第一端金属层107和所述第二端金属层112可以为W、Al、Cu、Ag、Au、Pt、Ni、Ti、TiN、TaN、Ta、TaC、TaSiN、WN、Wsi中的一种材料所形成的单层结构或者为上述材料所组成群组中的两种以上材料所形成的叠层结构。
在一些实施例中，所述第一端金属层107(参考图3)和第二端金属层112(参考图6)均包括向远离芯片区101的方向凸出的若干齿状部(108或113)和连接于所述若干齿状部(108或113)的本体部(109或114)，所述本体部(109或114)与相应的N型掺杂区106和P型掺杂区105电连接，通过前述 特定的形状，第一端金属层107和第二端金属层112作为热端时，单位体积内的散热面积更大，提高了散热的效率。具体的，所述第一端金属层107(参考图3)包括向远离芯片区101的方向凸出的若干齿状部108和连接于所述若干齿状部108的本体部109，所述本体部109与相应的N型掺杂区106电连接，在一些实施例中，所述本体部109通过连接部110与相应的N型掺杂区106电连接。所述第二端金属层112(参考图6)包括向远离芯片区101的方向凸出的若干齿状部113和连接于所述若干齿状部113的本体部114，所述本体部114与相应的P型掺杂区105电连接，在一些实施例中，所述本体部114通过连接部115与相应的P型掺杂区105电连接。
本实施例中，参考图3-图4以及图6-图7，所述第一端金属层107位于第二端金属层112下方，且所述第一端金属层107位于所述N型掺杂区106和P型掺杂区105远离芯片区101一侧的半导体衬底100中。在一些实施例中，参考图7，所述半导体结构还包括介质层118，所述第一端金属层107和第二端金属层112通过所述介质层118隔离。
在一些实施例中，所述介质层118位氧化硅、氮化硅、氮氧化硅、FSG(掺氟的二氧化硅)、BSG(掺硼的二氧化硅)、PSG(掺磷的二氧化硅)或BPSG(掺硼磷的二氧化硅)、低介电常数材料中的一种材料所形成的单层结构或者为上述材料所组成群组中的两种以上材料所形成的叠层结构。
在一些实施例中，参考图7，所述半导体结构还包括若干第一连接金属垫116和连接于每个所述第一连接金属垫116上表面的第一金属插塞117，所述第一连接金属垫116位于所述P型掺杂区105远离芯片区101一侧的半导体衬底100中且与所述P型掺杂区105远离芯片区101的一侧电连接，所述第二端金属层112通过位于所述介质层118中的第一金属插塞117与相应的第一连接金属垫116连接，从而与相应的P型掺杂区105的远离所述芯片区101的一侧电连接。
在一些实施例中，所述控温区102中的所述珀尔帖器件104可以位于所述芯片区的一条边界一侧或者多条边界一侧，从而可以从一个方向或多个方向对芯片区进行控温。
在一些实施例中，所述控温区102中的所述珀尔帖器件104沿着所述芯片 区101边界方向包围所述芯片区101，使得可以从芯片区101的四周对芯片区101进行横向的直接控温，能更好的控制芯片区101的温度。
在一些实施例中，所述半导体结构还包括保护环器件，所述保护环器件包括若干层金属层和将相邻层的金属层连接的金属插塞，所述保护环器件设置于所述珀尔帖器件和所述半导体芯片之间，且围绕所述半导体芯片。
在一些实施例中，所述控温区102还可以作为保护环区，所述半导体结构还包括保护环器件，所述保护环器件包括若干层金属层和将相邻层的金属层连接的金属插塞，所述保护环器件设置于所述珀尔帖器件上，且围绕所述芯片区，在一个区域既能实现控温又能实现对芯片区的半导体芯片的保护。
所述保护环器件(seal ring，也称作密封环器件、防护环器件)为了防止半导体芯片受到切割工艺的损害及避免水气引发劣化的情形，还可以阻挡水气渗透或例如含酸物、含碱物等污染源的扩散的化学损害，起到保护半导芯片的作用。所述保护环器件呈多层结构，包括若干层金属层和将相邻层的金属层连接的金属插塞，以及将若干层金属层和相应的金属插塞隔离的介质层，所述介质层为多层结构。
本发明另一实施例还提供了一种半导体结构，本实施例与前述实施例的区别在于，所述第一端金属层位于第二端金属层上方，具体请参考图8-图11，图9为图8沿切割线AB方向的剖面结构示意图，图11为图10沿切割线AB方向的剖面结构示意图(需要说明的是，为了方便示意，图8中仅示出了第二端金属层112，未示出第一端金属层107，图10中仅示出了第一端金属层107，未示出第二端金属层112)，所述第一端金属层107位于第二端金属层112(参考图11)上方，且所述第二端金属层112位于所述N型掺杂区106和P型掺杂区105远离芯片区101一侧的半导体衬底100中(参考图8和图9)；所述半导体结构还包括介质层118(参考图11)，所述第一端金属层107和第二端金属层112通过所述介质层118隔离。
在一些实施例中，参考图11，所述半导体结构还包括若干第二连接金属垫126和连接于每个所述第二连接金属垫126上表面的第二金属插塞127，所述第二连接金属垫126位于所述N型掺杂区106远离芯片区101一侧的半导体衬底100中且与所述N型掺杂区106远离芯片区101的一侧电连接，所述第一端 金属层107通过位于所述介质层118中的第二金属插塞127与相应的第二连接金属垫126连接，从而与对应的N型掺杂区106的远离所述芯片区101的一侧电连接。
本发明又一实施例还提供了一种半导体结构，本实施例与前述实施例的区别在于，所述第三端金属层的具体结构不同，具体请参考图12和图13，所述第三端金属层包括若干依次间隔的第三端子金属层(111a、111b、111c)，每一个第三端子金属层(111a、111b、111c)电连接于至少一对相邻的N型掺杂区106和P型掺杂区105。
本发明一些实施例中，还提供了一种半导体结构的形成方法，包括：
参考图1，提供半导体衬底100，所述半导体衬底100包括芯片区101和围绕芯片区101的控温区102。
在一些实施例中，所述半导体衬底100为晶圆，所述半导体衬底100包括若干呈行列排布的芯片区101，每一个芯片区100周围具有一个围绕该芯片区101的控温区102，所述控温区102之间为切割道区103。所述控温区102后续用于形成珀尔帖器件，所述芯片区101后续用于形成半导体芯片，所述切割道区103后续作为分割晶圆时的切割道。
参考图2，在所述控温区形成珀尔帖器件104，包括：
参考图3和图5，在位于所述控温区102的半导体衬底100中形成沿着所述芯片区101边界方向交替排布的若干N型掺杂区106和若干P型掺杂区105。
在一些实施例中，所述N型掺杂区和P型掺杂区通过离子注入工艺形成。具体的，向控温区102的半导体衬底100中的若干分立的第一区域注入N型杂质离子，形成若干N型掺杂区，向控温区102的半导体衬底100中的若干分立的第二区域注入P型杂质离子，形成若干P型掺杂区。所述离子注入注入的杂质离子为P型的杂质离子，所述P型的杂质离子为硼离子、镓离子或铟离子一种或几种。在另一些实施例中，所述N型掺杂区106和P型掺杂区105的形成过程还可以包括：在所述控温区102中形成凹槽；在所述凹槽中填充满碲化铋材料；对所述碲化铋材料进行掺杂，形成N型掺杂区106和P型掺杂区105。
参考图3和图6，形成位于所述N型掺杂区106和P型掺杂区105远离芯片区101一侧的第一端金属层107和第二端金属层112，所述第一端金属层107 电连接于所述若干N型掺杂区106，所述第二端金属层112电连接于所述若干P型掺杂区105。
在一些实施例中，所述第一端金属层107位于所述第二端金属层112的下方，所述第一端金属层107和第二端金属层112的形成过程包括：在所述N型掺杂区106的远离所述芯片区的一侧半导体衬底中形成梳状的第二沟槽，所述第二沟槽暴露出所述若干N型掺杂区106的远离所述芯片区的一侧的侧壁表面；在每一个所述P型掺杂区105远离芯片的一侧半导体衬底中形成若干第三沟槽，每一个所述第三沟槽相应的暴露出一个所述P型掺杂区105远离芯片的一侧侧壁表面；在所述梳状的第二沟槽中填充金属形成第一端金属层107(参考图3和图4)，在所述若干第三沟槽中填充金属，形成若干第一连接金属垫116(参考图3和图5)；在所述半导体衬底100上形成介质层118(参考图7)，所述介质层118中形成有与相应的第一连接金属垫116连接若干第一金属插塞117；在所述介质层118上形成与若干第一金属插塞117连接的第二端金属层112。
在另一些实施例中，参考图8-图11，所述第一端金属层107位于所述第二端金属层112的上方，所述第一端金属层107和第二端金属层112的形成过程包括：在所述P型掺杂区105的远离所述芯片区的一侧半导体衬底中形成梳状的第四沟槽，所述第四沟槽暴露出所述若干P型掺杂区105的远离所述芯片区的一侧的侧壁表面；在每一个所述N型掺杂区106远离芯片的一侧半导体衬底中形成若干第五沟槽，每一个所述第五沟槽相应的暴露出一个所述N型掺杂区106远离芯片的一侧侧壁表面；在所述梳状的第四沟槽中填充金属形成第二端金属层112(参考图8-图9)，在所述若干第五沟槽中填充金属，形成若干第二连接金属垫126(参考图8)；在所述半导体衬底100上形成介质层118(参考图11)，所述介质层118中形成有与相应的第二连接金属垫126连接的若干第二金属插塞127；在所述介质层118上形成与若干第二金属插塞127连接的第一端金属层107。
参考图3和图4，形成位于所述N型掺杂区106和P型掺杂区105靠近芯片区101一侧的半导体衬底100中的第三端金属层111，所述第三端金属层111电连接于所述N型掺杂区106与P型掺杂区105。
在一些实施例中，所述第三端金属层111的形成过程包括：在所述N型掺 杂区106和P型掺杂区105靠近芯片区101一侧的半导体衬底100中形成第一沟槽121，所述第一沟槽121暴露出所述N型掺杂区106和P型掺杂区105的靠近所述芯片区101的一侧侧壁表面；在所述第一沟槽121中填充金属形成第三端金属层111。
在一些实施例中，所述第三端金属层111与位于同层的第一端金属层107或第二端金属层112同步形成，具体的，当第一端金属层107位于第二端金属层112下层时，所述第三端金属层111与第一端金属层107同步形成。当第二端金属层112位于第一端金属层107下层时，所述第三端金属层111与第二端金属层112同步形成。
在一些实施例中，还包括：在所述芯片区101形成半导体芯片，在所述珀尔帖器件和所述半导体芯片之间形成围绕所述半导体芯片的保护环器件，所述保护环器件包括若干层金属层和将相邻层的金属层连接的金属插塞。
在一些实施例中，所述珀尔帖器件与半导体芯片的制作工艺可以集成，比如，位于上层的第一端金属层107或第二端金属层112的形成工艺可以与制作半导体芯片时的底层金属线工艺同步进行，所述N型掺杂区106和P型掺杂区105形成工艺可以与半导体芯片中的相关的掺杂工艺同步进行，所述控温区形成沟槽的工艺可以与芯片区形成沟槽的工艺同步进行。
在一些实施例中，在珀尔帖器件与半导体芯片的制作完成后，可以沿切割道区域对晶圆进行切割，形成若干独立的芯片。
本公开虽然已以较佳实施例公开如上，但其并不是用来限定本公开，任何本领域技术人员在不脱离本公开的精神和范围内，都可以利用上述揭示的方法和技术内容对本公开技术方案做出可能的变动和修改，因此，凡是未脱离本公开技术方案的内容，依据本公开的技术实质对以上实施例所作的任何简单修改、等同变化及修饰，均属于本公开技术方案的保护范围。

Claims (19)

  1. 一种半导体结构，包括：
    半导体衬底，所述半导体衬底包括芯片区和围绕芯片区的控温区；
    位于所述控温区的珀尔帖器件，所述珀尔帖器件包括位于所述控温区的半导体衬底中且沿着所述芯片区边界方向交替排布的若干P型掺杂区和若干N型掺杂区；位于所述N型掺杂区和P型掺杂区远离芯片区一侧的第一端金属层和第二端金属层，所述第一端金属层电连接于所述若干N型掺杂区，所述第二端金属层电连接于所述若干P型掺杂区；位于所述N型掺杂区和P型掺杂区靠近芯片区一侧的半导体衬底中的第三端金属层，所述第三端金属层电连接于所述N型掺杂区与P型掺杂区。
  2. 如权利要求1所述的半导体结构，其中，所述第三端金属层为长条形的金属层，所述长条形的金属层电连接于所有的所述N型掺杂区和所述P型掺杂区。
  3. 如权利要求1所述的半导体结构，其中，所述第三端金属层包括若干依次间隔的第三端子金属层，每一个第三端子金属层电连接于至少一对相邻的N型掺杂区和P型掺杂区。
  4. 如权利要求1所述的半导体结构，其中，所述N型掺杂区和P型掺杂区靠近芯片区一侧的半导体衬底中具有暴露出所述N型掺杂区和P型掺杂区的靠近芯片区的一侧侧壁表面的第一沟槽，所述第三端金属层填充满所述第一沟槽。
  5. 如权利要求1所述的半导体结构，其中，所述第一端金属层和第二端金属层均包括向远离芯片区的方向凸出的若干齿状部和连接于所述若干齿状部的本体部，所述本体部与相应的N型掺杂区和P型掺杂区电连接。
  6. 如权利要求1所述的半导体结构，其中，所述第一端金属层位于第二端金属层下方，且所述第一端金属层位于所述N型掺杂区和P型掺杂区远离芯片区一侧的半导体衬底中；所述半导体结构还包括介质层，所述第一端金属层和第二端金属层通过所述介质层隔离。
  7. 如权利要求6所述的半导体结构，其中，所述半导体结构还包括若干第一连接金属垫和连接于每个所述第一连接金属垫上表面的第一金属插塞，所 述第一连接金属垫位于所述P型掺杂区远离芯片区一侧的半导体衬底中且与所述P型掺杂区远离芯片区的一侧电连接，所述第二端金属层通过位于所述介质层中的第一金属插塞与相应的第一连接金属垫连接。
  8. 如权利要求1所述的半导体结构，其中，所述第一端金属层位于第二端金属层上方，且所述第二端金属层位于所述N型掺杂区和P型掺杂区远离芯片区一侧的半导体衬底中；所述半导体结构还包括介质层，所述第一端金属层和第二端金属层通过所述介质层隔离。
  9. 如权利要求8所述的半导体结构，其中，所述半导体结构还包括若干第二连接金属垫和连接于每个所述第二连接金属垫上表面的第二金属插塞，所述第二连接金属垫位于所述N型掺杂区远离芯片区一侧的半导体衬底中且与所述N型掺杂区远离芯片区的一侧电连接，所述第一端金属层通过位于所述介质层中的第二金属插塞与相应的第二连接金属垫连接。
  10. 如权利要求1所述的半导体结构，其中，所述N型掺杂区和P型掺杂区通过离子注入工艺形成。
  11. 如权利要求1所述的半导体结构，其中，所述控温区中的所述珀尔帖器件沿着所述芯片区边界方向包围所述芯片区。
  12. 如权利要求1所述的半导体结构，其中，所述第一端金属层连接电源正极，所述第二端金属层连接电源负极。
  13. 如权利要求1所述的半导体结构，其中，所述芯片区包含半导体芯片，所述半导体结构还包括保护环器件，所述保护环器件包括若干层金属层和将相邻层的金属层连接的金属插塞，所述保护环器件设置于所述珀尔帖器件和所述半导体芯片之间，且围绕所述半导体芯片。
  14. 一种半导体结构的形成方法，包括：
    提供半导体衬底，所述半导体衬底包括芯片区和围绕芯片区的控温区；
    在所述控温区形成珀尔帖器件，包括：
    在位于所述控温区的半导体衬底中形成沿着所述芯片区边界方向交替排布的若干P型掺杂区和若干N型掺杂区；
    形成位于所述N型掺杂区和P型掺杂区远离芯片区一侧的第一端金属层和 第二端金属层，所述第一端金属层电连接于所述若干N型掺杂区，所述第二端金属层电连接于所述若干P型掺杂区；
    形成位于所述N型掺杂区和P型掺杂区靠近芯片区一侧的半导体衬底中的第三端金属层，所述第三端金属层电连接于所述N型掺杂区与P型掺杂区。
  15. 如权利要求14所述的半导体结构的形成方法，其中，所述第三端金属层的形成过程包括：在所述N型掺杂区和P型掺杂区靠近芯片区一侧的半导体衬底中形成第一沟槽，所述第一沟槽暴露出所述N型掺杂区和P型掺杂区的靠近所述芯片区的一侧侧壁表面；在所述第一沟槽中填充金属形成第三端金属层。
  16. 如权利要求14所述的半导体结构的形成方法，其中，所述第一端金属层和第二端金属层的形成过程包括：在所述N型掺杂区的远离所述芯片区的一侧半导体衬底中形成梳状的第二沟槽，所述第二沟槽暴露出所述若干N型掺杂区的远离所述芯片区的一侧的侧壁表面；在每一个所述P型掺杂区远离芯片的一侧半导体衬底中形成若干第三沟槽，每一个所述第三沟槽相应的暴露出一个所述P型掺杂区远离芯片的一侧侧壁表面；在所述梳状的第二沟槽中填充金属形成第一端金属层，在所述若干第三沟槽中填充金属，形成若干第一连接金属垫；在所述半导体衬底上形成介质层，所述介质层中形成有与相应的第一连接金属垫连接若干第一金属插塞；在所述介质层上形成与若干第一金属插塞连接的第二端金属层。
  17. 如权利要求15所述的半导体结构的形成方法，其中，所述第一端金属层和第二端金属层的形成过程包括：在所述P型掺杂区的远离所述芯片区的一侧半导体衬底中形成梳状的第四沟槽，所述第四沟槽暴露出所述若干P型掺杂区的远离所述芯片区的一侧的侧壁表面；在每一个所述N型掺杂区远离芯片的一侧半导体衬底中形成若干第五沟槽，每一个所述第五沟槽相应的暴露出一个所述N型掺杂区远离芯片的一侧侧壁表面；在所述梳状的第四沟槽中填充金属形成第二端金属层，在所述若干第五沟槽中填充金属，形成若干第二连接金属垫；在所述半导体衬底上形成介质层，所述介质层中形成有与相应的第二连接金属垫连接若干第二金属插塞；在所述介质层 上形成与若干第二金属插塞连接的第一端金属层。
  18. 如权利要求14所述的半导体结构的形成方法，其中，所述N型掺杂区和P型掺杂区的形成过程包括：在所述控温区中形成凹槽；在所述凹槽中填充满碲化铋材料；对所述碲化铋材料进行掺杂，形成N型掺杂区和P型掺杂区。
  19. 如权利要求14所述的半导体结构的形成方法，其中，还包括：在所述芯片区形成半导体芯片，在所述珀尔帖器件和所述半导体芯片之间形成围绕所述半导体芯片的保护环器件，所述保护环器件包括若干层金属层和将相邻层的金属层连接的金属插塞。
PCT/CN2022/084281 2022-01-12 2022-03-31 半导体结构及其形成方法 WO2023134024A1 (zh)

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002289752A (ja) * 2001-03-27 2002-10-04 Toshiba Elevator Co Ltd 半導体スイッチ装置及びこの半導体スイッチ装置を用いた電力変換装置
JP2004241714A (ja) * 2003-02-07 2004-08-26 Okano Electric Wire Co Ltd 熱電変換モジュール
CN102099917A (zh) * 2008-07-23 2011-06-15 Nxp股份有限公司 集成塞贝克器件
CN108490577A (zh) * 2018-03-12 2018-09-04 广东欧珀移动通信有限公司 结构光投射器、图像获取装置和电子设备
CN111430466A (zh) * 2020-05-06 2020-07-17 厦门芯达茂微电子有限公司 TE-cooler MOSFET结构及其制备、调节方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002289752A (ja) * 2001-03-27 2002-10-04 Toshiba Elevator Co Ltd 半導体スイッチ装置及びこの半導体スイッチ装置を用いた電力変換装置
JP2004241714A (ja) * 2003-02-07 2004-08-26 Okano Electric Wire Co Ltd 熱電変換モジュール
CN102099917A (zh) * 2008-07-23 2011-06-15 Nxp股份有限公司 集成塞贝克器件
CN108490577A (zh) * 2018-03-12 2018-09-04 广东欧珀移动通信有限公司 结构光投射器、图像获取装置和电子设备
CN111430466A (zh) * 2020-05-06 2020-07-17 厦门芯达茂微电子有限公司 TE-cooler MOSFET结构及其制备、调节方法

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