WO2023132233A1 - 半導体装置 - Google Patents

半導体装置 Download PDF

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Publication number
WO2023132233A1
WO2023132233A1 PCT/JP2022/046949 JP2022046949W WO2023132233A1 WO 2023132233 A1 WO2023132233 A1 WO 2023132233A1 JP 2022046949 W JP2022046949 W JP 2022046949W WO 2023132233 A1 WO2023132233 A1 WO 2023132233A1
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Prior art keywords
opening
insulating film
layer
organic insulating
width
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PCT/JP2022/046949
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English (en)
French (fr)
Japanese (ja)
Inventor
真理 佐治
敦 黒川
雅博 柴田
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Murata Manufacturing Co Ltd
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Murata Manufacturing Co Ltd
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Priority to JP2023572412A priority Critical patent/JP7764898B2/ja
Publication of WO2023132233A1 publication Critical patent/WO2023132233A1/ja
Priority to US18/750,258 priority patent/US20240339425A1/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D10/00—Bipolar junction transistors [BJT]
    • H10D10/80—Heterojunction BJTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/23—Electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. sources, drains, anodes or cathodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0112—Integrating together multiple components covered by H10D8/00, H10D10/00 or H10D18/00, e.g. integrating multiple BJTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/40—Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/45—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their insulating parts
    • H10W20/48—Insulating materials thereof
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/65—Shapes or dispositions of interconnections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/231—Shapes
    • H10W72/232—Plan-view shape, i.e. in top view
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/241—Dispositions, e.g. layouts
    • H10W72/244—Dispositions, e.g. layouts relative to underlying supporting features, e.g. bond pads, RDLs or vias
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/251—Materials
    • H10W72/252—Materials comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu

Definitions

  • the present invention relates to semiconductor devices.
  • Patent Document 1 describes a semiconductor device including a heterojunction bipolar transistor.
  • a semiconductor device described in Patent Document 1 has a bump provided right above a transistor. The bump is electrically connected to the emitter electrode of the transistor through an opening in an organic insulating film (resin film) covering the transistor.
  • the heat radiation performance is improved (that is, the thermal resistance is reduced), but stress from the bumps may cause cracks in the mesa structure and other problems. Reliability may decrease.
  • An object of the present invention is to provide a semiconductor device capable of suppressing stress generated in a transistor.
  • a semiconductor device includes a semiconductor substrate, at least one transistor provided on the semiconductor substrate and including a plurality of semiconductor layers, a wiring provided on the transistor, and a transistor perpendicular to the semiconductor substrate.
  • a first insulating film provided with a first opening in a region overlapping with the transistor and the wiring when viewed in plan in a first direction; a first rewiring layer overlapping with the at least one transistor through the first opening and electrically connected to the wiring through the first opening;
  • a second insulating film provided with a second opening in a region overlapping at least a part of the first rewiring layer when viewed in plan in the first direction; and the first rewiring layer through the second opening. and a bump electrically connected to the second insulating film, wherein the width of the first opening of the first insulating film in the second direction parallel to the semiconductor substrate is is greater than the width of the second opening of the
  • FIG. 1 is a plan view of the semiconductor device according to the first embodiment.
  • FIG. 2 is a sectional view taken along line II-II' of FIG.
  • FIG. 3 is a table for explaining the relationship between the opening width and the presence/absence of defects in the semiconductor devices according to the example and the comparative example.
  • FIG. 4 is a cross-sectional view of the semiconductor device according to the second embodiment.
  • FIG. 5 is a cross-sectional view of a semiconductor device according to the third embodiment.
  • FIG. 6 is an explanatory diagram of a semiconductor device according to a modification of the third embodiment.
  • FIG. 7 is an explanatory diagram for explaining the manufacturing process of the semiconductor device.
  • FIG. 1 is a plan view of the semiconductor device according to the first embodiment. Note that FIG. 1 omits the detailed configuration of each transistor BT, and schematically shows the arrangement relationship between the mesa structure including the base layer 4 and the emitter electrode 6 of each transistor. Also, in FIG. 1, the bumps 21 are indicated by a chain double-dashed line in order to make the drawing easier to see.
  • a semiconductor device 100 includes a semiconductor substrate 1, a transistor group Q1, a first organic insulating film 16, a second organic insulating film 19, an emitter wiring 11, and a first rewiring layer 18. , bumps 21 and .
  • one direction in the plane parallel to the surface of the semiconductor substrate 1 is defined as the X-axis direction Dx.
  • a direction orthogonal to the X-axis direction Dx in a plane parallel to the surface of the semiconductor substrate 1 is defined as a Y-axis direction Dy.
  • a direction perpendicular to each of the X-axis direction Dx and the Y-axis direction Dy is defined as a Z-axis direction Dz.
  • a Z-axis direction Dz is a direction perpendicular to the surface of the semiconductor substrate 1 .
  • the Z-axis direction Dz is an example of the "first direction”
  • the X-axis direction Dx and the Y-axis direction Dy are examples of the "second direction”.
  • a planar view indicates a positional relationship when viewed from the Z-axis direction Dz.
  • the transistor group Q ⁇ b>1 is provided on the surface of the semiconductor substrate 1 .
  • the transistor group Q1 has a plurality of transistors BT.
  • the transistor BT is a heterojunction bipolar transistor (HBT: Heterojunction Bipolar Transistor).
  • the transistor BT is also called a unit transistor, and the unit transistor is defined as the smallest transistor forming the transistor group Q1.
  • Transistors BT are electrically connected in parallel to form a transistor group Q1.
  • a plurality of transistors BT in the transistor group Q1 are arranged side by side in the X-axis direction Dx.
  • the mesa structures including the base layers 4 of the plurality of transistors BT and the emitter electrodes 6 each extend in the Y-axis direction Dy.
  • the transistor group Q1 is configured with three or more transistors BT.
  • the number and arrangement of the transistors BT are only examples, and can be changed as appropriate. At least one transistor BT should be provided. Further, although one transistor group Q1 is shown in FIG. 1 for easy understanding of the description, two or more transistor groups may be provided on the same semiconductor substrate 1. FIG.
  • the first rewiring layer 18 and the bumps 21 overlap the plurality of transistors BT of the transistor group Q1 in plan view.
  • the first rewiring layer 18 is electrically connected to the emitter wiring 11 through the first opening 17 provided in the first organic insulating film 16 .
  • the bumps 21 are electrically connected to the first rewiring layer 18 through the second openings 20 provided in the second organic insulating film 19 . Thereby, the bumps 21 are electrically connected to the plurality of transistors BT via the first rewiring layer 18 .
  • the bump 21 has an oval shape in plan view, extends in the X-axis direction Dx, and is provided along the arrangement direction of the plurality of transistors BT.
  • the bump 21 is provided to cover the entirety of the plurality of transistors BT arranged in the X-axis direction Dx.
  • the width of the bump 21 in the Y-axis direction Dy is larger than the width in the Y-axis direction Dy of the mesa structure including the base layers 4 of the plurality of transistors BT and the emitter electrode 6 .
  • FIG. 2 is a sectional view taken along line II-II' of FIG.
  • the transistor BT includes a sub-collector layer 2, a collector layer 3, a base layer 4, an emitter layer 5, an emitter electrode 6, a base electrode 7, and a collector electrode 8. and including.
  • a subcollector layer 2, a collector layer 3, a base layer 4, an emitter layer 5, and an emitter electrode 6 are laminated on a semiconductor substrate 1 in this order.
  • the base electrode 7 is provided on the base layer 4 and the collector electrode 8 is provided on the subcollector layer 2 .
  • the mesa structure of this embodiment is composed of one or more of the semiconductor layers (subcollector layer 2, collector layer 3, base layer 4, emitter layer 5) of the transistor BT.
  • the mesa structure is a collector mesa composed of collector layer 3 and base layer 4 .
  • the semiconductor substrate 1 is, for example, a semi-insulating GaAs (gallium arsenide) substrate.
  • a subcollector layer 2 is provided on the semiconductor substrate 1 .
  • the subcollector layer 2 is a high-concentration n-type GaAs layer and has a thickness of, for example, about 0.5 ⁇ m.
  • a collector layer 3 is provided on the subcollector layer 2 .
  • the collector layer 3 is an n-type GaAs layer and has a thickness of, for example, about 1 ⁇ m.
  • a base layer 4 is provided on the collector layer 3 .
  • the base layer 4 is a p-type GaAs layer and has a thickness of, for example, about 100 nm.
  • the emitter layer 5 is provided on the base layer 4 . Although illustration is omitted, the emitter layer 5 includes, for example, an intrinsic emitter layer from the base layer 4 side and an emitter mesa layer provided thereon.
  • the intrinsic emitter layer is an n-type InGaP (indium gallium phosphide) layer and has a thickness of, for example, 30 nm or more and 40 nm or less.
  • the emitter mesa layer is formed of a high concentration n-type GaAs layer and a high concentration n-type InGaAs layer.
  • the thickness of the high-concentration n-type GaAs layer and the high-concentration n-type InGaAs layer are each about 100 nm, for example.
  • the high-concentration n-type InGaAs layer of the emitter mesa layer is provided for ohmic contact with the emitter electrode 6 .
  • the base layer 4 and the collector layer 3 are etched after being epitaxially grown on the semiconductor substrate 1 to form a mesa structure.
  • a mesa structure may be formed on the base layer 4 and the collector layer 3 without removing the lower part of the collector layer 3 .
  • the collector electrode 8 is provided on the subcollector layer 2 in contact with the subcollector layer 2 .
  • the collector electrode 8 is arranged adjacent to, for example, the mesa structure (base layer 4 and collector layer 3) in the X-axis direction Dx.
  • the collector electrode 8 has a laminated film in which, for example, an AuGe (gold germanium) film, a Ni (nickel) film, and an Au (gold) film are laminated in this order.
  • the thickness of the AuGe film is, for example, 60 nm.
  • the thickness of the Ni film is, for example, 10 nm.
  • the film thickness of the Au film is, for example, 200 nm.
  • the base electrode 7 is provided on the base layer 4 in contact with the base layer 4 .
  • the base electrode 7 is a laminated film in which a Ti film, a Pt film, and an Au film are laminated in this order.
  • the film thickness of the Ti film is, for example, 50 nm.
  • the film thickness of the Pt film is, for example, 50 nm.
  • the film thickness of the Au film is, for example, 200 nm.
  • the emitter electrode 6 is provided on the emitter layer 5 in contact with the emitter layer 5 .
  • the emitter electrode 6 is a Ti (titanium) film.
  • the film thickness of the Ti film is, for example, 50 nm.
  • An isolation region 2 b is provided adjacent to the subcollector layer 2 on the semiconductor substrate 1 .
  • the isolation region 2b is insulated by an ion implantation technique.
  • the isolation region 2b insulates between elements (between a plurality of transistors BT).
  • the inorganic insulating film 9 is provided on the subcollector layer 2 and the isolation region 2b, covering the plurality of transistors BT except for a part of the emitter electrode 6.
  • the inorganic insulating film 9 is, for example, a SiN (silicon nitride) layer.
  • the inorganic insulating film 9 may be a single layer, or may be laminated with a plurality of nitride layers or oxide layers.
  • the emitter wiring 11 is provided on the inorganic insulating film 9 covering the plurality of transistors BT.
  • An emitter opening 10 is provided in a region of the inorganic insulating film 9 overlapping the emitter electrode 6 in plan view, and the emitter wiring 11 is electrically connected to the emitter electrode 6 at the emitter opening 10 .
  • a first organic insulating film 16 is provided on the inorganic insulating film 9 to cover part of the emitter wiring 11 .
  • the first organic insulating film 16 is an organic protective film using an organic material such as polyimide or BCB.
  • a first opening 17 is provided in the first organic insulating film 16 in a region overlapping with the plurality of transistors BT, the emitter electrode 6 and the emitter wiring 11 in plan view.
  • the first rewiring layer 18 is provided on the first organic insulating film 16 , overlaps with the plurality of transistors BT, and is electrically connected to the emitter wiring 11 through the first openings 17 .
  • the second organic insulating film 19 is provided on the first organic insulating film 16 to cover part of the first rewiring layer 18 .
  • a second opening 20 is provided in a region of the second organic insulating film 19 that overlaps the first rewiring layer 18 in plan view.
  • the bump 21 is provided in a region overlapping the second opening 20 and electrically connected to the first rewiring layer 18 through the second opening 20 . With such a configuration, the bumps 21 are electrically connected to the emitter electrodes 6 of the transistors BT through the first openings 17 and the second openings 20 .
  • the bumps 21 are pillar bumps, and copper (Cu) is used, for example.
  • the bumps 21 are made of a low-resistance metal material such as aluminum (Al) or gold (Au) other than Cu.
  • a metal film such as a diffusion prevention layer or a plating seed layer may be provided between the bumps 21 and the first rewiring layer 18 .
  • Materials such as nickel (Ni), titanium (Ti), tungsten (W), and chromium (Cr) are used for the diffusion prevention layer and seed layer.
  • the width R1 of the first opening 17 of the first organic insulating film 16 in the X-axis direction Dx is larger than the width R2 of the second opening 20 of the second organic insulating film 19 in the X-axis direction Dx.
  • the inner peripheral surface of the second organic insulating film 19 forming the second opening 20 is formed in a region inside the inner peripheral surface of the first organic insulating film 16 forming the first opening 17 . (See FIG. 1).
  • the width R1 of the first opening 17 of the first organic insulating film 16 is the position where the inner peripheral surface of the first organic insulating film 16 forming the first opening 17 and the emitter wiring 11 on the semiconductor substrate 1 side are in contact. , in the X-axis direction Dx.
  • the width R2 of the second opening 20 of the second organic insulating film 19 is determined by the inner peripheral surface of the second organic insulating film 19 forming the second opening 20 and the first rewiring layer 18 on the semiconductor substrate 1 side. is the distance in the X-axis direction Dx of the contact position.
  • the width of the bump 21 provided on the second organic insulating film 19 in the X-axis direction Dx is larger than the width R1 of the first opening 17 and the width R2 of the second opening 20 .
  • the bump 21 contacts the first rewiring layer 18 at the bottom of the second opening 20 .
  • the width R1 of the first opening 17 is formed larger than the width R2 of the second opening 20.
  • the width (width R2 of the second opening 20) in the X-axis direction Dx of the portion of the second opening 20 where the bump 21 and the first rewiring layer 18 are in contact is larger than the width R1 of the first opening 17. small.
  • the width of the bump 21 in the X-axis direction Dx on the second organic insulating film 19 is not particularly limited, and can be changed as appropriate.
  • the width of the bump 21 in the X-axis direction Dx may be larger than the width R2 of the second opening 20 and smaller than the width R1 of the first opening 17 .
  • the semiconductor device 100 of this embodiment includes a semiconductor substrate 1, at least one transistor BT provided on the semiconductor substrate 1 and including a plurality of semiconductor layers, and an emitter wiring provided on the transistor BT. 11 (wiring), a first organic insulating film 16 (first insulating film) provided with a first opening 17 in a region overlapping with the transistor BT and the emitter wiring 11, and provided on the first organic insulating film 16, A first rewiring layer 18 overlapping with at least one transistor BT in plan view and electrically connected to the emitter wiring 11 through the first opening 17, the first rewiring layer 18 and the first organic insulating film 16 and through a second organic insulating film 19 (second insulating film) provided with a second opening 20 in a region overlapping at least a part of the first rewiring layer 18 and the second opening 20 and a bump 21 electrically connected to the first rewiring layer 18 .
  • first organic insulating film 16 first insulating film
  • a first rewiring layer 18 overlapping with at least one
  • the width R1 of the first opening 17 of the first organic insulating film 16 in the X-axis direction Dx parallel to the semiconductor substrate 1 is larger than the width R2 of the second opening 20 of the second organic insulating film 19 in the X-axis direction Dx. big.
  • the bumps 21 are provided so as to cover the entire region of the mesa structure of the plurality of transistors BT, and heat dissipation can be improved. Thermal stress generated when the semiconductor device 100 is mounted on an external substrate such as a printed wiring board is applied from the bumps 21 to the mesa structure of the plurality of transistors BT.
  • the width R1 of the first opening 17 of the first organic insulating film 16 in the X-axis direction Dx is larger than the width R2 of the second opening 20 of the second organic insulating film 19 in the X-axis direction Dx. It is formed.
  • the stress transmitted from the bump 21 to the first rewiring layer 18 is , are dispersed in the region overlapping the first opening 17 of the first redistribution layer 18 . That is, concentration of stress on the outer edge side of the first rewiring layer 18 (the portion of the first rewiring layer 18 in contact with the inner peripheral surface of the first organic insulating film 16) is suppressed. As a result, in this embodiment, thermal stress applied to the mesa structure of the transistor BT from the bump 21 via the first rewiring layer 18 can be suppressed.
  • FIG. 3 is a table for explaining the relationship between the opening width and the presence or absence of defects in the semiconductor devices according to the example and the comparative example.
  • Comparative Examples 1 and 2 are semiconductor devices each having a configuration in which the width R1 of the first opening 17 is smaller than the width R2 of the second opening 20 .
  • the width R1 of the first opening 17 is 49 ⁇ m
  • the width R2 of the second opening 20 is 69 ⁇ m.
  • the width R1 of the first opening 17 is 61 ⁇ m and the width R2 of the second opening 20 is 69 ⁇ m.
  • the width R1 of the first opening 17 is 73 ⁇ m and the width R2 of the second opening 20 is 69 ⁇ m.
  • the width R1 of the first opening 17 is formed smaller than the width R2 of the second opening 20, that is, the outer edge side of the bump 21 provided in the second opening 20 (A portion of the bump 21 in contact with the inner peripheral surface of the second organic insulating film 19 ) is located outside the first opening 17 .
  • the stress from the bump 21 mainly travels through hard materials and reaches the mesa structure of the transistor BT.
  • the Young's modulus of the first organic insulating film 16 and the second organic insulating film 19 is smaller than that of the metal material of the first rewiring layer 18 and the like, most of the thermal stress is applied to the first rewiring layer 18 and the emitter wiring. It concentrates on the wiring point of 11 and propagates to the mesa structure of the transistor BT.
  • the stress from the bump 21 is concentrated on the outer edge side of the bump 21 (the portion of the bump 21 in contact with the inner peripheral surface of the second organic insulating film 19), and furthermore, the stress on the outer edge side of the first rewiring layer 18 (the 1 rewiring layer 18 in contact with the inner peripheral surface of the first organic insulating film 16) and propagates to the transistor BT side.
  • thermal stress concentrates on a portion of the mesa structure of the transistor BT, and cracks occur in the mesa structure of the transistor BT.
  • the semiconductor device 100 of the embodiment has no cracks in the mesa structure of the transistor BT.
  • the semiconductor device 100 of the embodiment has a configuration in which the width R1 of the first opening 17 is formed larger than the width R2 of the second opening 20.
  • the stress transmitted from the bumps 21 to the first rewiring layer 18 is reduced. are dispersed in the region overlapping the first opening 17 of the first redistribution layer 18 .
  • the semiconductor device 100 of the example can suppress the concentration of stress as described in the comparative examples 1 and 2, and can suppress the occurrence of cracks in the mesa structure of the transistor BT.
  • FIG. 4 is a cross-sectional view of the semiconductor device according to the second embodiment.
  • the collector electrode 8, the emitter wiring 11 and the first rewiring layer 18 are arranged in the direction perpendicular to the semiconductor substrate 1.
  • a configuration having a superimposed organic insulating film 12 provided therebetween will be described.
  • the configurations of the plurality of transistors BT, the first openings 17 in the first organic insulating film 16, the second openings 20 in the second organic insulating film 19, and the like are the same as those in the first embodiment, and repeated description will be omitted.
  • the overlapping organic insulating film 12 is provided so as to overlap the collector electrode 8 of the transistor BT.
  • An inorganic insulating film 9 , a superimposed organic insulating film 12 , an emitter wiring 11 and a first rewiring layer 18 are laminated in this order on the collector electrode 8 .
  • the superimposed organic insulating film 12 is provided, insulation between the collector and the emitter can be ensured.
  • the superimposed organic insulating film 12 is provided in a region that does not overlap with the mesa structure composed of the collector layer 3, the base layer 4 and the emitter layer 5 in plan view. In this case, focusing on the emitter wiring 11 and the superimposed organic insulating film 12, since the superimposed organic insulating film 12 has a smaller Young's modulus than the emitter wiring 11, most of the thermal stress is in the portion where the superimposed organic insulating film 12 is not provided. A large stress may be transmitted to the mesa structure of the transistor BT, concentrating on the emitter wiring 11 .
  • the width R1 of the first opening 17 of the first organic insulating film 16 in the X-axis direction Dx is larger than the width R2 of the second opening 20 of the second organic insulating film 19 in the X-axis direction Dx. big. Therefore, concentration of stress transmitted from the bump 21 to the emitter wiring 11 via the first rewiring layer 18 is suppressed. Therefore, even with the structure in which the superimposed organic insulating film 12 is provided on the collector electrode 8, the stress concentration on the mesa structure of the transistor BT can be suppressed, and the occurrence of cracks can be suppressed.
  • the shape, thickness, etc. of the superimposed organic insulating film 12 shown in FIG. 4 are merely schematic representations, and may be changed as appropriate according to the configuration of the collector electrode 8 and the emitter wiring 11 and the required insulation characteristics. can do.
  • FIG. 5 is a cross-sectional view of a semiconductor device according to the third embodiment.
  • the semiconductor device 100B has a third organic insulating film 26 and a second rewiring layer 28. do.
  • the third organic insulating film 26 (third insulating film) is provided between the first organic insulating film 16 and the second organic insulating film 19, and comprises at least the first rewiring layer.
  • a third opening 27 is provided in a region overlapping with a part of 18 .
  • a second rewiring layer 28 is provided on the third organic insulating film 26 . More specifically, the second rewiring layer 28 is provided between the first rewiring layer 18 and the bumps 21 and electrically connected to the first rewiring layer 18 through the third openings 27 .
  • the second organic insulating film 19 is provided on the third organic insulating film 26 to cover the second rewiring layer 28 .
  • the second opening 20 in the second organic insulating film 19 is provided in a region that overlaps at least part of the second rewiring layer 28 .
  • the width R3 of the third opening 27 of the third organic insulating film 26 in the X-axis direction Dx is larger than the width R2 of the second opening 20 of the second organic insulating film 19 in the X-axis direction Dx. Also, the width R3 of the third opening 27 of the third organic insulating film 26 in the X-axis direction Dx is larger than the width R1 of the first opening 17 of the first organic insulating film 16 in the X-axis direction Dx. Further, similarly to the first and second embodiments, the width R1 of the first opening 17 of the first organic insulating film 16 in the X-axis direction Dx is equal to the width of the second organic insulating film 19 in the X-axis direction Dx. It is larger than the width R2 of the second opening 20 .
  • the third opening 27 is arranged between the second opening 20 and the first opening 17, and the width R3 of the third opening 27 is equal to the width R1 of the first opening 17 and It is larger than the width R2 of the second opening 20 .
  • the stress transmitted from the bumps 21 to the second rewiring layer 28 is dispersed in the region of the second rewiring layer 28 that overlaps the second opening 20 . That is, concentration of stress on the outer edge side of the second rewiring layer 28 (the portion of the second rewiring layer 28 in contact with the inner peripheral surface of the third organic insulating film 26) is suppressed. Since the concentration of stress on the outer edge side of the second rewiring layer 28 is suppressed, the stress transmitted from the second rewiring layer 28 to the first rewiring layer 18 is dispersed in the region overlapping the first opening 17. be done.
  • concentration of stress on the outer edge side of the first rewiring layer 18 (the portion of the first rewiring layer 18 in contact with the inner peripheral surface of the first organic insulating film 16) is suppressed.
  • the thermal stress applied to the mesa structure of the transistor BT from the bump 21 via the second rewiring layer 28 and the first rewiring layer 18 can be suppressed.
  • the insulating film at a position close to the transistor BT in the direction perpendicular to the semiconductor substrate 1 .
  • the width R1 of the first opening 17 of the first organic insulating film 16 larger than the width R2 of the second opening 20 of the second organic insulating film 19 provided at the farthest position from the transistor BT, Thermal stress applied from the bumps 21 to the mesa structure of the transistor BT can be suppressed.
  • the width R3 of the third opening 27 of the second rewiring layer 28 is not limited to being larger than the width R1 of the first opening 17 and the width R2 of the second opening 20. can be increased.
  • FIG. 6 is an explanatory diagram of a semiconductor device according to a modification of the third embodiment.
  • the width R3 of the third opening 27 is equal to the width R1 of the first opening 17 and the width R1 of the second opening 20 A configuration formed to be smaller than the width R2 of the will be described.
  • the width R3 of the third opening 27 of the third organic insulating film 26 in the X-axis direction Dx is smaller than the width R2 of the second opening 20 of the second organic insulating film 19 in the X-axis direction Dx. Also, the width R3 of the third opening 27 of the third organic insulating film 26 in the X-axis direction Dx is smaller than the width R1 of the first opening 17 of the first organic insulating film 16 in the X-axis direction Dx. Further, similarly to the first and second embodiments, the width R1 of the first opening 17 of the first organic insulating film 16 in the X-axis direction Dx is equal to the width of the second organic insulating film 19 in the X-axis direction Dx. It is larger than the width R2 of the second opening 20 .
  • the third opening 27 is arranged between the second opening 20 and the first opening 17, and the width R3 of the third opening 27 is equal to the width R1 of the first opening 17 and It is smaller than the width R2 of the second opening 20 .
  • the stress transmitted from the bumps 21 to the second rewiring layer 28 is applied to the outer edge side of the second rewiring layer 28 (the portion of the second rewiring layer 28 in contact with the inner peripheral surface of the third organic insulating film 26). concentrate on Even when stress concentrates on the outer edge side of the second rewiring layer 28 (the portion of the second rewiring layer 28 in contact with the inner peripheral surface of the third organic insulating film 26), the second rewiring layer 28
  • the stress transmitted from the to the first rewiring layer 18 is dispersed in the region overlapping the first opening 17 .
  • the outer edge side of the first rewiring layer 18 (the portion of the first rewiring layer 18 in contact with the inner peripheral surface of the first organic insulating film 16). ) is suppressed.
  • the thermal stress applied to the mesa structure of the transistor BT from the bump 21 via the second rewiring layer 28 and the first rewiring layer 18 can be suppressed.
  • width R3 of the third opening 27 is not limited to being smaller than the width R1 of the first opening 17 and the width R2 of the second opening 20, and the width R1 of the first opening 17 and the width R2 of the second opening 20 The size may be between That is, the width R3 of the third opening 27 may be larger than the width R2 of the second opening 20, and the width R1 of the first opening 17 may be larger than the width R3 of the third opening 27.
  • FIG. 7 is an explanatory diagram for explaining the manufacturing process of the semiconductor device.
  • a plurality of transistors BT and respective insulating films are provided on a semiconductor substrate 1, and an emitter wiring 11 is formed covering the plurality of transistors BT and respective insulating films (step ST11).
  • the emitter wiring 11 is provided covering the inorganic insulating film 9 and the emitter openings 10 and is in contact with the emitter electrodes 6 of the plurality of transistors BT at the emitter openings 10 .
  • a metal material having good conductivity is used for the emitter wiring 11 .
  • a first organic insulating film 16 is formed to cover the emitter wiring 11, and a first opening 17 is provided in a region overlapping with the emitter wiring 11 (step ST12).
  • the first opening 17 is formed by patterning the first organic insulating film 16 by photolithography, etching, or the like.
  • the first rewiring layer 18 is provided on the first organic insulating film 16 to cover the first opening 17 of the first organic insulating film 16 (step ST13).
  • the first rewiring layer 18 contacts the emitter wiring 11 at the bottom of the first opening 17 .
  • a second organic insulating film 19 is formed covering the first rewiring layer 18 and the first organic insulating film 16, and a region of the second organic insulating film 19 overlapping with a part of the first rewiring layer 18 is A second opening 20 is formed (step ST14).
  • the width of the second opening 20 in the second organic insulating film 19 is formed smaller than the width of the first opening 17 in the first organic insulating film 16 .
  • bumps 21 are formed on the second organic insulating film 19 and the first rewiring layer 18 (step ST15).
  • the bumps 21 may be formed by any process, but are formed by plating, for example.
  • a power feeding film (not shown) is provided on the second organic insulating film 19 and the first rewiring layer 18 as a base layer for the bumps 21 .
  • the manufacturing process shown in FIG. 7 is merely an example, and can be changed as appropriate.
  • the rewiring layer and the organic insulating film may be formed in multiple layers by repeating steps ST12 and ST13.
  • the semiconductor device in which one bump 21 is provided so as to overlap a plurality of transistors BT has been described as an example, but the present invention is not limited to this.
  • a semiconductor device in which one bump is formed so as to overlap one transistor may be used.
  • the pillar bumps have been described as examples of the bumps, other than the pillar bumps, for example, solder bumps and stud bumps may be used.
  • each configuration shown in each embodiment described above is merely examples, and may be changed as appropriate. Materials and thicknesses of the subcollector layer 2, the collector layer 3, the base layer 4, the emitter layer 5 and various wirings may be changed as appropriate.

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PCT/JP2022/046949 2022-01-07 2022-12-20 半導体装置 Ceased WO2023132233A1 (ja)

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2020088153A (ja) * 2018-11-26 2020-06-04 株式会社村田製作所 半導体装置
JP2021197473A (ja) * 2020-06-16 2021-12-27 株式会社村田製作所 半導体装置
JP2021197474A (ja) * 2020-06-16 2021-12-27 株式会社村田製作所 半導体装置

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2020088153A (ja) * 2018-11-26 2020-06-04 株式会社村田製作所 半導体装置
JP2021197473A (ja) * 2020-06-16 2021-12-27 株式会社村田製作所 半導体装置
JP2021197474A (ja) * 2020-06-16 2021-12-27 株式会社村田製作所 半導体装置

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