WO2023132231A1 - Dispositif à semi-conducteurs - Google Patents

Dispositif à semi-conducteurs Download PDF

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Publication number
WO2023132231A1
WO2023132231A1 PCT/JP2022/046893 JP2022046893W WO2023132231A1 WO 2023132231 A1 WO2023132231 A1 WO 2023132231A1 JP 2022046893 W JP2022046893 W JP 2022046893W WO 2023132231 A1 WO2023132231 A1 WO 2023132231A1
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Prior art keywords
insulating film
organic insulating
opening
width
bump
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PCT/JP2022/046893
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English (en)
Japanese (ja)
Inventor
真理 佐治
敦 黒川
雅博 柴田
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株式会社村田製作所
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Priority to JP2023572410A priority Critical patent/JPWO2023132231A1/ja
Publication of WO2023132231A1 publication Critical patent/WO2023132231A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8222—Bipolar technology
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/082—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including bipolar components only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66234—Bipolar junction transistors [BJT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/73—Bipolar junction transistors
    • H01L29/737—Hetero-junction transistors

Definitions

  • the present invention relates to semiconductor devices.
  • Patent Document 1 describes a semiconductor device including a heterojunction bipolar transistor.
  • a semiconductor device described in Patent Document 1 has a bump provided right above a transistor. The bump is electrically connected to the emitter electrode of the transistor through an opening in an organic insulating film (resin film) covering the transistor.
  • the heat radiation performance is improved (that is, the thermal resistance is reduced), but stress from the bumps may cause cracks in the mesa structure and other problems. Reliability may decrease.
  • An object of the present invention is to provide a semiconductor device capable of suppressing stress generated in a transistor.
  • a semiconductor device includes a semiconductor substrate, at least one transistor provided on the semiconductor substrate and including a plurality of semiconductor layers, an electrode provided on the transistor, and a first transistor perpendicular to the semiconductor substrate.
  • an organic insulating film provided with an opening in a region overlapping with the transistor and the electrode; a bump electrically connected to the electrode through an opening, wherein the width of the bump in a second direction parallel to the semiconductor substrate is equal to the width of the opening in the organic insulating film in the second direction. less than width.
  • a semiconductor device includes a semiconductor substrate, at least one transistor provided on the semiconductor substrate and including a plurality of semiconductor layers, an electrode provided on the transistor, and a first transistor perpendicular to the semiconductor substrate.
  • an organic insulating film provided with an opening in a region overlapping with the transistor and the electrode; a bump electrically connected to the electrode through an opening, wherein the width of the bump in a second direction parallel to the semiconductor substrate is equal to the width of the opening in the organic insulating film in the second direction. Equal to width.
  • FIG. 1 is a plan view of the semiconductor device according to the first embodiment.
  • FIG. 2 is a sectional view taken along line II-II' of FIG.
  • FIG. 3 is a cross-sectional view of the semiconductor device according to the second embodiment.
  • FIG. 4 is a cross-sectional view of the semiconductor device according to the third embodiment.
  • FIG. 5 is a cross-sectional view of a semiconductor device according to a fourth embodiment.
  • FIG. 6 is an explanatory diagram for explaining the manufacturing process of the semiconductor device according to the fourth embodiment.
  • FIG. 7 is a cross-sectional view of the semiconductor device according to the fifth embodiment.
  • FIG. 8 is a cross-sectional view of a semiconductor device according to a modification of the fifth embodiment.
  • FIG. 9 is an explanatory diagram for explaining the manufacturing process of the semiconductor device according to the fifth embodiment.
  • FIG. 10 is a cross-sectional view of a semiconductor device according to the sixth embodiment.
  • FIG. 11 is a cross-sectional view of a semiconductor device according to the seventh embodiment.
  • FIG. 1 is a plan view of the semiconductor device according to the first embodiment. Note that FIG. 1 omits the detailed configuration of each transistor BT, and schematically shows the arrangement relationship between the mesa structure including the base layer 4 and the emitter electrode 6 of each transistor.
  • the semiconductor device 100 has a semiconductor substrate 1, a transistor group Q1, a first organic insulating film 16, and bumps 21.
  • one direction in the plane parallel to the surface of the semiconductor substrate 1 is defined as the X-axis direction Dx.
  • a direction orthogonal to the X-axis direction Dx in a plane parallel to the surface of the semiconductor substrate 1 is defined as a Y-axis direction Dy.
  • a direction perpendicular to each of the X-axis direction Dx and the Y-axis direction Dy is defined as a Z-axis direction Dz.
  • a Z-axis direction Dz is a direction perpendicular to the surface of the semiconductor substrate 1 .
  • the Z-axis direction Dz is an example of the "first direction”
  • the X-axis direction Dx and the Y-axis direction Dy are examples of the "second direction”.
  • a planar view indicates a positional relationship when viewed from the Z-axis direction Dz.
  • the transistor group Q ⁇ b>1 is provided on the surface of the semiconductor substrate 1 .
  • the transistor group Q1 has a plurality of transistors BT.
  • the transistor BT is a heterojunction bipolar transistor (HBT: Heterojunction Bipolar Transistor).
  • the transistor BT is also called a unit transistor, and the unit transistor is defined as the smallest transistor forming the transistor group Q1.
  • Transistors BT are electrically connected in parallel to form a transistor group Q1.
  • a plurality of transistors BT in the transistor group Q1 are arranged side by side in the X-axis direction Dx.
  • the mesa structures including the base layers 4 of the plurality of transistors BT and the emitter electrodes 6 each extend in the Y-axis direction Dy.
  • the transistor group Q1 is configured with three or more transistors BT.
  • the number and arrangement of the transistors BT are only examples, and can be changed as appropriate. At least one transistor BT should be provided. Further, although one transistor group Q1 is shown in FIG. 1 for easy understanding of the description, two or more transistor groups may be provided on the same semiconductor substrate 1. FIG.
  • the bumps 21 overlap the plurality of transistors BT of the transistor group Q1 in plan view.
  • the bumps 21 are electrically connected to the plurality of transistors BT through openings 17 provided in the first organic insulating film 16 .
  • the bump 21 has an oval shape in plan view, extends in the X-axis direction Dx, and is provided along the arrangement direction of the plurality of transistors BT.
  • the bump 21 is provided to cover the entirety of the plurality of transistors BT arranged in the X-axis direction Dx.
  • the width of the bump 21 in the Y-axis direction Dy is larger than the width in the Y-axis direction Dy of the mesa structure including the base layers 4 of the plurality of transistors BT and the emitter electrode 6 .
  • a part of the bump 21 is provided inside the opening 17 provided in the first organic insulating film 16 in plan view. That is, the area of a part of bump 21 is smaller than the area of opening 17 , and the outer circumference of bump 21 is separated from the inner circumference of opening 17 .
  • a detailed relationship between the bumps 21 and the openings 17 provided in the first organic insulating film 16 will be described later.
  • FIG. 2 is a sectional view taken along line II-II' of FIG.
  • transistor BT includes subcollector layer 2 , collector layer 3 , base layer 4 , emitter layer 5 , and emitter electrode 6 .
  • a subcollector layer 2 a collector layer 3, a base layer 4, an emitter layer 5, and an emitter electrode 6 are laminated on a semiconductor substrate 1 in this order.
  • the subcollector layer 2 is provided with a collector electrode
  • the base layer 4 is provided with a base electrode.
  • the mesa structure of this embodiment is composed of one or more of the semiconductor layers (subcollector layer 2, collector layer 3, base layer 4, emitter layer 5) of the transistor BT.
  • the mesa structure is a collector mesa composed of collector layer 3 and base layer 4 .
  • the semiconductor substrate 1 is, for example, a semi-insulating GaAs (gallium arsenide) substrate.
  • a subcollector layer 2 is provided on the semiconductor substrate 1 .
  • the subcollector layer 2 is a high-concentration n-type GaAs layer and has a thickness of, for example, about 0.5 ⁇ m.
  • a collector layer 3 is provided on the subcollector layer 2 .
  • the collector layer 3 is an n-type GaAs layer and has a thickness of, for example, about 1 ⁇ m.
  • a base layer 4 is provided on the collector layer 3 .
  • the base layer 4 is a p-type GaAs layer and has a thickness of, for example, about 100 nm.
  • the emitter layer 5 is provided on the base layer 4 . Although illustration is omitted, the emitter layer 5 includes, for example, an intrinsic emitter layer from the base layer 4 side and an emitter mesa layer provided thereon.
  • the intrinsic emitter layer is an n-type InGaP (indium gallium phosphide) layer and has a thickness of, for example, 30 nm or more and 40 nm or less.
  • the emitter mesa layer is formed of a high concentration n-type GaAs layer and a high concentration n-type InGaAs layer.
  • the thickness of the high-concentration n-type GaAs layer and the high-concentration n-type InGaAs layer are each about 100 nm, for example.
  • the high-concentration n-type InGaAs layer of the emitter mesa layer is provided for ohmic contact with the emitter electrode 6 .
  • the base layer 4 and the collector layer 3 are etched after being epitaxially grown on the semiconductor substrate 1 to form a mesa structure.
  • a mesa structure may be formed on the base layer 4 and the collector layer 3 without removing the lower part of the collector layer 3 .
  • a collector electrode (not shown) is provided on the subcollector layer 2 in contact with the subcollector layer 2 .
  • the collector electrode is arranged adjacent to, for example, the mesa structure (base layer 4 and collector layer 3) in the X-axis direction Dx.
  • the collector electrode has a laminated film in which, for example, an AuGe (gold germanium) film, a Ni (nickel) film, and an Au (gold) film are laminated in this order.
  • the thickness of the AuGe film is, for example, 60 nm.
  • the thickness of the Ni film is, for example, 10 nm.
  • the film thickness of the Au film is, for example, 200 nm.
  • a base electrode (not shown) is provided on the base layer 4 in contact with the base layer 4 .
  • the base electrode is a laminated film in which a Ti film, a Pt film, and an Au film are laminated in this order.
  • the film thickness of the Ti film is, for example, 50 nm.
  • the film thickness of the Pt film is, for example, 50 nm.
  • the film thickness of the Au film is, for example, 200 nm.
  • the emitter electrode 6 is provided on the emitter layer 5 in contact with the emitter layer 5 .
  • Emitter electrode 6 is, for example, a Ti (titanium) film.
  • the film thickness of the Ti film is, for example, 50 nm.
  • An isolation region 2 b is provided adjacent to the subcollector layer 2 on the semiconductor substrate 1 .
  • the isolation region 2b is insulated by an ion implantation technique.
  • the isolation region 2b insulates between elements (between a plurality of transistors BT).
  • the first insulating film 9 is provided on the subcollector layer 2 and the isolation region 2b, covering the plurality of transistors BT except for part of the emitter electrode 6. As shown in FIG.
  • the first insulating film 9 is, for example, a SiN (silicon nitride) layer.
  • the first insulating film 9 may be a single layer, or may be laminated with a plurality of nitride layers or oxide layers.
  • An emitter wiring 12 made of metal is layered on the first insulating film 9 . Emitter wiring 12 is provided between a plurality of transistors BT.
  • a first insulating film opening 10 is provided in a region of the first insulating film 9 overlapping the emitter electrode 6 when viewed in plan in a direction perpendicular to the semiconductor substrate 1 . It is electrically connected to emitter electrode 6 .
  • An inorganic insulating film 14 (passivation film) is provided to partially cover the emitter wiring 12, and a first organic insulating film 16 is provided on the inorganic insulating film 14.
  • the inorganic insulating film 14 is an inorganic protective film using an inorganic material containing at least one of SiN and SiON (silicon oxynitride), for example. Note that the inorganic insulating film 14 can be omitted as necessary.
  • the first organic insulating film 16 is an organic protective film using an organic material such as polyimide or BCB.
  • the inorganic insulating film 14 and the first organic insulating film 16 are provided with openings 15 and 17 in regions overlapping with the plurality of transistors BT and the emitter electrode 6, respectively.
  • the bumps 21 are formed in regions overlapping the openings 15 of the inorganic insulating film 14 and the openings 17 of the first organic insulating film 16, and are electrically connected to the emitter electrodes 6 of the plurality of transistors BT through the openings 15 and 17. .
  • the bumps 21 are pillar bumps, and copper (Cu) is used, for example.
  • the bumps 21 are made of a low-resistance metal material such as aluminum (Al) or gold (Au) other than Cu.
  • a metal film such as a diffusion prevention layer or a plating seed layer may be provided between the bump 21 and the emitter wiring 12 .
  • Materials such as nickel (Ni), titanium (Ti), tungsten (W), and chromium (Cr) are used for the diffusion prevention layer and seed layer.
  • the width R1 of the bump 21 in the X-axis direction Dx is smaller than the width R2 of the opening 17 of the first organic insulating film 16 in the X-axis direction Dx.
  • the outer peripheral surface of the bump 21 faces the inner peripheral surface of the opening 17 of the first organic insulating film 16 with a space therebetween.
  • the bump 21 is formed with a constant width R1 from the inside of the opening 17 of the first organic insulating film 16 to the upper side of the first organic insulating film 16 .
  • the width R1 of the bump 21 in the X-axis direction Dx is equal to the width of the opening 15 of the inorganic insulating film 14 in the X-axis direction Dx.
  • the lower end side of the outer peripheral surface of the bump 21 is in contact with the inner peripheral surface of the opening 15 of the inorganic insulating film 14 . That is, the inorganic insulating film 14 covers the surface of the emitter wiring 12 between the bump 21 and the first organic insulating film 16 .
  • the width R1 of the bump 21 in the X-axis direction Dx may be an arbitrary width among the varying widths.
  • the width of the opening 17 in the first organic insulating film 16 in the X-axis direction Dx means the width in the X-axis direction Dx connecting the mutually facing inner peripheral surfaces of the first organic insulating film 16 forming the opening 17. point to distance.
  • the gap between the outer peripheral surface of the bump 21 and the inner peripheral surface of the opening 17 of the first organic insulating film 16 may be filled with, for example, an inorganic insulating film or a metal film.
  • the width of the bump 21 in the Y-axis direction Dy is smaller than the width of the opening 17 of the first organic insulating film 16 in the Y-axis direction Dy.
  • the outer peripheral surface of the bump 21 faces the inner peripheral surface of the opening 17 of the first organic insulating film 16 while being separated therefrom.
  • the semiconductor device 100 of this embodiment includes a semiconductor substrate 1, at least one transistor BT provided on the semiconductor substrate 1 and including a plurality of semiconductor layers, and an electrode (for example, an emitter) provided on the transistor BT. an electrode 6), a first organic insulating film 16 provided with an opening 17 in a region overlapping with the transistor BT and the electrode, and at least one transistor BT overlapping with the electrode through the opening 17 of the first organic insulating film 16. and a bump 21 to be electrically connected.
  • a width R1 of the bump 21 in the X-axis direction Dx parallel to the semiconductor substrate 1 is smaller than a width R2 of the opening 17 of the first organic insulating film 16 in the X-axis direction Dx.
  • the bumps 21 are provided so as to cover the entire region of the mesa structure of the plurality of transistors BT, and heat dissipation can be improved.
  • Thermal stress generated when the semiconductor device 100 is mounted on an external substrate such as a printed wiring board is applied from the bumps 21 to the mesa structure of the plurality of transistors BT.
  • the width R1 of the bump 21 is formed smaller than the width R2 of the opening 17 of the first organic insulating film 16.
  • the width R1 of the bump 21 is formed larger than the width R2 of the opening 17 of the first organic insulating film 16, and the bump 21 is partially provided on the first organic insulating film 16 as well.
  • the thermal stress applied from the bump 21 to the mesa structure of the transistor BT can be suppressed.
  • the bump 21 is not provided in the region overlapping the inner peripheral surface of the opening 17 of the first organic insulating film 16, the bump 21 is partially provided on the first organic insulating film 16 as well. Compared to , concentration of the thermal stress from the bump 21 in the vicinity of the opening 17 of the first organic insulating film 16 can be suppressed. As a result, it is possible to suppress the thermal stress from concentrating on a part of the mesa structure of the transistor BT, and to suppress the occurrence of cracks in the mesa structure of the transistor BT.
  • the transistors BT and the bumps 21 shown in FIGS. 1 and 2 are merely schematic representations, and their shapes and the like can be changed as appropriate.
  • the bumps 21 are shown to have a rectangular cross-section, they may have other shapes such as having a curved upper surface.
  • FIG. 3 is a cross-sectional view of the semiconductor device according to the second embodiment.
  • the width R3 of the opening 15 of the inorganic insulating film 14 in the X-axis direction Dx is smaller than the width R1 of the bump 21. do.
  • the configuration of the transistor group Q1 (plurality of transistors BT) is the same as that of the first embodiment, and repeated description will be omitted.
  • the inorganic insulating film 14 is provided covering the entire surface of the emitter wiring 12 between the bump 21 and the first organic insulating film 16 . Therefore, the semiconductor device 100A can suppress penetration of moisture from the bump 21 side, and is excellent in moisture resistance.
  • the inorganic insulating film 14 is made of an inorganic material as described above, and has a Young's modulus greater than that of the first organic insulating film 16 .
  • the inorganic insulating film 14 easily transmits the stress from the bump 21 to the transistor BT side, even if the width R3 of the opening 15 of the inorganic insulating film 14 is formed to be small, the concentration of stress occurs. can be suppressed.
  • FIG. 4 is a cross-sectional view of the semiconductor device according to the third embodiment.
  • the width R1 of the bump 21 in the X-axis direction Dx is the width of the first organic insulating film in the X-axis direction Dx.
  • a configuration equal to the width R2 of the 16 openings 17 will be described.
  • the outer peripheral surface of the bump 21 is in contact with the inner peripheral surface of the opening 17 of the first organic insulating film 16 .
  • the bump 21 has a constant width R1 from the inside of the opening 17 of the first organic insulating film 16 to the upper side of the first organic insulating film 16 .
  • the opening 15 of the inorganic insulating film 14 is formed with a width equal to the width R2 of the opening 17 of the first organic insulating film 16 .
  • the opening 15 of the inorganic insulating film 14 may be formed to be smaller than the width R2 of the opening 17 of the first organic insulating film 16 as in the second embodiment.
  • the bumps 21 are not provided on the first organic insulating film 16 outside the openings 17 of the first organic insulating film 16 . Therefore, the thermal stress applied to the mesa structure of the transistor BT can be suppressed as compared with the case where the width R1 of the bump 21 is larger than the width R2 of the opening 17 of the first organic insulating film 16.
  • FIG. 5 is a cross-sectional view of a semiconductor device according to a fourth embodiment. As shown in FIG. 5, in the fourth embodiment, unlike the first to third embodiments, the bump 21 has a first portion 21a and a second portion 21b having different widths. .
  • the bumps 21 are laminated in order of the second portion 21b and the first portion 21a on the plurality of transistors BT.
  • a width R1 of the first portion 21a in the X-axis direction Dx is smaller than a width R2 of the opening 17 of the first organic insulating film 16 in the X-axis direction Dx. Note that if the width R1 of the first portion 21a in the X-axis direction Dx varies slightly over the first organic insulating film 16, the width R1 may be any of the varying widths. width.
  • the second portion 21b is provided between the first portion 21a and the transistor BT in the Z-axis direction Dz and is provided inside the opening 17 of the first organic insulating film 16 .
  • the second portion 21 b is provided to fill the opening 17 of the first organic insulating film 16 , and the outer peripheral surface of the second portion 21 b is in contact with the inner peripheral surface of the opening 17 of the first organic insulating film 16 . That is, the width of the second portion 21b is greater than the width of the first portion 21a and equal to the width R2 of the opening 17 of the first organic insulating film 16. As shown in FIG.
  • FIG. 6 is an explanatory diagram for explaining the manufacturing process of the semiconductor device according to the fourth embodiment.
  • a plurality of transistors BT and respective insulating films are provided on a semiconductor substrate 1, and a power supply film 11 is formed to cover the plurality of transistors BT and respective insulating films (step ST1).
  • the power supply film 11 is provided covering the first organic insulating film 16 and the openings 17 , and is in contact with the emitter electrodes 6 of the plurality of transistors BT at the bottoms of the openings 17 .
  • a metal material having good conductivity is used for the power supply film 11 . Note that the power supply film 11 is omitted from FIGS. 2 to 5 described above.
  • step ST2 the power supply film 11 above the first organic insulating film 16 is removed.
  • the power supply film 11 provided at the bottom of the opening 17 remains without being removed.
  • a predetermined portion of the power supply film 11 above the first organic insulating film 16 is removed by, for example, etching.
  • the second portion 21b of the bump 21 is formed inside the opening 17 of the first organic insulating film 16 (step ST3).
  • the second portion 21b of the bump 21 is formed by plating, for example.
  • a resist 200 is applied on the first organic insulating film 16 and the second portion 21b, and an opening 201 is formed in a region of the resist 200 that partially overlaps the second portion 21b by photolithography.
  • a first portion 21a of the bump 21 is formed inside the opening 201 of the resist 200 (step ST4).
  • the first portion 21a of the bump 21 is formed by plating, for example.
  • the bump 21 having the first portion 21a and the second portion 21b is formed (step ST5).
  • the method of manufacturing the semiconductor device 100C according to the fourth embodiment can form the bump 21 having the first portion 21a and the second portion 21b by performing the plating process in two steps.
  • FIG. 7 is a cross-sectional view of the semiconductor device according to the fifth embodiment. As shown in FIG. 7, in the fifth embodiment, unlike the first to fourth embodiments, a configuration having a rewiring layer 18 will be described.
  • the rewiring layer 18 is provided on the first organic insulating film 16 and electrically connected to the plurality of transistors BT through the openings 17. be.
  • the second organic insulating film 19 is provided on the first organic insulating film 16 to cover the rewiring layer 18 .
  • An opening 20 is provided in a region of the second organic insulating film 19 overlapping with the rewiring layer 18 .
  • the bump 21 is provided in a region overlapping the opening 20 and electrically connected to the rewiring layer 18 through the opening 20 .
  • the first organic insulating film 16 and the second organic insulating film 19 may be made of the same material. That is, the first organic insulating film 16 and the second organic insulating film 19 are integrally formed, and there may be no clear interface between them.
  • the width R1 of the bump 21 in the X-axis direction Dx is equal to the width of the opening 20 in the second organic insulating film 19 in the X-axis direction Dx. Also, the width R1 of the bump 21 in the X-axis direction Dx is smaller than the width R2 of the opening 17 of the first organic insulating film 16 in the X-axis direction Dx. In other words, the width of the opening 20 in the second organic insulating film 19 is smaller than the width R2 of the opening 17 in the first organic insulating film 16 in the X-axis direction Dx.
  • the semiconductor device 100D has the rewiring layer 18 overlapping with at least one transistor BT, the first organic insulating film 16 stacked in this order from the side closer to the transistor BT, and a second organic insulating film 19 .
  • the rewiring layer 18 is provided between the first organic insulating film 16 and the second organic insulating film 19, and is connected to the emitter of the transistor BT through the opening 17 (first opening) provided in the first organic insulating film 16. It is electrically connected with the electrode 6 .
  • the bump 21 is electrically connected to the rewiring layer 18 through an opening 20 (second opening) provided in the second organic insulating film 19 .
  • a width R1 of the bump 21 in the X-axis direction Dx is smaller than a width R2 of the opening 17 of the first organic insulating film 16 in the X-axis direction Dx.
  • the first organic insulating film 16 provided closer to the transistor BT among the plurality of first organic insulating films 16 and the second organic insulating films 19 is By forming the width R1 of the bump 21 to be smaller than the width R2 of the opening 17, the thermal stress applied from the bump 21 to the mesa structure of the transistor BT can be suppressed as in the above embodiments.
  • FIG. 8 is a cross-sectional view of a semiconductor device according to a modification of the fifth embodiment.
  • the width R ⁇ b>1 of the bump 21 is not limited to the width of the opening 20 of the second organic insulating film 19 .
  • the width R1 of the bump 21 is larger than the width of the opening 20 of the second organic insulating film 19 and A configuration smaller than the width R2 of the 16 openings 17 may be used.
  • FIG. 9 is an explanatory diagram for explaining the manufacturing process of the semiconductor device according to the fifth embodiment.
  • a power supply film 11 is formed covering the plurality of transistors BT and each insulating film (step ST11).
  • the power supply film 11 is provided covering the first organic insulating film 16 and the openings 17 , and is in contact with the emitter electrodes 6 of the plurality of transistors BT at the bottoms of the openings 17 .
  • the power supply film 11 is patterned by etching or the like. Specifically, the power supply film 11 is provided to cover a portion of the upper surface of the first organic insulating film 16 near the opening 17 with the outer edge side of the first organic insulating film 16 removed.
  • a rewiring layer 18 is formed on the power supply film 11, covering the opening 17 of the first organic insulating film 16 (step ST12).
  • the rewiring layer 18 is formed by plating, for example.
  • a second organic insulating film 19 is formed to cover the rewiring layer 18 and the first organic insulating film 16, and an opening 20 is formed in a region of the second organic insulating film 19 overlapping with a part of the rewiring layer 18. (step ST13).
  • the width of the opening 20 in the second organic insulating film 19 is formed smaller than the width of the opening 17 in the first organic insulating film 16 .
  • a resist 200 is coated on the second organic insulating film 19 and the rewiring layer 18, and an opening 201 is formed in the resist 200 by photolithography in a region overlapping the opening 20 of the second organic insulating film 19. be.
  • a bump 21 is formed inside the opening 201 of the resist 200 (step ST14).
  • the bumps 21 are formed by plating, for example.
  • the width of the opening 201 of the resist 200 is equal to the width of the opening 20 of the second organic insulating film 19 .
  • the width R1 of the bump 21 is also formed to be equal to the width of the opening 20 of the second organic insulating film 19.
  • step ST15 the method for manufacturing the semiconductor device 100D according to the fifth embodiment can form the rewiring layer 18 and the bumps 21 .
  • step ST14 the width of the opening 201 of the resist 200 is made larger than the width of the opening 20 of the second organic insulating film 19 and smaller than the width R2 of the opening 17 of the first organic insulating film 16. good too.
  • the width R1 of the bump 21 is formed larger than the width of the opening 20 of the second organic insulating film 19 and smaller than the width R2 of the opening 17 of the first organic insulating film 16.
  • FIG. 10 is a cross-sectional view of a semiconductor device according to the sixth embodiment.
  • the width R1b of the second portion 21b of the bump 21 is different from that of the semiconductor device 100C (see FIG. 5) according to the fourth embodiment.
  • the difference lies in the configuration, which is smaller than the width R2 of the opening 17 in the membrane 16 .
  • the semiconductor device 100F according to the sixth embodiment can also be said to have a configuration in which the bumps 21 of the fourth embodiment are combined with the semiconductor device 100 according to the first embodiment.
  • the bump 21 has a first portion 21a and a second portion 21b with different widths.
  • the bump 21 is laminated in the order of the second portion 21b and the first portion 21a on the plurality of transistors BT.
  • a width R1a of the first portion 21a in the X-axis direction Dx is smaller than a width R1b of the second portion 21b.
  • the width R1a of the first portion 21a in the X-axis direction Dx is smaller than the width R2 of the opening 17 of the first organic insulating film 16 in the X-axis direction Dx.
  • the second portion 21b is provided between the first portion 21a and the transistor BT in the Z-axis direction Dz, and is provided inside the opening 17 of the first organic insulating film 16 .
  • the outer peripheral surface of the second portion 21b faces the inner peripheral surface of the opening 17 of the first organic insulating film 16 with a gap therebetween. That is, the width R1b of the second portion 21b is larger than the width of the first portion 21a and smaller than the width R2 of the opening 17 of the first organic insulating film 16. As shown in FIG.
  • FIG. 11 is a cross-sectional view of a semiconductor device according to the seventh embodiment. As shown in FIG. 11, the semiconductor device 100G according to the seventh embodiment differs from the semiconductor device 100 according to the first embodiment in that it has an under bump metal (UBM) 22 .
  • UBM under bump metal
  • the under bump metal 22 is provided under the bump 21 . More specifically, under bump metal 22 is provided between bump 21 and emitter wiring 12 in a direction perpendicular to semiconductor substrate 1 .
  • the width of the under bump metal 22 in the X-axis direction Dx is also the first organic insulating film width. less than the width R2 of the opening 17 in the membrane 16;
  • the under bump metal 22 is made of a material containing at least one of Ti, Cr, Cu, Au, Ni, and Pd, for example. Another adhesive layer or the like may be provided between the under bump metal 22 and the emitter wiring 12 .
  • the bumps 21 are crushed by the pressure during mounting, and the width R1 of the bumps 21 becomes the width R2 of the opening 17 of the first organic insulating film 16. It may spread further.
  • the width of the under bump metal 22 is narrower than the width R2 of the opening 17 of the first organic insulating film 16
  • the width R1 of the bump 21 in the semiconductor device 100G before being mounted is the same as that of the first organic insulating film. It is synonymous with being narrower than the width R2 of the opening 17 of the film 16, and the thermal stress applied from the bump 21 to the mesa structure of the transistor BT can be reduced as described above.
  • the semiconductor device 100G shown in FIG. 11 is configured by combining the semiconductor device 100 according to the first embodiment with the under bump metal 22, it is not limited to this.
  • the under bump metal 22 can be combined with each of the semiconductor devices 100A, 100B, 100C, 100D, 100E, and 100F shown in the second through sixth embodiments.
  • the semiconductor device in which one bump 21 is provided so as to overlap a plurality of transistors BT has been described as an example, but the present invention is not limited to this.
  • a semiconductor device in which one bump is formed so as to overlap one transistor may be used.
  • the pillar bumps have been described as examples of the bumps, other than the pillar bumps, for example, solder bumps and stud bumps may be used.
  • each configuration shown in each embodiment described above is merely examples, and may be changed as appropriate. Materials and thicknesses of the subcollector layer 2, the collector layer 3, the base layer 4, the emitter layer 5 and various wirings may be changed as appropriate.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Bipolar Transistors (AREA)
  • Thin Film Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

L'invention concerne un dispositif à semi-conducteurs comprenant : un substrat semi-conducteur ; au moins un transistor qui est disposé sur le substrat semi-conducteur et comprend une pluralité de couches semi-conductrices ; une électrode disposée sur le transistor ; un film isolant organique comportant une ouverture dans une région chevauchant le transistor et l'électrode dans une vue en plan dans une première direction perpendiculaire au substrat semi-conducteur ; et une bosse qui chevauche l'au moins un transistor dans une vue en plan dans la première direction, et est électriquement connectée à l'électrode à travers l'ouverture dans le film isolant organique, la largeur de la bosse dans une seconde direction parallèle au substrat semi-conducteur étant inférieure à la largeur de l'ouverture dans le film isolant organique dans la seconde direction.
PCT/JP2022/046893 2022-01-07 2022-12-20 Dispositif à semi-conducteurs WO2023132231A1 (fr)

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Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002261111A (ja) * 2001-03-06 2002-09-13 Texas Instr Japan Ltd 半導体装置及びバンプ形成方法
JP2003037129A (ja) * 2001-07-25 2003-02-07 Rohm Co Ltd 半導体装置およびその製造方法
JP2005268374A (ja) * 2004-03-17 2005-09-29 Sony Corp 半導体素子とその製造方法、及び半導体装置
JP2009064812A (ja) * 2007-09-04 2009-03-26 Panasonic Corp 半導体装置の電極構造およびその関連技術
JP2017112318A (ja) * 2015-12-18 2017-06-22 新光電気工業株式会社 端子構造、端子構造の製造方法、及び配線基板
JP2019075536A (ja) * 2017-10-11 2019-05-16 株式会社村田製作所 パワーアンプモジュール
JP2020048184A (ja) * 2018-09-14 2020-03-26 株式会社村田製作所 高周波電力増幅器及び電力増幅モジュール
JP2021197474A (ja) * 2020-06-16 2021-12-27 株式会社村田製作所 半導体装置

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002261111A (ja) * 2001-03-06 2002-09-13 Texas Instr Japan Ltd 半導体装置及びバンプ形成方法
JP2003037129A (ja) * 2001-07-25 2003-02-07 Rohm Co Ltd 半導体装置およびその製造方法
JP2005268374A (ja) * 2004-03-17 2005-09-29 Sony Corp 半導体素子とその製造方法、及び半導体装置
JP2009064812A (ja) * 2007-09-04 2009-03-26 Panasonic Corp 半導体装置の電極構造およびその関連技術
JP2017112318A (ja) * 2015-12-18 2017-06-22 新光電気工業株式会社 端子構造、端子構造の製造方法、及び配線基板
JP2019075536A (ja) * 2017-10-11 2019-05-16 株式会社村田製作所 パワーアンプモジュール
JP2020048184A (ja) * 2018-09-14 2020-03-26 株式会社村田製作所 高周波電力増幅器及び電力増幅モジュール
JP2021197474A (ja) * 2020-06-16 2021-12-27 株式会社村田製作所 半導体装置

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