WO2023131004A1 - 编码方法、解码方法、装置、设备、系统及可读存储介质 - Google Patents

编码方法、解码方法、装置、设备、系统及可读存储介质 Download PDF

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Publication number
WO2023131004A1
WO2023131004A1 PCT/CN2022/142363 CN2022142363W WO2023131004A1 WO 2023131004 A1 WO2023131004 A1 WO 2023131004A1 CN 2022142363 W CN2022142363 W CN 2022142363W WO 2023131004 A1 WO2023131004 A1 WO 2023131004A1
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block
code stream
code
data
blocks
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PCT/CN2022/142363
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English (en)
French (fr)
Inventor
何向
王心远
任浩
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华为技术有限公司
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Priority claimed from CN202210114840.5A external-priority patent/CN116455516A/zh
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Publication of WO2023131004A1 publication Critical patent/WO2023131004A1/zh

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received

Definitions

  • the present application relates to the field of communication technology, and in particular to an encoding method, decoding method, device, equipment, system and a readable storage medium.
  • the message from the media access control (media access control, MAC) layer is divided into blocks according to a fixed length, and enters the media independent interface (media independent interface, MII) in parallel.
  • media independent interface media independent interface
  • MII media independent interface
  • the 800GMII represents an MII with a transmission MAC rate of 800 gigabit per second (Gb/s). It is transmitted to the physical coding sublayer (physical coding sublayer, PCS) through the MII.
  • PCS physical coding sublayer
  • the stream block received by the PCS from the MII includes a data block (transmit data, TXD) and a control block (transmit control, TXC).
  • TXC and TXD are obtained by processing the message flow content from the MAC layer through the adaptation sublayer (reconciliation sublayer, RS).
  • TXC is a control word, which is used to identify whether the content of the corresponding byte in TXD is a control signal or a data signal, where the control signal includes information such as the start, end, error, and idle of the message.
  • PCS encodes according to TXC/TXD content, reduces overhead, and can provide necessary synchronization and protection functions at the same time.
  • PCS performs 64-bit (bit, B)/66B encoding on each group of code stream blocks from MII to obtain a 66-bit code block.
  • the 66-bit code block is a data code block or a control code block. If it is a control code block , the 66-bit code block includes a field with 4-bit Hamming distance protection.
  • each four 66-bit code blocks are transcoded into a 256B/257B-encoded code block with a length of 257 bits, and forward error correction (FEC) is performed on the 257-bit code blocks encoding, and transmit the FEC codeword obtained by the FEC encoding.
  • FEC forward error correction
  • This application proposes an encoding method, decoding method, device, equipment, system, and readable storage medium for improving encoding and decoding efficiency.
  • an encoding method comprising: obtaining 2 n sets of code stream blocks, any set of code stream blocks includes control blocks and data blocks, and the n is an integer greater than 1; for the 2 n groups of code stream blocks are first encoded to obtain a target code block, the target code block includes a type determined based on the control block of the 2 n groups of code stream blocks and a control block based on the 2 n groups of code stream blocks and A data unit defined by a data block.
  • the target code block can be obtained by performing the first encoding on 2 n groups of code stream blocks including control blocks and data blocks, it is not necessary to perform 64B/66B encoding on each group of code stream blocks in the 2 n groups of code stream blocks to obtain 2 n 66-bit code block, and then transcoding 2 n 66-bit code blocks to obtain the target code block, the coding efficiency is improved, and the time delay, power consumption and chip area occupied by the coding process are all reduced.
  • the type is used to indicate that the target code block is a data code block; the data unit is based on the order of the 2 n groups of code stream blocks A data block is obtained by performing the first encoding.
  • the type is used to indicate that the target code block is a control code block;
  • the data unit includes a type indication and code block content, and the code block content is based on the 2n groups of code streams
  • the sequence of determining the control block and data block of the block is obtained by performing the first encoding on the data blocks of the 2 n groups of code stream blocks, the type indication is obtained based on the control blocks of the 2 n groups of code stream blocks, and the The type indication is used to indicate the type of each group of code stream blocks.
  • the target code block is an error code block
  • the error code block includes data for identifying errors. Since the encoding method of the present application can first encode different types of code stream blocks to obtain target code blocks, the method has wide applicability.
  • the target code block is obtained by processing the 2 n groups of code stream blocks based on error detection results, and the error detection results are based on the control blocks and data of the 2 n groups of code stream blocks blocks get.
  • the erroneous data can be distinguished from the correct data during subsequent data transmission, ensuring the reliability of the data.
  • the error detection result includes a content sequence error or content error of the 2n groups of code stream blocks
  • the target code block is based on the fact that the content sequence in the 2n groups of code stream blocks is correct and Code stream blocks with correct content and error blocks are obtained by performing the first encoding, and the error blocks are obtained based on code stream blocks with wrong content sequence or wrong content in the 2n groups of code stream blocks.
  • control block includes m bits
  • data block includes 8m bits
  • m is a positive integer
  • the value of n is 2, the value of m is 8, and the target code block is 257 bits.
  • the 2n groups of code stream blocks all come from the media independent interface MII.
  • after the obtaining the target code block further includes: performing second encoding on the target code block according to an FEC pattern to obtain first data; and sending the first data.
  • the first data is obtained by performing second encoding on the target code block according to the FEC code pattern, so that the receiving end can perform error correction on the received first data to ensure the accuracy of data transmission.
  • a decoding method comprising: obtaining a target code block, the target code block including a type and a data unit; according to the type and data unit of the target code block, Perform the first decoding to obtain 2n groups of code stream blocks, any group of code stream blocks includes control blocks and data blocks obtained based on the type and the data unit, and the n is an integer greater than 1.
  • the first decoding of the target code block can obtain 2 n sets of code stream blocks including the control block and the data block, it is not necessary to transcode the target code block to obtain 2 n 66-bit code blocks, and then to 2 n 66-bit code blocks
  • the bit code blocks are decoded to obtain 2 n sets of code stream blocks, the decoding efficiency is improved, and the time delay, power consumption and chip area occupied by the decoding process are all reduced.
  • the type is used to indicate that the target code block is a data code block; the data block included in the i-th group of code stream blocks in the 2 n groups of code stream blocks is based on the The content of the 8m length corresponding to the i-th group of code stream blocks in the data unit is obtained by performing the first decoding, the m is a positive integer, and the i is an integer greater than or equal to 1 and less than or equal to 2 n or the Said i is an integer greater than or equal to 0 and less than or equal to 2 n -1.
  • the type is used to indicate that the target code block is a control code block
  • the data unit includes a type indication and code block content
  • the type indication includes 2 n bits
  • the 2 One of the n bits is used to indicate the type of a group of code stream blocks corresponding to the bits in the 2 n groups of code stream blocks, and the content of the code block includes 2 n bit groups;
  • the control block included in the i-th group of code stream blocks in the 2 n groups of code stream blocks is based on the type, the bit corresponding to the i-th group of code stream blocks in the type indication, and the content of the code block Obtained from the bit group corresponding to the i-th group of code stream blocks, the i is an integer greater than or equal to 1 and less than or equal to 2 n or the i is an integer greater than or equal to 0 and less than or equal to 2 n -1;
  • the data blocks included in the i-th group of code stream blocks in the 2 n groups of code stream blocks are based on the bit pair corresponding to the i-th group of code stream blocks in the type indication
  • the bit group corresponding to the i group of code stream blocks is obtained by performing the first decoding.
  • the 2 n bit groups include a first bit group and 2 n -1 second bit groups, the number of bits included in the first bit group and the number of bits included in the second bit group include The number of bits is not the same.
  • the data unit includes a type indication, and the type and the type indication are used to indicate that the target code block is an error code block; each group of code blocks in the 2 n groups of code stream blocks
  • the control block included in the stream block is a first value
  • the data block included in each group of code stream blocks in the 2 n groups of code stream blocks is a second value, and the first value and the second value are used to indicate the The code stream block is an error code stream block.
  • the decoding method of the present application can first decode different types of target code blocks to obtain 2 n sets of code stream blocks, the method has wide applicability.
  • the acquiring the target code block includes: receiving second data, the second data is obtained based on the first data encoded by using a forward error correction (FEC) pattern;
  • the second decoding is performed on the second data to obtain the target code block, and the second decoding is an error correction process.
  • FEC forward error correction
  • the target code block is an error code block obtained by performing error correction on the second data but failing to correct the error. Since the target code block is the code block obtained by error-correcting the second data but failing to correct the error, and then marking the code block in the FEC codeword, the receiving end can determine that the data obtained based on the target code block is Wrong data, to ensure the accuracy of the data.
  • the acquiring the target code block includes: receiving second data, the second data is obtained based on the first data encoded by using a forward error correction (FEC) pattern; Performing second decoding on the second data to obtain the target code block, the second decoding is error detection but not error correction.
  • FEC forward error correction
  • the target code block is an error code block obtained by detecting errors from the second data but not correcting errors.
  • the second decoding operation may be to perform error correction on the codeword, or to only detect but not correct errors.
  • the second decoding operation when it is determined that the current codeword cannot be corrected (for example, the number of errors exceeds the error correction capability), all code blocks in the codeword need to be marked error; or when only error detection but no error correction is performed on the codeword in the second decoding process, for the codeword in which an error is detected, all code blocks in the codeword need to be marked with errors.
  • the 2n groups of code stream blocks are obtained by first decoding the target code block according to the error detection result and the type and data unit of the target code block, and the error detection result is based on The type and data unit of the target code block are obtained.
  • the receiving end can distinguish the erroneous data from the correct data, ensuring the reliability of the data.
  • the error detection result includes a content sequence error or a content error of the target code block, and the 2 n groups of code stream blocks pair the second code block according to the type of the second code block and the data unit.
  • the second code block is obtained by first decoding, and the second code block is obtained by converting the target code block and has the same number of bits as the target code block.
  • the error detection result includes a content sequence error or content error of the target code block
  • the 2 n sets of code stream blocks are obtained based on converting 2 n sets of first code stream blocks
  • the 2 n groups of first code stream blocks are obtained by first decoding the target code block based on the type of the target code block and a data unit.
  • control block includes m bits
  • data block includes 8m bits
  • m is a positive integer
  • the value of n is 2, the value of m is 8, and the target code block is 257 bits.
  • the 2 n sets of code stream blocks are all in the MII format.
  • an encoding device comprising:
  • An acquisition module configured to acquire 2 n groups of code stream blocks, any group of code stream blocks includes a control block and a data block, and the n is an integer greater than 1;
  • the first encoding module is configured to perform first encoding on the 2 n groups of code stream blocks to obtain a target code block, the target code block includes a type determined based on the control block of the 2 n groups of code stream blocks and based on the set The data unit determined by the control block and the data block of the above 2 n groups of code stream blocks.
  • the type is used to indicate that the target code block is a data code block; the data unit is based on the sequence determined by the control block and the data block of the 2 n groups of code stream blocks. 2. Obtained by performing the first encoding on the data blocks of n groups of code stream blocks.
  • the type is used to indicate that the target code block is a control code block;
  • the data unit includes a type indication and code block content, and the code block content is based on the 2n groups of code streams
  • the sequence of determining the control block and data block of the block is obtained by performing the first encoding on the data blocks of the 2 n groups of code stream blocks, the type indication is obtained based on the control blocks of the 2 n groups of code stream blocks, and the The type indication is used to indicate the type of each group of code stream blocks.
  • the target code block is an error code block
  • the error code block includes data for identifying errors
  • the target code block is obtained by processing the 2 n groups of code stream blocks based on error detection results, and the error detection results are based on the control blocks and data of the 2 n groups of code stream blocks blocks get.
  • the error detection result includes a content sequence error or content error of the 2n groups of code stream blocks
  • the target code block is based on the fact that the content sequence in the 2n groups of code stream blocks is correct and Code stream blocks with correct content and error blocks are obtained by performing the first encoding, and the error blocks are obtained based on code stream blocks with wrong content sequence or wrong content in the 2n groups of code stream blocks.
  • control block includes m bits
  • data block includes 8m bits
  • m is a positive integer
  • the value of n is 2, the value of m is 8, and the target code block is 257 bits.
  • the 2n groups of code stream blocks all come from the media independent interface MII.
  • the device also includes:
  • the second encoding module is configured to perform second encoding on the target code block according to the forward error correction (FEC) pattern to obtain the first data; the sending module is configured to send the first data.
  • FEC forward error correction
  • a decoding device comprising:
  • An acquisition module configured to acquire a target code block, where the target code block includes a type and a data unit;
  • a decoding module configured to first decode the target code block according to the type and data unit of the target code block to obtain 2 n groups of code stream blocks, any group of code stream blocks includes For the control block and data block obtained by the data unit, the n is an integer greater than 1.
  • the type is used to indicate that the target code block is a data code block; the data block included in the i-th group of code stream blocks in the 2 n groups of code stream blocks is based on the The content of the 8m length corresponding to the i-th group of code stream blocks in the data unit is obtained by performing the first decoding, the m is a positive integer, and the i is an integer greater than or equal to 1 and less than or equal to 2 n or the Said i is an integer greater than or equal to 0 and less than or equal to 2 n -1.
  • the type is used to indicate that the target code block is a control code block;
  • the data unit includes a type indication and code block content, the type indication includes 2 n bits, and the 2 One of the n bits is used to indicate the type of a group of code stream blocks corresponding to the bit in the 2 n groups of code stream blocks, and the content of the code block includes 2 n bit groups; the 2 n
  • the control block included in the i-th group of code stream blocks in the group of code stream blocks is based on the type, the bit corresponding to the i-th group of code stream blocks in the type indication, and the bit corresponding to the i-th group of code stream blocks in the code block content.
  • the bit group corresponding to the i group of code stream blocks is obtained, the i is an integer greater than or equal to 1 and less than or equal to 2 n or the i is an integer greater than or equal to 0 and less than or equal to 2 n -1; the 2 n group code
  • the data blocks included in the i-th group of code stream blocks in the stream blocks are based on the bits corresponding to the i-th group of code stream blocks in the type indication and corresponding to the i-th group of code stream blocks in the code block content
  • the group of bits is obtained by performing the first decoding.
  • the 2 n bit groups include a first bit group and 2 n -1 second bit groups, the number of bits included in the first bit group and the number of bits included in the second bit group include The number of bits is not the same.
  • the data unit includes a type indication, and the type and the type indication are used to indicate that the target code block is an error code block; each group of code blocks in the 2 n groups of code stream blocks
  • the control block included in the stream block is a first value
  • the data block included in each group of code stream blocks in the 2 n groups of code stream blocks is a second value, and the first value and the second value are used to indicate the The code stream block is an error code stream block.
  • the obtaining module is configured to receive second data, the second data is obtained based on the first data encoded by using a forward error correction (FEC) pattern; for the second data performing second decoding to obtain the target code block, where the second decoding is error correction processing.
  • FEC forward error correction
  • the target code block is a code block obtained by performing error correction on the second data but failing to correct the error.
  • the obtaining module is configured to receive second data, the second data is obtained based on the first data encoded by using a forward error correction (FEC) pattern; for the second data performing second decoding to obtain the target code block, where the second decoding is error detection but not error correction.
  • FEC forward error correction
  • the target code block is an error code block obtained by detecting errors from the second data but not correcting errors.
  • the 2n groups of code stream blocks are obtained by performing the first decoding on the target code block according to the error detection result and the type and data unit of the target code block, and the error detection The result is obtained based on the type and data unit of the target code block.
  • the error detection result includes a content sequence error or a content error of the target code block, and the 2 n groups of code stream blocks pair the second code block according to the type of the second code block and the data unit.
  • the second code block is obtained by performing the first decoding, and the second code block is obtained by converting the target code block and has the same number of bits as the target code block.
  • the error detection result includes a content sequence error or content error of the target code block
  • the 2 n sets of code stream blocks are obtained based on converting 2 n sets of first code stream blocks
  • the 2 n groups of first code stream blocks are obtained by performing the first decoding on the target code block based on the type and data unit of the target code block.
  • control block includes m bits
  • data block includes 8m bits
  • m is a positive integer
  • the value of n is 2, the value of m is 8, and the target code block is 257 bits.
  • the 2 n sets of code stream blocks are all in the MII format.
  • a network device including a processor, the processor is coupled with a memory, at least one program instruction or code is stored in the memory, at least one program instruction or code is loaded and executed by the processor, so that the network device realizes Any encoding method in the first aspect, or implement any decoding method in the second aspect.
  • a computer-readable storage medium is provided. At least one program instruction or code is stored in the storage medium. When the program instruction or code is loaded and executed by the processor, the computer can realize any encoding method in the first aspect. , or implement any decoding method in the second aspect.
  • a communication system in a seventh aspect, includes a first network device and a second network device, the first network device is used to execute any encoding method in the first aspect, and the second network device It is used to implement any decoding method in the second aspect.
  • another communication device includes: a transceiver, a memory, and a processor.
  • the transceiver, the memory and the processor communicate with each other through an internal connection path, the memory is used to store instructions, and the processor is used to execute the instructions stored in the memory to control the transceiver to receive signals and control the transceiver to send signals , and when the processor executes the instruction stored in the memory, the processor is made to execute any encoding method in the first aspect, or execute any decoding method in the second aspect.
  • processors there are one or more processors, and one or more memories.
  • the memory may be integrated with the processor, or the memory may be set separately from the processor.
  • the memory can be a non-transitory (non-transitory) memory, such as a read-only memory (read only memory, ROM), which can be integrated with the processor on the same chip, or can be set in different On the chip, the application does not limit the type of the memory and the arrangement of the memory and the processor.
  • a non-transitory memory such as a read-only memory (read only memory, ROM)
  • ROM read only memory
  • a computer program product comprising: computer program code, when the computer program code is run by a computer, causing the computer to execute any encoding method in the first aspect, or Perform any decoding method in the second aspect.
  • a chip including a processor, configured to call and execute instructions stored in the memory from the memory, so that the communication device installed with the chip executes any encoding method in the first aspect, Or execute any decoding method in the second aspect.
  • another chip including: an input interface, an output interface, a processor, and a memory, the input interface, the output interface, the processor, and the memory are connected through an internal connection path, and the The processor is configured to execute the codes in the memory, and when the codes are executed, the processor is configured to execute any encoding method in the first aspect, or execute any decoding method in the second aspect.
  • FIG. 1 is a schematic diagram of an implementation environment of an encoding method and a decoding method provided in an embodiment of the present application;
  • FIG. 2 is a flow chart of an encoding method provided by an embodiment of the present application.
  • FIG. 3 is a schematic diagram of a process for obtaining a target code block provided by an embodiment of the present application
  • FIG. 4 is a schematic structural diagram of a target code block provided by an embodiment of the present application.
  • FIG. 5 is a schematic structural diagram of another target code block provided by an embodiment of the present application.
  • FIG. 6 is a schematic structural diagram of another target code block provided by an embodiment of the present application.
  • FIG. 7 is a flow chart of a decoding method provided by an embodiment of the present application.
  • FIG. 8 is a schematic structural diagram of an encoding device provided in an embodiment of the present application.
  • FIG. 9 is a schematic structural diagram of a decoding device provided by an embodiment of the present application.
  • FIG. 10 is a schematic structural diagram of a network device provided by an embodiment of the present application.
  • FIG. 11 is a schematic structural diagram of another network device provided by an embodiment of the present application.
  • FIG. 12 is a schematic structural diagram of another network device provided by an embodiment of the present application.
  • Ethernet As a local area network technology, Ethernet is widely used. Since 100 Gigabit Ethernet (GE), a single-channel 25Gb/s transmission rate has been used for data transmission.
  • the physical layer introduces FEC coding, and then transmits the coded FEC codewords.
  • the sender can use Reed-Solomon (Reed-Solomon, RS) (528, 514) to perform FEC encoding on the original data, and an RS code block obtained by encoding includes a 5140-bit payload and a 140-bit checksum. Due to the existence of the check code, the transmission rate required to transmit the FEC codeword is higher than the transmission rate required to transmit the original data for the transmission rate required to transmit the same payload within the same time.
  • Reed-Solomon Reed-Solomon
  • transcoding is adopted in the Ethernet standard to reduce the transmission rate required for transmitting FEC codewords by reducing the overhead of code blocks before FEC encoding. For example, every four 64B/66B coded blocks are transcoded into one 256B/257B coded block. Since the overhead of one 257-bit code block is lower than the overhead of four 66-bit code blocks, the transmission rate required for transmitting the FEC codeword obtained based on the 257-bit code block is relatively low.
  • the transmission rate required to transmit the FEC code word obtained based on the transcoded code block is 103.125Gb/s, which is the same as the transmission rate required for the 66-bit code block without FEC encoding.
  • the transfer rate is the same.
  • the receiving end can perform error correction on the FEC codeword. Since the identification of bit errors can be realized by FEC error marking, and most of the processing in PCS is based on 257-bit code blocks, the 64B/66B encoding process and the corresponding transcoding process will generate unnecessary delays , power consumption and chip area occupation.
  • an embodiment of the present application provides a data transmission method to solve the above problem.
  • first encoding is performed on 2 n (n is an integer greater than 1) groups of code stream blocks including control blocks and data blocks to obtain target code blocks, without having to encode each of the 2 n groups of code stream blocks 64B/66B encoding is performed on the group code stream blocks, and then 2 n 66-bit code blocks are transcoded to obtain the target code block.
  • the encoding efficiency is improved, and the time delay, power consumption, and chip area occupied by the encoding process are all reduced.
  • the target code block when the target code block is first decoded, the target code block can be directly decoded to obtain 2n groups of code stream blocks including control blocks and data blocks, without performing the first decoding on the target code block.
  • 2 n 66-bit code blocks are obtained by transcoding, and then 2 n 66-bit code blocks are decoded to obtain 2 n sets of code stream blocks.
  • the encoding method and decoding method provided in the embodiments of the present application can be applied to the current Ethernet interface or other scenarios where data transmission is required.
  • the implementation scenario includes multiple chips, and information can be exchanged between each chip to realize data transmission.
  • a chip 102 is provided in the first network device 101
  • a chip 104 is provided in the second network device 103, both the chip 102 and the chip 104 support FEC encoding and FEC decoding, and the first network device 101 and the second network device 103
  • the channel 105 in between is capable of transmitting FEC-encoded data.
  • the chip 102 can perform first encoding on the 2 n groups of code stream blocks to obtain the target code block, perform second encoding on the target code block according to the first FEC pattern to obtain the first data, and send the first data to the chip through the channel 105 104.
  • bit errors may occur when the first data is transmitted in the channel 105, and the received data is referred to as second data.
  • the chip 104 may use the first FEC pattern to perform second decoding on the second data to obtain target code blocks, and perform first decoding on the target code blocks to obtain 2 n groups of code stream blocks.
  • n is an integer greater than 1
  • the first FEC code type includes but is not limited to RS code, Bose-Chaudhuri-Hocquenghem (Bose-Chaudhuri-Hocquenghem, BCH) code, Hamming code (Hamming code), Extended BCH code (extended-BCH code), extended Hamming code (extended-Hamming code), Farr (fire) code, turbo (turbo) code, turbo product code (turbo product code, TPC), ladder (staircase) code and Any one or multiple concatenated combinations of low-density parity-check (low-density parity-check, LDPC) codes.
  • RS code Bose-Chaudhuri-Hocquenghem
  • BCH Bose-Chaudhuri-Hocquenghem
  • BCH Bose-Chaudhuri-Hocquenghem
  • Hamming code Hamming code
  • Extended BCH code extended-BCH code
  • each network device may include at least one chip.
  • FIG. 1 only two network devices, each of which includes a chip, are used as an example for illustration.
  • the encoding method provided by the embodiment of the present application is shown in FIG. 2 .
  • the encoding method provided by the embodiment of the present application is executed by the chip 102 in FIG. 1 , and the method includes but not limited to step 201 and step 202 .
  • Step 201 obtain 2 n sets of code stream blocks, any set of code stream blocks includes control blocks and data blocks, and n is an integer greater than 1.
  • the 2 n groups of code stream blocks are all from the MII.
  • the embodiment of the present application does not limit the manner of acquiring 2 n sets of code stream blocks based on the MII.
  • the MII may adopt the Institute of Electrical and Electronics Engineers (the Institute of Electrical and Electronics Engineers, IEEE) 802.3 standard, such as the MII defined by IEEE802.3-2018 and other versions of the IEEE802.3 standard, to obtain 2 n sets of code stream blocks.
  • the value of n is 2, that is, four sets of code stream blocks are obtained.
  • the control block of any group of code stream blocks includes m bits
  • the data block of any group of code stream blocks includes 8m bits, where m is positive integer.
  • 8m means 8 times of m, which can also be expressed as 8*m.
  • the value of m is 8, that is, for any set of code stream blocks, the control block of any set of code stream blocks includes 8 bits, and the data block of any set of code stream blocks includes 64 bits .
  • the m bits included in the control block are all control bits, that is, the control block includes m control bits; the 8m bits included in the data block are all data, that is, the 8m bits of data included in the data block.
  • control block including 8 control bits is represented as TXC ⁇ 7:0>
  • data block including 64-bit data is represented as TXD ⁇ 63:0>
  • order of each bit of the control block and the data block is the same as From the most significant bit (most significant bit, MSB) to the least significant bit (least significant bit, LSB).
  • Step 202 perform the first encoding on 2 n groups of code stream blocks to obtain target code blocks
  • the target code blocks include the type determined based on the control blocks of 2 n groups of code stream blocks and the control blocks and data based on 2 n groups of code stream blocks A unit of data identified by a block.
  • control blocks of each group of code stream blocks are 8 bits, and the data blocks are all 64 bits, and the first encoding is performed on the four groups of code stream blocks to obtain a 257-bit target code block.
  • the first encoding is performed on 2 n sets of code stream blocks to obtain target code blocks, including but not limited to the following encoding manner 1 and encoding manner 2.
  • Coding mode 1 based on the control blocks of 2 n groups of code stream blocks, it is determined that the type of the target code block is a data code block; based on the sequence of 2 n groups of code stream blocks, the first encoding is performed on the data blocks of 2 n groups of code stream blocks to obtain Data unit; based on the type and data unit, the target code block is obtained.
  • the type is used to indicate that the target code block is a data code block; the data unit performs the first data block of the 2 n groups of code stream blocks based on the order of the 2 n groups of code stream blocks A code is obtained.
  • the type of the target code block is determined to be a data code block, and the first specified value is used to indicate the code stream block
  • the type of is a data stream block.
  • the types of each group of code stream blocks are data code stream blocks.
  • the first encoding is performed on the data blocks of 2 n groups of code stream blocks to obtain the data unit, including: based on the order of 2 n groups of code stream blocks, respectively
  • the bits included in the data blocks of the 2n groups of code stream blocks are used as the bits of the data unit to obtain the data unit.
  • TXD_j ⁇ 63:0> indicates the data block of the jth group of code stream blocks
  • tx_coded ⁇ 256:0> indicates the target code block
  • tx_coded ⁇ (64j+64):( 64j+1)> indicates the (64j+64)th bit to (64j+1)th bit of the target code block
  • each bit of tx_coded ⁇ 256:0> is as shown in the following expressions 1 and 2:
  • tx_coded ⁇ 64:1> TXD_0 ⁇ 63:0>, indicating that the 63rd bit to the 0th bit of the data block of the 0th code stream block are respectively used as the 64th bit of the target code block to the 1st bit.
  • tx_coded ⁇ 128:65> TXD_1 ⁇ 63:0>, indicating that the 63rd to 0th bits of the data block of the first group of code stream blocks are respectively used as the 128th to 128th bits of the target code block 65 bits.
  • tx_coded ⁇ 192:129> TXD_2 ⁇ 63:0>, indicating that the 63rd bit to the 0th bit of the data block of the second group of code stream blocks are respectively used as the 192nd bit to the 192nd bit of the target code block 129 bits.
  • tx_coded ⁇ 256:193> TXD_3 ⁇ 63:0>, indicating that the 63rd to 0th bits of the data block of the third group of code stream blocks are respectively used as the 256th to 256th bits of the target code block 193 bits.
  • FIG. 3 shows a schematic diagram of a process of obtaining a target code block.
  • the control blocks of each group of code stream blocks are represented as TXC ⁇ 7:0>
  • the data blocks are represented as TXD ⁇ 63:0>.
  • the TXC ⁇ 7:0> of the four groups of code stream blocks are all 0x00
  • the type of the target code block is a data code block.
  • the type of the target code block corresponds to the 0th bit of the target code block, and assigning the 0th bit to 1 indicates that the type is a data code block.
  • the embodiment of the present application does not limit the method of assigning the 0th bit to indicate that the type is a data code block.
  • Based on the order of the four sets of code stream blocks multiple bits of the data blocks of the four sets of code stream blocks are respectively used as multiple bits of the data unit to obtain the data unit.
  • target bits can be obtained based on type and data unit.
  • the structure of the obtained target code block is shown in Figure 4, the 0th bit of the target code block is used to indicate the type of the target code block, and the 0th bit is assigned a value of 1 to indicate that the type of the target code block is a data code piece.
  • the 1st bit to the 256th bit of the target code block are used to represent the data unit of the target code block, wherein D0 represents the 64 bits of the data block of the 0th group of code stream block, and D1 represents the data block of the first group of code stream block 64 bits, D2 represents the 64 bits of the data block of the second group of code stream blocks, and D3 represents the 64 bits of the data block of the third group of code stream blocks.
  • Coding method 2 based on the control blocks of 2n groups of code stream blocks, it is determined that the type of the target code block is a control code block ; To indicate the type of code stream block; use the identification value of 2 n groups of code stream blocks as a type indication; based on the sequence determined by the control block and data block of 2 n groups of code stream blocks, perform the first data block of 2 n groups of code stream blocks After encoding, the content of the code block is obtained; based on the type and the data unit, the target code block is obtained, wherein the data unit includes the type indication and the content of the code block.
  • the target code block obtained by adopting the second encoding method includes a type and a data unit.
  • the type is used to indicate that the target code block is a control code block;
  • the data unit includes a type indication and a code block content, and the code block content is based on the sequence determined by the control block and the data block of the 2n group of code stream blocks to 2n groups of code stream blocks
  • the data block is obtained by first encoding, the type indication is obtained based on the control blocks of 2n groups of code stream blocks, and the type indication is used to indicate the type of each group of code stream blocks.
  • the determined order of the control blocks and the data blocks of the 2 n sets of code stream blocks is the receiving order of the 2 n sets of code stream blocks.
  • the control block of at least one group of code stream blocks in the 2 n groups of code stream blocks is a second specified value
  • the type of the target code block can be determined to be a control code block through the second specified value.
  • the second specified value is used to indicate that the type of the code stream block is a control code stream block, and the second specified value is different from the above-mentioned first specified value. That is to say, in the case that at least one group of code stream blocks in the 2n groups of code stream blocks is a control code stream block, the type of the target code stream block is a control code block.
  • the identification value of the group of code stream blocks is the third specified value
  • the identification value of the group of code stream blocks is the fourth specified value.
  • the third specified value is 1, and the fourth specified value is 0.
  • using the identification values of the 2n groups of code stream blocks as the type indication includes: according to the order determined by the control blocks and data blocks of the 2n groups of code stream blocks, using the identification values of the 2n groups of code stream blocks as types respectively Indicates the individual bits to get the type indication.
  • the first encoding is performed on the data blocks of the 2n groups of code stream blocks to obtain the code block content, including: based on the 2n groups of code stream blocks
  • the sequence determined by the control block and the data block performs the first encoding on the data blocks of the 2n groups of code stream blocks to obtain the content of each group of code stream blocks after the first encoding, and the content of each group of code stream blocks after the first encoding as code block content.
  • the group of code stream blocks after the first encoding, the group of code stream blocks
  • the content of is the content of the data block of this group of stream blocks.
  • the content of the code stream block after the first encoding includes but It is not limited to the following cases A1 to A11.
  • control block is 0x01
  • 7th to 0th bits of the data block are 0xFB, where the LSB is the bit sent first.
  • the data block includes 1 control byte and 7 data bytes, wherein the data bytes are also called octets.
  • the group of code stream blocks is the first group of control code stream blocks
  • the content of the group of code stream blocks after the first encoding is 60 bits
  • the first 4 bits are part of the type domain (block type field, BTF).
  • the BTF part is 0x8. If the group of code stream blocks is not the first group of control code stream blocks, the content of the code stream block after the first encoding is 64 bits, the first 8 bits are the BTF part, and the BTF part is 0x78. No matter which case is mentioned above, the remaining 56 bits are each bit of the 7 data bytes included in the data block.
  • control block is 0xFF
  • the data block includes 8 control bytes.
  • the group of code stream blocks is the first group of control code stream blocks
  • the content of the group of code stream blocks after the first encoding is 60 bits
  • the first 4 bits are the BTF part
  • the BTF part is 0xE.
  • the group of code stream blocks is not the first group of control code stream blocks
  • the content of the code stream block after the first encoding is 64 bits
  • the first 8 bits are the BTF part
  • the BTF part is 0x1E.
  • the remaining 56 bits are the 0th bit of the 8 control bytes included in the data block and the 6th bit.
  • control block is 0x01, and the 7th to 0th bits of the data block are 0x9C, where the LSB is the bit sent first.
  • the data block includes 1 control byte and 7 data bytes.
  • the group of code stream blocks is the first group of control code stream blocks
  • the first coded content of the code stream blocks is 60 bits
  • the first 4 bits are the BTF part
  • the BTF part is 0xB.
  • the content of the code stream block after the first encoding is 64 bits
  • the first 8 bits are BTF part
  • the BTF part is 0x4B.
  • the 24 bits following the BTF part are the 31st to 8th bits of the data block.
  • the 4 bits after the data byte are O code (O code), and O code can be obtained according to the IEEE802.3 standard.
  • the remaining 28 bits are multiple first padding bits, where the multiple first padding bits can be obtained based on the data bytes of the data block, or the multiple first padding bits are all 0.
  • control block is 0xFF
  • 7th bit to the 0th bit of the data block are 0xFD
  • the LSB is the bit sent first.
  • the data block includes 8 control bytes.
  • the group of code stream blocks is the first group of control code stream blocks
  • the content of the group of code stream blocks after the first encoding is 60 bits
  • the first 4 bits are the BTF part
  • the BTF part is 0x7.
  • the content of the code stream block after the first encoding is 64 bits
  • the first 8 bits are the BTF part
  • the BTF part is 0x87.
  • the 7 bits after the BTF part are all 0, and the remaining 49 bits are the 6th to 0th bits of the last 7 control bytes included in the data block.
  • control block is 0xFE
  • 15th to 8th bits of the data block are 0xFD
  • LSB is the bit sent first.
  • the data block includes 1 data byte and 7 control bytes.
  • the group of code stream blocks is the first group of control code stream blocks
  • the first coded content of the code stream blocks is 60 bits
  • the first 4 bits are BTF part
  • the BTF part is 0x9.
  • the content of the code stream block after the first encoding is 64 bits
  • the first 8 bits are the BTF part
  • the BTF part is 0x99.
  • the 8 bits after the BTF part are each bit of the data byte included in the data block
  • the 6 bits after the data byte are all 0, and the remaining 42 bits are the bits of the last 6 control bytes included in the data block Bit 6 to bit 0.
  • control block is 0xFC
  • 23rd to 16th bits of the data block are 0xFD, wherein the LSB is the bit sent first.
  • the data block includes 2 data bytes and 6 control bytes.
  • the group of code stream blocks is the first group of control code stream blocks
  • the content of the group of code stream blocks after the first encoding is 60 bits
  • the first 4 bits are the BTF part
  • the BTF part is 0xA.
  • the content of the code stream block after the first encoding is 64 bits
  • the first 8 bits are the BTF part
  • the BTF part is 0xAA.
  • the 16 bits after the BTF part are the bits of the 2 data bytes included in the data block, the 5 bits after the data byte are all 0, and the remaining 35 bits are the last 5 control words included in the data block Bit 6 to bit 0 of the section.
  • control block is 0xF8, and the 31st to 24th bits of the data block are 0xFD, wherein the LSB is the bit sent first.
  • the data block includes 3 data bytes and 5 control bytes.
  • the group of code stream blocks is the first group of control code stream blocks
  • the first coded content of the code stream blocks is 60 bits
  • the first 4 bits are BTF part
  • the BTF part is 0x4.
  • the group of code stream blocks is not the first group of control code stream blocks
  • the content of the code stream block after the first encoding is 64 bits
  • the first 8 bits are BTF part
  • the BTF part is 0xB4.
  • the 28 bits after the BTF part are the bits of the 3 data bytes included in the data block, the 4 bits after the data byte are all 0, and the remaining 28 bits are the last 4 control words included in the data block Bit 6 to bit 0 of the section.
  • control block is 0xF0, and the 39th to 32nd bits of the data block are 0xFD, wherein the LSB is the bit sent first.
  • the data block includes 4 data bytes and 4 control bytes.
  • the group of code stream blocks is the first group of control code stream blocks
  • the first coded content of the code stream blocks is 60 bits
  • the first 4 bits are the BTF part
  • the BTF part is 0xC.
  • the group of code stream blocks is not the first group of control code stream blocks
  • the content of the code stream block after the first encoding is 64 bits
  • the first 8 bits are BTF part
  • the BTF part is 0xCC.
  • the 32 bits after the BTF part are the bits of the 4 data bytes included in the data block, the 3 bits after the data byte are all 0, and the remaining 21 bits are the last 3 control words included in the data block Bit 6 to bit 0 of the section.
  • control block is 0xE0, and the 47th to 40th bits of the data block are 0xFD, wherein the LSB is the bit sent first.
  • the data block includes 5 data bytes and 3 control bytes.
  • the group of code stream blocks is the first group of control code stream blocks
  • the first coded content of the group of code stream blocks is 60 bits
  • the first 4 bits are the BTF part
  • the BTF part is 0x2.
  • the content of the code stream block after the first encoding is 64 bits
  • the first 8 bits are the BTF part
  • the BTF part is 0xD2.
  • the 32 bits after the BTF part are the bits of the 5 data bytes included in the data block, the 2 bits after the data byte are all 0, and the remaining 12 bits are the last 2 control words included in the data block Bit 6 to bit 0 of the section.
  • control block is 0xC0, and the 55th to 48th bits of the data block are 0xFD, wherein the LSB is the bit sent first.
  • the data block includes 6 data bytes and 2 control bytes.
  • the group of code stream blocks is the first group of control code stream blocks
  • the first coded content of the code stream blocks is 60 bits
  • the first 4 bits are BTF part
  • the BTF part is 0x1.
  • the first coded content of the group of code stream blocks is 64 bits
  • the first 8 bits are the BTF part
  • the BTF part is 0xE1.
  • the 48 bits after the BTF part are the bits of the 6 data bytes included in the data block, the 1 bit after the data byte is 0, and the remaining 7 bits are the last control byte included in the data block The 6th bit to the 0th bit.
  • control block is 0x80, and the 63rd to 56th bits of the data block are 0xFD, where the LSB is the bit sent first.
  • the data block includes 7 data bytes and 1 control byte.
  • the group of code stream blocks is the first group of control code stream blocks
  • the content of the group of code stream blocks after the first encoding is 60 bits
  • the first 4 bits are the BTF part
  • the BTF part is 0xF.
  • the content of the code stream block after the first encoding is 64 bits
  • the first 8 bits are the BTF part
  • the BTF part is 0xFF.
  • the remaining 56 bits are the respective bits of the 7 data bytes included in the data block.
  • the first encoded content of the 2 n groups of code stream blocks is used as the content of the code block.
  • the target code block can be obtained based on the type, type indication and code block content.
  • TXC_j ⁇ 7:0> indicates the control block of the jth code stream block
  • tx_payload ⁇ 251:0> indicates the first encoded content of the four code stream blocks
  • tx_coded ⁇ 256:0> indicates the target code block
  • tx_coded ⁇ 0> indicates the type of the target code block
  • tx_coded ⁇ j+1> indicates the type indication of the target code block
  • tx_coded ⁇ 256:5> indicates the code block content of the target code block
  • each bit of tx_coded ⁇ 256:0> As shown in Expression 3 to Expression 5 below:
  • TXC_j ⁇ 7:0> when TXC_j ⁇ 7:0> is not 0x00, the bit of the target code block corresponding to the j value is 0, and when TXC_j ⁇ 7:0> is 0x00, the target code block corresponding to the j value bit is 1.
  • the structure of the target code block is as shown in FIG. 5 , and 0 to 3 in FIG. 5 represent sequence numbers of four sets of code stream blocks respectively.
  • the left side of Figure 5 shows the types of the four acquired code stream blocks, C represents the control code stream block, and D represents the data code stream block.
  • the right side of Fig. 5 is the structure of the target code block corresponding to different situations, wherein b represents a bit, for example, 1b represents 1 bit, and 4b represents 4 bits. Exemplarily, case 1 in FIG.
  • the 5 corresponds to four groups of code stream blocks whose types are all control code stream blocks, the 0th bit of the target code block obtained by the first encoding is 0, and the 4th bit to the 1st bit are all 0 ;
  • the 8th bit to the 5th bit are represented as f_0, corresponding to the BTF part of the first coded content of the 0th group of code stream blocks, and the 64th to 9th bits correspond to the 0th group of code stream blocks after the first code
  • the remaining content in the content, that is, C0; the 72nd bit to the 65th bit are represented as BTF1, corresponding to the BTF part of the first coded content of the first group of stream blocks, and the 128th bit to the 73rd bit corresponds to the first
  • the rest of the content of the first coded content of a group of code stream blocks, that is, C1; the 136th to 129th bits are represented as BTF2, corresponding to the BTF part of the first coded content of the second group of code
  • the rest of the cases in Fig. 5 are the same as the above case 1.
  • the 68th bit to the 5th bit of the target code block are represented as D0, corresponding to the content of the 0th group code stream block after the first encoding
  • the 68th bit to the 5th bit of the target code block is represented by D0
  • the 72nd bit to the 69th bit are represented as f_1, corresponding to the BTF part of the first coded content of the first group of code stream blocks
  • the 128th to 73rd bits correspond to the first coded content of the first group of code stream blocks
  • the rest of the content in that is, C1 , will not be repeated here for other situations in FIG. 5 .
  • the target code block is an error code block
  • the error code block includes data for identifying errors.
  • a group of code stream blocks in the 2n groups of code stream blocks does not belong to the data code stream blocks, nor does it belong to any of the above-mentioned cases A1 to A11, it is determined that the target code block is an error code block ;
  • the type of 2 n groups of code stream blocks is obtained, and the type indication of the target code stream block is obtained based on the type of 2 n groups of code stream blocks, and the type and type indication are used as error code blocks for misidentified data.
  • the 0th bit of the target code block corresponds to the type
  • the 1st bit to the 4th bit correspond to the type indication
  • the 0th bit is assigned a value of 0
  • the first bit to the fourth bit are all assigned a value of 1.
  • the structure of the target code block is as shown in FIG. 6 .
  • the left side of Fig. 6 shows the types of four sets of code stream blocks obtained, and E represents an error code stream block.
  • the right side of Figure 6 shows the structure of the target code block.
  • the 0th bit of the target code block is 0, the 1st to 4th bits are all 1, the 5th to 64th bits correspond to the filling content obtained based on the first set of code stream blocks, and the 65th to 128th bits correspond to the content based on The filling content obtained from the second group of code stream blocks, the 129th bit to the 192nd bit correspond to the filling content obtained based on the third group of code stream blocks, and the 193rd to 256th bits correspond to the filling content obtained based on the fourth group of code stream blocks .
  • each bit of the filling content is 0.
  • the filling content obtained based on the first group of code stream blocks is represented as E0
  • the filling content obtained based on the second group of code stream blocks is represented as E1
  • the filling content obtained based on the third group of code stream blocks is expressed as E2
  • the filling content obtained based on the fourth group of code stream blocks is denoted as E3.
  • the encoding method provided by the embodiment of the present application can first encode different types of code stream blocks to obtain target code blocks, the method has wide applicability.
  • first encoding is performed on 2 n groups of code stream blocks to obtain target code blocks, including: obtaining error detection results based on control blocks and data blocks of 2 n groups of code stream blocks;
  • the 2 n sets of code stream blocks are processed, and the first encoding is performed on the processed 2 n sets of code stream blocks to obtain the target code block. That is to say, the target code block is obtained by processing 2 n sets of code stream blocks based on the error detection results, and the error detection result is obtained based on the control blocks and data blocks of the 2 n sets of code stream blocks.
  • the error detection result is obtained based on the control blocks and data blocks of 2n groups of code stream blocks, including: obtaining the content and content order of 2 n groups of code stream blocks based on the control blocks and data blocks of 2 n groups of code stream blocks,
  • the error detection results are obtained based on the content and content order of 2 n groups of stream blocks. For example, when the content order of the 2 n groups of code stream blocks is at least one of the first error case set, the content order of the 2 n groups of code stream blocks is wrong, and when the content order of the 2 n groups of code stream blocks is not In any case in the first error case set, the content sequence of the 2 n groups of code stream blocks is correct.
  • the content of the 2n group of code stream blocks is at least one of the second error case set, the content of the 2n group of code stream blocks is wrong, and when the content of the 2n group of code stream blocks is not the second When any of the cases in the error case set, the content of the 2 n groups of code stream blocks is correct.
  • the first set of error conditions includes but is not limited to the following four situations:
  • the latter group of code stream blocks includes other content except data bytes.
  • the latter group of code stream blocks includes other content except the idle control word (/I/) or sequence ordered set control word (/O/) .
  • the latter group of code stream blocks includes data bytes or termination control words.
  • a group of code stream blocks is taken as an example for illustration, and the second set of error conditions includes but is not limited to the following four situations:
  • the initial control word is followed by other content except data bytes.
  • the data bytes are followed by content other than data bytes or termination control words.
  • the termination control word is followed by other content except the idle control word or the sequence ordered set control word.
  • the idle control word or the sequence ordered set control word is followed by a data byte or a termination control word.
  • the error detection result includes 2 n groups of code stream blocks with wrong content order or wrong content, based on the code stream blocks with wrong content order or wrong content in 2 n groups of code stream blocks to obtain error blocks, for 2 n groups of code stream blocks
  • the code stream blocks and error blocks with correct content sequence and correct content in the block are first encoded to obtain the target code block. That is to say, in the case that the error detection result includes 2 n groups of code stream blocks in the wrong order or content error, the target code block is based on the code stream blocks with correct content order and correct content in the 2 n groups of code stream blocks and the error block.
  • the first encoding is obtained, and the error block is obtained based on the code stream blocks whose content sequence is wrong or whose content is wrong in the 2n groups of code stream blocks.
  • the error block includes an error control character.
  • the content of the code stream block is converted into an error control word to obtain an error block.
  • the code stream block with the wrong content order or content error is the first group of code stream blocks, and the content of the code stream block is converted into the first error control word.
  • the first error control word is 60 bits, and the first 4 bits are 0xE , and then every 7 bits are 0x1E.
  • the code stream block whose content is in the wrong order or whose content is wrong is at least one of the second group of code stream blocks, the third group of code stream blocks or the fourth group of code stream blocks, and the content of the code stream block is converted into the second group of code stream blocks.
  • An error control word, the second error control word is 64 bits, the first 8 bits are 0x1E, and every 7 bits thereafter are 0x1E.
  • the first encoding is performed on the code stream blocks and error blocks with correct content order and content order in the 2 n groups of code stream blocks to obtain the target code block, including: determining the type of the target code block as a control code block; obtaining 2 n The identification value of the group code stream block, the identification value is used to indicate the type of the code stream block, and the identification value of the 2n group of code stream blocks is used as the type indication; the sequence pair determined based on the control block and the data block of the 2n group of code stream blocks The error block and the data blocks of the code stream blocks with correct content sequence and correct content in the 2 n groups of code stream blocks are first encoded to obtain the code block content.
  • the first encoding is performed on the data blocks of the code stream blocks with correct content order and correct content in the 2n groups of code stream blocks, and the obtained content sequence is correct and The first coded content of the code stream block with correct content, the target code block is obtained based on the first coded content of the code stream block with correct content sequence and correct content and the error block.
  • the method of performing the first encoding on the data block of the code stream block with the correct content order and correct content please refer to the first encoding method for the code stream block whose type is data stream block and the code stream block whose type is control code stream block. Relevant content of a code will not be repeated here.
  • each group of code stream blocks in the 2 n groups of code stream blocks is a code stream block with wrong content order or wrong content
  • 2 n error blocks are obtained based on the 2 n groups of code stream blocks.
  • 2 n error blocks are first encoded to obtain a target code block, and the target code block is an error code block.
  • the erroneous data can be distinguished from the correct data during subsequent data transmission, thereby ensuring the reliability of the data.
  • the method further includes: performing second encoding on the target code block according to the FEC pattern to obtain the first data; and sending the first data.
  • the embodiment of the present application does not limit the manner of performing the second encoding on the target code block according to the FEC code type.
  • the first data is obtained by performing second encoding on the target code block according to the FEC code pattern, so that the receiving end can perform error correction on the received first data to ensure the accuracy of data transmission.
  • first encoding is performed on 2 n sets of code stream blocks including control blocks and data blocks to obtain target code blocks, without performing 64B on each set of code stream blocks in the 2 n sets of code stream blocks /66B encoding to obtain 2 n 66-bit code blocks, and then transcoding the 2 n 66-bit code blocks to obtain the target code block.
  • the encoding efficiency is improved, and the time delay, power consumption, and chip area occupied by the encoding process are all reduced.
  • the decoding method provided by the embodiment of the present application is described above, and the decoding method provided by the embodiment of the present application is introduced below. Combining with the implementation scenario shown in FIG. 1 , the decoding method provided by the embodiment of the present application is shown in FIG. 7 . Exemplarily, the decoding method provided by the embodiment of the present application is executed by the chip 104 in FIG. 1 , and the method includes but not limited to step 701 and step 702 .
  • step 701 a target code block is obtained, and the target code block includes a type and a data unit.
  • the chip 102 sends the first data encoded using the FEC code pattern to the chip 104 through the channel 105, and a bit error may occur in the first data during data transmission, and the error
  • the coded data is referred to as second data, and the chip 104 receives the second data through the channel 105 .
  • the target code block is acquired, including but not limited to the following manner A and manner B.
  • Mode A receiving second data, the second data is obtained based on the first data encoded by using the FEC pattern; performing second decoding on the second data to obtain the target code block, the second decoding is an error correction process.
  • the target code block is an error code block obtained by performing error correction on the second data but failing to correct the error.
  • performing second decoding on the second data to obtain the target code block includes: processing the second data according to the FEC pattern to obtain a first code word, performing error correction processing on the first code word, and performing error correction processing based on the error correction processing As a result, the target code block is obtained.
  • the chip 104 has the function of an FEC decoder.
  • the FEC decoder determines that the number of errors exceeds the error correction capability of the FEC decoder, that is, when the FEC decoder determines that the first codeword cannot be During error correction, mark all code blocks in the first codeword as error code blocks. Therefore, when the result of the error correction process is to mark all the code blocks in the first codeword as error code blocks, the acquired target code blocks are error code blocks.
  • the code block obtained based on the error-corrected first codeword is used as the target code block to obtain, and based on the error-corrected first codeword
  • a code block obtained by one code word is a code block whose error correction is successful.
  • Method B receiving the second data, the second data is obtained based on the first data encoded by the forward error correction FEC pattern; performing the second decoding on the second data to obtain the target code block, the second decoding is error detection but not Error handling.
  • the target code block is an error code block obtained by detecting errors from the second data but not correcting errors.
  • performing second decoding on the second data to obtain the target code block includes: processing the second data according to the FEC code pattern to obtain a first code word, performing only error detection but no error correction (bypass correction) on the first code word ) processing; obtaining the target code block based on the result of the error detection but not error correction processing.
  • the chip 104 has a function of an FEC decoder, and when the FEC decoder detects an error in the first codeword, it marks all code blocks in the first codeword as error code blocks. Therefore, when the result of the error detection but no error correction process is to mark all the code blocks in the first codeword as error code blocks, the acquired target code blocks are error code blocks.
  • the code block obtained based on the first codeword is used as the target code block to obtain, and the code block obtained based on the first codeword A block is an error-free code block.
  • the frame check sequence (frame check sequence, FCS) frame check performed based on the target code block fails.
  • the target code block is 257 bits
  • the first 5 bits are 01111
  • the remaining 252 bits include but are not limited to the following three situations: (1) the first 4 bits are 0x1, and every 8 bits in the remaining bits are 0x1E; (2) the first 248 Every 8 bits in the bit is 0x1E, and the last 4 bits are 0x1; (3) All bits are 0.
  • Step 702 first decode the target code block to obtain 2n groups of code stream blocks, any group of code stream blocks includes control blocks and data blocks obtained based on the type and data unit, n is an integer greater than 1.
  • the target code block is 257 bits
  • the control block of each code stream block is 8 bits
  • the data block is 64 bits.
  • the first decoding process can be performed on each target code block respectively, To get 2 n sets of stream blocks.
  • the first decoding can be performed on the two code blocks respectively to obtain four sets of code stream blocks, that is, the first decoding is performed on the two target code blocks to obtain eight sets of code stream blocks .
  • the first decoding is performed on the target code block to obtain 2 n sets of code stream blocks, including but not limited to the following decoding methods 1 to 3.
  • Decoding method 1 based on the type of the target code block, determine the type of the target code block as a data code block, the data unit of the target code block includes 2 n pieces of 8m-length content, m is a positive integer; based on the type of the target code block, 2 The control block of n groups of code stream blocks firstly decodes 2 n pieces of 8m-length content included in the data unit respectively, to obtain data blocks of 2 n groups of code stream blocks.
  • the target code block is first decoded in a decoding manner to obtain 2 n groups of code stream blocks.
  • the data blocks included in the i-th group of code stream blocks in the 2 n groups of code stream blocks are obtained based on the first decoding of the 8m-length content corresponding to the i-th group of code stream blocks in the data unit, and i is greater than or equal to An integer of 1 and less than or equal to 2 n or i is an integer of greater than or equal to 0 and less than or equal to 2 n -1.
  • the type of the target code block is 1 to indicate that the target code block is a data code block
  • the data unit of the target code block includes four 8m-length contents
  • one 8m-length content corresponds to a group of codes flow block.
  • the length of 8m is 64 bits.
  • RXC_j ⁇ 7:0> indicates the control block of the j-th code stream block
  • RXD_j ⁇ 63:0> indicates the data block of the j-th code stream block
  • rx_coded ⁇ 256:0> indicates the target code block
  • rx_coded ⁇ (64j+64):(64j+1)> represents the (64j+64)th to (64j+1)th bit of the target code block
  • RXC_j ⁇ 7:0> and the contents of RXD_j ⁇ 63:0> are shown in Expression 6 and Expression 7 below:
  • RXD_0 ⁇ 63:0> rx_coded ⁇ 64:1>, indicating that the 64th bit to the 1st bit of the target code block are respectively used as the 63rd bit of the data block of the 0th code stream block to bit 0.
  • RXD_1 ⁇ 63:0> rx_coded ⁇ 128:65>, indicating that the 128th to 65th bits of the target code block are respectively used as the 63rd to 63rd bits of the data block of the first group of code stream blocks 0 bits.
  • RXD_2 ⁇ 63:0> rx_coded ⁇ 192:129>, indicating that the 192nd to 129th bits of the target code block are respectively used as the 63rd to 63rd bits of the data block of the second group of code stream blocks 0 bits.
  • RXD_3 ⁇ 63:0> rx_coded ⁇ 256:193>, indicating that the 256th bit to the 193rd bit of the target code block are respectively used as the 63rd bit to the 63rd bit of the data block of the third group of code stream blocks 0 bits.
  • Decoding method two based on the type of the target code block, determine the type of the target code block as a control code block, the data unit of the target code block includes a type indication and code block content, the type indication includes 2 n bits, and the 2 n bits 1 bit in is used to indicate the type of a group of code stream blocks corresponding to this bit in 2 n groups of code stream blocks, and the content of the code block includes 2 n bit groups;
  • the bits corresponding to the block and the bit groups corresponding to the 2 n groups of code stream blocks in the content of the code block obtain the control block of the 2 n groups of code stream blocks, and the bits corresponding to the 2 n groups of code stream blocks in the type indication correspond to the code block content
  • the bit groups corresponding to the 2 n groups of code stream blocks are first decoded to obtain data blocks of the 2 n groups of code stream blocks.
  • the second decoding method is used to perform first decoding on the target code block to obtain 2 n groups of code stream blocks.
  • the control block included in the i-th group of code stream blocks in the 2 n groups of code stream blocks is based on the type, the bit corresponding to the i-th group of code stream blocks in the type indication and the bit corresponding to the i-th group of code stream blocks in the code block content obtained by the bit group, i is an integer greater than or equal to 1 and less than or equal to 2 n or i is an integer greater than or equal to 0 and less than or equal to 2 n -1; the i-th group of code stream blocks in the 2 n groups of code stream blocks include The data block is obtained by first decoding the bit group corresponding to the i-th group of code stream blocks in the code block content based on the bits corresponding to the i-th group of code stream blocks in the type indication.
  • a bit group is
  • the type of the code stream block obtained based on the bit is a data code stream block; when a bit in the type indication is 0, the code stream block obtained based on the bit
  • the type of is a control code stream block.
  • the 2 n bit groups include a first bit group and 2 n ⁇ 1 second bit groups, and the number of bits included in the first bit group is different from the number of bits included in the second bit group.
  • one bit of the type indication corresponds to one bit group of the content of the code block.
  • the structure of the target code block shown in FIG. 5 is taken as an example for description.
  • the type indication includes four bits
  • the code block content includes four bit groups.
  • the first bit indicated by the type corresponds to the first bit group, and the first bit group is the 5th to the 64th bit of the target code block;
  • the second bit indicated by the type corresponds to a second bit group, and the second bit
  • the second bit group corresponding to the bit is the 65th bit to the 128th bit of the target code block;
  • the third bit indicated by the type corresponds to a second bit group, and the second bit group corresponding to the third bit is the target code block.
  • the fourth bit indicated by the type corresponds to a second bit group, and the second bit group corresponding to the fourth bit is the 193rd bit to the 256th bit of the target code block.
  • the type indication includes four bits
  • the code block content includes four bit groups.
  • the first bit indicated by the type corresponds to a second bit group, and the second bit group corresponding to the first bit is the 5th bit to the 67th bit of the target code block;
  • the second bit indicated by the type corresponds to the first Bit group, the first bit group is the 68th bit to the 128th bit of the target code block;
  • the third bit indicated by the type corresponds to a second bit group, and the second bit group corresponding to the third bit is the target code block
  • the fourth bit indicated by the type corresponds to a second bit group, and the second bit group corresponding to the fourth bit is the 193rd bit to the 256th bit of the target code block.
  • the control block of the code stream block obtained based on the type if the bit is 1, the control block of the code stream block obtained based on the type, the bit and the bit group corresponding to the bit is 0x00, based on the The content of the data block of the code stream block obtained by first decoding the bit group corresponding to the bit is the content of the bit group.
  • the obtained control block and data block of the code stream block include but not limited to the following cases B1 to B11.
  • this bit is the first bit that is 0, the first 4 bits of the bit group corresponding to this bit is the BTF part, and the BTF part is 0x8; or this bit is not the first bit that is 0, this bit corresponds to
  • the first 8 bits of the bit group are the BTF part, and the BTF part is 0x78.
  • the BTF part of the bit group corresponding to this bit includes 7 data bytes after it.
  • the control block of the code stream block is 0x01
  • the data block of the code stream block is 64 bits.
  • the 7th bit to the 0th bit of the data block are 0xFB, and the remaining 56 bits are each bit of the 7 data bytes of the bit group corresponding to this bit.
  • LSB is the bit sent first.
  • this bit is the first bit that is 0, and the first 4 bits of the bit group corresponding to this bit are the BTF part, and the BTF part is 0xE; or this bit is not the first bit that is 0, and this bit corresponds to The first 8 bits of the bit group are the BTF part, and the BTF part is 0x1E.
  • the BTF part of the bit group corresponding to this bit includes 8 control bit groups, and each control bit group includes 7 bits.
  • the control block of the code stream block is 0xFF
  • the data block of the code stream block is 64 bits.
  • the 64 bits of the data block are obtained based on 8 control bit groups, wherein every 8 bits of the data block are based on one control bit group.
  • the embodiment of the present application does not limit the manner of obtaining each bit of the data block based on each control bit group, for example, it is obtained according to the IEEE802.3 standard.
  • LSB is the bit sent first.
  • this bit is the first bit that is 0, the first 4 bits of the bit group corresponding to this bit is the BTF part, and the BTF part is 0xB; or this bit is not the first bit that is 0, this bit corresponds to
  • the first 8 bits of the bit group are the BTF part, and the BTF part is 0x4B.
  • the BTF part of the bit group corresponding to this bit includes 3 data bytes, 1 4-bit O code and multiple first filling bits.
  • the control block of the code stream block is 0x01
  • the data block of the code stream block is 64 bits.
  • the 7th to 0th bits of the data block are 0x9C
  • the 31st to 8th bits of the data block are bits of 3 data bytes
  • the remaining 32 bits are obtained based on a plurality of first padding bits.
  • LSB is the bit sent first.
  • the embodiment of the present application does not limit the manner of obtaining the remaining 32 bits based on the multiple first padding bits.
  • this bit is the first bit that is 0, the first 4 bits of the bit group corresponding to this bit is the BTF part, and the BTF part is 0x7; or this bit is not the first bit that is 0, this bit corresponds to
  • the first 8 bits of the bit group are the BTF part, and the BTF part is 0x87.
  • the BTF part of the bit group corresponding to this bit includes a 7-bit termination control word and 7 control bit groups, and each control bit group includes 7 bits.
  • the control block of the code stream block is 0xFF
  • the data block of the code stream block is 64 bits.
  • the 7th bit to the 0th bit of the data block are 0xFD, and the remaining 56 bits are obtained based on 7 control bit groups, wherein, every 8 bits in the remaining 56 bits are obtained based on one control bit group.
  • LSB is the bit sent first.
  • this bit is the first bit that is 0, the first 4 bits of the bit group corresponding to this bit is the BTF part, and the BTF part is 0x9; or this bit is not the first bit that is 0, this bit corresponds to
  • the first 8 bits of the bit group are the BTF part, and the BTF part is 0x99.
  • the BTF part of the bit group corresponding to this bit includes 1 data byte, 1 6-bit termination control word and 6 control bit groups, and each control bit group includes 7 bits.
  • the control block of the code stream block is 0xFE
  • the data block of the code stream block is 64 bits.
  • the 7th to 0th bits of the data block are each bit of the data byte
  • the 15th to 8th bits of the data block are 0xFD
  • the remaining 48 bits are obtained based on 6 control bit groups, wherein each of the remaining 48 bits 8 bits are derived based on a control bit group.
  • LSB is the bit sent first.
  • this bit is the first bit that is 0, the first 4 bits of the bit group corresponding to this bit is the BTF part, and the BTF part is 0xA; or this bit is not the first bit that is 0, this bit corresponds to
  • the first 8 bits of the bit group are the BTF part, and the BTF part is 0xAA.
  • the BTF part of the bit group corresponding to this bit includes 2 data bytes, a 5-bit termination control word and 5 control bit groups, and each control bit group includes 7 bits.
  • the control block of the code stream block is 0xFC
  • the data block of the code stream block is 64 bits.
  • the 15th to 0th bits of the data block are obtained based on each bit of 2 data bytes
  • the 23rd to 16th bits of the data block are 0xFD
  • the remaining 40 bits are obtained based on 5 control bit groups, among which the remaining 40 bits
  • Each 8-bit in is obtained based on a group of control bits.
  • LSB is the bit sent first.
  • this bit is the first bit that is 0, the first 4 bits of the bit group corresponding to this bit is the BTF part, and the BTF part is 0x4; or this bit is not the first bit that is 0, this bit corresponds to
  • the first 8 bits of the bit group are the BTF part, and the BTF part is 0xB4.
  • the BTF part of the bit group corresponding to this bit includes 3 data bytes, a 4-bit termination control word and 4 control bit groups, and each control bit group includes 7 bits.
  • the control block of the code stream block is 0xF8, and the data block of the code stream block is 64 bits.
  • the 23rd to 0th bits of the data block are obtained based on each bit of the 3 data bytes, the 31st to 24th bits of the data block are 0xFD, and the remaining 32 bits are obtained based on 4 control bit groups, among which the remaining 32 bits
  • Each 8-bit in is obtained based on a group of control bits.
  • LSB is the bit sent first.
  • this bit is the first bit that is 0, the first 4 bits of the bit group corresponding to this bit is the BTF part, and the BTF part is 0xC; or this bit is not the first bit that is 0, this bit corresponds to
  • the first 8 bits of the bit group are the BTF part, and the BTF part is 0xCC.
  • the BTF part of the bit group corresponding to this bit includes 4 data bytes, a 3-bit termination control word and 3 control bit groups, and each control bit group includes 7 bits.
  • the control block of the code stream block is 0xF0
  • the data block of the code stream block is 64 bits.
  • the 31st to 0th bits of the data block are obtained based on each bit of 4 data bytes, the 39th to 32nd bits of the data block are 0xFD, and the remaining 24 bits are obtained based on 3 control bit groups, among which the remaining 24 bits
  • Each 8-bit in is obtained based on a group of control bits.
  • LSB is the bit sent first.
  • this bit is the first bit that is 0, the first 4 bits of the bit group corresponding to this bit is the BTF part, and the BTF part is 0x2; or this bit is not the first bit that is 0, this bit corresponds to
  • the first 8 bits of the bit group are the BTF part, and the BTF part is 0xD2.
  • the BTF part of the bit group corresponding to this bit includes 5 data bytes, a 2-bit termination control word and 2 control bit groups, and each control bit group includes 7 bits.
  • the control block of the code stream block is 0xE0
  • the data block of the code stream block is 64 bits.
  • the 39th to 0th bits of the data block are obtained based on each bit of the 5 data bytes, the 47th to 40th bits of the data block are 0xFD, and the remaining 16 bits are obtained based on 2 control bit groups, of which the remaining 16 bits
  • Each 8-bit in is based on a group of control bits.
  • LSB is the bit sent first.
  • this bit is the first bit that is 0, and the first 4 bits of the bit group corresponding to this bit are the BTF part, and the BTF part is 0x1; or this bit is not the first bit that is 0, and this bit corresponds to The first 8 bits of the bit group are the BTF part, and the BTF part is 0xE1.
  • the BTF part of the bit group corresponding to this bit includes 6 data bytes, a 1-bit termination control word and a 7-bit control bit group.
  • the control block of the code stream block is 0xC0
  • the data block of the code stream block is 64 bits.
  • the 47th to 0th bits of the data block are obtained based on the respective bits of the 6 data bytes, the 55th to 48th bits of the data block are 0xFD, and the remaining 8 bits are obtained based on the control bit group.
  • LSB is the bit sent first.
  • this bit is the first bit that is 0, the first 4 bits of the bit group corresponding to this bit is the BTF part, and the BTF part is 0xF; or this bit is not the first bit that is 0, this bit corresponds to
  • the first 8 bits of the bit group are the BTF part, and the BTF part is 0xFF.
  • the BTF part of the bit group corresponding to this bit includes 7 data bytes after it.
  • the control block of the code stream block is 0x80
  • the data block of the code stream block is 64 bits.
  • the 55th to 0th bits of the data block are obtained based on the respective bits of the 7 data bytes, and the 63rd to 56th bits of the data block are 0xFD.
  • LSB is the bit sent first.
  • the control block of 2 n groups of code stream blocks is obtained based on the bit group corresponding to 2 n groups of code stream blocks in the type and type indication and the bit group corresponding to 2 n groups of code stream blocks in the content of the code block, based on
  • the bits corresponding to the 2 n groups of code stream blocks in the type indication are first decoded to obtain the data blocks of the 2 n groups of code stream blocks in the code block content corresponding to the 2 n groups of code stream blocks, including: based on 2 n
  • the bit group obtains 2 n third bit groups of 64 bits, and obtains the control block of 2 n groups of code stream blocks based on the bits corresponding to 2 n groups of code stream blocks in the type and type indication and 2 n third bit groups.
  • the bits in the type indication corresponding to the 2 n groups of code stream blocks are first decoded on the 2 n third bit groups to obtain data blocks of the 2 n groups of code stream blocks.
  • the bit group corresponding to the bit includes a 4-bit BTF part
  • the 8-bit BTF part is obtained based on the 4-bit BTF part to obtain a third bit group.
  • query the IEEE802.3 standard based on the 4-bit BTF part to obtain the 8-bit BTF part or query the correspondence table between the 4-bit BTF part and the 8-bit BTF part based on the 4-bit BTF part to obtain the 8-bit BTF part.
  • the 8-bit BTF part corresponding to the 4-bit BTF part is included in the IEEE802.3 standard, or the 8-bit BTF part corresponding to the 4-bit BTF part is included in the correspondence table, the 8-bit BTF part As part of the obtained 8-bit BTF.
  • the 8-bit BTF part corresponding to the 4-bit BTF part is not included in the IEEE802.3 standard, or the 8-bit BTF part corresponding to the 4-bit BTF part is not included in the correspondence table, mark the 4-bit BTF part BTF part to get the 8-bit BTF part.
  • the embodiment of the present application does not limit the way of marking the 4-bit BTF part.
  • the 4-bit BTF part is used as the 3rd bit to the 0th bit, and the 7th bit to the 4th bit are all set to 0.
  • the control block of the code stream block obtained based on the third bit group is 0xFF, and the data block is 0xFEFEFEFE.
  • the control block of the code stream block is obtained based on the type, the bit and the bit group corresponding to the bit, and the bit group corresponding to the bit is first decoded based on the bit
  • Obtain the data block of the code stream block including: query the 8-bit BTF part based on the 4-bit BTF part included in the bit group corresponding to the bit, and in the case of query failure, set the control block of the code stream block to 0xFF, and set the code stream
  • the data block of the block is set to 0xFEFEFE.
  • the principle of querying the 8-bit BTF part based on the 4-bit BTF part is the same as the query method in the above related content, and will not be repeated here.
  • Decoding method three based on the type and data unit of the target code block, determine the type of the target code block as an error code block; obtain the control block and data block of 2 n groups of code stream blocks, and the 2 n groups of code stream blocks are all error code streams piece.
  • the data unit includes a type indication, and the type and type indication are used to indicate that the target code block is an error code block; the control block included in each group of code stream blocks in the 2 n groups of code stream blocks is the first value, and the 2 n groups of code stream blocks include The data blocks included in each group of code stream blocks in the stream blocks are the second value, and the first value and the second value are used to indicate that the code stream block is an error code stream block.
  • the type of the target code block is 0, the type indication is 1111, and the target code block is an error code block, then the control block included in each group of code stream blocks in the 2n groups of code stream blocks obtained through the first decoding is 0xFF, 2 The data blocks included in each group of code stream blocks in n groups of code stream blocks are all 0xFEFEFEFE.
  • the decoding method provided by the embodiment of the present application can first decode different types of target code blocks to obtain 2 n sets of code stream blocks, the method has wide applicability.
  • the first decoding is performed on the target code block to obtain 2n groups of code stream blocks, including: obtaining error detection based on the type and data unit of the target code block Result; according to the error detection result and the type and data unit of the target code block, the target code block is first decoded, and 2 n groups of code stream blocks are obtained. That is to say, the 2n groups of code stream blocks are obtained by first decoding the target code block according to the error detection result and the type and data unit of the target code block, and the error detection result is obtained based on the type and data unit of the target code block.
  • the error detection result is obtained based on the type and data unit of the target code block, including: obtaining the content and content order of the target code block based on the type and data unit of the target code block, and obtaining the error detection result based on the content and content order of the target code block Test results.
  • the content order of the target code block is at least one case in the third error case set, the content order of the target code block is wrong, and when the content order of the target code block is not any of the third error case set In this case, the content sequence of the object code block is correct.
  • the content of the target code block is at least one situation in the fourth error case set
  • the content of the target code block is wrong
  • the content of the target code block is not any situation in the fourth error case set
  • the content of the object code block is correct.
  • the target code block is a control code block
  • the target code block includes four bit groups as an example for illustration.
  • the third set of error conditions includes but is not limited to There are 4 situations as follows:
  • the latter bit group includes other contents except data bytes.
  • the latter bit group includes other contents except the idle control word (/I/) or sequence ordered set control word (/O/).
  • the latter group of bits includes a data byte or a termination control word.
  • bit group is taken as an example for illustration, and the fourth set of error conditions includes but is not limited to the following four situations:
  • the initial control word is followed by other content except data bytes.
  • the termination control word is followed by other content except the idle control word or the sequence ordered set control word.
  • the idle control word or the sequence ordered set control word is followed by a data byte or a termination control word.
  • the error detection result includes the content sequence error or content error of the target code block
  • the target code block is first decoded according to the error detection result and the type and data unit of the target code block to obtain 2n groups
  • the code stream block includes: converting the target code block to obtain a second code block, performing first decoding on the second code block according to the type and data unit of the second code block to obtain 2 n groups of code stream blocks. That is, 2 n groups of code stream blocks are obtained by first decoding the second code block according to the type and data unit of the second code block, and the second code block is obtained by converting the target code block and has the same number of bits as the target code block the same code block.
  • converting the target code block to obtain the second code block includes: converting the bit group whose content sequence is wrong or whose content is wrong in the target code block to an error control word;
  • the second code block is obtained based on the error control word and the bit groups with correct sequence and correct content in the target code block.
  • the first bit group is converted into a first error control word
  • the first bit group is a bit group whose content sequence is wrong or whose content is wrong.
  • the second bit group is converted into a second error control word, where the second bit group is a bit group whose contents are in the wrong order or whose content is wrong.
  • the converted second code block is a control code block, and the second code block may be decoded in the second decoding manner.
  • the error detection result includes the content sequence error or content error of the target code block
  • the target code block is first decoded according to the error detection result and the type and data unit of the target code block to obtain 2 n A group of code stream blocks, including: first decoding the target code block based on the type and data unit of the target code block to obtain 2 n groups of first code stream blocks, and converting 2 n groups of first code stream blocks to obtain 2 n groups of codes flow block. That is to say, 2 n sets of code stream blocks are obtained based on converting 2 n sets of first code stream blocks, and 2 n sets of first code stream blocks are obtained by first decoding the target code block based on the type and data unit of the target code block .
  • converting 2 n sets of first code stream blocks to obtain 2 n sets of code stream blocks including: for 2 n sets of first code stream blocks, code stream blocks obtained based on bit groups with incorrect content order or wrong content , convert the code stream block into an error code stream block.
  • the control block of the error code stream block is 0xFF
  • the data block is 0xFEFEFEFE.
  • the target code block is first decoded to obtain 2 n sets of code stream blocks including control blocks and data blocks, without transcoding the target code block to obtain 2 n 66-bit code blocks , and then decode 2 n 66-bit code blocks to obtain 2 n sets of code stream blocks.
  • the decoding efficiency is improved, and the time delay, power consumption and chip area occupied by the decoding process are all reduced.
  • FIG. 8 is a schematic structural diagram of an encoding device provided by an embodiment of the present application.
  • the device is applied to a first network device, and the first network device is the first network device in the embodiment shown in FIG. 1 above.
  • the encoding device shown in FIG. 8 can perform all or part of the operations performed by the first network device. It should be understood that the device may include more additional modules than those shown or omit some of the modules shown therein, which is not limited in this embodiment of the present application.
  • the device includes:
  • the obtaining module 801 is used to obtain 2 n groups of code stream blocks, any group of code stream blocks includes control blocks and data blocks, and n is an integer greater than 1;
  • the first encoding module 802 is configured to perform first encoding on 2n groups of code stream blocks to obtain target code blocks, the target code blocks include types determined based on 2n groups of code stream blocks and control blocks based on 2n groups of code stream blocks The control block and data block determine the data unit.
  • the type is used to indicate that the target code block is a data code block; the data unit is obtained by first encoding the data blocks of the 2 n groups of code stream blocks based on the order of the 2 n groups of code stream blocks.
  • the type is used to indicate that the target code block is a control code block;
  • the data unit includes a type indication and a code block content, and the code block content is determined based on the order of the control block and the data block of 2n groups of code stream blocks
  • the first encoding is performed on the data blocks of the 2 n groups of code stream blocks, the type indication is obtained based on the control blocks of the 2 n groups of code stream blocks, and the type indication is used to indicate the type of each group of code stream blocks.
  • the target code block is an error code block
  • the error code block includes data for identifying errors
  • the target code block is obtained by processing 2 n sets of code stream blocks based on error detection results, and the error detection results are obtained based on the control blocks and data blocks of the 2 n sets of code stream blocks.
  • the error detection results include 2 n groups of code stream blocks with wrong content order or wrong content
  • the target code block is based on the code stream blocks with correct content order and correct content in the 2 n groups of code stream blocks and the error
  • the block is obtained by performing the first encoding, and the error block is obtained based on the code stream blocks with wrong content sequence or wrong content in the 2n groups of code stream blocks.
  • control block includes m bits
  • data block includes 8m bits
  • m is a positive integer
  • the value of n is 2, the value of m is 8, and the target code block is 257 bits.
  • the 2n groups of code stream blocks all come from the media independent interface MII.
  • the device further includes: a second encoding module 803, configured to perform second encoding on the target code block according to a forward error correction (FEC) pattern to obtain first data; a sending module 804, configured to Send the first data.
  • FEC forward error correction
  • the encoding device performs the first encoding on 2 n sets of code stream blocks including control blocks and data blocks to obtain the target code block, without performing 64B on each set of code stream blocks in the 2 n sets of code stream blocks /66B encoding to obtain 2 n 66-bit code blocks, and then transcoding the 2 n 66-bit code blocks to obtain the target code block.
  • the encoding efficiency is improved, and the time delay, power consumption, and chip area occupied by the encoding process are all reduced.
  • FIG. 9 is a schematic structural diagram of a decoding device provided by an embodiment of the present application.
  • the device can be applied to a second network device, which is the second network device in the embodiment shown in FIG. 1 above.
  • the decoding apparatus shown in FIG. 9 can perform all or part of the operations performed by the second network device.
  • the device may include more additional modules than those shown or omit some of the modules shown therein, which is not limited in this embodiment of the present application.
  • the device includes:
  • An acquisition module 901 configured to acquire a target code block, where the target code block includes a type and a data unit;
  • the decoding module 902 is configured to perform first decoding on the target code block according to the type and data unit of the target code block, to obtain 2n groups of code stream blocks, any group of code stream blocks includes control blocks obtained based on types and data units and Data block, n is an integer greater than 1.
  • the type is used to indicate that the target code block is a data code block; the data block included in the i-th group of code stream blocks in 2 n groups of code stream blocks is based on the comparison between the data unit and the i-th group code
  • the 8m-length content corresponding to the stream block is obtained by first decoding, m is a positive integer, i is an integer greater than or equal to 1 and less than or equal to 2 n or i is an integer greater than or equal to 0 and less than or equal to 2 n -1.
  • the type is used to indicate that the target code block is a control code block
  • the data unit includes a type indication and code block content
  • the type indication includes 2 n bits
  • 1 bit of the 2 n bits is used for Indicates the type of a group of code stream blocks corresponding to bits in 2 n groups of code stream blocks
  • the code block content includes 2 n bit groups
  • the control block included in the i-th group of code stream blocks in 2 n groups of code stream blocks is based on
  • the type and type indication are obtained from the bits corresponding to the i-th group of code stream blocks and the bit groups corresponding to the i-th group of code stream blocks in the code block content, i is an integer greater than or equal to 1 and less than or equal to 2 n or i is greater than or equal to An integer equal to 0 and less than or equal to 2 n -1; the data block included in the i-th group of code stream blocks in the 2 n group of code stream blocks is based on the bit pair code block content corresponding
  • the 2 n bit groups include a first bit group and 2 n ⁇ 1 second bit groups, and the number of bits included in the first bit group is different from the number of bits included in the second bit group.
  • the data unit includes a type indication, and the type and type indication are used to indicate that the target code block is an error code block;
  • the control block included in each group of code stream blocks in the 2 n groups of code stream blocks is the first value , 2
  • the data blocks included in each group of code stream blocks in the n groups of code stream blocks are the second value, and the first value and the second value are used to indicate that the code stream block is an error code stream block.
  • the acquisition module is configured to receive second data, the second data is obtained based on the first data encoded using the forward error correction (FEC) pattern; perform second decoding on the second data to obtain the target code block, the second decoding is an error correction process.
  • FEC forward error correction
  • the target code block is a code block obtained by performing error correction on the second data but failing to correct the error.
  • the acquisition module 901 is configured to receive second data, the second data is obtained based on the first data encoded using the forward error correction (FEC) pattern; perform second decoding on the second data to obtain The target code block, the second decoding is an error detection but no error correction process.
  • FEC forward error correction
  • the target code block is a code block obtained by detecting errors from the second data but not correcting errors.
  • the 2n groups of code stream blocks are obtained by first decoding the target code block according to the error detection result and the type and data unit of the target code block, and the error detection result is based on the type and data unit of the target code block get.
  • the error detection result includes the content sequence error or content error of the target code block
  • the 2 n groups of code stream blocks perform the first decoding on the second code block according to the type and data unit of the second code block to obtain
  • the second code block is a code block obtained by converting the target code block and having the same number of bits as the target code block.
  • the error detection result includes the content sequence error or content error of the target code block
  • the 2 n groups of code stream blocks are obtained based on converting 2 n groups of first code stream blocks
  • the 2 n groups of first code stream blocks The stream block is obtained by first decoding the target code block based on the type of the target code block and the data unit.
  • control block includes m bits
  • data block includes 8m bits
  • m is a positive integer
  • the value of n is 2, the value of m is 8, and the target code block is 257 bits.
  • the 2n sets of code stream blocks are all in the MII format of the media independent interface.
  • the decoding device provided in the embodiment of the present application first decodes the target code block to obtain 2 n sets of code stream blocks including control blocks and data blocks, without transcoding the target code block to obtain 2 n 66-bit code blocks , and then decode 2 n 66-bit code blocks to obtain 2 n sets of code stream blocks.
  • the decoding efficiency is improved, and the time delay, power consumption and chip area occupied by the decoding process are all reduced.
  • the specific hardware structure of the device in the above embodiment is a network device 1500 as shown in FIG. 10 , which includes a transceiver 1501 , a processor 1502 and a memory 1503 .
  • the transceiver 1501 , the processor 1502 and the memory 1503 are connected through a bus 1504 .
  • the transceiver 1501 is used to receive and send messages
  • the memory 1503 is used to store instructions or program codes
  • the processor 1502 is used to call the instructions or program codes in the memory 1503 so that the device executes the first network in the above method embodiment.
  • Related processing steps of the device or the second network device are related processing steps of the device or the second network device.
  • the network device 1500 in the embodiment of the present application may correspond to the first network device or the second network device in the above method embodiments, and the processor 1502 in the network device 1500 reads the instructions in the memory 1503 or The program code enables the network device 1500 shown in FIG. 10 to perform all or part of the operations performed by the first network device or the second network device.
  • the network device 1500 may also correspond to the above-mentioned devices shown in FIG. 8 and FIG. 9, for example, the acquisition module 801 and the acquisition module 901 involved in FIG. 8 and FIG. 9 are equivalent to the transceiver 1501, the first encoding module 802 and the decoding module 902 processor 1502 .
  • FIG. 11 shows a schematic structural diagram of a network device 2000 provided by an exemplary embodiment of the present application.
  • the network device 2000 shown in FIG. 11 is configured to perform the operations involved in the encoding method shown in FIG. 2 and the operations involved in the decoding method shown in FIG. 7 .
  • the network device 2000 is, for example, a switch, a router, and the like.
  • a network device 2000 includes at least one processor 2001 , a memory 2003 and at least one communication interface 2004 .
  • the processor 2001 is, for example, a general-purpose central processing unit (central processing unit, CPU), a digital signal processor (digital signal processor, DSP), a network processor (network processor, NP), a graphics processing unit (graphics processing unit, GPU), A neural network processor (neural-network processing units, NPU), a data processing unit (data processing unit, DPU), a microprocessor, or one or more integrated circuits for implementing the solution of this application.
  • the processor 2001 includes an application-specific integrated circuit (application-specific integrated circuit, ASIC), a programmable logic device (programmable logic device, PLD) or other programmable logic devices, transistor logic devices, hardware components or any combination thereof.
  • the PLD is, for example, a complex programmable logic device (complex programmable logic device, CPLD), a field-programmable gate array (field-programmable gate array, FPGA), a general array logic (generic array logic, GAL) or any combination thereof. It can realize or execute various logical blocks, modules and circuits described in conjunction with the disclosure of the embodiments of the present invention.
  • the processor may also be a combination that implements computing functions, for example, a combination of one or more microprocessors, a combination of a DSP and a microprocessor, and the like.
  • the network device 2000 further includes a bus.
  • the bus is used to transfer information between the various components of the network device 2000 .
  • the bus may be a peripheral component interconnect standard (PCI for short) bus or an extended industry standard architecture (EISA for short) bus or the like.
  • PCI peripheral component interconnect standard
  • EISA extended industry standard architecture
  • the bus can be divided into address bus, data bus, control bus and so on. For ease of representation, only one thick line is used in FIG. 11 , but it does not mean that there is only one bus or one type of bus.
  • the components of the network device 2000 in FIG. 11 may be connected in other ways besides the bus connection, and the embodiment of the present invention does not limit the connection mode of the components.
  • the memory 2003 is, for example, a read-only memory (read-only memory, ROM) or other types of static storage devices that can store static information and instructions, or a random access memory (random access memory, RAM) or a storage device that can store information and instructions.
  • Other types of dynamic storage devices such as electrically erasable programmable read-only memory (EEPROM), compact disc read-only memory (CD-ROM) or other optical disc storage, optical disc Storage (including Compact Disc, Laser Disc, Optical Disc, Digital Versatile Disc, Blu-ray Disc, etc.), magnetic disk storage medium, or other magnetic storage device, or is capable of carrying or storing desired program code in the form of instructions or data structures and capable of Any other medium accessed by a computer, but not limited to.
  • the memory 2003 exists independently, for example, and is connected to the processor 2001 via a bus.
  • the memory 2003 can also be integrated with the processor 2001.
  • the communication interface 2004 uses any device such as a transceiver for communicating with other devices or a communication network.
  • the communication network can be Ethernet, radio access network (RAN) or wireless local area network (wireless local area networks, WLAN).
  • the communication interface 2004 may include a wired communication interface, and may also include a wireless communication interface.
  • the communication interface 2004 can be an ethernet (ethernet) interface, a fast ethernet (fast ethernet, FE) interface, a gigabit ethernet (gigabit ethernet, GE) interface, an asynchronous transfer mode (asynchronous transfer mode, ATM) interface, a wireless local area network ( wireless local area networks, WLAN) interface, cellular network communication interface or a combination thereof.
  • the Ethernet interface can be an optical interface, an electrical interface or a combination thereof.
  • the communication interface 2004 may be used for the network device 2000 to communicate with other devices.
  • the processor 2001 may include one or more CPUs, such as CPU0 and CPU1 shown in FIG. 11 .
  • Each of these processors may be a single-core (single-CPU) processor or a multi-core (multi-CPU) processor.
  • a processor herein may refer to one or more devices, circuits, and/or processing cores for processing data (eg, computer program instructions).
  • the network device 2000 may include multiple processors, such as the processor 2001 and the processor 2005 shown in FIG. 11 .
  • processors can be a single-core processor (single-CPU) or a multi-core processor (multi-CPU).
  • a processor herein may refer to one or more devices, circuits, and/or processing cores for processing data such as computer program instructions.
  • the network device 2000 may further include an output device and an input device.
  • Output devices communicate with processor 2001 and can display information in a variety of ways.
  • the output device may be a liquid crystal display (liquid crystal display, LCD), a light emitting diode (light emitting diode, LED) display device, a cathode ray tube (cathode ray tube, CRT) display device, or a projector (projector).
  • the input device communicates with the processor 2001 and can receive user input in various ways.
  • the input device may be a mouse, a keyboard, a touch screen device, or a sensing device, among others.
  • the memory 2003 is used to store the program code 2010 for implementing the solution of the present application
  • the processor 2001 can execute the program code 2010 stored in the memory 2003 . That is, the network device 2000 can implement the encoding method or decoding method provided by the method embodiment through the processor 2001 and the program code 2010 in the memory 2003 .
  • One or more software modules may be included in the program code 2010 .
  • the processor 2001 itself may also store program codes or instructions for executing the solutions of the present application.
  • the network device 2000 in the embodiment of the present application may correspond to the first network device or the second network device in the above method embodiments, and the processor 2001 in the network device 2000 reads the program code in the memory 2003
  • the program codes or instructions stored in 2010 or the processor 2001 enable the network device 2000 shown in FIG. 11 to perform all or part of the operations performed by the first network device or the second network device.
  • the network device 2000 may also correspond to the above-mentioned devices shown in FIG. 8 and FIG. 9 , and each functional module in the device shown in FIG. 8 and FIG. 9 is implemented by software of the network device 2000 .
  • the functional modules included in the devices shown in FIG. 8 and FIG. 9 are generated after the processor 2001 of the network device 2000 reads the program code 2010 stored in the memory 2003 .
  • the obtaining module 801 and the obtaining module 901 involved in FIG. 8 and FIG. 9 are equivalent to the communication interface 2004
  • the first encoding module 802 and the decoding module 902 are equivalent to the processor 2001 and/or the processor 2005 .
  • each step of the method shown in FIG. 2 and FIG. 7 is completed by an integrated logic circuit of hardware in the processor of the network device 2000 or an instruction in the form of software.
  • the steps of the methods disclosed in connection with the embodiments of the present application may be directly implemented by a hardware processor, or implemented by a combination of hardware and software modules in the processor.
  • the software module can be located in a mature storage medium in the field such as random access memory, flash memory, read-only memory, programmable read-only memory or electrically erasable programmable memory, register.
  • the storage medium is located in the memory, and the processor reads the information in the memory, and completes the steps of the above method in combination with its hardware. To avoid repetition, no detailed description is given here.
  • FIG. 12 shows a schematic structural diagram of a network device 2100 provided by another exemplary embodiment of the present application.
  • the network device 2100 shown in FIG. 12 is configured to perform all or part of the operations involved in the methods shown in FIGS. 2 and 7 above.
  • the network device 2100 is, for example, a switch, a router, etc., and the network device 2100 may be implemented by a general bus architecture.
  • the network device 2100 includes: a main control board 2110 and an interface board 2130 .
  • the main control board is also called a main processing unit (main processing unit, MPU) or a route processing card (route processor card). , equipment maintenance, protocol processing functions.
  • the main control board 2110 includes: a central processing unit 2111 and a memory 2112 .
  • the interface board 2130 is also called a line interface unit card (line processing unit, LPU), a line card (line card), or a service board.
  • the interface board 2130 is used to provide various service interfaces and implement data packet forwarding.
  • the service interface includes but not limited to Ethernet interface, POS (packet over SONET/SDH) interface, etc., and the Ethernet interface is, for example, flexible Ethernet service interface (flexible ethernet clients, FlexE Clients).
  • the interface board 2130 includes: a central processing unit 2131 , a network processor 2132 , a forwarding entry storage 2134 and a physical interface card (physical interface card, PIC) 2133 .
  • the central processor 2131 on the interface board 2130 is used to control and manage the interface board 2130 and communicate with the central processor 2111 on the main control board 2110 .
  • the network processor 2132 is used to implement message sending processing.
  • the form of the network processor 2132 may be a forwarding chip.
  • the forwarding chip may be a network processor (network processor, NP).
  • the forwarding chip may be implemented by an application-specific integrated circuit (application-specific integrated circuit, ASIC) or a field programmable gate array (field programmable gate array, FPGA).
  • the network processor 2132 is configured to forward the received message based on the forwarding table stored in the forwarding table item memory 2134, and if the destination address of the message is the address of the network device 2100, then send the message to the CPU (such as central processing unit 2131) processing; If the destination address of message is not the address of network equipment 2100, then according to this destination address, find out the next hop and outgoing interface corresponding to this destination address from the forwarding table, and this message is forwarded to The outbound interface corresponding to the destination address.
  • the processing of the uplink message may include: processing of the inbound interface of the message, forwarding table search; the processing of the downlink message may include: forwarding table search and so on.
  • the central processing unit can also perform the function of the forwarding chip, such as implementing software forwarding based on a general-purpose CPU, so that no forwarding chip is needed in the interface board.
  • the physical interface card 2133 is used to implement the interconnection function of the physical layer, through which the original traffic enters the interface board 2130 , and the processed packets are sent out from the physical interface card 2133 .
  • the physical interface card 2133 is also called a daughter card, which can be installed on the interface board 2130, and is responsible for converting the photoelectric signal into a message, checking the validity of the message and forwarding it to the network processor 2132 for processing.
  • the central processor 2131 can also execute the functions of the network processor 2132 , such as implementing software forwarding based on a general-purpose CPU, so that the physical interface card 2133 does not need the network processor 2132 .
  • the network device 2100 includes multiple interface boards.
  • the network device 2100 further includes an interface board 2140
  • the interface board 2140 includes: a central processing unit 2141 , a network processor 2142 , a forwarding entry storage 2144 and a physical interface card 2143 .
  • the functions and implementation methods of the components in the interface board 2140 are the same as or similar to those of the interface board 2130 , and will not be repeated here.
  • the network device 2100 further includes a switching fabric unit 2120 .
  • the SFU 2120 may also be called a switch fabric unit (switch fabric unit, SFU).
  • SFU 2120 is used to complete data exchange between the interface boards.
  • the interface board 2130 and the interface board 2140 may communicate through the SFU 2120 .
  • the main control board 2110 is coupled to the interface board.
  • the main control board 2110, the interface board 2130, the interface board 2140, and the switching fabric board 2120 are connected to the system backplane through the system bus to realize intercommunication.
  • an inter-process communication protocol IPC
  • IPC inter-process communication
  • the network device 2100 includes a control plane and a forwarding plane.
  • the control plane includes a main control board 2110 and a central processing unit 2111.
  • the forwarding plane includes various components for performing forwarding, such as forwarding entry storage 2134, physical interface card 2133, and network processing. device 2132.
  • the control plane executes routers, generates forwarding tables, processes signaling and protocol packets, configures and maintains the status of network devices, and other functions.
  • the control plane sends the generated forwarding tables to the forwarding plane.
  • the network processor 2132 controls The forwarding table issued by the above checks the table and forwards the packets received by the physical interface card 2133.
  • the forwarding table delivered by the control plane may be stored in the forwarding table item storage 2134 .
  • the control plane and the forwarding plane can be completely separated and not on the same network device.
  • main control boards there may be one or more main control boards, and when there are multiple main control boards, it may include the main main control board and the standby main control board. There may be one or more interface boards. The stronger the data processing capability of the network device, the more interface boards it provides. There may also be one or more physical interface cards on the interface board. There may be no SFU, or there may be one or more SFUs. When there are multiple SFUs, they can jointly implement load sharing and redundant backup. Under the centralized forwarding architecture, the network device does not need a switching network board, and the interface board undertakes the processing function of the service data of the entire system.
  • the network device can have at least one SFU, through which the data exchange between multiple interface boards can be realized, and large-capacity data exchange and processing capabilities can be provided. Therefore, the data access and processing capabilities of network devices with a distributed architecture are greater than those with a centralized architecture.
  • the form of the network device can also be that there is only one board, that is, there is no switching fabric board, and the functions of the interface board and the main control board are integrated on this board.
  • the central processing unit and the main control board on the interface board The central processing unit on the board can be combined into one central processing unit on the board to perform the superimposed functions of the two.
  • This form of network equipment has low data exchange and processing capabilities (for example, low-end switches or routers, etc.) Internet equipment). Which architecture to use depends on the specific networking deployment scenario, and there is no limitation here.
  • the network device 2100 corresponds to the devices shown in FIG. 8 and FIG. 9 above.
  • the obtaining module 801 and the obtaining module 901 in the apparatus shown in FIG. 8 and FIG. 9 are equivalent to the physical interface card 2133 or the physical interface card 2143 in the network device 2100 .
  • the first encoding module 802 and the decoding module 902 in the devices shown in FIG. 8 and FIG. 9 are equivalent to at least one of the central processing unit 2111 , the network processor 2132 and the network processor 2142 in the network device 2100 .
  • an embodiment of the present application further provides a communication system, and the system includes: a first network device and a second network device.
  • the first network device is the network device 1500 shown in FIG. 10 or the network device 2000 shown in FIG. 11 or the network device 2100 shown in FIG. 12
  • the second network device is the network device 1500 shown in FIG. 10 or The network device 2000 shown in FIG. 11 or the network device 2100 shown in FIG. 12 .
  • processor may be a central processing unit (CPU), and may also be other general-purpose processors, digital signal processing (digital signal processing, DSP), application specific integrated circuit (application specific integrated circuit, ASIC), field-programmable gate array (field-programmable gate array, FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc.
  • DSP digital signal processing
  • ASIC application specific integrated circuit
  • FPGA field-programmable gate array
  • a general purpose processor may be a microprocessor or any conventional processor or the like. It should be noted that the processor may be a processor supporting advanced RISC machines (ARM) architecture.
  • ARM advanced RISC machines
  • the above-mentioned memory may include a read-only memory and a random-access memory, and provide instructions and data to the processor.
  • Memory may also include non-volatile random access memory.
  • the memory may also store device type information.
  • the memory can be either volatile memory or nonvolatile memory, or can include both volatile and nonvolatile memory.
  • the non-volatile memory can be read-only memory (read-only memory, ROM), programmable read-only memory (programmable ROM, PROM), erasable programmable read-only memory (erasable PROM, EPROM), electrically programmable Erases programmable read-only memory (electrically EPROM, EEPROM) or flash memory.
  • Volatile memory can be random access memory (RAM), which acts as external cache memory. By way of illustration and not limitation, many forms of RAM are available.
  • static random access memory static random access memory
  • dynamic random access memory dynamic random access memory
  • DRAM dynamic random access memory
  • SDRAM synchronous dynamic random access memory
  • double data rate synchronous dynamic random access Memory double data rate SDRAM, DDR SDRAM
  • enhanced synchronous dynamic random access memory enhanced SDRAM, ESDRAM
  • serial link DRAM SLDRAM
  • direct memory bus random access memory direct rambus RAM
  • a computer-readable storage medium at least one program instruction or code is stored in the storage medium, and when the program instruction or code is loaded and executed by a processor, the computer can realize the encoding method in FIG. 2 or the coding method in FIG. 7 the decoding method.
  • the present application provides a computer program (product).
  • the computer program When the computer program is executed by a computer, it can cause a processor or a computer to execute the corresponding steps and/or processes in the above method embodiments.
  • a chip including a processor, configured to call from a memory and execute instructions stored in the memory, so that a communication device installed with the chip executes the methods in the above aspects.
  • Another chip including: an input interface, an output interface, a processor, and a memory, the input interface, the output interface, the processor, and the memory are connected through an internal connection path, and the processor is used to execute the codes in the memory, and when the codes are executed, the processor is configured to perform the methods in the above aspects.
  • a device is also provided, which includes the above-mentioned chip.
  • the device is a network device.
  • the device is a router or a switch or a server.
  • all or part of them may be implemented by software, hardware, firmware or any combination thereof.
  • software When implemented using software, it may be implemented in whole or in part in the form of a computer program product.
  • the computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on the computer, the processes or functions according to the present application will be generated in whole or in part.
  • the computer can be a general purpose computer, a special purpose computer, a computer network, or other programmable devices.
  • the computer instructions may be stored in or transmitted from one computer-readable storage medium to another computer-readable storage medium, for example, the computer instructions may be transmitted from a website, computer, server or data center Transmission to another website site, computer, server, or data center by wired (eg, coaxial cable, optical fiber, DSL) or wireless (eg, infrared, wireless, microwave, etc.) means.
  • the computer-readable storage medium may be any available medium that can be accessed by a computer, or a data storage device such as a server or a data center integrated with one or more available media.
  • the available medium may be a magnetic medium (such as a floppy disk, a hard disk, or a magnetic tape), an optical medium (such as a DVD), or a semiconductor medium (such as a solid state disk (solid state disk, SSD)), etc.
  • the computer program product includes one or more computer program instructions.
  • the methods of embodiments of the present application may be described in the context of machine-executable instructions, such as program modules included in a device executed on a real or virtual processor of a target.
  • program modules include routines, programs, libraries, objects, classes, components, data structures, etc. that perform particular tasks or implement particular abstract data structures.
  • the functionality of the program modules may be combined or divided between the described program modules.
  • Machine-executable instructions for program modules may be executed locally or in distributed devices. In a distributed device, program modules may be located in both local and remote storage media.
  • Computer program codes for implementing the methods of the embodiments of the present application may be written in one or more programming languages. These computer program codes can be provided to processors of general-purpose computers, special-purpose computers, or other programmable data processing devices, so that when the program codes are executed by the computer or other programmable data processing devices, The functions/operations specified in are implemented.
  • the program code may execute entirely on the computer, partly on the computer, as a stand-alone software package, partly on the computer and partly on a remote computer or entirely on the remote computer or server.
  • computer program codes or related data may be carried by any appropriate carrier, so that a device, apparatus or processor can perform various processes and operations described above.
  • Examples of carriers include signals, computer readable media, and the like.
  • Examples of signals may include electrical, optical, radio, sound, or other forms of propagated signals, such as carrier waves, infrared signals, and the like.
  • a machine-readable medium may be any tangible medium that contains or stores a program for or related to an instruction execution system, apparatus, or device.
  • a machine-readable medium can be a machine-readable signal medium or a machine-readable storage medium.
  • a machine-readable medium may include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any suitable combination thereof. More detailed examples of machine-readable storage media include electrical connections with one or more wires, portable computer disks, hard disks, random storage access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash), optical storage, magnetic storage, or any suitable combination thereof.
  • the disclosed systems, devices and methods may be implemented in other ways.
  • the device embodiments described above are only illustrative.
  • the division of the modules is only a logical function division. In actual implementation, there may be other division methods.
  • multiple modules or components can be combined or can be Integrate into another system, or some features may be ignored, or not implemented.
  • the mutual coupling or direct coupling or communication connection shown or discussed may be indirect coupling or communication connection through some interfaces, devices or modules, and may also be electrical, mechanical or other forms of connection.
  • the modules described as separate components may or may not be physically separated, and the components displayed as modules may or may not be physical modules, that is, they may be located in one place, or may be distributed to multiple network modules. Part or all of the modules can be selected according to actual needs to achieve the purpose of the solution of the embodiment of the present application.
  • each functional module in each embodiment of the present application may be integrated into one processing module, each module may exist separately physically, or two or more modules may be integrated into one module.
  • the above-mentioned integrated modules can be implemented in the form of hardware or in the form of software function modules.
  • the integrated module is realized in the form of a software function module and sold or used as an independent product, it can be stored in a computer-readable storage medium.
  • the technical solution of the present application is essentially or the part that contributes to the prior art, or all or part of the technical solution can be embodied in the form of software products, and the computer software products are stored in a storage medium
  • several instructions are included to make a computer device (which may be a personal computer, a server, or a network device, etc.) execute all or part of the steps of the methods in the various embodiments of the present application.
  • the aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (read-only memory, ROM), random access memory (random access memory, RAM), magnetic disk or optical disc and other media that can store program codes. .
  • first and second are used to distinguish the same or similar items with basically the same function and function. It should be understood that “first”, “second” and “nth” There are no logical or timing dependencies, nor are there restrictions on quantity or order of execution. It should also be understood that although the following description uses the terms first, second, etc. to describe various elements, these elements should not be limited by the terms. These terms are only used to distinguish one element from another. For example, a first network device could be termed a second network device, and, similarly, a second network device could be termed a first network device, without departing from the scope of the various described examples. Both the first network device and the second network device may be either type of network device, and in some cases, may be separate and distinct network devices.
  • if and “if” may be construed to mean “when” ("when” or “upon”) or “in response to determining” or “in response to detecting”.
  • phrases “if it is determined" or “if [the stated condition or event] is detected” may be construed to mean “when determining” or “in response to determining... ” or “upon detection of [stated condition or event]” or “in response to detection of [stated condition or event]”.
  • determining B according to A does not mean determining B only according to A, and B may also be determined according to A and/or other information.

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  • Error Detection And Correction (AREA)

Abstract

本申请公开了一种编码方法、解码方法、装置、设备、系统及可读存储介质，属于通信技术领域。编码方法包括：获取包括控制块和数据块的2 n组码流块，n为大于1的整数；对2 n组码流块进行第一编码得到目标码块，目标码块包括基于2 n组码流块的控制块确定的类型和基于2 n组码流块的控制块和数据块确定的数据单元。解码方法包括：获取目标码块，根据目标码块的类型和数据单元对目标码块进行第一解码得到2 n组码流块，各组码流块包括基于类型和数据单元得到的控制块和数据块。

Description

编码方法、解码方法、装置、设备、系统及可读存储介质
本申请要求于2022年1月5日提交的申请号为202210005434.5、发明名称为“一种编码方法、装置和芯片”的中国专利申请的优先权，其全部内容通过引用结合在本申请中；本申请还要求于2022年1月30日提交的申请号为202210114840.5、发明名称为“编码方法、解码方法、装置、设备、系统及可读存储介质”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及通信技术领域，尤其涉及一种编码方法、解码方法、装置、设备、系统及可读存储介质。
背景技术
随着通信技术的发展，通过以太网进行报文传输的方式也越来越完善。在传输报文的过程中，来自媒体访问控制(media access control，MAC)层的报文按照固定长度被切分成块，并行进入介质无关接口(media independent interface，MII)。例如，报文被切分成块后并行进入800吉比特(gigabit，G)MII，该800GMII表示传输MAC速率为800吉比特/秒(gigabit per second，Gb/s)的MII。通过MII传输至物理编码子层(physical coding sublayer，PCS)。PCS从MII接收到的码流块包括数据块(transmit data，TXD)和控制块(transmit control，TXC)。其中，TXC和TXD是由来自MAC层的报文流内容经过适配子层(reconciliation sublayer，RS)处理得到的。TXC是控制字，用于标识TXD中对应字节的内容是控制信号还是数据信号，其中控制信号包括报文的开始、终结、错误、空闲等信息。PCS根据TXC/TXD内容进行编码，减少开销，同时可以提供必需的同步、保护功能。
相关技术中，PCS对来自MII的各组码流块进行64比特(bit，B)/66B编码，编码得到66bit码块，该66bit码块为数据码块或控制码块，若为控制码块，该66bit码块包括具备4bit汉明距离保护的字段。当采用高速物理链路进行数据传输时，将每四个66bit码块转码为一个长度为257bit的256B/257B编码的码块，对257bit码块进行前向纠错(forward error correction，FEC)编码，传输FEC编码得到的FEC码字。
当存在不可纠正的FEC码字时，由于该FEC码字中误码的数量较多且位置不固定，66bit码块中具备汉明距离保护的字段无法保证误码的可靠识别；又由于可以通过FEC标错来实现误码的可靠识别，因此误码识别无需通过66bit码块中具备汉明距离保护的字段实现。在此基础上，又由于PCS中绝大多数处理是基于257bit码块进行的，因此64B/66B编码过程不再必要。若保留64B/66B编码过程，随之而来的转码过程将带来不必要的时延、功耗和芯片面积占用。
发明内容
本申请提出一种编码方法、解码方法、装置、设备、系统及可读存储介质，用于提高编 解码效率。
第一方面，提供了一种编码方法，所述方法包括：获取2 n组码流块，任一组码流块包括控制块和数据块，所述n为大于1的整数；对所述2 n组码流块进行第一编码，得到目标码块，所述目标码块包括基于所述2 n组码流块的控制块确定的类型和基于所述2 n组码流块的控制块和数据块确定的数据单元。
由于对包括控制块和数据块的2 n组码流块进行第一编码能够得到目标码块，而不必对2 n组码流块中的每组码流块进行64B/66B编码得到2 n个66比特码块，再对2 n个66比特码块进行转码得到目标码块，编码效率得以提高，编码过程所带来的时延、功耗和芯片面积占用都得以降低。
在一种可能的实现方式中，所述类型用于指示所述目标码块为数据码块；所述数据单元基于所述2 n组码流块的顺序对所述2 n组码流块的数据块进行所述第一编码得到。
在一种可能的实现方式中，所述类型用于指示所述目标码块为控制码块；所述数据单元包括类型指示和码块内容，所述码块内容基于所述2 n组码流块的控制块和数据块确定的顺序对所述2 n组码流块的数据块进行所述第一编码得到，所述类型指示基于所述2 n组码流块的控制块得到，所述类型指示用于指示各组码流块的类型。
在一种可能的实现方式中，所述目标码块为错误码块，所述错误码块中包括用于标识错误的数据。由于本申请的编码方法能够对不同类型的码流块进行第一编码以得到目标码块，该方法的适用性较广。
在一种可能的实现方式中，所述目标码块基于错误检测结果对所述2 n组码流块进行处理得到，所述错误检测结果基于所述2 n组码流块的控制块和数据块得到。通过对存在错误的码流块进行处理，再得到目标码块，使得后续进行数据传输时存在错误的数据能够与正确的数据区分开来，保证数据的可靠性。
在一种可能的实现方式中，所述错误检测结果包括所述2 n组码流块的内容顺序错误或内容错误，所述目标码块基于所述2 n组码流块中内容顺序正确且内容正确的码流块以及错误块进行所述第一编码得到，所述错误块基于所述2 n组码流块中内容顺序错误或内容错误的码流块得到。
在一种可能的实现方式中，所述控制块包括m比特，所述数据块包括8m比特，所述m为正整数。
在一种可能的实现方式中，所述n的取值为2，所述m的取值为8，所述目标码块为257比特。
在一种可能的实现方式中，所述2 n组码流块均来自介质无关接口MII。
在一种可能的实现方式中，所述得到目标码块之后，还包括：按照FEC码型对所述目标码块进行第二编码，得到第一数据；发送所述第一数据。通过按照FEC码型对目标码块进行第二编码得到第一数据，使得接收端能够对接收的第一数据进行纠错，保证数据传输的准确性。
第二方面，提供了一种解码方法，所述方法包括：获取目标码块，所述目标码块包括类型和数据单元；根据所述目标码块的类型和数据单元，对所述目标码块进行第一解码，得到2 n组码流块，任一组码流块包括基于所述类型和所述数据单元得到的控制块和数据块，所述n为大于1的整数。
由于对目标码块进行第一解码能够得到包括控制块和数据块的2 n组码流块，而不必对目标码块进行转码得到2 n个66比特码块，再对2 n个66比特码块进行解码得到2 n组码流块，解码效率得以提高，解码过程所带来的时延、功耗和芯片面积占用都得以降低。
在一种可能的实现方式中，所述类型用于指示所述目标码块为数据码块；所述2 n组码流块中的第i组码流块包括的数据块是基于对所述数据单元中与所述第i组码流块对应的8m长度的内容进行所述第一解码得到的，所述m为正整数，所述i为大于等于1且小于等于2 n的整数或者所述i为大于等于0且小于等于2 n-1的整数。
在一种可能的实现方式中，所述类型用于指示所述目标码块为控制码块，所述数据单元包括类型指示和码块内容，所述类型指示包括2 n个比特，所述2 n个比特中的1个比特用于指示所述2 n组码流块中与所述比特对应的一组码流块的类型，所述码块内容包括2 n个比特组；
所述2 n组码流块中的第i组码流块包括的控制块是基于所述类型、所述类型指示中与所述第i组码流块对应的比特和所述码块内容中与所述第i组码流块对应的比特组得到的，所述i为大于等于1且小于等于2 n的整数或者所述i为大于等于0且小于等于2 n-1的整数；
所述2 n组码流块中的第i组码流块包括的数据块是基于所述类型指示中与所述第i组码流块对应的比特对所述码块内容中与所述第i组码流块对应的比特组进行所述第一解码得到的。
在一种可能的实现方式中，所述2 n个比特组包括第一比特组和2 n-1个第二比特组，所述第一比特组包括的比特数量和所述第二比特组包括的比特数量不相同。
在一种可能的实现方式中，所述数据单元包括类型指示，所述类型和所述类型指示用于指示所述目标码块为错误码块；所述2 n组码流块中每组码流块包括的控制块为第一值，所述2 n组码流块中每组码流块包括的数据块为第二值，所述第一值和所述第二值用于指示所述码流块为错误码流块。
由于本申请的解码方法能够对不同类型的目标码块进行第一解码以得到2 n组码流块，该方法的适用性较广。
在一种可能的实现方式中，所述获取目标码块，包括：接收第二数据，所述第二数据是基于采用前向纠错FEC码型编码的第一数据获得的；对所述第二数据进行第二解码获取所述目标码块，所述第二解码为纠错处理。
在一种可能的实现方式中，所述目标码块是对所述第二数据进行纠错但未成功纠错所获得的错误码块。由于目标码块是对第二数据进行纠错但未能成功纠错，进而对FEC码字中的码块进行标错后所获得的码块，接收端能够确定基于目标码块得到的数据为错误数据，保证数据的准确性。
在一种可能的实现方式中，所述获取目标码块，包括：接收第二数据，所述第二数据是基于采用前向纠错FEC码型编码的第一数据获得的；对所述第二数据进行第二解码获取所述目标码块，所述第二解码为检错但不纠错处理。
在一种可能的实现方式中，所述目标码块是从所述第二数据检出错误但不纠错所获得的错误码块。
针对本申请提供的解码方法，第二解码操作可以是对码字进行纠错，或者仅检错但不纠错。在第二解码过程中对码字进行纠错的情况下，当判定无法对当前码字进行纠错时(例如错误个数超出纠错能力)，需要对该码字中所有的码块进行标错；或者当在第二解码过程中对码字只进行检错但不纠错的情况下，对于检出错误的码字，需要对该码字中所有的码块进 行标错。
在一种可能的实现方式中，所述2 n组码流块根据错误检测结果以及所述目标码块的类型和数据单元对所述目标码块进行第一解码得到，所述错误检测结果基于所述目标码块的类型和数据单元得到。通过对存在错误的目标码块进行处理，使得接收端能够区分错误数据和正确数据，保证数据的可靠性。
在一种可能的实现方式中，所述错误检测结果包括所述目标码块的内容顺序错误或内容错误，所述2 n组码流块根据第二码块的类型和数据单元对所述第二码块进行第一解码得到，所述第二码块是对所述目标码块进行转换得到的且与所述目标码块比特数相同的码块。
在一种可能的实现方式中，所述错误检测结果包括所述目标码块的内容顺序错误或内容错误，所述2 n组码流块基于对2 n组第一码流块进行转换得到，所述2 n组第一码流块基于所述目标码块的类型和数据单元对所述目标码块进行第一解码得到。
在一种可能的实现方式中，所述控制块包括m比特，所述数据块包括8m比特，所述m为正整数。
在一种可能的实现方式中，所述n的取值为2，所述m的取值为8，所述目标码块为257比特。
在一种可能的实现方式中，所述2 n组码流块均为介质无关接口MII格式。
第三方面，提供了一种编码装置，所述装置包括：
获取模块，用于获取2 n组码流块，任一组码流块包括控制块和数据块，所述n为大于1的整数；
第一编码模块，用于对所述2 n组码流块进行第一编码，得到目标码块，所述目标码块包括基于所述2 n组码流块的控制块确定的类型和基于所述2 n组码流块的控制块和数据块确定的数据单元。
在一种可能的实现方式中，所述类型用于指示所述目标码块为数据码块；所述数据单元基于所述2 n组码流块的控制块和数据块确定的顺序对所述2 n组码流块的数据块进行所述第一编码得到。
在一种可能的实现方式中，所述类型用于指示所述目标码块为控制码块；所述数据单元包括类型指示和码块内容，所述码块内容基于所述2 n组码流块的控制块和数据块确定的顺序对所述2 n组码流块的数据块进行所述第一编码得到，所述类型指示基于所述2 n组码流块的控制块得到，所述类型指示用于指示各组码流块的类型。
在一种可能的实现方式中，所述目标码块为错误码块，所述错误码块中包括用于标识错误的数据。
在一种可能的实现方式中，所述目标码块基于错误检测结果对所述2 n组码流块进行处理得到，所述错误检测结果基于所述2 n组码流块的控制块和数据块得到。
在一种可能的实现方式中，所述错误检测结果包括所述2 n组码流块的内容顺序错误或内容错误，所述目标码块基于所述2 n组码流块中内容顺序正确且内容正确的码流块以及错误块进行所述第一编码得到，所述错误块基于所述2 n组码流块中内容顺序错误或内容错误的码流块得到。
在一种可能的实现方式中，所述控制块包括m比特，所述数据块包括8m比特，所述m为正整数。
在一种可能的实现方式中，所述n的取值为2，所述m的取值为8，所述目标码块为257比特。
在一种可能的实现方式中，所述2 n组码流块均来自介质无关接口MII。
在一种可能的实现方式中，该装置还包括：
第二编码模块，用于按照前向纠错FEC码型对所述目标码块进行第二编码，得到第一数据；发送模块，用于发送所述第一数据。
第四方面，提供了一种解码装置，所述装置包括：
获取模块，用于获取目标码块，所述目标码块包括类型和数据单元；
解码模块，用于根据所述目标码块的类型和数据单元，对所述目标码块进行第一解码，得到2 n组码流块，任一组码流块包括基于所述类型和所述数据单元得到的控制块和数据块，所述n为大于1的整数。
在一种可能的实现方式中，所述类型用于指示所述目标码块为数据码块；所述2 n组码流块中的第i组码流块包括的数据块是基于对所述数据单元中与所述第i组码流块对应的8m长度的内容进行所述第一解码得到的，所述m为正整数，所述i为大于等于1且小于等于2 n的整数或者所述i为大于等于0且小于等于2 n-1的整数。
在一种可能的实现方式中，所述类型用于指示所述目标码块为控制码块；所述数据单元包括类型指示和码块内容，所述类型指示包括2 n个比特，所述2 n个比特中的1个比特用于指示所述2 n组码流块中与所述比特对应的一组码流块的类型，所述码块内容包括2 n个比特组；所述2 n组码流块中的第i组码流块包括的控制块是基于所述类型、所述类型指示中与所述第i组码流块对应的比特和所述码块内容中与所述第i组码流块对应的比特组得到的，所述i为大于等于1且小于等于2 n的整数或者所述i为大于等于0且小于等于2 n-1的整数；所述2 n组码流块中的第i组码流块包括的数据块是基于所述类型指示中与所述第i组码流块对应的比特对所述码块内容中与所述第i组码流块对应的比特组进行所述第一解码得到的。
在一种可能的实现方式中，所述2 n个比特组包括第一比特组和2 n-1个第二比特组，所述第一比特组包括的比特数量和所述第二比特组包括的比特数量不相同。
在一种可能的实现方式中，所述数据单元包括类型指示，所述类型和所述类型指示用于指示所述目标码块为错误码块；所述2 n组码流块中每组码流块包括的控制块为第一值，所述2 n组码流块中每组码流块包括的数据块为第二值，所述第一值和所述第二值用于指示所述码流块为错误码流块。
在一种可能的实现方式中，所述获取模块，用于接收第二数据，所述第二数据是基于采用前向纠错FEC码型编码的第一数据获得的；对所述第二数据进行第二解码获取所述目标码块，所述第二解码为纠错处理。
在一种可能的实现方式中，所述目标码块是对所述第二数据进行纠错但未成功纠错所获得的码块。
在一种可能的实现方式中，所述获取模块，用于接收第二数据，所述第二数据是基于采用前向纠错FEC码型编码的第一数据获得的；对所述第二数据进行第二解码获取所述目标码块，所述第二解码为检错但不纠错处理。
在一种可能的实现方式中，所述目标码块是从所述第二数据检出错误但不纠错所获得的错误码块。
在一种可能的实现方式中，所述2 n组码流块根据错误检测结果以及所述目标码块的类型和数据单元对所述目标码块进行所述第一解码得到，所述错误检测结果基于所述目标码块的类型和数据单元得到。
在一种可能的实现方式中，所述错误检测结果包括所述目标码块的内容顺序错误或内容错误，所述2 n组码流块根据第二码块的类型和数据单元对所述第二码块进行所述第一解码得到，所述第二码块是对所述目标码块进行转换得到的且与所述目标码块比特数相同的码块。
在一种可能的实现方式中，所述错误检测结果包括所述目标码块的内容顺序错误或内容错误，所述2 n组码流块基于对2 n组第一码流块进行转换得到，所述2 n组第一码流块基于所述目标码块的类型和数据单元对所述目标码块进行所述第一解码得到。
在一种可能的实现方式中，所述控制块包括m比特，所述数据块包括8m比特，所述m为正整数。
在一种可能的实现方式中，所述n的取值为2，所述m的取值为8，所述目标码块为257比特。
在一种可能的实现方式中，所述2 n组码流块均为介质无关接口MII格式。
第五方面，提供了一种网络设备，包括处理器，处理器与存储器耦合，存储器中存储有至少一条程序指令或代码，至少一条程序指令或代码由处理器加载并执行，以使网络设备实现第一方面中任一的编码方法，或者实现第二方面中任一的解码方法。
第六方面，提供了一种计算机可读存储介质，存储介质中存储有至少一条程序指令或代码，程序指令或代码由处理器加载并执行时以使计算机实现第一方面中任一的编码方法，或者实现第二方面中任一的解码方法。
第七方面，提供了一种通信系统，所述系统包括第一网络设备和第二网络设备，所述第一网络设备用于执行第一方面中任一的编码方法，所述第二网络设备用于执行第二方面中任一的解码方法。
第八方面，提供了另一种通信装置，该装置包括：收发器、存储器和处理器。其中，该收发器、该存储器和该处理器通过内部连接通路互相通信，该存储器用于存储指令，该处理器用于执行该存储器存储的指令，以控制收发器接收信号，并控制收发器发送信号，并且当该处理器执行该存储器存储的指令时，使得该处理器执行第一方面中任一的编码方法，或者执行第二方面中任一的解码方法。
示例性地，所述处理器为一个或多个，所述存储器为一个或多个。
示例性地，所述存储器可以与所述处理器集成在一起，或者所述存储器与处理器分离设置。
在具体实现过程中，存储器可以为非瞬时性(non-transitory)存储器，例如只读存储器(read only memory，ROM)，其可以与处理器集成在同一块芯片上，也可以分别设置在不同的芯片上，本申请对存储器的类型以及存储器与处理器的设置方式不做限定。
第九方面，提供了一种计算机程序产品，所述计算机程序产品包括：计算机程序代码，当所述计算机程序代码被计算机运行时，使得所述计算机执行第一方面中任一的编码方法，或者执行第二方面中任一的解码方法。
第十方面，提供了一种芯片，包括处理器，用于从存储器中调用并运行所述存储器中存储的指令，使得安装有所述芯片的通信设备执行第一方面中任一的编码方法，或者执行第二 方面中任一的解码方法。
第十一方面，提供另一种芯片，包括：输入接口、输出接口、处理器和存储器，所述输入接口、输出接口、所述处理器以及所述存储器之间通过内部连接通路相连，所述处理器用于执行所述存储器中的代码，当所述代码被执行时，所述处理器用于执行第一方面中任一的编码方法，或者执行第二方面中任一的解码方法。
附图说明
图1是本申请实施例提供的一种编码方法和解码方法的实施环境示意图；
图2是本申请实施例提供的一种编码方法的流程图；
图3是本申请实施例提供的一种得到目标码块的过程示意图；
图4是本申请实施例提供的一种目标码块的结构示意图；
图5是本申请实施例提供的另一种目标码块的结构示意图；
图6是本申请实施例提供的另一种目标码块的结构示意图；
图7是本申请实施例提供的一种解码方法的流程图；
图8是本申请实施例提供的一种编码装置的结构示意图；
图9是本申请实施例提供的一种解码装置的结构示意图；
图10是本申请实施例提供的一种网络设备的结构示意图；
图11是本申请实施例提供的另一种网络设备的结构示意图；
图12是本申请实施例提供的另一种网络设备的结构示意图。
具体实施方式
本申请的实施方式部分使用的术语仅用于对本申请的实施例进行解释，而非旨在限定本申请。下面结合附图，对本申请的实施例进行描述。
以太网作为一种局域网技术，应用范围越来越广。100吉比特以太网(gigabit ethernet，GE)以来，采用单通道25Gb/s的传输速率进行数据传输。为了能够纠正接收的数据中的误码，物理层引入了FEC编码，进而传输编码得到的FEC码字。例如采用100G通道进行数据传输时，发送端可以采用里德-所罗门(Reed-Solomon，RS)(528，514)对原始数据进行FEC编码，编码得到的一个RS码字块包括5140比特的有效载荷和140比特的校验码。由于校验码的存在，对于在相同时间内传输相同有效载荷所需要的传输速率而言，传输FEC码字所需的传输速率高于传输原始数据所需的传输速率。
为了降低传输FEC码字所需的传输速率，以太网标准上采用了转码，以通过降低FEC编码前的码块的开销来实现降低传输FEC码字所需的传输速率。例如，将每四个64B/66B编码的码块转码为一个256B/257B编码的码块。由于一个257比特码块的开销低于四个66比特码块的开销，从而传输基于257比特码块得到的FEC码字所需的传输速率相对较低。在采用100G通道进行数据传输时，传输基于转码后的码块得到的FEC码字所需的传输速率为103.125Gb/s，该传输速率与传输未进行FEC编码的66比特码块所需的传输速率相同。
接收端在获取到FEC码字之后，可以对FEC码字进行纠错。由于误码的识别可以通过FEC标错来实现，且PCS中绝大多数处理是基于257比特码块进行的，因此，64B/66B编码过程和相应的转码过程将产生不必要的时延、功耗和芯片面积占用。
对此，本申请实施例提供了一种数据传输方法，以解决上述问题。在本申请实施例中，对包括控制块和数据块的2 n(n为大于1的整数)组码流块进行第一编码得到目标码块，而不必对2 n组码流块中的每组码流块进行64B/66B编码，再对2 n个66比特码块进行转码得到目标码块。由此，编码效率得以提高，编码过程所带来的时延、功耗和芯片面积占用都得以降低。
本申请实施例提供的方法在对目标码块进行第一解码时，可直接对目标码块进行第一解码得到包括控制块和数据块的2 n组码流块，而无需对目标码块进行转码得到2 n个66比特码块，再对2 n个66比特码块进行解码得到2 n组码流块。由此，解码效率得以提高，解码过程所带来的时延、功耗和芯片面积占用都得以降低。
本申请实施例提供的编码方法和解码方法可适用于当前的以太接口或者其他需要传输数据的场景下。以图1所示的实施场景为例，该实施场景包括多个芯片，各个芯片之间能够进行信息的交互，实现数据传输。示例性地，第一网络设备101中设置有芯片102，第二网络设备103中设置有芯片104，芯片102和芯片104均支持FEC编码和FEC解码，第一网络设备101和第二网络设备103之间的信道105能够传输FEC编码的数据。则芯片102可以对2 n组码流块进行第一编码得到目标码块，对目标码块按照第一FEC码型进行第二编码得到第一数据，并通过信道105将第一数据发送给芯片104。示例性地，第一数据在信道105中传输时可能会出现误码，将接收到的数据称为第二数据。芯片104在接收到第二数据后，可以采用第一FEC码型对第二数据进行第二解码得到目标码块，对目标码块进行第一解码得到2 n组码流块。其中，n为大于1的整数，第一FEC码型包括但不限于RS码、博斯-乔赫里-霍克文黑姆(Bose-Chaudhuri-Hocquenghem，BCH)码、汉明码(Hamming code)、扩展BCH码(extended-BCH code)、扩展汉明码(extended-Hamming code)、法尔(fire)码、涡轮(turbo)码、涡轮乘积码(turbo product code，TPC)、阶梯(staircase)码以及低密度奇偶校验(low-density parity-check，LDPC)码中的任一种或者多种的级联组合。
可以理解的是，如图1所示的实施场景可以包括多个网络设备，各个网络设备可以包括至少一个芯片，图1中仅以两个网络设备，各个网络设备包括一个芯片为例进行说明。
结合图1所示的实施场景，本申请实施例提供的编码方法如图2所示。示例性地，本申请实施例提供的编码方法由图1中的芯片102执行，该方法包括但不限于步骤201和步骤202。
步骤201，获取2 n组码流块，任一组码流块包括控制块和数据块，n为大于1的整数。
在一种可能的实现方式中，2 n组码流块均来自MII。关于基于MII获取2 n组码流块的方式，本申请实施例对此不加以限定。例如，MII可以采用电气与电子工程师协会(the Institute of Electrical and Electronics Engineers，IEEE)802.3标准，比如IEEE802.3-2018以及其他版本的IEEE802.3标准定义的MII，获取2 n组码流块。示例性地，n的取值为2，也即获取四组码流块。
示例性地，对于2 n组码流块中的任一组码流块，该任一组码流块的控制块包括m比特，该任一组码流块的数据块包括8m比特，m为正整数。其中，8m表示m的8倍，也可表示为8*m。示例性地，m的取值为8，也即对于任一组码流块而言，该任一组码流块的控制块包括8比特，该任一组码流块的数据块包括64比特。在一种可能的实现方式中，控制块包括的m比特均为控制比特，也即控制块包括m个控制比特；数据块包括的8m比特均为数据，也即数据块包括的8m比特数据。
示例性地，将包括8个控制比特的控制块表示为TXC<7:0>，将包括64比特数据的数据块表示为TXD<63:0>，控制块和数据块的各个比特的顺序均为由最高有效位(most significant bit， MSB)至最低有效位(least significant bit，LSB)。
步骤202，对2 n组码流块进行第一编码，得到目标码块，目标码块包括基于2 n组码流块的控制块确定的类型和基于2 n组码流块的控制块和数据块确定的数据单元。
示例性地，各组码流块的控制块均为8比特，数据块均为64比特，对四组码流块进行第一编码得到一个257比特的目标码块。本申请实施例以n＝2为例进行说明，n为其他值时，可以对每四组码流块执行该第一编码过程，得到多个目标码块。例如，n＝3，也即获取到八组码流块，可以对前四组码流块进行第一编码得到一个目标码块，对后四组码流块进行第一编码得到一个目标码块。
在一种可能的实现方式中，对2 n组码流块进行第一编码，得到目标码块包括但不限于如下编码方式一和编码方式二。
编码方式一，基于2 n组码流块的控制块确定目标码块的类型为数据码块；基于2 n组码流块的顺序对2 n组码流块的数据块进行第一编码，得到数据单元；基于类型和数据单元，得到目标码块。
示例性地，对于采用编码方式一得到的目标码块，类型用于指示目标码块为数据码块；数据单元基于2 n组码流块的顺序对2 n组码流块的数据块进行第一编码得到。
在一种可能的实现方式中，在2 n组码流块的控制块均为第一指定值的情况下，确定目标码块的类型为数据码块，第一指定值用于指示码流块的类型为数据码流块。例如，以各组码流块的控制块均为表示为TXC<7:0>，第一指定值为0x00为例进行说明，在各组码流块的TXC<7:0>均为0x00的情况下，各组码流块的类型均为数据码流块。
在一种可能的实现方式中，基于2 n组码流块的顺序对2 n组码流块的数据块进行第一编码，得到数据单元，包括：基于2 n组码流块的顺序，分别将2 n组码流块的数据块包括的比特作为数据单元的比特，以得到数据单元。
示例性地，以j表示四组码流块的序号，j＝0，1，2或3。TXD_j<63:0>表示第j组码流块的数据块，tx_coded<256:0>表示目标码块，其中，tx_coded<0>表示目标码块的类型，tx_coded<(64j+64):(64j+1)>表示目标码块的第(64j+64)比特至第(64j+1)比特，则tx_coded<256:0>的各个比特如下方表达式1和表达式2所示：
tx_coded<0>＝1  (表达式1)
tx_coded<(64j+64):(64j+1)>＝TXD_j<63:0>，j＝0，1，2或3  (表达式2)
在表达式1中，tx_coded<0>＝1表示类型为数据码块，在表达式2中，tx_coded<(64j+64):(64j+1)>＝TXD_j<63:0>表示分别将各组码流块的数据块的多个比特作为数据单元的多个比特。
例如，当j＝0时，tx_coded<64:1>＝TXD_0<63:0>，表示将第0组码流块的数据块的第63比特至第0比特分别作为目标码块的第64比特至第1比特。当j＝1时，tx_coded<128:65>＝TXD_1<63:0>，表示将第1组码流块的数据块的第63比特至第0比特分别作为目标码块的第128比特至第65比特。当j＝2时，tx_coded<192:129>＝TXD_2<63:0>，表示将第2组码流块的数据块的第63比特至第0比特分别作为目标码块的第192比特至第129比特。当j＝3时，tx_coded<256:193>＝TXD_3<63:0>，表示将第3组码流块的数据块的第63比特至第0比特分别作为目标码块的第256比特至第193比特。
示例性地，图3示出了一种得到目标码块的过程示意图。如图3所示，对于获取到的四组 码流块，各组码流块的控制块均表示为TXC<7:0>，数据块均表示为TXD<63:0>。该四组码流块的TXC<7:0>均为0x00，则目标码块的类型为数据码块。示例性地，目标码块的类型对应目标码块的第0比特，将第0比特赋值为1表示类型为数据码块。关于将第0比特赋值以表示类型为数据码块的方式，本申请实施例不加以限定。基于四组码流块的顺序，分别将四组码流块的数据块的多个比特作为数据单元的多个比特，以得到数据单元。从而，基于类型和数据单元能够得到目标比特。
示例性地，得到的目标码块的结构如图4所示，目标码块的第0比特用于表示目标码块的类型，第0比特赋值为1用于表示目标码块的类型为数据码块。目标码块的第1比特至第256比特用于表示目标码块的数据单元，其中，D0表示第0组码流块的数据块的64比特，D1表示第1组码流块的数据块的64比特，D2表示第2组码流块的数据块的64比特，D3表示第3组码流块的数据块的64比特。
编码方式二，基于2 n组码流块的控制块确定目标码块的类型为控制码块；基于2 n组码流块的控制块，获取2 n组码流块的标识值，标识值用于指示码流块的类型；将2 n组码流块的标识值作为类型指示；基于2 n组码流块的控制块和数据块确定的顺序对2 n组码流块的数据块进行第一编码，得到码块内容；基于类型和数据单元，得到目标码块，其中，数据单元包括类型指示和码块内容。
示例性地，对于采用编码方式二得到的目标码块包括类型和数据单元。其中，类型用于指示目标码块为控制码块；数据单元包括类型指示和码块内容，码块内容基于2 n组码流块的控制块和数据块确定的顺序对2 n组码流块的数据块进行第一编码得到，类型指示基于2 n组码流块的控制块得到，类型指示用于指示各组码流块的类型。示例性地，2 n组码流块的控制块和数据块确定的顺序为2 n组码流块的接收顺序。
在一种可能的实现方式中，2 n组码流块中的至少一组码流块的控制块为第二指定值，通过该第二指定值可确定目标码块的类型为控制码块。第二指定值用于指示码流块的类型为控制码流块，第二指定值与上述第一指定值不同。也就是说，在2 n组码流块中的至少一组码流块的类型为控制码流块的情况下，目标码块的类型为控制码块。例如，以各组码流块的控制块均为表示为TXC<7:0>，第一指定值为0x00为例，在各组码流块中的一组码流块的TXC<7:0>不为0x00的情况下，目标码块为控制码块。
示例性地，对于2 n组码流块中的一组码流块，在该组码流块的类型为数据码流块的情况下，该组码流块的标识值为第三指定值，在该组码流块的类型为控制码流块的情况下，该组码流块的标识值为第四指定值。例如，第三指定值为1，第四指定值为0。示例性地，将2 n组码流块的标识值作为类型指示，包括：按照2 n组码流块的控制块和数据块确定的顺序，将2 n组码流块的标识值分别作为类型指示的各个比特，以得到类型指示。
示例性地，基于2 n组码流块的控制块和数据块确定的顺序对2 n组码流块的数据块进行第一编码，得到码块内容，包括：基于2 n组码流块的控制块和数据块确定的顺序对2 n组码流块的数据块进行第一编码，得到各组码流块经第一编码后的内容，将各组码流块经第一编码后的内容作为码块内容。
在一种可能的实现方式中，对于2 n组码流块中类型为数据码流块(TXC<7:0>＝0x00)的一组码流块，该组码流块经第一编码后的内容为该组码流块的数据块的内容。对于2 n组码流块中类型为控制码流块的一组码流块，根据该组码流块的控制块和数据块的情况，该组码流 块经第一编码后的内容包括但不限于如下情况A1至情况A11。
情况A1，控制块为0x01，数据块的第7比特至第0比特为0xFB，其中LSB为先发送的比特。
示例性地，针对情况A1，该数据块包括1个控制字节和7个数据字节，其中，数据字节也称为八位组(octet)。在该组码流块是第一组控制码流块的情况下，该组码流块经第一编码后的内容为60比特，前4比特为类型域(block type field，BTF)部分，该BTF部分为0x8。在该组码流块不是第一组控制码流块的情况下，该组码流块经第一编码后的内容为64比特，前8比特为BTF部分，该BTF部分为0x78。无论是上述哪种情况，其余56比特为数据块包括的7个数据字节的各个比特。
情况A2，控制块为0xFF，数据块的第(k+7)比特至第k比特为0x06，0x07或0xFE中的至少一种，k＝0，1，2，3，4，5，6或7，其中LSB为先发送的比特。
示例性地，针对情况A2，该数据块包括8个控制字节。在该组码流块是第一组控制码流块的情况下，该组码流块经第一编码后的内容为60比特，前4比特为BTF部分，该BTF部分为0xE。在该组码流块不是第一组控制码流块的情况下，该组码流块经第一编码后的内容为64比特，前8比特为BTF部分，该BTF部分为0x1E。无论上述哪种情况，其余56比特为数据块包括的8个控制字节的第0比特置第6比特。
情况A3，控制块为0x01，数据块的第7比特至第0比特为0x9C，其中LSB为先发送的比特。
示例性地，针对情况A3，该数据块包括1个控制字节和7个数据字节。在该组码流块是第一组控制码流块的情况下，该组码流块经第一编码后的内容为60比特，前4比特为BTF部分，该BTF部分为0xB。在该组码流块不是第一组控制码流块的情况下，该组码流块经第一编码后的内容为64比特，前8比特为BTF部分，该BTF部分为0x4B。无论上述哪种情况，BTF部分后的24比特为数据块的第31比特至第8比特。数据字节后的4比特为O码(O code)，O code可以根据IEEE802.3标准得到。示例性的，其余28比特为多个第一填充比特，其中，多个第一填充比特可以基于数据块的数据字节得到，或者多个第一填充比特均为0。
情况A4，控制块为0xFF，数据块的第7比特至第0比特为0xFD，其中LSB为先发送的比特。
示例性地，针对情况A4，该数据块包括8个控制字节。在该组码流块是第一组控制码流块的情况下，该组码流块经第一编码后的内容为60比特，前4比特为BTF部分，该BTF部分为0x7。在该组码流块不是第一组控制码流块的情况下，该组码流块经第一编码后的内容为64比特，前8比特为BTF部分，该BTF部分为0x87。无论上述哪种情况，BTF部分后的7比特均为0，其余49比特为数据块包括的后7个控制字节的第6比特至第0比特。
情况A5，控制块为0xFE，数据块的第15比特至第8比特为0xFD，其中LSB为先发送的比特。
示例性地，针对情况A5，该数据块包括1个数据字节和7个控制字节。在该组码流块是第一组控制码流块的情况下，该组码流块经第一编码后的内容为60比特，前4比特为BTF部分，该BTF部分为0x9。在该组码流块不是第一组控制码流块的情况下，该组码流块经第一编码后的内容为64比特，前8比特为BTF部分，该BTF部分为0x99。无论上述哪种情况，BTF部分后的8比特为数据块包括的数据字节的各个比特，数据字节后的6比特均为0，其余42比特为数据块包括的后6个控制字节的第6比特至第0比特。
情况A6，控制块为0xFC，数据块的第23比特至第16比特为0xFD，其中，LSB为先发送的比特。
示例性地，针对情况A6，该数据块包括2个数据字节和6个控制字节。在该组码流块是第一组控制码流块的情况下，该组码流块经第一编码后的内容为60比特，前4比特为BTF部分，该BTF部分为0xA。在该组码流块不是第一组控制码流块的情况下，该组码流块经第一编码后的内容为64比特，前8比特为BTF部分，该BTF部分为0xAA。无论上述哪种情况，BTF部分后的16比特为数据块包括的2个数据字节的各个比特，数据字节后的5比特均为0，其余35比特为数据块包括的后5个控制字节的第6比特至第0比特。
情况A7，控制块为0xF8，数据块的第31比特至第24比特为0xFD，其中，LSB为先发送的比特。
示例性地，针对情况A7，该数据块包括3个数据字节和5个控制字节。在该组码流块是第一组控制码流块的情况下，该组码流块经第一编码后的内容为60比特，前4比特为BTF部分，该BTF部分为0x4。在该组码流块不是第一组控制码流块的情况下，该组码流块经第一编码后的内容为64比特，前8比特为BTF部分，该BTF部分为0xB4。无论上述哪种情况，BTF部分后的28比特为数据块包括的3个数据字节的各个比特，数据字节后的4比特均为0，其余28比特为数据块包括的后4个控制字节的第6比特至第0比特。
情况A8，控制块为0xF0，数据块的第39比特至第32比特为0xFD，其中，LSB为先发送的比特。
示例性地，针对情况A8，该数据块包括4个数据字节和4个控制字节。在该组码流块是第一组控制码流块的情况下，该组码流块经第一编码后的内容为60比特，前4比特为BTF部分，该BTF部分为0xC。在该组码流块不是第一组控制码流块的情况下，该组码流块经第一编码后的内容为64比特，前8比特为BTF部分，该BTF部分为0xCC。无论上述哪种情况，BTF部分后的32比特为数据块包括的4个数据字节的各个比特，数据字节后的3比特均为0，其余21比特为数据块包括的后3个控制字节的第6比特至第0比特。
情况A9，控制块为0xE0，数据块的第47比特至第40比特为0xFD，其中，LSB为先发送的比特。
示例性地，针对情况A9，该数据块包括5个数据字节和3个控制字节。在该组码流块是第一组控制码流块的情况下，该组码流块经第一编码后的内容为60比特，前4比特为BTF部分，该BTF部分为0x2。在该组码流块不是第一组控制码流块的情况下，该组码流块经第一编码后的内容为64比特，前8比特为BTF部分，该BTF部分为0xD2。无论上述哪种情况，BTF部分后的32比特为数据块包括的5个数据字节的各个比特，数据字节后的2比特均为0，其余12比特为数据块包括的后2个控制字节的第6比特至第0比特。
情况A10，控制块为0xC0，数据块的第55比特至第48比特为0xFD，其中，LSB为先发送的比特。
示例性地，针对情况A10，该数据块包括6个数据字节和2个控制字节。在该组码流块是第一组控制码流块的情况下，该组码流块经第一编码后的内容为60比特，前4比特为BTF部分，该BTF部分为0x1。在该组码流块不是第一组控制码流块的情况下，该组码流块经第一编码后的内容为64比特，前8比特为BTF部分，该BTF部分为0xE1。无论上述哪种情况，BTF部分后的48比特为数据块包括的6个数据字节的各个比特，数据字节后的1比特为0，其余7比特为数据块包括的最后1个控制字节的第6比特至第0比特。
情况A11，控制块为0x80，数据块的第63比特至第56比特为0xFD，其中，LSB为先发送 的比特。
示例性地，针对情况A11，该数据块包括7个数据字节和1个控制字节。在该组码流块是第一组控制码流块的情况下，该组码流块经第一编码后的内容为60比特，前4比特为BTF部分，该BTF部分为0xF。在该组码流块不是第一组控制码流块的情况下，该组码流块经第一编码后的内容为64比特，前8比特为BTF部分，该BTF部分为0xFF。无论上述哪种情况，其余56比特为数据块包括的7个数据字节的各个比特。
由此，基于2 n组码流块的控制块和数据块确定的顺序，将2 n组码流块经第一编码后的内容作为码块内容。从而，基于类型、类型指示和码块内容能够得到目标码块。
示例性地，j表示四组码流块的序号，j＝0，1，2或3。TXC_j<7:0>表示第j组码流块的控制块，tx_payload<251:0>表示四组码流块经第一编码后的内容，tx_coded<256:0>表示目标码块，其中，tx_coded<0>表示目标码块的类型，tx_coded<j+1>表示目标码块的类型指示，tx_coded<256:5>表示目标码块的码块内容，则tx_coded<256:0>的各个比特如下方表达式3至表达式5所示：
tx_coded<0>＝0  (表达式3)
Figure PCTCN2022142363-appb-000001
tx_coded<256：5>＝tx_payload<251：0>   (表达式5)
在表达式3中，tx_coded<0>＝0表示类型为控制码块。在表达式4中，当TXC_j<7:0>不为0x00时，该j值对应的目标码块的比特为0，当TXC_j<7:0>为0x00时，该j值对应的目标码块的比特为1。在表达式5中，tx_coded<256:5>＝tx_payload<251:0>表示分别将四组码流块经第一编码后的内容的多个比特作为码块内容的多个比特。
示例性地，目标码块的结构如图5所示，图5中的0至3分别表示四组码流块的序号。图5左侧表示获取的四组码流块的类型，C表示控制码流块，D表示数据码流块。图5右侧为对应不同情况得到的目标码块的结构，其中，b表示比特，例如1b表示1比特，4b表示4比特。示例性地，图5中的情况1对应四组码流块的类型均为控制码流块，第一编码得到的目标码块的第0比特为0，第4比特至第1比特均为0；第8比特至第5比特表示为f_0，对应第0组码流块经第一编码后的内容中的BTF部分，第64比特至第9比特对应第0组码流块经第一编码后的内容中的其余内容，也即C0；第72比特至第65比特表示为BTF1，对应第1组码流块经第一编码后的内容中的BTF部分，第128比特至第73比特对应第1组码流块经第一编码后的内容中的其余内容，也即C1；第136比特至第129比特表示为BTF2，对应第2组码流块经第一编码后的内容中的BTF部分，第192比特至第137比特对应第2组码流块经第一编码后的内容中的其余内容，也即C2；第200比特至第193比特表示为BTF3，对应第3组码流块经第一编码后的内容中的BTF部分，第256比特至第201比特对应第四组码流块经第一编码后的内容中的其余内容，也即C3。图5中的其余情况与上述情况1原理相同，例如，对于情况2，目标码块的第68比特至第5比特表示为D0，对应第0组码流块经第一编码后的内容，第72比特至第69比特表示为f_1，对应第1组码流块经第一编码后的内容中的BTF部分，第128比特至第73比特对应第1组码流块经第一编码后的内容中的其余内容，也即C1，此处不再对图5中的其他情况进行赘述。
在一种可能的实现方式中，目标码块为错误码块，错误码块中包括用于标识错误的数据。示例性地，当2 n组码流块中的一组码流块不属于数据码流块，也不属于上述情况A1至情况A11 中的任一种情况时，确定目标码块为错误码块；基于2 n组码流块的控制块，获取2 n组码流块的类型，基于2 n组码流块的类型得到目标码流块的类型指示，类型和类型指示作为错误码块中用于标识错误的数据。例如，目标码块的第0比特对应类型，第1比特至第4比特对应类型指示，将第0比特赋值为0，第1比特至第4比特均赋值为1。
示例性地，目标码块为错误码块时，目标码块的结构如图6所示。图6左侧表示获取的四组码流块的类型，E表示错误码流块。图6右侧为目标码块的结构。目标码块的第0比特为0，第1比特至第4比特均为1，第5比特至第64比特对应基于第一组码流块得到的填充内容，第65比特至第128比特对应基于第二组码流块得到的填充内容，第129比特至第192比特对应基于第三组码流块得到的填充内容，第193比特至第256比特对应基于第四组码流块得到的填充内容。示例性地，填充内容的各个比特均为0。示例性地，将基于第一组码流块得到的填充内容表示为E0，将基于第二组码流块得到的填充内容表示为E1，将基于第三组码流块得到的填充内容表示为E2，将基于第四组码流块得到的填充内容表示为E3。
由于本申请实施例提供的编码方法能够对不同类型的码流块进行第一编码，以得到目标码块，该方法的适用性较广。
在一种可能的实现方式中，对2 n组码流块进行第一编码，得到目标码块，包括：基于2 n组码流块的控制块和数据块得到错误检测结果；基于错误检测结果对2 n组码流块进行处理，对处理后的2 n组码流块进行第一编码，得到目标码块。也就是说，目标码块基于错误检测结果对2 n组码流块进行处理得到，错误检测结果基于2 n组码流块的控制块和数据块得到。
示例性地，基于2 n组码流块的控制块和数据块得到错误检测结果，包括：基于2 n组码流块的控制块和数据块得到2 n组码流块的内容和内容顺序，基于2 n组码流块的内容和内容顺序得到错误检测结果。例如，当2 n组码流块的内容顺序为第一错误情况集合中的至少一种情况时，该2 n组码流块的内容顺序错误，当2 n组码流块的内容顺序不为第一错误情况集合中的任一种情况时，该2 n组码流块的内容顺序正确。又例如，当2 n组码流块的内容为第二错误情况集合中的至少一种情况时，该2 n组码流块的内容错误，当2 n组码流块的内容不为第二错误情况集合中的任一种情况时，该2 n组码流块的内容正确。
在一种可能的实现方式中，以相邻的两组码流块为例进行说明，第一错误情况集合包括但不限于如下4种情况：
(1)在前一组码流块包括起始控制字(/S/)的情况下，后一组码流块包括除数据字节以外的其他内容。
(2)在前一组码流块仅包括数据字节的情况下，后一组码流块包括除数据字节或终止控制字(/T/)以外的其他内容。
(3)在前一组码流块包括终止控制字的情况下，后一组码流块包括除空闲控制字(/I/)或序列有序集控制字(/O/)以外的其他内容。
(4)在前一组码流块包括空闲控制字或序列有序集控制字的情况下，后一组码流块包括数据字节或终止控制字。
在一种可能的实现方式中，以一组码流块为例进行说明，第二错误情况集合包括但不限于如下4种情况：
(1)对于包括起始控制字的码流块，起始控制字后为除数据字节以外的其他内容。
(2)对于包括数据字节的码流块，数据字节后为除数据字节或终止控制字以外的其他内容。
(3)对于包括终止控制字的码流块，终止控制字后为除空闲控制字或序列有序集控制字以外的其他内容。
(4)对于包括空闲控制字或序列有序集控制字的码流块，空闲控制字或序列有序集控制字后为数据字节或终止控制字。
示例性地，错误检测结果包括2 n组码流块的内容顺序错误或内容错误，基于2 n组码流块中内容顺序错误或内容错误的码流块得到错误块，对2 n组码流块中内容顺序正确且内容正确的码流块及错误块进行第一编码得到目标码块。也即，在错误检测结果包括2 n组码流块的内容顺序错误或内容错误的情况下，目标码块基于2 n组码流块中内容顺序正确且内容正确的码流块以及错误块进行第一编码得到，错误块基于2 n组码流块中内容顺序错误或内容错误的码流块得到。示例性地，错误块包括错误控制字(error control character)。
在一种可能的实现方式中，对于内容顺序错误或内容错误的码流块，将该码流块的内容转换为错误控制字，以得到错误块。例如，内容顺序错误或内容错误的码流块为第一组码流块，将该码流块的内容转换为第一错误控制字，该第一错误控制字为60比特，前4比特为0xE，之后每7比特为0x1E。又例如，内容顺序错误或内容错误的码流块为第二组码流块、第三组码流块或第四组码流块中的至少一个，将该码流块的内容转换为第二错误控制字，该第二错误控制字为64比特，前8比特为0x1E，之后每7比特为0x1E。
示例性地，对2 n组码流块中内容顺序正确且内容顺序的码流块及错误块进行第一编码得到目标码块，包括：确定目标码块的类型为控制码块；获取2 n组码流块的标识值，标识值用于指示码流块的类型，将2 n组码流块的标识值作为类型指示；基于2 n组码流块的控制块和数据块确定的顺序对错误块和2 n组码流块中内容顺序正确且内容正确的码流块的数据块进行第一编码，得到码块内容。
例如，基于2 n组码流块的控制块和数据块确定的顺序，对2 n组码流块中内容顺序正确且内容正确的码流块的数据块进行第一编码，得到内容顺序正确且内容正确的码流块经第一编码后的内容，基于内容顺序正确且内容正确的码流块经第一编码后的内容和错误块得到目标码块。关于对内容顺序正确且内容正确的码流块的数据块进行第一编码的方式，请参照前文中对类型为数据码流块的码流块和类型为控制码流块的码流块进行第一编码的相关内容，此处不再赘述。
示例性地，在2 n组码流块中的各组码流块均为内容顺序错误或内容错误的码流块的情况下，基于2 n组码流块得到2 n个错误块，对该2 n个错误块进行第一编码得到目标码块，该目标码块为错误码块。
通过对存在错误的码流块进行处理，使得后续进行数据传输时存在错误的数据能够与正确的数据区分开来，保证数据的可靠性。
示例性地，得到目标码块之后，该方法还包括：按照FEC码型对目标码块进行第二编码，得到第一数据；发送第一数据。关于按照FEC码型对目标码块进行第二编码的方式，本申请实施例不加以限定。通过按照FEC码型对目标码块进行第二编码得到第一数据，使得接收端能够对接收的第一数据进行纠错，保证数据传输的准确性。
本申请实施例提供的编码方法，对包括控制块和数据块的2 n组码流块进行第一编码得到 目标码块，而不必对2 n组码流块中的每组码流块进行64B/66B编码得到2 n个66比特码块，再对2 n个66比特码块进行转码得到目标码块。由此，编码效率得以提高，编码过程所带来的时延、功耗和芯片面积占用都得以降低。
上述介绍了本申请实施例提供的编码方法，下面介绍本申请实施例提供的解码方法。结合图1所示的实施场景，本申请实施例提供的解码方法如图7所示。示例性地，本申请实施例提供的解码方法由图1中的芯片104执行，该方法包括但不限步骤701和步骤702。
步骤701，获取目标码块，目标码块包括类型和数据单元。
示例性地，结合图1的实施场景，芯片102通过信道105向芯片104发送采用FEC码型编码的第一数据，在数据传输的过程中第一数据中可能会出现误码，将该出现误码的数据称为第二数据，芯片104通过信道105接收到该第二数据。
在一种可能的实现方式中，获取目标码块，包括但不限于如下方式A和方式B。
方式A，接收第二数据，第二数据是基于采用FEC码型编码的第一数据获得的；对第二数据进行第二解码获得目标码块，该第二解码为纠错处理。
示例性地，目标码块是对第二数据进行纠错但未成功纠错所获得的错误码块。例如，对第二数据进行第二解码获取目标码块，包括：按照该FEC码型对第二数据进行处理得到第一码字，对该第一码字进行纠错处理，基于纠错处理的结果获取目标码块。
示例性地，芯片104具有FEC解码器的功能，当FEC解码器判定误码的个数超出该FEC解码器的纠错能力时，也就是说，当FEC解码器判定无法对第一码字进行纠错时，标记该第一码字中所有的码块为错误码块。从而，在纠错处理的结果为标记第一码字中所有的码块为错误码块的情况下，获取的目标码块为错误码块。
示例性地，在纠错处理的结果为对第一码字纠错成功的情况下，将基于纠错后的第一码字得到的码块作为获取的目标码块，基于纠错后的第一码字得到的码块为纠错成功的码块。
方式B，接收第二数据，第二数据是基于采用前向纠错FEC码型编码的第一数据获得的；对第二数据进行第二解码获取目标码块，第二解码为检错但不纠错处理。
示例性地，目标码块是从第二数据检出错误但不纠错所获得的错误码块。例如，对第二数据进行第二解码获取目标码块，包括：按照该FEC码型对第二数据进行处理得到第一码字，对第一码字进行仅检错但不纠错(bypass correction)处理；基于检错但不纠错处理的结果获取目标码块。
示例性地，芯片104具有FEC解码器的功能，当FEC解码器检测到第一码字中存在错误时，标记该第一码字中所有的码块为错误码块。从而，在检错但不纠错处理的结果为标记第一码字中所有的码块为错误码块的情况下，获取的目标码块为错误码块。
示例性地，在检错但不纠错处理的结果为第一码字无错误的情况下，将基于第一码字得到的码块作为获取的目标码块，基于第一码字得到的码块为无错误的码块。
示例性地，基于目标码块执行的帧校验序列(frame check sequence，FCS)帧校验失败。例如，目标码块为257比特，前5比特为01111，其余252比特包括但不限于如下三种情况：(1)前4比特为0x1，其余比特中每8比特为0x1E；(2)前248比特中每8比特为0x1E，最后4比特为0x1；(3)各个比特均为0。
步骤702，根据目标码块的类型和数据单元，对目标码块进行第一解码，得到2 n组码流块，任一组码流块包括基于类型和数据单元得到的控制块和数据块，n为大于1的整数。
示例性地，目标码块为257比特，各组码流块的控制块均为8比特，数据块均为64比特。以对一个目标码块进行第一解码得到四组码流块(n＝2)为例进行说明，当获取到多个目标码块时，可以对各个目标码块分别执行该第一解码过程，以得到2 n组码流块。例如，当获取到两个目标码块时，可以对该两个码块分别进行第一解码得到四组码流块，也即，对两个目标码块进行第一解码得到八组码流块。
在一种可能的实现方式中，根据目标码块的类型和数据单元，对目标码块进行第一解码，得到2 n组码流块，包括但不限于如下解码方式一至解码方式三。
解码方式一，基于目标码块的类型，确定目标码块的类型为数据码块，目标码块的数据单元包括2 n个8m长度的内容，m为正整数；基于目标码块的类型得到2 n组码流块的控制块，对数据单元包括的2 n个8m长度的内容分别进行第一解码，得到2 n组码流块的数据块。
示例性地，在类型用于指示目标码块为数据码块的情况下，采用解码方式一对目标码块进行第一解码得到2 n组码流块。该2 n组码流块中的第i组码流块包括的数据块是基于对数据单元中与该第i组码流块对应的8m长度的内容进行第一解码得到的，i为大于等于1且小于等于2 n的整数或者i为大于等于0且小于等于2 n-1的整数。
在一种可能的实现方式中，目标码块的类型为1用于指示目标码块为数据码块，目标码块的数据单元包括四个8m长度的内容，一个8m长度的内容对应一组码流块。示例性地，8m长度为64比特。将四组码流块的控制块均置为0x00，将四个64比特的内容分别作为四组码流块的数据块的内容。
示例性地，j表示四组码流块的序号，j＝0，1，2或3。RXC_j<7:0>表示第j组码流块的控制块，RXD_j<63:0>表示第j组码流块的数据块，rx_coded<256:0>表示目标码块，其中，rx_coded<0>表示目标码块的类型，rx_coded<(64j+64):(64j+1)>表示目标码块的第(64j+64)比特至第(64j+1)比特，则RXC_j<7:0>和RXD_j<63:0>的内容如下方表达式6和表达式7所示：
RXC_j<7:0>＝0x00，j＝0，1，2或3  (表达式6)
RXD_j<63:0>＝rx_coded<(64j+64):(64j+1)>，j＝0，1，2或3    (表达式7)
在表达式6中，RXC_j<7:0>＝0x00表示各组码流块的控制块均为0x00，在表达式7中，RXD_j<63:0>＝rx_coded<(64j+64):(64j+1)>表示将数据单元的每64比特作为一组码流块的数据块的64比特。
例如，当j＝0时，RXD_0<63:0>＝rx_coded<64:1>，表示将目标码块的第64比特至第1比特分别作为第0组码流块的数据块的第63比特至第0比特。当j＝1时，RXD_1<63:0>＝rx_coded<128:65>，表示将目标码块的第128比特至第65比特分别作为第1组码流块的数据块的第63比特至第0比特。当j＝2时，RXD_2<63:0>＝rx_coded<192:129>，表示将目标码块的第192比特至第129比特分别作为第2组码流块的数据块的第63比特至第0比特。当j＝3时，RXD_3<63:0>＝rx_coded<256:193>，表示将目标码块的第256比特至第193比特分别作为第3组码流块的数据块的第63比特至第0比特。
解码方式二，基于目标码块的类型，确定目标码块的类型为控制码块，目标码块的数据单元包括类型指示和码块内容，类型指示包括2 n个比特，所述2 n个比特中的1个比特用于指示2 n组码流块中与该比特对应的一组码流块的类型，码块内容包括2 n个比特组；基于类型、类 型指示中与2 n组码流块对应的比特和码块内容中与2 n组码流块对应的比特组得到2 n组码流块的控制块，基于类型指示中与2 n组码流块对应的比特对码块内容中与2 n组码流块对应的比特组进行第一解码得到2 n组码流块的数据块。
示例性地，在类型用于指示目标码块为控制码块的情况下，采用解码方式二对目标码块进行第一解码得到2 n组码流块。该2 n组码流块中的第i组码流块包括的控制块是基于类型、类型指示中与第i组码流块对应的比特和码块内容中与第i组码流块对应的比特组得到的，i为大于等于1且小于等于2 n的整数或者i为大于等于0且小于等于2 n-1的整数；该2 n组码流块中的第i组码流块包括的数据块是基于类型指示中与第i组码流块对应的比特对码块内容中与第i组码流块对应的比特组进行第一解码得到的。示例性地，比特组为多个比特的集合。
示例性地，当类型指示中的一个比特为1时，基于该比特得到的码流块的类型为数据码流块；当类型指示中的一个比特为0时，基于该比特得到的码流块的类型为控制码流块。
在一种可能的实现方式中，2 n个比特组包括第一比特组和2 n-1个第二比特组，第一比特组包括的比特数量和第二比特组包括的比特数量不相同。示例性地，类型指示的一个比特对应码块内容的一个比特组。例如，以图5示出的目标码块的结构为例进行说明。对于情况1，类型指示包括四个比特，码块内容包括四个比特组。其中，类型指示的第一个比特对应第一比特组，第一比特组为目标码块的第5比特至第64比特；类型指示的第二个比特对应一个第二比特组，该第二个比特对应的第二比特组为目标码块的第65比特至第128比特；类型指示的第三个比特对应一个第二比特组，该第三个比特对应的第二比特组为目标码块的第129比特至第192比特；类型指示的第四个比特对应一个第二比特组，该第四个比特对应的第二比特组为目标码块的第193比特至第256比特。对于情况2，类型指示包括四个比特，码块内容包括四个比特组。其中，类型指示的第一个比特对应一个第二比特组，该第一个比特对应的第二比特组为目标码块的第5比特至第67比特；类型指示的第二个比特对应第一比特组，第一比特组为目标码块的第68比特至第128比特；类型指示的第三个比特对应一个第二比特组，该第三个比特对应的第二比特组为目标码块的第129比特至第192比特；类型指示的第四个比特对应一个第二比特组，该第四个比特对应的第二比特组为目标码块的第193比特至第256比特。其余情况与上述情况1和情况2的原理相同，此处不再赘述。
在一种可能的实现方式中，对于类型指示的一个比特，在该比特为1的情况下，基于类型、该比特和该比特对应的比特组得到的码流块的控制块为0x00，基于该比特对该比特对应的比特组进行第一解码得到的码流块的数据块的内容为比特组的内容。在该比特为0的情况下，根据该比特的位置和该比特对应的比特组的情况，得到的码流块的控制块和数据块包括但不限于如下情况B1至B11。
情况B1，该比特为第一个为0的比特，该比特对应的比特组的前4比特为BTF部分，该BTF部分为0x8；或者该比特不为第一个为0的比特，该比特对应的比特组的前8比特为BTF部分，该BTF部分为0x78。
示例性地，针对情况B1，该比特对应的比特组的BTF部分之后包括7个数据字节。码流块的控制块为0x01，码流块的数据块为64比特。数据块的第7比特至第0比特为0xFB，其余56比特分别为该比特对应的比特组的7个数据字节的各个比特。其中，LSB为先发送的比特。
情况B2，该比特为第一个为0的比特，该比特对应的比特组的前4比特为BTF部分，该BTF部分为0xE；或者该比特不为第一个为0的比特，该比特对应的比特组的前8比特为BTF部分， 该BTF部分为0x1E。
示例性地，针对情况B2，该比特对应的比特组的BTF部分之后包括8个控制比特组，每个控制比特组包括7比特。码流块的控制块为0xFF，码流块的数据块为64比特。数据块的64比特基于8个控制比特组得到，其中，数据块的每8比特基于一个控制比特组。关于基于各个控制比特组得到数据块的各个比特的方式，本申请实施例对此不加以限定，例如，根据IEEE802.3标准得到。示例性地，数据块的第(k+7)比特至第k比特为0x06，0x07或0xFE中的至少一种，k＝0，1，2，3，4，5，6或7。其中，LSB为先发送的比特。
情况B3，该比特为第一个为0的比特，该比特对应的比特组的前4比特为BTF部分，该BTF部分为0xB；或者该比特不为第一个为0的比特，该比特对应的比特组的前8比特为BTF部分，该BTF部分为0x4B。
示例性地，针对情况B3，该比特对应的比特组的BTF部分之后包括3个数据字节，1个4比特的O码和多个第一填充比特。码流块的控制块为0x01，码流块的数据块为64比特。数据块的第7比特至第0比特为0x9C，数据块的第31比特至第8比特为3个数据字节的各个比特，其余32比特基于多个第一填充比特得到。其中，LSB为先发送的比特。关于基于多个第一填充比特得到其余32比特的方式，本申请实施例对此不加以限定。
情况B4，该比特为第一个为0的比特，该比特对应的比特组的前4比特为BTF部分，该BTF部分为0x7；或者该比特不为第一个为0的比特，该比特对应的比特组的前8比特为BTF部分，该BTF部分为0x87。
示例性地，针对情况B4，该比特对应的比特组的BTF部分之后包括1个7比特的终止控制字和7个控制比特组，每个控制比特组包括7比特。码流块的控制块为0xFF，码流块的数据块为64比特。数据块的第7比特至第0比特为0xFD，其余56比特基于7个控制比特组得到，其中，其余56比特中的每8比特基于一个控制比特组得到。其中，LSB为先发送的比特。
情况B5，该比特为第一个为0的比特，该比特对应的比特组的前4比特为BTF部分，该BTF部分为0x9；或者该比特不为第一个为0的比特，该比特对应的比特组的前8比特为BTF部分，该BTF部分为0x99。
示例性地，针对情况B5，该比特对应的比特组的BTF部分之后包括1个数据字节，1个6比特的终止控制字和6个控制比特组，每个控制比特组包括7比特。码流块的控制块为0xFE，码流块的数据块为64比特。数据块的第7比特至第0比特为数据字节的各个比特，数据块的第15比特至第8比特为0xFD，其余48比特基于6个控制比特组得到，其中，其余48比特中的每8比特基于一个控制比特组得到。其中，LSB为先发送的比特。
情况B6，该比特为第一个为0的比特，该比特对应的比特组的前4比特为BTF部分，该BTF部分为0xA；或者该比特不为第一个为0的比特，该比特对应的比特组的前8比特为BTF部分，该BTF部分为0xAA。
示例性地，针对情况B6，该比特对应的比特组的BTF部分之后包括2个数据字节，1个5比特的终止控制字和5个控制比特组，每个控制比特组包括7比特。码流块的控制块为0xFC，码流块的数据块为64比特。数据块的第15比特至第0比特基于2个数据字节的各个比特得到，数据块的第23比特至第16比特为0xFD，其余40比特基于5个控制比特组得到，其中，其余40比特中的每8比特基于一个控制比特组得到。其中，LSB为先发送的比特。
情况B7，该比特为第一个为0的比特，该比特对应的比特组的前4比特为BTF部分，该BTF 部分为0x4；或者该比特不为第一个为0的比特，该比特对应的比特组的前8比特为BTF部分，该BTF部分为0xB4。
示例性地，针对情况B7，该比特对应的比特组的BTF部分之后包括3个数据字节，1个4比特的终止控制字和4个控制比特组，每个控制比特组包括7比特。码流块的控制块为0xF8，码流块的数据块为64比特。数据块的第23比特至第0比特基于3个数据字节的各个比特得到，数据块的第31比特至第24比特为0xFD，其余32比特基于4个控制比特组得到，其中，其余32比特中的每8比特基于一个控制比特组得到。其中，LSB为先发送的比特。
情况B8，该比特为第一个为0的比特，该比特对应的比特组的前4比特为BTF部分，该BTF部分为0xC；或者该比特不为第一个为0的比特，该比特对应的比特组的前8比特为BTF部分，该BTF部分为0xCC。
示例性地，针对情况B8，该比特对应的比特组的BTF部分之后包括4个数据字节，1个3比特的终止控制字和3个控制比特组，每个控制比特组包括7比特。码流块的控制块为0xF0，码流块的数据块为64比特。数据块的第31比特至第0比特基于4个数据字节的各个比特得到，数据块的第39比特至第32比特为0xFD，其余24比特基于3个控制比特组得到，其中，其余24比特中的每8比特基于一个控制比特组得到。其中，LSB为先发送的比特。
情况B9，该比特为第一个为0的比特，该比特对应的比特组的前4比特为BTF部分，该BTF部分为0x2；或者该比特不为第一个为0的比特，该比特对应的比特组的前8比特为BTF部分，该BTF部分为0xD2。
示例性地，针对情况B9，该比特对应的比特组的BTF部分之后包括5个数据字节，1个2比特的终止控制字和2个控制比特组，每个控制比特组包括7比特。码流块的控制块为0xE0，码流块的数据块为64比特。数据块的第39比特至第0比特基于5个数据字节的各个比特得到，数据块的第47比特至第40比特为0xFD，其余16比特基于2个控制比特组得到，其中，其余16比特中的每8比特基于一个控制比特组。其中，LSB为先发送的比特。
情况B10，该比特为第一个为0的比特，该比特对应的比特组的前4比特为BTF部分，该BTF部分为0x1；或者该比特不为第一个为0的比特，该比特对应的比特组的前8比特为BTF部分，该BTF部分为0xE1。
示例性地，针对情况B10，该比特对应的比特组的BTF部分之后包括6个数据字节，1个1比特的终止控制字和1个7比特的控制比特组。码流块的控制块为0xC0，码流块的数据块为64比特。数据块的第47比特至第0比特基于6个数据字节的各个比特得到，数据块的第55比特至第48比特为0xFD，其余8比特基于控制比特组得到。其中，LSB为先发送的比特。
情况B11，该比特为第一个为0的比特，该比特对应的比特组的前4比特为BTF部分，该BTF部分为0xF；或者该比特不为第一个为0的比特，该比特对应的比特组的前8比特为BTF部分，该BTF部分为0xFF。
示例性地，针对情况B11，该比特对应的比特组的BTF部分之后包括7个数据字节。码流块的控制块为0x80，码流块的数据块为64比特。数据块的第55比特至第0比特基于7个数据字节的各个比特得到，数据块的第63比特至第56比特为0xFD。其中，LSB为先发送的比特。
在一些实施例中，基于类型、类型指示中与2 n组码流块对应的比特和码块内容中与2 n组码流块对应的比特组得到2 n组码流块的控制块，基于类型指示中与2 n组码流块对应的比特对码块内容中与2 n组码流块对应的比特组进行第一解码得到2 n组码流块的数据块，包括：基于 2 n个比特组获取2 n个64比特的第三比特组，基于类型、类型指示中与2 n组码流块对应的比特和2 n个第三比特组得到2 n组码流块的控制块，基于类型指示中与2 n组码流块对应的比特对2 n个第三比特组进行第一解码得到2 n组码流块的数据块。
示例性地，对于第一个为0的比特，该比特对应的比特组包括4比特BTF部分，基于该4比特BTF部分获取8比特BTF部分，得到第三比特组。例如，基于该4比特BTF部分查询IEEE802.3标准，以获取8比特BTF部分，或者基于4比特BTF部分查询4比特BTF部分和8比特BTF部分的对应表，以获取8比特BTF部分。
在查询成功的情况下，也即IEEE802.3标准中包括该4比特BTF部分对应的8比特BTF部分，或者对应表中包括该4比特BTF部分对应的8比特BTF部分，将该8比特BTF部分作为获取到的8比特BTF部分。在查询失败的情况下，也即IEEE802.3标准中不包括该4比特BTF部分对应的8比特BTF部分，或者对应表中不包括该4比特BTF部分对应的8比特BTF部分，标记该4比特BTF部分以获取8比特BTF部分。关于标记4比特BTF部分的方式，本申请实施例不加以限定，例如将4比特BTF部分作为第3比特至第0比特，将第7比特至第4比特均置为0。示例性地，在查询失败的情况下，基于该第三比特组得到的码流块的控制块为0xFF，数据块为0xFEFEFEFE。
在另一些实施例中，对于第一个为0的比特，基于类型、该比特和该比特对应的比特组得到码流块的控制块，基于该比特对该比特对应的比特组进行第一解码得到码流块的数据块，包括：基于该比特对应的比特组包括的4比特BTF部分查询8比特BTF部分，在查询失败的情况下，将码流块的控制块置为0xFF，将码流块的数据块置为0xFEFEFEFE。关于基于4比特BTF部分查询8比特BTF部分的方式，与上述相关内容中的查询方式原理相同，此处不再赘述。
解码方式三，基于目标码块的类型和数据单元，确定目标码块的类型为错误码块；得到2 n组码流块的控制块和数据块，2 n组码流块均为错误码流块。
示例性地，数据单元包括类型指示，类型和类型指示用于指示目标码块为错误码块；2 n组码流块中每组码流块包括的控制块为第一值，2 n组码流块中每组码流块包括的数据块为第二值，第一值和第二值用于指示码流块为错误码流块。例如，目标码块的类型为0，类型指示为1111，该目标码块为错误码块，则经第一解码得到的2 n组码流块中每组码流块包括的控制块为0xFF，2 n组码流块中每组码流块包括的数据块均为0xFEFEFEFE。
由于本申请实施例提供的解码方法能够对不同类型的目标码块进行第一解码，以得到2 n组码流块，该方法的适用性较广。
在一种可能的实现方式中，根据目标码块的类型和数据单元，对目标码块进行第一解码，得到2 n组码流块，包括：基于目标码块的类型和数据单元得到错误检测结果；根据错误检测结果以及目标码块的类型和数据单元对目标码块进行第一解码，得到2 n组码流块。也就是说，2 n组码流块根据错误检测结果以及目标码块的类型和数据单元对目标码块进行第一解码得到，错误检测结果基于目标码块的类型和数据单元得到。
示例性地，基于目标码块的类型和数据单元得到错误检测结果，包括：基于目标码块的类型和数据单元得到目标码块的内容和内容顺序，基于目标码块的内容和内容顺序得到错误检测结果。例如，当目标码块的内容顺序为第三错误情况集合中的至少一种情况时，该目标码块的内容顺序错误，当目标码块的内容顺序不为第三错误情况集合中的任一种情况时，该目标码块的内容顺序正确。又例如，当目标码块的内容为第四错误情况集合中的至少一种情 况时，该目标码块的内容错误，当目标码块的内容不为第四错误情况集合中的任一种情况时，该目标码块的内容正确。
在一种可能的实现方式中，以目标码块为控制码块，该目标码块包括四个比特组为例进行说明，对于相邻的两个比特组，第三错误情况集合包括但不限于如下4种情况：
(1)在前一个比特组包括起始控制字(/S/)的情况下，后一个比特组包括除数据字节以外的其他内容。
(2)在前一个比特组仅包括数据字节的情况下，后一个比特组包括除数据字节或终止控制字(/T/)以外的其他内容。
(3)在前一个比特组包括终止控制字的情况下，后一个比特组包括除空闲控制字(/I/)或序列有序集控制字(/O/)以外的其他内容。
(4)在前一个比特组包括空闲控制字或序列有序集控制字的情况下，后一个比特组包括数据字节或终止控制字。
本申请实施例中的控制字的具体含义和取值可参考具体参考IEEE802.3-2018，本申请实施例不再赘述。
在一种可能的实现方式中，以一个比特组为例进行说明，第四错误情况集合包括但不限于如下4种情况：
(1)对于包括起始控制字的比特组，起始控制字后为除数据字节以外的其他内容。
(2)对于包括数据字节的比特组，数据字节后为除数据字节或终止控制字以外的其他内容。
(3)对于包括终止控制字的比特组，终止控制字后为除空闲控制字或序列有序集控制字以外的其他内容。
(4)对于包括空闲控制字或序列有序集控制字的比特组，空闲控制字或序列有序集控制字后为数据字节或终止控制字。
在一种可能的实现方式中，错误检测结果包括目标码块的内容顺序错误或内容错误，根据错误检测结果以及目标码块的类型和数据单元对目标码块进行第一解码，得到2 n组码流块，包括：对目标码块进行转换得到第二码块，根据第二码块的类型和数据单元对第二码块进行第一解码得到2 n组码流块。也即，2 n组码流块根据第二码块的类型和数据单元对第二码块进行第一解码得到，第二码块是对目标码块进行转换得到的且与目标码块比特数相同的码块。
示例性地，对目标码块进行转换得到第二码块，包括：对于目标码块中内容顺序错误或内容错误的比特组，将该内容顺序错误或内容错误的比特组转换为错误控制字；基于该错误控制字和目标码块中内容顺序正确且内容正确的比特组，得到第二码块。例如，将第一比特组转换为第一错误控制字，该第一比特组是内容顺序错误或内容错误的比特组。又例如，将第二比特组转换为第二错误控制字，该第二比特组是内容顺序错误或内容错误的比特组。在一种可能的实现方式中，转换得到的第二码块为控制码块，可以采用解码方式二对该第二码块进行第一解码。
在另一种可能的实现方式中，错误检测结果包括目标码块的内容顺序错误或内容错误，根据错误检测结果以及目标码块的类型和数据单元对目标码块进行第一解码，得到2 n组码流块，包括：基于目标码块的类型和数据单元对目标码块进行第一解码得到2 n组第一码流块，对2 n组第一码流块进行转换得到2 n组码流块。也就是说，2 n组码流块基于对2 n组第一码流块进 行转换得到，2 n组第一码流块基于目标码块的类型和数据单元对目标码块进行第一解码得到。
示例性地，对2 n组第一码流块进行转换得到2 n组码流块，包括：对于2 n组第一码流块中基于内容顺序错误或内容错误的比特组得到的码流块，将该码流块转换为错误码流块。例如，错误码流块的控制块为0xFF，数据块为0xFEFEFEFE。通过对存在错误的目标码块进行处理，使得接收端能够区分错误数据和正确数据，保证数据的可靠性。
本申请实施例提供的解码方法，对目标码块进行第一解码得到包括控制块和数据块的2 n组码流块，而不必对目标码块进行转码得到2 n个66比特码块，再对2 n个66比特码块进行解码得到2 n组码流块。由此，解码效率得以提高，解码过程所带来的时延、功耗和芯片面积占用都得以降低。
以上介绍了本申请实施例提供的编码方法，与上述方法对应，本申请实施例还提供了编码装置。图8是本申请实施例提供的一种编码装置的结构示意图，该装置应用于第一网络设备，该第一网络设备为上述图1所示实施例中的第一网络设备。基于图8所示的如下多个模块，该图8所示的编码装置能够执行第一网络设备所执行的全部或部分操作。应理解到，该装置可以包括比所示模块更多的附加模块或者省略其中所示的一部分模块，本申请实施例对此并不进行限制。如图8所示，该装置包括：
获取模块801，用于获取2 n组码流块，任一组码流块包括控制块和数据块，n为大于1的整数；
第一编码模块802，用于对2 n组码流块进行第一编码，得到目标码块，目标码块包括基于2 n组码流块的控制块确定的类型和基于2 n组码流块的控制块和数据块确定的数据单元。
在一种可能的实现方式中，类型用于指示目标码块为数据码块；数据单元基于2 n组码流块的顺序对2 n组码流块的数据块进行第一编码得到。
在一种可能的实现方式中，类型用于指示目标码块为控制码块；数据单元包括类型指示和码块内容，码块内容基于2 n组码流块的控制块和数据块确定的顺序对2 n组码流块的数据块进行第一编码得到，类型指示基于2 n组码流块的控制块得到，类型指示用于指示各组码流块的类型。
在一种可能的实现方式中，目标码块为错误码块，错误码块中包括用于标识错误的数据。
在一种可能的实现方式中，目标码块基于错误检测结果对2 n组码流块进行处理得到，错误检测结果基于2 n组码流块的控制块和数据块得到。
在一种可能的实现方式中，错误检测结果包括2 n组码流块的内容顺序错误或内容错误，目标码块基于2 n组码流块中内容顺序正确且内容正确的码流块以及错误块进行第一编码得到，错误块基于2 n组码流块中内容顺序错误或内容错误的码流块得到。
在一种可能的实现方式中，控制块包括m比特，数据块包括8m比特，m为正整数。
在一种可能的实现方式中，n的取值为2，m的取值为8，目标码块为257比特。
在一种可能的实现方式中，2 n组码流块均来自介质无关接口MII。
在一种可能的实现方式中，该装置还包括：第二编码模块803，用于按照前向纠错FEC码型对目标码块进行第二编码，得到第一数据；发送模块804，用于发送第一数据。
本申请实施例提供的编码装置，对包括控制块和数据块的2 n组码流块进行第一编码得到目标码块，而不必对2 n组码流块中的每组码流块进行64B/66B编码得到2 n个66比特码块，再对 2 n个66比特码块进行转码得到目标码块。由此，编码效率得以提高，编码过程所带来的时延、功耗和芯片面积占用都得以降低。
以上介绍了本申请实施例提供的解码方法，与上述方法对应，本申请实施例还提供了解码装置。图9是本申请实施例提供的一种解码装置的结构示意图，该装置可应用于第二网络设备，该第二网络设备为上述图1所示实施例中的第二网络设备。基于图9所示的如下多个模块，该图9所示的解码装置能够执行第二网络设备所执行的全部或部分操作。应理解到，该装置可以包括比所示模块更多的附加模块或者省略其中所示的一部分模块，本申请实施例对此并不进行限制。如图9所示，该装置包括：
获取模块901，用于获取目标码块，目标码块包括类型和数据单元；
解码模块902，用于根据目标码块的类型和数据单元，对目标码块进行第一解码，得到2 n组码流块，任一组码流块包括基于类型和数据单元得到的控制块和数据块，n为大于1的整数。
在一种可能的实现方式中，类型用于指示目标码块为数据码块；2 n组码流块中的第i组码流块包括的数据块是基于对数据单元中与第i组码流块对应的8m长度的内容进行第一解码得到的，m为正整数，i为大于等于1且小于等于2 n的整数或者i为大于等于0且小于等于2 n-1的整数。
在一种可能的实现方式中，类型用于指示目标码块为控制码块，数据单元包括类型指示和码块内容，类型指示包括2 n个比特，2 n个比特中的1个比特用于指示2 n组码流块中与比特对应的一组码流块的类型，码块内容包括2 n个比特组；2 n组码流块中的第i组码流块包括的控制块是基于类型、类型指示中与第i组码流块对应的比特和码块内容中与第i组码流块对应的比特组得到的，i为大于等于1且小于等于2 n的整数或者i为大于等于0且小于等于2 n-1的整数；2 n组码流块中的第i组码流块包括的数据块是基于类型指示中与第i组码流块对应的比特对码块内容中与第i组码流块对应的比特组进行第一解码得到的。
在一种可能的实现方式中，2 n个比特组包括第一比特组和2 n-1个第二比特组，第一比特组包括的比特数量和第二比特组包括的比特数量不相同。
在一种可能的实现方式中，数据单元包括类型指示，类型和类型指示用于指示目标码块为错误码块；2 n组码流块中每组码流块包括的控制块为第一值，2 n组码流块中每组码流块包括的数据块为第二值，第一值和第二值用于指示码流块为错误码流块。
在一种可能的实现方式中，获取模块，用于接收第二数据，第二数据是基于采用前向纠错FEC码型编码的第一数据获得的；对第二数据进行第二解码获取目标码块，第二解码为纠错处理。
在一种可能的实现方式中，目标码块是对第二数据进行纠错但未成功纠错所获得的码块。
在一种可能的实现方式中，获取模块901，用于接收第二数据，第二数据是基于采用前向纠错FEC码型编码的第一数据获得的；对第二数据进行第二解码获取目标码块，第二解码为检错但不纠错处理。
在一种可能的实现方式中，目标码块是从第二数据检出错误但不纠错所获得的码块。
在一种可能的实现方式中，2 n组码流块根据错误检测结果以及目标码块的类型和数据单元对目标码块进行第一解码得到，错误检测结果基于目标码块的类型和数据单元得到。
在一种可能的实现方式中，错误检测结果包括目标码块的内容顺序错误或内容错误，2 n 组码流块根据第二码块的类型和数据单元对第二码块进行第一解码得到，第二码块是对目标码块进行转换得到的且与目标码块比特数相同的码块。
在一种可能的实现方式中，错误检测结果包括目标码块的内容顺序错误或内容错误，2 n组码流块基于对2 n组第一码流块进行转换得到，2 n组第一码流块基于目标码块的类型和数据单元对目标码块进行第一解码得到。
在一种可能的实现方式中，控制块包括m比特，数据块包括8m比特，m为正整数。
在一种可能的实现方式中，n的取值为2，m的取值为8，目标码块为257比特。
在一种可能的实现方式中，2 n组码流块均为介质无关接口MII格式。
本申请实施例提供的解码装置，对目标码块进行第一解码得到包括控制块和数据块的2 n组码流块，而不必对目标码块进行转码得到2 n个66比特码块，再对2 n个66比特码块进行解码得到2 n组码流块。由此，解码效率得以提高，解码过程所带来的时延、功耗和芯片面积占用都得以降低。
应理解的是，上述图8和图9提供的装置在实现其功能时，仅以上述各功能模块的划分进行举例说明，实际应用中，可以根据需要而将上述功能分配由不同的功能模块完成，即将设备的内部结构划分成不同的功能模块，以完成以上描述的全部或者部分功能。另外，上述实施例提供的装置与方法实施例属于同一构思，其具体实现过程详见方法实施例，这里不再赘述。
上述实施例中的设备的具体硬件结构如图10所示的网络设备1500，包括收发器1501、处理器1502和存储器1503。收发器1501、处理器1502和存储器1503之间通过总线1504连接。其中，收发器1501用于接收报文和发送报文，存储器1503用于存放指令或程序代码，处理器1502用于调用存储器1503中的指令或程序代码使得设备执行上述方法实施例中第一网络设备或第二网络设备的相关处理步骤。在具体实施例中，本申请实施例的网络设备1500可对应于上述各个方法实施例中的第一网络设备或第二网络设备，网络设备1500中的处理器1502读取存储器1503中的指令或程序代码，使图10所示的网络设备1500能够执行第一网络设备或第二网络设备所执行的全部或部分操作。
网络设备1500还可以对应于上述图8和图9所示的装置，例如，图8和图9中所涉及的获取模块801和获取模块901相当于收发器1501，第一编码模块802和解码模块902处理器1502。
参见图11，图11示出了本申请一个示例性实施例提供的网络设备2000的结构示意图。图11所示的网络设备2000用于执行上述图2所示的编码方法所涉及的操作和图7所示的解码方法所涉及的操作。该网络设备2000例如是交换机、路由器等。
如图11所示，网络设备2000包括至少一个处理器2001、存储器2003以及至少一个通信接口2004。
处理器2001例如是通用中央处理器(central processing unit，CPU)、数字信号处理器(digital signal processor，DSP)、网络处理器(network processer，NP)、图形处理器(graphics processing unit，GPU)、神经网络处理器(neural-network processing units，NPU)、数据处理单元(data processing unit，DPU)、微处理器或者一个或多个用于实现本申请方案的集成电路。例如，处理器2001包括专用集成电路(application-specific integrated circuit，ASIC)， 可编程逻辑器件(programmable logic device，PLD)或者其他可编程逻辑器件、晶体管逻辑器件、硬件部件或者其任意组合。PLD例如是复杂可编程逻辑器件(complex programmable logic device，CPLD)、现场可编程逻辑门阵列(field-programmable gate array，FPGA)、通用阵列逻辑(generic array logic，GAL)或其任意组合。其可以实现或执行结合本发明实施例公开内容所描述的各种逻辑方框、模块和电路。所述处理器也可以是实现计算功能的组合，例如包括一个或多个微处理器组合，DSP和微处理器的组合等等。
可选的，网络设备2000还包括总线。总线用于在网络设备2000的各组件之间传送信息。总线可以是外设部件互连标准(peripheral component interconnect，简称PCI)总线或扩展工业标准结构(extended industry standard architecture，简称EISA)总线等。总线可以分为地址总线、数据总线、控制总线等。为便于表示，图11中仅用一条粗线表示，但并不表示仅有一根总线或一种类型的总线。图11中网络设备2000的各组件之间除了采用总线连接，还可采用其他方式连接，本发明实施例不对各组件的连接方式进行限定。
存储器2003例如是只读存储器(read-only memory，ROM)或可存储静态信息和指令的其它类型的静态存储设备，又如是随机存取存储器(random access memory，RAM)或者可存储信息和指令的其它类型的动态存储设备，又如是电可擦可编程只读存储器(electrically erasable programmable read-only Memory，EEPROM)、只读光盘(compact disc read-only memory，CD-ROM)或其它光盘存储、光碟存储(包括压缩光碟、激光碟、光碟、数字通用光碟、蓝光光碟等)、磁盘存储介质或者其它磁存储设备，或者是能够用于携带或存储具有指令或数据结构形式的期望的程序代码并能够由计算机存取的任何其它介质，但不限于此。存储器2003例如是独立存在，并通过总线与处理器2001相连接。存储器2003也可以和处理器2001集成在一起。
通信接口2004使用任何收发器一类的装置，用于与其它设备或通信网络通信，通信网络可以为以太网、无线接入网(RAN)或无线局域网(wireless local area networks，WLAN)等。通信接口2004可以包括有线通信接口，还可以包括无线通信接口。具体的，通信接口2004可以为以太(ethernet)接口、快速以太(fast ethernet，FE)接口、千兆以太(gigabit ethernet，GE)接口，异步传输模式(asynchronous transfer mode，ATM)接口，无线局域网(wireless local area networks，WLAN)接口，蜂窝网络通信接口或其组合。以太网接口可以是光接口，电接口或其组合。在本申请实施例中，通信接口2004可以用于网络设备2000与其他设备进行通信。
在具体实现中，作为一种实施例，处理器2001可以包括一个或多个CPU，如图11中所示的CPU0和CPU1。这些处理器中的每一个可以是一个单核(single-CPU)处理器，也可以是一个多核(multi-CPU)处理器。这里的处理器可以指一个或多个设备、电路、和/或用于处理数据(例如计算机程序指令)的处理核。
在具体实现中，作为一种实施例，网络设备2000可以包括多个处理器，如图11中所示的处理器2001和处理器2005。这些处理器中的每一个可以是一个单核处理器(single-CPU)，也可以是一个多核处理器(multi-CPU)。这里的处理器可以指一个或多个设备、电路、和/或用于处理数据(如计算机程序指令)的处理核。
在具体实现中，作为一种实施例，网络设备2000还可以包括输出设备和输入设备。输出设备和处理器2001通信，可以以多种方式来显示信息。例如，输出设备可以是液晶显示器 (liquid crystal display，LCD)、发光二级管(light emitting diode，LED)显示设备、阴极射线管(cathode ray tube，CRT)显示设备或投影仪(projector)等。输入设备和处理器2001通信，可以以多种方式接收用户的输入。例如，输入设备可以是鼠标、键盘、触摸屏设备或传感设备等。
在一些实施例中，存储器2003用于存储执行本申请方案的程序代码2010，处理器2001可以执行存储器2003中存储的程序代码2010。也即是，网络设备2000可以通过处理器2001以及存储器2003中的程序代码2010，来实现方法实施例提供的编码方法或解码方法。程序代码2010中可以包括一个或多个软件模块。可选地，处理器2001自身也可以存储执行本申请方案的程序代码或指令。
在具体实施例中，本申请实施例的网络设备2000可对应于上述各个方法实施例中的第一网络设备或第二网络设备，网络设备2000中的处理器2001读取存储器2003中的程序代码2010或处理器2001自身存储的程序代码或指令，使图11所示的网络设备2000能够执行第一网络设备或第二网络设备所执行的全部或部分操作。
网络设备2000还可以对应于上述图8和图9所示的装置，图8和图9所示的装置中的每个功能模块采用网络设备2000的软件实现。换句话说，图8和图9所示的装置包括的功能模块为网络设备2000的处理器2001读取存储器2003中存储的程序代码2010后生成的。例如，图8和图9中所涉及的获取模块801和获取模块901相当于通信接口2004，第一编码模块802和解码模块902相当于处理器2001和/或处理器2005。
其中，图2和图7所示的方法的各步骤通过网络设备2000的处理器中的硬件的集成逻辑电路或者软件形式的指令完成。结合本申请实施例所公开的方法的步骤可以直接体现为硬件处理器执行完成，或者用处理器中的硬件及软件模块组合执行完成。软件模块可以位于随机存储器，闪存、只读存储器，可编程只读存储器或者电可擦写可编程存储器、寄存器等本领域成熟的存储介质中。该存储介质位于存储器，处理器读取存储器中的信息，结合其硬件完成上述方法的步骤，为避免重复，这里不再详细描述。
参见图12，图12示出了本申请另一个示例性实施例提供的网络设备2100的结构示意图。图12所示的网络设备2100用于执行上述图2和图7所示的方法所涉及的全部或部分操作。该网络设备2100例如是交换机、路由器等，该网络设备2100可以由一般性的总线体系结构来实现。
如图12所示，网络设备2100包括：主控板2110和接口板2130。
主控板也称为主处理单元(main processing unit，MPU)或路由处理卡(route processor card)，主控板2110用于对网络设备2100中各个组件的控制和管理，包括路由计算、设备管理、设备维护、协议处理功能。主控板2110包括：中央处理器2111和存储器2112。
接口板2130也称为线路接口单元卡(line processing unit，LPU)、线卡(line card)或业务板。接口板2130用于提供各种业务接口并实现数据包的转发。业务接口包括而不限于以太网接口、POS(packet over SONET/SDH)接口等，以太网接口例如是灵活以太网业务接口(flexible ethernet clients，FlexE Clients)。接口板2130包括：中央处理器2131网络处理器2132、转发表项存储器2134和物理接口卡(physical interface card，PIC)2133。
接口板2130上的中央处理器2131用于对接口板2130进行控制管理并与主控板2110上的中央处理器2111进行通信。
网络处理器2132用于实现报文的发送处理。网络处理器2132的形态可以是转发芯片。转发芯片可以是网络处理器(network processor，NP)。在一些实施例中，转发芯片可以通过专用集成电路(application-specific integrated circuit，ASIC)或现场可编程门阵列(field programmable gate array，FPGA)实现。具体而言，网络处理器2132用于基于转发表项存储器2134保存的转发表转发接收到的报文，如果报文的目的地址为网络设备2100的地址，则将该报文上送至CPU(如中央处理器2131)处理；如果报文的目的地址不是网络设备2100的地址，则根据该目的地址从转发表中查找到该目的地址对应的下一跳和出接口，将该报文转发到该目的地址对应的出接口。其中，上行报文的处理可以包括：报文入接口的处理，转发表查找；下行报文的处理可以包括：转发表查找等等。在一些实施例中，中央处理器也可执行转发芯片的功能，比如基于通用CPU实现软件转发，从而接口板中不需要转发芯片。
物理接口卡2133用于实现物理层的对接功能，原始的流量由此进入接口板2130，以及处理后的报文从该物理接口卡2133发出。物理接口卡2133也称为子卡，可安装在接口板2130上，负责将光电信号转换为报文并对报文进行合法性检查后转发给网络处理器2132处理。在一些实施例中，中央处理器2131也可执行网络处理器2132的功能，比如基于通用CPU实现软件转发，从而物理接口卡2133中不需要网络处理器2132。
可选地，网络设备2100包括多个接口板，例如网络设备2100还包括接口板2140，接口板2140包括：中央处理器2141、网络处理器2142、转发表项存储器2144和物理接口卡2143。接口板2140中各部件的功能和实现方式与接口板2130相同或相似，在此不再赘述。
可选地，网络设备2100还包括交换网板2120。交换网板2120也可以称为交换网板单元(switch fabric unit，SFU)。在网络设备有多个接口板的情况下，交换网板2120用于完成各接口板之间的数据交换。例如，接口板2130和接口板2140之间可以通过交换网板2120通信。
主控板2110和接口板耦合。例如。主控板2110、接口板2130和接口板2140，以及交换网板2120之间通过系统总线与系统背板相连实现互通。在一种可能的实现方式中，主控板2110和接口板2130及接口板2140之间建立进程间通信协议(inter-process communication，IPC)通道，主控板2110和接口板2130及接口板2140之间通过IPC通道进行通信。
在逻辑上，网络设备2100包括控制面和转发面，控制面包括主控板2110和中央处理器2111，转发面包括执行转发的各个组件，比如转发表项存储器2134、物理接口卡2133和网络处理器2132。控制面执行路由器、生成转发表、处理信令和协议报文、配置与维护网络设备的状态等功能，控制面将生成的转发表下发给转发面，在转发面，网络处理器2132基于控制面下发的转发表对物理接口卡2133收到的报文查表转发。控制面下发的转发表可以保存在转发表项存储器2134中。在有些实施例中，控制面和转发面可以完全分离，不在同一网络设备上。
值得说明的是，主控板可能有一块或多块，有多块的时候可以包括主用主控板和备用主控板。接口板可能有一块或多块，网络设备的数据处理能力越强，提供的接口板越多。接口板上的物理接口卡也可以有一块或多块。交换网板可能没有，也可能有一块或多块，有多块的时候可以共同实现负荷分担冗余备份。在集中式转发架构下，网络设备可以不需要交换网板，接口板承担整个系统的业务数据的处理功能。在分布式转发架构下，网络设备可以有至少一块交换网板，通过交换网板实现多块接口板之间的数据交换，提供大容量的数据交换和处理能力。所以，分布式架构的网络设备的数据接入和处理能力要大于集中式架构的网络设 备。可选地，网络设备的形态也可以是只有一块板卡，即没有交换网板，接口板和主控板的功能集成在该一块板卡上，此时接口板上的中央处理器和主控板上的中央处理器在该一块板卡上可以合并为一个中央处理器，执行两者叠加后的功能，这种形态网络设备的数据交换和处理能力较低(例如，低端交换机或路由器等网络设备)。具体采用哪种架构，取决于具体的组网部署场景，此处不做任何限定。
在具体实施例中，网络设备2100对应于上述图8和图9所示的装置。在一些实施例中，图8和图9所示的装置中的获取模块801和获取模块901相当于网络设备2100中的物理接口卡2133或物理接口卡2143。图8和图9所示的装置中的第一编码模块802和解码模块902相当于网络设备2100中的中央处理器2111、网络处理器2132和网络处理器2142中的至少一个。
基于上述图10、图11及图12所示的网络设备，本申请实施例还提供了一种通信系统，该系统包括：第一网络设备及第二网络设备。可选的，第一网络设备为图10所示的网络设备1500或图11所示的网络设备2000或图12所示的网络设备2100，第二网络设备为图10所示的网络设备1500或图11所示的网络设备2000或图12所示的网络设备2100。
第一网络设备及第二网络设备所执行的方法可参见上述图1、图2和图7所示实施例的相关描述，此处不再加以赘述。
应理解的是，上述处理器可以是中央处理器(central processing unit，CPU)，还可以是其他通用处理器、数字信号处理器(digital signal processing，DSP)、专用集成电路(application specific integrated circuit，ASIC)、现场可编程门阵列(field-programmable gate array，FPGA)或者其他可编程逻辑器件、分立门或者晶体管逻辑器件、分立硬件组件等。通用处理器可以是微处理器或者是任何常规的处理器等。值得说明的是，处理器可以是支持进阶精简指令集机器(advanced RISC machines，ARM)架构的处理器。
进一步地，在一种可选的实施例中，上述存储器可以包括只读存储器和随机存取存储器，并向处理器提供指令和数据。存储器还可以包括非易失性随机存取存储器。例如，存储器还可以存储设备类型的信息。
该存储器可以是易失性存储器或非易失性存储器，或可包括易失性和非易失性存储器两者。其中，非易失性存储器可以是只读存储器(read-only memory，ROM)、可编程只读存储器(programmable ROM，PROM)、可擦除可编程只读存储器(erasable PROM，EPROM)、电可擦除可编程只读存储器(electrically EPROM，EEPROM)或闪存。易失性存储器可以是随机存取存储器(random access memory，RAM)，其用作外部高速缓存。通过示例性但不是限制性说明，许多形式的RAM可用。例如，静态随机存取存储器(static RAM，SRAM)、动态随机存取存储器(dynamic random access memory，DRAM)、同步动态随机存取存储器(synchronous DRAM，SDRAM)、双倍数据速率同步动态随机存取存储器(double data rate SDRAM，DDR SDRAM)、增强型同步动态随机存取存储器(enhanced SDRAM，ESDRAM)、同步连接动态随机存取存储器(synchlink DRAM，SLDRAM)和直接内存总线随机存取存储器(direct rambus RAM，DR RAM)。
还提供了一种计算机可读存储介质，存储介质中存储有至少一条程序指令或代码，所述程序指令或代码由处理器加载并执行时以使计算机实现图2中的编码方法或者图7中的解码方法。
本申请提供了一种计算机程序(产品)，当计算机程序被计算机执行时，可以使得处理器或计算机执行上述方法实施例中对应的各个步骤和/或流程。
提供了一种芯片，包括处理器，用于从存储器中调用并运行所述存储器中存储的指令，使得安装有所述芯片的通信设备执行上述各方面中的方法。
提供另一种芯片，包括：输入接口、输出接口、处理器和存储器，所述输入接口、输出接口、所述处理器以及所述存储器之间通过内部连接通路相连，所述处理器用于执行所述存储器中的代码，当所述代码被执行时，处理器用于执行上述各方面中的方法。
还提供了一种设备，该设备包括上述芯片。可选地，该设备为网络设备。示例性地，该设备为路由器或交换机或服务器。
在上述实施例中，可以全部或部分地通过软件、硬件、固件或者其任意组合来实现。当使用软件实现时，可以全部或部分地以计算机程序产品的形式实现。所述计算机程序产品包括一个或多个计算机指令。在计算机上加载和执行所述计算机程序指令时，全部或部分地产生按照本申请所述的流程或功能。所述计算机可以是通用计算机、专用计算机、计算机网络、或者其他可编程装置。所述计算机指令可以存储在计算机可读存储介质中，或者从一个计算机可读存储介质向另一个计算机可读存储介质传输，例如，所述计算机指令可以从一个网站站点、计算机、服务器或数据中心通过有线(例如同轴电缆、光纤、数字用户线)或无线(例如红外、无线、微波等)方式向另一个网站站点、计算机、服务器或数据中心进行传输。所述计算机可读存储介质可以是计算机能够存取的任何可用介质或者是包含一个或多个可用介质集成的服务器、数据中心等数据存储设备。所述可用介质可以是磁性介质，(例如，软盘、硬盘、磁带)、光介质(例如，DVD)、或者半导体介质(例如固态硬盘(solid state disk，SSD))等。
以上所述的具体实施方式，对本申请的目的、技术方案和有益效果进行了进一步详细说明，所应理解的是，以上所述仅为本申请的具体实施方式而已，并不用于限定本申请的保护范围，凡在本申请的技术方案的基础之上，所做的任何修改、等同替换、改进等，均应包括在本申请的保护范围之内。
本领域普通技术人员可以意识到，结合本文中所公开的实施例中描述的各方法步骤和模块，能够以软件、硬件、固件或者其任意组合来实现，为了清楚地说明硬件和软件的可互换性，在上述说明中已经按照功能一般性地描述了各实施例的步骤及组成。这些功能究竟以硬件还是软件方式来执行，取决于技术方案的特定应用和设计约束条件。本领域普通技术人员可以对每个特定的应用来使用不同方法来实现所描述的功能，但是这种实现不应认为超出本申请的范围。
本领域普通技术人员可以理解实现上述实施例的全部或部分步骤可以通过硬件来完成，也可以通过程序来指令相关的硬件完成，该程序可以存储于一种计算机可读存储介质中，上述提到的存储介质可以是只读存储器，磁盘或光盘等。
当使用软件实现时，可以全部或部分地以计算机程序产品的形式实现。该计算机程序产品包括一个或多个计算机程序指令。作为示例，本申请实施例的方法可以在机器可执行指令的上下文中被描述，机器可执行指令诸如包括在目标的真实或者虚拟处理器上的器件中执行的程序模块中。一般而言，程序模块包括例程、程序、库、对象、类、组件、数据结构等，其执行特定的任务或者实现特定的抽象数据结构。在各实施例中，程序模块的功能可以在所 描述的程序模块之间合并或者分割。用于程序模块的机器可执行指令可以在本地或者分布式设备内执行。在分布式设备中，程序模块可以位于本地和远程存储介质二者中。
用于实现本申请实施例的方法的计算机程序代码可以用一种或多种编程语言编写。这些计算机程序代码可以提供给通用计算机、专用计算机或其他可编程的数据处理装置的处理器，使得程序代码在被计算机或其他可编程的数据处理装置执行的时候，引起在流程图和/或框图中规定的功能/操作被实施。程序代码可以完全在计算机上、部分在计算机上、作为独立的软件包、部分在计算机上且部分在远程计算机上或完全在远程计算机或服务器上执行。
在本申请实施例的上下文中，计算机程序代码或者相关数据可以由任意适当载体承载，以使得设备、装置或者处理器能够执行上文描述的各种处理和操作。载体的示例包括信号、计算机可读介质等等。
信号的示例可以包括电、光、无线电、声音或其它形式的传播信号，诸如载波、红外信号等。
机器可读介质可以是包含或存储用于或有关于指令执行系统、装置或设备的程序的任何有形介质。机器可读介质可以是机器可读信号介质或机器可读存储介质。机器可读介质可以包括但不限于电子的、磁的、光学的、电磁的、红外的或半导体系统、装置或设备，或其任意合适的组合。机器可读存储介质的更详细示例包括带有一根或多根导线的电气连接、便携式计算机磁盘、硬盘、随机存储存取器(RAM)、只读存储器(ROM)、可擦除可编程只读存储器(EPROM或闪存)、光存储设备、磁存储设备，或其任意合适的组合。
所属领域的技术人员可以清楚地了解到，为了描述的方便和简洁，上述描述的系统、设备和模块的具体工作过程，可以参见前述方法实施例中的对应过程，在此不再赘述。
在本申请所提供的几个实施例中，应该理解到，所揭露的系统、设备和方法，可以通过其它的方式实现。例如，以上所描述的设备实施例仅仅是示意性的，例如，该模块的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，例如多个模块或组件可以结合或者可以集成到另一个系统，或一些特征可以忽略，或不执行。另外，所显示或讨论的相互之间的耦合或直接耦合或通信连接可以是通过一些接口、设备或模块的间接耦合或通信连接，也可以是电的，机械的或其它的形式连接。
该作为分离部件说明的模块可以是或者也可以不是物理上分开的，作为模块显示的部件可以是或者也可以不是物理模块，即可以位于一个地方，或者也可以分布到多个网络模块上。可以根据实际的需要选择其中的部分或者全部模块来实现本申请实施例方案的目的。
另外，在本申请各个实施例中的各功能模块可以集成在一个处理模块中，也可以是各个模块单独物理存在，也可以是两个或两个以上模块集成在一个模块中。上述集成的模块既可以采用硬件的形式实现，也可以采用软件功能模块的形式实现。
该集成的模块如果以软件功能模块的形式实现并作为独立的产品销售或使用时，可以存储在一个计算机可读存储介质中。基于这样的理解，本申请的技术方案本质上或者说对现有技术做出贡献的部分，或者该技术方案的全部或部分可以以软件产品的形式体现出来，该计算机软件产品存储在一个存储介质中，包括若干指令用以使得一台计算机设备(可以是个人计算机，服务器，或者网络设备等)执行本申请各个实施例中方法的全部或部分步骤。而前述的存储介质包括：U盘、移动硬盘、只读存储器(read-only memory，ROM)、随机存取存储器(random access memory，RAM)、磁碟或者光盘等各种可以存储程序代码的介质。
本申请中术语“第一”“第二”等字样用于对作用和功能基本相同的相同项或相似项进行区分，应理解，“第一”、“第二”、“第n”之间不具有逻辑或时序上的依赖关系，也不对数量和执行顺序进行限定。还应理解，尽管以下描述使用术语第一、第二等来描述各种元素，但这些元素不应受术语的限制。这些术语只是用于将一元素与另一元素区别分开。例如，在不脱离各种所述示例的范围的情况下，第一网络设备可以被称为第二网络设备，并且类似地，第二网络设备可以被称为第一网络设备。第一网络设备和第二网络设备都可以是任一类型的网络设备，并且在某些情况下，可以是单独且不同的网络设备。
还应理解，在本申请的各个实施例中，各个过程的序号的大小并不意味着执行顺序的先后，各过程的执行顺序应以其功能和内在逻辑确定，而不应对本申请实施例的实施过程构成任何限定。
本申请中术语“至少一个”的含义是指一个或多个，本申请中术语“多个”的含义是指两个或两个以上，例如，多个第二报文是指两个或两个以上的第二报文。本文中术语“系统”和“网络”经常可互换使用。
应理解，在本文中对各种所述示例的描述中所使用的术语只是为了描述特定示例，而并非旨在进行限制。如在对各种所述示例的描述和所附权利要求书中所使用的那样，单数形式“一个(“a”，“an”)”和“该”旨在也包括复数形式，除非上下文另外明确地指示。
还应理解，术语“包括”(也称“includes”、“including”、“comprises”和/或“comprising”)当在本说明书中使用时指定存在所陈述的特征、整数、步骤、操作、元素、和/或部件，但是并不排除存在或添加一个或多个其他特征、整数、步骤、操作、元素、部件、和/或其分组。
还应理解，术语“若”和“如果”可被解释为意指“当...时”(“when”或“upon”)或“响应于确定”或“响应于检测到”。类似地，根据上下文，短语“若确定...”或“若检测到[所陈述的条件或事件]”可被解释为意指“在确定...时”或“响应于确定...”或“在检测到[所陈述的条件或事件]时”或“响应于检测到[所陈述的条件或事件]”。
应理解，根据A确定B并不意味着仅仅根据A确定B，还可以根据A和/或其它信息确定B。
还应理解，说明书通篇中提到的“一个实施例”、“一实施例”、“一种可能的实现方式”意味着与实施例或实现方式有关的特定特征、结构或特性包括在本申请的至少一个实施例中。因此，在整个说明书各处出现的“在一个实施例中”或“在一实施例中”、“一种可能的实现方式”未必一定指相同的实施例。此外，这些特定的特征、结构或特性可以任意适合的方式结合在一个或多个实施例中。

Claims (56)

  1. 一种编码方法，其特征在于，所述方法包括：
    获取2 n组码流块，任一组码流块包括控制块和数据块，所述n为大于1的整数；
    对所述2 n组码流块进行第一编码，得到目标码块，所述目标码块包括基于所述2 n组码流块的控制块确定的类型和基于所述2 n组码流块的控制块和数据块确定的数据单元。
  2. 根据权利要求1所述的方法，其特征在于，所述类型用于指示所述目标码块为数据码块；
    所述数据单元基于所述2 n组码流块的顺序对所述2 n组码流块的数据块进行所述第一编码得到。
  3. 根据权利要求1所述的方法，其特征在于，所述类型用于指示所述目标码块为控制码块；
    所述数据单元包括类型指示和码块内容，所述码块内容基于所述2 n组码流块的控制块和数据块确定的顺序对所述2 n组码流块的数据块进行所述第一编码得到，所述类型指示基于所述2 n组码流块的控制块得到，所述类型指示用于指示各组码流块的类型。
  4. 根据权利要求3所述的方法，其特征在于，所述目标码块为错误码块，所述错误码块中包括用于标识错误的数据。
  5. 根据权利要求1-4任一所述的方法，其特征在于，所述目标码块基于错误检测结果对所述2 n组码流块进行处理得到，所述错误检测结果基于所述2 n组码流块的控制块和数据块得到。
  6. 根据权利要求5所述的方法，其特征在于，所述错误检测结果包括所述2 n组码流块的内容顺序错误或内容错误，所述目标码块基于所述2 n组码流块中内容顺序正确且内容正确的码流块以及错误块进行所述第一编码得到，所述错误块基于所述2 n组码流块中内容顺序错误或内容错误的码流块得到。
  7. 根据权利要求1-6任一所述的方法，其特征在于，所述控制块包括m比特，所述数据块包括8m比特，所述m为正整数。
  8. 根据权利要求7所述的方法，其特征在于，所述n的取值为2，所述m的取值为8，所述目标码块为257比特。
  9. 根据权利要求1-8任一所述的方法，其特征在于，所述2 n组码流块均来自介质无关接口MII。
  10. 根据权利要求1-9任一所述的方法，其特征在于，所述得到目标码块之后，还包括：
    按照前向纠错FEC码型对所述目标码块进行第二编码，得到第一数据；
    发送所述第一数据。
  11. 一种解码方法，其特征在于，所述方法包括：
    获取目标码块，所述目标码块包括类型和数据单元；
    根据所述目标码块的类型和数据单元，对所述目标码块进行第一解码，得到2 n组码流块，任一组码流块包括基于所述类型和所述数据单元得到的控制块和数据块，所述n为大于1的整数。
  12. 根据权利要求11所述的方法，其特征在于，所述类型用于指示所述目标码块为数据码块；
    所述2 n组码流块中的第i组码流块包括的数据块是基于对所述数据单元中与所述第i组码流块对应的8m长度的内容进行所述第一解码得到的，所述m为正整数，所述i为大于等于1且小于等于2 n的整数或者所述i为大于等于0且小于等于2 n-1的整数。
  13. 根据权利要求11所述的方法，其特征在于，所述类型用于指示所述目标码块为控制码块，所述数据单元包括类型指示和码块内容，所述类型指示包括2 n个比特，所述2 n个比特中的1个比特用于指示所述2 n组码流块中与所述比特对应的一组码流块的类型，所述码块内容包括2 n个比特组；
    所述2 n组码流块中的第i组码流块包括的控制块是基于所述类型、所述类型指示中与所述第i组码流块对应的比特和所述码块内容中与所述第i组码流块对应的比特组得到的，所述i为大于等于1且小于等于2 n的整数或者所述i为大于等于0且小于等于2 n-1的整数；
    所述2 n组码流块中的第i组码流块包括的数据块是基于所述类型指示中与所述第i组码流块对应的比特对所述码块内容中与所述第i组码流块对应的比特组进行所述第一解码得到的。
  14. 根据权利要求13所述的方法，其特征在于，所述2 n个比特组包括第一比特组和2 n-1个第二比特组，所述第一比特组包括的比特数量和所述第二比特组包括的比特数量不相同。
  15. 根据权利要求11所述的方法，其特征在于，所述数据单元包括类型指示，所述类型和所述类型指示用于指示所述目标码块为错误码块；
    所述2 n组码流块中每组码流块包括的控制块为第一值，所述2 n组码流块中每组码流块包括的数据块为第二值，所述第一值和所述第二值用于指示所述码流块为错误码流块。
  16. 根据权利要求11-15任一所述的方法，其特征在于，所述获取目标码块，包括：
    接收第二数据，所述第二数据是基于采用前向纠错FEC码型编码的第一数据获得的；
    对所述第二数据进行第二解码获取所述目标码块，所述第二解码为纠错处理。
  17. 根据权利要求16所述的方法，其特征在于，所述目标码块是对所述第二数据进行纠错但未成功纠错所获得的错误码块。
  18. 根据权利要求11-15任一所述的方法，其特征在于，所述获取目标码块，包括：
    接收第二数据，所述第二数据是基于采用前向纠错FEC码型编码的第一数据获得的；
    对所述第二数据进行第二解码获取所述目标码块，所述第二解码为检错但不纠错处理。
  19. 根据权利要求18所述的方法，其特征在于，所述目标码块是从所述第二数据检出错误但不纠错所获得的错误码块。
  20. 根据权利要求11-15任一所述的方法，其特征在于，所述2 n组码流块根据错误检测结果以及所述目标码块的类型和数据单元对所述目标码块进行所述第一解码得到，所述错误检测结果基于所述目标码块的类型和数据单元得到。
  21. 根据权利要求20所述的方法，其特征在于，所述错误检测结果包括所述目标码块的内容顺序错误或内容错误，所述2 n组码流块根据第二码块的类型和数据单元对所述第二码块进行所述第一解码得到，所述第二码块是对所述目标码块进行转换得到的且与所述目标码块比特数相同的码块。
  22. 根据权利要求20所述的方法，其特征在于，所述错误检测结果包括所述目标码块的内容顺序错误或内容错误，所述2 n组码流块基于对2 n组第一码流块进行转换得到，所述2 n组第一码流块基于所述目标码块的类型和数据单元对所述目标码块进行所述第一解码得到。
  23. 根据权利要求11-22任一所述的方法，其特征在于，所述控制块包括m比特，所述数据块包括8m比特，所述m为正整数。
  24. 根据权利要求23所述的方法，其特征在于，所述n的取值为2，所述m的取值为8，所述目标码块为257比特。
  25. 根据权利要求11-24任一所述的方法，其特征在于，所述2 n组码流块均为介质无关接口MII格式。
  26. 一种编码装置，其特征在于，所述装置包括：
    获取模块，用于获取2 n组码流块，任一组码流块包括控制块和数据块，所述n为大于1的整数；
    第一编码模块，用于对所述2 n组码流块进行第一编码，得到目标码块，所述目标码块包括基于所述2 n组码流块的控制块确定的类型和基于所述2 n组码流块的控制块和数据块确定的数据单元。
  27. 根据权利要求26所述的装置，其特征在于，所述类型用于指示所述目标码块为数据码块；所述数据单元基于所述2 n组码流块的顺序对所述2 n组码流块的数据块进行所述第一编码得到。
  28. 根据权利要求26所述的装置，其特征在于，所述类型用于指示所述目标码块为控制码块；所述数据单元包括类型指示和码块内容，所述码块内容基于所述2 n组码流块的控制块和数据块确定的顺序对所述2 n组码流块的数据块进行所述第一编码得到，所述类型指示基于所述2 n组码流块的控制块得到，所述类型指示用于指示各组码流块的类型。
  29. 根据权利要求28所述的装置，其特征在于，所述目标码块为错误码块，所述错误码块中包括用于标识错误的数据。
  30. 根据权利要求26-29任一所述的装置，其特征在于，所述目标码块基于错误检测结果对所述2 n组码流块进行处理得到，所述错误检测结果基于所述2 n组码流块的控制块和数据块得到。
  31. 根据权利要求30所述的装置，其特征在于，所述错误检测结果包括所述2 n组码流块的内容顺序错误或内容错误，所述目标码块基于所述2 n组码流块中内容顺序正确且内容正确的码流块以及错误块进行所述第一编码得到，所述错误块基于所述2 n组码流块中内容顺序错误或内容错误的码流块得到。
  32. 根据权利要求26-31任一所述的装置，其特征在于，所述控制块包括m比特，所述数据块包括8m比特，所述m为正整数。
  33. 根据权利要求31所述的装置，其特征在于，所述n的取值为2，所述m的取值为8，所述目标码块为257比特。
  34. 根据权利要求26-33任一所述的装置，其特征在于，所述2 n组码流块均来自介质无关接口MII。
  35. 根据权利要求26-34任一所述的装置，其特征在于，所述装置还包括：
    第二编码模块，用于按照前向纠错FEC码型对所述目标码块进行第二编码，得到第一数据；
    发送模块，用于发送所述第一数据。
  36. 一种解码装置，其特征在于，所述装置包括：
    获取模块，用于获取目标码块，所述目标码块包括类型和数据单元；
    解码模块，用于根据所述目标码块的类型和数据单元，对所述目标码块进行第一解码，得到2 n组码流块，任一组码流块包括基于所述类型和所述数据单元得到的控制块和数据块，所述n为大于1的整数。
  37. 根据权利要求36所述的装置，其特征在于，所述类型用于指示所述目标码块为数据码 块；所述2 n组码流块中的第i组码流块包括的数据块是基于对所述数据单元中与所述第i组码流块对应的8m长度的内容进行所述第一解码得到的，所述m为正整数，所述i为大于等于1且小于等于2 n的整数或者所述i为大于等于0且小于等于2 n-1的整数。
  38. 根据权利要求36所述的装置，其特征在于，所述类型用于指示所述目标码块为控制码块，所述数据单元包括类型指示和码块内容，所述类型指示包括2 n个比特，所述2 n个比特中的1个比特用于指示所述2 n组码流块中与所述比特对应的一组码流块的类型，所述码块内容包括2 n个比特组；所述2 n组码流块中的第i组码流块包括的控制块是基于所述类型、所述类型指示中与所述第i组码流块对应的比特和所述码块内容中与所述第i组码流块对应的比特组得到的，所述i为大于等于1且小于等于2 n的整数或者所述i为大于等于0且小于等于2 n-1的整数；所述2 n组码流块中的第i组码流块包括的数据块是基于所述类型指示中与所述第i组码流块对应的比特对所述码块内容中与所述第i组码流块对应的比特组进行所述第一解码得到的。
  39. 根据权利要求38所述的装置，其特征在于，所述2 n个比特组包括第一比特组和2 n-1个第二比特组，所述第一比特组包括的比特数量和所述第二比特组包括的比特数量不相同。
  40. 根据权利要求36所述的装置，其特征在于，所述数据单元包括类型指示，所述类型和所述类型指示用于指示所述目标码块为错误码块；所述2 n组码流块中每组码流块包括的控制块为第一值，所述2 n组码流块中每组码流块包括的数据块为第二值，所述第一值和所述第二值用于指示所述码流块为错误码流块。
  41. 根据权利要求36-40任一所述的装置，其特征在于，所述获取模块，用于接收第二数据，所述第二数据是基于采用前向纠错FEC码型编码的第一数据获得的；对所述第二数据进行第二解码获取所述目标码块，所述第二解码为纠错处理。
  42. 根据权利要求41所述的装置，其特征在于，所述目标码块是对所述第二数据进行纠错但未成功纠错所获得的错误码块。
  43. 根据权利要求36-40任一所述的装置，其特征在于，所述获取模块，用于接收第二数据，所述第二数据是基于采用前向纠错FEC码型编码的第一数据获得的；对所述第二数据进行第二解码获取所述目标码块，所述第二解码为检错但不纠错处理。
  44. 根据权利要求43所述的装置，其特征在于，所述目标码块是从所述第二数据检出错误但不纠错所获得的错误码块。
  45. 根据权利要求36-40任一所述的装置，其特征在于，所述2 n组码流块根据错误检测结果以及所述目标码块的类型和数据单元对所述目标码块进行所述第一解码得到，所述错误检测结果基于所述目标码块的类型和数据单元得到。
  46. 根据权利要求45所述的装置，其特征在于，所述错误检测结果包括所述目标码块的内容顺序错误或内容错误，所述2 n组码流块根据第二码块的类型和数据单元对所述第二码块进行所述第一解码得到，所述第二码块是对所述目标码块进行转换得到的且与所述目标码块比特数相同的码块。
  47. 根据权利要求45所述的装置，其特征在于，所述错误检测结果包括所述目标码块的内容顺序错误或内容错误，所述2 n组码流块基于对2 n组第一码流块进行转换得到，所述2 n组第一码流块基于所述目标码块的类型和数据单元对所述目标码块进行所述第一解码得到。
  48. 根据权利要求36-47任一所述的装置，其特征在于，所述控制块包括m比特，所述数据块包括8m比特，所述m为正整数。
  49. 根据权利要求48所述的装置，其特征在于，所述n的取值为2，所述m的取值为8，所述目标码块为257比特。
  50. 根据权利要求36-49任一所述的装置，其特征在于，所述2 n组码流块均为介质无关接口MII格式。
  51. 一种网络设备，其特征在于，所述网络设备包括：处理器，所述处理器与存储器耦合，所述存储器中存储有至少一条程序指令或代码，所述至少一条程序指令或代码由所述处理器加载并执行，以使所述网络设备实现如权利要求1-25中任一所述的方法。
  52. 一种通信系统，其特征在于，所述系统包括第一网络设备和第二网络设备，所述第一网络设备用于执行如权利要求1-10中任一所述的方法，所述第二网络设备用于执行如权利要求11-25中任一所述的方法。
  53. 一种计算机可读存储介质，其特征在于，所述计算机可读存储介质中存储有至少一条程序指令或代码，所述程序指令或代码由处理器加载并执行时以使计算机实现如权利要求1-25中任一所述的方法。
  54. 一种计算机程序产品，其特征在于，所述计算机程序产品包括计算机程序代码，当所述计算机程序代码被计算机运行时，使得所述计算机实现如权利要求1-25中任一所述的方法。
  55. 一种芯片，其特征在于，所述芯片包括处理器，所述处理器用于从存储器中调用并运行所述存储器中存储的指令，使得安装有所述芯片的通信设备执行如权利要求1-25中任一所述的方法。
  56. 一种芯片，其特征在于，所述芯片包括：输入接口、输出接口、处理器和存储器，所述输入接口、所述输出接口、所述处理器以及所述存储器之间通过内部连接通路相连，所述 处理器用于执行所述存储器中的代码，当所述代码被执行时，所述处理器用于执行如权利要求1-25中任一所述的方法。
PCT/CN2022/142363 2022-01-05 2022-12-27 编码方法、解码方法、装置、设备、系统及可读存储介质 WO2023131004A1 (zh)

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