WO2023130954A1 - 处理方法、通信设备及存储介质 - Google Patents

处理方法、通信设备及存储介质 Download PDF

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Publication number
WO2023130954A1
WO2023130954A1 PCT/CN2022/140485 CN2022140485W WO2023130954A1 WO 2023130954 A1 WO2023130954 A1 WO 2023130954A1 CN 2022140485 W CN2022140485 W CN 2022140485W WO 2023130954 A1 WO2023130954 A1 WO 2023130954A1
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WIPO (PCT)
Prior art keywords
bit rate
priority
logical channel
data
priority bit
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PCT/CN2022/140485
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English (en)
French (fr)
Inventor
朱荣昌
黄伟
黄钧蔚
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深圳传音控股股份有限公司
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Publication of WO2023130954A1 publication Critical patent/WO2023130954A1/zh

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04W—WIRELESS COMMUNICATION NETWORKS
    • H04W24/00—Supervisory, monitoring or testing arrangements
    • H04W24/02—Arrangements for optimising operational condition
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04W—WIRELESS COMMUNICATION NETWORKS
    • H04W72/00—Local resource management
    • H04W72/50—Allocation or scheduling criteria for wireless resources
    • H04W72/56—Allocation or scheduling criteria for wireless resources based on priority criteria
    • H04W72/566—Allocation or scheduling criteria for wireless resources based on priority criteria of the information or information source or recipient
    • H04W72/569—Allocation or scheduling criteria for wireless resources based on priority criteria of the information or information source or recipient of the traffic information
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04W—WIRELESS COMMUNICATION NETWORKS
    • H04W92/00—Interfaces specially adapted for wireless communication networks
    • H04W92/04—Interfaces between hierarchically different network devices
    • H04W92/10—Interfaces between hierarchically different network devices between terminal device and access point, i.e. wireless air interface

Definitions

  • the present application relates to the technical field of communications, and in particular to a processing method, communications equipment, and a storage medium.
  • the terminal device may determine, based on the uplink transmission resources configured by the network device, the transmission data volume of each logical channel in the initial media access control packet data unit (Medium Access Control Packet Data Unit, MAC PDU for short).
  • the initial media access control packet data unit Medium Access Control Packet Data Unit, MAC PDU for short.
  • the network radio resource control (Radio Resource Control, referred to as RRC) will configure the following parameters for each uplink logical channel: logic Channel priority (priority): the smaller the priority value, the higher the priority of the corresponding logical channel; PBR: priority bit rate, indicating the minimum rate that the logical channel needs to guarantee; the token bucket duration (Bucket Size Duration , referred to as BSD): This parameter determines the depth of the token bucket.
  • RRC Radio Resource Control
  • the present application provides a processing method, a communication device and a storage medium to solve the above technical problems.
  • the present application provides a processing method, which can be applied to communication devices such as terminal devices or network devices, including the following steps:
  • the S1 step includes:
  • the delay budget result is calculated or determined according to the actual rate of data transmission of the logical channel within the first duration and/or the amount of buffered data, and the delay budget value.
  • the delay budget result includes at least one of the following:
  • the buffering delay of data in the logical channel does not meet the delay budget, and the actual rate and/or the amount of buffered data satisfies at least one of the following: the actual rate is less than or equal to the current priority bit rate, and the buffering The amount of data is greater than or equal to the product of the current priority bit rate and the first duration; the amount of buffered data is greater than or equal to the product of the actual rate and the delay budget value; the amount of buffered data is greater than or equal to a product of the actual rate, the delay budget value, and a first threshold;
  • the buffer delay of data in the logical channel meets the delay budget, and the actual rate and/or the amount of buffered data satisfies at least one of the following: the actual rate is greater than the current priority bit rate; the buffer The amount of data is less than the product of the current priority bit rate and the first duration; the amount of cached data is less than the product of the actual rate and the delay budget value; the amount of cached data is less than the actual rate, the The product of the delay budget value and the first threshold.
  • the S2 step includes:
  • the target priority bit rate is at least one of the following:
  • the buffering delay of the data in the logical channel does not meet the delay budget, and the target priority bit rate is greater than or equal to the current priority bit rate; and/or,
  • the buffer delay of the data in the logical channel meets the delay budget, and the target priority bit rate is less than or equal to the current priority bit rate; and/or,
  • the buffer delay of the data in the logical channel meets the delay budget, and the target priority is lower than or equal to the current priority; and/or,
  • the buffering delay of the data in the logical channel does not meet the delay budget, and the target priority is higher than or equal to the current priority.
  • the buffering delay of the data in the logical channel does not meet the delay budget, including at least one of the following:
  • the target priority bit rate is at least one of the following: the current priority bit rate, the quotient of the cached data amount and the delay budget value, the product of the current priority bit rate and the second threshold, the first The second threshold is a positive number greater than or equal to 1;
  • the target priority bit rate is the quotient of the buffered data amount and the delay budget value
  • the target priority bit rate is the current priority bit rate.
  • the target priority bit rate is the product of the current priority bit rate and the second threshold
  • the target priority bit rate is the current priority bit rate
  • the target priority is the current priority
  • the target priority is incremented for the current priority.
  • the priority bit rate threshold is the quotient of the cached data amount and the delay budget; or, the priority bit rate threshold is a third threshold.
  • the buffering delay of the data in the logical channel meets the delay budget, including at least one of the following:
  • the target priority bit rate is at least one of the following: the current priority bit rate, the initial priority bit rate, the product of the current priority bit rate and the second threshold, and the second threshold is less than or equal to 1 A positive number.
  • the target priority bit rate is the current priority bit rate
  • the target priority bit rate is the product of the current priority bit rate and a third threshold
  • the target priority is the current priority
  • the target priority is the current priority decrementing
  • the present application provides a processing method, which can be applied to communication equipment such as terminal equipment or network equipment, including the following steps:
  • the delay budget result meeting preset conditions includes at least one of the following:
  • the buffer delay of data in the logical channel does not meet the delay budget, and the actual rate of data transmission and/or buffered data volume of the logical channel within the first duration meets at least one of the following: the actual rate is less than or equal to The current priority bit rate, and the buffered data amount is greater than or equal to the product of the current priority bit rate and the first duration, and the buffered data amount is greater than or equal to the product of the actual rate and the delay budget value , the amount of cached data is greater than or equal to the product of the actual rate, the delay budget value, and a first threshold;
  • the buffering delay of data in the logical channel meets the delay budget, and the actual rate and/or the amount of buffered data satisfies at least one of the following: the actual rate is greater than the current priority bit rate, the buffering The amount of data is less than the product of the current priority bit rate and the first duration, the amount of cached data is less than the product of the actual rate and the delay budget value, the amount of cached data is less than the actual rate, and the amount of buffered data is less than the product of the actual rate.
  • the adjusting the priority bit rate and/or priority of the logical channel includes:
  • the target priority bit rate is at least one of the following:
  • the buffering delay of the data in the logical channel does not meet the delay budget, and the target priority bit rate is greater than or equal to the current priority bit rate; and/or,
  • the buffer delay of the data in the logical channel meets the delay budget, and the target priority bit rate is less than or equal to the current priority bit rate; and/or,
  • the buffer delay of the data in the logical channel meets the delay budget, and the target priority is lower than or equal to the current priority; and/or,
  • the buffering delay of the data in the logical channel does not meet the delay budget, and the target priority is higher than or equal to the current priority.
  • the buffering delay of the data in the logical channel does not meet the delay budget, including at least one of the following:
  • the target priority bit rate is at least one of the following: the current priority bit rate, the quotient of the cached data amount and the delay budget value, the product of the current priority bit rate and the second threshold, the first The second threshold is a positive number greater than or equal to 1;
  • the target priority bit rate is the quotient of the buffered data amount and the delay budget value
  • the target priority bit rate is the current priority bit rate.
  • the target priority bit rate is the product of the current priority bit rate and the second threshold
  • the target priority bit rate is the current priority bit rate
  • the target priority is the current priority
  • the target priority is incremented for the current priority.
  • the priority bit rate threshold is the quotient of the cached data amount and the delay budget; or, the priority bit rate threshold is a third threshold.
  • the buffering delay of the data in the logical channel meets the delay budget, including at least one of the following:
  • the target priority bit rate is at least one of the following: the current priority bit rate, the initial priority bit rate, the product of the current priority bit rate and the second threshold, and the second threshold is less than or equal to 1 A positive number.
  • the target priority bit rate is the current priority bit rate
  • the target priority bit rate is the product of the current priority bit rate and a third threshold
  • the target priority is the current priority
  • the target priority is the current priority decremented.
  • the present application provides a processing device, comprising:
  • a processing module configured to calculate or determine the delay budget result of the logical channel according to the delay budget value
  • An adjustment module configured to adjust the priority bit rate and/or priority of the logical channel according to the delay budget result.
  • the present application provides a processing device, including:
  • a processing module configured to adjust the priority bit rate and/or priority of the logical channel in response to the delay budget result of the logical channel meeting a preset condition.
  • the present application provides a communication device, including: a memory and a processor;
  • the memory is used to store program instructions
  • the processor is configured to call program instructions in the memory to execute the processing method according to any one of the first aspect or the second aspect.
  • the present application provides a computer-readable storage medium, on which a computer program is stored; when the computer program is executed, the processing described in any one of the first aspect or the second aspect is realized method.
  • the processing method, communication device and storage medium provided by the present application first determine the delay budget result of the logical channel according to the delay budget value, and the delay budget result is used to indicate whether the buffer delay of data in the logical channel meets the delay budget. Then, adjust the PBR and/or priority of the logical channel according to the delay budget result. After adjusting the PBR and/or priority of the logical channel, the air interface resource and/or processing level obtained by the logical channel can be changed, thereby changing the data in the logical channel. transmission rate, thereby changing the buffer delay of data in the logical channel. In the solution of the present application, the buffer delay of data in the logical channel is controlled by dynamically adjusting the PBR and/or priority of the logical channel.
  • FIG. 1 is a schematic diagram of a hardware structure of a terminal device provided in an embodiment of the present application
  • FIG. 2 is a system architecture diagram of a communication network provided by an embodiment of the present application.
  • Fig. 3 is a schematic flow diagram 1 of the processing method provided by the embodiment of the present application.
  • FIG. 4 is a schematic flow diagram of adjusting PBR of a logical channel provided by an embodiment of the present application.
  • FIG. 5 is a schematic flow diagram II of the processing method provided by the embodiment of the present application.
  • FIG. 6 is a first schematic diagram of PBR adjustment provided by the embodiment of the present application.
  • Fig. 7 is the second schematic diagram of PBR adjustment provided by the embodiment of the present application.
  • Fig. 8 is the third schematic diagram of PBR adjustment provided by the embodiment of the present application.
  • FIG. 9 is a first structural schematic diagram of a processing device provided in an embodiment of the present application.
  • FIG. 10 is a second structural schematic diagram of the processing device provided in the embodiment of the present application.
  • FIG. 11 is a schematic structural diagram of a communication device provided by an embodiment of the present application.
  • FIG. 12 is a schematic diagram of a hardware structure of a controller provided by an embodiment of the present application.
  • FIG. 13 is a schematic diagram of a hardware structure of a network node provided by an embodiment of the present application.
  • first, second, third, etc. may be used herein to describe various information, the information should not be limited to these terms. These terms are only used to distinguish information of the same type from one another. For example, without departing from the scope of this document, first information may also be called second information, and similarly, second information may also be called first information.
  • first information may also be called second information, and similarly, second information may also be called first information.
  • second information may also be called first information.
  • the word “if” as used herein may be interpreted as “at” or “when” or “in response to a determination”.
  • the singular forms "a”, “an” and “the” are intended to include the plural forms as well, unless the context indicates otherwise.
  • A, B, C means “any of the following: A; B; C; A and B; A and C; B and C; A and B and C
  • A, B or C or "A, B and/or C” means "any of the following: A; B; C; A and B; A and C; B and C; A and B and C”. Exceptions to this definition will only arise when combinations of elements, functions, steps or operations are inherently mutually exclusive in some way.
  • the words “if”, “if” as used herein may be interpreted as “at” or “when” or “in response to determining” or “in response to detecting”.
  • the phrases “if determined” or “if detected (the stated condition or event)” could be interpreted as “when determined” or “in response to the determination” or “when detected (the stated condition or event) )” or “in response to detection of (a stated condition or event)”.
  • step codes such as S1 and S2 are used, the purpose of which is to express the corresponding content more clearly and concisely, and does not constitute a substantive limitation on the order.
  • S2 will be executed first and then S1, etc., but these should be within the protection scope of this application.
  • Smart terminals can be implemented in various forms.
  • the smart terminals described in this application may include mobile phones, tablet computers, notebook computers, palmtop computers, personal digital assistants (Personal Digital Assistant, PDA), portable media players (Portable Media Player, PMP), navigation devices, Smart terminals such as wearable devices, smart bracelets, and pedometers, as well as fixed terminals such as digital TVs and desktop computers.
  • PDA Personal Digital Assistant
  • PMP portable media players
  • navigation devices Smart terminals such as wearable devices, smart bracelets, and pedometers
  • Smart terminals such as wearable devices, smart bracelets, and pedometers
  • fixed terminals such as digital TVs and desktop computers.
  • a mobile terminal will be taken as an example, and those skilled in the art will understand that, in addition to elements specially used for mobile purposes, the configurations according to the embodiments of the present application can also be applied to fixed-type terminals.
  • FIG. 1 is a schematic diagram of the hardware structure of a terminal device implementing various embodiments of the present application.
  • the terminal device 100 may include: an RF (Radio Frequency, radio frequency) unit 101, a WiFi module 102, an audio output unit 103, an A /V (audio/video) input unit 104, sensor 105, display unit 106, user input unit 107, interface unit 108, memory 109, processor 110, and power supply 111 and other components.
  • RF Radio Frequency, radio frequency
  • the radio frequency unit 101 can be used for sending and receiving information or receiving and sending signals during a call.
  • the radio frequency unit 101 can be processed by the processor 110; in addition, the uplink data can be sent to the base station.
  • the radio frequency unit 101 includes, but is not limited to, an antenna, at least one amplifier, a transceiver, a coupler, a low noise amplifier, a duplexer, and the like.
  • the radio frequency unit 101 can also communicate with the network and other devices through wireless communication.
  • the above wireless communication can use any communication standard or protocol, including but not limited to GSM (Global System of Mobile communication, Global System for Mobile Communications), GPRS (General Packet Radio Service, General Packet Radio Service), CDMA2000 (Code Division Multiple Access 2000 , Code Division Multiple Access 2000), WCDMA (Wideband Code Division Multiple Access, Wideband Code Division Multiple Access), TD-SCDMA (Time Division-Synchronous Code Division Multiple Access, Time Division Synchronous Code Division Multiple Access), FDD-LTE (Frequency Division Duplexing-Long Term Evolution, frequency division duplex long-term evolution), TDD-LTE (Time Division Duplexing-Long Term Evolution, time-division duplex long-term evolution) and 5G, etc.
  • GSM Global System of Mobile communication, Global System for Mobile Communications
  • GPRS General Packet Radio Service
  • CDMA2000 Code Division Multiple Access 2000
  • WCDMA Wideband Code Division Multiple Access
  • TD-SCDMA Time Division-Synchronous Code Division Multiple Access, Time Division Synchro
  • WiFi is a short-distance wireless transmission technology.
  • the terminal device can help users send and receive emails, browse web pages, and access streaming media, etc. It provides users with wireless broadband Internet access.
  • FIG. 1 shows the WiFi module 102, it can be understood that it is not a necessary component of the terminal device, and can be completely omitted as required without changing the essence of the invention.
  • the audio output unit 103 can store the audio received by the radio frequency unit 101 or the WiFi module 102 or stored in the memory 109 when the terminal device 100 is in a call signal receiving mode, a call mode, a recording mode, a voice recognition mode, a broadcast receiving mode, or the like.
  • the audio data is converted into an audio signal and output as sound.
  • the audio output unit 103 may also provide audio output related to a specific function performed by the terminal device 100 (eg, call signal reception sound, message reception sound, etc.).
  • the audio output unit 103 may include a speaker, a buzzer, and the like.
  • the A/V input unit 104 is used to receive audio or video signals.
  • the A/V input unit 104 may include a graphics processing unit (Graphics Processing Unit, GPU) 1041 and a microphone 1042, and the graphics processing unit 1041 is used for still pictures or The image data of the video is processed.
  • the processed image frames may be displayed on the display unit 106 .
  • the image frames processed by the graphics processor 1041 may be stored in the memory 109 (or other storage media) or sent via the radio frequency unit 101 or the WiFi module 102 .
  • the microphone 1042 can receive sound (audio data) via the microphone 1042 in a phone call mode, a recording mode, a voice recognition mode, and the like operating modes, and can process such sound as audio data.
  • the processed audio (voice) data can be converted into a format transmittable to a mobile communication base station via the radio frequency unit 101 for output in case of a phone call mode.
  • the microphone 1042 may implement various types of noise cancellation (or suppression) algorithms to cancel (or suppress) noise or interference generated in the process of receiving and transmitting audio signals.
  • the terminal device 100 also includes at least one sensor 105, such as a light sensor, a motion sensor, and other sensors.
  • the light sensor includes an ambient light sensor and a proximity sensor.
  • the ambient light sensor can adjust the brightness of the display panel 1061 according to the brightness of the ambient light, and the proximity sensor can turn off the display when the terminal device 100 moves to the ear. panel 1061 and/or backlight.
  • the accelerometer sensor can detect the magnitude of acceleration in various directions (generally three axes), and can detect the magnitude and direction of gravity when it is stationary, and can be used for applications that recognize the posture of mobile phones (such as horizontal and vertical screen switching, related Games, magnetometer attitude calibration), vibration recognition related functions (such as pedometer, tap), etc.; as for mobile phones, fingerprint sensors, pressure sensors, iris sensors, molecular sensors, gyroscopes, barometers, hygrometers, Other sensors such as thermometers and infrared sensors will not be described in detail here.
  • the display unit 106 is used to display information input by the user or information provided to the user.
  • the display unit 106 may include a display panel 1061, and the display panel 1061 may be configured in the form of a liquid crystal display (Liquid Crystal Display, LCD), an organic light-emitting diode (Organic Light-Emitting Diode, OLED), or the like.
  • LCD Liquid Crystal Display
  • OLED Organic Light-Emitting Diode
  • the user input unit 107 can be used to receive input numbers or character information, and generate key signal input related to user settings and function control of the terminal device.
  • the user input unit 107 may include a touch panel 1071 and other input devices 1072 .
  • the touch panel 1071 also referred to as a touch screen, can collect touch operations of the user on or near it (for example, the user uses any suitable object or accessory such as a finger or a stylus on the touch panel 1071 or near the touch panel 1071). operation), and drive the corresponding connection device according to the preset program.
  • the touch panel 1071 may include two parts, a touch detection device and a touch controller.
  • the touch detection device detects the user's touch orientation, detects the signal brought by the touch operation, and transmits the signal to the touch controller; the touch controller receives touch information from the touch detection device and converts it into contact coordinates , and then sent to the processor 110, and can receive the command sent by the processor 110 and execute it.
  • the touch panel 1071 can be implemented in various types such as resistive, capacitive, infrared, and surface acoustic wave.
  • the user input unit 107 may also include other input devices 1072 .
  • other input devices 1072 may include, but are not limited to, one or more of physical keyboards, function keys (such as volume control buttons, switch buttons, etc.), trackballs, mice, joysticks, etc., which are not specifically described here. limited.
  • the touch panel 1071 may cover the display panel 1061.
  • the touch panel 1071 detects a touch operation on or near it, it transmits to the processor 110 to determine the type of the touch event, and then the processor 110 determines the touch event according to the touch event.
  • the corresponding visual output is provided on the display panel 1061 .
  • the touch panel 1071 and the display panel 1061 are used as two independent components to realize the input and output functions of the terminal device, in some embodiments, the touch panel 1071 and the display panel 1061 can be integrated
  • the implementation of the input and output functions of the terminal device is not specifically limited here.
  • the interface unit 108 serves as an interface through which at least one external device can be connected with the terminal device 100 .
  • an external device may include a wired or wireless headset port, an external power (or battery charger) port, a wired or wireless data port, a memory card port, a port for connecting a device with an identification module, audio input/output (I/O) ports, video I/O ports, headphone ports, and more.
  • the interface unit 108 can be used to receive input from an external device (for example, data information, power, etc.) transfer data between devices.
  • the memory 109 can be used to store software programs as well as various data.
  • the memory 109 can mainly include a storage program area and a storage data area.
  • the storage program area can store an operating system, at least one function required application program (such as a sound playback function, an image playback function, etc.) etc.
  • the storage data area can be Store data (such as audio data, phone book, etc.) created according to the use of the mobile phone.
  • the memory 109 may include a high-speed random access memory, and may also include a non-volatile memory, such as at least one magnetic disk storage device, flash memory device, or other volatile solid-state storage devices.
  • the processor 110 is the control center of the terminal equipment, uses various interfaces and lines to connect various parts of the entire terminal equipment, runs or executes software programs and/or modules stored in the memory 109, and calls data stored in the memory 109 , execute various functions of the terminal equipment and process data, so as to monitor the terminal equipment as a whole.
  • the processor 110 may include one or more processing units; preferably, the processor 110 may integrate an application processor and a modem processor.
  • the application processor mainly processes operating systems, user interfaces, and application programs, etc.
  • the demodulation processor mainly handles wireless communication. It can be understood that the foregoing modem processor may not be integrated into the processor 110 .
  • the terminal device 100 can also include a power supply 111 (such as a battery) for supplying power to various components.
  • a power supply 111 (such as a battery) for supplying power to various components.
  • the power supply 111 can be logically connected to the processor 110 through a power management system, so as to manage charging, discharging, and power consumption through the power management system. and other functions.
  • the terminal device 100 may also include a Bluetooth module, etc., which will not be repeated here.
  • the following describes the communication network system on which the mobile terminal of the present application is based.
  • the following describes the communication network system on which the terminal device of the present application is based.
  • FIG. 2 is a structure diagram of a communication network system provided by an embodiment of the present application.
  • the communication network system is an LTE system of general mobile communication technology.
  • 201 E-UTRAN (Evolved UMTS Terrestrial Radio Access Network, Evolved UMTS Terrestrial Radio Access Network) 202, EPC (Evolved Packet Core, Evolved Packet Core Network) 203 and the operator's IP service 204.
  • E-UTRAN Evolved UMTS Terrestrial Radio Access Network
  • EPC Evolved Packet Core, Evolved Packet Core Network
  • the UE 201 may be the above-mentioned terminal device 100, which will not be repeated here.
  • E-UTRAN 202 includes eNodeB 2021 and other eNodeB 2022 and so on.
  • the eNodeB2021 can be connected to other eNodeB2022 through a backhaul (for example, X2 interface), the eNodeB2021 is connected to the EPC203, and the eNodeB2021 can provide access from the UE 201 to the EPC 203.
  • a backhaul for example, X2 interface
  • EPC203 may include MME (Mobility Management Entity, Mobility Management Entity) 2031, HSS (Home Subscriber Server, Home Subscriber Server) 2032, other MME2033, SGW (Serving Gate Way, Serving Gateway) 2034, PGW (PDN Gate Way, packet data Network Gateway) 2035 and PCRF (Policy and Charging Rules Function, Policy and Charging Functional Entity) 2036, etc.
  • MME2031 is a control node that processes signaling between UE201 and EPC203, and provides bearer and connection management.
  • HSS2032 is used to provide some registers to manage functions such as home location register (not shown in the figure), and save some user-specific information about service features and data rates.
  • PCRF2036 is the policy and charging control policy decision point of business data flow and IP bearer resources, it is the policy and charging execution functional unit (not shown) Select and provide available policy and charging control decisions.
  • the IP service 204 may include Internet, Intranet, IMS (IP Multimedia Subsystem, IP Multimedia Subsystem) or other IP services.
  • IMS IP Multimedia Subsystem, IP Multimedia Subsystem
  • LTE system is used as an example above, those skilled in the art should know that this application is not only applicable to the LTE system, but also applicable to other wireless communication systems, such as GSM, CDMA2000, WCDMA, TD-SCDMA and future new wireless communication systems.
  • the network system (such as 5G), etc., is not limited here.
  • FIG 3 is a schematic flow diagram of the processing method provided by the embodiment of the present application.
  • This embodiment uses the subject of the processing method as a terminal device (such as UE) as an example for illustration. In actual implementation, it may also be performed by a network device. , as shown in Figure 3, the method includes:
  • the network allocates uplink transmission resources based on each UE rather than per-bearer. Which radio bearer data can be put into the allocated uplink transmission resources is determined by the UE. Based on the uplink transmission resources configured by the network, the UE needs to determine the transmission data volume of each logical channel in the initial media access control packet data unit (Medium Access Control Packet Data Unit, MAC PDU). In some cases, the UE also needs to To allocate resources for MAC Control Element (MAC CE). In order to realize multiplexing of uplink logical channels (Logical Channel, LCH), it is necessary to assign a priority to each uplink logical channel.
  • LCH Logical Channel
  • the resources of the MAC PDU are allocated in order of the logical channel priorities corresponding to each uplink logical channel from large to small .
  • PBR Prioritized Bit Rate
  • network radio resource control configures the following parameters for each uplink logical channel:
  • Logical channel priority the smaller the priority value, the higher the priority of the corresponding logical channel
  • PBR priority bit rate, indicating the minimum rate that the logical channel needs to guarantee
  • Token Bucket Duration BSD This parameter determines the depth of the token bucket.
  • the UE's MAC uses the token bucket mechanism to multiplex uplink logical channels.
  • the UE maintains a variable Bj for each uplink logical channel j, which indicates the number of currently available tokens in the token bucket.
  • Bj logical channel priority
  • UE initializes Bj to 0; UE increases Bj by PBR*T before each logical channel priority (Logical Channel Priority, LCP for short) process, where T is the last increment The time interval from the moment of Bj to the current moment; if the updated Bj according to the above steps is greater than the maximum capacity of the token bucket (that is, PBR*BSD), then Bj is set to the maximum capacity of the token bucket.
  • the UE When the UE receives the uplink grant resource (UL grant) indicating the new transmission, the UE performs logical channel priority processing according to the following steps:
  • the data transmission rate in the logical channel depends on the rate of the air interface, so the data transmission rate in the logical channel is also limited accordingly.
  • the buffering delay of data in the logical channel refers to the length of time from the buffering of the data to the logical channel to the completion of the transmission from the logical channel.
  • the data transmission rate in the logical channel is limited, it will also cause the buffering of the data in the logical channel. Latency increases.
  • a delay budget value (delay budget value) can be set for the logical channel to realize the dynamic adjustment of the buffer delay, so as to achieve the purpose of delay control.
  • the buffering delay of data in the logical channel may be controlled based on the delay budget value.
  • the buffering delay of data in the logical channel is not guaranteed.
  • the delay budget value is configured by the network device for the terminal device.
  • the terminal device can calculate or determine the delay budget result of the logical channel according to the delay budget value, and the delay budget result is used to indicate whether the buffer delay of data in the logical channel meets the delay budget.
  • the buffering delay of data in the logical channel may or may not meet the delay budget.
  • the buffering delay of data in the logical channel meets the delay budget, it means that the buffering delay of the data in the logical channel is small.
  • the PBR of the logical channel may not be adjusted, or the PBR of the logical channel may be adjusted to a smaller value. More air interface resources are allocated to other logical channels that have higher requirements on delay budget.
  • the buffering delay of data in the logical channel does not meet the delay budget, it means that the buffering delay of the data in the logical channel is relatively large.
  • the PBR of the logical channel can be increased, so that the logical channel can be allocated more resources to reduce the buffering delay of data in the logical channel.
  • the logical channel can work in at least one priority, and the priority of the logical channel can be adjusted according to the delay budget result.
  • the buffer delay of data in the logical channel can be affected by setting the priority, and then the response speed of the logical channel can be adjusted. For example, when sending data, logical channels with higher channel priorities are assigned resources first and sent first, and logical channels with lower channel priorities are assigned resources later and sent later.
  • Fig. 4 is a schematic flow diagram of adjusting the PBR of the logical channel provided by the embodiment of the present application, as shown in Fig. 4 , including:
  • the first duration is a duration configured by the network device, and the first duration is a duration of the timer.
  • the PBR is periodically adjusted according to the first duration.
  • the actual rate of data transmission and/or buffered data volume of the logical channel within the first duration is obtained, and then the delay budget result is calculated or determined according to the actual rate and/or buffered data volume, and the delay budget value.
  • the actual rate is the transmission rate of the data in the logical channel within the first duration. Since the data transmission rate in the logical channel changes dynamically, there are many ways to obtain the actual rate.
  • One possible implementation is to determine the actual rate by means of a sliding window average or a filtered average. For example, the data transmission rates on the logical channel at N moments within the first duration may be obtained, and then the N data transmission rates are averaged to obtain the actual rate. For example, the data transmission rate of the logical channel within M time periods within the first duration may be obtained, and then the M data transmission rates are averaged to obtain the actual rate.
  • the amount of cached data is the size of the data newly cached to the logical channel within the first time period. Taking the first time period as the period between t1-t2 as an example, the data newly cached to the logical channel within the period t1-t2 is For buffering data, the size of data newly buffered to the logical channel is the amount of buffered data.
  • the delay budget result of the logical channel can be determined in the following manner.
  • Method 1.1 Determine whether the actual rate is less than or equal to the current PBR, and the amount of cached data is greater than or equal to the product of the current PBR and the first duration.
  • the delay budget result is that the buffer delay of the data in the logical channel does not meet the delay budget.
  • the delay budget result is that the buffer delay of data in the logical channel meets the delay budget.
  • Method 1.2 Determine whether the amount of buffered data is greater than or equal to the product of the actual rate and the delay budget value, and if so, determine that the delay budget result is that the buffer delay of the data in the logical channel does not meet the delay budget; and/or, if not , then the result of determining the delay budget is that the buffer delay of data in the logical channel meets the delay budget.
  • Method 1.3 Determine whether the amount of buffered data is greater than or equal to the product of the actual rate, the delay budget value and the first threshold, and if so, determine that the delay budget result is that the buffer delay of the data in the logical channel does not meet the delay budget; and/ Or, if not, the result of determining the delay budget is that the buffer delay of the data in the logical channel meets the delay budget.
  • the first threshold is a value greater than or equal to 0, such as 80%, 90%, and so on.
  • the first threshold may be configured by the network device for the terminal device, or may be configured by the terminal device.
  • the PBR can be adjusted as the target PBR according to the delay budget result.
  • the target PBR is greater than or equal to the current PBR, that is, when the delay budget is not met, the PBR of the logical channel is increased so that The logical channel obtains more air interface resources, increases the transmission rate of data on the logical channel, and then reduces the buffering delay of data on the logical channel.
  • the PBR of the logical channel can be adjusted in the following manner:
  • the second threshold a may be a value configured by the network device, or may be a value configured by the terminal device.
  • the PBR threshold value is the quotient of the cached data amount and the delay budget value.
  • the PBR threshold may be a third threshold.
  • the third threshold may be a value configured by the network device, or may be a value configured by the terminal device.
  • the target PBR is the product of the current PBR, the buffered data amount and the delay budget value, the current priority bit rate and the second threshold a At least one item of , the second threshold a is a positive number greater than or equal to 1.
  • the target PBR is smaller than the current PBR, that is, when the delay budget is met, the PBR of the logical channel is reduced so that the logical channel obtains
  • the air interface resources are reduced, so that more limited air interface resources can be allocated to logical channels that do not meet the delay budget.
  • the PBR of the logical channel can be adjusted in the following manner:
  • Method 2.3 restore the PBR of the logical channel to the initial PBR.
  • the second threshold b may be a value configured by the network device, or may be a value configured by the terminal device.
  • the target PBR is at least one of the product of the current PBR, the initial PBR, the current priority bit rate and the second threshold b, and the second threshold b is a positive number less than 1.
  • the priority of the logical channel may be adjusted to the target priority according to the delay budget result.
  • the result of the delay budget is that the buffer delay of the data in the logical channel does not meet the delay budget, and the target priority is higher than or equal to the current priority, that is, when the delay budget is not met, the priority of the logical channel is increased , so that the processing level of the logical channel is higher, the response speed of the data in the logical channel is improved, and the buffer delay of the data in the logical channel is reduced.
  • the priority of the logical channel can be adjusted through the following implementation methods:
  • Embodiment 3.1 If the current priority is the highest priority, the target priority is the current priority.
  • Real-time mode 3.2 If the current priority is not the highest priority, the target priority is incremented by the current priority.
  • the priority of the logical channel can be divided into multiples. If the current priority is the highest priority, the priority of the logical channel cannot be increased, and the target priority can be the current priority. If the current priority is not the highest priority, the priority of the logical channel can be increased by one or more levels, and the target priority is the current priority incremented. By increasing the priority, the timely adjustment of the logical channel that does not meet the delay budget is realized to ensure the normal data transmission.
  • the result of the delay budget is that the buffer delay of the data in the logical channel meets the delay budget, and the target priority is lower than the current priority, that is, when the delay budget is met, the priority of the logical channel is lowered to reduce the logical
  • the processing level of the channel makes concessions for the processing of higher logical channels, thereby improving the overall data cache efficiency of the logical channels.
  • the priority of the logical channel can be adjusted through the following implementation methods:
  • Embodiment 4.1 if the current priority is the initial configuration priority, the target priority is the current priority.
  • Embodiment 4.2 if the current priority is not the initial configuration priority, the target priority is decremented from the current priority.
  • the initial configuration priority may be the minimum priority corresponding to the logical channel.
  • the initial configuration priority can also be any priority of the logical channel.
  • the minimum priority of the processing priority of the logical channel can be the initial configuration priority of the logical channel, so , the adjusted target priority cannot be lower than the initial configuration priority.
  • the priority of the logical channel can be divided into multiple. If the current priority is the priority of the initial configuration, the priority cannot be reduced to avoid affecting data transmission. Therefore, the target priority can be the current priority class. If the current priority is not the initial configuration priority, you can downgrade the current priority to obtain the target priority. Realize the timely adjustment of the logical channel that meets the delay budget to ensure the normal transmission of data.
  • Fig. 5 is the second schematic flow diagram of the processing method provided by the embodiment of the present application.
  • the main body executing the processing method is a terminal device (such as UE) as an example for illustration.
  • a network device such as a GPRS Support Node (GSM)
  • the method includes:
  • the network allocates uplink transmission resources based on each UE rather than per-bearer. Which radio bearer data can be put into the allocated uplink transmission resources is determined by the UE. Based on the uplink transmission resources configured by the network, the UE needs to determine the transmission data volume of each logical channel in the initial media access control packet data unit (Medium Access Control Packet Data Unit, MAC PDU). In some cases, the UE also needs to To allocate resources for MAC Control Element (MAC CE). In order to realize multiplexing of uplink logical channels (Logical Channel 1, LCH), it is necessary to assign a priority to each uplink logical channel.
  • LCH Logical Channel 1
  • the resources of the MAC PDU are allocated in order of the logical channel priorities corresponding to each uplink logical channel from large to small .
  • PBR Prioritized Bit Rate
  • network radio resource control configures the following parameters for each uplink logical channel:
  • Logical channel priority the smaller the priority value, the higher the priority of the corresponding logical channel
  • PBR priority bit rate, indicating the minimum rate that the logical channel needs to guarantee
  • Token Bucket Duration BSD This parameter determines the depth of the token bucket.
  • the UE's MAC uses the token bucket mechanism to multiplex uplink logical channels.
  • the UE maintains a variable Bj for each uplink logical channel j, which indicates the number of currently available tokens in the token bucket.
  • Bj Logical Channel Priority
  • the UE when the UE establishes a logical channel j, it initializes Bj to 0; before each logical channel priority (Logical Channel Priority, LCP) processing process, the UE increases Bj by PBR*T, where T is the last increase in Bj The time interval from the moment to the current moment; if the updated Bj according to the above steps is greater than the maximum capacity of the token bucket (that is, PBR*BSD), then set Bj to the maximum capacity of the token bucket.
  • LCP Logical Channel Priority
  • the UE When the UE receives the uplink grant resource (UL grant) indicating the new transmission, the UE performs logical channel priority processing according to the following steps:
  • the data transmission rate in the logical channel depends on the rate of the air interface, so the data transmission rate in the logical channel is also limited accordingly.
  • the buffering delay of data in the logical channel refers to the length of time from the buffering of the data to the logical channel to the completion of the transmission from the logical channel.
  • the data transmission rate in the logical channel is limited, it will also cause the buffering of the data in the logical channel. Latency increases.
  • a delay budget value (delay budget value) can be set for the logical channel to realize the dynamic adjustment of the buffer delay, so as to achieve the purpose of delay control.
  • the buffering delay of data in the logical channel may be controlled based on the delay budget value.
  • the buffering delay of data in the logical channel is not guaranteed.
  • the delay budget value is configured by the network device for the terminal device.
  • the terminal device adjusts the PBR of the logical channel.
  • the delay budget result meeting the preset condition includes at least one of the following:
  • the buffering delay of data in the logical channel does not meet the delay budget, and the actual rate and/or the amount of buffered data meet at least one of the following: the actual rate is less than or equal to the current PBR, and the amount of buffered data is greater than or equal to the difference between the current PBR and the first duration product; the amount of cached data is greater than or equal to the product of the actual rate and the delay budget; the amount of cached data is greater than or equal to the product of the actual rate, the delay budget and the first threshold;
  • the cache delay of the data in the logical channel meets the delay budget, and the actual rate and/or the cached data volume satisfies at least one of the following: the actual rate is greater than the current PBR; the cached data volume is less than the product of the current PBR and the first duration; the cached data The amount is less than the product of the actual rate and the delay budget value; the cached data volume is less than the product of the actual rate, the delay budget value and the first threshold.
  • the buffering delay of data in the logical channel may or may not meet the delay budget.
  • the buffering delay of data in the logical channel meets the delay budget, it means that the buffering delay of the data in the logical channel is small.
  • the PBR of the logical channel may not be adjusted, or the PBR of the logical channel may be adjusted to a smaller value. More air interface resources are allocated to other logical channels that have higher requirements on delay budget.
  • the buffering delay of data in the logical channel does not meet the delay budget, it means that the buffering delay of the data in the logical channel is relatively large.
  • the PBR of the logical channel can be increased, so that the logical channel can be allocated more resources to reduce the buffering delay of data in the logical channel.
  • the first duration is a duration configured by the network device, and the first duration is a duration of the timer.
  • the PBR is periodically adjusted according to the first duration.
  • the delay budget result of the logical channel is acquired.
  • the actual rate of data transmission and/or buffered data volume of the logical channel within the first duration is obtained, and then the delay budget result is calculated or determined according to the actual rate and/or buffered data volume, and the delay budget value.
  • the actual rate is the transmission rate of the data in the logical channel within the first duration. Since the data transmission rate in the logical channel changes dynamically, there are many ways to obtain the actual rate.
  • One possible implementation is to determine the actual rate by means of a sliding window average or a filtered average. For example, the data transmission rates on the logical channel at N moments within the first duration may be obtained, and then the N data transmission rates are averaged to obtain the actual rate. For example, the data transmission rate of the logical channel within M time periods within the first duration may be obtained, and then the M data transmission rates are averaged to obtain the actual rate.
  • the amount of cached data is the size of the data newly cached to the logical channel within the first time period. Taking the first time period as the period between t1-t2 as an example, the data newly cached to the logical channel within the period t1-t2 is For buffering data, the size of data newly buffered to the logical channel is the amount of buffered data.
  • the delay budget result of the logical channel can be determined in the following manner.
  • Method 1.1 Determine whether the actual rate is less than or equal to the current PBR, and the amount of cached data is greater than or equal to the product of the current PBR and the first duration.
  • the delay budget result is that the buffer delay of the data in the logical channel does not meet the delay budget.
  • the delay budget result is that the buffer delay of data in the logical channel meets the delay budget.
  • Method 1.2 Determine whether the amount of buffered data is greater than or equal to the product of the actual rate and the delay budget value, and if so, determine that the delay budget result is that the buffer delay of the data in the logical channel does not meet the delay budget; and/or, if not , then the result of determining the delay budget is that the buffer delay of data in the logical channel meets the delay budget.
  • Method 1.3 Determine whether the amount of buffered data is greater than or equal to the product of the actual rate, the delay budget value and the first threshold, and if so, determine that the delay budget result is that the buffer delay of the data in the logical channel does not meet the delay budget; and/ Or, if not, the result of determining the delay budget is that the buffer delay of the data in the logical channel meets the delay budget.
  • the first threshold is a value greater than or equal to 0, such as 80%, 90%, and so on.
  • the first threshold may be configured by the network device for the terminal device, or may be configured by the terminal device.
  • the PBR can be adjusted as the target PBR according to the delay budget result.
  • the priority of the logical channel may be adjusted to the target priority according to the delay budget result.
  • the result of the delay budget is that the buffer delay of the data in the logical channel does not meet the delay budget, and the target priority is higher than or equal to the current priority, that is, when the delay budget is not met, the priority of the logical channel is increased , so that the processing level of the logical channel is higher, the response speed of the data in the logical channel is improved, and the buffer delay of the data in the logical channel is reduced.
  • the priority of the logical channel can be adjusted through the following implementation methods:
  • Embodiment 3.1 If the current priority is the highest priority, the target priority is the current priority.
  • Real-time mode 3.2 If the current priority is not the highest priority, the target priority is incremented by the current priority.
  • the priority of the logical channel can be divided into multiples. If the current priority is the highest priority, the priority of the logical channel cannot be increased, and the target priority can be the current priority. If the current priority is not the highest priority, the priority of the logical channel can be increased by one or more levels, and the target priority is the current priority incremented. By increasing the priority, the timely adjustment of the logical channel that does not meet the delay budget is realized to ensure the normal data transmission.
  • the result of the delay budget is that the buffer delay of the data in the logical channel meets the delay budget, and the target priority is lower than the current priority, that is, when the delay budget is met, the priority of the logical channel is lowered to reduce the logical
  • the processing level of the channel makes concessions for the processing of higher logical channels, thereby improving the overall data cache efficiency of the logical channels.
  • the priority of the logical channel can be adjusted through the following implementation methods:
  • Embodiment 4.1 if the current priority is the initial configuration priority, the target priority is the current priority.
  • Embodiment 4.2 if the current priority is not the initial configuration priority, the target priority is decremented from the current priority.
  • the initial configuration priority may be the minimum priority corresponding to the logical channel.
  • the initial configuration priority can also be any priority of the logical channel.
  • the minimum priority of the processing priority of the logical channel can be the initial configuration priority of the logical channel, so , the adjusted target priority cannot be lower than the initial configuration priority.
  • the priority of the logical channel can be divided into multiple. If the current priority is the priority of the initial configuration, the priority cannot be reduced to avoid affecting data transmission. Therefore, the target priority can be the current priority class. If the current priority is not the initial configuration priority, you can downgrade the current priority to obtain the target priority. Realize the timely adjustment of the logical channel that meets the delay budget to ensure the normal transmission of data.
  • the target PBR is greater than or equal to the current PBR, that is, when the delay budget is not met, the PBR of the logical channel is increased so that The logical channel obtains more air interface resources, increases the transmission rate of data on the logical channel, and then reduces the buffering delay of data on the logical channel.
  • the PBR of the logical channel can be adjusted in the following manner:
  • the second threshold a may be a value configured by the network device, or may be a value configured by the terminal device.
  • the PBR threshold value is the quotient of the cached data amount and the delay budget value.
  • the PBR threshold may be a third threshold.
  • the third threshold may be a value configured by the network device, or may be a value configured by the terminal device.
  • the target PBR is the product of the current PBR, the buffered data amount and the delay budget value, the current priority bit rate and the second threshold a At least one item of , the second threshold a is a positive number greater than or equal to 1.
  • the target PBR is smaller than the current PBR, that is, when the delay budget is met, the PBR of the logical channel is reduced so that the logical channel obtains
  • the air interface resources are reduced, so that more limited air interface resources can be allocated to logical channels that do not meet the delay budget.
  • the PBR of the logical channel can be adjusted in the following manner:
  • Method 2.3 restore the PBR of the logical channel to the initial PBR.
  • the second threshold b may be a value configured by the network device, or may be a value configured by the terminal device.
  • the target PBR is at least one of the product of the current PBR, the initial PBR, the current priority bit rate and the second threshold b, and the second threshold b is a positive number less than 1.
  • the delay budget result may be obtained.
  • the PBR of the logical channel can be adjusted according to at least one of method 2.1 and method 2.2 in the above embodiment; when the delay budget result is the data
  • the PBR of the logical channel may be adjusted according to at least one of method 2.3 and method 2.4 in the foregoing embodiments.
  • Figure 6 is a first schematic diagram of PBR adjustment provided by the embodiment of the present application.
  • the execution subject is a terminal device (such as UE) as an example for illustration.
  • a network device as shown in FIG. 6 ,include:
  • the buffering delay of the logical channel is controlled.
  • periodic detection may be performed by setting a timer, and the duration of the timer may be configured by a network device.
  • the timer reaches the first duration, execute S63, and/or, when the timer does not reach the first duration, continue to detect the running duration of the timer.
  • S63 is an implementation manner of determining the delay budget result of the logical channel, that is, judging whether the buffer delay of the data in the logical channel meets the delay budget according to method 1.1 in the above-mentioned embodiment.
  • perform S64 and/or, when the buffering delay of the data in the logical channel meets the delay budget, perform S66.
  • the PBR of the logical channel is adjusted according to method 2.1 in the foregoing embodiment.
  • the target PBR is adjusted to the quotient of the buffered data amount and the delay budget value.
  • target PBR current PBR.
  • the target PBR is adjusted to the initial PBR.
  • the target PBR of the logical channel is equal to the current PBR.
  • the LCP process can be executed according to the target PBR to realize the dynamic adjustment of the buffer delay of data in the logical channel.
  • Figure 7 is a schematic diagram of the second PBR adjustment provided by the embodiment of the present application.
  • the execution subject is a terminal device (such as a UE) as an example for illustration.
  • a network device as shown in FIG. 7 ,include:
  • the buffering delay of the logical channel is controlled.
  • periodic detection may be performed by setting a timer, and the duration of the timer may be configured by a network device.
  • the timer reaches the first duration, execute S73, and when the timer does not reach the first duration, continue to detect the running duration of the timer.
  • S73 is an implementation manner of determining the delay budget result of the logical channel, that is, judging whether the buffer delay of the data in the logical channel satisfies the delay budget according to method 1.2 in the above embodiment.
  • perform S74 and/or, when the buffering delay of the data in the logical channel meets the delay budget, perform S76.
  • the PBR of the logical channel is adjusted according to method 2.2 in the foregoing embodiment.
  • target PBR current PBR*a
  • a is the second threshold
  • a is a positive number greater than or equal to 1.
  • the PBR of the logical channel is adjusted according to method 2.3 in the foregoing embodiment.
  • target PBR current PBR, that is, the PBR of the logical channel is not adjusted.
  • the LCP process can be executed according to the target PBR to realize the dynamic adjustment of the buffer delay of data in the logical channel.
  • Figure 8 is a third schematic diagram of PBR adjustment provided by the embodiment of the present application.
  • the execution subject is a terminal device (such as a UE) as an example for illustration.
  • a network device as shown in FIG. 8 ,include:
  • the buffering delay of the logical channel is controlled.
  • periodic detection may be performed by setting a timer, and the duration of the timer may be configured by a network device.
  • the timer reaches the first duration, execute S83, and/or, when the timer does not reach the first duration, continue to detect the running duration of the timer.
  • S83 is an implementation manner of determining the delay budget result of the logical channel, that is, judging whether the buffer delay of the data in the logical channel meets the delay budget according to method 1.2 in the above embodiment.
  • perform S84 and/or, when the buffering delay of the data in the logical channel meets the delay budget, perform S86.
  • the PBR of the logical channel is adjusted according to method 2.2 in the foregoing embodiment.
  • target PBR current PBR*a
  • a is the second threshold
  • a is a positive number greater than or equal to 1.
  • the PBR of the logical channel is adjusted according to method 2.3 in the foregoing embodiment.
  • target PBR current PBR, that is, the PBR of the logical channel is not adjusted.
  • the LCP process can be executed according to the target PBR to realize the dynamic adjustment of the buffer delay of data in the logical channel.
  • Fig. 6 to Fig. 8 have introduced several control schemes of the buffer delay of the logical channel, it can be understood that, according to at least one of method 1.1, method 1.2 and method 1.3 in the above-mentioned embodiment, determine the time delay of the logical channel Delay budget results; when the buffer delay of data in the logical channel does not meet the delay budget, the PBR of the logical channel can be adjusted according to method 2.1 or method 2.2 in the above embodiment; when the buffer delay of data in the logical channel is satisfied When delaying the budget, the PBR of the logical channel can be adjusted according to method 2.3 or method 2.4 in the foregoing embodiments. That is, method 1.1, method 1.2, and method 1.3, and method 2.1, method 2.2, method 2.3, and method 2.4 in the foregoing embodiments may be combined arbitrarily to implement buffering delay control of logical channels.
  • the delay budget result of the logical channel is determined according to the delay budget value, and the delay budget result is used to indicate whether the buffer delay of data in the logical channel meets the delay budget. Then, adjust the PBR of the logical channel according to the delay budget result. After adjusting the PBR of the logical channel, the air interface resources obtained by the logical channel can be changed, thereby changing the transmission rate of data on the logical channel, and then changing the buffering delay of data on the logical channel.
  • the buffer delay of data in the logical channel is controlled by dynamically adjusting the PBR of the logical channel.
  • Fig. 9 is a schematic structural diagram of a processing device provided in an embodiment of the present application. As shown in Fig. 9, the processing device 90 includes:
  • a processing module 91 configured to calculate or determine the delay budget result of the logical channel according to the delay budget value
  • An adjustment module 92 configured to adjust the priority bit rate and/or priority of the logical channel according to the delay budget result.
  • processing module 91 is specifically configured to:
  • the delay budget result is calculated or determined according to the actual rate of data transmission of the logical channel within the first duration and/or the amount of buffered data, and the delay budget value.
  • the delay budget result includes at least one of the following:
  • the buffering delay of data in the logical channel does not meet the delay budget, and the actual rate and/or the amount of buffered data satisfies at least one of the following: the actual rate is less than or equal to the current priority bit rate, and the buffering The amount of data is greater than or equal to the product of the current priority bit rate and the first duration; the amount of buffered data is greater than or equal to the product of the actual rate and the delay budget value; the amount of buffered data is greater than or equal to a product of the actual rate, the delay budget value, and a first threshold;
  • the buffer delay of data in the logical channel meets the delay budget, and the actual rate and/or the amount of buffered data satisfies at least one of the following: the actual rate is greater than the current priority bit rate; the buffer The amount of data is less than the product of the current priority bit rate and the first duration; the amount of cached data is less than the product of the actual rate and the delay budget value; the amount of cached data is less than the actual rate, the The product of the delay budget value and the first threshold.
  • the adjustment module 92 is specifically used for:
  • the target priority bit rate is at least one of the following:
  • the buffer delay of the data in the logical channel does not meet the delay budget, and the target priority bit rate is greater than or equal to the current priority bit rate; and/or, the data in the logical channel
  • the buffering delay of the data meets the delay budget, and the target priority bit rate is less than or equal to the current priority bit rate; and/or, the buffering delay of the data in the logical channel meets the delay budget, and the The target priority is lower than or equal to the current priority; and/or, the buffering delay of the data in the logical channel does not meet the delay budget, and the target priority is higher than or equal to the current priority.
  • the buffering delay of the data in the logical channel does not meet the delay budget, including at least one of the following:
  • the target priority bit rate is at least one of the following: the current priority bit rate, the quotient of the cached data amount and the delay budget value, the product of the current priority bit rate and the second threshold, the first The second threshold is a positive number greater than or equal to 1;
  • the target priority bit rate is the quotient of the buffered data amount and the delay budget value
  • the target priority bit rate is the current priority bit rate.
  • the target priority bit rate is the product of the current priority bit rate and the second threshold
  • the target priority bit rate is the current priority bit rate
  • the target priority is the current priority
  • the target priority is incremented for the current priority.
  • the priority bit rate threshold is the quotient of the cached data amount and the delay budget; or, the priority bit rate threshold is a third threshold.
  • the buffering delay of the data in the logical channel meets the delay budget, including at least one of the following:
  • the target priority bit rate is at least one of the following: the current priority bit rate, the initial priority bit rate, the product of the current priority bit rate and the second threshold, and the second threshold is less than or equal to 1 A positive number.
  • the target priority bit rate is the current priority bit rate; when the current priority bit rate is greater than or equal to the initial priority bit rate, The target priority bit rate is the product of the current priority bit rate and the third threshold; when the current priority has been the initial configuration priority, the target priority is the current priority; when the current priority When the priority is not the initial configuration, the target priority is decremented from the current priority.
  • the processing device provided in the embodiment of the present application can execute the technical solution shown in the above method embodiment, and its implementation principle and beneficial effect are similar, and will not be repeated here.
  • FIG. 10 is a schematic structural diagram II of the processing device provided in the embodiment of the present application. As shown in FIG. 10, the processing device 100 includes:
  • the processing module 101 is configured to adjust the priority bit rate and/or priority of the logical channel in response to the delay budget result of the logical channel meeting a preset condition.
  • the delay budget result meeting preset conditions includes at least one of the following:
  • the buffer delay of data in the logical channel does not meet the delay budget, and the actual rate of data transmission and/or buffered data volume of the logical channel within the first duration meets at least one of the following: the actual rate is less than or equal to The current priority bit rate, and the buffered data amount is greater than or equal to the product of the current priority bit rate and the first duration, and the buffered data amount is greater than or equal to the product of the actual rate and the delay budget value , the amount of cached data is greater than or equal to the product of the actual rate, the delay budget value, and a first threshold;
  • the buffering delay of data in the logical channel meets the delay budget, and the actual rate and/or the amount of buffered data satisfies at least one of the following: the actual rate is greater than the current priority bit rate, the buffering The amount of data is less than the product of the current priority bit rate and the first duration, the amount of cached data is less than the product of the actual rate and the delay budget value, the amount of cached data is less than the actual rate, and the amount of buffered data is less than the product of the actual rate.
  • processing module 101 is specifically configured to:
  • the target priority bit rate is at least one of the following: a current priority bit rate; an initial priority bit rate; a quotient of the cached data amount and the delay budget value; a ratio between the current priority bit rate and a second threshold product, the second threshold is a positive number.
  • the buffer delay of the data in the logical channel does not meet the delay budget, and the target priority bit rate is greater than or equal to the current priority bit rate; and/or, the data in the logical channel
  • the buffering delay of the data meets the delay budget, and the target priority bit rate is less than or equal to the current priority bit rate; and/or, the buffering delay of the data in the logical channel meets the delay budget, and the The target priority is lower than or equal to the current priority; and/or, the buffering delay of the data in the logical channel does not meet the delay budget, and the target priority is higher than or equal to the current priority.
  • the buffering delay of the data in the logical channel does not meet the delay budget, including at least one of the following:
  • the target priority bit rate is at least one of the following: the current priority bit rate, the quotient of the cached data amount and the delay budget value, the product of the current priority bit rate and the second threshold, the first The second threshold is a positive number greater than or equal to 1; when the current priority bit rate is less than the quotient of the buffered data amount and the delay budget value, the target priority bit rate is the buffered data amount and the A quotient of a delay budget value; when the current priority bit rate is greater than or equal to the quotient of the cached data amount and the delay budget value, the target priority bit rate is the current priority bit rate.
  • the target priority bit rate is the product of the current priority bit rate and the second threshold; when the current priority bit rate is greater than or equal to the When the priority bit rate threshold value, the target priority bit rate is the current priority bit rate; when the current priority is the highest priority, the target priority is the current priority; when the When the current priority is not the highest priority, the target priority is incremented for the current priority.
  • the priority bit rate threshold is the quotient of the cached data amount and the delay budget; or, the priority bit rate threshold is a third threshold.
  • the buffering delay of the data in the logical channel meets the delay budget, including at least one of the following:
  • the target priority bit rate is at least one of the following: the current priority bit rate, the initial priority bit rate, the product of the current priority bit rate and the second threshold, and the second threshold is less than or equal to 1 A positive number.
  • the target priority bit rate is the current priority bit rate; when the current priority bit rate is greater than or equal to the initial priority bit rate, The target priority bit rate is the product of the current priority bit rate and the third threshold; when the current priority has been the initial configuration priority, the target priority is the current priority; when the current priority When the priority is not the initial configuration, the target priority is decremented from the current priority.
  • the processing device provided in the embodiment of the present application can execute the technical solution shown in the above method embodiment, and its implementation principle and beneficial effect are similar, and will not be repeated here.
  • FIG. 11 is a schematic structural diagram of a communication device provided by an embodiment of the present application.
  • the communication device 1100 described in this embodiment may be the terminal device (or a component applicable to a terminal device) or a network device (or a component applicable to a network device) mentioned in the foregoing method embodiments.
  • the communication device 1100 may be used to implement the method corresponding to the terminal device or the network device described in the foregoing method embodiments, and for details, refer to the description in the foregoing method embodiments.
  • the communication device 1100 may include one or more processors 1101, and the processors 1101 may also be referred to as processing units, and may implement certain control or processing functions.
  • the processor 1101 may be a general-purpose processor or a special-purpose processor. For example, it may be a baseband processor or a central processing unit.
  • the baseband processor can be used to process communication protocols and communication data
  • the central processing unit can be used to control communication devices, execute software programs, and process data of software programs.
  • the processor 1101 may also store instructions 1103 or data (such as intermediate data).
  • the instruction 1103 may be executed by the processor 1101, so that the communication device 1100 executes the method corresponding to the terminal device or the network device described in the foregoing method embodiments.
  • the communication device 1100 may include a circuit, and the circuit may implement the function of sending or receiving or communicating in the foregoing method embodiments.
  • the communication device 1100 may include one or more memories 1102, on which instructions 1104 may be stored, and the instructions may be executed on the processor 1101, so that the communication device 1100 executes the methods described in the foregoing method embodiments.
  • data may also be stored in the memory 1102 .
  • the processor 1101 and the memory 1102 can be set independently or integrated together.
  • the communication device 1100 may further include a transceiver 1105 and/or an antenna 1106 .
  • the processor 1101 may be called a processing unit, and controls the communication device 1100 (terminal device or core network device or radio access network device).
  • the transceiver 1105 may be called a transceiver unit, a transceiver, a transceiver circuit, or a transceiver, etc., and is used to implement the transceiver function of the communication device 1100 .
  • the processor 1101 and transceiver 1105 described in this application can be implemented in IC (Integrated Circuit, integrated circuit), analog integrated circuit, RFIC (Radio Frequency Integrated Circuit, radio frequency integrated circuit), mixed signal integrated circuit, ASIC (Application Specific Integrated Circuit, ASIC), PCB (Printed Circuit Board, printed circuit board), electronic equipment, etc.
  • IC Integrated Circuit, integrated circuit
  • RFIC Radio Frequency Integrated Circuit, radio frequency integrated circuit
  • mixed signal integrated circuit aSIC (Application Specific Integrated Circuit, ASIC)
  • ASIC Application Specific Integrated Circuit
  • PCB Print Circuit Board, printed circuit board
  • electronic equipment etc.
  • the processor 1101 and the transceiver 1105 can also be manufactured with various integrated circuit technology, such as CMOS (Complementary Metal Oxide Semiconductor, complementary metal oxide semiconductor), NMOS (N Metal-Oxide-Semiconductor, N-type metal oxide semiconductor ), PMOS (Positive channel Metal Oxide Semiconductor, P-type metal oxide semiconductor), BJT (Bipolar Junction Transistor, bipolar junction transistor), bipolar CMOS (BiCMOS), silicon germanium (SiGe), gallium arsenide (GaAs) wait.
  • CMOS Complementary Metal Oxide Semiconductor, complementary metal oxide semiconductor
  • NMOS N Metal-Oxide-Semiconductor, N-type metal oxide semiconductor
  • PMOS Positive channel Metal Oxide Semiconductor, P-type metal oxide semiconductor
  • BJT Bipolar Junction Transistor, bipolar junction transistor
  • BiCMOS bipolar CMOS
  • SiGe silicon germanium
  • GaAs
  • a communication device may be a terminal device or a network device (such as a base station), which needs to be determined according to the context.
  • the terminal device may be implemented in various forms.
  • the terminal equipment described in this application may include mobile phones, tablet computers, notebook computers, palmtop computers, personal digital assistants (Personal Digital Assistant, PDA), portable media players (Portable Media Player, PMP), navigation devices, Mobile terminals such as wearable devices, smart bracelets, and pedometers, and fixed terminals such as digital TVs and desktop computers.
  • the communication device is described by taking the terminal device or network device as an example, the scope of the communication device described in this application is not limited to the above-mentioned terminal device or network device, and the structure of the communication device may not be limited Figure 11 Limitations.
  • a communication device may be a stand-alone device or may be part of a larger device.
  • FIG. 12 is a schematic diagram of the hardware structure of a controller 1200 provided by the present application.
  • the controller 1200 may include: a memory 1201 and a processor 1202.
  • the memory 1201 is used to store program instructions
  • the processor 1202 is used to call the program in the memory 1201.
  • the instruction executes the steps executed in the foregoing method embodiments, and its implementation principles and beneficial effects are similar, and will not be repeated here.
  • the above-mentioned controller further includes a communication interface 1203, which can be connected to the processor 1202 through the bus 1204, and the processor 1202 can control the communication interface 1203 to realize the receiving and sending functions of the controller 1200.
  • FIG. 13 is a schematic diagram of a hardware structure of a network node 1300 provided in the present application.
  • the network node 1300 may include: a memory 1301 and a processor 1302.
  • the memory 1301 is used to store program instructions
  • the processor 1302 is used to call programs in the memory 1301.
  • the instruction executes the steps executed in the foregoing method embodiments, and its implementation principles and beneficial effects are similar, and will not be repeated here.
  • the above-mentioned network node 1300 further includes a communication interface 1303, which can be connected to the processor 1302 through the bus 1304, and the processor 1302 can control the communication interface 1303 to implement the receiving and sending functions of the network node 1300.
  • the above-mentioned integrated modules implemented in the form of software function modules can be stored in a computer-readable storage medium.
  • the above-mentioned software function modules are stored in a storage medium, and include several instructions to enable a computer device (which may be a personal computer, server, or network device, etc.) or a processor (English: processor) to execute the methods of the various embodiments of the present application. partial steps.
  • An embodiment of the present application further provides a communication system, including: the terminal device in any one of the above method embodiments; and the network device in any one of the above method embodiments.
  • An embodiment of the present application further provides a communication device, which includes: a memory and a processor; wherein, a computer program is stored in the memory, and when the computer program is executed by the processor, the steps of the processing method in any of the foregoing embodiments are implemented.
  • An embodiment of the present application further provides a terminal device, and the terminal device includes: a memory and a processor; wherein, a computer program is stored in the memory, and when the computer program is executed by the processor, the steps of the processing method in any of the foregoing embodiments are implemented.
  • An embodiment of the present application also provides a network device, and the network device includes: a memory and a processor; wherein, a computer program is stored in the memory, and when the computer program is executed by the processor, the steps of the processing method in any of the foregoing embodiments are implemented.
  • An embodiment of the present application further provides a computer-readable storage medium, on which a computer program is stored, and when the computer program is executed by a processor, the steps of the processing method in any of the foregoing embodiments are implemented.
  • the embodiment of the present application also provides a computer program product, the computer program product includes computer program code, and when the computer program code is run on the computer, the computer is made to execute the methods in the above various possible implementation manners.
  • the embodiment of the present application also provides a chip, including a memory and a processor.
  • the memory is used to store a computer program
  • the processor is used to call and run the computer program from the memory, so that the device installed with the chip executes the above various possible implementation modes. Methods.
  • Units in the device in the embodiment of the present application may be combined, divided and deleted according to actual needs.
  • the methods of the above embodiments can be implemented by means of software plus a necessary general-purpose hardware platform, and of course also by hardware, but in many cases the former is better implementation.
  • the technical solution of the present application can be embodied in the form of a software product in essence or in other words, the part that contributes to the prior art, and the computer software product is stored in one of the above storage media (such as ROM/RAM, magnetic CD, CD), including several instructions to make a terminal device (which may be a mobile phone, computer, server, controlled terminal, or network device, etc.) execute the method of each embodiment of the present application.
  • all or part of them may be implemented by software, hardware, firmware or any combination thereof.
  • software When implemented using software, it may be implemented in whole or in part in the form of a computer program product.
  • a computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on the computer, the processes or functions according to the embodiments of the present application will be generated in whole or in part.
  • the computer can be a general purpose computer, special purpose computer, a computer network, or other programmable apparatus.
  • Computer instructions may be stored in or transmitted from one computer-readable storage medium to another computer-readable storage medium, e.g. Coaxial cable, optical fiber, digital subscriber line) or wireless (such as infrared, wireless, microwave, etc.) to another website site, computer, server or data center.
  • the computer-readable storage medium may be any available medium that can be accessed by a computer, or a data storage device such as a server, a data center, etc. integrated with one or more available media.
  • Usable media may be magnetic media, (eg, floppy disk, memory disk, magnetic tape), optical media (eg, DVD), or semiconductor media (eg, Solid State Disk (SSD)), among others.

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Abstract

本申请公开了一种处理方法、通信设备及存储介质，该方法包括：根据时延预算值计算或确定逻辑信道的时延预算结果，该时延预算结果用于指示数据在逻辑信道的缓存时延是否满足时延预算。然后，根据时延预算结果调整逻辑信道的PBR和或优先级，调整逻辑信道的PBR和/或优先级后，能够改变该逻辑信道获得的空口资源或优先级，从而改变数据在该逻辑信道的传输速率，进而改变数据在该逻辑信道的缓存时延。本申请的方案，实现了通过对逻辑信道的PBR和/或优先级的动态调整来控制数据在逻辑信道的缓存时延。

Description

处理方法、通信设备及存储介质
相关申请
本申请要求于2022年01月06日提交中国专利局、申请号为202210007414.1、发明名称为“处理方法、通信设备及存储介质”的中国专利申请的优先权，其全部内容通过引用结合在申请中。
技术领域
本申请涉及通信技术领域，具体涉及一种处理方法、通信设备及存储介质。
背景技术
一些实现中，终端设备可以基于网络设备配置的上行传输资源，确定在初传媒体接入控制分组数据单元(Medium Access Control Packet Data Unit，简称MAC PDU)中各个逻辑信道的传输数据量。
在构思及实现本申请过程中，发明人发现至少存在如下问题：为了实现上行逻辑信道的复用，网络无线资源控制(Radio Resource Control，简称RRC)会为每个上行逻辑信道配置以下参数：逻辑信道优先级(priority)：优先级的取值越小，对应的逻辑信道的优先级越高；PBR：优先比特速率，表示该逻辑信道需要保证的最小速率；令牌桶持续时间(Bucket Size Duration，简称BSD)：该参数确定令牌桶的深度。
当空口能力受限时，在逻辑信道上进行数据传输的实际速率会降低，此时数据从开始在逻辑信道进行缓存至通过逻辑信道传输这一过程的缓存时延较大。目前没有相应的方案解决空口能力受限情况下如何控制数据在逻辑信道的缓存时延的问题。
前面的叙述在于提供一般的背景信息，并不一定构成现有技术。
技术解决方案
本申请提供一种处理方法、通信设备及存储介质，以解决上述技术问题。
第一方面，本申请提供一种处理方法，可应用于终端设备或网络设备等通信设备，包括以下步骤：
S1、根据时延预算值计算或确定逻辑信道的时延预算结果；
S2、根据所述时延预算结果调整所述逻辑信道的优先比特率和/或优先级。
可选地，所述S1步骤包括：
根据所述逻辑信道在第一时长内的数据传输的实际速率和/或缓存数据量，以及所述时延预算值，计算或确定所述时延预算结果。
可选地，所述时延预算结果包括以下至少一种：
数据在所述逻辑信道的缓存时延不满足时延预算，所述实际速率和/或所述缓存数据量满足以下至少一项：所述实际速率小于或等于当前优先比特率，且所述缓存数据量大于或等于所述当前优先比特率与所述第一时长之积；所述缓存数据量大于或等于所述实际速率与所述时延预算值之积；所述缓存数据量大于或等于所述实际速率、所述时延预算值和第一阈值之积；
数据在所述逻辑信道的缓存时延满足所述时延预算，所述实际速率和/或所述缓存数据量满足以下至少一项：所述实际速率大于所述当前优先比特率；所述缓存数据量小于所述当前优先比特率与所述第一时长之积；所述缓存数据量小于所述实际速率与所述时延预算值之积；所述缓存数据量小于所述实际速率、所述时延预算值和所述第一阈值之积。
可选地，所述S2步骤，包括：
根据所述时延预算结果调整所述逻辑信道的优先比特率为目标优先比特率和/或根据所述时 延预算结果调整所述逻辑信道的优先级为目标优先级。
可选地，目标优先比特率为以下至少一项：
当前优先比特率；
初始优先比特率；
所述缓存数据量与所述时延预算值之商；
所述当前优先比特率与第二阈值之积，所述第二阈值为正数。
可选地，所述数据在所述逻辑信道的缓存时延不满足所述时延预算，所述目标优先比特率大于或等于当前优先比特率；和/或，
所述数据在所述逻辑信道的缓存时延满足所述时延预算，所述目标优先比特率小于或等于当前优先比特率；和/或，
所述数据在所述逻辑信道的缓存时延满足所述时延预算，所述目标优先级低于或等于当前优先级；和/或，
所述数据在所述逻辑信道的缓存时延不满足所述时延预算，所述目标优先级高于或等于当前优先级。
可选地，所述数据在所述逻辑信道的缓存时延不满足所述时延预算，包括以下至少一项：
所述目标优先比特率为以下至少一项：当前优先比特率、所述缓存数据量与所述时延预算值之商、所述当前优先比特率与所述第二阈值之积，所述第二阈值为大于或等于1的正数；
当所述当前优先比特率小于所述缓存数据量与所述时延预算值之商时，所述目标优先比特率为所述缓存数据量与所述时延预算值之商；
当所述当前优先比特率大于或等于所述缓存数据量与所述时延预算值之商时，所述目标优先比特率为所述当前优先比特率。
当所述当前优先比特率小于优先比特率门限值时，所述目标优先比特率为所述当前优先比特率与所述第二阈值之积；
当所述当前优先比特率大于或等于所述优先比特率门限值时，所述目标优先比特率为所述当前优先比特率；
当所述当前优先级已经为最高优先级时，所述目标优先级为所述当前优先级；
当所述当前优先级不为最高优先级时，所述目标优先级为所述当前优先级递增。
可选地，所述优先比特率门限值为所述缓存数据量与所述时延预算值之商；或者，所述优先比特率门限值为第三阈值。
可选地，所述数据在所述逻辑信道的缓存时延满足所述时延预算，包括以下至少一项：
所述目标优先比特率为以下至少一项：所述当前优先比特率、初始优先比特率、所述当前优先比特率与所述第二阈值之积，所述第二阈值为小于或等于1的正数。
当所述当前优先比特率小于或等于所述初始优先比特率时，所述目标优先比特率为所述当前优先比特率；
当所述当前优先比特率大于或等于所述初始优先比特率时，所述目标优先比特率为当前优先比特率与第三阈值之积；
当所述当前优先级已经为初始配置优先级时，所述目标优先级为所述当前优先级；
当所述当前优先级不为初始配置优先级时，所述目标优先级为所述当前优先级递减；。
第二方面，本申请提供一种处理方法，可应用于终端设备或网络设备等通信设备，包括以下步骤：
S10，响应于逻辑信道的时延预算结果满足预设条件，调整逻辑信道的优先比特率和/或优先级。
可选地，所述时延预算结果满足预设条件包括以下至少一种：
数据在所述逻辑信道的缓存时延不满足时延预算，所述逻辑信道在第一时长内的数据传输的 实际速率和/或缓存数据量满足以下至少一项：所述实际速率小于或等于当前优先比特率，且所述缓存数据量大于或等于所述当前优先比特率与所述第一时长之积、所述缓存数据量大于或等于所述实际速率与所述时延预算值之积、所述缓存数据量大于或等于所述实际速率、所述时延预算值和第一阈值之积；
数据在所述逻辑信道的缓存时延满足所述时延预算，所述实际速率和/或所述缓存数据量满足以下至少一项：所述实际速率大于所述当前优先比特率、所述缓存数据量小于所述当前优先比特率与所述第一时长之积、所述缓存数据量小于所述实际速率与所述时延预算值之积、所述缓存数据量小于所述实际速率、所述时延预算值和所述第一阈值之积。
可选地，所述调整所述逻辑信道的优先比特率和/或优先级，包括：
调整所述逻辑信道的优先比特率为目标优先比特率和/或调整所述逻辑信道的优先级为目标优先级。
可选地，目标优先比特率为以下至少一项：
当前优先比特率；
初始优先比特率；
所述缓存数据量与所述时延预算值之商；
所述当前优先比特率与第二阈值之积，所述第二阈值为正数。
可选地，所述数据在所述逻辑信道的缓存时延不满足所述时延预算，所述目标优先比特率大于或等于当前优先比特率；和/或，
所述数据在所述逻辑信道的缓存时延满足所述时延预算，所述目标优先比特率小于或等于当前优先比特率；和/或，
所述数据在所述逻辑信道的缓存时延满足所述时延预算，所述目标优先级低于或等于当前优先级；和/或，
所述数据在所述逻辑信道的缓存时延不满足所述时延预算，所述目标优先级高于或等于当前优先级。
可选地，所述数据在所述逻辑信道的缓存时延不满足所述时延预算，包括以下至少一项：
所述目标优先比特率为以下至少一项：当前优先比特率、所述缓存数据量与所述时延预算值之商、所述当前优先比特率与所述第二阈值之积，所述第二阈值为大于或等于1的正数；
当所述当前优先比特率小于所述缓存数据量与所述时延预算值之商时，所述目标优先比特率为所述缓存数据量与所述时延预算值之商；
当所述当前优先比特率大于或等于所述缓存数据量与所述时延预算值之商时，所述目标优先比特率为所述当前优先比特率。
当所述当前优先比特率小于优先比特率门限值时，所述目标优先比特率为所述当前优先比特率与所述第二阈值之积；
当所述当前优先比特率大于或等于所述优先比特率门限值时，所述目标优先比特率为所述当前优先比特率；
当所述当前优先级已经为最高优先级时，所述目标优先级为所述当前优先级；
当所述当前优先级不为最高优先级时，所述目标优先级为所述当前优先级递增。
可选地，所述优先比特率门限值为所述缓存数据量与所述时延预算值之商；或者，所述优先比特率门限值为第三阈值。
可选地，所述数据在所述逻辑信道的缓存时延满足所述时延预算，包括以下至少一项：
所述目标优先比特率为以下至少一项：所述当前优先比特率、初始优先比特率、所述当前优先比特率与所述第二阈值之积，所述第二阈值为小于或等于1的正数。
当所述当前优先比特率小于或等于所述初始优先比特率时，所述目标优先比特率为所述当前优先比特率；
当所述当前优先比特率大于或等于所述初始优先比特率时，所述目标优先比特率为当前优先比特率与第三阈值之积；
当所述当前优先级已经为初始配置优先级时，所述目标优先级为所述当前优先级；
当所述当前优先级不为初始配置优先级时，所述目标优先级为所述当前优先级递减。
第三方面，本申请提供一种处理装置，包括：
处理模块，用于根据时延预算值计算或确定逻辑信道的时延预算结果；
调整模块，用于根据所述时延预算结果调整所述逻辑信道的优先比特率和/或优先级。
第四方面，本申请提供一种处理装置，包括：
处理模块，用于响应于逻辑信道的时延预算结果满足预设条件，调整所述逻辑信道的优先比特率和/或优先级。
第五方面，本申请提供一种通信设备，包括：存储器和处理器；
所述存储器用于存储程序指令；
所述处理器用于调用所述存储器中的程序指令以执行如第一方面或第二方面中任一项所述的处理方法。
第六方面，本申请提供一种计算机可读存储介质，所述存储介质上存储有计算机程序；所述计算机程序被执行时，实现如第一方面或第二方面中任一项所述的处理方法。
本申请提供的处理方法、通信设备及存储介质，首先根据时延预算值确定逻辑信道的时延预算结果，该时延预算结果用于指示数据在逻辑信道的缓存时延是否满足时延预算。然后，根据时延预算结果调整逻辑信道的PBR和/或优先级，调整逻辑信道的PBR和/或优先级后，能够改变逻辑信道获得的空口资源和/或处理级别，从而改变数据在逻辑信道的传输速率，进而改变数据在逻辑信道的缓存时延。本申请的方案，实现了通过对逻辑信道的PBR和/或优先级的动态调整来控制数据在逻辑信道的缓存时延。
附图说明
此处的附图被并入说明书中并构成本说明书的一部分，示出了符合本申请的实施例，并与说明书一起用于解释本申请的原理。为了更清楚地说明本申请实施例的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，对于本领域普通技术人员而言，在不付出创造性劳动性的前提下，还可以根据这些附图获得其他的附图。
图1为本申请实施例提供的一种终端设备的硬件结构示意图；
图2为本申请实施例提供的一种通信网络系统架构图；
图3为本申请实施例提供的处理方法的流程示意图一；
图4为本申请实施例提供的调整逻辑信道的PBR的流程示意图；
图5为本申请实施例提供的处理方法的流程示意图二；
图6为本申请实施例提供的PBR调整示意图一；
图7为本申请实施例提供的PBR调整示意图二；
图8为本申请实施例提供的PBR调整示意图三；
图9为本申请实施例提供的处理装置的结构示意图一；
图10为本申请实施例提供的处理装置的结构示意图二；
图11为本申请实施例提供的通信设备的结构示意图；
图12为本申请实施例提供的一种控制器的硬件结构示意图；
图13为本申请实施例提供的一种网络节点的硬件结构示意图。
本申请目的的实现、功能特点及优点将结合实施例，参照附图做进一步说明。通过上述附图，已示出本申请明确的实施例，后文中将有更详细的描述。这些附图和文字描述并不是为了通过任何方式限制本申请构思的范围，而是通过参考特定实施例为本领域技术人员说明本申请的概念。
本申请的实施方式
这里将详细地对示例性实施例进行说明，其示例表示在附图中。下面的描述涉及附图时，除非另有表示，不同附图中的相同数字表示相同或相似的要素。以下示例性实施例中所描述的实施方式并不代表与本申请相一致的所有实施方式。相反，它们仅是与如所附权利要求书中所详述的、本申请的一些方面相一致的装置和方法的例子。
需要说明的是，在本文中，术语“包括”、“包含”或者其任何其他变体意在涵盖非排他性的包含，从而使得包括一系列要素的过程、方法、物品或者装置不仅包括那些要素，而且还包括没有明确列出的其他要素，或者是还包括为这种过程、方法、物品或者装置所固有的要素。在没有更多限制的情况下，由语句“包括一个……”限定的要素，并不排除在包括该要素的过程、方法、物品或者装置中还存在另外的相同要素，此外，本申请不同实施例中具有同样命名的部件、特征、要素可能具有相同含义，也可能具有不同含义，其具体含义需以其在该具体实施例中的解释或者进一步结合该具体实施例中上下文进行确定。
应当理解，尽管在本文可能采用术语第一、第二、第三等来描述各种信息，但这些信息不应限于这些术语。这些术语仅用来将同一类型的信息彼此区分开。例如，在不脱离本文范围的情况下，第一信息也可以被称为第二信息，类似地，第二信息也可以被称为第一信息。取决于语境，如在此所使用的词语"如果"可以被解释成为"在……时"或"当……时"或"响应于确定"。再者，如同在本文中所使用的，单数形式“一”、“一个”和“该”旨在也包括复数形式，除非上下文中有相反的指示。应当进一步理解，术语“包含”、“包括”表明存在所述的特征、步骤、操作、元件、组件、项目、种类、和/或组，但不排除一个或多个其他特征、步骤、操作、元件、组件、项目、种类、和/或组的存在、出现或添加。本申请使用的术语“或”、“和/或”、“包括以下至少一个”等可被解释为包括性的，或意味着任一个或任何组合。例如，“包括以下至少一个：A、B、C”意味着“以下任一个：A；B；C；A和B；A和C；B和C；A和B和C”，再如，“A、B或C”或者“A、B和/或C”意味着“以下任一个：A；B；C；A和B；A和C；B和C；A和B和C”。仅当元件、功能、步骤或操作的组合在某些方式下内在地互相排斥时，才会出现该定义的例外。
应该理解的是，虽然本申请实施例中的流程图中的各个步骤按照箭头的指示依次显示，但是这些步骤并不是必然按照箭头指示的顺序依次执行。除非本文中有明确的说明，这些步骤的执行并没有严格的顺序限制，其可以以其他的顺序执行。而且，图中的至少一部分步骤可以包括多个子步骤或者多个阶段，这些子步骤或者阶段并不必然是在同一时刻执行完成，而是可以在不同的时刻执行，其执行顺序也不必然是依次进行，而是可以与其他步骤或者其他步骤的子步骤或者阶段的至少一部分轮流或者交替地执行。
取决于语境，如在此所使用的词语“如果”、“若”可以被解释成为“在……时”或“当……时”或“响应于确定”或“响应于检测”。类似地，取决于语境，短语“如果确定”或“如果检测(陈述的条件或事件)”可以被解释成为“当确定时”或“响应于确定”或“当检测(陈述的条件或事件)时”或“响应于检测(陈述的条件或事件)”。
需要说明的是，在本文中，采用了诸如S1、S2等步骤代号，其目的是为了更清楚简要地表述相应内容，不构成顺序上的实质性限制，本领域技术人员在具体实施时，可能会先执行S2后执行S1等，但这些均应在本申请的保护范围之内。
应当理解，此处所描述的具体实施例仅仅用以解释本申请，并不用于限定本申请。
在后续的描述中，使用用于表示元件的诸如“模块”、“部件”或者“单元”的后缀仅为了有利于本申请的说明，其本身没有特定的意义。因此，“模块”、“部件”或者“单元”可以混合地使用。
智能终端可以以各种形式来实施。例如，本申请中描述的智能终端可以包括诸如手机、平板电脑、笔记本电脑、掌上电脑、个人数字助理(Personal Digital Assistant，PDA)、便捷式媒 体播放器(Portable Media Player，PMP)、导航装置、可穿戴设备、智能手环、计步器等智能终端，以及诸如数字TV、台式计算机等固定终端。
后续描述中将以移动终端为例进行说明，本领域技术人员将理解的是，除了特别用于移动目的的元件之外，根据本申请的实施方式的构造也能够应用于固定类型的终端。
请参阅图1，其为实现本申请各个实施例的一种终端设备的硬件结构示意图，该终端设备100可以包括：RF(Radio Frequency，射频)单元101、WiFi模块102、音频输出单元103、A/V(音频/视频)输入单元104、传感器105、显示单元106、用户输入单元107、接口单元108、存储器109、处理器110、以及电源111等部件。本领域技术人员可以理解，图1中示出的终端设备结构并不构成对终端设备的限定，终端设备可以包括比图示更多或更少的部件，或者组合某些部件，或者不同的部件布置。
下面结合图1对终端设备的各个部件进行具体的介绍：
射频单元101可用于收发信息或通话过程中，信号的接收和发送，可选地，将基站的下行信息接收后，给处理器110处理；另外，将上行的数据发送给基站。通常，射频单元101包括但不限于天线、至少一个放大器、收发信机、耦合器、低噪声放大器、双工器等。此外，射频单元101还可以通过无线通信与网络和其他设备通信。上述无线通信可以使用任一通信标准或协议，包括但不限于GSM(Global System of Mobile communication，全球移动通讯系统)、GPRS(General Packet Radio Service，通用分组无线服务)、CDMA2000(Code Division Multiple Access 2000，码分多址2000)、WCDMA(Wideband Code Division Multiple Access,宽带码分多址)、TD-SCDMA(Time Division-Synchronous Code Division Multiple Access，时分同步码分多址)、FDD-LTE(Frequency Division Duplexing-Long Term Evolution，频分双工长期演进)、TDD-LTE(Time Division Duplexing-Long Term Evolution，分时双工长期演进)和5G等。
WiFi属于短距离无线传输技术，终端设备通过WiFi模块102可以帮助用户收发电子邮件、浏览网页和访问流式媒体等，它为用户提供了无线的宽带互联网访问。虽然图1示出了WiFi模块102，但是可以理解的是，其并不属于终端设备的必须构成，完全可以根据需要在不改变发明的本质的范围内而省略。
音频输出单元103可以在终端设备100处于呼叫信号接收模式、通话模式、记录模式、语音识别模式、广播接收模式等等模式下时，将射频单元101或WiFi模块102接收的或者在存储器109中存储的音频数据转换成音频信号并且输出为声音。而且，音频输出单元103还可以提供与终端设备100执行的特定功能相关的音频输出(例如，呼叫信号接收声音、消息接收声音等等)。音频输出单元103可以包括扬声器、蜂鸣器等等。
A/V输入单元104用于接收音频或视频信号。A/V输入单元104可以包括图形处理器(Graphics Processing Unit，GPU)1041和麦克风1042，图形处理器1041对在视频捕获模式或图像捕获模式中由图像捕获装置(如摄像头)获得的静态图片或视频的图像数据进行处理。处理后的图像帧可以显示在显示单元106上。经图形处理器1041处理后的图像帧可以存储在存储器109(或其它存储介质)中或者经由射频单元101或WiFi模块102进行发送。麦克风1042可以在电话通话模式、记录模式、语音识别模式等等运行模式中经由麦克风1042接收声音(音频数据)，并且能够将这样的声音处理为音频数据。处理后的音频(语音)数据可以在电话通话模式的情况下转换为可经由射频单元101发送到移动通信基站的格式输出。麦克风1042可以实施各种类型的噪声消除(或抑制)算法以消除(或抑制)在接收和发送音频信号的过程中产生的噪声或者干扰。
终端设备100还包括至少一种传感器105，比如光传感器、运动传感器以及其他传感器。可选地，光传感器包括环境光传感器及接近传感器，可选地，环境光传感器可根据环境光线的明暗来调节显示面板1061的亮度，接近传感器可在终端设备100移动到耳边时，关闭显示面板1061和/或背光。作为运动传感器的一种，加速计传感器可检测各个方向上(一般为三轴)加速度的大小，静止时可检测出重力的大小及方向，可用于识别手机姿态的应用(比如横竖屏切换、相关游 戏、磁力计姿态校准)、振动识别相关功能(比如计步器、敲击)等；至于手机还可配置的指纹传感器、压力传感器、虹膜传感器、分子传感器、陀螺仪、气压计、湿度计、温度计、红外线传感器等其他传感器，在此不再赘述。
显示单元106用于显示由用户输入的信息或提供给用户的信息。显示单元106可包括显示面板1061，可以采用液晶显示器(Liquid Crystal Display，LCD)、有机发光二极管(Organic Light-Emitting Diode,OLED)等形式来配置显示面板1061。
用户输入单元107可用于接收输入的数字或字符信息，以及产生与终端设备的用户设置以及功能控制有关的键信号输入。可选地，用户输入单元107可包括触控面板1071以及其他输入设备1072。触控面板1071，也称为触摸屏，可收集用户在其上或附近的触摸操作(比如用户使用手指、触笔等任何适合的物体或附件在触控面板1071上或在触控面板1071附近的操作)，并根据预先设定的程式驱动相应的连接装置。触控面板1071可包括触摸检测装置和触摸控制器两个部分。可选地，触摸检测装置检测用户的触摸方位，并检测触摸操作带来的信号，将信号传送给触摸控制器；触摸控制器从触摸检测装置上接收触摸信息，并将它转换成触点坐标，再送给处理器110，并能接收处理器110发来的命令并加以执行。此外，可以采用电阻式、电容式、红外线以及表面声波等多种类型实现触控面板1071。除了触控面板1071，用户输入单元107还可以包括其他输入设备1072。可选地，其他输入设备1072可以包括但不限于物理键盘、功能键(比如音量控制按键、开关按键等)、轨迹球、鼠标、操作杆等中的一种或多种，具体此处不做限定。
可选地，触控面板1071可覆盖显示面板1061，当触控面板1071检测到在其上或附近的触摸操作后，传送给处理器110以确定触摸事件的类型，随后处理器110根据触摸事件的类型在显示面板1061上提供相应的视觉输出。虽然在图1中，触控面板1071与显示面板1061是作为两个独立的部件来实现终端设备的输入和输出功能，但是在某些实施例中，可以将触控面板1071与显示面板1061集成而实现终端设备的输入和输出功能，具体此处不做限定。
接口单元108用作至少一个外部装置与终端设备100连接可以通过的接口。例如，外部装置可以包括有线或无线头戴式耳机端口、外部电源(或电池充电器)端口、有线或无线数据端口、存储卡端口、用于连接具有识别模块的装置的端口、音频输入/输出(I/O)端口、视频I/O端口、耳机端口等等。接口单元108可以用于接收来自外部装置的输入(例如，数据信息、电力等等)并且将接收到的输入传输到终端设备100内的一个或多个元件或者可以用于在终端设备100和外部装置之间传输数据。
存储器109可用于存储软件程序以及各种数据。存储器109可主要包括存储程序区和存储数据区，可选地，存储程序区可存储操作系统、至少一个功能所需的应用程序(比如声音播放功能、图像播放功能等)等；存储数据区可存储根据手机的使用所创建的数据(比如音频数据、电话本等)等。此外，存储器109可以包括高速随机存取存储器，还可以包括非易失性存储器，例如至少一个磁盘存储器件、闪存器件、或其他易失性固态存储器件。
处理器110是终端设备的控制中心，利用各种接口和线路连接整个终端设备的各个部分，通过运行或执行存储在存储器109内的软件程序和/或模块，以及调用存储在存储器109内的数据，执行终端设备的各种功能和处理数据，从而对终端设备进行整体监控。处理器110可包括一个或多个处理单元；优选的，处理器110可集成应用处理器和调制解调处理器，可选地，应用处理器主要处理操作系统、用户界面和应用程序等，调制解调处理器主要处理无线通信。可以理解的是，上述调制解调处理器也可以不集成到处理器110中。
终端设备100还可以包括给各个部件供电的电源111(比如电池)，优选的，电源111可以通过电源管理系统与处理器110逻辑相连，从而通过电源管理系统实现管理充电、放电、以及功耗管理等功能。
尽管图1未示出，终端设备100还可以包括蓝牙模块等，在此不再赘述。
为了便于理解本申请实施例，下面对本申请的移动终端所基于的通信网络系统进行描述。
为了便于理解本申请实施例，下面对本申请的终端设备所基于的通信网络系统进行描述。
请参阅图2，图2为本申请实施例提供的一种通信网络系统架构图，该通信网络系统为通用移动通信技术的LTE系统，该LTE系统包括依次通讯连接的UE(User Equipment，用户设备)201，E-UTRAN(Evolved UMTS Terrestrial Radio Access Network，演进式UMTS陆地无线接入网)202，EPC(Evolved Packet Core，演进式分组核心网)203和运营商的IP业务204。
可选地，UE201可以是上述终端设备100，此处不再赘述。
E-UTRAN202包括eNodeB2021和其它eNodeB2022等。可选地，eNodeB2021可以通过回程(backhaul)(例如X2接口)与其它eNodeB2022连接，eNodeB2021连接到EPC203，eNodeB2021可以提供UE 201到EPC 203的接入。
EPC203可以包括MME(Mobility Management Entity，移动性管理实体)2031，HSS(Home Subscriber Server，归属用户服务器)2032，其它MME2033，SGW(Serving Gate Way，服务网关)2034，PGW(PDN Gate Way，分组数据网络网关)2035和PCRF(Policy and Charging Rules Function，政策和资费功能实体)2036等。可选地，MME2031是处理UE201和EPC203之间信令的控制节点，提供承载和连接管理。HSS2032用于提供一些寄存器来管理诸如归属位置寄存器(图中未示)之类的功能，并且保存有一些有关服务特征、数据速率等用户专用的信息。所有用户数据都可以通过SGW2034进行发送，PGW2035可以提供UE201的IP地址分配以及其它功能，PCRF2036是业务数据流和IP承载资源的策略与计费控制策略决策点，它为策略与计费执行功能单元(图中未示)选择及提供可用的策略和计费控制决策。
IP业务204可以包括因特网、内联网、IMS(IP Multimedia Subsystem，IP多媒体子系统)或其它IP业务等。
虽然上述以LTE系统为例进行了介绍，但本领域技术人员应当知晓，本申请不仅仅适用于LTE系统，也可以适用于其他无线通信系统，例如GSM、CDMA2000、WCDMA、TD-SCDMA以及未来新的网络系统(如5G)等，此处不做限定。
基于上述终端设备硬件结构以及通信网络系统，提出本申请各个实施例。
图3为本申请实施例提供的处理方法的流程示意图一，本实施例以执行本处理方法的主体为终端设备(如UE)为例进行示例说明，实际实现中，也可能由网络设备来执行，如图3所示，该方法包括：
S31，根据时延预算值计算或确定逻辑信道的时延预算结果。
在5G NR中，网络是基于每个UE而不是每个无线承载(per-bearer)分配上行传输资源的，哪些无线承载的数据能够放入分配的上行传输资源中传输是由UE确定的。基于网络配置的上行传输资源，UE需要确定在初传媒体接入控制分组数据单元(Medium Access Control Packet Data Unit，MAC PDU)中的每个逻辑信道的传输数据量，在某些情况下UE还要为MAC控制单元(MAC Control Element，MAC CE)分配资源。为了实现上行逻辑信道(Logical Channel，LCH)的复用，需要为每个上行逻辑信道分配一个优先级。对于一个给定大小的MAC PDU，在有多个上行逻辑信道同时有数据传输需求的情况下，按照有各个上行逻辑信道对应的逻辑信道优先级从大到小的顺序依次分配该MAC PDU的资源。同时，为了兼顾不同逻辑信道之间的公平性，引入了优先比特速率(Prioritized Bit Rate，PBR)的概率，在UE进行逻辑信道复用时，需要先保证各个逻辑信道的最小数据速率需求，从而避免由于优先级高的上行逻辑信道始终占据网络分配给UE的上行资源导致该UE的其他优先级低的上行逻辑信道被“饿死”的情况。
为了实现上行逻辑信道的复用，网络无线资源控制为每个上行逻辑信道配置以下参数：
逻辑信道优先级(priority)：优先级的取值越小，对应的逻辑信道的优先级越高；
PBR：优先比特率，表示该逻辑信道需要保证的最小速率；
令牌桶持续时间BSD：该参数确定令牌桶的深度。
UE的MAC使用令牌桶机制实现上行逻辑信道复用。UE为每个上行逻辑信道j维护一个变量 Bj，该变量指示了令牌桶里当前可用的令牌数。可选地，UE在建立逻辑信道j时，初始化Bj为0；UE在每次逻辑信道优先级(Logical Channel Priority，简称LCP)处理过程之前，将Bj增加PBR*T，其中T为上次增加Bj的时刻到当前时刻的时间间隔；如果按照上述步骤更新后的Bj大于令牌桶最大容量(即PBR*BSD)，则将Bj设置为令牌桶的最大容量。
当UE收到指示新传的上行授权资源(UL grant)时，UE按照如下步骤进行逻辑信道优先级处理：
1：对于所有Bj>0的逻辑信道，按照优先级从高到低的顺序分配资源，每个逻辑信道分配的资源只能满足PBR的要求，即根据逻辑信道对应的PBR令牌桶中的令牌数为该逻辑信道分配资源。当某个逻辑信道的PBR设置为无穷大时，只有当这个逻辑信道的资源得到满足后，才会考虑比它优先级低的逻辑信道。
2：将Bj减去逻辑信道j在S1里复用到MAC PDU的所有MAC SDU的大小。
3：如果执行完S1和S2之后还有剩余的上行资源，则不管Bj的大小，把剩余的资源按照逻辑信道优先级从高到低的顺序依次分配给各个逻辑信道。只有当高优先级的逻辑信道的数据都发送完毕且UL grant还未耗尽的情况下，低优先级的逻辑信道才能得到服务。即此时UE最大化高优先级的逻辑信道的数据传输。
在空口能力受限时，逻辑信道中的数据传输速率取决于空口速率，因此逻辑信道中的数据传输速率也相应受限。数据在逻辑信道的缓存时延指的是数据从缓存到逻辑信道直至从逻辑信道完成传输这一过程的时长，当逻辑信道中的数据传输速率受限时，也会导致数据在逻辑信道的缓存时延增加。
为了控制数据在逻辑信道的缓存时延，可以为逻辑信道设置时延预算值(delay budget value)，以实现缓存时延的动态调整，从而达到时延控制的目的。
可选地，当逻辑信道被配置了时延预算值时，可以基于时延预算值控制数据在逻辑信道的缓存时延。
可选地，当逻辑信道未被配置时延预算值时，不保证数据在逻辑信道的缓存时延。
可选地，时延预算值由网络设备为终端设备配置。
终端设备根据时延预算值可以计算或确定逻辑信道的时延预算结果，时延预算结果用于指示数据在逻辑信道的缓存时延是否满足时延预算。
S32，根据时延预算结果调整逻辑信道的优先比特率和/或优先级。
数据在逻辑信道的缓存时延可能满足时延预算，也可能不满足时延预算。当数据在逻辑信道的缓存时延满足时延预算时，表示数据在逻辑信道的缓存时延较小，此时可以不对逻辑信道的PBR进行调整，也可以将逻辑信道的PBR调小，从而将更多的空口资源分配给其他对时延预算要求较高的逻辑信道。
当数据在逻辑信道的缓存时延不满足时延预算时，表示数据在逻辑信道的缓存时延较大，此时可以将逻辑信道的PBR调大，从而使得该逻辑信道能够被分配更多的资源，降低数据在该逻辑信道的缓存时延。
可选地，逻辑信道可以在至少一个优先级工作，可以根据延时预算结果调整逻辑信道的优先级。逻辑信道的优先级越高，分配资源优先级越高，数据在该逻辑信道的缓存时延越低，响应速度越快。逻辑信道的优先级越低，分配资源优先级越低，数据在该逻辑信道的缓存时延越高，响应速度越慢。通过优先级的设置可以影响数据在该逻辑信道的缓存时延，进而对逻辑信道的响应速度进行调整。例如，发送数据时，信道优先级高的逻辑信道优先分配资源，先发送，信道优先级低的逻辑信道后分配资源，后发送。
首先介绍确定逻辑信道的时延预算结果的方案。
图4为本申请实施例提供的调整逻辑信道的PBR的流程示意图，如图4所示，包括：
S41，确定逻辑信道配置了参数时延预算值。
S42，判断计时器是否达到第一时长，若是，执行S43。
可选地，第一时长为网络设备配置的时长，第一时长为该计时器的时长。
可选地，PBR根据第一时长周期性调整。
S43，获取逻辑信道的时延预算结果。
可选地，获取逻辑信道在第一时长内的数据传输的实际速率和/或缓存数据量，然后根据实际速率和/或缓存数据量，以及时延预算值，计算或确定时延预算结果。
实际速率为数据在第一时长内在逻辑信道的传输速率，由于逻辑信道内的数据传输速率是动态变化的，因此实际速率的获取方式有多种实现形式。
一种可能的方式是，获取第一时长内在逻辑信道传输的数据量，然后根据第一时长内在逻辑信道传输的数据量和第一时长，确定实际速率，即v＝L/t，v为实际速率，L为第一时长内在逻辑信道传输的数据量，t为第一时长。
一种可能的实现方式是，通过滑窗平均值或滤波平均值确定实际速率。例如，可以获取第一时长内的N个时刻在逻辑信道的数据传输速率，然后对这N个数据传输速率取平均值，得到实际速率。例如，可以获取第一时长内的M个时段内逻辑信道的数据传输速率，然后对这M个数据传输速率取平均值，得到实际速率。
缓存数据量为在第一时长内新缓存到该逻辑信道的数据的大小，以第一时长为t1-t2之间的时段为例，在t1-t2时段内新缓存到该逻辑信道的数据即为缓存数据，新缓存到该逻辑信道的数据大小即为该缓存数据量。
在获取实际速率和/或缓存数据量后，可以通过如下方式确定逻辑信道的时延预算结果。
方法1.1：判断实际速率是否小于或等于当前PBR，且缓存数据量大于或等于当前PBR与第一时长之积。
若是，则确定时延预算结果为数据在逻辑信道的缓存时延不满足时延预算。
和/或，若否，即实际速率大于当前PBR，或缓存数据量小于当前PBR与第一时长之积，则确定时延预算结果为数据在逻辑信道的缓存时延满足时延预算。
方法1.2：判断缓存数据量是否大于或等于实际速率与时延预算值之积，若是，则确定时延预算结果为数据在逻辑信道的缓存时延不满足时延预算；和/或，若否，则确定时延预算结果为数据在逻辑信道的缓存时延满足时延预算。
方法1.3：判断缓存数据量是否大于或等于实际速率、时延预算值和第一阈值之积，若是，则确定时延预算结果为数据在逻辑信道的缓存时延不满足时延预算；和/或，若否，则确定时延预算结果为数据在逻辑信道的缓存时延满足时延预算。
可选地，第一阈值为大于或等于0的值，例如可以为80％、90％、等等。
可选地，第一阈值可以由网络设备为终端设备配置，也可以由终端设备配置。
S44，调整逻辑信道的PBR为目标PBR和/或调整逻辑信道的优先级为目标优先级。
在获取逻辑信道的时延预算结果后，可以根据时延预算结果调整PBR为目标PBR。
可选地，当时延预算结果为数据在逻辑信道的缓存时延不满足时延预算时，目标PBR大于或等于当前PBR，即在不满足时延预算时，调大逻辑信道的PBR，以使得逻辑信道获取更多的空口资源，提高数据在该逻辑信道的传输速率，进而降低数据在该逻辑信道的缓存时延。
可选地，当数据在逻辑信道的缓存时延不满足时延预算时，可以通过如下方式调整逻辑信道的PBR：
方法2.1：若当前PBR小于缓存数据量与时延预算值之商，则将当前PBR调整为缓存数据量与时延预算值之商，即目标PBR＝缓存数据量/时延预算值；和/或，若当前PBR大于或等于缓存数据量与时延预算值之商，则不对当前PBR进行调整，即目标PBR＝当前PBR。
方法2.2：若当前PBR小于PBR门限值，将当前PBR与第二阈值相乘，得到目标PBR，其中第二阈值a为大于或等于1的正数，即目标PBR＝a*当前PBR。和/或，若当前PBR大于或等于PBR 门限值，则不对当前PBR进行调整，即目标PBR＝当前PBR。
可选地，第二阈值a可以为网络设备配置的数值，也可以为终端设备配置的数值。
可选地，PBR门限值为缓存数据量与时延预算值之商。
可选地，PBR门限值可以为第三阈值。
可选地，第三阈值可以为网络设备配置的数值，也可以为终端设备配置的数值。
综上所述，当数据在逻辑信道的缓存时延不满足时延预算时，目标PBR为当前PBR、缓存数据量与时延预算值之商、当前优先比特率与第二阈值a之积中的至少一项，第二阈值a为大于或等于1的正数。
可选地，当时延预算结果为数据在逻辑信道的缓存时延满足时延预算时，目标PBR小于当前PBR，即在满足时延预算时，调小逻辑信道的PBR，以使得逻辑信道获取的空口资源减少，进而使得有限的空口资源能够更多的分配给不满足时延预算的逻辑信道。
可选地，当数据在逻辑信道的缓存时延满足时延预算时，可以通过如下方式调整逻辑信道的PBR：
方法2.3：将逻辑信道的PBR恢复为初始PBR。
方法2.4：若当前PBR小于或等于初始PBR，不对当前PBR进行调整，即目标PBR＝当前PBR。和/或，若当前PBR大于PBR，将当前PBR与第二阈值相乘，得到目标PBR，其中第二阈值b为小于1的正数，即目标PBR＝b*当前PBR。
可选地，第二阈值b可以为网络设备配置的数值，也可以为终端设备配置的数值。
综上所述，当数据在逻辑信道的缓存时延满足时延预算时，目标PBR为当前PBR、初始PBR、当前优先比特率与第二阈值b之积中的至少一项，第二阈值b为小于1的正数。
在获取逻辑信道的时延预算结果后，可以根据时延预算结果调整逻辑信道的优先级为目标优先级。
可选地，当时延预算结果为数据在逻辑信道的缓存时延不满足时延预算，目标优先级高于或等于当前优先级，即在不满足时延预算时，调大逻辑信道的优先级，以使得逻辑信道的处理级别更高，提高数据在该逻辑信道的响应速度，进而降低数据在该逻辑信道的缓存时延。
可选地，当数据在逻辑信道的缓存时延不满足时延预算时，可以通过如下实施方式调整逻辑信道的优先级：
实施方式3.1:若当前优先级为最高优先级，目标优先级为当前优先级。
实时方式3.2：若当前优先级不为最高优先级，目标优先级为当前优先级递增。
本实施例中，逻辑信道的优先级可以划分为多个，若当前优先级已为最高优先级，则逻辑信道的优先级不能再提高，可以目标优先级为当前优先级。若当前优先级不为最高优先级，则逻辑信道的优先级可以提升一级或多级，目标优先级为当前优先级递增。通过优先级增加的方式，实现对不满足延时预算的逻辑信道的及时调整，以确保数据传输的正常。
可选地，当时延预算结果为数据在逻辑信道的缓存时延满足时延预算，目标优先级低于当前优先级，即在满足时延预算时，调低逻辑信道的优先级，以降低逻辑信道的处理级别，为更高的逻辑信道的处理作出让步，进而提升逻辑信道整体的数据缓存效率。
可选地，当数据在逻辑信道的缓存时延满足时延预算时，可以通过如下实施方式调整逻辑信道的优先级：
实施方式4.1，若当前优先级已经为初始配置优先级时，所述目标优先级为所述当前优先级。
实施方式4.2，若当前优先级不为初始配置优先级时，所述目标优先级为所述当前优先级递减。
可选地，初始配置优先级可以为逻辑信道对应的最小优先级。当然，在实际应用中，初始配置优先级也可以为逻辑信道的任意优先级，初始配置优先级之后，逻辑信道的处理优先级的最小优先级即可以为该逻辑信道的初始配置优先级，因此，调整后的目标优先级不能低于初始配置优 先级。
本实施例中，逻辑信道的优先级可以划分为多个，若当前优先级已为初始配置的优先级，不能再对优先级进行减少，以免影响数据传输，因此，可以目标优先级为当前优先级。若当前优先级不为初始配置优先级，可以将当前优先级降级，以获得目标优先级。实现对满足时延预算的逻辑信道的及时调整，以确保数据的正常传输。
图5为本申请实施例提供的处理方法的流程示意图二，本实施例以执行本处理方法的主体为终端设备(如UE)为例进行示例说明，实际实现中，也可能由网络设备来执行，如图5所示，该方法包括：
S51，响应于逻辑信道的时延预算结果满足预设条件，调整逻辑信道的优先比特率和/或优先级。
在5G NR中，网络是基于每个UE而不是每个无线承载(per-bearer)分配上行传输资源的，哪些无线承载的数据能够放入分配的上行传输资源中传输是由UE确定的。基于网络配置的上行传输资源，UE需要确定在初传媒体接入控制分组数据单元(Medium Access Control Packet Data Unit，MAC PDU)中的每个逻辑信道的传输数据量，在某些情况下UE还要为MAC控制单元(MAC Control Element，MAC CE)分配资源。为了实现上行逻辑信道(Logical Channe l，LCH)的复用，需要为每个上行逻辑信道分配一个优先级。对于一个给定大小的MAC PDU，在有多个上行逻辑信道同时有数据传输需求的情况下，按照有各个上行逻辑信道对应的逻辑信道优先级从大到小的顺序依次分配该MAC PDU的资源。同时，为了兼顾不同逻辑信道之间的公平性，引入了优先比特速率(Prioritized Bit Rate，PBR)的概率，在UE进行逻辑信道复用时，需要先保证各个逻辑信道的最小数据速率需求，从而避免由于优先级高的上行逻辑信道始终占据网络分配给UE的上行资源导致该UE的其他优先级低的上行逻辑信道被“饿死”的情况。
为了实现上行逻辑信道的复用，网络无线资源控制为每个上行逻辑信道配置以下参数：
逻辑信道优先级(priority)：优先级的取值越小，对应的逻辑信道的优先级越高；
PBR：优先比特率，表示该逻辑信道需要保证的最小速率；
令牌桶持续时间BSD：该参数确定令牌桶的深度。
UE的MAC使用令牌桶机制实现上行逻辑信道复用。UE为每个上行逻辑信道j维护一个变量Bj，该变量指示了令牌桶里当前可用的令牌数。可选地，UE在建立逻辑信道j时，初始化Bj为0；UE在每次逻辑信道优先级(Logical Channel Priority，LCP)处理过程之前，将Bj增加PBR*T，其中T为上次增加Bj的时刻到当前时刻的时间间隔；如果按照上述步骤更新后的Bj大于令牌桶最大容量(即PBR*BSD)，则将Bj设置为令牌桶的最大容量。
当UE收到指示新传的上行授权资源(UL grant)时，UE按照如下步骤进行逻辑信道优先级处理：
1：对于所有Bj>0的逻辑信道，按照优先级从高到低的顺序分配资源，每个逻辑信道分配的资源只能满足PBR的要求，即根据逻辑信道对应的PBR令牌桶中的令牌数为该逻辑信道分配资源。当某个逻辑信道的PBR设置为无穷大时，只有当这个逻辑信道的资源得到满足后，才会考虑比它优先级低的逻辑信道。
2：将Bj减去逻辑信道j在S1里复用到MAC PDU的所有MAC SDU的大小。
3：如果执行完S1和S2之后还有剩余的上行资源，则不管Bj的大小，把剩余的资源按照逻辑信道优先级从高到低的顺序依次分配给各个逻辑信道。只有当高优先级的逻辑信道的数据都发送完毕且UL grant还未耗尽的情况下，低优先级的逻辑信道才能得到服务。即此时UE最大化高优先级的逻辑信道的数据传输。
在空口能力受限时，逻辑信道中的数据传输速率取决于空口速率，因此逻辑信道中的数据传输速率也相应受限。数据在逻辑信道的缓存时延指的是数据从缓存到逻辑信道直至从逻辑信道完成传输这一过程的时长，当逻辑信道中的数据传输速率受限时，也会导致数据在逻辑信道的缓存 时延增加。
为了控制数据在逻辑信道的缓存时延，可以为逻辑信道设置时延预算值(delay budget value)，以实现缓存时延的动态调整，从而达到时延控制的目的。
可选地，当逻辑信道被配置了时延预算值时，可以基于时延预算值控制数据在逻辑信道的缓存时延。
可选地，当逻辑信道未被配置时延预算值时，不保证数据在逻辑信道的缓存时延。
可选地，时延预算值由网络设备为终端设备配置。
当逻辑信道的时延预算结果满足预设条件，终端设备调整逻辑信道的PBR。
可选地，时延预算结果满足预设条件包括以下至少一种：
数据在逻辑信道的缓存时延不满足时延预算，实际速率和/或缓存数据量满足以下至少一项：实际速率小于或等于当前PBR，且缓存数据量大于或等于当前PBR与第一时长之积；缓存数据量大于或等于实际速率与时延预算值之积；缓存数据量大于或等于实际速率、时延预算值和第一阈值之积；
数据在逻辑信道的缓存时延满足时延预算，实际速率和/或缓存数据量满足以下至少一项：实际速率大于所述当前PBR；缓存数据量小于当前PBR与第一时长之积；缓存数据量小于实际速率与时延预算值之积；缓存数据量小于实际速率、时延预算值和第一阈值之积。
数据在逻辑信道的缓存时延可能满足时延预算，也可能不满足时延预算。当数据在逻辑信道的缓存时延满足时延预算时，表示数据在逻辑信道的缓存时延较小，此时可以不对逻辑信道的PBR进行调整，也可以将逻辑信道的PBR调小，从而将更多的空口资源分配给其他对时延预算要求较高的逻辑信道。
当数据在逻辑信道的缓存时延不满足时延预算时，表示数据在逻辑信道的缓存时延较大，此时可以将逻辑信道的PBR调大，从而使得该逻辑信道能够被分配更多的资源，降低数据在该逻辑信道的缓存时延。
首先介绍确定逻辑信道的时延预算结果的方案。
如图4所示，首先确定逻辑信道配置了参数时延预算值，然后判断计时器是否达到第一时长。
可选地，第一时长为网络设备配置的时长，第一时长为该计时器的时长。
可选地，PBR根据第一时长周期性调整。
在计时器达到第一时长后，获取逻辑信道的时延预算结果。
可选地，获取逻辑信道在第一时长内的数据传输的实际速率和/或缓存数据量，然后根据实际速率和/或缓存数据量，以及时延预算值，计算或确定时延预算结果。
实际速率为数据在第一时长内在逻辑信道的传输速率，由于逻辑信道内的数据传输速率是动态变化的，因此实际速率的获取方式有多种实现形式。
一种可能的方式是，获取第一时长内在逻辑信道传输的数据量，然后根据第一时长内在逻辑信道传输的数据量和第一时长，确定实际速率，即v＝L/t，v为实际速率，L为第一时长内在逻辑信道传输的数据量，t为第一时长。
一种可能的实现方式是，通过滑窗平均值或滤波平均值确定实际速率。例如，可以获取第一时长内的N个时刻在逻辑信道的数据传输速率，然后对这N个数据传输速率取平均值，得到实际速率。例如，可以获取第一时长内的M个时段内逻辑信道的数据传输速率，然后对这M个数据传输速率取平均值，得到实际速率。
缓存数据量为在第一时长内新缓存到该逻辑信道的数据的大小，以第一时长为t1-t2之间的时段为例，在t1-t2时段内新缓存到该逻辑信道的数据即为缓存数据，新缓存到该逻辑信道的数据大小即为该缓存数据量。
在获取实际速率和/或缓存数据量后，可以通过如下方式确定逻辑信道的时延预算结果。
方法1.1：判断实际速率是否小于或等于当前PBR，且缓存数据量大于或等于当前PBR与第 一时长之积。
若是，则确定时延预算结果为数据在逻辑信道的缓存时延不满足时延预算。
和/或，若否，即实际速率大于当前PBR，或缓存数据量小于当前PBR与第一时长之积，则确定时延预算结果为数据在逻辑信道的缓存时延满足时延预算。
方法1.2：判断缓存数据量是否大于或等于实际速率与时延预算值之积，若是，则确定时延预算结果为数据在逻辑信道的缓存时延不满足时延预算；和/或，若否，则确定时延预算结果为数据在逻辑信道的缓存时延满足时延预算。
方法1.3：判断缓存数据量是否大于或等于实际速率、时延预算值和第一阈值之积，若是，则确定时延预算结果为数据在逻辑信道的缓存时延不满足时延预算；和/或，若否，则确定时延预算结果为数据在逻辑信道的缓存时延满足时延预算。
可选地，第一阈值为大于或等于0的值，例如可以为80％、90％、等等。
可选地，第一阈值可以由网络设备为终端设备配置，也可以由终端设备配置。
在获取时延预算结果后，调整逻辑信道的PBR为目标PBR和/或调整逻辑信道的优先级为目标优先级。
在获取逻辑信道的时延预算结果后，可以根据时延预算结果调整PBR为目标PBR。
在获取逻辑信道的时延预算结果后，可以根据时延预算结果调整逻辑信道的优先级为目标优先级。
可选地，当时延预算结果为数据在逻辑信道的缓存时延不满足时延预算，目标优先级高于或等于当前优先级，即在不满足时延预算时，调大逻辑信道的优先级，以使得逻辑信道的处理级别更高，提高数据在该逻辑信道的响应速度，进而降低数据在该逻辑信道的缓存时延。
可选地，当数据在逻辑信道的缓存时延不满足时延预算时，可以通过如下实施方式调整逻辑信道的优先级：
实施方式3.1:若当前优先级为最高优先级，目标优先级为当前优先级。
实时方式3.2：若当前优先级不为最高优先级，目标优先级为当前优先级递增。
本实施例中，逻辑信道的优先级可以划分为多个，若当前优先级已为最高优先级，则逻辑信道的优先级不能再提高，可以目标优先级为当前优先级。若当前优先级不为最高优先级，则逻辑信道的优先级可以提升一级或多级，目标优先级为当前优先级递增。通过优先级增加的方式，实现对不满足延时预算的逻辑信道的及时调整，以确保数据传输的正常。
可选地，当时延预算结果为数据在逻辑信道的缓存时延满足时延预算，目标优先级低于当前优先级，即在满足时延预算时，调低逻辑信道的优先级，以降低逻辑信道的处理级别，为更高的逻辑信道的处理作出让步，进而提升逻辑信道整体的数据缓存效率。
可选地，当数据在逻辑信道的缓存时延满足时延预算时，可以通过如下实施方式调整逻辑信道的优先级：
实施方式4.1，若当前优先级已经为初始配置优先级时，所述目标优先级为所述当前优先级。
实施方式4.2，若当前优先级不为初始配置优先级时，所述目标优先级为所述当前优先级递减。
可选地，初始配置优先级可以为逻辑信道对应的最小优先级。当然，在实际应用中，初始配置优先级也可以为逻辑信道的任意优先级，初始配置优先级之后，逻辑信道的处理优先级的最小优先级即可以为该逻辑信道的初始配置优先级，因此，调整后的目标优先级不能低于初始配置优先级。
本实施例中，逻辑信道的优先级可以划分为多个，若当前优先级已为初始配置的优先级，不能再对优先级进行减少，以免影响数据传输，因此，可以目标优先级为当前优先级。若当前优先级不为初始配置优先级，可以将当前优先级降级，以获得目标优先级。实现对满足时延预算的逻辑信道的及时调整，以确保数据的正常传输。
可选地，当时延预算结果为数据在逻辑信道的缓存时延不满足时延预算时，目标PBR大于或等于当前PBR，即在不满足时延预算时，调大逻辑信道的PBR，以使得逻辑信道获取更多的空口资源，提高数据在该逻辑信道的传输速率，进而降低数据在该逻辑信道的缓存时延。
可选地，当数据在逻辑信道的缓存时延不满足时延预算时，可以通过如下方式调整逻辑信道的PBR：
方法2.1：若当前PBR小于缓存数据量与时延预算值之商，则将当前PBR调整为缓存数据量与时延预算值之商，即目标PBR＝缓存数据量/时延预算值；和/或，若当前PBR大于或等于缓存数据量与时延预算值之商，则不对当前PBR进行调整，即目标PBR＝当前PBR。
方法2.2：若当前PBR小于PBR门限值，将当前PBR与第二阈值相乘，得到目标PBR，其中第二阈值a为大于或等于1的正数，即目标PBR＝a*当前PBR。和/或，若当前PBR大于或等于PBR门限值，则不对当前PBR进行调整，即目标PBR＝当前PBR。
可选地，第二阈值a可以为网络设备配置的数值，也可以为终端设备配置的数值。
可选地，PBR门限值为缓存数据量与时延预算值之商。
可选地，PBR门限值可以为第三阈值。
可选地，第三阈值可以为网络设备配置的数值，也可以为终端设备配置的数值。
综上所述，当数据在逻辑信道的缓存时延不满足时延预算时，目标PBR为当前PBR、缓存数据量与时延预算值之商、当前优先比特率与第二阈值a之积中的至少一项，第二阈值a为大于或等于1的正数。
可选地，当时延预算结果为数据在逻辑信道的缓存时延满足时延预算时，目标PBR小于当前PBR，即在满足时延预算时，调小逻辑信道的PBR，以使得逻辑信道获取的空口资源减少，进而使得有限的空口资源能够更多的分配给不满足时延预算的逻辑信道。
可选地，当数据在逻辑信道的缓存时延满足时延预算时，可以通过如下方式调整逻辑信道的PBR：
方法2.3：将逻辑信道的PBR恢复为初始PBR。
方法2.4：若当前PBR小于或等于初始PBR，不对当前PBR进行调整，即目标PBR＝当前PBR。和/或，若当前PBR大于PBR，将当前PBR与第二阈值相乘，得到目标PBR，其中第二阈值b为小于1的正数，即目标PBR＝b*当前PBR。
可选地，第二阈值b可以为网络设备配置的数值，也可以为终端设备配置的数值。
综上所述，当数据在逻辑信道的缓存时延满足时延预算时，目标PBR为当前PBR、初始PBR、当前优先比特率与第二阈值b之积中的至少一项，第二阈值b为小于1的正数。
在上述实施例中，介绍了如何获取时延预算结果，以及如何根据时延预算结果调整逻辑信道的PBR。可选地，根据上述实施例中的方法1.1、方法1.2、方法1.3中的至少一项，可以获取时延预算结果。当时延预算结果为数据在逻辑信道的缓存时延不满足时延预算时，可以根据上述实施例中的方法2.1和方法2.2中的至少一项来调整逻辑信道的PBR；当时延预算结果为数据在逻辑信道的缓存时延满足时延预算时，可以根据上述实施例中的方法2.3和方法2.4中的至少一项来调整逻辑信道的PBR。下面将结合附图进行举例介绍。
图6为本申请实施例提供的PBR调整示意图一，本实施例以执行主体为终端设备(如UE)为例进行示例说明，实际实现中，也可能由网络设备来执行，如图6所示，包括：
S61，确定逻辑信道配置了时延预算值。
当逻辑信道被配置了时延预算值时，进行该逻辑信道的缓存时延的控制。
S62，判断计时器是否达到第一时长，若是，则执行S63，和/或，若否，则在经过一定的时长后继续执行S62。
本申请实施例中，可以通过设置计时器进行周期性的检测，计时器的时长可以由网络设备来配置。当计时器达到第一时长后，执行S63，和/或，当计时器未达到第一时长，则继续检测计时 器运行时长。
S63，判断是否满足实际速率小于或等于当前PBR，且缓存数据量大于或等于当前PBR与第一时长之积。若是，则执行S64，和/或，若否，则执行S66。
S63为一种确定逻辑信道的时延预算结果的实现方式，即根据上述实施例中的方法1.1判断数据在逻辑信道的缓存时延是否满足时延预算。当数据在逻辑信道的缓存时延不满足时延预算时，执行S64，和/或，当数据在逻辑信道的缓存时延满足时延预算时，执行S66。
S64，判断当前PBR是否小于缓存数据量与时延预算值之商，若是，则执行S65，和/或，若否，则执行S67。
当数据在逻辑信道的缓存时延不满足时延预算时，根据上述实施例中的方法2.1调整逻辑信道的PBR。可选地，判断当前PBR是否小于缓存数据量与时延预算值之商，若是，则执行S65，和/或，若否，则执行S67。
S65，将目标PBR调整为缓存数据量与时延预算值之商。
在数据在逻辑信道的缓存时延不满足时延预算，且当前PBR小于缓存数据量与时延预算值之商时，将目标PBR调整为缓存数据量与时延预算值之商。在数据在逻辑信道的缓存时延不满足时延预算，且当前PBR大于或等于缓存数据量与时延预算值之商时，目标PBR＝当前PBR。
S66，将目标PBR调整为初始PBR。
在数据在逻辑信道的缓存时延满足时延预算时，将目标PBR调整为初始PBR。
S67，将目标PBR确定为当前PBR。
在数据在逻辑信道的缓存时延不满足时延预算，且当前PBR大于或等于缓存数据量与时延预算值之商时，由于此时当前PBR已经比较大，不适合再调大，因此此时不对逻辑信道的PBR进行调整，逻辑信道的目标PBR等于当前PBR。
S68，保存目标PBR，并用于LCP过程，执行S62。
在确定目标PBR后，可以根据目标PBR执行LCP过程，实现数据在逻辑信道的缓存时延的动态调整。
图7为本申请实施例提供的PBR调整示意图二，本实施例以执行主体为终端设备(如UE)为例进行示例说明，实际实现中，也可能由网络设备来执行，如图7所示，包括：
S71，确定逻辑信道配置了时延预算值。
当逻辑信道被配置了时延预算值时，进行该逻辑信道的缓存时延的控制。
S72，判断计时器是否达到第一时长，若是，则执行S73，和/或，若否，则在经过一定的时长后继续执行S72。
本申请实施例中，可以通过设置计时器进行周期性的检测，计时器的时长可以由网络设备来配置。当计时器达到第一时长后，执行S73，当计时器未达到第一时长，则继续检测计时器运行时长。
S73，判断缓存数据量是否大于或等于实际速率与时延预算值之积，若是，则执行S74，和/或，若否，则执行S76。
S73为一种确定逻辑信道的时延预算结果的实现方式，即根据上述实施例中的方法1.2判断数据在逻辑信道的缓存时延是否满足时延预算。当数据在逻辑信道的缓存时延不满足时延预算时，执行S74，和/或，当数据在逻辑信道的缓存时延满足时延预算时，执行S76。
S74，判断当前PBR是否小于PBRmax，若是，则执行S75，和/或，若否，则执行S77。
当数据在逻辑信道的缓存时延不满足时延预算时，根据上述实施例中的方法2.2调整逻辑信道的PBR。可选地，判断当前PBR是否小于PBR门限值(即PBRmax)，若是，则执行S75，和/或，若否，则执行S77。
S75，将目标PBR调整为当前PBR与a的乘积。
当数据在逻辑信道的缓存时延不满足时延预算，且当前PBR小于PBRmax时，目标PBR＝当前 PBR*a，a为第二阈值，且a为大于或等于1的正数。
S76，将目标PBR调整为初始PBR。
当数据在逻辑信道的缓存时延满足时延预算时，根据上述实施例中的方法2.3调整逻辑信道的PBR。可选地，将目标PBR恢复为初始PBR即可。
S77，将目标PBR确定为当前PBR。
当数据在逻辑信道的缓存时延不满足时延预算，且当前PBR大于或等于PBRmax时，目标PBR＝当前PBR，即不对逻辑信道的PBR进行调整。
S78，保存目标PBR，并用于LCP过程，执行S72。
在确定目标PBR后，可以根据目标PBR执行LCP过程，实现数据在逻辑信道的缓存时延的动态调整。
图8为本申请实施例提供的PBR调整示意图三，本实施例以执行主体为终端设备(如UE)为例进行示例说明，实际实现中，也可能由网络设备来执行，如图8所示，包括：
S81，确定逻辑信道配置了时延预算值。
当逻辑信道被配置了时延预算值时，进行该逻辑信道的缓存时延的控制。
S82，判断计时器是否达到第一时长，若是，则执行S83，和/或，若否，则在经过一定的时长后继续执行S82。
本申请实施例中，可以通过设置计时器进行周期性的检测，计时器的时长可以由网络设备来配置。当计时器达到第一时长后，执行S83，和/或，当计时器未达到第一时长，则继续检测计时器运行时长。
S83，判断缓存数据量是否大于或等于实际速率与时延预算值之积，若是，则执行S84，和/或，若否，则执行S86。
S83为一种确定逻辑信道的时延预算结果的实现方式，即根据上述实施例中的方法1.2判断数据在逻辑信道的缓存时延是否满足时延预算。当数据在逻辑信道的缓存时延不满足时延预算时，执行S84，和/或，当数据在逻辑信道的缓存时延满足时延预算时，执行S86。
S84，判断当前PBR是否小于PBRmax，若是，则执行S85，和/或，若否，则执行S88。
当数据在逻辑信道的缓存时延不满足时延预算时，根据上述实施例中的方法2.2调整逻辑信道的PBR。可选地，判断当前PBR是否小于PBR门限值(即PBRmax)，若是，则执行S85，和/或，若否，则执行S88。
S85，将目标PBR调整为当前PBR与a的乘积。
当数据在逻辑信道的缓存时延不满足时延预算，且当前PBR小于PBRmax时，目标PBR＝当前PBR*a，a为第二阈值，且a为大于或等于1的正数。
S86，判断当前PBR是否大于初始PBR，若是，则执行S87，和/或，若否，则执行S88。
当数据在逻辑信道的缓存时延满足时延预算时，根据上述实施例中的方法2.3调整逻辑信道的PBR。可选地，判断当前PBR是否大于初始PBR，若是，则执行S87，和/或，若否，则执行S88。
S87，将目标PBR调整为当前PBR与b的乘积。
当数据在逻辑信道的缓存时延满足时延预算，且当前PBR大于初始PBR时，将当前PBR与第二阈值相乘，得到目标PBR，其中第二阈值b为小于1的正数，即目标PBR＝b*当前PBR。
S88，将目标PBR确定为当前PBR。
当数据在逻辑信道的缓存时延不满足时延预算，且当前PBR大于或等于PBRmax时，目标PBR＝当前PBR，即不对逻辑信道的PBR进行调整。
S89，保存目标PBR，并用于LCP过程，执行S82。
在确定目标PBR后，可以根据目标PBR执行LCP过程，实现数据在逻辑信道的缓存时延的动态调整。
图6至图8介绍了几种逻辑信道的缓存时延的控制方案，可以理解的是，根据上述实施例中 的方法1.1、方法1.2和方法1.3中的至少一项，来确定逻辑信道的时延预算结果；当数据在逻辑信道的缓存时延不满足时延预算时，可以根据上述实施例中的方法2.1或方法2.2来调整逻辑信道的PBR；当数据在逻辑信道的缓存时延满足时延预算时，可以根据上述实施例中的方法2.3或方法2.4来调整逻辑信道的PBR。即，上述实施例中的方法1.1、方法1.2和方法1.3，以及方法2.1、方法2.2、方法2.3和方法2.4可以任意组合，实现逻辑信道的缓存时延的控制。
本申请提供的处理方法，首先根据时延预算值确定逻辑信道的时延预算结果，该时延预算结果用于指示数据在逻辑信道的缓存时延是否满足时延预算。然后，根据时延预算结果调整逻辑信道的PBR，调整逻辑信道的PBR后，能够改变逻辑信道获得的空口资源，从而改变数据在逻辑信道的传输速率，进而改变数据在逻辑信道的缓存时延。本申请的方案，实现了通过对逻辑信道的PBR的动态调整来控制数据在逻辑信道的缓存时延。
图9为本申请实施例提供的处理装置的结构示意图一，如图9所示，该处理装置90包括：
处理模块91，用于根据时延预算值计算或确定逻辑信道的时延预算结果；
调整模块92，用于根据所述时延预算结果调整所述逻辑信道的优先比特率和/或优先级。
可选地，所述处理模块91具体用于：
根据所述逻辑信道在第一时长内的数据传输的实际速率和/或缓存数据量，以及所述时延预算值，计算或确定所述时延预算结果。
可选地，所述时延预算结果包括以下至少一种：
数据在所述逻辑信道的缓存时延不满足时延预算，所述实际速率和/或所述缓存数据量满足以下至少一项：所述实际速率小于或等于当前优先比特率，且所述缓存数据量大于或等于所述当前优先比特率与所述第一时长之积；所述缓存数据量大于或等于所述实际速率与所述时延预算值之积；所述缓存数据量大于或等于所述实际速率、所述时延预算值和第一阈值之积；
数据在所述逻辑信道的缓存时延满足所述时延预算，所述实际速率和/或所述缓存数据量满足以下至少一项：所述实际速率大于所述当前优先比特率；所述缓存数据量小于所述当前优先比特率与所述第一时长之积；所述缓存数据量小于所述实际速率与所述时延预算值之积；所述缓存数据量小于所述实际速率、所述时延预算值和所述第一阈值之积。
可选地，所述调整模块92具体用于：
根据所述时延预算结果调整所述逻辑信道的优先比特率为目标优先比特率和/或根据所述时延预算结果调整所述逻辑信道的优先级为目标优先级。
可选地，目标优先比特率为以下至少一项：
当前优先比特率；
初始优先比特率；
所述缓存数据量与所述时延预算值之商；
所述当前优先比特率与第二阈值之积，所述第二阈值为正数。
可选地，所述数据在所述逻辑信道的缓存时延不满足所述时延预算，所述目标优先比特率大于或等于当前优先比特率；和/或，所述数据在所述逻辑信道的缓存时延满足所述时延预算，所述目标优先比特率小于或等于当前优先比特率；和/或，所述数据在所述逻辑信道的缓存时延满足所述时延预算，所述目标优先级低于或等于当前优先级；和/或，所述数据在所述逻辑信道的缓存时延不满足所述时延预算，所述目标优先级高于或等于当前优先级。
可选地，所述数据在所述逻辑信道的缓存时延不满足所述时延预算，包括以下至少一项：
所述目标优先比特率为以下至少一项：当前优先比特率、所述缓存数据量与所述时延预算值之商、所述当前优先比特率与所述第二阈值之积，所述第二阈值为大于或等于1的正数；
当所述当前优先比特率小于所述缓存数据量与所述时延预算值之商时，所述目标优先比特率为所述缓存数据量与所述时延预算值之商；
当所述当前优先比特率大于或等于所述缓存数据量与所述时延预算值之商时，所述目标优先 比特率为所述当前优先比特率。
当所述当前优先比特率小于优先比特率门限值时，所述目标优先比特率为所述当前优先比特率与所述第二阈值之积；
当所述当前优先比特率大于或等于所述优先比特率门限值时，所述目标优先比特率为所述当前优先比特率；
当所述当前优先级已经为最高优先级时，所述目标优先级为所述当前优先级；
当所述当前优先级不为最高优先级时，所述目标优先级为所述当前优先级递增。
可选地，所述优先比特率门限值为所述缓存数据量与所述时延预算值之商；或者，所述优先比特率门限值为第三阈值。
可选地，所述数据在所述逻辑信道的缓存时延满足所述时延预算，包括以下至少一项：
所述目标优先比特率为以下至少一项：所述当前优先比特率、初始优先比特率、所述当前优先比特率与所述第二阈值之积，所述第二阈值为小于或等于1的正数。
当所述当前优先比特率小于或等于所述初始优先比特率时，所述目标优先比特率为所述当前优先比特率；当所述当前优先比特率大于或等于所述初始优先比特率时，所述目标优先比特率为当前优先比特率与第三阈值之积；当所述当前优先级已经为初始配置优先级时，所述目标优先级为所述当前优先级；当所述当前优先级不为初始配置优先级时，所述目标优先级为所述当前优先级递减。
本申请实施例提供的处理装置可以执行上述方法实施例所示的技术方案，其实现原理以及有益效果类似，此处不再进行赘述。
图10为本申请实施例提供的处理装置的结构示意图二，如图10所示，该处理装置100包括：
处理模块101，用于响应于逻辑信道的时延预算结果满足预设条件，调整所述逻辑信道的优先比特率和/或优先级。
可选地，所述时延预算结果满足预设条件包括以下至少一种：
数据在所述逻辑信道的缓存时延不满足时延预算，所述逻辑信道在第一时长内的数据传输的实际速率和/或缓存数据量满足以下至少一项：所述实际速率小于或等于当前优先比特率，且所述缓存数据量大于或等于所述当前优先比特率与所述第一时长之积、所述缓存数据量大于或等于所述实际速率与所述时延预算值之积、所述缓存数据量大于或等于所述实际速率、所述时延预算值和第一阈值之积；
数据在所述逻辑信道的缓存时延满足所述时延预算，所述实际速率和/或所述缓存数据量满足以下至少一项：所述实际速率大于所述当前优先比特率、所述缓存数据量小于所述当前优先比特率与所述第一时长之积、所述缓存数据量小于所述实际速率与所述时延预算值之积、所述缓存数据量小于所述实际速率、所述时延预算值和所述第一阈值之积。
可选地，所述处理模块101具体用于：
调整所述逻辑信道的优先比特率为目标优先比特率和/或调整所述逻辑信道的优先级为目标优先级。
可选地，目标优先比特率为以下至少一项：当前优先比特率；初始优先比特率；所述缓存数据量与所述时延预算值之商；所述当前优先比特率与第二阈值之积，所述第二阈值为正数。
可选地，所述数据在所述逻辑信道的缓存时延不满足所述时延预算，所述目标优先比特率大于或等于当前优先比特率；和/或，所述数据在所述逻辑信道的缓存时延满足所述时延预算，所述目标优先比特率小于或等于当前优先比特率；和/或，所述数据在所述逻辑信道的缓存时延满足所述时延预算，所述目标优先级低于或等于当前优先级；和/或，所述数据在所述逻辑信道的缓存时延不满足所述时延预算，所述目标优先级高于或等于当前优先级。
可选地，所述数据在所述逻辑信道的缓存时延不满足所述时延预算，包括以下至少一项：
所述目标优先比特率为以下至少一项：当前优先比特率、所述缓存数据量与所述时延预算值 之商、所述当前优先比特率与所述第二阈值之积，所述第二阈值为大于或等于1的正数；当所述当前优先比特率小于所述缓存数据量与所述时延预算值之商时，所述目标优先比特率为所述缓存数据量与所述时延预算值之商；当所述当前优先比特率大于或等于所述缓存数据量与所述时延预算值之商时，所述目标优先比特率为所述当前优先比特率。
当所述当前优先比特率小于优先比特率门限值时，所述目标优先比特率为所述当前优先比特率与所述第二阈值之积；当所述当前优先比特率大于或等于所述优先比特率门限值时，所述目标优先比特率为所述当前优先比特率；当所述当前优先级已经为最高优先级时，所述目标优先级为所述当前优先级；当所述当前优先级不为最高优先级时，所述目标优先级为所述当前优先级递增。
可选地，所述优先比特率门限值为所述缓存数据量与所述时延预算值之商；或者，所述优先比特率门限值为第三阈值。
可选地，所述数据在所述逻辑信道的缓存时延满足所述时延预算，包括以下至少一项：
所述目标优先比特率为以下至少一项：所述当前优先比特率、初始优先比特率、所述当前优先比特率与所述第二阈值之积，所述第二阈值为小于或等于1的正数。
当所述当前优先比特率小于或等于所述初始优先比特率时，所述目标优先比特率为所述当前优先比特率；当所述当前优先比特率大于或等于所述初始优先比特率时，所述目标优先比特率为当前优先比特率与第三阈值之积；当所述当前优先级已经为初始配置优先级时，所述目标优先级为所述当前优先级；当所述当前优先级不为初始配置优先级时，所述目标优先级为所述当前优先级递减。
本申请实施例提供的处理装置可以执行上述方法实施例所示的技术方案，其实现原理以及有益效果类似，此处不再进行赘述。
图11为本申请实施例提供的通信设备的结构示意图。如图11所示，本实施例所述的通信设备1100可以是前述方法实施例中提到的终端设备(或者可用于终端设备的部件)或者网络设备(或者可用于网络设备的部件)。通信设备1100可用于实现上述方法实施例中描述的对应于终端设备或者网络设备的方法，具体参见上述方法实施例中的说明。
通信设备1100可以包括一个或多个处理器1101，该处理器1101也可以称为处理单元，可以实现一定的控制或者处理功能。处理器1101可以是通用处理器或者专用处理器等。例如可以是基带处理器、或中央处理器。基带处理器可以用于对通信协议以及通信数据进行处理，中央处理器可以用于对通信设备进行控制，执行软件程序，处理软件程序的数据。
可选地，处理器1101也可以存有指令1103或者数据(例如中间数据)。可选地，指令1103可以被处理器1101运行，使得通信设备1100执行上述方法实施例中描述的对应于终端设备或者网络设备的方法。
可选地，通信设备1100可以包括电路，该电路可以实现前述方法实施例中发送或接收或者通信的功能。
可选地，通信设备1100中可以包括一个或多个存储器1102，其上可以存有指令1104，该指令可在处理器1101上被运行，使得通信设备1100执行上述方法实施例中描述的方法。
可选地，存储器1102中也可以是存储有数据。处理器1101和存储器1102可以单独设置，也可以集成在一起。
可选地，通信设备1100还可以包括收发器1105和/或天线1106。处理器1101可以称为处理单元，对通信设备1100(终端设备或核心网设备或者无线接入网设备)进行控制。收发器1105可以称为收发单元、收发机、收发电路、或者收发器等，用于实现通信设备1100的收发功能。
可选地，处理器1101和收发器1105的具体实现过程可以参见上述各实施例的相关描述，此处不再赘述。
可选地，处理器1101和收发器1105的具体实现过程可以参见上述各实施例的相关描述，此处不再赘述。
本申请中描述的处理器1101和收发器1105可实现在IC(Integrated Circuit，集成电路)、模拟集成电路、RFIC(Radio Frequency Integrated Circuit，射频集成电路)、混合信号集成电路、ASIC(Application Specific Integrated Circuit，专用集成电路)、PCB(Printed Circuit Board，印刷电路板)、电子设备等上。该处理器1101和收发器1105也可以用各种集成电路工艺技术来制造，例如CMOS(Complementary Metal Oxide Semiconductor，互补金属氧化物半导体)、NMOS(N Metal-Oxide-Semiconductor，N型金属氧化物半导体)、PMOS(Positive channel Metal Oxide Semiconductor，P型金属氧化物半导体)、BJT(Bipolar Junction Transistor，双极结型晶体管)、双极CMOS(BiCMOS)、硅锗(SiGe)、砷化镓(GaAs)等。
本申请中，通信设备可以为终端设备，也可以为网络设备(如基站)，具体需要根据上下文来加以确定，另外，终端设备可以以各种形式来实施。例如，本申请中描述的终端设备可以包括诸如手机、平板电脑、笔记本电脑、掌上电脑、个人数字助理(Personal Digital Assistant，PDA)、便捷式媒体播放器(Portable Media Player，PMP)、导航装置、可穿戴设备、智能手环、计步器等移动终端，以及诸如数字TV、台式计算机等固定终端。
虽然在以上的实施例描述中，通信设备以终端设备或者网络设备为例来描述，但本申请中描述的通信设备的范围并不限于上述终端设备或网络设备，而且通信设备的结构可以不受图11的限制。通信设备可以是独立的设备或者可以是较大设备的一部分。
图12为本申请提供的一种控制器1200的硬件结构示意图，该控制器1200可以包括：存储器1201和处理器1202，存储器1201用于存储程序指令，处理器1202用于调用存储器1201中的程序指令执行上述方法实施例中所执行的步骤，其实现原理及有益效果类似，此处不再进行赘述。
可选地，上述控制器还包括通信接口1203，该通信接口1203可以通过总线1204与处理器1202连接，处理器1202可以控制通信接口1203来实现控制器1200的接收和发送的功能。
图13为本申请提供的一种网络节点1300的硬件结构示意图，该网络节点1300可以包括：存储器1301和处理器1302，存储器1301用于存储程序指令，处理器1302用于调用存储器1301中的程序指令执行上述方法实施例中所执行的步骤，其实现原理及有益效果类似，此处不再进行赘述。可选地，上述网络节点1300还包括通信接口1303，该通信接口1303可以通过总线1304与处理器1302连接，处理器1302可以控制通信接口1303来实现网络节点1300的接收和发送的功能。上述以软件功能模块的形式实现的集成的模块，可以存储在一个计算机可读取存储介质中。上述软件功能模块存储在一个存储介质中，包括若干指令用以使得一台计算机设备(可以是个人计算机，服务器，或者网络设备等)或处理器(英文：processor)执行本申请各个实施例方法的部分步骤。
本申请实施例还提供一种通信系统，包括：如上任一方法实施例中的终端设备；以及，如上任一方法实施例中的网络设备。
本申请实施例还提供一种通信设备，通信设备包括：存储器、处理器；其中，存储器上存储有计算机程序，计算机程序被处理器执行时实现上述任一实施例中的处理方法的步骤。
本申请实施例还提供一种终端设备，终端设备包括：存储器、处理器；其中，存储器上存储有计算机程序，计算机程序被处理器执行时实现上述任一实施例中的处理方法的步骤。
本申请实施例还提供一种网络设备，网络设备包括：存储器、处理器；其中，存储器上存储有计算机程序，计算机程序被处理器执行时实现上述任一实施例中的处理方法的步骤。
本申请实施例还提供一种计算机可读存储介质，存储介质上存储有计算机程序，计算机程序被处理器执行时实现上述任一实施例中的处理方法的步骤。
在本申请实施例提供的通信设备、终端设备、网络设备和计算机可读存储介质的实施例中，可以包含任一上述处理方法实施例的全部技术特征，说明书拓展和解释内容与上述方法的各实施例基本相同，在此不做再赘述。
本申请实施例还提供一种计算机程序产品，计算机程序产品包括计算机程序代码，当计算机 程序代码在计算机上运行时，使得计算机执行如上各种可能的实施方式中的方法。
本申请实施例还提供一种芯片，包括存储器和处理器，存储器用于存储计算机程序，处理器用于从存储器中调用并运行计算机程序，使得安装有芯片的设备执行如上各种可能的实施方式中的方法。
可以理解，上述场景仅是作为示例，并不构成对于本申请实施例提供的技术方案的应用场景的限定，本申请的技术方案还可应用于其他场景。例如，本领域普通技术人员可知，随着系统架构的演变和新业务场景的出现，本申请实施例提供的技术方案对于类似的技术问题，同样适用。
上述本申请实施例序号仅仅为了描述，不代表实施例的优劣。
本申请实施例方法中的步骤可以根据实际需要进行顺序调整、合并和删减。
本申请实施例设备中的单元可以根据实际需要进行合并、划分和删减。
在本申请中，对于相同或相似的术语概念、技术方案和/或应用场景描述，一般只在第一次出现时进行详细描述，后面再重复出现时，为了简洁，一般未再重复阐述，在理解本申请技术方案等内容时，对于在后未详细描述的相同或相似的术语概念、技术方案和/或应用场景描述等，可以参考其之前的相关详细描述。
在本申请中，对各个实施例的描述都各有侧重，某个实施例中没有详述或记载的部分，可以参见其它实施例的相关描述。
本申请技术方案的各技术特征可以进行任意的组合，为使描述简洁，未对上述实施例中的各个技术特征所有可能的组合都进行描述，然而，只要这些技术特征的组合不存在矛盾，都应当认为是本申请记载的范围。
通过以上的实施方式的描述，本领域的技术人员可以清楚地了解到上述实施例方法可借助软件加必需的通用硬件平台的方式来实现，当然也可以通过硬件，但很多情况下前者是更佳的实施方式。基于这样的理解，本申请的技术方案本质上或者说对现有技术做出贡献的部分可以以软件产品的形式体现出来，该计算机软件产品存储在如上的一个存储介质(如ROM/RAM、磁碟、光盘)中，包括若干指令用以使得一台终端设备(可以是手机，计算机，服务器，被控终端，或者网络设备等)执行本申请每个实施例的方法。
在上述实施例中，可以全部或部分地通过软件、硬件、固件或者其任意组合来实现。当使用软件实现时，可以全部或部分地以计算机程序产品的形式实现。计算机程序产品包括一个或多个计算机指令。在计算机上加载和执行计算机程序指令时，全部或部分地产生按照本申请实施例的流程或功能。计算机可以是通用计算机、专用计算机、计算机网络，或者其他可编程装置。计算机指令可以存储在计算机可读存储介质中，或者从一个计算机可读存储介质向另一个计算机可读存储介质传输，例如，计算机指令可以从一个网站站点、计算机、服务器或数据中心通过有线(例如同轴电缆、光纤、数字用户线)或无线(例如红外、无线、微波等)方式向另一个网站站点、计算机、服务器或数据中心进行传输。计算机可读存储介质可以是计算机能够存取的任何可用介质或者是包含一个或多个可用介质集成的服务器、数据中心等数据存储设备。可用介质可以是磁性介质，(例如，软盘、存储盘、磁带)、光介质(例如，DVD)，或者半导体介质(例如固态存储盘Solid State Disk(SSD))等。
以上仅为本申请的优选实施例，并非因此限制本申请的专利范围，凡是利用本申请说明书及附图内容所作的等效结构或等效流程变换，或直接或间接运用在其他相关的技术领域，均同理包括在本申请的专利保护范围内。

Claims (19)

  1. 一种处理方法，其中，包括以下步骤：
    S1、根据时延预算值计算或确定逻辑信道的时延预算结果；
    S2、根据所述时延预算结果调整所述逻辑信道的优先比特率和/或优先级。
  2. 根据权利要求1所述的方法，其中，所述S1步骤包括：
    根据所述逻辑信道在第一时长内的数据传输的实际速率和/或缓存数据量，以及所述时延预算值，计算或确定所述时延预算结果。
  3. 根据权利要求2所述的方法，其中，所述时延预算结果包括以下至少一种：
    数据在所述逻辑信道的缓存时延不满足时延预算，所述实际速率和/或所述缓存数据量满足以下至少一项：所述实际速率小于或等于当前优先比特率，且所述缓存数据量大于或等于所述当前优先比特率与所述第一时长之积；所述缓存数据量大于或等于所述实际速率与所述时延预算值之积；所述缓存数据量大于或等于所述实际速率、所述时延预算值和第一阈值之积；
    数据在所述逻辑信道的缓存时延满足所述时延预算，所述实际速率和/或所述缓存数据量满足以下至少一项：所述实际速率大于所述当前优先比特率；所述缓存数据量小于所述当前优先比特率与所述第一时长之积；所述缓存数据量小于所述实际速率与所述时延预算值之积；所述缓存数据量小于所述实际速率、所述时延预算值和所述第一阈值之积。
  4. 根据权利要求3所述的方法，其中，所述S2步骤，包括：
    根据所述时延预算结果调整所述逻辑信道的优先比特率为目标优先比特率和/或根据所述时延预算结果调整所述逻辑信道的优先级为目标优先级。
  5. 根据权利要求4所述的方法，其中，所述目标优先比特率为以下至少一项：
    当前优先比特率；
    初始优先比特率；
    所述缓存数据量与所述时延预算值之商；
    所述当前优先比特率与第二阈值之积，所述第二阈值为正数。
  6. 根据权利要求5所述的方法，其中，所述数据在所述逻辑信道的缓存时延不满足所述时延预算，所述目标优先比特率大于或等于当前优先比特率；和/或，
    所述数据在所述逻辑信道的缓存时延满足所述时延预算，所述目标优先比特率小于或等于当前优先比特率；和/或，
    所述数据在所述逻辑信道的缓存时延满足所述时延预算，所述目标优先级低于或等于当前优先级；和/或，
    所述数据在所述逻辑信道的缓存时延不满足所述时延预算，所述目标优先级高于或等于当前优先级。
  7. 根据权利要求6所述的方法，其中，所述数据在所述逻辑信道的缓存时延不满足所述时延预算，包括以下至少一项：
    所述目标优先比特率为以下至少一项：当前优先比特率、所述缓存数据量与所述时延预算值之商、所述当前优先比特率与所述第二阈值之积，所述第二阈值为大于或等于1的正数；
    当所述当前优先比特率小于所述缓存数据量与所述时延预算值之商时，所述目标优先比特率为所述缓存数据量与所述时延预算值之商；
    当所述当前优先比特率大于或等于所述缓存数据量与所述时延预算值之商时，所述目标优先比特率为所述当前优先比特率；
    当所述当前优先比特率小于优先比特率门限值时，所述目标优先比特率为所述当前优先比特率与所述第二阈值之积；
    当所述当前优先比特率大于或等于所述优先比特率门限值时，所述目标优先比特率为所述当 前优先比特率；
    当所述当前优先级已经为最高优先级时，所述目标优先级为所述当前优先级；
    当所述当前优先级不为最高优先级时，所述目标优先级为所述当前优先级递增。
  8. 根据权利要求7所述的方法，其中，所述优先比特率门限值为所述缓存数据量与所述时延预算值之商；或者，所述优先比特率门限值为第三阈值。
  9. 根据权利要求6至8中任一项所述的方法，其中，所述数据在所述逻辑信道的缓存时延满足所述时延预算，包括以下至少一项：
    所述目标优先比特率为以下至少一项：所述当前优先比特率、初始优先比特率、所述当前优先比特率与所述第二阈值之积，所述第二阈值为小于或等于1的正数；
    当所述当前优先比特率小于或等于所述初始优先比特率时，所述目标优先比特率为所述当前优先比特率；
    当所述当前优先比特率大于或等于所述初始优先比特率时，所述目标优先比特率为所述当前优先比特率与第三阈值之积；
    当所述当前优先级已经为初始配置优先级时，所述目标优先级为所述当前优先级；
    当所述当前优先级不为初始配置优先级时，所述目标优先级为所述当前优先级递减。
  10. 一种处理方法，其中，包括以下步骤：
    S10，响应于逻辑信道的时延预算结果满足预设条件，调整所述逻辑信道的优先比特率和/或优先级。
  11. 根据权利要求10所述的方法，其中，所述时延预算结果满足预设条件包括以下至少一种：
    数据在所述逻辑信道的缓存时延不满足时延预算，所述逻辑信道在第一时长内的数据传输的实际速率和/或缓存数据量满足以下至少一项：所述实际速率小于或等于当前优先比特率，且所述缓存数据量大于或等于所述当前优先比特率与所述第一时长之积；所述缓存数据量大于或等于所述实际速率与所述时延预算值之积；所述缓存数据量大于或等于所述实际速率；所述时延预算值和第一阈值之积；
    数据在所述逻辑信道的缓存时延满足所述时延预算，所述实际速率和/或所述缓存数据量满足以下至少一项：所述实际速率大于所述当前优先比特率；所述缓存数据量小于所述当前优先比特率与所述第一时长之积；所述缓存数据量小于所述实际速率与所述时延预算值之积；所述缓存数据量小于所述实际速率、所述时延预算值和所述第一阈值之积。
  12. 根据权利要求11所述的方法，其中，所述调整所述逻辑信道的优先比特率和/或优先级，包括：
    调整所述逻辑信道的优先比特率为目标优先比特率和/或调整所述逻辑信道的优先级为目标优先级。
  13. 根据权利要求12所述的方法，其中，所述目标优先比特率为以下至少一项：
    当前优先比特率；
    初始优先比特率；
    所述缓存数据量与所述时延预算值之商；
    所述当前优先比特率与第二阈值之积，所述第二阈值为正数。
  14. 根据权利要求13所述的方法，其中，所述数据在所述逻辑信道的缓存时延不满足所述时延预算，所述目标优先比特率大于或等于当前优先比特率；和/或，
    所述数据在所述逻辑信道的缓存时延满足所述时延预算，所述目标优先比特率小于或等于当前优先比特率；和/或，
    所述数据在所述逻辑信道的缓存时延满足所述时延预算，所述目标优先级低于或等于当前优先级；和/或，
    所述数据在所述逻辑信道的缓存时延不满足所述时延预算，所述目标优先级高于或等于当前优先级。
  15. 根据权利要求14所述的方法，其中，所述数据在所述逻辑信道的缓存时延不满足所述时延预算，包括以下至少一项：
    所述目标优先比特率为以下至少一项：当前优先比特率；所述缓存数据量与所述时延预算值之商；所述当前优先比特率与所述第二阈值之积，所述第二阈值为大于或等于1的正数；
    当所述当前优先比特率小于所述缓存数据量与所述时延预算值之商时，所述目标优先比特率为所述缓存数据量与所述时延预算值之商；
    当所述当前优先比特率大于或等于所述缓存数据量与所述时延预算值之商时，所述目标优先比特率为所述当前优先比特率；
    当所述当前优先比特率小于优先比特率门限值时，所述目标优先比特率为所述当前优先比特率与所述第二阈值之积；
    当所述当前优先比特率大于或等于所述优先比特率门限值时，所述目标优先比特率为所述当前优先比特率；
    当所述当前优先级已经为最高优先级时，所述目标优先级为所述当前优先级；
    当所述当前优先级不为最高优先级时，所述目标优先级为所述当前优先级递增。
  16. 根据权利要求15所述的方法，其中，所述优先比特率门限值为所述缓存数据量与所述时延预算值之商；或者，所述优先比特率门限值为第三阈值。
  17. 根据权利要求14至16中任一项所述的方法，其中，所述数据在所述逻辑信道的缓存时延满足所述时延预算，包括以下至少一项：
    所述目标优先比特率为以下至少一项：所述当前优先比特率；初始优先比特率；所述当前优先比特率与所述第二阈值之积，所述第二阈值为小于或等于1的正数；
    当所述当前优先比特率小于或等于所述初始优先比特率时，所述目标优先比特率为所述当前优先比特率；
    当所述当前优先比特率大于或等于所述初始优先比特率时，所述目标优先比特率为所述当前优先比特率与第三阈值之积；
    当所述当前优先级已经为初始配置优先级时，所述目标优先级为所述当前优先级；
    当所述当前优先级不为初始配置优先级时，所述目标优先级为所述当前优先级递减。
  18. 一种通信设备，其中，包括：存储器和处理器；
    所述存储器用于存储程序指令；
    所述处理器用于调用所述存储器中的程序指令以执行如权利要求1所述的方法步骤。
  19. 一种计算机可读存储介质，其中，所述存储介质上存储有计算机程序；所述计算机程序被执行时，实现如权利要求1所述的处理方法步骤。
PCT/CN2022/140485 2022-01-06 2022-12-20 处理方法、通信设备及存储介质 WO2023130954A1 (zh)

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