WO2023124637A1 - 一种输出电压可控型电荷泵电路及射频芯片 - Google Patents

一种输出电压可控型电荷泵电路及射频芯片 Download PDF

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WO2023124637A1
WO2023124637A1 PCT/CN2022/132961 CN2022132961W WO2023124637A1 WO 2023124637 A1 WO2023124637 A1 WO 2023124637A1 CN 2022132961 W CN2022132961 W CN 2022132961W WO 2023124637 A1 WO2023124637 A1 WO 2023124637A1
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effect transistor
field effect
capacitor
clock output
charge pump
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PCT/CN2022/132961
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English (en)
French (fr)
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尚鹏飞
郭嘉帅
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深圳飞骧科技股份有限公司
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Publication of WO2023124637A1 publication Critical patent/WO2023124637A1/zh

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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/06—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider
    • H02M3/07—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps

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  • the utility model relates to the technical field of circuits, in particular to an output voltage controllable charge pump circuit and the charge pump.
  • the circuit of the first charge pump in the related art includes non-overlapping clocks, field effect transistors P1, P2, N3, N4, P5, P6, N7, N8, and capacitors C1, C3, as shown in Figure 2, which utilizes The level at both ends of the two capacitors cannot be mutated.
  • LDO low dropout linear voltage regulator
  • the purpose of the utility model is to overcome at least one technical problem above, and provide a charge pump circuit and a radio frequency chip with controllable output voltage.
  • the utility model provides an output voltage controllable charge pump circuit, including: non-overlapping clock, first field effect transistor, second field effect transistor, third field effect transistor, Four FETs, fifth FETs, sixth FETs, seventh FETs, eighth FETs, first capacitors, second capacitors, third capacitors and fourth capacitors;
  • the non-overlapping clock includes a first clock output terminal, a second clock output terminal, a third clock output terminal and a fourth clock output terminal;
  • the source of the first field effect transistor and the source of the second field effect transistor are used as output terminals to output the charge pump voltage, and the source of the third field effect transistor and the source of the fourth field effect transistor Both poles are connected to the supply voltage;
  • the drain of the first field effect transistor, the gate of the second field effect transistor, the drain of the third field effect transistor and the gate of the fourth field effect transistor are all connected to the first capacitor connected to the first end of the second capacitor, and at the same time both are connected to the first end of the second capacitor;
  • the gate of the first field effect transistor, the drain of the second field effect transistor, the gate of the third field effect transistor, and the drain of the fourth field effect transistor are all connected to the third capacitor are connected to the first end of the capacitor, and are connected to the first end of the fourth capacitor at the same time;
  • Both the source of the fifth field effect transistor and the source of the sixth field effect transistor are connected to a power supply voltage; the source of the seventh field effect transistor and the source of the eighth field effect transistor are connected to to ground;
  • the gate of the fifth field effect transistor is connected to the second clock output end, the gate of the sixth field effect transistor is connected to the fourth clock output end, and the gate of the seventh field effect transistor connected to the third clock output terminal, and the gate of the eighth field effect transistor is connected to the first clock output terminal;
  • the second end of the first capacitor is connected to the drain of the fifth field effect transistor and the drain of the seventh field effect transistor, the second end of the second capacitor is grounded; the second end of the third capacitor The second end is connected to the drain of the sixth field effect transistor and the drain of the eighth field effect transistor, and the second end of the fourth capacitor is grounded.
  • the output signals of the first clock output end and the second clock output end are opposite to each other, the output signals of the third clock output end and the fourth clock output end are opposite to each other, and the first clock output end and the fourth clock output end are opposite to each other.
  • the output signals of the first clock output terminal and the third clock output terminal are opposite to each other and are non-overlapping signals.
  • the first field effect transistor, the second field effect transistor, the fifth field effect transistor and the sixth field effect transistor are P-type field effect transistors.
  • the third field effect transistor, the fourth field effect transistor, the seventh field effect transistor and the eighth field effect transistor are N-type field effect transistors.
  • the utility model provides a radio frequency chip, and the radio frequency chip includes the above-mentioned output voltage controllable charge pump circuit provided by the utility model.
  • the output voltage controllable charge pump circuit and radio frequency chip of the utility model can obtain VDD ⁇ VPOS ⁇ 2VDD by adjusting the ratio of the first capacitor (the third capacitor) and the second capacitor (the fourth capacitor). , improve the reliability of the circuit, avoid the risk of breakdown, and do not need to add an additional LDO, which reduces the difficulty of design and the cost of the circuit.
  • FIG. 1 is a schematic diagram of an output voltage controllable charge pump circuit provided by an embodiment of the present invention.
  • FIG. 2 is a schematic diagram of the first charge pump circuit in the related art.
  • FIG. 3 is a schematic diagram of a second charge pump circuit in the related art.
  • the embodiment of the present invention provides a controllable output voltage charge pump circuit, including: non-overlapping clock 10, first field effect transistor P1, second field effect transistor P2, third field effect transistor Effect transistor N3, fourth field effect transistor N4, fifth field effect transistor P5, sixth field effect transistor P6, seventh field effect transistor N7, eighth field effect transistor N7, first capacitor C1, second capacitor C2, Three capacitors C3 and a fourth capacitor C4.
  • the non-overlapping clock 10 includes a first clock output terminal (Clk1), a second clock output terminal (Clk1b), a third clock output terminal (Clk2) and a fourth clock output terminal (Clk2b).
  • the first clock output terminal, the second clock output terminal, the third clock output terminal and the fourth clock output terminal are used to output or input signals of the non-overlapping clock 10 .
  • the first FET P1 , the second FET P2 , the fifth FET P5 and the sixth FET P6 are P-type FETs.
  • the third field effect transistor N3, the fourth field effect transistor N4, the seventh field effect transistor N7 and the eighth field effect transistor N7 are N-type field effect transistors.
  • the first capacitor C1, the second capacitor C2, the third capacitor C3 and the fourth capacitor C4 are all adjustable capacitors, and the first capacitor C1 and the third capacitor C3 are of the same type A type of capacitor, the second capacitor C2 and the fourth capacitor C4 are capacitors of the same type.
  • the first capacitor C1 , the third capacitor C3 , the second capacitor C2 and the fourth capacitor C4 can all use the same type of capacitor, or use different types of capacitors.
  • the output signals of the first clock output end and the second clock output end are opposite to each other, and the output signals of the third clock output end and the fourth clock output end are opposite to each other, so The output signals of the first clock output end and the third clock output end are opposite to each other and are non-overlapping signals.
  • the source of the first field effect transistor P1 and the source of the second field effect transistor P2 are used as output terminals to output the charge pump voltage
  • the source of the third field effect transistor N3 and the The sources of the fourth field effect transistor N4 are all connected to the power supply voltage
  • the drain of the first field effect transistor P1, the gate of the second field effect transistor P2, and the drain of the third field effect transistor N3 pole and the gate of the fourth field effect transistor N4 are connected to the first end of the first capacitor C1, and at the same time are connected to the first end of the second capacitor C2, the first field effect transistor
  • the gate of P1, the drain of the second field effect transistor P2, the gate of the third field effect transistor N3, and the drain of the fourth field effect transistor N4 are all connected to the first field effect transistor of the third capacitor C2. One end is connected, and both are connected to the first end of the fourth capacitor C3 at the same time.
  • the output terminal is the output terminal of the output voltage controllable charge pump circuit to output the charge pump voltage.
  • the drain of the first field effect transistor P1, the gate of the second field effect transistor P2, the drain of the third field effect transistor N3 and the gate of the fourth field effect transistor N4 are connected together Afterwards, both are connected to the first end of the first capacitor C1, and at the same time are connected to the first end of the second capacitor C2; correspondingly, the first end of the first capacitor C1 and the second
  • the first end of the capacitor C2 can also be connected after the point C (connection point C), and then through the point C and the drain electrode of the first field effect transistor P1 and the drain electrode of the second field effect transistor P2 connected together.
  • the gate, the drain of the third field effect transistor N3 and the gate of the fourth field effect transistor N4 are connected.
  • the gate of the first field effect transistor P1, the drain of the second field effect transistor P2, the gate of the third field effect transistor N3 and the drain of the fourth field effect transistor N4 are connected together Afterwards, both are connected to the first end of the third capacitor C3, and at the same time are connected to the first end of the fourth capacitor C3; correspondingly, the first end of the third capacitor C3 and the fourth capacitor C3
  • the first end of the capacitor C3 can also be connected after the point D (connection point D), and then through the point D and the grid of the first field effect transistor P1 and the gate of the second field effect transistor P2 connected together.
  • the drain, the gate of the third field effect transistor N3 and the drain of the fourth field effect transistor N4 are connected.
  • the source of the fifth field effect transistor P5 and the source of the sixth field effect transistor P6 are both connected to the power supply voltage (VDD), and the source of the seventh field effect transistor N7 and the The sources of the eighth field effect transistor N7 are connected to ground (GND), the gate of the fifth field effect transistor P5 is connected to the second clock output terminal, and the gate of the sixth field effect transistor P6 Connected to the fourth clock output end, the gate of the seventh field effect transistor N7 is connected to the third clock output end, the gate of the eighth field effect transistor N7 is connected to the first clock output end connect.
  • the second end of the first capacitor C1 is connected to the drain of the fifth field effect transistor P5 and the drain of the seventh field effect transistor N7, and the second end of the second capacitor C2
  • the second end of the third capacitor C3 is connected to the drain of the sixth field effect transistor P6 and the drain of the eighth field effect transistor N7, and the second end of the fourth capacitor C4 is grounded .
  • the drain of the fifth field effect transistor P5 and the drain of the seventh field effect transistor N7 are connected after point A (connection point A), and then connected to the other end of the first capacitor C1 through point A .
  • the drain of the sixth field effect transistor P6 and the drain of the eighth field effect transistor N7 are connected after point B (connection point B), and then pass through point B to the other end of the third capacitor C3.
  • VDD is the power supply voltage
  • VPOS is the output voltage of the charge pump.
  • the output voltage controllable charge pump circuit of the present invention can obtain VDD ⁇ VPOS ⁇ 2VDD, which improves the reliability of the circuit, avoids the risk of breakdown, and does not need to add an additional LDO, which reduces the difficulty of design and the cost of the circuit.
  • the utility model also provides a radio frequency chip, including the above-mentioned output voltage controllable charge pump circuit, because the radio frequency chip adopts the above output voltage controllable charge pump circuit, therefore, the radio frequency chip can also achieve the above-mentioned The technical effects achieved by the output voltage controllable charge pump circuit will not be repeated here.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Dc-Dc Converters (AREA)

Abstract

本申请提供了一种输出电压可控型电荷泵电路及射频芯片，其中，所述输出电压可控型电荷泵电路包括：非交叠时钟、第一场效应管、第二场效应管、第三场效应管、第四场效应管、第五场效应管、第六场效应管、第七场效应管、第八场效应管、第一电容、第二电容、第三电容以及第四电容。本申请可以通过调节第一电容(第三电容)和第二电容(第四电容)的比例得到VDD<VPOS<2VDD，提高电路的可靠性，避免击穿风险，且无需额外增加LDO，降低了设计的难度以及电路成本。

Description

一种输出电压可控型电荷泵电路及射频芯片 【技术领域】
本实用新型涉及电路技术领域，尤其涉及一种输出电压可控型电荷泵电路及电荷泵。
【背景技术】
目前，随着半导体技术的迅速发展，集成电路的使用已经遍布各个领域，产品逐步向低电源、低功耗、高可靠性及高性能方面发展。然而，电源的逐步降低，又需要不影响产品的高性能，因此，许多电路设计需要使用电荷泵得出高于电源电压的一个输出电平，以便于电路的设计能保证其高性能。
相关技术中的第一种电荷泵的电路包含非交叠时钟，场效应管P1、P2、N3、N4、P5、P6、N7、N8、以及电容C1、C3，如图2所示，其利用两个电容两端的电平不可突变的特性，将非交叠时钟对两个电容的充电电荷传输至输出电平VPOS，最终得出VPOS＝2*VDD，针对具体应用2*VDD的电平大小会使被供电的电路存在击穿风险；第二种电荷泵的电路是在第一种的基础上添加LDO(低压差线性稳压器)电路，如图3所示，最终得出VPOS＝2*LDO_OUT(输出电压)<2vdd，通过这种方式得到想要的VPOS电平，然而，在其设计过程中需要额外设计一个LDO，这增加了设计的复杂度以及电路成本。
【实用新型内容】
本实用新型的目的是克服上述至少一个技术问题，提供一种输出电压可控型电荷泵电路及射频芯片。
为了实现上述目的，一方面，本实用新型提供了一种输出电压可 控型电荷泵电路，包括：非交叠时钟、第一场效应管、第二场效应管、第三场效应管、第四场效应管、第五场效应管、第六场效应管、第七场效应管、第八场效应管、第一电容、第二电容、第三电容以及第四电容；
所述非交叠时钟包括第一时钟输出端、第二时钟输出端、第三时钟输出端以及第四时钟输出端；
所述第一场效应管的源极和所述第二场效应管的源极作为输出端以输出电荷泵电压，所述第三场效应管的源极和所述第四场效应管的源极均连接至电源电压；
所述第一场效应管的漏极、所述第二场效应管的栅极、所述第三场效应管的漏极以及所述第四场效应管的栅极均与所述第一电容的第一端连接，且同时均与所述第二电容的第一端连接；
所述第一场效应管的栅极、所述第二场效应管的漏极、所述第三场效应管的栅极以及所述第四场效应管的漏极均与所述第三电容的第一端连接，且同时均与所述第四电容的第一端连接；
所述第五场效应管的源极和所述第六场效应管的源极均连接至电源电压；所述第七场效应管的源极以及所述第八场效应管的源极均连接至接地；
所述第五场效应管的栅极与所述第二时钟输出端连接，所述第六场效应管的栅极与所述第四时钟输出端连接，所述第七场效应管的栅极与所述第三时钟输出端连接，所述第八场效应管的栅极与所述第一时钟输出端连接；
所述第一电容的第二端与所述第五场效应管的漏极以及所述第七场效应管的漏极连接，所述第二电容的第二端接地；所述第三电容的第二端与所述第六场效应管的漏极以及所述第八场效应管的漏极连接，所述第四电容的第二端接地。
优选的，所述第一时钟输出端和所述第二时钟输出端的输出信号互为反向，所述第三时钟输出端和所述第四时钟输出端的输出信号互 为反向，所述第一时钟输出端和所述第三时钟输出端的输出信号互为反向且为非交叠信号。
优选的，所述第一场效应管、所述第二场效应管、所述第五场效应管以及所述第六场效应管为P型场效应管。
优选的，所述第三场效应管、所述第四场效应管、所述第七场效应管以及所述第八场效应管为N型场效应管。
第二方面，本实用新型提供了一种射频芯片，所述射频芯片包括本实用新型提供的如上述输出电压可控型电荷泵电路。
与相关技术相比，本实用新型的输出电压可控型电荷泵电路及射频芯片，可以通过调节第一电容(第三电容)和第二电容(第四电容)的比例得到VDD<VPOS<2VDD，提高电路的可靠性，避免击穿风险，且无需额外增加LDO，降低了设计的难度以及电路成本。
【附图说明】
为了更清楚地说明本实用新型实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本实用新型的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其它的附图，其中：
图1为本实用新型实施例提供的一种输出电压可控型电荷泵电路的原理图。
图2为相关技术中的第一种电荷泵电路的原理图。
图3为相关技术中的第二种电荷泵电路的原理图。
【具体实施方式】
下面将结合本实用新型实施例中的附图，对本实用新型实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅是本实 用新型的一部分实施例，而不是全部的实施例。基于本实用新型中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其它实施例，都属于本实用新型保护的范围。
请参阅图1所示，本实用新型实施例提供了一种输出电压可控型电荷泵电路，包括：非交叠时钟10、第一场效应管P1、第二场效应管P2、第三场效应管N3、第四场效应管N4、第五场效应管P5、第六场效应管P6、第七场效应管N7、第八场效应管N7、第一电容C1、第二电容C2、第三电容C3以及第四电容C4。
其中，所述非交叠时钟10包括第一时钟输出端(Clk1)、第二时钟输出端(Clk1b)、第三时钟输出端(Clk2)以及第四时钟输出端(Clk2b)。
所述第一时钟输出端、所述第二时钟输出端、所述第三时钟输出端以及所述第四时钟输出端用于输出或输入所述非交叠时钟10的信号。
所述第一场效应管P1、所述第二场效应管P2、所述第五场效应管P5以及所述第六场效应管P6为P型场效应管。
所述第三场效应管N3、所述第四场效应管N4、所述第七场效应管N7以及所述第八场效应管N7为N型场效应管。
所述第一电容C1、所述第二电容C2、所述第三电容C3以及所述第四电容C4均为可调电容，且所述第一电容C1和所述第三电容C3为同一种型号的电容，所述第二电容C2和所述第四电容C4为同一种型号的电容。当然，根据实际需求，所述第一电容C1、所述第三电容C3、所述第二电容C2以及所述第四电容C4均可以使用同一种型号的电容，或者使用不同型号的电容。
本实施例中，所述第一时钟输出端和所述第二时钟输出端的输出信号互为反向，所述第三时钟输出端和所述第四时钟输出端的输出信号互为反向，所述第一时钟输出端和所述第三时钟输出端的输出信号互为反向且为非交叠信号。
本实施例中，所述第一场效应管P1的源极和所述第二场效应管P2的源极作为输出端以输出电荷泵电压，所述第三场效应管N3的源极和所述第四场效应管N4的源极均连接至电源电压，所述第一场效应管P1的漏极、所述第二场效应管P2的栅极、所述第三场效应管N3的漏极以及所述第四场效应管N4的栅极均与所述第一电容C1的第一端连接，且同时均与所述第二电容C2的第一端连接，所述第一场效应管P1的栅极、所述第二场效应管P2的漏极、所述第三场效应管N3的栅极以及所述第四场效应管N4的漏极均与所述第三电容C2的第一端连接，且同时均与所述第四电容C3的第一端连接。
其中，所述输出端为所述输出电压可控型电荷泵电路的输出端以输出电荷泵电压。
所述第一场效应管P1的漏极、所述第二场效应管P2的栅极、所述第三场效应管N3的漏极以及所述第四场效应管N4的栅极连接在一起后，再均与所述第一电容C1的第一端连接，同时均与所述第二电容C2的第一端连接；相应的，所述第一电容C1的第一端以及所述第二电容C2的第一端也可以连接在C点(连接点C)后，再通过C点与连接在一起后的所述第一场效应管P1的漏极、所述第二场效应管P2的栅极、所述第三场效应管N3的漏极以及所述第四场效应管N4的栅极连接。
所述第一场效应管P1的栅极、所述第二场效应管P2的漏极、所述第三场效应管N3的栅极以及所述第四场效应管N4的漏极连接在一起后，再均与所述第三电容C3的第一端连接，同时均与所述第四电容C3的第一端连接；相应的，所述第三电容C3的第一端以及所述第四电容C3的第一端也可以连接在D点(连接点D)后，再通过D点与连接在一起后的所述第一场效应管P1的栅极、所述第二场效应管P2的漏极、所述第三场效应管N3的栅极以及所述第四场效应管N4的漏极连接。
本实施例中，所述第五场效应管P5的源极和所述第六场效应管 P6的源极均连接至电源电压(VDD)，所述第七场效应管N7的源极以及所述第八场效应管N7的源极均连接至接地(GND)，所述第五场效应管P5的栅极与所述第二时钟输出端连接，所述第六场效应管P6的栅极与所述第四时钟输出端连接，所述第七场效应管N7的栅极与所述第三时钟输出端连接，所述第八场效应管N7的栅极与所述第一时钟输出端连接。
本实施例中，所述第一电容C1的第二端与所述第五场效应管P5的漏极以及所述第七场效应管N7的漏极连接，所述第二电容C2的第二端接地，所述第三电容C3的第二端与所述第六场效应管P6的漏极以及所述第八场效应管N7的漏极连接，所述第四电容C4的第二端接地。
其中，所述第五场效应管P5的漏极以及所述第七场效应管N7的漏极连接在A点(连接点A)后，再通过A点与所述第一电容C1的另一端。
所述第六场效应管P6的漏极以及所述第八场效应管N7的漏极连接在B点(连接点B)后，再通过B点与所述第三电容C3的另一端。
所述输出电压可控型电荷泵电路的工作原理为：通过非交叠时钟10控制，在A(B)点存在电压变化ΔVDD，利用电容分压的原理，在C(D)端得到ΔVDD*[C1/(C1+C2)]，最终VPOS＝VDD+ΔVDD*[C1/(C1+C2)]，VDD<VPOS<2*VDD，通过调节第一电容C1(第三电容C3)和第二电容C2(第四电容C4)的比例来控制输出电平VPOS的幅值。这样可以有效的避免被供电器件存在的击穿风险，同时，设计过程避免了需要额外设计一个LDO的情况，降低了设计难度以及电路成本。
其中，VDD为电源电压；VPOS为电荷泵的输出电压。
与相关技术相比，本实用新型的输出电压可控型电荷泵电路，可以通过调节第一电容C1(第三电容C3)和第二电容C2(第四电容C4)的比例得到VDD<VPOS<2VDD，提高电路的可靠性，避免击穿风险， 且无需额外增加LDO，降低了设计的难度以及电路成本。
本实用新型还提供了一种射频芯片，包括上述的输出电压可控型电荷泵电路，由于该射频芯片采用了上述的输出电压可控型电荷泵电路，因此，该射频芯片也可以达到上述的输出电压可控型电荷泵电路所达到的技术效果，在此不作赘述。
以上所述的仅是本实用新型的实施方式，在此应当指出，对于本领域的普通技术人员来说，在不脱离本实用新型创造构思的前提下，还可以做出改进，但这些均属于本实用新型的保护范围。

Claims (5)

  1. 一种输出电压可控型电荷泵电路，其特征在于，包括：非交叠时钟、第一场效应管、第二场效应管、第三场效应管、第四场效应管、第五场效应管、第六场效应管、第七场效应管、第八场效应管、第一电容、第二电容、第三电容以及第四电容；
    所述非交叠时钟包括第一时钟输出端、第二时钟输出端、第三时钟输出端以及第四时钟输出端；
    所述第一场效应管的源极和所述第二场效应管的源极作为输出端以输出电荷泵电压，所述第三场效应管的源极和所述第四场效应管的源极均连接至电源电压；
    所述第一场效应管的漏极、所述第二场效应管的栅极、所述第三场效应管的漏极以及所述第四场效应管的栅极均与所述第一电容的第一端连接，且同时均与所述第二电容的第一端连接；
    所述第一场效应管的栅极、所述第二场效应管的漏极、所述第三场效应管的栅极以及所述第四场效应管的漏极均与所述第三电容的第一端连接，且同时均与所述第四电容的第一端连接；
    所述第五场效应管的源极和所述第六场效应管的源极均连接至电源电压；所述第七场效应管的源极以及所述第八场效应管的源极均连接至接地；
    所述第五场效应管的栅极与所述第二时钟输出端连接，所述第六场效应管的栅极与所述第四时钟输出端连接，所述第七场效应管的栅极与所述第三时钟输出端连接，所述第八场效应管的栅极与所述第一时钟输出端连接；
    所述第一电容的第二端与所述第五场效应管的漏极以及所述第七场效应管的漏极连接，所述第二电容的第二端接地；所述第三电容的第二端与所述第六场效应管的漏极以及所述第八场效应管的漏极连接，所述第四电容的第二端接地。
  2. 利要求1所述的输出电压可控型电荷泵电路，其特征在于，所 述第一时钟输出端和所述第二时钟输出端的输出信号互为反向，所述第三时钟输出端和所述第四时钟输出端的输出信号互为反向，所述第一时钟输出端和所述第三时钟输出端的输出信号互为反向且为非交叠信号。
  3. 权利要求1所述的输出电压可控型电荷泵电路，其特征在于，所述第一场效应管、所述第二场效应管、所述第五场效应管以及所述第六场效应管为P型场效应管。
  4. 权利要求3所述的输出电压可控型电荷泵电路，其特征在于，所述第三场效应管、所述第四场效应管、所述第七场效应管以及所述第八场效应管为N型场效应管。
  5. 一种射频芯片，其特征在于，所述射频芯片包括如权利要求1至4任意一项所述的输出电压可控型电荷泵电路。
PCT/CN2022/132961 2021-12-28 2022-11-18 一种输出电压可控型电荷泵电路及射频芯片 WO2023124637A1 (zh)

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111525790A (zh) * 2020-03-25 2020-08-11 东南大学 一种电荷泵电路
CN112448576A (zh) * 2020-11-16 2021-03-05 上海唯捷创芯电子技术有限公司 一种正负电压电荷泵电路、芯片及通信终端
CN112671393A (zh) * 2020-12-29 2021-04-16 成都锐成芯微科技股份有限公司 电平转换电路
US11011981B1 (en) * 2020-09-02 2021-05-18 Psemi Corporation Differential clock level translator for charge pumps
CN216437058U (zh) * 2021-12-28 2022-05-03 深圳飞骧科技股份有限公司 一种输出电压可控型电荷泵电路及射频芯片

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111525790A (zh) * 2020-03-25 2020-08-11 东南大学 一种电荷泵电路
US11011981B1 (en) * 2020-09-02 2021-05-18 Psemi Corporation Differential clock level translator for charge pumps
CN112448576A (zh) * 2020-11-16 2021-03-05 上海唯捷创芯电子技术有限公司 一种正负电压电荷泵电路、芯片及通信终端
CN112671393A (zh) * 2020-12-29 2021-04-16 成都锐成芯微科技股份有限公司 电平转换电路
CN216437058U (zh) * 2021-12-28 2022-05-03 深圳飞骧科技股份有限公司 一种输出电压可控型电荷泵电路及射频芯片

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