WO2023123915A1 - Appareil et procédé d'accès mémoire, dispositif électronique et support de stockage - Google Patents

Appareil et procédé d'accès mémoire, dispositif électronique et support de stockage Download PDF

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WO2023123915A1
WO2023123915A1 PCT/CN2022/100162 CN2022100162W WO2023123915A1 WO 2023123915 A1 WO2023123915 A1 WO 2023123915A1 CN 2022100162 W CN2022100162 W CN 2022100162W WO 2023123915 A1 WO2023123915 A1 WO 2023123915A1
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bank
channel
access
memory
parameter
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PCT/CN2022/100162
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English (en)
Chinese (zh)
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曹庆新
李炜
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深圳云天励飞技术股份有限公司
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Publication of WO2023123915A1 publication Critical patent/WO2023123915A1/fr

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal

Definitions

  • the present application relates to the technical field of computers, and in particular to a storage access method, device, electronic equipment and storage medium.
  • Memory is a memory device used to save information in modern information technology. With the development of computer technology and storage technology, the capacity of memory in electronic equipment is getting larger and larger. Generally, a memory includes a plurality of BANKs (also referred to as memory banks). With the continuous increase of memory capacity, the number of BANKs is also increasing.
  • DMA Direct Memory Access
  • the present application provides a memory access method, device, electronic equipment and storage medium, which reduce memory access delay and improve access efficiency.
  • the present application provides a memory access method, which is applied to memory access.
  • the memory includes N BANKs, where N is an integer greater than 1.
  • the method includes: acquiring the memory of M channels issued by DMA Access request; M is an integer greater than 1; obtain the BANK access parameters of the channel according to the memory access request of each channel; the BANK access parameters include N groups of parameters corresponding to the N BANKs one-to-one; according to The BANK access parameters of the M channels determine the authorization parameters of each of the channels in parallel; the authorization parameters are used to indicate the BANKs that the channels can access.
  • each set of parameters includes a BANK access identifier and a BANK access address; the BANK access identifier is used to indicate whether the channel accesses the BANK; the BANK access parameters of the M channels determine in parallel
  • the authorization parameters of the channels include: obtaining the access priorities of the M channels; determining the target channel of each channel according to the access priority, and the priority of the target channel is higher than that of the channel. Priority; for each channel, determine the authorization parameters of the channel according to the channel and the BANK access identifier and BANK access address of the target channel of the channel.
  • determining the authorization parameters of the channel according to the channel and the BANK access ID and BANK access address of the channel's target channel includes: according to the BANK access ID of the channel's target channel, the The BANK access address of the channel and the BANK access address of the target channel of the channel determine the first parameter and the second parameter of the target channel; the first parameter is used to indicate that the channel and the target channel are accessed in BANK The BANK that the channel can access under the condition that the address does not conflict; the second parameter is used to indicate the channel and the target channel, and the BANK that the channel cannot access when the BANK access address conflicts; according to the target The first parameter and the second parameter of the channel, and the BANK access identifier of the channel determine the authorization parameters of the channel.
  • the determining the authorization parameter of the channel according to the first parameter and the second parameter of the target channel and the BANK access identifier of the channel includes: according to the first parameter and the second The parameter determines a third parameter, and the third parameter is used to indicate the BANK accessible to the channel; and the authorization parameter of the channel is determined according to the third parameter and the BANK access identifier of the channel.
  • the memory access method further includes: combining the memory access requests of the M channels according to the authorization parameters and BANK access parameters of the M channels, and determining a memory signal; the memory signal includes N-dimensional parameters, The N dimensions correspond to the N BANKs one-to-one; output the memory signal.
  • the memory signal includes an N-dimensional enable parameter, a memory address parameter, a memory write indication parameter, and a memory write data parameter;
  • the enable parameter is used to indicate whether the M channels access the BANK, so
  • the memory address parameter is used to indicate the address of the BANK accessed by the M channels
  • the memory write instruction parameter is used to indicate the position where the M channels write data to the BANK
  • the memory write data Parameters are used to indicate the data to be written.
  • each set of parameters includes a BANK write indication parameter and a BANK write data parameter; the memory access requests of the M channels are combined according to the authorization parameters of the M channels and the BANK access parameters, and the memory access requests of the M channels are determined.
  • the signal includes: determining the enable parameter according to the authorization parameters of the M channels; determining the memory address parameter according to the authorization parameters of the M channels and the BANK access address; determining the memory address parameter according to the authorization parameters of the M channels and BANK write indication parameters to determine the memory write indication parameters; according to the authorization parameters of the M channels and the BANK write data parameters, determine the memory write data parameters.
  • a device for accessing a memory which is used for accessing the memory.
  • the memory includes N BANKs, and N is an integer greater than 1.
  • the device includes: an acquisition module, configured to acquire a direct memory access DMA issued The memory access requests of M channels; M is an integer greater than 1; the decoding module is used to obtain the BANK access parameters of the channels according to the memory access requests of each of the channels; the BANK access parameters include the same as the N groups of parameters corresponding to N BANKs one-to-one; a processing module, configured to determine the authorization parameters of each of the channels in parallel according to the BANK access parameters of the M channels; the authorization parameters are used to indicate that the channels are accessible BANK.
  • the present application provides an electronic device, including: a memory, a processor, and a computer program stored on the memory and operable on the processor, and the processor implements the present invention when executing the computer program.
  • the access method of the memory provided by the application.
  • a chip including: a memory, a processor, and a computer program stored on the memory and operable on the processor, and the processor implements the computer program provided by the present application when executing the computer program.
  • Memory access method including: a memory, a processor, and a computer program stored on the memory and operable on the processor, and the processor implements the computer program provided by the present application when executing the computer program.
  • the present application provides a computer-readable storage medium on which a computer program is stored, and when the computer program is executed by a processor, the memory access method provided in the present application is implemented.
  • the present application provides a memory access method, device, electronic equipment and storage medium, by performing BANK decoding on the memory access requests of M channels sent by DMA, the BANK access parameters for each channel to access each BANK can be obtained , based on the BANK access parameters, the parallel processing logic is used to perform conflict detection on M channels at the same time, thereby realizing the parallel conflict detection of multiple channels and the parallel access of the memory, shortening the logic processing delay, and improving the access efficiency of the memory.
  • FIG. 1 is a schematic diagram of the principle of DMA access memory provided by the embodiment of the present application.
  • FIG. 2 is a flow chart of a memory access method provided in an embodiment of the present application.
  • FIG. 3 is another flow chart of a memory access method provided in an embodiment of the present application.
  • FIG. 4 is a schematic structural diagram of a device for accessing a memory provided in an embodiment of the present application.
  • FIG. 5 is a schematic structural diagram of an electronic device provided by an embodiment of the present application.
  • the memory chip can be manufactured by dividing the memory capacity into several arrays, that is to say, the memory chip includes multiple BANKs.
  • DMA is an important module in electronic equipment. DMA transfers can copy data from one address space to another without relying on the central processing unit (CPU), between peripherals and memory or between memory and Provides high-speed data transfer between memories. When the CPU initiates this transfer action, the transfer action itself is implemented and completed by the DMA controller. DMA transmission does not require the CPU to directly control the transmission, and there is no interrupt processing.
  • the hardware opens up a channel for direct data transmission for memory and input/output (Input/Output, IO) devices, which greatly improves the efficiency of the CPU.
  • DMA transfers can simultaneously access memory through multiple access channels.
  • Access channels can also be called channels.
  • the number of access channels is M, and M is an integer greater than 1. This application does not limit the value of M.
  • M 8 as an example for description.
  • FIG. 1 is a schematic diagram of a principle of DMA accessing a memory provided by an embodiment of the present application.
  • the number M of channels 14 is 8, which can be marked as channels 0 to 7 .
  • DMA11 performs data access to 16 BANK13 through 8 channels 14, and each BANK13 can be independently accessed in parallel.
  • the access module 12 is used to perform conflict judgment on the memory access requests of the 8 channels sent by the DMA, and merge the memory access requests of the 8 channels according to the conflict judgment results, thereby realizing multi-channel parallel conflict judgment and parallel Memory access shortens logic processing delay and improves memory access efficiency.
  • the present application does not limit the name of the access module 12, for example, it may also be called a memory access device, a memory access device, and the like.
  • the DMA access includes but is not limited to at least one of the following: reading data from the memory (referred to as a read request for short), or writing data into the memory (referred to as a write request for short).
  • the memory access requests of the 8 channels sent by the DMA may be read requests at the same time, or write requests at the same time, or partly read requests and partly write requests.
  • the memory access requests of the two channels are all read requests, and the addresses of the BANKs are the same.
  • the memory access requests of the two channels are write requests, the address of the BANK is the same, and data is written to different areas in the BANK respectively.
  • the 8 channels can be marked as channel 0 ⁇ channel 7.
  • the 16 banks can be marked as BANK0 ⁇ BANK15.
  • the access priority of channel 0 to channel 7 decreases in turn.
  • FIG. 2 is a flowchart of a memory access method provided by an embodiment of the present application.
  • the memory access method provided in this embodiment may be executed by a memory access device, an electronic device, or a chip for accessing the memory.
  • the memory includes N BANKs, and N is an integer greater than 1.
  • the memory access method provided in this embodiment may include:
  • M is an integer greater than 1.
  • the parameters in the memory access request can be referred to Table 1.
  • the parameters included in the memory access request of 8 channels can be expressed as: dma_req[8], dma_addr[8], dma_wdata[8], dma_wmask[8], dma_rdata[8], dma_rmask[8].
  • [8] indicates that each parameter is an 8-dimensional array.
  • dma_req[8] may include a total of 8 parameters, dma_req[0], dma_req[1], ..., dma_req[7], respectively representing the first identification information corresponding to channels 0-7.
  • the memory access request of channel 0 may include the following parameters: first identification information dma_req[0], first address information dma_addr[0], first write indication parameter dma_wdata[0], first A write data parameter dma_wmask[0], a first read indication parameter dma_rdata[0] and a first read data parameter dma_rmask[0].
  • the BANK access parameters include N groups of parameters corresponding to N BANKs one-to-one.
  • BANK decoding is performed on the memory access request of each channel to obtain the BANK access parameter of each channel. Since each channel can access N BANKs in parallel, after BANK decoding, the memory access request of each channel corresponds to the parameters of N BANKs, that is, the BANK access parameters of each channel include N groups of parameters, N Group parameters correspond to N BANKs one-to-one.
  • the parameters shown in Table 2 are respectively the same as the parameters shown in Table 1 (the first identification information , the first address information, the first write instruction parameter, the first write data parameter, the first read instruction parameter and the first read data parameter) one-to-one correspondence, which is obtained by performing BANK decoding on the parameters in Table 1.
  • the BANK access parameters of 8 channels can be expressed as: dma_bank_req[8][16], dma_bank_addr[8][16], dma_bank_wdata[8][16], dma_bank_wmask[8][16], dma_bank_rdata[8][16] , dma_bank_rmask[8][16].
  • [8][16] means that each parameter is a two-dimensional array of 8 ⁇ 16 dimensions, [8] corresponds to 8 channels, and [16] corresponds to 16 banks.
  • dma_bank_req[8][16] includes dma_bank_req[0][0] ⁇ dma_bank_req[0][15], dma_bank_req[1][0] ⁇ dma_bank_req[1][15], dma_bank_req[2][0] ⁇ dma_bank_req[2][15], dma_bank_req[3][0] ⁇ dma_bank_req[3][15], dma_bank_req[4][0] ⁇ dma_bank_req[4][15], dma_bank_req[5][0] ⁇ dma_bank_req[ 5][15], dma_bank_req[6][0] ⁇ dma_bank_req[6][15], dma_bank_req[7][0] ⁇ dma_bank_req[0]
  • S203 Determine the authorization parameters of each channel in parallel according to the BANK access parameters of the M channels.
  • the authorization parameter is used to indicate the BANK that the channel can access.
  • the BANK access parameters of the M channels can indicate the access status of each of the M channels to each of the N BANKs. Therefore, the authorization of the M channels can be determined in parallel according to the BANK access parameters of the M channels. Parameters, that is, the conflict detection can be performed on M channels at the same time through the parallel processing logic, the conflict detection result can be obtained, and the BANK accessible to each channel can be determined.
  • the memory access method provided in this embodiment is applicable to the scenario where the DMA performs parallel access to N BANKs through M channels.
  • the BANK access parameters for each channel to access each BANK can be obtained.
  • parallel processing logic is used to simultaneously perform conflict detection on M channels. Therefore, the parallel conflict detection of multiple channels and the parallel access of the memory are realized, the logic processing time delay is shortened, and the access efficiency of the memory is improved.
  • FIG. 3 is another flowchart of a method for accessing a memory provided in the embodiment of the present application.
  • the authorization parameters of each channel are determined in parallel according to the BANK access parameters of M channels, which may include:
  • the access priority is used to indicate the access sequence and/or the access authorization sequence of the M channels. for example. Assume that the access priority of channel 0 is higher than that of channel 1. If the accesses of channel 0 and channel 1 do not conflict, for example, they both access BANK0 and the address of BANK0 is the same. Then, if channel 0 determines that BANK0 can be accessed, then channel 1 must have access to BANK0. If channel 0 and channel 1 access conflict, for example, they both access BANK0 and the address of BANK0 is different. Then, if channel 0 determines that BANK0 can be accessed, then channel 1 cannot access BANK0, and channel 0 and channel 1 need to access BANK0 serially.
  • the access priorities of the M channels may be preset access priorities.
  • the access priorities of channels 0 to 7 decrease in order, that is, the access priority of channel 0 is the highest, and the access priority of channel 7 is the lowest.
  • the access priorities of the M channels can be obtained in real time.
  • the target channels include channel 0 and channel 1.
  • the target channels include channel 0 to channel 3.
  • the target channels include channels 0 to 6.
  • the BANK access identifier is used to indicate whether the channel accesses the BANK. By accessing the address of the BANK, it can be determined whether the addresses of two channels with different access priorities conflict. It can be understood that if a channel with high access priority accesses a certain bank, and the channels with high access priority and low access priority do not conflict, then the channel with low access priority can access the bank. If a channel with high access priority accesses a certain bank, and the channels with high access priority and low access priority conflict, the channel with low access priority cannot access the bank. If a channel with a high access priority does not access a certain bank, a channel with a low access priority can access the bank. Channels with low access priority will not affect channels with high access priority.
  • the target channels include channel 0 and channel 1.
  • the authorization parameter of channel 2 may be determined according to the BANK access ID and BANK access address of channel 2, and the BANK access ID and BANK access address of channel 0 and channel 1.
  • the target channels include channels 0 to 6.
  • the authorization parameter of channel 7 may be determined according to the BANK access ID and BANK access address of channel 7, and the BANK access IDs and BANK access addresses of channels 0 to 6.
  • the target channel corresponding to each channel with a higher access priority than the channel can be determined.
  • the channel performs conflict detection to determine the authorization parameters of the channel, avoiding the processing of related parameters of channels lower than the access priority of the channel, improving the detection efficiency of conflict detection for M channels at the same time, and shortening the logic processing delay , improving memory access efficiency.
  • the authorization parameters of the channel are determined, which may include:
  • the first parameter and the second parameter are determined according to the BANK access identifier of the target channel of the channel, the BANK access address of the channel, and the BANK access address of the target channel of the channel.
  • the first parameter is used to indicate the BANK that the channel can access under the condition that the access address of the channel and the target channel do not conflict with each other.
  • the second parameter is used to indicate the BANK that the channel cannot access when the access address of the BANK conflicts between the channel and the target channel.
  • the authorization parameter of the channel is determined.
  • Step 71 Determine the first parameter dma_bank_addr_eq7[i] of the i-th target channel according to the following algorithm logic.
  • dma_bank_req[i] indicates the BANK access identifier of the i-th target channel
  • dma_bank_addr[7] indicates the BANK access address of the seventh channel
  • dma_bank_addr[i] indicates the BANK access address of the i-th target channel.
  • dma_bank_addr_eq7[i] may indicate the bank that the i-th target channel can access when channel 7 does not conflict with the i-th target channel.
  • Step 72 Determine the second parameter Dma_bank_addr_ne7[i] of the i-th target channel according to the following algorithm logic.
  • dma_bank_addr[7]! dma_bank_addr[i], indicating that channel 7 conflicts with the i-th target channel.
  • dma_bank_addr_eq7[i] may indicate the BANK that the i-th target channel can access when channel 7 conflicts with the i-th target channel.
  • Step 73 According to the first parameter dma_bank_addr_eq7[i], the second parameter Dma_bank_addr_ne7[i] and the BANK access identifier dma_bank_req[7] of channel 7, the authorization parameters of channel 7 can be determined.
  • Step 61 Determine the first parameter dma_bank_addr_eq6[i] of the i-th target channel according to the following algorithm logic.
  • dma_bank_req[i] indicates the bank access identifier of the i-th target channel
  • dma_bank_addr[6] indicates the bank access address of the sixth channel
  • dma_bank_addr[i] indicates the bank access address of the i-th target channel.
  • dma_bank_addr_eq6[i] may indicate the BANK that the i-th target channel can access when channel 6 does not conflict with the i-th target channel.
  • Step 63 According to the first parameter dma_bank_addr_eq6[i], the second parameter Dma_bank_addr_ne6[i] and the BANK access identifier dma_bank_req[6] of channel 6, the authorization parameters of channel 6 can be determined.
  • determining the authorization parameters of the channel may include:
  • a third parameter is determined according to the first parameter and the second parameter, and the third parameter is used to indicate a bank accessible to the channel.
  • the authorization parameter of the channel is determined.
  • step 73 may include:
  • Step 731 determine the third parameter Dma_bank_issue7 of channel 7 according to the following algorithm logic.
  • and ⁇ are operators in the programming language,
  • dma_bank_addr_eq7[0] may indicate the bank that channel 0 can access when channel 7 does not conflict with the 0th target channel (channel 0), that is, the bank that channel 7 can access.
  • (dma_bank_addr_eq7[1]&( ⁇ Dma_bank_addr_ne7[0])) can indicate the bank that channel 1 can access when channel 7 and the first target channel (channel 1) do not conflict, that is, the bank that channel 7 can access.
  • Dma_bank_issue7 may indicate the bank that channel 7 can access when channel 7 does not conflict with the target channel.
  • Step 732 according to the following algorithm logic, according to the third parameter Dma_bank_issue7 of channel 7 and the BANK access identifier dma_bank_req[7] of channel 7, determine the authorization parameter dma_bank_gnt[7] of channel 7.
  • dma_bank_gnt[7] dma_bank_req[7] & Dma_bank_issue7.
  • step 63 may include:
  • Step 631 determine the third parameter Dma_bank_issue6 of channel 6 according to the following algorithm logic.
  • Step 632 according to the following algorithm logic, according to the third parameter Dma_bank_issue6 of channel 6 and the BANK access identifier dma_bank_req[6] of channel 6, determine the authorization parameter dma_bank_gnt[6] of channel 6.
  • dma_bank_gnt[6] dma_bank_req[6]&Dma_bank_issue6.
  • the memory access method provided in this embodiment may also include:
  • the memory access requests of the M channels are combined according to the authorization parameters of the M channels and the BANK access parameters, and the memory signal is determined.
  • the memory signal includes N-dimensional parameters, and the N-dimension corresponds to N BANKs one-to-one.
  • the memory signal is an N-dimensional parameter, and the N-dimension corresponds to N BANKs one-to-one.
  • combining the memory access requests of the M channels according to the authorization parameters and the BANK access parameters of the M channels, and determining the memory signal may include:
  • the enabling parameter is determined according to the authorization parameters of the M channels.
  • the memory write data parameters are determined.
  • Dma_bank_en
  • Dma_bank_addr (dma_bank_gnt[0]&dma_bank_addr[0])
  • (dma_bank_gnt[0]&dma_bank_addr[0]) indicates the address of the BANK that channel 0 can access, and so on.
  • Dma_bank_wmask (dma_bank_gnt[0]&dma_bank_wmask[0])
  • Dma_bank_wdata (dma_bank_gnt[0]&dma_bank_wdata[0])
  • FIG. 4 is a schematic structural diagram of a device for accessing a memory provided by an embodiment of the present application.
  • the memory access method provided in this embodiment may execute the memory access method provided in this embodiment, and be applied to memory access.
  • the memory includes N BANKs, where N is an integer greater than 1.
  • the memory access device provided in this embodiment may include:
  • the acquiring module 401 is configured to acquire the memory access requests of M channels issued by the DMA.
  • M is an integer greater than 1.
  • the decoding module 402 is configured to obtain the BANK access parameters of the channel according to the memory access request of each channel.
  • the BANK access parameters include N groups of parameters corresponding to N BANKs one-to-one.
  • the processing module 403 is configured to determine the authorization parameters of each channel in parallel according to the BANK access parameters of the M channels.
  • the authorization parameter is used to indicate the BANK that the channel can access.
  • each set of parameters includes a BANK access identifier and a BANK access address; the BANK access identifier is used to indicate whether the channel accesses the BANK;
  • the processing module 403 is used for:
  • the priority of the target channel is higher than the priority of the channel
  • the authorization parameters of the channel are determined according to the channel and the BANK access identifier and BANK access address of the channel's target channel.
  • processing module 403 is used for:
  • the BANK access address of the channel and the BANK access address of the target channel of the channel determine the first parameter and the second parameter of the target channel;
  • the first parameter It is used to indicate that the channel and the target channel have access to the BANK under the condition that the BANK access address does not conflict;
  • the second parameter is used to indicate that the channel and the target channel have a BANK access address conflict BANKs that are inaccessible to the channel under the circumstances;
  • the authorization parameters of the channel are determined according to the first parameter and the second parameter of the target channel, and the BANK access identifier of the channel.
  • processing module 403 is used for:
  • the shown processing module 403 is also used for:
  • the memory signal includes N-dimensional parameters, and the N-dimension is the same as the N BANKs. one-to-one correspondence;
  • the memory signal includes an N-dimensional enable parameter, a memory address parameter, a memory write indication parameter, and a memory write data parameter;
  • the enable parameter is used to indicate whether the M channels access the BANK, so
  • the memory address parameter is used to indicate the address of the BANK accessed by the M channels
  • the memory write instruction parameter is used to indicate the position where the M channels write data to the BANK
  • the memory write data Parameters are used to indicate the data to be written.
  • each set of parameters includes a BANK write indication parameter and a BANK write data parameter
  • the processing module 403 shown is used for:
  • the memory write data parameter is determined according to the authorization parameters of the M channels and the BANK write data parameter.
  • FIG. 5 is a schematic structural diagram of an electronic device provided by an embodiment of the present application.
  • the electronic device provided in this embodiment may include a processor 502 connected to a system bus 501 , a memory 504 and a communication interface 503 .
  • the processor 502 is used to provide calculation and control capabilities.
  • the memory 504 includes a non-volatile storage medium and an internal memory.
  • the non-volatile storage medium stores an operating system and computer programs.
  • the internal memory provides an environment for the operation of the operating system and computer programs in the non-volatile storage medium.
  • the communication interface 503 of the electronic device is used to implement communication. When the computer program is executed by the processor 502, the memory access method provided in this application can be implemented.
  • FIG. 5 is only a block diagram of a part of the structure related to the solution of this application, and does not constitute a limitation on the access method of the memory provided by this application. More or fewer components than those shown, or combinations of certain components, or different arrangements of components.
  • a chip including: a memory, a processor, and a computer program stored on the memory and operable on the processor, when the processor executes the computer program, the present invention is realized.
  • the access method of the memory provided by the application.
  • a computer-readable storage medium on which a computer program is stored, and when the computer program is executed by a processor, the memory access method provided in this application can be implemented.
  • Nonvolatile memory can include read only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), or flash memory.
  • Volatile memory can include random access memory (RAM) or external cache memory.
  • RAM random access memory
  • RAM is available in many forms such as Static RAM (SRAM), Dynamic RAM (DRAM), Synchronous DRAM (SDRAM), Double Data Rate SDRAM (DDRSDRAM), Enhanced SDRAM (ESDRAM), Synchronous Chain Synchlink DRAM (SLDRAM), memory bus (Rambus) direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM), etc.

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Abstract

La présente demande se rapporte au domaine technique des ordinateurs. L'invention concerne un appareil et procédé d'accès mémoire, un dispositif électronique et un support de stockage. La mémoire comprend N BANQUES. Le procédé d'accès mémoire comprend : l'acquisition de demandes d'accès à la mémoire de M canaux envoyés par accès direct en mémoire (DMA), M étant un nombre entier supérieur à 1 ; l'acquisition de paramètres d'accès à la BANQUE des canaux en fonction des demandes d'accès à la mémoire des canaux, les paramètres d'accès à la BANQUE comprenant N groupes de paramètres correspondant aux N BANQUES sur une base individuelle ; et la détermination simultanée des paramètres d'autorisation respectifs des canaux en fonction des paramètres d'accès à la BANQUE des M canaux, chaque paramètre d'autorisation étant utilisé pour indiquer une BANQUE à laquelle un canal peut avoir accès. Au moyen du procédé d'accès mémoire décrit dans la présente invention, dans un scénario où le DMA accède à une mémoire au moyen de canaux multiples, la détermination simultanée des conflits et l'accès simultané à la mémoire sont réalisés, et le délai de traitement logique est réduit, ce qui améliore l'efficacité de l'accès mémoire.
PCT/CN2022/100162 2021-12-27 2022-06-21 Appareil et procédé d'accès mémoire, dispositif électronique et support de stockage WO2023123915A1 (fr)

Applications Claiming Priority (2)

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