WO2023123756A1 - 一种半导体发光元件及其制备方法、led芯片 - Google Patents

一种半导体发光元件及其制备方法、led芯片 Download PDF

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Publication number
WO2023123756A1
WO2023123756A1 PCT/CN2022/087897 CN2022087897W WO2023123756A1 WO 2023123756 A1 WO2023123756 A1 WO 2023123756A1 CN 2022087897 W CN2022087897 W CN 2022087897W WO 2023123756 A1 WO2023123756 A1 WO 2023123756A1
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emitting element
semiconductor light
side wall
sidewall
layer
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PCT/CN2022/087897
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English (en)
French (fr)
Inventor
赵洋
宋林青
廖汉忠
芦玲
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淮安澳洋顺昌光电技术有限公司
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Publication of WO2023123756A1 publication Critical patent/WO2023123756A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/20—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/20—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate
    • H01L33/22—Roughened surfaces, e.g. at the interface between epitaxial layers

Definitions

  • the present disclosure relates to the field of semiconductor manufacturing, in particular, to a semiconductor light-emitting element, a preparation method thereof, and an LED chip.
  • LEDs semiconductor light-emitting elements
  • Semiconductor light-emitting elements have the advantages of small size, high brightness, and low energy consumption, and are widely used in lighting, display, and vehicle applications.
  • the side wall of the component is generally at a right angle to the light emitting surface of the component.
  • This single side wall structure will cause a large part of the light path reflected from the inside of the component to the side wall to be fully reflected back to the inside of the component, making the light emission of the component The effect is greatly reduced.
  • the sidewall structure of the semiconductor light emitting element in the prior art often has some disadvantages. For example, there are often concave grooves on the surface of the substrate, which easily leads to impurities remaining in the grooves, absorbing light and heat, thereby affecting the light output effect.
  • the present disclosure provides a semiconductor light-emitting element, including a patterned substrate, and an N-type semiconductor layer, a light-emitting layer, and a P-type semiconductor layer sequentially stacked on the patterned substrate;
  • the surface of the patterned substrate is provided with a patterned structure
  • the P-type semiconductor layer, the light-emitting layer and the N-type semiconductor layer form a sidewall structure
  • the sidewalls of the P-type semiconductor layer, the light-emitting layer and part of the N-type semiconductor layer constitute the first sidewall
  • the sidewalls of the N-type semiconductor layer other than the first sidewalls are second sidewalls
  • the step surface exposing the patterned structure between the second sidewall and the patterned substrate is a first step surface
  • the sidewall of the patterned substrate is a third sidewall.
  • the included angle between the first side wall and the second side wall is 10°-180°.
  • the included angle between the second side wall and the first stepped surface is 20°-70° or 110°-160°.
  • the width of the first stepped surface is not greater than 50% of the overall width of the semiconductor light emitting element.
  • a second stepped surface is formed on the N-type semiconductor layer at the junction of the first sidewall and the second sidewall.
  • the width of the second stepped surface is 0.01-10 ⁇ m.
  • the included angle between the first side wall and the second stepped surface is 10°-170°.
  • the second sidewall is planar or non-planar.
  • the second side wall when the second side wall is non-planar, the second side wall includes a first branch wall and a second branch wall, and the first branch wall is connected to the second stepped surface, so The second branch wall is connected to the patterned substrate.
  • the included angle between the first branch wall and the second branch wall is 10° ⁇ 180°.
  • the angle between the first branch wall and the first step surface, the angle between the first side wall and the first step surface, and the second branch The included angles between the wall and the first step surface are all different.
  • a third branch wall is further provided between the first branch wall and the second branch wall.
  • the included angle between the third branch wall and the first stepped surface is no greater than 90°.
  • the included angle between the third branch wall and the second branch wall is 90-180°.
  • the angle between the third branch wall and the first step surface, the angle between the first branch wall and the first step surface, and the second branch wall are all different.
  • the intersection of the first stepped surface and the third side wall further includes a stepped structure, the stepped surface of the stepped structure is a third stepped surface, and the third stepped surface is the first stepped surface.
  • the included angle between the fourth side wall and the third stepped surface is 90°-170°.
  • the surface of the fourth side wall has a raised patterned structure.
  • the height of the patterned structure on the surface of the first stepped surface is greater than the height of the patterned structure on the surface of the third stepped surface.
  • the shape of the patterned structure on the surface of the first stepped surface, the third stepped surface, and the fourth side wall includes a combination of stacked mesa and cones, a cone, and a cone At least one of solid, yurt-shaped and flat-shaped structures.
  • the cone in the combination of the platform and the cone, is arranged on the top of the platform, and the radius of the bottom surface of the cone is not greater than the radius of the upper surface of the platform.
  • the material of the mesa is sapphire, and the material of the cone is SiO 2 .
  • the preparation method of the semiconductor light-emitting element includes the following steps:
  • step (c) Etching the sidewalls of the N-type semiconductor layer obtained in step (b) except for the first sidewalls to obtain second sidewalls; wherein, the depth of the etching is to expose For the patterned substrate, the exposed step of the patterned substrate is a first stepped surface;
  • step (d) Cutting the sidewall of the patterned substrate of the semiconductor light-emitting element obtained in step (c), to obtain a third sidewall.
  • the etching method includes plasma etching and/or wet etching.
  • the cutting method includes stealth cutting technology and cleaving technology.
  • step (b) and/or step (c) during the etching process, two adjacent sides of the semiconductor light-emitting element are etched simultaneously, and two adjacent sides The etch rate is different during etching to obtain a sidewall structure with a first branch wall and a second branch wall, or a sidewall structure with a third branch wall.
  • each side of the semiconductor light emitting element is etched sequentially, so that each of the semiconductor light emitting element
  • the shapes of the sidewalls formed after the strip edge etching are the same or different.
  • An LED chip including the semiconductor light-emitting element, the semiconductor light-emitting element also includes a current blocking layer, a current spreading layer, an insulating layer, a P-type electrode and an N-type electrode;
  • the insulating layer does not cover or at least partially covers the second side wall, and/or the insulating layer does not cover or at least partially covers the first stepped surface.
  • FIG. 1 is a schematic structural view of the sidewall of a semiconductor light emitting element provided by the present disclosure
  • FIG. 2 is a schematic structural view of another side wall of the semiconductor light emitting element provided by the present disclosure.
  • FIG. 3 is a schematic structural view of another side wall of the semiconductor light emitting element provided by the present disclosure.
  • FIG. 4 is a schematic structural view of the sidewall including the second stepped surface of the semiconductor light emitting element provided by the present disclosure
  • FIG. 5 is a schematic structural view of another side wall including a second stepped surface of the semiconductor light emitting element provided by the present disclosure
  • FIG. 6 is a schematic structural view of the sidewalls of the semiconductor light-emitting element provided by the present disclosure, including the first branch wall and the second branch wall;
  • FIG. 7 is a schematic structural view of the sidewall including the third stepped surface of the semiconductor light emitting element provided by the present disclosure.
  • FIG. 8 is a schematic structural view of another side wall including a third stepped surface of the semiconductor light emitting element provided by the present disclosure.
  • FIG. 9 is a schematic structural view of another sidewall including a third stepped surface of the semiconductor light emitting element provided by the present disclosure.
  • FIG. 10 is a schematic structural view of yet another sidewall including a third stepped surface of the semiconductor light emitting element provided by the present disclosure
  • Fig. 11 is a schematic structural view of the sidewalls of the semiconductor light emitting element provided by the present disclosure, including the third stepped surface, the first branch wall and the second branch wall;
  • Fig. 12 is a schematic structural view of a semiconductor light-emitting element provided by the present disclosure with an angle between the first branch wall and the second branch wall greater than 90°;
  • FIG. 13 is a schematic structural view of a semiconductor light emitting element with a third branch wall provided by the present disclosure.
  • FIG. 14 is a topography diagram of a patterned substrate of a semiconductor light emitting element provided by the present disclosure.
  • Fig. 16 is a top view of a semiconductor light emitting element provided by the present disclosure.
  • FIG. 17 is a schematic structural diagram of the LED chip provided by the present disclosure in the X direction;
  • FIG. 18 is a schematic structural diagram of the LED chip provided by the present disclosure in the Y direction;
  • FIG. 19 is another structural schematic diagram of the LED chip provided by the present disclosure in the X direction;
  • FIG. 20 is another structural schematic diagram of the LED chip provided by the present disclosure in the Y direction;
  • Fig. 21 is another schematic structural diagram of the LED chip provided by the present disclosure in the X direction;
  • Fig. 22 is another structural schematic diagram of the LED chip provided by the present disclosure in the Y direction;
  • Fig. 23 is another structural schematic diagram of the LED chip provided by the present disclosure in the X direction;
  • Fig. 24 is another structural schematic diagram of the LED chip provided by the present disclosure in the Y direction;
  • Fig. 25 is another structural schematic diagram of the LED chip provided by the present disclosure in the X direction;
  • FIG. 26 is a schematic structural view of another sidewall of the semiconductor light emitting element provided by the present disclosure.
  • the present disclosure provides a semiconductor light-emitting element.
  • the semiconductor light-emitting element includes a patterned substrate 1, and an N-type semiconductor layer 3, a light-emitting layer 4, and a P-type semiconductor layer sequentially stacked on the patterned substrate 1.
  • patterned structure 2 is provided on the surface of patterned substrate 1; P-type semiconductor layer 5, light-emitting layer 4 and N-type semiconductor layer 3 form a sidewall structure; wherein, P-type semiconductor layer 5, light-emitting layer 4 and part of the sidewalls of the N-type semiconductor layer 3 form the first sidewall 101; the sidewalls of the N-type semiconductor layer 3 other than the first sidewall 101 are the second sidewall 102; the second sidewall 102 and the patterned substrate
  • the step surface where the patterned structure 2 is exposed between the bottom 1 is the first step surface 201 ; the sidewall of the patterned substrate 1 is the third sidewall 103 .
  • the light extraction efficiency of the semiconductor light emitting element can be improved.
  • the sides of the first sidewall 101 and the second sidewall 102 are on a straight line, and the first sidewall 101 and the second sidewall 102 form a whole with an inverted trapezoidal structure.
  • the sides of the first sidewall 101 and the second sidewall 102 are on a straight line, and the first sidewall 101 and the second sidewall 102 form a whole with a regular trapezoidal structure.
  • the angle between the first side wall 101 and the second side wall 102 is 10°-180°, including but not limited to 20°, 30°, 40°, 50°, 60°, 70°, The point value of any one of 80°, 90°, 100°, 110°, 120°, 130°, 140°, 150°, 160°, 170° or the range value between any two.
  • the included angle between the first side wall 101 and the second side wall 102 within the above range can reduce the photometric angle and increase the surface light extraction efficiency.
  • the included angle between the first side wall 101 and the second side wall 102 is 180°, and the first side wall 101 and the second side wall 102 form an inverted trapezoidal structure.
  • the included angle between the first side wall 101 and the second side wall 102 is also 180°, but the first side wall 101 and the second side wall 102 form a regular trapezoidal structure.
  • the included angle between the first side wall 101 and the second side wall 102 is less than 90°.
  • the included angle between the second side wall 102 and the first stepped surface 201 is 20°-70° (including but not limited to 25°, 30°, 35°, 40°, 45°, 50°, any one of 55°, 60° or the range value between any two) or 110° ⁇ 160° (including but not limited to 115°, 120°, 125°, 130°, 135°, 140° °, 145°, 150°, 155°, or any range between the two).
  • the embodiment shown in Figure 1 and Figure 2 is that the angle between the second side wall 102 and the first stepped surface 201 is 20° to 70°; the embodiment shown in Figure 3 is the second The included angle between the side wall 102 and the first stepped surface 201 is 110° ⁇ 160°.
  • Adopting the included angle in the above range is beneficial to increase the light extraction efficiency of the semiconductor light emitting element.
  • the width of the first stepped surface 201 is not greater than 50% of the overall width of the semiconductor light emitting element. Setting the width of the first stepped surface 201 within the above-mentioned range is beneficial to ensuring light emission from the sidewall of the semiconductor light-emitting element and ensuring light emission from the front side thereof.
  • a second stepped surface 202 is formed on the N-type semiconductor layer.
  • the provision of the second stepped surface 202 can increase the light emitting area of the side wall of the semiconductor light emitting element.
  • the width of the second stepped surface is 0.01-10 ⁇ m, including but not limited to 0.02 ⁇ m, 0.04 ⁇ m, 0.05 ⁇ m, 0.07 ⁇ m, 0.09 ⁇ m, 0.1 ⁇ m, 0.15 ⁇ m, 0.3 ⁇ m, 0.5 ⁇ m, 0.8 ⁇ m, A point value of any one of 1 ⁇ m, 2 ⁇ m, 3 ⁇ m, 4 ⁇ m, 5 ⁇ m, 6 ⁇ m, 7 ⁇ m, 8 ⁇ m, and 9 ⁇ m or a range value between any two.
  • the angle between the first side wall 101 and the second stepped surface 202 is 10°-170°, including but not limited to 20°, 30°, 40°, 50°, 60°, 70°, The point value of any one of 80°, 90°, 100°, 110°, 120°, 130°, 140°, 150°, 160° or the range value between any two.
  • the second sidewall 102 is planar or non-planar.
  • the second side wall 102 when the second side wall 102 is non-planar, the second side wall 102 includes a first branch wall 1021 and a second branch wall 1022, and the first branch wall 1021 and the second step surface 202, and the second branch wall is connected to the patterned substrate 1.
  • the first branch wall 1021 and the second branch wall 1022 By arranging the first branch wall 1021 and the second branch wall 1022, the light emitting area of the side wall can be increased.
  • the angle between the first branch wall 1021 and the second branch wall 1022 is 10°-180°, including but not limited to 15°, 20°, 25°, 30°, 35°, 40°, A point value of any one of 45°, 50°, 55°, 60°, 80°, 90°, 100°, 120°, 140°, 160°, 170° or a range value between any two.
  • the angle between the first branch wall 1021 and the second branch wall 1022 is less than 90°. As shown in FIG. 12 , the angle between the first branch wall 1021 and the second branch wall 1022 is larger than 90°.
  • the angle between the first branch wall 1021 and the first step surface 201, the angle between the first side wall 101 and the first step surface 201, and the angle between the second branch wall 1022 and the first step are all different.
  • a third branch wall 1023 is further provided between the first branch wall 1021 and the second branch wall 1022 ; as shown in FIG. 13 .
  • the third branch wall 1023 By providing the third branch wall 1023, the light emitting area of the side wall can be further increased. At the same time, it can also prevent chipping or splitting caused by the angle between the first branch wall 1021 and the second branch wall 1022 being too small.
  • the angle between the third branch wall 1023 and the first stepped surface 201 is not greater than 90°;
  • the angle between the third branch wall 1023 and the second branch wall 1022 is 90-180°;
  • the angle between the third branch wall 1023 and the first step surface 201, the angle between the first branch wall 1021 and the first step surface 201, and the angle between the second branch wall 1022 and the first step are all different.
  • the intersection of the first stepped surface 201 and the third side wall 103 further includes a stepped structure, and the stepped surface of the stepped structure is the second Three stepped surfaces 203, the third stepped surface 203 is the bare patterned structure 2 formed after the first stepped surface 201 is etched again, the connection between the third stepped surface 203 and the first stepped surface 201 forms a fourth side wall 104 .
  • the included angle between the fourth side wall 104 and the third stepped surface 203 is 90°-170°, including but not limited to 95°, 100°, 110°, 120°, 130°, 140°, A point value of either 150°, 160° or any range value between the two.
  • the surface of the fourth sidewall has a raised patterned structure.
  • the height of the patterned structure on the surface of the first stepped surface is greater than the height of the patterned structure on the surface of the third stepped surface.
  • the shape of the patterned structure is a cone when it is not etched initially (that is, when each sidewall and each step is not formed).
  • the diameter of the bottom of the cone is 2-4 ⁇ m (2.5 ⁇ m, 3 ⁇ m or 3.5 ⁇ m can also be selected), and the height is 2-3 ⁇ m (2.5 ⁇ m can also be selected).
  • the shape of the patterned structure on the surface of the first stepped surface, the third stepped surface, and the fourth side wall includes a combination of stacked mesa and cones, a cone, and a cone. At least one of solid, yurt-shaped and flat-shaped structures. This can reduce light refraction.
  • FIG. 15 it is an SEM image of various shapes of the patterned structure on the surface of the first stepped surface, the third stepped surface and the surface of the fourth side wall.
  • the cone in the combination of the mesa and the cone, the cone is arranged on the top of the mesa, and the radius of the bottom surface of the cone is not greater than the radius of the upper surface of the mesa.
  • the mesa in the combination of the mesa and the cone, the mesa is made of sapphire, and the cone is made of SiO 2 .
  • the shape of the patterned structure on the surface of the patterned substrate is conical. When it is etched, the shape of the patterned structure will change and become a combination of a platform and a cone, a cone, a cone, At least one of yurt-shaped and flat-shaped structures.
  • the patterned structure of the surface of the third stepped surface may be the same as that of the first stepped surface, or may be flatter than that of the first stepped surface.
  • the different topography formed by etching can reduce light refraction.
  • the present disclosure also provides a method for preparing the above semiconductor light-emitting element, including the following steps:
  • step (c) Etching the sidewalls of the N-type semiconductor layer obtained in step (b) except the first sidewalls to obtain the second sidewalls; wherein, the depth of etching is to expose the patterned substrate, and the exposed The step of the patterned substrate is the first step surface;
  • step (d) Cutting the sidewall of the patterned substrate of the semiconductor light-emitting element obtained in step (c), to obtain a third sidewall.
  • the etching method includes plasma etching and/or wet etching.
  • the cutting method in step (d), includes stealth cutting technology and cleaving technology.
  • the present disclosure can effectively solve the problems of rough side walls, damaged substrates, and residual impurities caused by the surface cutting technology in the prior art.
  • the technology of etching the N-type semiconductor layer 3 with a high-temperature mixed acid solution can change the light-emitting angle of the sidewall of the semiconductor light-emitting element, further increase the light-emitting efficiency of the sidewall of the semiconductor light-emitting element, and effectively control the width of the cutting line.
  • the etching depth of the first sidewall 101 is smaller than the etching depth of the second sidewall 102 . In some embodiments, the etching depth of the first sidewall 101 is 1 ⁇ 6 ⁇ m (2 ⁇ m, 3 ⁇ m, 4 ⁇ m or 5 ⁇ m can also be selected).
  • step (b) before etching, the second barrier layer and the first barrier layer are sequentially formed on the surface of the semiconductor light emitting element.
  • the first barrier layer is formed by photoresist through exposure, development and baking.
  • the material used for the second barrier layer includes one of metal, metal oxide and silicide. Then the P-type semiconductor layer, the light-emitting layer and part of the N-type semiconductor layer are etched to obtain the first sidewall.
  • step (c) specifically includes:
  • a second barrier layer and a first barrier layer are formed in sequence again, and the first barrier layer is exposed, developed and baked, and then chemically etched (ie, wet etching) ) pattern the second barrier layer to expose part of the N-type semiconductor layer 3, and then use plasma bombardment technology (ie, plasma etching technology) to etch the exposed N-type semiconductor layer 3 until the etching depth is exposed. Thinning the substrate 1 to obtain the processed semiconductor light emitting element.
  • the semiconductor light-emitting element after the above treatment is placed in a quartz basket, and then the quartz basket is placed in a low-temperature acid solution for soaking and preheating; the quartz basket is then corroded in a high-temperature acid solution to make the exposed N Type semiconductor layer 3 is eroded to the inside of the semiconductor light-emitting element to form a second side wall; then the quartz basket is taken out and placed in a low-temperature acid solution to cool; after cooling, the corroded semiconductor light-emitting element is washed with water, and then cleaned The semiconductor light-emitting element is placed in an acetone solution to remove the first barrier layer on its surface; finally, the second barrier layer on the surface of the semiconductor light-emitting element is removed with a buffered oxide etching solution, and cleaned with water to obtain the second side wall and the first step surface.
  • the acid solution is a mixed solution of concentrated phosphoric acid and concentrated sulfuric acid with a volume ratio of 1 to 3:1 (or 2:1).
  • the temperature of the low-temperature acid solution is 80-150°C (90°C, 100°C, 110°C, 120°C, 130°C or 140°C can also be selected), and the soaking preheating time is 100-500s (it can also be Choose from 150s, 200s, 250s, 300s, 350s, 400s, or 450s).
  • the temperature of the high-temperature acid solution is 150-300°C (160°C, 170°C, 180°C, 200°C, 250°C or 280°C can also be selected), and the corrosion time is 300-800s (350s can also be selected , 400s, 450s, 500s, 550s, 600s, 650s, 700s, or 750s).
  • step (c) in the process of etching to obtain the second sidewall 102 and the first stepped surface 201, it also includes that the exposed first stepped surface 201 of the patterned substrate 1 continues downward
  • the step of performing etching that is, along the direction of the patterned substrate 1 ) to obtain the third stepped surface 203 .
  • the etching method includes chemical etching and/or plasma etching.
  • FIG. 7 it can be seen that there is a certain height difference between the first stepped surface 201 and the third stepped surface 203 .
  • the appearance of the patterned substrate 1 on the surface of the third step surface 203 is changed under the action of etching.
  • the appearance of the patterned structure 2 on the surface of the patterned substrate 1 can be frustum-shaped, yurt-shaped, One or more of several forms of platform (refer to Figures 12 and 13).
  • the material of the N-type semiconductor layer 3 and/or the P-type semiconductor layer 5 includes but not limited to at least one of GaN, GaAs, GaP, PbS and silicide.
  • the preparation method of the N-type semiconductor layer 3 and/or the P-type semiconductor layer 5 includes but not limited to at least one of CVD (Chemical Vapor Deposition) and PVD (Physical Vapor Deposition).
  • step (b) and/or step (c) during the etching process, the adjacent two sides of the semiconductor light emitting element are etched simultaneously, and the adjacent two sides are etched during the etching process.
  • the etch rates are different in order to obtain a sidewall structure with a first branch wall and a second branch wall, or, alternatively, a sidewall structure with a third branch wall.
  • the shape of the semiconductor light emitting element is square. Assuming that the directions along the two sides perpendicular to each other are the X direction and the Y direction respectively, due to the preferred orientation of semiconductor material crystals during the growth process, there may be different epitaxial crystallographic directions along the X direction and the Y direction of the semiconductor light emitting element. Therefore, during the etching process of the N-type semiconductor layer 3 and the P-type semiconductor layer 5 of the semiconductor light emitting element, there are different etching rates in the X direction and the Y direction.
  • the semiconductor light-emitting element has different corrosion rates in the X direction and the Y direction, when the corrosion rate of one side is smaller than that of the other side, there will be two stages (that is, two branch walls) or three stages on the side with a slower corrosion rate.
  • the side wall structure of the angle that is, having three branch walls
  • that is, the second side wall 102 including the first branch wall 1021 and the second branch wall 1022 its appearance refers to FIG. 6; or, as shown in FIG.
  • the side wall structure of three branch walls 1023 refers to FIG. 6; or, as shown in FIG.
  • each side of the semiconductor light emitting element is etched sequentially, so that each side of the semiconductor light emitting element is etched to form
  • the topography of the sidewalls is the same or different. That is, one or both of those shown in Figures 1 to 13.
  • the appearance and shape of the side walls of the two adjacent sides are different, and the amount of light output from the two boundary side walls can be controlled respectively, so that the light pattern of the light output from the semiconductor light-emitting element can be controlled.
  • each side of the semiconductor light-emitting element before etching, use a photoresist or an oxide mask to first use a photoresist or an oxide mask to etch the other sides that are not to be etched (that is, except for those that are etched). Edges other than the edge of the eclipse) are masked.
  • the present disclosure also provides an LED chip, including the semiconductor light-emitting element as above, and the semiconductor light-emitting element also includes a current blocking layer 11, a current spreading layer 12, an insulating layer 13, a P-type electrode 14, and an N-type electrode 15; wherein, the insulating layer 13 does not cover or at least partially covers the second side wall 102 , and/or the insulating layer 13 does not cover or at least partially covers the first stepped surface 201 .
  • the first stepped surface 201 also refers to the stepped surface including the third stepped surface 203 , that is, the insulating layer 13 does not cover or at least partially cover the third stepped surface 203 .
  • the directions perpendicular to each other along the two sides of the semiconductor light emitting element are the X direction and the Y direction.
  • the insulating layer 13 does not cover the second sidewall 102 , the insulating layer 13 partially covers the first stepped surface 201 , and completely covers the third stepped surface 203 . In this way, the luminosity angle of the cladding is larger, and the side wall emits more light.
  • the insulating layer 13 completely covers the second sidewall 102 , the insulating layer 13 completely covers the first stepped surface 201 , and completely covers the third stepped surface 203 .
  • this cladding method the light reflection of the side wall is enhanced, more light is emitted from the front, and the luminosity angle is smaller.
  • the insulating layer 13 partially covers the second side wall 102 , specifically covers the first branch wall 1021 entirely, and does not cover the second branch wall 1022 .
  • the insulating layer 13 does not cover the first stepped surface 201 , but completely covers the third stepped surface 203 .
  • This kind of cladding method has a larger luminosity angle, and more light is emitted from the side wall.
  • the insulating layer 13 completely covers the first branch wall 1021 and the second branch wall 1022 .
  • the insulating layer 13 completely covers the first stepped surface 201 and completely covers the third stepped surface 203 . In this way, the enveloping luminosity angle is smaller and more light is emitted from the front.
  • the LED chip further includes a second insulating layer.
  • the present disclosure also provides a method for preparing the above LED chip, comprising the following steps:
  • first side wall 101, the second side wall 102 and the third side wall 103 on the semiconductor light-emitting element, and then form the current blocking layer 11, the current spreading layer 12, the P-type electrode 14, the N-type electrode 15 and the insulating layer 13 .
  • first sidewall 101 and the second stepped surface 202 are formed on the semiconductor light emitting element, then the current blocking layer 11 and the current spreading layer 12 are formed, the second sidewall 102 and the third sidewall 103 are formed, and finally the P-type electrode 14, N-type electrode 15 and insulating layer 13.
  • the present disclosure provides a semiconductor light emitting element, a manufacturing method thereof, and an LED chip.
  • the semiconductor light emitting element can increase light output from the side wall, has controllable angle and high light output efficiency.
  • the preparation method can increase the light extraction efficiency of the semiconductor light emitting element.

Abstract

本公开涉及半导体制造领域，具体而言，涉及一种半导体发光元件及其制备方法、LED芯片。半导体发光元件包括图形化衬底，N型半导体层、发光层和P型半导体层；P型半导体层、发光层和部分N型半导体层的侧壁组成了第一侧壁；除第一侧壁以外的N型半导体层的侧壁为第二侧壁；第二侧壁与图形化衬底之间裸露出图形化结构的台阶面为第一台阶面；图形化衬底的侧壁为第三侧壁。通过设置多层侧壁结构，能够提高半导体发光元件的出光效率。

Description

一种半导体发光元件及其制备方法、LED芯片
相关申请的交叉引用
本申请要求于2021年12月31日提交中国专利局的申请号为2021116821126、名称为“一种半导体发光元件及其制备方法、LED芯片”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本公开涉及半导体制造领域，具体而言，涉及一种半导体发光元件及其制备方法、LED芯片。
背景技术
随着半导体技术的更新迭代，节能环保、高寿命、高效率的半导体发光元件(LED)得到了广泛应用。半导体发光元件具有体积小、亮度高，能耗低等优点，被广泛应用于照明、显示以及车载等领域。
虽然半导体发光元件的制造技术已经相当成熟，但是在元件的应用过程中，仍然存在较多的问题，其中最主要的问题之一就是元件的表面和侧壁的出光问题。
在现有技术中，元件侧壁与元件的出光表面一般为垂直的直角，这种单一的侧壁结构会导致元件内部反射到侧壁的光路一大部分全反射回元件内部，使得元件的发光效果大打折扣。
并且，现有技术中的半导体发光元件的侧壁结构往往存在一些弊端。例如，基板表面往往会有呈凹陷形状的沟槽，这容易导致杂质残留在沟槽中，吸光吸热，从而影响出光效果。
因此，如何克服现有技术中的半导体发光元件的侧壁结构存在的弊端，以增加侧壁出光，提高半导体发光元件的出光效率是急需解决的技术问题。
发明内容
本公开提供一种半导体发光元件，包括图形化衬底，以及在所述图形化衬底上依次层叠设置的N型半导体层、发光层和P型半导体层；
所述图形化衬底的表面设置有图形化结构；
所述P型半导体层、所述发光层和所述N型半导体层形成了侧壁结构；
其中，所述P型半导体层、所述发光层和部分所述N型半导体层的侧壁组成了第一侧壁；
除所述第一侧壁以外的所述N型半导体层的侧壁为第二侧壁；
所述第二侧壁与所述图形化衬底之间裸露出所述图形化结构的台阶面为第一台阶面；
所述图形化衬底的侧壁为第三侧壁。
一些实施方式中，所述第一侧壁与所述第二侧壁之间的夹角为10°～180°。
一些实施方式中，所述第二侧壁与所述第一台阶面之间的夹角为20°～70°或110°～160°。
一些实施方式中，所述第一台阶面的宽度不大于所述半导体发光元件整体宽度的50％。
一些实施方式中，所述第一侧壁与所述第二侧壁的连接处，在所述N型半导体层上形成第二台阶面。
一些实施方式中，所述第二台阶面的宽度为0.01～10μm。
一些实施方式中，所述第一侧壁与所述第二台阶面之间的夹角为10°～170°。
一些实施方式中，所述第二侧壁为平面或非平面。
一些实施方式中，当所述第二侧壁为非平面时，所述第二侧壁包括第一支壁和第二支壁，所述第一支壁与所述第二台阶面相连接，所述第二支壁与所述图形化衬底相连接。
一些实施方式中，所述第一支壁和所述第二支壁之间的夹角为10°～180°。
一些实施方式中，所述第一支壁与所述第一台阶面之间的夹角，所述第一侧壁与所述第一台阶面之间的夹角，以及，所述第二支壁与所述第一台阶面之间的夹角均不相同。
一些实施方式中，在所述第一支壁和所述第二支壁之间，还设置有第三支壁。
一些实施方式中，所述第三支壁与所述第一台阶面之间的夹角不大于90°。
一些实施方式中，所述第三支壁与所述第二支壁之间的夹角为90～180°。
一些实施方式中，所述第三支壁与所述第一台阶面之间的夹角，所述第一支壁与所述第一台阶面之间的夹角，以及，所述第二支壁与所述第一台阶面之间的夹角均不相同。
一些实施方式中，所述第一台阶面与所述第三侧壁的交汇处还包括一台阶结构，所述台阶结构的台阶面为第三台阶面，所述第三台阶面为所述第一台阶面经过再次刻蚀后形成的裸露的图形化结构，所述第三台阶面与所述第一台阶面之间的连接处形成了第四侧壁；
一些实施方式中，所述第四侧壁与所述第三台阶面之间的夹角为90°～170°。
一些实施方式中，所述第四侧壁的表面具有凸起的图形化结构。
一些实施方式中，所述第一台阶面表面的图形化结构的高度大于所述第三台阶面表面的图形化结构的高度。
一些实施方式中，所述第一台阶面、所述第三台阶面以及所述第四侧壁的表面的图形化结构的形状包括堆叠设置的台体和锥体的组合体、圆锥体、圆台体、蒙古包形和平坦形结构中的至少一种。
一些实施方式中，在所述台体和锥体的组合体中，所述锥体设置在所述台体的顶端，所述锥体的底面半径不大于所述台体的上表面的半径。
一些实施方式中，在所述台体和锥体的组合体中，所述台体的材质为蓝宝石，所述锥体的材质为SiO 2。
所述的半导体发光元件的制备方法，包括以下步骤：
(a)、提供一带有图形化结构的图形化衬底，并在所述图形化衬底的表面依次沉积N型半导体层、发光层和P型半导体层；
(b)、对所述P型半导体层、所述发光层和部分所述N型半导体层进行刻蚀，得到第一侧壁；
(c)、对步骤(b)得到的除所述第一侧壁以外的所述N型半导体层的侧壁进行刻蚀，得到第二侧壁；其中，所述刻蚀的深度至裸露出所述图形化衬底，所述裸露的所述图形化衬底的台阶为第一台阶面；
(d)、对步骤(c)得到的半导体发光元件的所述图形化衬底的侧壁进行切割，得到第三侧壁。
一些实施方式中，在步骤(b)和/或步骤(c)中，所述刻蚀的方法包括等离子刻蚀和/或湿法刻蚀。
一些实施方式中，所述切割的方法包括隐形切割技术和劈裂技术。
一些实施方式中，步骤(b)和/或步骤(c)中，在所述刻蚀的过程中，同时对所述半导体发光元件的相邻的两条边进行刻蚀，相邻两条边在刻蚀过程中的腐蚀速率不同，以得到具有第一支壁和第二支壁的侧壁结构，或者，具有第三支壁的侧壁结构。
一些实施方式中，步骤(b)和/或步骤(c)中，在所述刻蚀的过程中，依次对所述半导体发光元件的各条边进行刻蚀，以使所述半导体发光元件各条边刻蚀后形成的侧壁的形貌相同或者不同。
一些实施方式中，所述依次对所述半导体发光元件的各条边进行刻蚀的过程中，在刻蚀之前，先采用光刻胶或氧化物掩膜对不进行刻蚀的其他条边进行掩盖。
一种LED芯片，包括所述的半导体发光元件，所述半导体发光元件还包括电流阻挡层、电流扩展层、绝缘层、P型电极和N型电极；
其中，所述绝缘层不包覆或者至少部分包覆所述第二侧壁，和/或，所述绝缘层不包覆或者至少部分包覆所述第一台阶面。
附图说明
为了更清楚地说明本公开实施方式的技术方案，下面将对实施方式中所需要使用的附图作简单地介绍，应当理解，以下附图仅示例地表征本公开的实施方式，图中尺寸比例与实施方式的真实比例并不能直接对应，同时以下附图仅示出了本公开的某些实施方式，因此不应被看作是对范围的限定。
图1为本公开提供的半导体发光元件的侧壁的结构示意图；
图2为本公开提供的半导体发光元件的另一侧壁的结构示意图；
图3为本公开提供的半导体发光元件的又一侧壁的结构示意图；
图4为本公开提供的半导体发光元件的包括第二台阶面的侧壁的结构示意图；
图5为本公开提供的半导体发光元件的另一包括第二台阶面的侧壁的结构示意图；
图6为本公开提供的半导体发光元件的包括第一支壁和第二支壁的侧壁的结构示意图；
图7为本公开提供的半导体发光元件的包括第三台阶面的侧壁的结构示意图；
图8为本公开提供的半导体发光元件的又一包括第三台阶面的侧壁的结构示意图；
图9为本公开提供的半导体发光元件的另一包括第三台阶面的侧壁的结构示意图；
图10为本公开提供的半导体发光元件的再一包括第三台阶面的侧壁的结构示意图；
图11为本公开提供的半导体发光元件的包括第三台阶面、第一支壁和第二支壁的侧壁的结构示意图；
图12为本公开提供的第一支壁和第二支壁之间的夹角大于90°的半导体发光元件的结构示意图；
图13为本公开提供的具有第三支壁的半导体发光元件的结构示意图；
图14为本公开提供的半导体发光元件的图形化衬底的形貌图；
图15为本公开提供的半导体发光元件的图形化衬底的SEM图；
图16为本公开提供的半导体发光元件的俯视图；
图17为本公开提供的LED芯片在X方向的结构示意图；
图18为本公开提供的LED芯片在Y方向的结构示意图；
图19为本公开提供的LED芯片在X方向的另一结构示意图；
图20为本公开提供的LED芯片在Y方向的另一结构示意图；
图21为本公开提供的LED芯片在X方向的又一结构示意图；
图22为本公开提供的LED芯片在Y方向的又一结构示意图；
图23为本公开提供的LED芯片在X方向的再一结构示意图；
图24为本公开提供的LED芯片在Y方向的再一结构示意图；
图25为本公开提供的LED芯片在X方向的再一结构示意图；
图26为本公开提供的半导体发光元件的再一侧壁的结构示意图。
附图标记：
1-图形化衬底；          2-图形化结构；          3-N型半导体层；
4-发光层；              5-P型半导体层；
101-第一侧壁；          102-第二侧壁；          103-第三侧壁；
104-第四侧壁；
1021-第一支壁；         1022-第二支壁；         1023-第三支壁；
201-第一台阶面；        202-第二台阶面；        203-第三台阶面；
11-电流阻挡层；         12-电流扩展层；         13-绝缘层；
14-P型电极；            15-N型电极。
具体实施方式
发明内容中实施方式的优点将会在下面的说明书实施方式部分阐明，一部分根据说明书是显而易见的，或者可以通过本公开实施例的部分实施例而获得。
下面结合附图并通过一些实施方式来进一步说明本公开的技术方案。
本公开提供了一种半导体发光元件，如图1所示，半导体发光元件包括图形化衬底1，以及在图形化衬底1上依次层叠设置的N型半导体层3、发光层4和P型半导体层5；图形化衬底1的表面设置有图形化结构2；P型半导体层5、发光层4和N型半导体层3形成了侧壁结构；其中，P型半导体层5、发光层4和部分N型半导体层3的侧壁组成了第一侧壁101；除第一侧壁101以外的N型半导体层3的侧壁为第二侧壁102；第二侧壁102与图形化衬底1之间裸露出图形化结构2的台阶面为第一台阶面201；图形化衬底1的侧壁为第三侧壁103。
本公开通过设置包括第一侧壁101、第二侧壁102和第三侧壁103的多层侧壁结构，能够提高半导体发光元件的出光效率。
一些实施方式中，如图2所示，第一侧壁101和第二侧壁102的边在一条直线上，第一侧壁101和第二侧壁102形成一个呈倒梯形结构的整体。
一些实施方式中，如图3所示，第一侧壁101和第二侧壁102的边在一条直线上，第一侧壁101和第二侧壁102形成一个呈正梯形结构的整体。
一些实施方式中，第一侧壁101与第二侧壁102之间的夹角为10°～180°，包括但不限于20°、30°、40°、50°、60°、70°、80°、90°、100°、110°、120°、130°、140°、150°、160°、170°中的任意一者的点值或任意两者之间的范围值。
将第一侧壁101与第二侧壁102之间的夹角设置在上述范围内，可以减小光度角，增大表面出光效率。其中，如图2所示，第一侧壁101与第二侧壁102之间的夹角即为180°，第一侧壁101与第二侧壁102形成倒梯形结构。如图3所示，第一侧壁101与第二侧壁102之间的夹角也为180°，但第一侧壁101与第二侧壁102形成正梯形结构。如图26所示，第一侧壁101与第二侧壁102之间的夹角为小于90°。
一些实施方式中，第二侧壁102与第一台阶面201之间的夹角为20°～70°(包括但不限于25°、30°、35°、40°、45°、50°、55°、60°中的任意一者的点值或任意两者之间的范围值)或110°～160°(包括但不限于115°、120°、125°、130°、135°、140°、145°、150°、155°中的任意一者的点值或任意两者之间的范围值)。
如图1和图2所示的实施方式，即为第二侧壁102与第一台阶面201之间的夹角为20°～70°；如图3所示的实施方式，即为第二侧壁102与第一台阶面201之间的夹角为110°～160°。
采用上述范围的夹角，有利于增大半导体发光元件的出光效率。
一些实施方式中，第一台阶面201的宽度不大于半导体发光元件整体宽度的50％。将第一台阶面201的宽度设置在上述范围内，有利于在保证半导体发光元件的侧壁出光的同时，也保证其正面出光。
在一实施方式中，如图4和图5所示，第一侧壁101与第二侧壁102的连接处，在N型半导体层上形成第二台阶面202。设置第二台阶面202，能够增大半导体发光元件的侧壁的出光面积。
一些实施方式中，第二台阶面的宽度为0.01～10μm，包括但不限于0.02μm、0.04μm、0.05μm、0.07μm、0.09μm、0.1μm、0.15μm、0.3μm、0.5μm、0.8μm、1μm、2μm、3μm、4μm、5μm、6μm、7μm、8μm、9μm中的任意一者的点值或任意两者之间的范围值。
一些实施方式中，第一侧壁101与第二台阶面202之间的夹角为10°～170°，包括但 不限于20°、30°、40°、50°、60°、70°、80°、90°、100°、110°、120°、130°、140°、150°、160°中的任意一者的点值或任意两者之间的范围值。
一些实施方式中，第二侧壁102为平面或非平面。
一些实施方式中，如图6所示，当第二侧壁102为非平面时，第二侧壁102包括第一支壁1021和第二支壁1022，第一支壁1021与第二台阶面202相连接，第二支壁与图形化衬底1相连接。通过设置第一支壁1021和第二支壁1022，能够增大侧壁出光面积。
一些实施方式中，第一支壁1021和第二支壁1022之间的夹角为10°～180°，包括但不限于15°、20°、25°、30°、35°、40°、45°、50°、55°、60°、80°、90°、100°、120°、140°、160°、170°中的任意一者的点值或任意两者之间的范围值。
如图11所示，第一支壁1021和第二支壁1022之间的夹角小于90°。如图12所示，第一支壁1021和第二支壁1022之间的夹角大于90°。
一些实施方式中，第一支壁1021与第一台阶面201之间的夹角，第一侧壁101与第一台阶面201之间的夹角，以及，第二支壁1022与第一台阶面201之间的夹角均不相同。
角度不同出光方向不同，上述将各个角度设置不同是为了侧壁能够多角度出光。一些实施方式中，在第一支壁1021和第二支壁1022之间，还设置有第三支壁1023；如图13所示。通过设置第三支壁1023，能够进一步增大侧壁出光面积。同时，还能够防止第一支壁1021和第二支壁1022之间角度过小而发生崩边或劈裂的现象。
一些实施方式中，第三支壁1023与第一台阶面201之间的夹角不大于90°；
一些实施方式中，第三支壁1023与第二支壁1022之间的夹角为90～180°；
一些实施方式中，第三支壁1023与第一台阶面201之间的夹角，第一支壁1021与第一台阶面201之间的夹角，以及，第二支壁1022与第一台阶面201之间的夹角均不相同。
一些实施方式中，如图7、图8、图9、图10和图11所示，第一台阶面201与第三侧壁103的交汇处还包括一台阶结构，台阶结构的台阶面为第三台阶面203，第三台阶面203为第一台阶面201经过再次刻蚀后形成的裸露的图形化结构2，第三台阶面203与第一台阶面201之间的连接处形成了第四侧壁104。
一些实施方式中，第四侧壁104与第三台阶面203之间的夹角为90°～170°，包括但 不限于95°、100°、110°、120°、130°、140°、150°、160°中的任意一者的点值或任意两者之间的范围值。
一些实施方式中，第四侧壁的表面具有凸起的图形化结构。
一些实施方式中，第一台阶面表面的图形化结构的高度大于第三台阶面表面的图形化结构的高度。
一些实施方式中，图形化结构最初未经刻蚀时(即未形成各个侧壁和各个台阶面时)的形状为圆锥体。一些实施方式中，圆锥体的底面直径为2～4μm(还可以选择2.5μm、3μm或3.5μm)，高为2～3μm(还可以选择2.5μm)。
一些实施方式中，如图14所示，第一台阶面、第三台阶面以及第四侧壁的表面的图形化结构的形状包括堆叠设置的台体和锥体的组合体、圆锥体、圆台体、蒙古包形和平坦形结构中的至少一种。这样能够减小光折射。
一些实施方式中，如图15所示，为第一台阶面、第三台阶面以及第四侧壁的表面的图形化结构的各种形状的SEM图。一些实施方式中，在台体和锥体的组合体中，锥体设置在台体的顶端，锥体的底面半径不大于台体的上表面的半径。一些实施方式中，在台体和锥体的组合体中，台体的材质为蓝宝石，锥体的材质为SiO 2。
图形化衬底的表面的图形化结构的形状为圆锥形，当对其进行刻蚀时，图形化结构的形状会发生改变，变为台体和锥体的组合体、圆锥体、圆台体、蒙古包形和平坦形结构中的至少一种。当半导体发光元件中存在第三台阶面时，第三台阶面表面的图形化结构可能与第一台阶面的结构相同，也可能相比于第一台阶面更为平坦。经过刻蚀形成的不同的形貌能够减小光折射。
本公开还提供了如上的半导体发光元件的制备方法，包括以下步骤：
(a)、提供一带有图形化结构的图形化衬底，并在图形化衬底的表面依次沉积N型半导体层、发光层和P型半导体层；
(b)、对P型半导体层、发光层和部分N型半导体层进行刻蚀，得到第一侧壁；
(c)、对步骤(b)得到的除第一侧壁以外的N型半导体层的侧壁进行刻蚀，得到第二侧壁；其中，刻蚀的深度至裸露出图形化衬底，裸露的图形化衬底的台阶为第一台阶面；
(d)、对步骤(c)得到的半导体发光元件的图形化衬底的侧壁进行切割，得到第三侧壁。
一些实施方式中，在步骤(b)和/或步骤(c)中，刻蚀的方法包括等离子刻蚀和/或湿法刻蚀。
一些实施方式中，在步骤(d)中，切割的方法包括隐形切割技术和劈裂技术。
本公开通过采用等离子刻蚀和湿法刻蚀，可有效解决现有技术中存在的表面切割技术对元件造成的侧壁粗糙不平滑、损伤基板以及杂质残留的问题，且湿法刻蚀中所采用的高温混酸溶液腐蚀N型半导体层3的技术可以改变半导体发光元件的侧壁的出光角度，进一步的增大半导体发光元件的侧壁的出光效率，同时有效的控制了切割道的宽度。
一些实施方式中，第一侧壁101的刻蚀深度小于第二侧壁102的刻蚀深度。一些实施方式中，第一侧壁101的刻蚀深度为1～6μm(还可以选择2μm、3μm、4μm或5μm)。
一些实施方式中，步骤(b)中，在刻蚀之前，先在半导体发光元件的表面依次形成第二阻挡层和第一阻挡层。其中，第一阻挡层采用光刻胶，通过曝光、显影、烘烤后形成。第二阻挡层所用的材料包括金属、金属氧化物和硅化物中的一种。然后对P型半导体层、发光层和部分N型半导体层进行刻蚀，得到第一侧壁。
在本公开一些具体的实施例中，步骤(c)具体包括：
在步骤(b)得到的半导体发光元件的表面再次依次形成第二阻挡层和第一阻挡层，对第一阻挡层进行曝光、显影和烘烤处理，然后利用化学腐蚀技术(即湿法刻蚀)对第二阻挡层做图形化处理，露出部分N型半导体层3，再利用等离子体轰击技术(即等离子刻蚀技术)对裸露的N型半导体层3进行刻蚀，刻蚀深度直至露出图形化衬底1，得到处理后的半导体发光元件。然后，将上述处理后的半导体发光元件置于石英提篮中，再将该石英提篮置于低温酸溶液中，进行浸泡预热；再将该石英提篮置于高温酸溶液中腐蚀，使裸露的N型半导体层3向半导体发光元件的内侧侵蚀，形成第二侧壁；随后将石英提篮取出，放置在低温酸溶液中冷却；冷却后采用水对腐蚀后的半导体发光元件进行洗涤，再将洗涤干净的半导体发光元件置于丙酮溶液中，以除去其表面的第一阻挡层；最后采用缓冲氧化物刻蚀液除去半导体发光元件表面的第二阻挡层，并用水清洗干净，即得到第二侧壁和第一台阶面。
一些实施方式中，酸溶液为体积比为1～3:1(还可以选择2:1)的浓磷酸和浓硫酸的 混合溶液。
一些实施方式中，低温酸溶液的温度为80～150℃(还可以选择90℃、100℃、110℃、120℃、130℃或140℃)，浸泡预热的时间为100～500s(还可以选择150s、200s、250s、300s、350s、400s或450s)。
一些实施方式中，高温酸溶液的温度为150～300℃(还可以选择160℃、170℃、180℃、200℃、250℃或280℃)，腐蚀的时间为300～800s(还可以选择350s、400s、450s、500s、550s、600s、650s、700s或750s)。
一些实施方式中，在步骤(c)中，在刻蚀得到第二侧壁102和第一台阶面201的过程中，还包括对裸露出图形化衬底1的第一台阶面201继续向下(即沿图形化衬底1的方向)进行刻蚀，得到第三台阶面203的步骤。
一些实施方式中，在形成第三台阶面203的过程中，刻蚀的方法包括化学腐蚀和/或等离子刻蚀。
具体可参考图7，能够看出，第一台阶面201与第三台阶面203之间具有一定的高度差。同时，第三台阶面203表面的图形化衬底1在刻蚀作用下其形貌发生了改变，改变后图形化衬底1表面的图形化结构2的形貌可以是圆台形、蒙古包形、平台形几种形貌中的一种或多种(可参考图12和13)。
一些实施方式中，N型半导体层3和/或P型半导体层5的材料包括但不限于GaN、GaAs、GaP、PbS和硅化物中的至少一种。一些实施方式中，N型半导体层3和/或P型半导体层5的制备方法包括但不限于CVD(化学气相沉积)和PVD(物理气相沉积)中的至少一种。
一些实施方式中，步骤(b)和/或步骤(c)中，在刻蚀的过程中，同时对半导体发光元件的相邻的两条边进行刻蚀，相邻两条边在刻蚀过程中的腐蚀速率不同，以得到具有第一支壁和第二支壁的侧壁结构，或者，具有第三支壁的侧壁结构。
一些实施方式中，如图16所示，半导体发光元件的形状为方形。假设沿互相垂直的两条边的方向分别为X方向和Y方向，由于半导体材料晶体在生长过程中存在择优取向性，所以沿半导体发光元件的X方向和Y方向可以具有不同的外延结晶方向。因此，半导体发光元件的N型半导体层3和P型半导体层5在刻蚀的过程中，其X方向和Y方向存在不同的腐蚀速率。而由于半导体发光元件在X方向和Y方向存在不同的腐蚀速率， 当其中一边的腐蚀速率小于另外一边时，腐蚀速率较慢的一边将会出现两段(即具有两个支壁)或三段角度(即具有三个支壁)的侧壁结构，即包括第一支壁1021和第二支壁1022的第二侧壁102，其外观参考图6；或者，如图13所示的具有第三支壁1023的侧壁结构。
一些实施方式中，步骤(b)和/或步骤(c)中，在刻蚀的过程中，依次对半导体发光元件的各条边进行刻蚀，以使半导体发光元件各条边刻蚀后形成的侧壁的形貌相同或者不同。即如图1至图13中的一种或者两种。
相邻两条边的侧壁外观形貌不同，可以分别控制两条边界侧壁的出光量，使半导体发光元件出光的光型可控。
一些实施方式中，依次对半导体发光元件的各条边进行刻蚀的过程中，在刻蚀之前，先采用光刻胶或氧化物掩膜对不进行刻蚀的其他条边(即除了进行刻蚀的边以外的边)进行掩盖。
本公开还提供了一种LED芯片，包括如上的半导体发光元件，半导体发光元件还包括电流阻挡层11、电流扩展层12、绝缘层13、P型电极14和N型电极15；其中，绝缘层13不包覆或者至少部分包覆第二侧壁102，和/或，绝缘层13不包覆或者至少部分包覆第一台阶面201。其中，第一台阶面201还指包括第三台阶面203在内的台阶面，即，绝缘层13还不包覆或者至少部分包覆第三台阶面203。
如图16所示，分别假设沿半导体发光元件的两条边相互垂直的方向为X方向和Y方向。
如图17和图18所示，绝缘层13不包覆第二侧壁102，绝缘层13部分包覆第一台阶面201，且全部包覆了第三台阶面203。这样包覆出光度角更大，侧壁出光更多。
如图19和图20所示，绝缘层13全部包覆第二侧壁102，绝缘层13全部包覆第一台阶面201，且全部包覆了第三台阶面203。采用该包覆方式，侧壁光反射加强，正面出光更多，光度角更小。
如图21和图22所示，绝缘层13部分包覆第二侧壁102，具体为全部包覆第一支壁1021，不包覆第二支壁1022。绝缘层13不包覆第一台阶面201，而全部包覆第三台阶面203。这样的包覆方式光度角更大，侧壁出光更多。
如图23、图24和图25所示，绝缘层13全部包覆第一支壁1021和第二支壁1022。 绝缘层13全部包覆第一台阶面201，且全部包覆第三台阶面203。这样包覆光度角更小，正面出光更多。
一些实施方式中，LED芯片还包括第二绝缘层。
本公开还提供了如上的LED芯片的制备方法，包括以下步骤：
在半导体发光元件上形成第一侧壁101、第二侧壁102和第三侧壁103，然后再形成电流阻挡层11、电流扩展层12、P型电极14、N型电极15和绝缘层13。或者，在半导体发光元件上形成第一侧壁101和第二台阶面202，然后形成电流阻挡层11和电流扩展层12，再形成第二侧壁102和第三侧壁103，最后形成P型电极14、N型电极15和绝缘层13。
工业实用性
综上所述，本公开提供了一种半导体发光元件及其制备方法、LED芯片。该半导体发光元件可以增加侧壁出光，角度可控，出光效率高。该制备方法能够增大半导体发光元件的出光效率。

Claims (15)

  1. 一种半导体发光元件，其特征在于，包括图形化衬底，以及在所述图形化衬底上依次层叠设置的N型半导体层、发光层和P型半导体层；
    所述图形化衬底的表面设置有图形化结构；
    所述P型半导体层、所述发光层和所述N型半导体层形成了侧壁结构；
    其中，所述P型半导体层、所述发光层和部分所述N型半导体层的侧壁组成了第一侧壁；
    除所述第一侧壁以外的所述N型半导体层的侧壁为第二侧壁；
    所述第二侧壁与所述图形化衬底之间裸露出所述图形化结构的台阶面为第一台阶面；
    所述图形化衬底的侧壁为第三侧壁。
  2. 根据权利要求1所述的半导体发光元件，其特征在于，所述第一侧壁与所述第二侧壁之间的夹角为10°～180°；
    和/或，所述第二侧壁与所述第一台阶面之间的夹角为20°～70°或110°～160°。
  3. 根据权利要求1或2所述的半导体发光元件，其特征在于，所述第一台阶面的宽度不大于所述半导体发光元件整体宽度的50％。
  4. 根据权利要求1～3中任一项所述的半导体发光元件，其特征在于，包含以下特征(1)～(3)中的至少一种：
    (1)所述第一侧壁与所述第二侧壁的连接处，在所述N型半导体层上形成第二台阶面；
    (2)所述第二台阶面的宽度为0.01～10μm；
    (3)所述第一侧壁与所述第二台阶面之间的夹角为10°～170°。
  5. 根据权利要求4所述的半导体发光元件，其特征在于，包含以下特征(1)～(4)中的至少一种：
    (1)所述第二侧壁为平面或非平面；
    (2)当所述第二侧壁为非平面时，所述第二侧壁包括第一支壁和第二支壁，所述第一支壁与所述第二台阶面相连接，所述第二支壁与所述图形化衬底相连接；
    (3)所述第一支壁和所述第二支壁之间的夹角为10°～180°；
    (4)所述第一支壁与所述第一台阶面之间的夹角，所述第一侧壁与所述第一台阶面之间的夹角，以及，所述第二支壁与所述第一台阶面之间的夹角均不相同。
  6. 根据权利要求5所述的半导体发光元件，其特征在于，包含以下特征(1)～(4)中的至少一种：
    (1)在所述第一支壁和所述第二支壁之间，还设置有第三支壁；
    (2)所述第三支壁与所述第一台阶面之间的夹角不大于90°；
    (3)所述第三支壁与所述第二支壁之间的夹角为90～180°；
    (4)所述第三支壁与所述第一台阶面之间的夹角，所述第一支壁与所述第一台阶面之间的夹角，以及，所述第二支壁与所述第一台阶面之间的夹角均不相同。
  7. 根据权利要求1～6中任一项所述的半导体发光元件，其特征在于，包含以下特征(1)～(4)中的至少一种：
    (1)所述第一台阶面与所述第三侧壁的交汇处还包括一台阶结构，所述台阶结构的台阶面为第三台阶面，所述第三台阶面为所述第一台阶面经过再次刻蚀后形成的裸露的图形化结构，所述第三台阶面与所述第一台阶面之间的连接处形成了第四侧壁；
    (2)所述第四侧壁与所述第三台阶面之间的夹角为90°～170°；
    (3)所述第四侧壁的表面具有凸起的图形化结构；
    (4)所述第一台阶面表面的图形化结构的高度大于所述第三台阶面表面的图形化结构的高度。
  8. 根据权利要求7所述的半导体发光元件，其特征在于，包含以下特征(1)～(3)中的至少一种：
    (1)所述第一台阶面、所述第三台阶面以及所述第四侧壁的表面的图形化结构的形状包括堆叠设置的台体和锥体的组合体、圆锥体、圆台体、蒙古包形和平坦形结构中的至少一种；
    (2)在所述台体和锥体的组合体中，所述锥体设置在所述台体的顶端，所述锥体的底面半径不大于所述台体的上表面的半径；
    (3)在所述台体和锥体的组合体中，所述台体的材质为蓝宝石，所述锥体的材质为SiO 2。
  9. 如权利要求1～8任一项所述的半导体发光元件的制备方法，其特征在于，包括以下步骤：
    (a)、提供一带有图形化结构的图形化衬底，并在所述图形化衬底的表面依次沉积N型半导体层、发光层和P型半导体层；
    (b)、对所述P型半导体层、所述发光层和部分所述N型半导体层进行刻蚀，得到第一侧壁；
    (c)、对步骤(b)得到的除所述第一侧壁以外的所述N型半导体层的侧壁进行刻蚀，得到第二侧壁；其中，所述刻蚀的深度至裸露出所述图形化衬底，所述裸露的所述图形化衬底的台阶为第一台阶面；
    (d)、对步骤(c)得到的半导体发光元件的所述图形化衬底的侧壁进行切割，得到第三侧壁。
  10. 根据权利要求9所述的半导体发光元件的制备方法，其特征在于，在步骤(b)和/或步骤(c)中，所述刻蚀的方法包括等离子刻蚀和/或湿法刻蚀。
  11. 根据权利要求9或10所述的半导体发光元件的制备方法，其特征在于，在步骤(d)中，所述切割的方法包括隐形切割技术和劈裂技术。
  12. 根据权利要求9～11中任一项所述的半导体发光元件的制备方法，其特征在于，步骤(b)和/或步骤(c)中，在所述刻蚀的过程中，同时对所述半导体发光元件的相邻的两条边进行刻蚀，相邻两条边在刻蚀过程中的腐蚀速率不同，以得到具有第一支壁和第二支壁的侧壁结构，或者，具有第三支壁的侧壁结构。
  13. 根据权利要求9所述的半导体发光元件的制备方法，其特征在于，步骤(b)和/或步骤(c)中，在所述刻蚀的过程中，依次对所述半导体发光元件的各条边进行刻蚀，以使所述半导体发光元件各条边刻蚀后形成的侧壁的形貌相同或者不同。
  14. 根据权利要求13所述的半导体发光元件的制备方法，其特征在于，所述依次对所 述半导体发光元件的各条边进行刻蚀的过程中，在刻蚀之前，先采用光刻胶或氧化物掩膜对不进行刻蚀的其他条边进行掩盖。
  15. 一种LED芯片，包括如权利要求1～8中任一项所述的半导体发光元件，其特征在于，所述半导体发光元件还包括电流阻挡层、电流扩展层、绝缘层、P型电极和N型电极；
    其中，所述绝缘层不包覆或者至少部分包覆所述第二侧壁，和/或，所述绝缘层不包覆或者至少部分包覆所述第一台阶面。
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