WO2023122997A1 - 源极驱动器、源极驱动电路及其驱动方法、显示装置 - Google Patents

源极驱动器、源极驱动电路及其驱动方法、显示装置 Download PDF

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Publication number
WO2023122997A1
WO2023122997A1 PCT/CN2021/142216 CN2021142216W WO2023122997A1 WO 2023122997 A1 WO2023122997 A1 WO 2023122997A1 CN 2021142216 W CN2021142216 W CN 2021142216W WO 2023122997 A1 WO2023122997 A1 WO 2023122997A1
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Prior art keywords
data
output
control signal
transmission control
data transmission
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PCT/CN2021/142216
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English (en)
French (fr)
Inventor
杨飞
陈燚
李天集
朱明毅
董志强
王俪蓉
许静波
Original Assignee
京东方科技集团股份有限公司
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Application filed by 京东方科技集团股份有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US17/927,627 priority Critical patent/US20240233652A1/en
Priority to PCT/CN2021/142216 priority patent/WO2023122997A1/zh
Priority to CN202180004283.5A priority patent/CN116686039A/zh
Publication of WO2023122997A1 publication Critical patent/WO2023122997A1/zh

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    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3275—Details of drivers for data electrodes
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    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
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    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
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    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3685—Details of drivers for data electrodes
    • G09G3/3688—Details of drivers for data electrodes suitable for active matrices only
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    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/027—Details of drivers for data electrodes, the drivers handling digital grey scale data, e.g. use of D/A converters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0291—Details of output amplifiers or buffers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/06—Details of flat display driving waveforms
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0233—Improving the luminance or brightness uniformity across the screen
    • G—PHYSICS
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    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0242—Compensation of deficiencies in the appearance of colours
    • G—PHYSICS
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    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2370/00—Aspects of data communication
    • G09G2370/08—Details of image data interface between the display device controller and the data line driver circuit

Definitions

  • the present disclosure relates to the field of display technology, and in particular to a source driver, a source driver circuit and a driving method thereof, and a display device.
  • LCD liquid crystal display devices
  • ELD Electro Luminescent Display
  • OLED Organic Light Emitting Diode
  • a source driving circuit includes: a first source driver and a second source driver.
  • the first source driver is configured to convert the latched first image data into the plurality of first data voltages in response to a first trigger moment of a first data transmission control signal; based on the first data transmission output the plurality of first data voltages at a second triggering moment of the control signal;
  • the second source driver is configured to, in response to the first triggering moment of the second data transmission control signal, output the latched second image data Converting into the plurality of second data voltages; outputting the plurality of second data voltages based on the second trigger moment of the second data transmission control signal; wherein, the second trigger of the first data transmission control signal There is a time difference between the moment and the second trigger moment of the second data transmission control signal.
  • the first trigger moment of the first data transmission control signal arrives at the same time as the first trigger moment of the second data transmission control signal.
  • the waveforms of the first data transmission control signal and the second data transmission control signal are the same, and there is a phase difference between them.
  • the first source driver includes an output buffer, and the output buffer includes a plurality of output channels; the output buffer is configured to be triggered by a second trigger based on the first data transmission control signal output the multiple first data voltages through the multiple output channels respectively, wherein there is a time difference between the output timings of at least two output channels.
  • the first source driver further includes a delay controller configured to output a plurality of output enable signals based on the first data transmission control signal; the output The buffer is configured to respectively output a plurality of first data voltages through the plurality of output channels in response to the plurality of output enable signals.
  • the waveforms of the plurality of output enable signals are all the same, and the waveforms of at least two output enable signals have a phase difference; the first trigger moment of at least one output enable signal is the same as the first data The first trigger moment of the transmission control signal arrives at the same time; or, the first trigger moment of at least one output enable signal and the second trigger moment of the first data transmission control signal arrive at the same time.
  • the first trigger moment of the plurality of output enable signals arrives at the same time as the first trigger moment of the first data transmission control signal; the arrival of the second trigger moment of at least one output enable signal The time is later than the arrival time of the second trigger time of the first data transmission control signal.
  • the time difference between the output moments of any two adjacent output channels is the same.
  • a source driver in another aspect, includes a data buffer, a digital-to-analog converter and an output buffer.
  • the data buffer is configured to receive and latch image data, and output the image data in response to the first trigger moment of the data transmission control signal;
  • the digital-to-analog converter is configured to receive the output of the data buffer the image data, and convert the image data into a plurality of data voltages;
  • the output buffer includes a plurality of output channels, and the output buffer is configured to be based on a second trigger moment of the data transmission control signal,
  • the plurality of data voltages are respectively output through the plurality of output channels; wherein, output moments of at least two output channels have a time difference.
  • the source driver further includes a delay controller configured to output a plurality of output enable signals based on the data transmission control signal; the output buffer is configured In response to the multiple output enable signals, multiple data voltages are respectively output through the multiple output channels.
  • the waveforms of the plurality of output enable signals are the same, and at least two output enable signals have a phase difference; the first trigger moment of at least one output enable signal is the same as that of the data transmission control signal The first trigger moment arrives at the same time; or, the first trigger moment of at least one output enable signal and the second trigger moment of the data transmission control signal arrive at the same time.
  • the first trigger moment of the plurality of output enable signals arrives at the same time as the first trigger moment of the data transmission control signal; the arrival moment of the second trigger moment of at least one output enable signal, An arrival time later than the second trigger time of the data transmission control signal.
  • the time difference between the output moments of any adjacent two output channels is the same.
  • a display device in yet another aspect, includes the source driver circuit as described in any of the foregoing embodiments; or, the source driver as described in any of the foregoing embodiments; the display device further includes: a plurality of gate lines, a plurality of data lines and at least one gate driver.
  • the at least one gate driver is configured to generate a plurality of gate drive signals, and output the plurality of gate drive signals to the plurality of gate lines respectively; the source drive circuit is configured to provide the The multiple data lines output multiple data voltages.
  • the display device further includes a timing controller configured to provide a data transmission control signal to the source driving circuit.
  • the plurality of gate lines have equal line resistances.
  • the at least one gate driver is located on the same side of the multiple data lines; the multiple data lines respectively receive the multiple data The moment of voltage is delayed step by step from one side of the display device to the other.
  • the display device includes a plurality of gate drivers, and along the arrangement direction of the plurality of data lines, the plurality of gate drivers include a first gate driver located on one side of the display device , and a second gate driver located on the other side of the display device, the first gate driver and the second gate driver are coupled to the same gate line; along the arrangement of the plurality of data lines Direction, the moment when the plurality of data lines respectively receive the plurality of data voltages is symmetrically delayed step by step from both sides of the display device to the middle.
  • a driving method of a source driving circuit which is used for driving the source driving circuit described in any one of the foregoing embodiments.
  • the driving method of the source driving circuit includes: the first source driver responds to the first trigger moment of the first data transmission control signal, converting the latched first image data into the plurality of first data voltages; Outputting the plurality of first data voltages at the second triggering moment of the first data transmission control signal; the second source driver responding to the first triggering moment of the second data transmission control signal, the latched second image Convert data into the plurality of second data voltages; output the plurality of second data voltages based on the second trigger moment of the second data transmission control signal; wherein, the second of the first data transmission control signal There is a time difference between the trigger moment and the second trigger moment of the second data transmission control signal.
  • a driving method of a source driver is provided, which is used for driving the source driver described in any one of the foregoing embodiments.
  • the driving method of the source driver includes: receiving and latching image data, and outputting the image data in response to a first trigger moment of a data transmission control signal; converting the image data into a plurality of data voltages; based on the At the second triggering moment of the data transmission control signal, the plurality of data voltages are respectively output; wherein, there is a time difference between the outputting moments of at least two data voltages.
  • FIG. 1 is a structural diagram of a display device according to some embodiments.
  • Figure 2 is a structural diagram of a sub-pixel according to some embodiments.
  • 3 is a waveform diagram of gate driving signals at different positions of gate lines according to some embodiments.
  • FIG. 4 is a structural diagram of a source driving circuit according to some embodiments.
  • 5 is a timing diagram of transmission of source driving signals and image data according to some embodiments.
  • FIG. 6 is a waveform diagram of an output enable signal according to some embodiments.
  • FIG. 7 is a waveform diagram of an output enable signal according to other embodiments.
  • FIG. 8 is a waveform diagram of an output enable signal according to still other embodiments.
  • FIG. 9 is an output delay diagram of data lines in a display device according to some embodiments.
  • FIG. 10 is a structural diagram of a display device according to some embodiments.
  • Fig. 11 is an output delay diagram of data lines in a display device according to other embodiments.
  • Fig. 12 is an output delay diagram of data lines in a display device according to still other embodiments.
  • FIG. 13 is a structural diagram of a display device according to some embodiments.
  • FIG. 14 is a coupling structure diagram of a timing controller and a source driving circuit according to some embodiments.
  • FIG. 15 is a coupling structure diagram of a timing controller and a source driving circuit according to other embodiments.
  • 16 is an output waveform diagram of a source driving circuit according to some embodiments.
  • FIG. 17 is an output waveform diagram of a source driving circuit according to other embodiments.
  • Figure 18 is a waveform diagram of an output enable signal according to some embodiments.
  • FIG. 19 is a waveform diagram of an output enable signal according to other embodiments.
  • FIG. 20 is a waveform diagram of an output enable signal according to still other embodiments.
  • first and second are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance or implicitly specifying the quantity of indicated technical features. Thus, a feature defined as “first” and “second” may explicitly or implicitly include one or more of these features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality” means two or more.
  • the expressions “coupled” and “connected” and their derivatives may be used.
  • the term “connected” may be used in describing some embodiments to indicate that two or more elements are in direct physical or electrical contact with each other.
  • the term “coupled” may be used when describing some embodiments to indicate that two or more elements are in direct physical or electrical contact.
  • the terms “coupled” or “communicatively coupled” may also mean that two or more elements are not in direct contact with each other, but yet still co-operate or interact with each other.
  • the embodiments disclosed herein are not necessarily limited by the context herein.
  • At least one of A, B and C has the same meaning as “at least one of A, B or C” and both include the following combinations of A, B and C: A only, B only, C only, A and B A combination of A and C, a combination of B and C, and a combination of A, B and C.
  • a and/or B includes the following three combinations: A only, B only, and a combination of A and B.
  • the term “if” is optionally interpreted to mean “when” or “at” or “in response to determining” or “in response to detecting,” depending on the context.
  • the phrases “if it is determined that " or “if [the stated condition or event] is detected” are optionally construed to mean “when determining ! or “in response to determining ! depending on the context Or “upon detection of [stated condition or event]” or “in response to detection of [stated condition or event]”.
  • parallel As used herein, “parallel”, “perpendicular”, and “equal” include the stated situation and the situation similar to the stated situation, the range of the similar situation is within the acceptable deviation range, wherein the The stated range of acceptable deviation is as determined by one of ordinary skill in the art taking into account the measurement in question and errors associated with measurement of the particular quantity (ie, limitations of the measurement system).
  • “parallel” includes absolute parallelism and approximate parallelism, wherein the acceptable deviation range of approximate parallelism can be, for example, a deviation within 5°; Deviation within 5°.
  • “Equal” includes absolute equality and approximate equality, where the difference between the two that may be equal is less than or equal to 5% of either within acceptable tolerances for approximate equality, for example.
  • a display device configured to display images; for example, static images or dynamic images may be displayed.
  • the display device may be: a monitor, a TV, a billboard, a home appliance, a large wall, an information query device (such as a business query device in an e-government, a bank, a hospital, or an electric power department), a mobile phone, a personal digital assistant ( Personal Digital Assistant, PDA), digital camera, camcorder or navigator, etc.
  • PDA Personal Digital Assistant
  • a display device 1 includes a display panel 10 , a timing controller 20 , a gate driving circuit 30 and a source driving circuit 40 .
  • the display panel 10 has a display area (Active Area) and a peripheral area S.
  • the peripheral area S is located on at least one side of the display area AA.
  • the peripheral area S may be set around the display area AA.
  • the display panel 10 can be an OLED (Organic Light Emitting Diode, organic light emitting diode) panel, a QLED (Quantum Dot Light Emitting Diodes, quantum dot light emitting diode) panel, an LCD (Liquid Crystal Display, liquid crystal display) panel, a micro LED (including: miniLED or microLED) panels, etc., without too many restrictions.
  • OLED Organic Light Emitting Diode, organic light emitting diode
  • QLED Quantum Dot Light Emitting Diodes, quantum dot light emitting diode
  • LCD Liquid Crystal Display, liquid crystal display
  • micro LED including: miniLED or microLED
  • the display panel 10 may include a plurality of signal lines, such as gate lines (Gate Line, GL), data lines (Data Line, DL), and other drive control signal lines (such as light emission control signal lines) wait.
  • the gate line can be used to transmit the gate driving signal GDS
  • the data line is configured to transmit the data voltage DV (data current or data signal)
  • the driving control signal line (such as the light emission control signal line) can be used to transmit the driving control signal ( For example, light control signal).
  • the plurality of gate lines sequentially arranged along the first direction Y are GL1-GLm
  • the plurality of data lines arranged sequentially along the second direction X are sequentially DL1-DLn, where m and n are both positive integers.
  • a plurality of gate lines are arranged parallel to each other, a plurality of data lines are also arranged in parallel to each other, and a plurality of gate lines and a plurality of data lines are arranged intersecting each other, for example, arranged perpendicularly to each other.
  • the display panel 10 may further include a plurality of sub-pixels P, and the plurality of sub-pixels P are located in the display area AA.
  • a plurality of sub-pixels P may be arranged in an array.
  • sub-pixels P arranged in a row along the second direction X are called sub-pixels P in the same row
  • sub-pixels P arranged in a row along the first direction Y are called sub-pixels P in the same column.
  • the plurality of sub-pixels P may include a first-color sub-pixel configured to emit light of a first color, a second-color sub-pixel configured to emit light of a second color, and a third-color sub-pixel configured to emit light of a third color.
  • the first color, the second color and the third color are red, green and blue, respectively.
  • At least one (for example, each) sub-pixel P of the display panel 10 includes a pixel circuit 110 and a light emitting device L, the pixel circuit 110 is coupled to the light emitting device L, and the pixel circuit 110 is configured to drive the light emitting device L shines.
  • a plurality of pixel circuits 110 are also arranged in an array, including the position of the sub-pixel P of the pixel circuit 110 as the position of the pixel circuit 110 .
  • the light emitting device L can be LED, OLED or QLED, etc.
  • the light emitting device L includes a cathode and an anode, and a light emitting functional layer between the cathode and the anode.
  • the light-emitting functional layer may include an emission layer (Emission layer, EML), a hole transport layer (Hole Transporting Layer, HTL) between the light-emitting layer and the anode, an electron transport layer (Election Transporting layer) between the light-emitting layer and the cathode. Layer, ETL).
  • a hole injection layer (Hole Injection Layer, HIL) can also be set between the hole transport layer HTL and the anode, and an electron injection layer (HIL) can be set between the electron transport layer ETL and the cathode.
  • HIL Hole Injection Layer
  • EIL election Injection Layer
  • the anode can be formed of a transparent conductive material with a high work function, and its electrode material can include indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium oxide (IGO), gallium zinc oxide (GZO) oxide Any one or a combination of zinc (ZnO), indium oxide (In2O3), aluminum zinc oxide (AZO), and carbon nanotubes.
  • ITO indium tin oxide
  • IZO indium zinc oxide
  • IGO indium gallium oxide
  • GZO gallium zinc oxide
  • ZnO zinc
  • In2O3 aluminum zinc oxide
  • AZO aluminum zinc oxide
  • carbon nanotubes carbon nanotubes
  • the cathode for example, can be formed of a material with high conductivity and low work function, and its electrode material can include any one or combination of alloys such as magnesium aluminum alloy (MgAl) and lithium aluminum alloy (LiAl), as well as magnesium (Mg), aluminum ( Any one or combination of metal elements such as Al), lithium (Li) and silver (Ag).
  • the material of the light-emitting layer can be selected according to the color of the emitted light.
  • the material of the light emitting layer includes a fluorescent light emitting material or a phosphorescent light emitting material.
  • the light-emitting layer may adopt a doping system, that is, a dopant material is mixed into a host light-emitting material to obtain a usable light-emitting material.
  • a dopant material is mixed into a host light-emitting material to obtain a usable light-emitting material.
  • metal compound materials, anthracene derivatives, aromatic diamine compounds, triphenylamine compounds, aromatic triamine compounds, biphenyldiamine derivatives, and triarylamine polymers can be used as the host luminescent material.
  • the pixel circuit 110 may be composed of electronic devices such as transistors and capacitors (Capacitance, C for short).
  • the transistor may be a thin film transistor (Thin Film Transistor, TFT for short), or a field effect transistor (Field Effect Transistor, TFE for short).
  • TFT Thin Film Transistor
  • FFE Field Effect Transistor
  • the pixel circuit 110 may include two transistors (a switching transistor T1 and a driving transistor T2) and a capacitor C to form a 2T1C structure; for another example, the pixel circuit 110 may also include more than two transistors (multiple switching transistors and a driving transistor) and at least one capacitor C, for example, the pixel circuit 110 may include a capacitor C and seven transistors (six switching transistors and a driving transistor), forming a 7T1C structure.
  • the pixel circuit is illustrated as an example with a 2T1C structure.
  • One pole (such as the anode) of the light emitting device L is coupled to the pixel circuit, and the other pole (such as the cathode) of the light emitting device L is coupled to the second power supply voltage terminal ELVSS; the second power supply voltage terminal ELVSS is configured to transmit a DC voltage , such as DC low voltage.
  • the switch transistor T1 in response to the gate drive signal, the switch transistor T1 is turned on, and in response to the data signal, the gate g of the drive transistor T2 is coupled to the drain d, and the data voltage is applied to the gate g of the drive transistor T2, the first The current path between the power supply voltage terminal ELVDD and the second power supply voltage terminal ELVSS is conducted, based on the connection between the voltage of the gate g of the driving transistor T2 and the first power supply voltage signal (the signal received by the first power supply voltage terminal ELVDD) The driving current generated by the voltage difference is transmitted to the light-emitting device L through the current path, and the light-emitting device L is driven to emit light.
  • the timing controller 20 can receive the initial image data ID and the synchronous control signal TCS from the system (for example, the main board in the display device 1), and generate a gate control signal GCS (Gate Control Signal), an image Data RGB and source control signal SCS.
  • GCS Gate Control Signal
  • the synchronous control signal TCS input to the timing controller 20 may include a main clock signal (or called a data sampling clock), a horizontal synchronous signal (Hsync, referred to as HS), a vertical synchronous signal (Vsync, referred to as VS) and Data enable signal (Data Enable, referred to as DE) and other signals.
  • the timing controller 20 generates image data, a gate control signal GCS, and a source control signal SCS based on the initial image data ID and the synchronization control signal TCS.
  • the image data RGB may be generated by correcting the original image data ID, for example, the image data RGB may be generated from the original image data ID through image quality correction, spot correction, color characteristic compensation and/or active capacitance compensation, etc. owned.
  • the image data RGB may include red grayscale data, green grayscale data, and blue grayscale data of different sub-pixels P.
  • the timing controller 20 may output the generated gate control signal GCS to the gate driving circuit 30 .
  • the gate driving circuit 30 receives and responds to the gate control signal GCS, generates a plurality of gate driving signals GDS, and outputs the plurality of gate driving signals GDS to the plurality of gate lines GL1 ⁇ GLm in the display panel, to control Each row of sub-pixels P coupled to a plurality of gate lines GL1 ⁇ GLm is gated.
  • the gate control signal GCS may include a frame start (Start Vertical, STV) signal, a scan clock pulse (Clock Pulse Vertical, CPV) signal, an enable (Output Enable, OE) signal, and the like.
  • the STV signal is the start signal for the start of scanning of a frame display screen
  • the CPV is the clock signal of the gate drive circuit 30.
  • One cycle represents the output of a row of the gate drive signal GDS, and the setting of the OE signal will affect the gate drive signal GDS. output waveform.
  • the gate drive circuit 30 may scan multiple rows of sub-pixels P row by row, that is, sequentially input gate drive to multiple gate lines GL1 ⁇ GLm in order from the first row of sub-pixels P to the last row of sub-pixels P.
  • Signal GDS may be used to determine whether the first row of sub-pixels P row by row.
  • the gate driving circuit 30 may include at least one (for example, a plurality of) gate drivers 300 , and each gate driver 300 is coupled to the timing controller 20 .
  • the gate drive circuit 30 includes a plurality of gate drivers 300. According to the order in which the gate drivers 300 are arranged, the first gate driver 300 is coupled to the timing controller 20, and the remaining gate drivers 300 are coupled to the previous gate drivers 300.
  • One gate driver 300 is coupled, that is, multiple gate drivers 300 are sequentially cascaded.
  • the gate driver 300 may be mounted on the display panel 10 in the form of a chip, or may be connected to the display panel 10 in the form of a tape carrier package (Tape Carrier Package, TCP) or a chip on film (Chip On Film, COF). .
  • TCP Tap Carrier Package
  • COF Chip On Film
  • the gate drive circuit 30 may include at least one (for example, multiple) GOA (Gate driver On Array) circuits, which are used to provide the gate drive signal GDS to the gate lines, thereby reducing external
  • GOA Gate driver On Array
  • the chip bonding (bonding) process is beneficial to increase production capacity and reduce product cost, and can make the frame of the display device 1 narrower to achieve better display effect.
  • the driving method of the display device 1 may be single-sided driving or double-sided driving.
  • the driving mode of the display device 1 is unilateral driving
  • the gate driving circuit 30 includes a plurality of gate drivers 300.
  • the gate drivers 300 are all located on the same side of the plurality of data lines.
  • the timing controller 20 may output the generated image data RGB and the source data transmission control signal SCS to the source driving circuit 40 .
  • the signal format for outputting the image data RGB and the source control signal SCS to the source drive circuit 40 by the timing controller 20 is not too limited, and the signal format may be Low Voltage Differential Signaling (LVDS), Any one of various signal formats such as Embedded Display Port (eDP), Transistor to Transistor Logic (TTL), mini LVDS signal, etc., can be set by those skilled in the art according to needs.
  • the timing controller 20 encodes image data and source control signals into LVDS signals, and then outputs them to the source driving circuit 40 .
  • LVDS signal has the characteristics of high data transmission rate, low noise, low power consumption and long transmission distance, which is conducive to achieving better signal transmission effect.
  • the source control signal SCS may include a row start signal (Start Horizontal, STH), a row clock pulse signal (Clock Pulse Horizontal, CPH), a data transmission control signal (marked as TP or STB) and other signals.
  • the line start signal represents the beginning of data transmission of a row of sub-pixel P
  • the line clock signal is the clock signal of the source drive circuit 40
  • the data transmission control signal is used to control the source drive circuit 40 to transfer the image data from the timing controller RGB is converted into a plurality of data voltages DV, and the plurality of data voltages DV are respectively output to the plurality of data lines DL1 ⁇ DLn in the display panel 10, so as to input the plurality of data voltages DV to the selected sub-pixels P of each row respectively, so that Each sub-pixel P displays a corresponding color under the action of the electric field.
  • the source driving circuit 40 may sequentially input a plurality of data voltages DV into multiple rows of sub-pixels P in sequence from the sub-pixel
  • the source driver circuit 40 may include at least one (eg, one or more) source drivers 400 , and each source driver circuit 40 is coupled to the timing controller 20 .
  • the source driver 400 can also be provided in the form of a chip, a tape-carrying package, or a chip-on-chip, and there is no excessive limitation on this.
  • the source driver circuit 40 includes a source driver 400 , a plurality of data lines DL1 -DLn in the display device are all coupled to the source driver 400 .
  • the source driver circuit 40 includes a plurality of source drivers 400, and the plurality of data lines DL1 ⁇ DLn in the display device can be divided into a plurality of data line groups (not shown in the figure), and in each data line group Multiple data lines are coupled to the same source driver 400 .
  • the display device 1 is developing toward a large size and high resolution. As the size of the display device 1 increases, along the second direction X, the length of the gate line increases, and along the first direction Y, the data As the length of the lines increases, the resistance values of the gate lines and the data lines also increase accordingly. The gate lines and data lines are intersected. As the resolution of the display device 1 increases, the number of gate lines and data lines increases, the number of crossing positions between gate lines and data lines increases, and the parasitic capacitance increases. The increase of resistance value and parasitic capacitance makes both the gate line and the data line have a larger resistance-capacitance load (RC Loading).
  • RC Loading resistance-capacitance load
  • a larger RC Loading will weaken the strength of the transmitted signal, resulting in a larger degree of signal attenuation.
  • a large RC Loading will cause the waveform of the gate drive signal GDS to be seriously distorted at a position on the gate line far away from the gate drive circuit 30 .
  • the multiple data lines DL1 ⁇ DLn include a first data line DLa and a second data line DLb, and the same row of sub-pixels P includes a first sub-pixel P1 and a second sub-pixel P2, wherein the first One sub-pixel P1 is coupled to the first data line DLa, and the second sub-pixel P2 is coupled to the second data line DLb.
  • the first data line DLa is located on the side of the second data line DLb close to the gate drive circuit 30, and the first data line DLa and the second data line DLb may be adjacent to each other, or there may be an interval between them.
  • the first sub-pixel P1 takes the first data line DLa adjacent to the second data line DLb as an example, along the second direction X, the first sub-pixel P1 is also located on the side of the second sub-pixel P2 close to the gate driving circuit 30 .
  • the first sub-pixel P1 and the second sub-pixel P2 are coupled to the same gate line GL1, wherein the gate line part coupled to the first sub-pixel P1 is the first gate line part LP1, which is the same as the second sub-pixel P2.
  • the coupled gate line portion is the second gate line portion LP2.
  • the attenuation degree of the gate drive signal GDS transmitted by the second gate line part LP2 is greater than the attenuation of the gate drive signal GDS transmitted by the first gate line part LP degree.
  • e is a positive integer, and e ⁇ m-1.
  • the time required for the potential of the gate drive signal GDS transmitted by the first gate line part LP1 in the gate line GLe to reach Von is t1, and due to the signal attenuation caused by RC Loading, the second gate line part LP2 in the gate line GLe
  • the time required for the potential of the transmitted gate driving signal GDS to reach Von is t2, t2>t1, that is, compared with the switching transistor in the first sub-pixel P1 coupled to the first gate line part LP1 (hereinafter referred to as is the first switching transistor), the turn-on delay of the switching transistor (hereinafter referred to as the second switching transistor) in the second sub-pixel P2 coupled with the second gate line part LP2 makes it impossible for the data voltage DV to be written into the second sub-pixel normally.
  • the charging rate of the second sub-pixel P2 is lower than the charging rate of the first sub-pixel P1
  • the light-emitting luminance of the insufficiently charged second sub-pixel P2 is lower than the light-emitting luminance of the first sub-pixel P1
  • the signal attenuation caused by RC Loading will also affect the closing of the switching transistor.
  • the time required for the first switch transistor to be turned off is t3
  • the time required for the second switch transistor to be turned off is t4, t4>t3, that is, compared with the first switch transistor, the second switch transistor
  • some embodiments of the present disclosure provide a source driver 400 including circuit modules such as a data buffer 420 , a digital-to-analog converter 440 and an output buffer 450 . It should be understood that the present disclosure only introduces circuit modules related to the embodiments of the present disclosure, while omitting other irrelevant circuit modules.
  • the data buffer 420 is configured to receive and latch the image data RGB, and output the image data RGB in response to the first trigger moment L1 of the data transmission control signal STB.
  • the data buffer 420 includes a data receiver 421 and a data buffer 422, the data receiver 421 and the data buffer 422 work in parallel, and the data receiver 421 takes the i-1th (i is a positive integer, After the image data RGB of the sub-pixels of i ⁇ m) rows, these image data RGB are sent to the data buffer 422 at the same time.
  • the data buffer 422 stores the image data RGB of the i-1th row of sub-pixels and outputs the data voltage of the i-1th row of sub-pixels to the i-1th row of sub-pixels after being processed by subsequent circuit modules.
  • the data receiver 421 receives the image data RGB of the i-th row of sub-pixels.
  • the data receiver 421 and the data buffer 422 work in parallel, which can improve the working efficiency of the source driver 400 .
  • the data receiver 421 may include a plurality of data receiving units (not shown in the figure) for registering the image data RGB
  • the data buffer 422 may include a plurality of data buffer units (not shown in the figure) for outputting the image data RGB not shown).
  • the number of data receiving units is related to the number of data lines DL coupled to the source driver 400 and the number of input bits of image data RGB.
  • the source driver 400 is coupled to n data lines DL, and the color depth of each sub-pixel is 8 bits, so the required number of input buffer units is 8n.
  • the required number of output buffer units The number is also 8n.
  • the data transmission control signal STB can be a control command (also can be said to be control command data), including: control command start duration (STB Start) and control command pulse width duration (STB Width) .
  • the data transmission control signal STB has a first trigger time L1 and a second trigger time L2.
  • the start duration of the control command starts from the moment when the last data voltage DV of the previous row of sub-pixels P is output, and ends when the data buffer 420 starts outputting the image data RGB of the next row of sub-pixels P.
  • the pulse width duration of the control command starts from the moment when the image data RGB of the next row of sub-pixels P starts to be output, and ends when the data voltage DV of the next row of sub-pixels P starts to be output to the display panel.
  • the end time of the control command start time is reached at the same time as the start time of the control command pulse width, which is the first trigger time L1 of the data transmission control signal STB; the end time of the control command pulse width is the data transmission control signal
  • the second trigger moment L2 of the STB At the first trigger time L1, the image data RGB input to the source driver 400 is latched, and at the second trigger time L2, a plurality of data voltages DV obtained by converting the image data RGB are output to the display panel.
  • the number of bits of the start duration of the control command and the pulse width duration of the control command may be the same or different.
  • the start duration of the control command can be a 10-bit digital signal
  • the pulse width duration of the control command can also be a 10-bit digital signal, both of which correspond to 2 ⁇ 10 (1024) durations.
  • the control command start duration is, for example, 480
  • it may indicate that the control command start duration is 480 unit durations
  • the control command pulse width duration is, for example, 960
  • one unit duration may be is a clock cycle.
  • the start duration of the control command can be an 8bit digital signal, corresponding to 2 ⁇ 8 (256) durations; the pulse width duration of the control command is a 10bit digital signal, corresponding to 2 ⁇ 10 (1024) durations.
  • the start duration of the control command is, for example, 255, and the duration of the pulse width of the control command is, for example, 600.
  • the data transmission control signal STB can also be a pulse signal for controlling the data buffer 420, the data transmission control signal STB has a first trigger moment L1 and a second trigger moment L2, and at the first trigger
  • the image data RGB input to the source driver 400 is latched at time L1, and a plurality of data voltages DV obtained by converting the image data RGB are output to the display panel at a second trigger time L2.
  • the edge of the data transmission control signal STB from the first level V1 to the second level V2 is the first trigger time L1 of the data transmission control signal STB
  • the edge from the second level V2 to the first level V1 is the data
  • the second trigger moment L2 of the control signal STB is transmitted.
  • Levels of the first level V1 and the second level V2 are relative. For example, when the first level V1 is at a high level, the second level V2 is at a low level.
  • the first level V1 can be a high level or a low level.
  • the first level V1 is a low level and the second level V2 is a high level as an example for illustration.
  • the first trigger time L1 of the data transmission control signal STB is a rising edge
  • the second trigger time L2 is a falling edge.
  • the digital-to-analog converter 440 is configured to receive the image data RGB output from the data buffer 420 and convert the image data RGB into a plurality of data voltages DV (also referred to as grayscale voltages) in analog form.
  • the digital-to-analog converter 440 can generally perform digital-to-analog conversion by selecting an analog voltage corresponding to the image data RGB generated by a grayscale voltage generating circuit (not shown).
  • the digital-to-analog converter 440 may include multiple digital-to-analog conversion units (not shown in the figure), and the multiple digital-to-analog conversion units may convert image data RGB into corresponding multiple data voltages DV.
  • the digital-to-analog converter 440 may include 8n digital-to-analog conversion units.
  • the output buffer 450 includes a plurality of output channels OP, and the output buffer 450 is configured to transfer a plurality of data voltages DV through a plurality of output channels OP respectively.
  • the number of output channels OP in the output buffer 450 is equal to the number of data lines DL coupled to the source driver 400 .
  • the source driver 400 is coupled to n data lines DL, then the number of output channels OP in the output buffer 450 is n.
  • the timing at which at least one (eg, multiple) output channels OP respectively output the data voltage DV is no earlier than the arrival timing of the second triggering timing L2 of the data transmission control signal STB.
  • the source driver 400 may further include a control signal receiver 410 .
  • the control signal receiver 410 is configured to receive and separate the image data RGB and the source control signal SCS encoded by the timing controller 20, and transmit the separated image data RGB and the source control signal SCS to the source respectively.
  • Corresponding circuit modules in the driver 400 can be an interface, and the type of the interface can be set according to the signal format output by the timing controller 20. For example, when the output of the timing controller 20 is an eDP signal, the control signal receiver 410 is an eDP signal.
  • the control signal receiver 410 when the timing controller 20 outputs a TTL signal, the control signal receiver 410 is a TTL interface; when the timing controller 20 outputs a LVDS signal, the control signal receiver 410 is a LVDS interface.
  • the type and number of data ports (Ports) of the interface can be set according to actual needs, and this disclosure does not impose too many restrictions on this.
  • the source driver 400 may further include a command receiver 430 configured to receive the source control signal SCS from the control signal receiver 410 and send the source control signal SCS included The various signals are transmitted to the corresponding circuit modules respectively.
  • the image data RGB and the source control signal SCS can be time-divisionally transmitted.
  • the source control signal SCS of one row of sub-pixels (for example, the f-th row, f is a positive integer, f ⁇ n-1) can be transmitted first, and then the source control signal SCS of the f-th row of sub-pixels can be transmitted in the subsequent period T2.
  • Image data RGB; the source control signal SCS of the f+1th row of sub-pixels can be transmitted in the period T3, and the image data RGB of the f+1th row of sub-pixels can be transmitted in the subsequent period T4, and so on.
  • the T5 period (the duration is determined by the start duration of the control command of the data transmission control signal STB) is the buffer period after the output of the last data voltage DV of the sub-pixel in the f-2th row is completed, in response to the first trigger moment of the data transmission control signal STB L1, the data buffer 422 in the data buffer 420 outputs the image data RGB of the f ⁇ 1th row of sub-pixels to the digital-to-analog converter 440 .
  • the digital-to-analog converter 440 converts the received image data RGB into a plurality of data voltages DV, and converts the converted plurality of data voltages DV output to the output buffer 450.
  • the output buffer 450 starts to output the data voltage DV of the f-1th row of sub-pixels.
  • the output buffer 450 outputs the multiple data voltages DV of the sub-pixels in the f-1th row to the data lines DL respectively through multiple output channels.
  • the sub-pixel P image data RGB of the f-th row is processed in the same manner during the T8 period to the T10 period.
  • the gate line Both the turn-on and turn-off of the second switch transistor in the coupled second sub-pixel are delayed.
  • at least two output channels OP may be set to have a time difference between output moments, wherein the time difference between any two data lines DL receiving the data voltage DV may be the same or different.
  • the plurality of output channels OP includes a first output channel OP1 and a second output channel OP2, the first output channel OP1 is coupled to the first sub-pixel through the first data line DLa, and the second output channel OP2 is coupled to the first sub-pixel through the second data line DLb is coupled to the second sub-pixel, and there is a time difference between the output moment of the first output channel OP1 (hereinafter referred to as the first moment) and the output moment of the second output channel OP2 (hereinafter referred to as the second moment).
  • the first moment the first output channel OP1
  • the second moment of the second output channel OP2 hereinafter referred to as the second moment
  • the time when the first data line DLa receives the data voltage DV is earlier than the time when the second data line DLb receives the data voltage DV, and the time difference between the two is ta, that is, the second time is delayed by ta from the first time.
  • ta can be set according to the delay time between the turn-on moment of the second switch transistor and the turn-on moment of the first switch transistor, or can be adjusted according to the line resistance of each gate line or the corresponding RC Loading.
  • the time difference between two sub-pixels adjacently arranged along the second direction X receiving the data voltage DV is basically consistent with the time difference between the turn-on moments of the switching transistors in these two sub-pixels, thereby reducing The charging rate difference between these two sub-pixels is minimized, so that the luminous brightness is relatively uniform.
  • the data voltage DV of the next row will be output.
  • the output of the data voltage DV of the subpixels of the previous row is delayed, the output of the data voltage DV of the subpixels of the next row It will also be delayed accordingly, so that when the switching transistors of the previous row of sub-pixels are turned off and delayed, the data voltage DV of the next row of sub-pixels will not be written into the previous row of sub-pixels by mistake, which can reduce the risk of uneven color rendering of the display device, and is conducive to improving Display quality.
  • the time difference between the output moments of any two adjacent output channels OP is the same. That is, along the second direction X, the time difference between any two adjacent data lines DL receiving the data voltage DV is the same (for example, both are ta).
  • this setting can help simplify the source The design of pole driver 400.
  • the source driver 400 further includes at least one (for example, one) delay controller 460, and the delay controller 460 is configured to output a plurality of output enable based on the data transmission control signal STB Signal EN.
  • the output buffer 450 is configured to respectively output a plurality of data voltages DV through a plurality of output channels OP in response to a plurality of output enable signals EN.
  • the multiple data lines DL1-DLn sequentially arranged along the second direction X are respectively coupled to the multiple output channels OP, and the multiple output enable signals EN corresponding to the multiple output channels OP are respectively EN1-ENn.
  • multiple output enable signals EN may be stored in the delay controller 460, and the delay controller 460 receives and responds to the command from the command receiving unit 430.
  • the stored multiple output enable signals EN are output to the output buffer 450 to control the output of the multiple output channels OP.
  • the delay controller 460 may reflect the delay information of each output channel OP in the data transmission control signal according to the received data transmission control signal STB, and generate multiple output enable signals EN.
  • the edge of the output enable signal EN from the third level V3 to the fourth level V4 is the first trigger moment L3 of the output enable signal EN, and the edge from the fourth level V4 to the third level V3 is the second trigger time L4 for outputting the enable signal EN.
  • the levels of the third level V3 and the fourth level V4 are relative. It may be that the third level V3 is a high level, and the fourth level V4 is a low level; or the third level V3 is a low level, and the fourth level V4 is a high level. In this disclosure, the third level V3 is a low level, and the fourth level V4 is a high level as an example for illustration.
  • the first trigger time L3 of the output enable signal EN is a rising edge
  • the second trigger moment L4 of the enable signal EN is a falling edge.
  • Each output channel OP in the output buffer 450 can output the data voltage DV in response to a signal triggering moment of an output enable signal EN, and multiple output channels output data voltage DV in response to multiple signal triggering moments of a plurality of output enable signals EN.
  • the multiple signal triggering moments may all be rising edges of the output enable signal EN, or all be falling edges of the output enable signal EN, and there is no excessive limitation on this.
  • the waveforms of the multiple output enable signals EN are all the same, and at least two output enable signals EN have a phase difference.
  • the waveforms of multiple output enable signals EN output by the delay controller are the same, and each output channel in the output buffer can output data in response to the second trigger moment L4 of an output enable signal EN voltage, at least one (for example one) of the first trigger moment L3 of the output enable signal EN and the first trigger moment L1 of the data transmission control signal STB arrive at the same time.
  • the first triggering time L3 and the second triggering time of the output enable signal EN responded by any adjacent two output channels
  • the two triggering moments L4 are both staggered, and the time difference between the arrival times of the two first triggering moments L3 is equal to the time difference between the arrival times of the two second triggering moments L4.
  • the first trigger moment L3 of the output enable signal EN1 is aligned with the first trigger moment L1 of the data transmission control signal STB
  • the second trigger moment L4 of the output enable signal EN1 is aligned with the second trigger moment L4 of the data transmission control signal STB L2 is aligned
  • the second triggering moment L4 of the output enable signals EN1-ENn is delayed step by step, and the delay time is tb.
  • the delay controller performs delay processing on the received data transmission control signal STB according to the preset delay information and outputs it. For another example, referring to FIG.
  • the waveforms of the multiple output enable signals EN output by the delay controller 460 are all the same, and each output channel in the output buffer may respond to the first trigger moment L3 of an output enable signal EN To output the data voltage, the first trigger time L3 of at least one (eg one) output enable signal EN and the second trigger time L2 of the data transmission control signal STB arrive at the same time.
  • the first triggering time L3 and the second triggering time of the output enable signal EN responded by any adjacent two output channels
  • the two triggering moments L4 are both staggered, and the time difference between the arrival times of the two first triggering moments L3 is equal to the time difference between the arrival times of the two second triggering moments L4.
  • the first trigger time L3 of the output enable signal EN1 is aligned with the second trigger time L2 of the data transmission control signal STB, and the second trigger time L4 of the output enable signals EN1-ENn is delayed step by step, and the delay time is tc .
  • At least two output enable signals EN may have different waveforms, and any two output enable signals EN with different waveforms control the arrival times of the triggering moments of the two output signals to have a time difference.
  • the waveforms of any two output enable signals EN output by the delay controller are different, and each output channel in the output buffer may output in response to the second trigger moment L4 of an output enable signal EN
  • the data voltage, the first trigger moment L3 of a plurality of output enable signals EN arrives at the same time as the first trigger moment L1 of the data transmission control signal STB, and the second trigger moment L4 of at least one (for example, multiple) output enable signals EN
  • the arrival time of is later than the arrival time of the second trigger time L2 of the data transmission control signal STB.
  • the first trigger time L3 of the output enable signals EN1-ENn and the first trigger time L1 of the data transmission control signal STB arrive at the same time
  • the second trigger time L4 of the output enable signal EN1 and the data transmission control signal STB arrive at the same time.
  • the second triggering moment L2 arrives at the same time
  • the second triggering moment L4 of the output enable signals EN1 ⁇ ENn is delayed step by step, and the delay time is td. It is also possible to realize different output channels delaying the output data voltage for different lengths, so that in the same row The charging rate of multiple sub-pixels is relatively uniform.
  • Some embodiments of the present disclosure provide a display device, the display device includes the aforementioned source driver, and the settings of the multiple output enable signals are as described above.
  • the structure of the display device is shown in FIG. 1.
  • the driving mode of the display device 1 is unilateral drive, referring to FIG. 9, along the arrangement direction of the multiple data lines DL, the multiple data lines DL respectively receive multiple data voltages DV
  • the moment of is delayed step by step from one side of the display device 1 to the other side, specifically, from the side of the display device 1 provided with the gate drive circuit 30 to the side of the display device 1 not provided with the gate drive circuit 30 Gradually delayed.
  • the display device includes the aforementioned source driver, and the settings of the multiple output enable signals are also as described above.
  • the structure of the display device is shown in FIG. 10 .
  • the driving mode of the display device 1 is double-sided driving.
  • the display device 1 includes a timing controller 20 and a plurality of gate drivers 300, and the plurality of gate drivers 300 are coupled to the timing controller 20. catch.
  • the plurality of gate drivers 300 includes at least one (eg, multiple) first gate drivers 310 located on one side of the display device 1, and at least one (eg, multiple) first gate drivers 310 located on the other side of the display device 1
  • the second gate driver 320, a first gate driver 310 and a second gate driver 320 are coupled to the same gate line.
  • a plurality of first gate drivers 310 constitutes a first gate driving circuit 31
  • a plurality of second gate drivers 320 constitutes a second gate driving circuit 32 .
  • the gate drive signal GDS is input from both ends, which is beneficial to reduce the signal attenuation at the position of the gate line away from the first gate drive circuit 31 and the second gate drive circuit 32 .
  • the driving mode of the display device 1 is double-sided driving, along the arrangement direction of the multiple data lines DL1-DLn, from both sides to the middle of the display device 1, the switch transistors in the multiple sub-pixels P in the same row are turned on and off.
  • the delay gradually increases, and correspondingly, the charging rate of the sub-pixel P gradually decreases from both sides to the middle of the display device 1, and the charging rate of the sub-pixel P far away from the gate drive circuit 30 will also be insufficient, and the sub-pixels in the next row will be insufficient.
  • the problem that the data voltage DV of P is wrongly written into the sub-pixel P of the previous row.
  • the output channel can be set to output to the data lines DL1 ⁇ DLn/2
  • the moment of the data voltage is delayed step by step, and the moment when the output channel outputs the data voltage to the data lines DLn ⁇ DLn+1/2 is also delayed step by step.
  • the delay is symmetrical step by step from both sides of the display device to the middle.
  • the moment when the output channel outputs the data voltage to the data lines DL1 ⁇ DLn+1/2 can be set to be delayed step by step , the moment when the output channel outputs the data voltage to the data lines DLn ⁇ DLn+1/2 is delayed step by step.
  • the plurality of gate lines GL1 ⁇ GLm in the display device 1 may have equal line resistances, and similarly, the plurality of data lines DL1 ⁇ DLn in the display device 1 may also have equal line resistances. resistance.
  • the display device 1 includes a source driving circuit 40
  • the source driving circuit 40 includes a plurality of source drivers 400
  • the plurality of source drivers 400 are all coupled to the timing controller 20 catch.
  • a plurality of source drivers 400 may all be connected to the timing controller 20, and the timing controller 20 outputs the image data RGB and the source driving signal SCS to each source driver 400, and each source driver 400 receives
  • the source drive signal SCS separates the required data transmission control signals, and performs image data RGB conversion and data voltage output in response to the respective data transmission control signals.
  • the source driver circuit 40 includes a plurality of source drivers 400 cascaded to each other, at least one (for example, one) source driver 400 is connected to the timing controller 20, and the image data output by the timing controller 20 RGB and source driving signals SCS are continuously transmitted from this source driver 400 to other source drivers 400 .
  • the plurality of source drivers 400 and the timing controller 20 may also adopt other feasible connection methods, which are not limited too much in the embodiment of the present disclosure.
  • the multiple data lines DL1 ⁇ DLn in the display panel 10 can be divided into multiple data line groups (not shown in the figure), and the multiple data lines DL1 ⁇ DLn in each data line group Coupled with the same source driver 400 .
  • the plurality of source drivers 400 includes a first source driver 401 and a second source driver 402 .
  • the timing controller 20 provides the first image data RGB1 and the first source control signal SCS1 to the first source driver 401, the first source control signal SCS1 includes the first data transmission control signal, and provides the second source driver 402 with The second image data RGB2 and the second source driving signal SCS2 are provided, and the second source driving signal SCS2 includes a second data transmission control signal.
  • the first source driver 401 and the second source driver 402 respectively convert image data RGB into a plurality of data voltages DV in response to respective data transmission control signals, and output the plurality of data voltages DV to the display panel 10 .
  • the relative positions of the first source driver 401 and the second source driver 402 are not restricted too much, and the two may or may not be adjacent to each other.
  • the first source driver 401 It may be located on the left side of the second source driver 402 or on the right side of the second source driver 402 .
  • the multiple data line groups in the display panel 10 include a first data line group and a second data line group, the multiple data lines in the first data line group are coupled to the first source driver 401, and the second data line group A plurality of data lines are coupled to the second source driver 402 .
  • the first source driver 401 can simultaneously output multiple first data voltages to multiple data lines in the first data line group
  • the second source driver 402 can also simultaneously output multiple first data voltages to multiple data lines in the second data line group. a plurality of second data voltages.
  • the driving mode of the display device 1 is unilateral driving
  • the first source driver 401 and the second source driver 402 are adjacent
  • the first source driver 401 is located in the second source driver.
  • 402 is close to the side of the gate driving circuit 30
  • the first source driver 401 is one of the plurality of source drivers 400 closest to the gate driving circuit 30 as an example for illustration.
  • the data transmission control signal STB to which the first source driver 401 responds is the first data transmission control signal STB1
  • the data transmission control signal STB to which the second source driver 402 responds is the second data transmission control signal STB.
  • Both the first data transmission control signal STB1 and the second data transmission control signal STB2 have a first trigger time L1 and a second trigger time L2.
  • the first source driver 401 may convert the latched first image data into a plurality of first data voltages in response to the first trigger moment L1 of the first data transmission control signal STB1, and may be based on the first data voltage of the first data transmission control signal STB1. At the second triggering time L2, a plurality of first data voltages are output. Similar to the first source driver 401, the second source driver 402 can convert the latched plurality of second image data into a plurality of second data in response to the first trigger time L1 of the second data transmission control signal STB2 The voltage outputs a plurality of second data voltages based on the second trigger time L2 of the second data transmission control signal STB2. Wherein, referring to FIG.
  • the second triggering moment L2 of the first data transmission control signal STB1 there is a time difference between the second triggering moment L2 of the first data transmission control signal STB1 and the second triggering moment L2 of the second data transmission control signal STB2 .
  • the second trigger moment L2 of the second data transmission control signal STB2 is delayed from the second trigger moment L2 of the first data transmission control signal STB1, and the delay time is t.
  • the delay time can be determined according to the line resistance of each gate line or Adjust the corresponding RC Loading.
  • the plurality of sub-pixels P in the display device 1 includes the previous sub-pixel Pc and the subsequent sub-pixel Pd, along the second direction X, and the first source driver 401 and the second source driver 402 respectively Among the multiple coupled data lines DL (respectively constituting the first data line group and the second data line group), the two data lines DL with the same arrangement position are respectively the previous data line DLc and the subsequent data line DLd.
  • the first sub-pixel Pc is coupled to the previous data line DLc
  • the subsequent sub-pixel Pd is coupled to the subsequent data line DLd
  • the previous data line DLc transmits the previous data voltage DVc
  • the subsequent data line DLd transmits the subsequent data voltage DVd .
  • the previous data line DLc is the first data line in the first data line group
  • the subsequent data line DLd is the first data line in the second data line group.
  • the second trigger moment L2 of the second data transmission control signal STB2 is shorter than the second trigger moment L2 of the second data transmission control signal STB2.
  • the second triggering time L2 of the data transmission control signal STB1 is delayed, and the delay time is also t, so that the difference in charging rates of the two sub-pixels can be reduced, and the luminous brightness of the two sub-pixels is relatively uniform.
  • the output of multiple data voltages DV of sub-pixels P in the previous row is delayed, and the output of multiple data voltages DV of sub-pixels P in the next row will also be delayed accordingly.
  • the data voltage DV of the sub-pixel P will not be wrongly written into the sub-pixel P of the previous row, which can reduce the risk of uneven color rendering of the display device 1 .
  • the specific waveforms of the first data transmission control signal STB1 and the second data transmission control signal STB2 are not restricted too much, as long as the second triggering moment L2 of the second data transmission control signal STB2 is shorter than the second trigger time of the first data transmission control signal STB1. It only needs to delay the triggering time by L2.
  • the waveform of the first data transmission control signal STB1 is different from the waveform of the second data transmission control signal STB2, and the first trigger moment L1 of the first data transmission control signal STB1 is different from that of the second data transmission control signal STB2.
  • the first trigger time L1 arrives at the same time, and the second trigger time L2 of the second data transmission control signal STB2 is delayed by t from the second trigger time L2 of the first data transmission control signal STB1 .
  • the waveforms of the first data transmission control signal STB1 and the second data transmission control signal STB2 are the same, and both have a phase difference.
  • the first trigger moment L1 of the transmission control signal STB2 has a time difference. Specifically, the first trigger moment L1 of the second data transmission control signal STB2 is later than the first trigger moment L1 of the first data transmission control signal STB1, and the second trigger moment L2 of the second data transmission control signal STB2 is also later than the first data transmission control signal STB2.
  • the second triggering moment L2 of the transmission control signal STB1 is delayed, and the delay time is t.
  • the first source driver may include circuit modules such as display data receivers, data buffers, digital-to-analog converters, and output buffers, and may also include other circuit modules.
  • the circuit modules in the second source driver It is consistent with the first source driver, and will not be repeated here.
  • the first source driver includes an output buffer (hereinafter referred to as a first output buffer), and the first output buffer includes a plurality of output channels.
  • the first output buffer is configured to respectively output the plurality of first data voltages through the plurality of output channels based on the second trigger timing of the first data transmission control signal, wherein the output timing of at least two output channels has a time difference. For example, along the arrangement direction of a plurality of output channels in an output buffer, there is a time difference when any two adjacent output channels output the first data voltage.
  • the output buffer of the second source driver (hereinafter referred to as the second output buffer) also includes a plurality of output channels, and the second output buffer is configured to transfer the plurality of The second data voltage is respectively output through the multiple output channels.
  • the above settings adjust the delay time in units of a single output channel, so that each source driver has a relatively continuous output delay change, and can fine-tune the delay time, thereby effectively reducing the gap between multiple sub-pixels in the same row.
  • the difference in charging rate can improve the display effect.
  • the time difference between the output moments of any two adjacent output channels is the same. That is, along the second direction X, the time difference between any two adjacently arranged data lines receiving the data voltage is the same.
  • the time difference between the output moments of any two adjacent output channels may be determined according to the time difference between the second trigger moment of the first data transmission control signal and the second trigger moment of the second data transmission control signal. For example, referring to FIG.
  • the time difference between the second trigger moment L2 of the first data transmission control signal STB1 and the second trigger moment L2 of the second data transmission control signal STB2 is t, and the first data line in the first data line group
  • the number of the second data lines is equal to the number of the second data lines in the second data line group, both are k, and along the second direction X, the time difference between any two adjacent data lines receiving the data voltage is the same.
  • the time difference between any two first data lines arranged adjacently in the first data group receiving the first data voltage is t/k
  • any two second data lines arranged adjacently in the second data group receive the first data voltage
  • the time difference between the two data voltages is t/k.
  • the moment when the first second data line in the second data group receives the second data voltage is the same as the moment when the kth first data line in the first data group receives the second data voltage.
  • the time difference between the moments when the data line receives the first data voltage is also t/k.
  • the first source driver further includes at least one (for example, one) delay controller (hereinafter referred to as the first delay controller), and the first delay controller is configured to, based on the first data transmission control signal, Multiple output enable signals are output.
  • the first output buffer is configured to respectively output a plurality of first data voltages through a plurality of output channels in response to a plurality of output enable signals.
  • multiple output enable signals may be stored in the first delay controller, and the first delay controller receives and responds to the first delay controller from the command receiving unit.
  • the stored multiple output enable signals are output to the first output buffer to control the output of multiple output channels.
  • the first delay controller may reflect the delay information of each output channel in the first data transmission control signal according to the received first data transmission control signal to generate multiple output enable signals.
  • each output channel in the first output buffer can output the first data voltage in response to the second trigger time L4 of an output enable signal, along the In the arrangement direction, there is a time difference when any two adjacent output channels output data voltages.
  • the first trigger moment L3 of at least one (for example, one) output enable signal and the first trigger moment L1 of the data transmission control signal arrive at the same time, and the first trigger moment of the output enable signal responded by any two adjacent output channels
  • Both L3 and the second triggering moment L4 are staggered, and the time difference between the arrival times of the two first triggering moments L3 is equal to the time difference between the arrival times of the two second triggering moments L4.
  • the moment when the multiple first data lines receive the multiple first data voltages is delayed step by step, and the delay time is t/k.
  • each output channel in the first output buffer can output the first data voltage in response to the first triggering moment L3 of an output enable signal, along the arrangement direction of the multiple output channels, any There is a time difference between two adjacent output channels outputting data voltages.
  • the first trigger moment L3 of at least one (for example, one) output enable signal and the second trigger moment L2 of the data transmission control signal arrive at the same time, and the first trigger moment of the output enable signal corresponding to any two adjacent output channels
  • Both L3 and the second triggering time L4 are staggered, and along the second direction X, the times when the multiple first data lines receive multiple first data voltages are delayed step by step, and the delay time is t/k.
  • the waveforms of at least two output enable signals are different, and any two output enable signals with different waveforms control the output of two signal triggering times with a time difference between arrival times.
  • the waveforms of any two output enable signals output by the first delay controller are different, and the first trigger time L3 of multiple output enable signals is different from the first trigger moment L3 of the first data transmission control signal STB1.
  • the trigger moment L1 arrives at the same time, the arrival moment of the second trigger moment L4 of at least one (for example, multiple) output enable signals is later than the arrival moment of the second trigger moment L2 of the first data transmission control signal STB1, along the second direction X, the moment when the multiple first data lines receive the multiple first data voltages is delayed step by step, and the delay time is t/k.
  • the arrival moment of the second trigger moment L4 of at least one (for example, multiple) output enable signals is later than the arrival moment of the second trigger moment L2 of the first data transmission control signal STB1, along the second direction X, the moment when the multiple first data lines receive the multiple first data voltages is delayed step by step, and the delay time is t/k.
  • the second source controller may also include at least one (for example, one) delay controller (hereinafter referred to as the second delay controller), the second delay controller and the second delay controller
  • the second delay controller may also include at least one (for example, one) delay controller (hereinafter referred to as the second delay controller), the second delay controller and the second delay controller
  • the second delay controller may also include at least one (for example, one) delay controller (hereinafter referred to as the second delay controller), the second delay controller and the second delay controller
  • the second delay controller may also include at least one (for example, one) delay controller (hereinafter referred to as the second delay controller), the second delay controller and the second delay controller
  • the second delay controller may also include at least one (for example, one) delay controller (hereinafter referred to as the second delay controller), the second delay controller and the second delay controller
  • the specific settings of the multiple output enable signals generated by the time delay controller are similar to those of the first time delay controller, and will not be repeated here.
  • Some embodiments of the present disclosure provide a display device, the display device includes the aforementioned source driving circuit, and the settings of the multiple output enable signals are as described above.
  • the driving mode of the display device is unilateral drive, the arrangement direction of multiple data lines at the trigger moment, and the moment when multiple data lines respectively receive multiple data voltages, are delayed step by step from one side of the display device to the other side ;
  • the driving mode of the display device is double-sided driving, the moments when multiple data lines respectively receive multiple data voltages are symmetrically delayed step by step from both sides of the display device to the middle.
  • Some embodiments of the present disclosure provide a driving method of a source driver, which is used to drive the source driver in any of the foregoing embodiments.
  • the driving method of the source driver includes: the source driver receives and latches image data, and outputs the image data in response to the first trigger moment of the data transmission control signal.
  • the source driver converts the image data into multiple data voltages, and outputs the multiple data voltages respectively based on the second triggering moment of the data transmission control signal. Wherein, there is a time difference between output moments of at least two data voltages.
  • the driving method of the source driving circuit includes: the first source driver responds to the first trigger moment of the first data transmission control signal, converts the latched first image data into a plurality of first data voltages, and based on the first At the second trigger moment of the data transmission control signal, a plurality of first data voltages are output.
  • the second source driver converts the latched plurality of second image data into a plurality of second data voltages in response to the first trigger moment of the second data transmission control signal, and based on the second trigger of the second data transmission control signal time, a plurality of second data voltages are output. Wherein, there is a time difference between the second triggering moment of the first data transmission control signal and the second triggering moment of the second data transmission control signal.
  • Some embodiments of the present disclosure provide a computer-readable storage medium (for example, a non-transitory computer-readable storage medium), in which computer program instructions are stored, and the computer program instructions are executed on a computer (for example, the aforementioned When running on any display device), the computer is made to execute the driving method of the source driver or the driving method of the source driving circuit as described in any of the above embodiments.
  • a computer-readable storage medium for example, a non-transitory computer-readable storage medium
  • the computer program instructions are stored, and the computer program instructions are executed on a computer (for example, the aforementioned When running on any display device), the computer is made to execute the driving method of the source driver or the driving method of the source driving circuit as described in any of the above embodiments.
  • the above-mentioned computer-readable storage medium may include, but is not limited to: a magnetic storage device (for example, a hard disk, a floppy disk, or a magnetic tape, etc.), an optical disk (for example, a CD (Compact Disk, a compact disk), a DVD (Digital Versatile Disk, Digital Versatile Disk), etc.), smart cards and flash memory devices (for example, EPROM (Erasable Programmable Read-Only Memory, Erasable Programmable Read-Only Memory), card, stick or key drive, etc.).
  • Various computer-readable storage media described in this disclosure can represent one or more devices and/or other machine-readable storage media for storing information.
  • the term "machine-readable storage medium" may include, but is not limited to, wireless channels and various other media capable of storing, containing and/or carrying instructions and/or data.
  • Some embodiments of the present disclosure also provide a computer program product.
  • the computer program product includes computer program instructions.
  • the computer program instructions When the computer program instructions are executed on a computer (such as any of the aforementioned display devices), the computer program instructions cause the computer to execute the driving method of the source driver as described in the above-mentioned embodiments or A driving method of a source driver circuit.
  • Some embodiments of the present disclosure also provide a computer program.
  • the computer program When the computer program is executed on a computer (such as any of the aforementioned display devices), the computer program causes the computer to execute the driving method of the source driver or the driving method of the source driving circuit as described in the above-mentioned embodiments.

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Abstract

一种源极驱动电路，包括：第一源极驱动器（401）和第二源极驱动器（402）。第一源极驱动器（401）被配置为响应于第一数据传输控制信号（STB1）的第一触发时刻（L1），将锁存的第一图像数据转换成多个第一数据电压（DVc）；基于所述第一数据传输控制信号的第二触发时刻（L2），输出多个第一数据电压（DVc）；第二源极驱动器（402）被配置为响应于第二数据传输控制信号（STB2）的第一触发时刻（L1），将锁存的第二图像数据转换成多个第二数据电压（DVd）；基于第二数据传输控制信号的第二触发时刻（L2），输出多个第二数据电压（DVd）；其中，第一数据传输控制信号（STB1）的第二触发时刻（L2）与第二数据传输控制信号（STB2）的第二触发时刻（L2）具有时间差。

Description

源极驱动器、源极驱动电路及其驱动方法、显示装置 技术领域
本公开涉及显示技术领域，尤其涉及一种源极驱动器、源极驱动电路及其驱动方法、显示装置。
背景技术
显示装置的种类繁多，按显示媒质和工作原理进行划分，可分为液晶显示装置(LCD，Liquid Crystal Display)、无机电致发光显示装置(ELD，Electro Luminescent Display)、有机电致发光显示装置(OLED，Organic Light Emitting Diode)等多种类型。每种类型的显示装置可以应用到各种各样的场景中，满足不同的图像显示需求。
随着显示技术的进步和应用需求的逐步提升，超大尺寸、超高分辨率成为显示装置未来的发展方向。
发明内容
一方面，提供一种源极驱动电路。所述源极驱动电路包括：第一源极驱动器和第二源极驱动器。所述第一源极驱动器被配置为响应于第一数据传输控制信号的第一触发时刻，将锁存的第一图像数据转换成所述多个第一数据电压；基于所述第一数据传输控制信号的第二触发时刻，输出所述多个第一数据电压；所述第二源极驱动器被配置为响应于第二数据传输控制信号的第一触发时刻，将锁存的第二图像数据转换成所述多个第二数据电压；基于所述第二数据传输控制信号的第二触发时刻，输出所述多个第二数据电压；其中，所述第一数据传输控制信号的第二触发时刻与所述第二数据传输控制信号的第二触发时刻具有时间差。
在一些实施例中，所述第一数据传输控制信号的所述第一触发时刻，与所述第二数据传输控制信号的所述第一触发时刻同时到达。
在一些实施例中，所述第一数据传输控制信号与所述第二数据传输控制信号的波形相同，且两者具有相位差。
在一些实施例中，所述第一源极驱动器包括输出缓冲器，所述输出缓冲器包括多个输出通道；所述输出缓冲器被配置为基于所述第一数据传输控制信号的第二触发时刻，将所述多个第一数据电压通过所述多个输出通道分别输出，其中，至少两个输出通道的输出时刻具有时间差。
在一些实施例中，所述第一源极驱动器还包括延时控制器，所述延时控制器被配置为基于所述第一数据传输控制信号，输出多个输出使能信号；所 述输出缓冲器被配置为响应于所述多个输出使能信号，将多个第一数据电压通过所述多个输出通道分别输出。
在一些实施例中，所述多个输出使能信号的波形均相同，且至少两个输出使能信号的波形具有相位差；至少一个输出使能信号的第一触发时刻与所述第一数据传输控制信号的第一触发时刻同时到达；或者，至少一个输出使能信号的第一触发时刻与所述第一数据传输控制信号的第二触发时刻同时到达。
在一些实施例中，所述多个输出使能信号的第一触发时刻，与所述第一数据传输控制信号的第一触发时刻同时到达；至少一个输出使能信号的第二触发时刻的到达时刻，晚于所述第一数据传输控制信号的第二触发时刻的到达时刻。
在一些实施例中，沿所述多个输出通道的排布方向，任意相邻的两个输出通道的输出时刻的时间差相同。
另一方面，提供一种源极驱动器。所述源极驱动器包括数据缓冲器、数模转换器和输出缓冲器。所述数据缓冲器被配置为接收和锁存图像数据，并响应于数据传输控制信号的第一触发时刻输出所述图像数据；所述数模转换器被配置为接收所述数据缓冲器输出的所述图像数据，并将所述图像数据转换成多个数据电压；所述输出缓冲器包括多个输出通道，所述输出缓冲器被配置为基于所述数据传输控制信号的第二触发时刻，将所述多个数据电压通过所述多个输出通道分别输出；其中，至少两个输出通道的输出时刻具有时间差。
在一些实施例中，所述源极驱动器还包括延时控制器，所述延时控制器被配置为基于所述数据传输控制信号，输出多个输出使能信号；所述输出缓冲器被配置为响应于所述多个输出使能信号，将多个数据电压通过所述多个输出通道分别输出。
在一些实施例中，所述多个输出使能信号的波形均相同，且至少两个输出使能信号具有相位差；至少一个输出使能信号的第一触发时刻与所述数据传输控制信号的第一触发时刻同时到达；或者，至少一个输出使能信号的第一触发时刻与所述数据传输控制信号的第二触发时刻同时到达。
在一些实施例中，所述多个输出使能信号的第一触发时刻，与所述数据传输控制信号的第一触发时刻同时到达；至少一个输出使能信号的第二触发时刻的到达时刻，晚于所述数据传输控制信号的第二触发时刻的到达时刻。
在一些实施例中，沿所述多个输出通道的排布方向，任意相邻的两个输 出通道的输出时刻的时间差相同。
又一方面，提供一种显示装置。所述显示装置包括如前述任一实施例中所述的源极驱动电路；或者，如前述任一实施例中所述的源极驱动器；所述显示装置还包括：多条栅线，多条数据线和至少一个栅极驱动器。所述至少一个栅极驱动器被配置为生成多个栅极驱动信号，并将所述多个栅极驱动信号分别输出给所述多条栅线；所述源极驱动电路被配置为向所述多条数据线输出多个数据电压。
在一些实施例中，所述显示装置还包括时序控制器，所述时序控制器被配置为向所述源极驱动电路提供数据传输控制信号。
在一些实施例中，所述多条栅线具有相等的线电阻。
在一些实施例中，沿所述多条数据线的排布方向，所述至少一个栅极驱动器位于所述多条数据线的同一侧；所述多条数据线分别接收到所述多个数据电压的时刻，由所述显示装置的一侧到另一侧逐级延迟。
在一些实施例中，所述显示装置包括多个栅极驱动器，沿所述多条数据线的排布方向，所述多个栅极驱动器包括位于所述显示装置一侧的第一栅极驱动器，和位于所述显示装置另一侧的第二栅极驱动器，所述第一栅极驱动器和所述第二栅极驱动器与同一条栅线耦接；沿所述多条数据线的排布方向，所述多条数据线分别接收到所述多个数据电压的时刻，由所述显示装置的两侧向中间对称性地逐级延迟。
又一方面，提供一种源极驱动电路的驱动方法，用于驱动前述任一实施例中所述的源极驱动电路。所述源极驱动电路的驱动方法包括：第一源极驱动器响应于第一数据传输控制信号的第一触发时刻，将锁存的第一图像数据转换成所述多个第一数据电压；基于所述第一数据传输控制信号的第二触发时刻，输出所述多个第一数据电压；第二源极驱动器响应于第二数据传输控制信号的第一触发时刻，将锁存的第二图像数据转换成所述多个第二数据电压；基于所述第二数据传输控制信号的第二触发时刻，输出所述多个第二数据电压；其中，所述第一数据传输控制信号的第二触发时刻与所述第二数据传输控制信号的第二触发时刻具有时间差。
又一方面，提供一种源极驱动器的驱动方法，用于驱动前述任一实施例中所述的源极驱动器。所述源极驱动器的驱动方法包括：接收和锁存图像数据，并响应于数据传输控制信号的第一触发时刻输出所述图像数据；将所述图像数据转换成多个数据电压；基于所述数据传输控制信号的第二触发时刻，将所述多个数据电压分别输出；其中，至少两个数据电压的输出时刻具有时 间差。
附图说明
为了更清楚地说明本公开中的技术方案，下面将对本公开一些实施例中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例的附图，对于本领域普通技术人员来讲，还可以根据这些附图获得其他的附图。此外，以下描述中的附图可以视作示意图，并非对本公开实施例所涉及的产品的实际尺寸、方法的实际流程、信号的实际时序等的限制。
图1为根据一些实施例的显示装置的结构图；
图2为根据一些实施例的子像素的结构图；
图3为根据一些实施例的栅线不同位置处的栅极驱动信号的波形图；
图4为根据一些实施例的源极驱动电路的结构图；
图5为根据一些实施例的源极驱动信号和图像数据的传输时序图；
图6为根据一些实施例的输出使能信号的波形图；
图7为根据另一些实施例的输出使能信号的波形图；
图8为根据又一些实施例的输出使能信号的波形图；
图9为根据一些实施例的显示装置中数据线的输出延迟图；
图10为根据一些实施例的显示装置的结构图；
图11为根据另一些实施例的显示装置中数据线的输出延迟图；
图12为根据又一些实施例的显示装置中数据线的输出延迟图；
图13为根据一些实施例的显示装置的结构图；
图14为根据一些实施例的时序控制器与源极驱动电路的耦接结构图；
图15为根据另一些实施例的时序控制器与源极驱动电路的耦接结构图；
图16为根据一些实施例的源极驱动电路的输出波形图；
图17为根据另一些实施例的源极驱动电路的输出波形图；
图18为根据一些实施例的输出使能信号的波形图；
图19为根据另一些实施例的输出使能信号的波形图；
图20为根据又一些实施例的输出使能信号的波形图。
具体实施方式
下面将结合附图，对本公开一些实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开所提供的实施例，本领域普通技术人员所获得的所有其他实施例，都属于本公开保护的范围。
除非上下文另有要求，否则，在整个说明书和权利要求书中，术语“包括(comprise)”及其其他形式例如第三人称单数形式“包括(comprises)”和现在分词形式“包括(comprising)”被解释为开放、包含的意思，即为“包含，但不限于”。在说明书的描述中，术语“一个实施例(one embodiment)”、“一些实施例(some embodiments)”、“示例性实施例(exemplary embodiments)”、“示例(example)”、“特定示例(specific example)”或“一些示例(some examples)”等旨在表明与该实施例或示例相关的特定特征、结构、材料或特性包括在本公开的至少一个实施例或示例中。上述术语的示意性表示不一定是指同一实施例或示例。此外，所述的特定特征、结构、材料或特点可以以任何适当方式包括在任何一个或多个实施例或示例中。
以下，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个该特征。在本公开实施例的描述中，除非另有说明，“多个”的含义是两个或两个以上。
在描述一些实施例时，可能使用了“耦接”和“连接”及其衍伸的表达。例如，描述一些实施例时可能使用了术语“连接”以表明两个或两个以上部件彼此间有直接物理接触或电接触。又如，描述一些实施例时可能使用了术语“耦接”以表明两个或两个以上部件有直接物理接触或电接触。然而，术语“耦接”或“通信耦合(communicatively coupled)”也可能指两个或两个以上部件彼此间并无直接接触，但仍彼此协作或相互作用。这里所公开的实施例并不必然限制于本文内容。
“A、B和C中的至少一个”与“A、B或C中的至少一个”具有相同含义，均包括以下A、B和C的组合：仅A，仅B，仅C，A和B的组合，A和C的组合，B和C的组合，及A、B和C的组合。
“A和/或B”，包括以下三种组合：仅A，仅B，及A和B的组合。
如本文中所使用，根据上下文，术语“如果”任选地被解释为意思是“当……时”或“在……时”或“响应于确定”或“响应于检测到”。类似地，根据上下文，短语“如果确定……”或“如果检测到[所陈述的条件或事件]”任选地被解释为是指“在确定……时”或“响应于确定……”或“在检测到[所陈述的条件或事件]时”或“响应于检测到[所陈述的条件或事件]”。
本文中“适用于”或“被配置为”的使用意味着开放和包容性的语言，其不排除适用于或被配置为执行额外任务或步骤的设备。
另外，“基于”的使用意味着开放和包容性，因为“基于”一个或多个所述条件或值的过程、步骤、计算或其他动作在实践中可以基于额外条件或超出所述的值。
如本文所使用的那样，“约”、“大致”或“近似”包括所阐述的值以及处于特定值的可接受偏差范围内的平均值，其中所述可接受偏差范围如由本领域普通技术人员考虑到正在讨论的测量以及与特定量的测量相关的误差(即，测量系统的局限性)所确定。
如本文所使用的那样，“平行”、“垂直”、“相等”包括所阐述的情况以及与所阐述的情况相近似的情况，该相近似的情况的范围处于可接受偏差范围内，其中所述可接受偏差范围如由本领域普通技术人员考虑到正在讨论的测量以及与特定量的测量相关的误差(即，测量系统的局限性)所确定。例如，“平行”包括绝对平行和近似平行，其中近似平行的可接受偏差范围例如可以是5°以内偏差；“垂直”包括绝对垂直和近似垂直，其中近似垂直的可接受偏差范围例如也可以是5°以内偏差。“相等”包括绝对相等和近似相等，其中近似相等的可接受偏差范围内例如可以是相等的两者之间的差值小于或等于其中任一者的5％。
本公开的一些实施例提供了一种显示装置，该显示装置被配置为显示图像；例如，可以显示静态图像或动态图像等。示例性地，该显示装置可以是：显示器、电视、广告牌、家电、大面积墙壁、信息查询设备(如电子政务、银行、医院或电力等部门的业务查询设备)、手机、个人数字助理(Personal Digital Assistant，PDA)、数码相机、摄录机或导航仪等。
示例性地，参见图1，显示装置1包括显示面板10、时序控制器20、栅极驱动电路30和源极驱动电路40。
参见图1，显示面板10具有显示区(Active Area)和周边区S。其中，周边区S位于显示区AA至少一侧。示例性地，周边区S可以围绕显示区AA一圈设置。显示面板10可以是OLED(Organic Light Emitting Diode，有机发光二极管)面板、QLED(Quantum Dot Light Emitting Diodes，量子点发光二极管)面板、LCD(Liquid Crystal Display，液晶显示器)面板、微LED(包括：miniLED或microLED)面板等，对此不作过多限制。为了表述简便，以下以显示面板10为OLED面板为例进 行说明。
示例性地，参见图1，显示面板10可以包括多条信号线，例如栅线(Gate Line，GL)，数据线(Data Line，DL)，以及其他驱动控制信号线(例如发光控制信号线)等。其中，栅线可以用来传输栅极驱动信号GDS，数据线被配置为传输数据电压DV(数据电流或数据信号)，驱动控制信号线(例如发光控制信号线)可以用来传输驱动控制信号(例如发光控制信号)。沿第一方向Y依次排布的多条栅线依次为GL1～GLm，沿第二方向X依次排布的多条数据线依次为DL1～DLn，m和n均为正整数。多条栅线彼此平行设置，多条数据线也彼此平行设置，多条栅线和多条数据线交叉设置，例如相互垂直设置。
示例性地，参见图1，显示面板10还可以包括多个子像素P，多个子像素P位于显示区AA。示例性地，多个子像素P可以呈阵列排布。例如，沿第二方向X排列成一排的子像素P称为同一行子像素P，沿第一方向Y排列成一排的子像素P称为同一列子像素P。多个子像素P可以包括被配置为发出第一颜色光线的第一颜色子像素、被配置为发出第二颜色光线的第二颜色子像素和被配置为发出第三颜色光线的第三颜色子像素。例如，第一颜色、第二颜色和第三颜色分别为红色、绿色和蓝色。
示例性地，参见图2，显示面板10的至少一个(例如每个)子像素P包括像素电路110和发光器件L，像素电路110与发光器件L耦接，像素电路110被配置为驱动发光器件L发光。示例性地，多个像素电路110也呈阵列排布，包含像素电路110的子像素P的位置作为该像素电路110的位置。
不同类型的显示面板所采用的发光器件L的类型不同。与显示面板的类型相对应的，发光器件L可以为LED、OLED或QLED等。发光器件L包括阴极和阳极，以及位于阴极和阳极之间的发光功能层。其中，发光功能层可以包括发光层(Emission layer，EML)、位于发光层和阳极之间的空穴传输层(Hole Transporting Layer，HTL)、位于发光层和阴极之间的电子传输层(Election Transporting Layer，ETL)。当然，根据需要在一些实施例中，还可以在空穴传输层HTL和阳极之间设置空穴注入层(Hole Injection Layer，HIL)，可以在电子传输层ETL和阴极之间设置电子注入层(Election Injection Layer，EIL)。
示例性地，阳极例如可由具有高功函数的透明导电材料形成，其电 极材料可以包括氧化铟锡(ITO)、氧化铟锌(IZO)、氧化铟镓(IGO)、氧化镓锌(GZO)氧化锌(ZnO)、氧化铟(In2O3)、氧化铝锌(AZO)和碳纳米管等中的任一种或组合。阴极例如可由高导电性和低功函数的材料形成，其电极材料可以包括镁铝合金(MgAl)和锂铝合金(LiAl)等合金中的任一种或组合，以及镁(Mg)、铝(Al)、锂(Li)和银(Ag)等金属单质中的任一种或组合。发光层的材料可以根据其发射光颜色的不同进行选择。例如，发光层的材料包括荧光发光材料或磷光发光材料。例如，在本公开至少一个实施例中，发光层可以采用掺杂体系，即在主体发光材料中混入掺杂材料来得到可用的发光材料。例如，主体发光材料可以采用金属化合物材料、蒽的衍生物、芳香族二胺类化合物、三苯胺化合物、芳香族三胺类化合物、联苯二胺衍生物和三芳胺聚合物等。
像素电路110的具体结构可以根据实际情况进行设计，本公开的实施例对此不作限定。示例性地，像素电路110可以由晶体管、电容器(Capacitance，简称C)等电子器件组成。晶体管可以为薄膜晶体管(Thin Film Transistor，简称TFT)，或者可以为场效应晶体管(Field Effect Transistor，简称TFE)等。例如，参见图2，像素电路110可以包括两个晶体管(一个开关晶体管T1和一个驱动晶体管T2)和一个电容器C，构成2T1C结构；又例如，像素电路110还可以包括两个以上的晶体管(多个开关晶体管和一个驱动晶体管)和至少一个电容器C，例如，像素电路110可以包括一个电容器C和七个晶体管(六个开关晶体管和一个驱动晶体管)，构成7T1C结构。
参见图2，以像素电路为2T1C结构进行示例说明。发光器件L的一极(例如阳极)与像素电路耦接，发光器件L的另一极(例如阴极)与第二电源电压端ELVSS耦接；该第二电源电压端ELVSS被配置为传输直流电压，例如直流低电压。例如，响应于栅极驱动信号，开关晶体管T1导通，响应于数据信号，驱动晶体管T2的控制极g与漏极d耦接，并将由数据电压施加到驱动晶体管T2的控制极g，第一电源电压端ELVDD与第二电源电压端ELVSS之间的电流通路导通，基于驱动晶体管T2的控制极g的电压与第一电源电压信号(第一电源电压端ELVDD所接收到的信号)之间的电压差产生的驱动电流，通过电流通路传输至发光器件L，驱动发光器件L发光。
示例性地，参见图1，时序控制器20可以接收来自系统(例如，显示装置1中的主板)的初始图像数据ID和同步控制信号TCS，产生栅极 控制信号GCS(Gate Control Signal)、图像数据RGB和源极控制信号SCS。
其中，输入至时序控制器20中的同步控制信号TCS可以包括主时钟信号(或者称为数据采样时钟)、行同步信号(Hsync，简称为HS)、场同步信号(Vsync，简称为VS)和数据使能信号(Data Enable，简称为DE)等多种信号。时序控制器20基于初始图像数据ID和同步控制信号TCS生成图像数据、栅极控制信号GCS和源极控制信号SCS。具体地，图像数据RGB可以是通过校正初始图像数据ID而生成的，例如，图像数据RGB可以是由初始图像数据ID经过图像质量校正、光点校正、颜色特性补偿和/或有源电容补偿等得到的。图像数据RGB可以包括不同子像素P的红色灰度数据、绿色灰度数据和蓝色灰度数据。
示例性地，参见图1，时序控制器20可以将产生的栅极控制信号GCS输出给栅极驱动电路30。栅极驱动电路30接收并响应于栅极控制信号GCS，生成多个栅极驱动信号GDS，并将多个栅极驱动信号GDS分别输出给显示面板中的多条栅线GL1～GLm，以控制与多条栅线GL1～GLm耦接的各行子像素P的选通。其中，栅极控制信号GCS可以包括帧起始(Start Vertical，STV)信号、扫描时钟脉冲(Clock Pulse Vertical，CPV)信号、使能(Output Enable，OE)信号等。其中，STV信号为一帧显示画面扫描开始的起始信号，CPV为栅极驱动电路30的时钟信号，一个周期代表一行栅极驱动信号GDS的输出，OE信号的设置会影响栅极驱动信号GDS的输出波形。
示例性地，栅极驱动电路30可以逐行扫描多行子像素P，即按照从第一行子像素P到最后一行子像素P的顺序，依次向多条栅线GL1～GLm输入栅极驱动信号GDS。
在一种可能的实现方式中，栅极驱动电路30中可以包括至少一个(例如多个)栅极驱动器300，每个栅极驱动器300均与时序控制器20耦接。例如，栅极驱动电路30中包括多个栅极驱动器300，按照多个栅极驱动器300排列的顺序，第一个栅极驱动器300与时序控制器20耦接，其余的栅极驱动器300与前一个栅极驱动器300耦接，即多个栅极驱动器300之间依次级联。具体地，栅极驱动器300可以以芯片的形式安装在显示面板10上，也可以以带载封装(Tape Carrier Package，TCP)或覆晶薄膜(Chip On Film，COF)的形式连接到显示面板10。
在另一种可能的实现方式中，栅极驱动电路30可以包括至少一个 (例如多个)GOA(Gate driver On Array)电路，用于向栅线提供栅极驱动信号GDS，从而有利于减少外接芯片的绑定(Bonding)工序，有利于提升产能并降低产品成本，而且可以使显示装置1的边框更窄，实现更好的显示效果。
示例性地，对显示装置1的驱动方式不作过多限制，显示装置1的驱动方式可以为单边驱动，或者为双边驱动。例如，参见图1，显示装置1的驱动方式为单边驱动，栅极驱动电路30中包括多个栅极驱动器300，沿多条数据线的排布方向(即第二方向X)，多个栅极驱动器300均位于多条数据线的同一侧。
示例性地，继续参见图1，时序控制器20可以将产生的图像数据RGB和源极数据传输控制信号SCS输出给源极驱动电路40。具体地，对时序控制器20将图像数据RGB和源极控制信号SCS输出给源极驱动电路40的信号格式不作过多限制，该信号格式可以为低压差分信号(Low Voltage Differential Signaling，LVDS)、嵌入式显示信号(Embedded Display Port，eDP)、晶体管-晶体管逻辑信号(Transistor to Transistor Logic，TTL)、mini LVDS信号等多种信号格式中的任一种，本领域技术人员可以根据需要自行设置。例如，时序控制器20将图像数据和源极控制信号编码为LVDS信号，然后输出给源极驱动电路40。相较于其他信号格式，LVDS信号具有数据传输速率高、低噪声、低功耗和传输距离远等特点，有利于实现更好的信号传输效果。
示例性地，源极控制信号SCS可以包括行起始信号(Start Horizontal，STH)、行时钟脉冲信号(Clock Pulse Horizontal，CPH)、数据传输控制信号(标记为TP或STB)等多种信号。其中，行起始信号代表一行子像素P数据传输的开始；行时钟脉冲信号为源极驱动电路40的时钟信号；数据传输控制信号用于控制源极驱动电路40将来自时序控制器的图像数据RGB转换为多个数据电压DV，并向显示面板10中的多条数据线DL1～DLn分别输出多个数据电压DV，以向选通的各行子像素P中分别输入多个数据电压DV，从而使得各个子像素P在电场的作用下呈现对应的颜色。具体地，源极驱动电路40可以按照从第一行子像素P到最后一行子像素P的顺序，依次向多行子像素P中分别输入多个数据电压DV。
示例性地，源极驱动电路40中可以包括至少一个(例如一个或多个)源极驱动器400，每个源极驱动电路40均与时序控制器20耦接。源极 驱动器400同样可以以芯片、带载封装或覆晶薄膜等形式进行设置，对此不作过多限制。例如，参见图1，当源极驱动电路40中包括一个源极驱动器400时，显示装置中的多条数据线DL1～DLn均与该源极驱动器400耦接。又例如，源极驱动电路40中包括多个源极驱动器400，显示装置中的多条数据线DL1～DLn可以划分为多个数据线组(图中未示出)，每个数据线组中的多条数据线与同一个源极驱动器400耦接。
继续参见图1，显示装置1朝着大尺寸、高分辨率的方向发展，随着显示装置1尺寸的增大，沿第二方向X，栅线的长度增大，沿第一方向Y，数据线的长度增大，相应的，栅线和数据线的电阻值也增大。栅线和数据线交叉设置，随着显示装置1分辨率的提高，栅线和数据线的数量增多，栅线和数据线之间交叉位置的数量增多，寄生电容增大。电阻值和寄生电容的增大使得栅线和数据线均具有较大的电阻电容负载(RC Loading)，在信号传输过程中，较大的RC Loading会使所传输信号的强度减弱，出现较大程度的信号衰减。对栅线而言，较大的RC Loading会导致栅线上远离栅极驱动电路30的位置处，栅极驱动信号GDS的波形严重失真。
示例性地，参见图1，多条数据线DL1～DLn包括第一数据线DLa和第二数据线DLb，同一行子像素P中包括第一子像素P1和第二子像素P2，其中，第一子像素P1与第一数据线DLa耦接，第二子像素P2与第二数据线DLb耦接。沿第二方向X，第一数据线DLa位于第二数据线DLb靠近栅极驱动电路30的一侧，第一数据线DLa和第二数据线DLb可以相邻，也可以两者之间还间隔有至少一条(例如一条或多条数据线)。图1以第一数据线DLa和第二数据线DLb相邻作为示例，沿第二方向X，第一子像素P1也位于第二子像素P2靠近栅极驱动电路30的一侧。第一子像素P1和第二子像素P2与同一条栅线GL1耦接，其中，与第一子像素P1相耦接的栅线部分为第一栅线部分LP1，与第二子像素P2相耦接的栅线部分为第二栅线部分LP2。对这条栅线GL1而言，由于RC Loading的存在，第二栅线部分LP2所传输的栅极驱动信号GDS的衰减程度，大于第一栅线部分LP所传输的栅极驱动信号GDS的衰减程度。
结合前述的图2中的像素电路，当栅极驱动信号GDS的电位高于像素电路中开关晶体管T1的开启电压Von时，开关晶体管的源极和漏极导通，从而能够向子像素P中写入数据电压DV，而当栅极驱动信号GDS的电位低于像素电路中开关晶体管的关闭电压Voff时，开关晶体管关闭， 数据电压DV无法写入。参见图1和图3，对第e条栅线GLe而言，栅线GLe中的第一栅线部分LP1和第二栅线部分LP2所传输的栅极驱动信号GDS的波形如图4所示，e为正整数，且e≤m-1。栅线GLe中的第一栅线部分LP1所传输的栅极驱动信号GDS的电位达到Von所需的时长为t1，而由于RC Loading引起的信号衰减，栅线GLe中的第二栅线部分LP2所传输的栅极驱动信号GDS的电位达到Von所需的时长为t2，t2＞t1，也即相较于与第一栅线部分LP1耦接的第一子像素P1中的开关晶体管(以下称为第一开关晶体管)，与第二栅线部分LP2耦接的第二子像素P2中的开关晶体管(以下称为第二开关晶体管)的开启延迟，使得数据电压DV无法正常写入第二子像素P2中，在此情况下，第二子像素P2的充电率低于第一子像素P1的充电率，充电不足的第二子像素P2的发光亮度低于第一子像素P1的发光亮度，最终对显示效果产生不良影响。
此外，RC Loading引起的信号衰减同样会影响到开关晶体管的关闭。继续参见图1和图3，第一开关晶体管关闭所需的时长为t3，第二开关晶体管关闭所需的时长为t4，t4＞t3，也即相较于第一开关晶体管，第二开关晶体管的关闭延迟，导致第e+1行子像素P的数据电压DV写入时，可能会同时向第e行子像素P中误写入第e+1行子像素P的数据电压DV，使得显示装置1出现显色不均的风险增大，不利于显示质量的提升。
为了降低出现前述的问题的风险，参见图4，本公开的一些实施例提供了一种源极驱动器400，包括数据缓冲器420，数模转换器440和输出缓冲器450等电路模块。应当理解的是，本公开中仅介绍了与本公开实施例有关的电路模块，而省略了其他无关的电路模块。
示例性地，参见图4，数据缓冲器420被配置为接收和锁存图像数据RGB，并响应于数据传输控制信号STB的第一触发时刻L1输出图像数据RGB。具体地，数据缓冲器420包括数据接收器421和数据缓存器422，数据接收器421和数据缓存器422是并行工作的，数据接收器421依序取好第i-1(i为正整数，i≤m)行子像素的图像数据RGB后，将这些图像数据RGB同时送入数据缓存器422。数据缓存器422存储好第i-1行子像素的图像数据RGB后经后续电路模块的处理，把第i-1行子像素的数据电压输出给第i-1行子像素。与此同时，数据接收器421接收第i行子像素的图像数据RGB。数据接收器421和数据缓存器422并行工作， 可以提高源极驱动器400的工作效率。具体地，数据接收器421可以包括用于寄存图像数据RGB的多个数据接收单元(图中未示出)，数据缓存器422可以包括用于输出图像数据RGB的多个数据缓存单元(图中未示出)。多个数据接收单元的数目和与该源极驱动器400耦接的数据线DL的条数以及图像数据RGB的输入位数有关。例如，该源极驱动器400与n条数据线DL均耦接，每个子像素的色深为8bit，则需要的输入缓冲单元的个数为8n个，同理，需要的输出端缓冲单元的个数也为8n个。
示例性地，参见图4和图5，数据传输控制信号STB可以是控制命令(也可以说是控制命令数据)，包括：控制命令开始时长(STB Start)和控制命令脉宽时长(STB Width)。同时，数据传输控制信号STB具有第一触发时刻L1和第二触发时刻L2。其中，控制命令开始时长从前一行子像素P的最后一个数据电压DV输出完成的时刻开始，到数据缓冲器420开始输出后一行子像素P的图像数据RGB的时刻结束。控制命令脉宽时长从开始输出后一行子像素P的图像数据RGB的时刻开始，到开始向显示面板输出后一行子像素P的数据电压DV的时刻结束。控制命令开始时长的结束时刻，与控制命令脉宽时长的开始时刻同时达到，该到达时刻为数据传输控制信号STB的第一触发时刻L1；控制命令脉宽时长的结束时刻，为数据传输控制信号STB的第二触发时刻L2。在第一触发时刻L1，锁存输入到源极驱动器400中的图像数据RGB，在第二触发时刻L2，将图像数据RGB转换得到的多个数据电压DV输出给显示面板。
控制命令开始时长与控制命令脉宽时长两者的比特数可以相同，也可以不同。例如，控制命令开始时长可以为一个10bit的数字信号，控制命令脉宽时长也为一个10bit的数字信号，两者均对应2^10(1024)种持续时长。其中，控制命令开始时长例如为480，则可以表示控制命令开始时长是480个单位时长；控制命令脉宽时长例如为960，则可以表示控制命令脉宽时长是960个单位时长，一个单位时长可以是一个时钟的周期。又例如，控制命令开始时长可以为一个8bit的数字信号，对应2^8(256)种持续时长；控制命令脉宽时长为一个10bit的数字信号，对应2^10(1024)种持续时长。其中，控制命令开始时长例如为255，控制命令脉宽时长例如为600。
示例性地，参见图4和图5，数据传输控制信号STB还可以为控制数据缓冲器420的脉冲信号，数据传输控制信号STB具有第一触发时刻 L1和第二触发时刻L2，在第一触发时刻L1锁存输入到源极驱动器400中的图像数据RGB，在第二触发时刻L2将图像数据RGB转换得到的多个数据电压DV输出给显示面板。其中，数据传输控制信号STB从第一电平V1到第二电平V2的边沿为数据传输控制信号STB的第一触发时刻L1，从第二电平V2到第一电平V1的边沿为数据传输控制信号STB的第二触发时刻L2。第一电平V1与第二电平V2的电平高低是相对的，例如，当第一电平V1为高电平时，第二电平V2为低电平。第一电平V1可以为高电平，也可以为低电平，图5中以第一电平V1为低电平，第二电平V2为高电平为例进行说明，在此情况下，数据传输控制信号STB的第一触发时刻L1为上升沿，第二触发时刻L2为下降沿。
示例性地，数模转换器440被配置为接收数据缓冲器420输出的图像数据RGB，并将图像数据RGB转换成多个具有模拟形式的数据电压DV(也可以称为灰阶电压)。具体地，数模转换器440通常可以通过选择图像数据RGB对应的由灰阶电压生成电路(未示出)生成的模拟电压而施行数模转换。数模转换器440可以包括多个数模转换单元(图中未示出)，多个数模转换单元可以将图像数据RGB转换成对应的多个数据电压DV。依照前述示例，数模转换器440可以包括8n个数模转换单元。
示例性地，参见图4和图5，输出缓冲器450包括多个输出通道OP，输出缓冲器450被配置为基于数据传输控制信号STB的第二触发时刻L2，将多个数据电压DV通过多个输出通道OP分别输出。具体地，输出缓冲器450中的输出通道OP的数目，和与该源极驱动器400耦接的数据线DL的条数相等。例如，该源极驱动器400与n条数据线DL均耦接，那么，输出缓冲器450中的输出通道OP的数目为n个。至少一个(例如多个)输出通道OP分别输出数据电压DV的时刻，不早于数据传输控制信号STB的第二触发时刻L2的到达时刻。
示例性地，继续参见图4，除了前述的数据缓冲器420，数模转换器440和输出缓冲器450以外，源极驱动器400还可以包括控制信号接收器410。其中，控制信号接收器410被配置为接收和分离经过时序控制器20所编码的图像数据RGB和源极控制信号SCS，并将分离出的图像数据RGB和源极控制信号SCS分别传输给源极驱动器400中的相应电路模块。具体地，控制信号接收器410可以为接口，接口的类型可以根据时序控制器20所输出的信号格式进行设置，例如，当时序控制器20输出的为eDP信号时，控制信号接收器410为eDP接口；当时序控制器 20输出的为TTL信号时，控制信号接收器410为TTL接口；当时序控制器20输出的为LVDS信号时，控制信号接收器410为LVDS接口。接口的数据口(Port)的类型和个数可以根据实际需要进行设置，本公开对此不作过多限制。
示例性地，参见图4，源极驱动器400还可以包括命令接收器430，命令接收器430被配置为接收来自控制信号接收器410的源极控制信号SCS，并将源极控制信号SCS所包括的多种信号分别传输给相应的电路模块。
示例性地，参见图4和图5，图像数据RGB和源极控制信号SCS可以分时传输。例如，在时段T1中可以先传输一行子像素(例如第f行，f为正整数，f≤n-1)的源极控制信号SCS，在之后的时段T2中再传输第f行子像素的图像数据RGB；在时段T3中可以传输第f+1行子像素的源极控制信号SCS，在之后的时段T4中再传输第f+1行子像素的图像数据RGB，以此类推。T5时段(时长由数据传输控制信号STB的控制命令开始时长决定)为第f-2行子像素的最后一个数据电压DV输出完成后的缓冲时段，响应于数据传输控制信号STB的第一触发时刻L1，数据缓冲器420中的数据缓存器422向数模转换器440输出第f-1行子像素的图像数据RGB。在T6时段(时长由数据传输控制信号STB的控制命令脉宽时长决定)，数模转换器440将接收到的图像数据RGB转换成多个数据电压DV，并将转换得到的多个数据电压DV输出给输出缓冲器450。基于数据传输控制信号STB的第二触发时刻L2，输出缓冲器450开始输出第f-1行子像素的数据电压DV。在T7时段，输出缓冲器450中通过多个输出通道将第f-1行子像素的多个数据电压DV分别输出给各条数据线DL。T8时段～T10时段同理，进行第f行子像素P图像数据RGB的处理。
当栅线所传输的栅极驱动信号由于RC Loading出现较严重的波形失真时，相较于与该栅线耦接的第一子像素中的第一开关晶体管的开启和关闭，与该栅线耦接的第二子像素中的第二开关晶体管的开启和关闭均延迟。此时，示例性地，参见图4和图5，可以设置至少两个输出通道OP的输出时刻具有时间差，其中，任意两条数据线DL接收到数据电压DV的时间差可以相同，也可以不同。具体地，多个输出通道OP包括第一输出通道OP1和第二输出通道OP2，第一输出通道OP1通过第一数据线DLa与第一子像素耦接，第二输出通道OP2通过第二数据线DLb与 第二子像素耦接，第一输出通道OP1的输出时刻(以下称为第一时刻)和第二输出通道OP2的输出时刻(以下称为第二时刻)具有时间差。例如，沿第二方向X，第一子像素与第二子像素相邻排布，第一数据线DLa与第二数据线DLb也相邻排布。第一数据线DLa接收到数据电压DV的时刻早于第二数据线DLb接收到数据电压DV的时刻，且两者之间的时间差为ta，也即第二时刻较第一时刻延迟ta。ta可以根据第二开关晶体管的开启时刻相较于第一开关晶体管的开启时刻所延迟的时长进行设置，也可以根据每条栅线的线电阻或者对应的RC Loading进行调整。
调整后的显示装置中，沿第二方向X相邻排布的两个子像素接收到数据电压DV的时间差，与这两个子像素中的开关晶体管的开启时刻之间的时间差基本一致，进而能够减小这两个子像素的充电率差异，使发光亮度较为均一。此外，前一行子像素的最后一个数据电压DV输出后，后一行的数据电压DV才会进行输出，当前一行子像素的数据电压DV的输出存在延迟时，后一行子像素的数据电压DV的输出也会相应延迟，从而当前一行子像素的开关晶体管关闭延迟时，后一行子像素的数据电压DV不会误写入前一行子像素中，能够降低显示装置显色不均的风险，有利于提升显示质量。
示例性地，参见图4，沿多个输出通道OP的排布方向，任意相邻的两个输出通道OP的输出时刻的时间差相同。也即沿第二方向X，相邻排布的任意两条数据线DL接收到数据电压DV的时间差均相同(例如均为ta)，在提升显示效果的前提下，该设置能够有利于简化源极驱动器400的设计。
示例性地，参见图4和图6，源极驱动器400还包括至少一个(例如一个)延时控制器460，延时控制器460被配置为基于数据传输控制信号STB，输出多个输出使能信号EN。输出缓冲器450被配置为响应于多个输出使能信号EN，将多个数据电压DV通过多个输出通道OP分别输出。沿第二方向X依次排布的多条数据线DL1～DLn与多个输出通道OP分别对应耦接，多个输出通道OP响应的多个输出使能信号EN分别为EN1～ENn。
对多个输出使能信号EN的获取方式不作过多限制，例如，延时控制器460中可以存储有多个输出使能信号EN，延时控制器460接收并响应于来自命令接收单元430的数据传输控制信号STB的第二触发时刻L2，将存储的多个输出使能信号EN输出给输出缓冲器450，以控制多个 输出通道OP的输出。又例如，延时控制器460可以依据接收到的数据传输控制信号STB，将每个输出通道OP的延迟信息反映在数据传输控制信号中，生成多个输出使能信号EN。
示例性地，输出使能信号EN从第三电平V3到第四电平V4的边沿为输出使能信号EN的第一触发时刻L3，从第四电平V4到第三电平V3的边沿为输出使能信号EN的第二触发时刻L4。与前述类似的，第三电平V3与第四电平V4的电平高低是相对的。可以是第三电平V3为高电平，第四电平V4为低电平；或者第三电平V3为低电平，第四电平V4为高电平。本公开中以第三电平V3为低电平，第四电平V4为高电平为例进行说明，在此情况下，输出使能信号EN的第一触发时刻L3为上升沿，输出使能信号EN的第二触发时刻L4为下降沿。输出缓冲器450中的每个输出通道OP可以响应于一个输出使能信号EN的信号触发时刻输出数据电压DV，多个输出通道响应于多个输出使能信号EN的多个信号触发时刻分别输出多个数据电压DV。多个信号触发时刻可以均为输出使能信号EN的上升沿，或者均为输出使能信号EN的下降沿，对此不作过多限制。
示例性地，可以设置多个输出使能信号EN的波形均相同，且至少两个输出使能信号EN具有相位差。例如，参见图6，延时控制器输出的多个输出使能信号EN的波形均相同，输出缓冲器中的每个输出通道可以响应于一个输出使能信号EN的第二触发时刻L4输出数据电压，至少一个(例如一个)输出使能信号EN的第一触发时刻L3与数据传输控制信号STB的第一触发时刻L1同时到达。沿多个输出通道的排布方向，任意相邻的两个输出通道输出数据电压的时刻具有时间差，任意相邻的两个输出通道所响应的输出使能信号EN的第一触发时刻L3和第二触发时刻L4均错开，且两个第一触发时刻L3的到达时刻之间的时间差，等于两个第二触发时刻L4的到达时刻之间的时间差。具体地，输出使能信号EN1的第一触发时刻L3与数据传输控制信号STB的第一触发时刻L1对齐，输出使能信号EN1的第二触发时刻L4与数据传输控制信号STB的第二触发时刻L2对齐，输出使能信号EN1～ENn的第二触发时刻L4逐级延迟，延迟时长均为tb。相当于延时控制器按照预设的延时信息，对接收到的数据传输控制信号STB进行了延迟处理并输出。又例如，参见图7，延时控制器460输出的多个输出使能信号EN的波形均相同，输出缓冲器中的每个输出通道可以响应于一个输出使能信号EN的第一触 发时刻L3输出数据电压，至少一个(例如一个)输出使能信号EN的第一触发时刻L3与数据传输控制信号STB的第二触发时刻L2同时到达。沿多个输出通道的排布方向，任意相邻的两个输出通道输出数据电压的时刻具有时间差，任意相邻的两个输出通道所响应的输出使能信号EN的第一触发时刻L3和第二触发时刻L4均错开，且两个第一触发时刻L3的到达时刻之间的时间差，等于两个第二触发时刻L4的到达时刻之间的时间差。具体地，输出使能信号EN1的第一触发时刻L3与数据传输控制信号STB的第二触发时刻L2对齐，输出使能信号EN1～ENn的第二触发时刻L4逐级延迟，延迟时长均为tc。
又示例地，也可以设置至少两个输出使能信号EN的波形不相同，且波形不相同的任意两个输出使能信号EN控制输出的两个信号触发时刻的到达时刻具有时间差。例如，参见图8，延时控制器输出的任意两个输出使能信号EN的波形不相同，输出缓冲器中的每个输出通道可以响应于一个输出使能信号EN的第二触发时刻L4输出数据电压，多个输出使能信号EN的第一触发时刻L3，与数据传输控制信号STB的第一触发时刻L1同时到达，至少一个(例如多个)输出使能信号EN的第二触发时刻L4的到达时刻，晚于所述数据传输控制信号STB的第二触发时刻L2的到达时刻。具体地，输出使能信号EN1～ENn的第一触发时刻L3与数据传输控制信号STB的第一触发时刻L1均同时到达，输出使能信号EN1的第二触发时刻L4与数据传输控制信号STB的第二触发时刻L2同时到达，输出使能信号EN1～ENn的第二触发时刻L4逐级延迟，延迟时长均为td，同样可以实现不同输出通道延迟不同的时长输出数据电压，从而使得同一行中的多个子像素的充电率较为均一。
本公开的一些实施例中提供了一种显示装置，该显示装置包括前述的源极驱动器，且多个输出使能信号的设置如前所述。显示装置的结构如图1所示，显示装置1的驱动方式为单边驱动时，结合图9，沿多条数据线DL的排布方向，多条数据线DL分别接收到多个数据电压DV的时刻，由显示装置1的一侧到另一侧逐级延迟，具体地，由显示装置1设置有栅极驱动电路30的一侧，向显示装置1未设置栅极驱动电路30的一侧逐级延迟。
又示例地，显示装置包括前述的源极驱动器，且多个输出使能信号的设置同样如前所述。显示装置的结构如图10所示，显示装置1的驱动方式为双边驱动，显示装置1中包括时序控制器20和多个栅极驱动器 300，多个栅极驱动器300均与时序控制器20耦接。沿第二方向X，多个栅极驱动器300包括位于显示装置1一侧的至少一个(例如多个)第一栅极驱动器310，和位于显示装置1另一侧的至少一个(例如多个)第二栅极驱动器320，一个第一栅极驱动器310和一个第二栅极驱动器320与同一条栅线耦接。多个第一栅极驱动器310构成一个第一栅极驱动电路31，多个第二栅极驱动器320构成一个第二栅极驱动电路32。对一条栅线而言，栅极驱动信号GDS从两端输入，有利于减小栅线远离第一栅极驱动电路31和第二栅极驱动电路32的位置处的信号衰减。
当显示装置1的驱动方式为双边驱动时，沿多条数据线DL1～DLn的排布方向，从显示装置1的两侧到中间，同一行中的多个子像素P中开关晶体管开启和关闭的延迟逐渐增大，相应的，子像素P的充电率也从显示装置1的两侧到中间逐渐减小，同样会出现前述远离栅极驱动电路30的子像素P充电率不足、后一行子像素P的数据电压DV误写入前一行子像素P中的问题。
因此，为了避免出现前述问题，当源极驱动器400与n条数据线DL1～DLn耦接，n为正整数且为偶数时，参见图11，可以设置输出通道向数据线DL1～DLn/2输出数据电压的时刻逐级延迟，输出通道向数据线DLn～DLn+1/2输出数据电压的时刻也逐级延迟，相应的，多条数据线DL1～DLn分别接收到多个数据电压的时刻，由显示装置的两侧向中间对称性地逐级延迟。当源极驱动器与n条数据线DL1～DLn耦接，n为正整数且为奇数时，参见图12，可以设置输出通道向数据线DL1～DLn+1/2输出数据电压的时刻逐级延迟，输出通道向数据线DLn～DLn+1/2输出数据电压的时刻逐级延迟。
示例性地，参见图10，显示装置1中的多条栅线GL1～GLm可以具有相等的线电阻，与之类似的，显示装置1中的多条数据线DL1～DLn也可以具有相等的线电阻。以栅线为例，显示装置1中多条栅线GL1～GLm的线电阻相等时，当根据RC Loading设置一条数据线接收到数据电压DV所需延迟的时长时，由于栅线与数据线交叉位置处的RC Loading，与该交叉位置和栅极驱动电路30之间的距离的对应关系近似为线性，从而有利于降低多条数据线DL1～DLn分别对应的延迟时间的设计难度。
本公开的另一些实施例中，参见图13，显示装置1包括源极驱动电路40，源极驱动电路40中包括多个源极驱动器400，多个源极驱动器 400均与时序控制器20耦接。例如，参见图14，多个源极驱动器400可以均与时序控制器20连接，时序控制器20向各源极驱动器400输出图像数据RGB和源极驱动信号SCS，各源极驱动器400根据接收到的源极驱动信号SCS分离出所需的数据传输控制信号，并响应于各自的数据传输控制信号进行图像数据RGB的转换和数据电压的输出。又例如，参见图15，源极驱动电路40中包括相互级联的多个源极驱动器400，至少一个(例如一个)源极驱动器400与时序控制器20连接，时序控制器20输出的图像数据RGB和源极驱动信号SCS从该源极驱动器400向其他源极驱动器400连续传输。除上述的两种设置方式外，多个源极驱动器400与时序控制器20还可以采用其他可行的连接方式，本公开实施例对此不作过多限制。
示例性地，参见图13，显示面板10中的多条数据线DL1～DLn可以划分为多个数据线组(图中未示出)，每个数据线组中的多条数据线DL1～DLn与同一个源极驱动器400耦接。多个源极驱动器400包括第一源极驱动器401和第二源极驱动器402。其中，时序控制器20向第一源极驱动器401提供第一图像数据RGB1和第一源极控制信号SCS1，第一源极控制信号SCS1包括第一数据传输控制信号，向第二源极驱动器402提供第二图像数据RGB2和第二源极驱动信号SCS2，第二源极驱动信号SCS2包括第二数据传输控制信号。第一源极驱动器401和第二源极驱动器402分别响应于各自的数据传输控制信号将图像数据RGB转换为多个数据电压DV，并向显示面板10输出多个数据电压DV。具体地，对第一源极驱动器401和第二源极驱动器402的相对位置不做过多限制，两者可以相邻，也可以不相邻，沿第二方向X，第一源极驱动器401可以位于第二源极驱动器402的左侧，也可以位于第二源极驱动器402的右侧。显示面板10中的多个数据线组包括第一数据线组和第二数据线组，第一数据线组中的多条数据线与第一源极驱动器401耦接，第二数据线组中的多条数据线与第二源极驱动器402耦接。第一源极驱动器401可以同时向第一数据线组中的多条数据线输出多个第一数据电压，第二源极驱动器402也可以同时向第二数据线组中的多条数据线输出多个第二数据电压。
为了表述简便，继续参见图13，以下以显示装置1的驱动方式为单边驱动，第一源极驱动器401和第二源极驱动器402相邻，第一源极驱动器401位于第二源极驱动器402靠近栅极驱动电路30的一侧，且第一 源极驱动器401为多个源极驱动器400中最靠近栅极驱动电路30的一者为例进行说明。
示例性地，参见图16，第一源极驱动器401所响应的数据传输控制信号STB为第一数据传输控制信号STB1，第二源极驱动器402所响应的数据传输控制信号STB为第二数据传输控制信号STB2。第一数据传输控制信号STB1和第二数据传输控制信号STB2均具有第一触发时刻L1和第二触发时刻L2。
第一源极驱动器401可以响应于第一数据传输控制信号STB1的第一触发时刻L1将锁存的第一图像数据转换成多个第一数据电压，可以基于第一数据传输控制信号STB1的第二触发时刻L2，输出多个第一数据电压。与第一源极驱动器401类似的，第二源极驱动器402可以响应于第二数据传输控制信号STB2的第一触发时刻L1，将锁存的多个第二图像数据转换成多个第二数据电压，基于第二数据传输控制信号STB2的第二触发时刻L2，输出多个第二数据电压。其中，继续参见图16，第一数据传输控制信号STB1的第二触发时刻L2与第二数据传输控制信号STB2的第二触发时刻L2具有时间差。例如，第二数据传输控制信号STB2的第二触发时刻L2比第一数据传输控制信号STB1的第二触发时刻L2延迟，延迟的时长为t，该延迟时长可以根据每条栅线的线电阻或者对应的RC Loading进行调整。
参见图13和图17，显示装置1中的多个子像素P包括在先子像素Pc和在后子像素Pd，沿第二方向X，与第一源极驱动器401和第二源极驱动器402分别耦接的多条数据线DL(分别构成第一数据线组和第二数据线组)中，排布位置相同的两条数据线DL分别为在先数据线DLc和在后数据线DLd，在先子像素Pc与在先数据线DLc耦接，在后子像素Pd与在后数据线DLd耦接，在先数据线DLc传输在先数据电压DVc，在后数据线DLd传输在后数据电压DVd。例如，沿第二方向X，在先数据线DLc为第一数据线组中的第一条数据线，那么在后数据线DLd则为第二数据线组中的第一条数据线。当在后子像素Pd中的开关晶体管的开启时刻，与在先子像素Pc中的开关晶体管的开启时刻之间的时间差为t时，第二数据传输控制信号STB2的第二触发时刻L2比第一数据传输控制信号STB1的第二触发时刻L2延迟，且延迟时长也为t，从而能够减小这两个子像素的充电率差异，使其发光亮度较为均一。此外，前一行子像素P的多个数据电压DV的输出延迟，后一行子像素P的多个数据 电压DV的输出也会相应延迟，从而当前一行子像素P的开关晶体管关闭延迟时，后一行子像素P的数据电压DV不会误写入前一行子像素P中，能够降低显示装置1显色不均的风险。
对第一数据传输控制信号STB1和第二数据传输控制信号STB2的具体波形不作过多限制，只要限制第二数据传输控制信号STB2的第二触发时刻L2比第一数据传输控制信号STB1的第二触发时刻L2延迟即可。例如，参见图16，第一数据传输控制信号STB1的波形与第二数据传输控制信号STB2的波形不相同，第一数据传输控制信号STB1的第一触发时刻L1与第二数据传输控制信号STB2的第一触发时刻L1同时到达，第二数据传输控制信号STB2的第二触发时刻L2比第一数据传输控制信号STB1的第二触发时刻L2延迟t。又例如，参见图17，第一数据传输控制信号STB1与第二数据传输控制信号STB2的波形相同，且两者具有相位差，第一数据传输控制信号STB1的第一触发时刻L1与第二数据传输控制信号STB2的第一触发时刻L1具有时间差。具体地，第二数据传输控制信号STB2的第一触发时刻L1比第一数据传输控制信号STB1的第一触发时刻L1延迟，第二数据传输控制信号STB2的第二触发时刻L2也比第一数据传输控制信号STB1的第二触发时刻L2延迟，延迟时长均为t。
参见前述，第一源极驱动器中可以包括显示数据接收器，数据缓存器，数模转换器和输出缓冲器等电路模块，还可以包括其他电路模块，第二源极驱动器中所具有的电路模块与第一源极驱动器一致，在此不再赘述。
示例性地，第一源极驱动器包括输出缓冲器(以下称为第一输出缓冲器)，第一输出缓冲器包括多个输出通道。第一输出缓冲器被配置为基于第一数据传输控制信号的第二触发时刻，将多个第一数据电压通过多个输出通道分别输出，其中，至少两个输出通道的输出时刻具有时间差。例如，沿一输出缓冲器中多个输出通道的排布方向，任意相邻的两个输出通道输出第一数据电压的时刻具有时间差。第二源极驱动器的输出缓冲器(以下称为第二输出缓冲器)也包括多个输出通道，第二输出缓冲器被配置为基于第二数据传输控制信号的第二触发时刻，将多个第二数据电压通过多个输出通道分别输出，沿第二输出缓冲器中多个输出通道的排布方向，任意相邻的两个输出通道输出第二数据电压的时刻具有时间差。上述设置以单个输出通道为单位进行延迟时长的调整，使得 每个源极驱动器内部具有相对连续的输出延迟变化，能够对延迟时长进行精细调整，从而有效减小同一行中的多个子像素之间的充电率差异，提升显示效果。
示例性地，沿多个输出通道的排布方向，任意相邻的两个输出通道的输出时刻的时间差相同。也即沿第二方向X，相邻排布的任意两条数据线接收到数据电压的时间差均相同，在以单个输出通道为单位进行延迟时长的精细调整从而提升显示效果的前提下，该设置有利于简化源极驱动器的设计。任意相邻的两个输出通道的输出时刻的时间差，可以依据第一数据传输控制信号的第二触发时刻与第二数据传输控制信号的第二触发时刻之间的时间差进行确定。例如，参见图18，第一数据传输控制信号STB1的第二触发时刻L2与第二数据传输控制信号STB2的第二触发时刻L2之间的时间差为t，第一数据线组中第一数据线的条数，与第二数据线组中第二数据线的条数相等，均为k条，沿第二方向X，相邻排布的任意两条数据线接收到数据电压的时间差均相同。第一数据组中相邻排布的任意两条第一数据线接收到第一数据电压的时间差为t/k，第二数据组中相邻排布的任意两条第二数据线接收到第二数据电压的时间差为t/k，沿第二方向X，第二数据组中的第一条第二数据线接收到第二数据电压的时刻，与第一数据组中的第k条第一数据线接收到第一数据电压的时刻之间的时间差也为t/k。
示例性地，第一源极驱动器还包括至少一个(例如一个)延时控制器(以下称为第一延时控制器)，第一延时控制器被配置为基于第一数据传输控制信号，输出多个输出使能信号。第一输出缓冲器被配置为响应于多个输出使能信号，将多个第一数据电压通过多个输出通道分别输出。对多个输出使能信号的获取方式不作过多限制，例如，第一延时控制器中可以存储有多个输出使能信号，第一延时控制器接收并响应于来自命令接收单元的第一数据传输控制信号的第二触发时刻，将存储的多个输出使能信号输出给第一输出缓冲器，以控制多个输出通道的输出。又例如，第一延时控制器可以依据接收到的第一数据传输控制信号，将每个输出通道的延迟信息反映在第一数据传输控制信号中，来生成多个输出使能信号。
可以设置多个输出使能信号的波形均相同，且至少两个输出使能信号的波形具有相位差。在此前提下，示例性地，参见图18，第一输出缓冲器中的每个输出通道可以响应于一个输出使能信号的第二触发时刻 L4输出第一数据电压，沿多个输出通道的排布方向，任意相邻的两个输出通道输出数据电压的时刻具有时间差。至少一个(例如一个)输出使能信号的第一触发时刻L3与数据传输控制信号的第一触发时刻L1同时到达，任意相邻的两个输出通道所响应的输出使能信号的第一触发时刻L3和第二触发时刻L4均错开，且两个第一触发时刻L3的到达时刻之间的时间差，等于两个第二触发时刻L4的到达时刻之间的时间差。沿第二方向X，多条第一数据线接收到多个第一数据电压的时刻逐级延迟，延迟时长为t/k。又示例地，参见图19，第一输出缓冲器中的每个输出通道可以响应于一个输出使能信号的第一触发时刻L3输出第一数据电压，沿多个输出通道的排布方向，任意相邻的两个输出通道输出数据电压的时刻具有时间差。至少一个(例如一个)输出使能信号的第一触发时刻L3与数据传输控制信号的第二触发时刻L2同时到达，任意相邻的两个输出通道所响应的输出使能信号的第一触发时刻L3和第二触发时刻L4均错开，且沿第二方向X，多条第一数据线接收到多个第一数据电压的时刻逐级延迟，延迟时长为t/k。
示例性地，也可以设置至少两个输出使能信号的波形不相同，且波形不相同的任意两个输出使能信号控制输出的两个信号触发时刻的到达时刻具有时间差。例如，参见图20，第一延时控制器输出的任意两个输出使能信号的波形不相同，多个输出使能信号的第一触发时刻L3，与第一数据传输控制信号STB1的第一触发时刻L1同时到达，至少一个(例如多个)输出使能信号的第二触发时刻L4的到达时刻，晚于第一数据传输控制信号STB1的第二触发时刻L2的到达时刻，沿第二方向X，多条第一数据线接收到多个第一数据电压的时刻逐级延迟，延迟时长为t/k。
与第一源极驱动器类似的，第二源极控制器也可以包括至少一个(例如一个)延时控制器(以下称为第二延时控制器)，第二延时控制器以及第二延时控制器所生成的多个输出使能信号的具体设置与第一延时控制器类似，在此不再赘述。
本公开的一些实施例中提供了一种显示装置，该显示装置包括前述的源极驱动电路，且多个输出使能信号的设置如前所述。当显示装置的驱动方式为单边驱动时，触发时刻多条数据线的排布方向，多条数据线分别接收到多个数据电压的时刻，由显示装置的一侧到另一侧逐级延迟；当显示装置的驱动方式为双边驱动时，多条数据线分别接收到多个数据电压的时刻，由显示装置的两侧向中间对称性地逐级延迟。
本公开的一些实施例中提供了一种源极驱动器的驱动方法，用于对前述任一实施例中的源极驱动器进行驱动。该源极驱动器的驱动方法包括：源极驱动器接收和锁存图像数据，并响应于数据传输控制信号的第一触发时刻输出图像数据。源极驱动器将图像数据转换成多个数据电压，并基于数据传输控制信号的第二触发时刻，将多个数据电压通过分别输出。其中，至少两个数据电压的输出时刻具有时间差。
本公开的一些实施例中提供了一种源极驱动电路的驱动方法，用于对前述任一实施例中的源极驱动电路进行驱动。该源极驱动电路的驱动方法包括：第一源极驱动器响应于第一数据传输控制信号的第一触发时刻，将锁存的第一图像数据转换成多个第一数据电压，并基于第一数据传输控制信号的第二触发时刻，输出多个第一数据电压。第二源极驱动器响应于第二数据传输控制信号的第一触发时刻，将锁存的多个第二图像数据转换成多个第二数据电压，并基于第二数据传输控制信号的第二触发时刻，输出多个第二数据电压。其中，第一数据传输控制信号的第二触发时刻与第二数据传输控制信号的第二触发时刻具有时间差。
本公开的一些实施例提供了一种计算机可读存储介质(例如，非暂态计算机可读存储介质)，该计算机可读存储介质中存储有计算机程序指令，计算机程序指令在计算机(例如前述的任一种显示装置)上运行时，使得计算机执行如上述实施例中任一实施例所述的源极驱动器的驱动方法或者源极驱动电路的驱动方法。
示例性的，上述计算机可读存储介质可以包括，但不限于：磁存储器件(例如，硬盘、软盘或磁带等)，光盘(例如，CD(Compact Disk，压缩盘)、DVD(Digital Versatile Disk，数字通用盘)等)，智能卡和闪存器件(例如，EPROM(Erasable Programmable Read-Only Memory，可擦写可编程只读存储器)、卡、棒或钥匙驱动器等)。本公开描述的各种计算机可读存储介质可代表用于存储信息的一个或多个设备和/或其它机器可读存储介质。术语“机器可读存储介质”可包括但不限于，无线信道和能够存储、包含和/或承载指令和/或数据的各种其它介质。
本公开的一些实施例还提供了一种计算机程序产品。该计算机程序产品包括计算机程序指令，在计算机(例如前述的任一种显示装置)上执行该计算机程序指令时，该计算机程序指令使计算机执行如上述实施例所述的源极驱动器的驱动方法或者源极驱动电路的驱动方法。
本公开的一些实施例还提供了一种计算机程序。当该计算机程序在 计算机(例如前述的任一种显示装置)上执行时，该计算机程序使计算机执行如上述实施例所述的源极驱动器的驱动方法或者源极驱动电路的驱动方法。
上述计算机可读存储介质、计算机程序产品及计算机程序的有益效果和上述一些实施例所述的源极驱动器的驱动方法或者源极驱动电路的驱动方法的有益效果相同，此处不再赘述。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (20)

  1. 一种源极驱动电路，包括：
    第一源极驱动器，被配置为响应于第一数据传输控制信号的第一触发时刻，将锁存的第一图像数据转换成所述多个第一数据电压；基于所述第一数据传输控制信号的第二触发时刻，输出所述多个第一数据电压；
    第二源极驱动器，被配置为响应于第二数据传输控制信号的第一触发时刻，将锁存的第二图像数据转换成所述多个第二数据电压；基于所述第二数据传输控制信号的第二触发时刻，输出所述多个第二数据电压；
    其中，所述第一数据传输控制信号的第二触发时刻与所述第二数据传输控制信号的第二触发时刻具有时间差。
  2. 根据权利要求1所述的源极驱动电路，其中，
    所述第一数据传输控制信号的所述第一触发时刻，与所述第二数据传输控制信号的所述第一触发时刻同时到达。
  3. 根据权利要求1所述的源极驱动电路，其中，
    所述第一数据传输控制信号与所述第二数据传输控制信号的波形相同，且两者具有相位差。
  4. 根据权利要求1～3中任一项所述的源极驱动电路，其中，
    所述第一源极驱动器包括输出缓冲器，所述输出缓冲器包括多个输出通道；
    所述输出缓冲器被配置为基于所述第一数据传输控制信号的第二触发时刻，将所述多个第一数据电压通过所述多个输出通道分别输出，其中，至少两个输出通道的输出时刻具有时间差。
  5. 根据权利要求4所述的源极驱动电路，其中，
    所述第一源极驱动器还包括延时控制器，所述延时控制器被配置为基于所述第一数据传输控制信号，输出多个输出使能信号；
    所述输出缓冲器被配置为响应于所述多个输出使能信号，将多个第一数据电压通过所述多个输出通道分别输出。
  6. 根据权利要求5所述的源极驱动电路，其中，
    所述多个输出使能信号的波形均相同，且至少两个输出使能信号的波形具有相位差；
    至少一个输出使能信号的第一触发时刻与所述第一数据传输控制信号的第一触发时刻同时到达；
    或者，至少一个输出使能信号的第一触发时刻与所述第一数据传输控制信号的第二触发时刻同时到达。
  7. 根据权利要求5所述的源极驱动电路，其中，
    所述多个输出使能信号的第一触发时刻，与所述第一数据传输控制信号的第一触发时刻同时到达；
    至少一个输出使能信号的第二触发时刻的到达时刻，晚于所述第一数据传输控制信号的第二触发时刻的到达时刻。
  8. 根据权利要求4～7中任一项所述的源极驱动电路，其中，
    沿所述多个输出通道的排布方向，任意相邻的两个输出通道的输出时刻的时间差相同。
  9. 一种源极驱动器，包括：
    数据缓冲器，被配置为接收和锁存图像数据，并响应于数据传输控制信号的第一触发时刻输出所述图像数据；
    数模转换器，被配置为接收所述数据缓冲器输出的所述图像数据，并将所述图像数据转换成多个数据电压；
    输出缓冲器，所述输出缓冲器包括多个输出通道，所述输出缓冲器被配置为基于所述数据传输控制信号的第二触发时刻，将所述多个数据电压通过所述多个输出通道分别输出；
    其中，至少两个输出通道的输出时刻具有时间差。
  10. 根据权利要求9所述的源极驱动器，其中，
    所述源极驱动器还包括延时控制器，所述延时控制器被配置为基于所述数据传输控制信号，输出多个输出使能信号；
    所述输出缓冲器被配置为响应于所述多个输出使能信号，将多个数据电压通过所述多个输出通道分别输出。
  11. 根据权利要求10所述的源极驱动器，其中，
    所述多个输出使能信号的波形均相同，且至少两个输出使能信号具有相位差；
    至少一个输出使能信号的第一触发时刻与所述数据传输控制信号的第一触发时刻同时到达；
    或者，至少一个输出使能信号的第一触发时刻与所述数据传输控制信号的第二触发时刻同时到达。
  12. 根据权利要求9所述的源极驱动器，其中，
    所述多个输出使能信号的第一触发时刻，与所述数据传输控制信号的第一触发时刻同时到达；
    至少一个输出使能信号的第二触发时刻的到达时刻，晚于所述数据传输 控制信号的第二触发时刻的到达时刻。
  13. 根据权利要求10～12中任一项所述的源极驱动器，其中，
    沿所述多个输出通道的排布方向，任意相邻的两个输出通道的输出时刻的时间差相同。
  14. 一种显示装置，包括：
    如权利要求1～8中任一项所述的源极驱动电路；
    或者，如权利要求9～13中任一项所述的源极驱动器；
    所述显示装置还包括：多条栅线和多条数据线；
    至少一个栅极驱动器，被配置为生成多个栅极驱动信号，并将所述多个栅极驱动信号分别输出给所述多条栅线；
    所述源极驱动电路被配置为向所述多条数据线输出多个数据电压。
  15. 根据权利要求14所述的显示装置，还包括：
    时序控制器，被配置为向所述源极驱动电路提供数据传输控制信号。
  16. 根据权利要求14～15中任一项所述的显示装置，其中：
    所述多条栅线具有相等的线电阻。
  17. 根据权利要求14～16中任一项所述的显示装置，其中，
    沿所述多条数据线的排布方向，所述至少一个栅极驱动器位于所述多条数据线的同一侧；
    所述多条数据线分别接收到所述多个数据电压的时刻，由所述显示装置的一侧到另一侧逐级延迟。
  18. 根据权利要求14～16中任一项所述的显示装置，其中，
    所述显示装置包括多个栅极驱动器，沿所述多条数据线的排布方向，所述多个栅极驱动器包括位于所述显示装置一侧的第一栅极驱动器，和位于所述显示装置另一侧的第二栅极驱动器，所述第一栅极驱动器和所述第二栅极驱动器与同一条栅线耦接；
    沿所述多条数据线的排布方向，所述多条数据线分别接收到所述多个数据电压的时刻，由所述显示装置的两侧向中间对称性地逐级延迟。
  19. 一种源极驱动电路的驱动方法，用于驱动如权利要求1～8中任一项所述的源极驱动电路，包括：
    第一源极驱动器响应于第一数据传输控制信号的第一触发时刻，将锁存的第一图像数据转换成所述多个第一数据电压；基于所述第一数据传输控制信号的第二触发时刻，输出所述多个第一数据电压；
    第二源极驱动器响应于第二数据传输控制信号的第一触发时刻，将锁存 的第二图像数据转换成所述多个第二数据电压；基于所述第二数据传输控制信号的第二触发时刻，输出所述多个第二数据电压；
    其中，所述第一数据传输控制信号的第二触发时刻与所述第二数据传输控制信号的第二触发时刻具有时间差。
  20. 一种源极驱动器的驱动方法，用于驱动如权利要求9～13中任一项所述的源极驱动器，包括：
    接收和锁存图像数据，并响应于数据传输控制信号的第一触发时刻输出所述图像数据；
    将所述图像数据转换成多个数据电压；
    基于所述数据传输控制信号的第二触发时刻，将所述多个数据电压分别输出；
    其中，至少两个数据电压的输出时刻具有时间差。
PCT/CN2021/142216 2021-12-28 2021-12-28 源极驱动器、源极驱动电路及其驱动方法、显示装置 WO2023122997A1 (zh)

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