WO2023115382A1 - 多赫蒂放大器及其输出网络、多赫蒂放大器的设计方法 - Google Patents

多赫蒂放大器及其输出网络、多赫蒂放大器的设计方法 Download PDF

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WO2023115382A1
WO2023115382A1 PCT/CN2021/140419 CN2021140419W WO2023115382A1 WO 2023115382 A1 WO2023115382 A1 WO 2023115382A1 CN 2021140419 W CN2021140419 W CN 2021140419W WO 2023115382 A1 WO2023115382 A1 WO 2023115382A1
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Prior art keywords
amplifier
output
transmission line
inductor
network
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PCT/CN2021/140419
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English (en)
French (fr)
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刘昊宇
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苏州华太电子技术股份有限公司
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Priority to CN202180004108.6A priority Critical patent/CN116648851A/zh
Priority to EP21968531.0A priority patent/EP4325720A1/en
Priority to PCT/CN2021/140419 priority patent/WO2023115382A1/zh
Publication of WO2023115382A1 publication Critical patent/WO2023115382A1/zh

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/02—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation
    • H03F1/0205—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation in transistor amplifiers
    • H03F1/0288—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation in transistor amplifiers using a main and one or several auxiliary peaking amplifiers whereby the load is connected to the main amplifier using an impedance inverter, e.g. Doherty amplifiers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/42—Modifications of amplifiers to extend the bandwidth
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/56—Modifications of input or output impedances, not otherwise provided for
    • H03F1/565—Modifications of input or output impedances, not otherwise provided for using inductive elements
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/189—High-frequency amplifiers, e.g. radio frequency amplifiers
    • H03F3/19—High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only
    • H03F3/195—High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only in integrated circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
    • H03F3/24—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers of transmitter output stages
    • H03F3/245—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers of transmitter output stages with semiconductor devices only
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/60—Amplifiers in which coupling networks have distributed constants, e.g. with waveguide resonators
    • H03F3/602—Combinations of several amplifiers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/387—A circuit being added at the output of an amplifier to adapt the output impedance of the amplifier
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/423—Amplifier output adaptation especially for transmission line coupling purposes, e.g. impedance adaptation
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/451—Indexing scheme relating to amplifiers the amplifier being a radio frequency amplifier
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/543—A transmission line being used as coupling element between two amplifying stages

Definitions

  • the present application relates to the field of wireless communication, and in particular, relates to an output network for a Doherty amplifier, a Doherty amplifier including the output network, and a method for designing a Doherty amplifier.
  • the communication bandwidth required by the wireless communication system continues to increase, and the modulation signals used by the wireless communication system are also becoming more and more complex.
  • the efficiency, back-off power range, working bandwidth, and size of the power amplifier (PA) are more and more advanced. Come higher demands.
  • a Doherty amplifier can be used in the RF front-end of a wireless communication system (including base stations, broadcasting and mobile terminals, etc.) to improve the efficiency of the wireless communication system, but due to the The number of power amplifiers and antennas, etc.) is constantly increasing, and the Doherty amplifier uses more components and larger circuit size, so it is difficult to meet the design requirements of miniaturized amplifiers.
  • the load modulation of the Doherty amplifier is realized by a quarter-wavelength transmission line, this structure results in a narrow operating bandwidth of the Doherty amplifier and a small back-off power range for high efficiency.
  • the present application provides an output network for a Doherty amplifier, a Doherty amplifier including the output network and a method for designing a Doherty amplifier, so as to alleviate, alleviate, or even eliminate the above-mentioned problems.
  • An embodiment of the present application provides an output network for a Doherty amplifier
  • the Doherty amplifier includes a main amplifier and an auxiliary amplifier
  • the output network includes: a first sub-output network corresponding to the main amplifier , a second sub-output network corresponding to the auxiliary amplifier, a combining node and a combining matching network.
  • Both the output terminal of the first sub-output network and the output terminal of the second sub-output network are connected to the combination node, and the combining matching network is configured to connect the combination node to the Doherty
  • the radio frequency output terminal of the amplifier, the first sub-output network includes a first series circuit composed of a first inductor and a first transmission line in series
  • the second sub-output network includes a circuit composed of a second inductor and a second transmission line a second series circuit, the first series circuit being connected between the output of the main amplifier and the combining node, the second series circuit being connected between the output of the auxiliary amplifier and the combining node , the first series circuit and the second series circuit are configured such that a node impedance at the combining node is matched to a target load impedance of the main amplifier and the auxiliary amplifier.
  • At least one of the first transmission line and the second transmission line only includes a microstrip line.
  • the combination matching network includes a third transmission line, a fourth transmission line and a first capacitor
  • the third transmission line is connected between the combination node and the output end of the combination matching network
  • the fourth transmission line is connected between the output terminal of the combining matching network and the DC voltage terminal
  • one terminal of the first capacitor is connected to the DC voltage terminal
  • the other terminal of the first capacitor is grounded
  • the DC voltage terminal is configured to provide a DC bias voltage to the main amplifier and the auxiliary amplifier via the fourth transmission line, the third transmission line, the first sub-output network and the second sub-output network.
  • the combination matching network includes a fifth transmission line, a sixth transmission line, a seventh transmission line and a second capacitor, and the fifth transmission line is connected between the combination node and the combination matching network.
  • the sixth transmission line is connected between the combination node and the DC voltage end
  • one end of the seventh transmission line is connected to the output end of the combining matching network
  • one end of the second capacitor is connected to the DC voltage terminal
  • the other end of the second capacitor is grounded, wherein the DC voltage terminal is configured to pass through the sixth transmission line, the first sub-output network and
  • the second sub-output network provides a DC bias voltage to the main and auxiliary amplifiers.
  • the combined matching network includes a third inductor, a fourth inductor and a third capacitor, wherein the third inductor and the third capacitor are connected in series between the DC voltage terminal and the ground between terminals, the combination node is connected to the connection point between the third inductor and the third capacitor, the fourth inductor is connected between the third inductor and the third capacitor Between the connection point of and the output terminal of the combining matching network, wherein the DC voltage terminal is configured to pass through the third inductor, the first sub-output network and the second sub-output network A DC bias voltage is provided to the main and auxiliary amplifiers.
  • the combined matching network further includes an output capacitor, the output capacitor is connected between the output terminal of the combined matching network and the radio frequency output terminal of the Doherty amplifier and is configured to block transmission of a DC signal at the DC voltage terminal to the RF output terminal of the Doherty amplifier.
  • the combining matching network is configured such that the node impedance presents a complex impedance.
  • At least one of the first inductor and the second inductor includes a plurality of bonding wires.
  • At least one of the first inductor and the second inductor includes a microstrip line.
  • At least one of the first transmission line and the second transmission line comprises a stripline, a coplanar waveguide, or a substrate-integrated waveguide.
  • a Doherty amplifier including: a main amplifier; an auxiliary amplifier; and the output network according to any one of the preceding embodiments, the output network is configured to receive the a first amplified signal at the output of the main amplifier and a second amplified signal at the output of the auxiliary amplifier such that the first amplified signal and the second amplified signal are combined at the combining node to be provided to the Doherty RF output of the amplifier.
  • the Doherty amplifier includes a carrier signal input path that supplies a carrier signal to the main amplifier to generate the first amplified signal, and provides a peak signal to the auxiliary amplifier to generate the The peak signal input path of the second amplified signal
  • the Doherty amplifier includes a phase delay element located in at least one of the carrier signal input path and the peak signal input path, the phase delay element is configured to provide A phase difference is formed between the carrier signal to the main amplifier and the peak signal to the auxiliary amplifier, and the phase difference is less than 90 degrees.
  • both the main amplifier and the auxiliary amplifier include transistors, a first characteristic impedance Z Main of the first transmission line, a first electrical angle ⁇ Main , a second characteristic impedance Z of the second transmission line Aux and the second electrical angle ⁇ Aux are respectively:
  • ⁇ IN represents the phase difference
  • ⁇ is the center operating frequency of the Doherty amplifier
  • R opt is the optimum operating load of the transistor
  • L P1 represents the first inductance value of the first inductor
  • L P2 represents the second inductance value of the second inductor
  • C DS is the drain parasitic capacitance of the transistor
  • ⁇ represents the power level for enabling the auxiliary amplifier to work
  • x is a constant.
  • the phase difference ⁇ IN is
  • ⁇ is greater than 0 and less than 0.5, where 1 ⁇ x ⁇ 10.
  • the node impedance Z combine at the combined node satisfies the following formula:
  • the Doherty amplifier includes a plurality of auxiliary amplifiers
  • the output network includes a plurality of second sub-output networks respectively corresponding to the plurality of auxiliary amplifiers one-to-one
  • the first sub-output network is configured to receive a first amplified signal output by the main amplifier
  • each second sub-output network is configured to receive a second amplified signal output by a corresponding auxiliary amplifier in the plurality of auxiliary amplifiers , so that the first amplified signal and the second amplified signal output by each auxiliary amplifier are combined at the combining node to be provided to the radio frequency output terminal of the Doherty amplifier.
  • Yet another embodiment of the present application provides a method of designing a Doherty amplifier, which includes a main amplifier, at least one auxiliary amplifier, and the output network as described in the preceding embodiments, wherein the method includes : selecting transistors for the main amplifier and the auxiliary amplifier; determining the target backoff power range of the Doherty amplifier, and according to the target backoff power range, the first inductance value of the first inductor, The second inductance value of the second inductor, the drain parasitic capacitance of the transistor, the central operating frequency of the Doherty amplifier and the optimal operating load determine the first characteristic impedance and the first characteristic impedance of the first transmission line.
  • the second characteristic impedance, the second electrical angle, the optimum working load, the first inductance value of the first inductor, the second inductance value of the second inductor, and the target backoff power range determine the The nodal impedance at the combined node.
  • the first inductance value of the first inductor, the second inductance value of the second inductor, and the drain parasitic capacitance of the transistor determine the first characteristic impedance and the first electrical angle of the first transmission line, and the second characteristic impedance and the second electrical angle of the second transmission line include : respectively calculate the first characteristic impedance Z Main and the first electrical angle ⁇ Main of the first transmission line, and the second characteristic impedance Z Aux and the second electrical angle ⁇ Aux of the second transmission line by the following formulas:
  • ⁇ IN represents the phase difference
  • ⁇ is the center operating frequency of the Doherty amplifier
  • R opt is the optimum operating load of the transistor
  • L P1 represents the first inductance value of the first inductor
  • L P2 represents the second inductance value of the second inductor
  • C DS is the drain parasitic capacitance of the transistor
  • ⁇ represents the power level coefficient for enabling the auxiliary amplifier to work
  • x is a constant
  • the first characteristic impedance of the first transmission line, the first electrical angle, the second characteristic impedance of the second transmission line, the second electrical angle, the optimal working load, the first The first inductance value of an inductor, the second inductance value of the second inductor and the target backoff power range determine the node impedance at the combined node includes determining the node impedance at the combined node by the following formula Z combine :
  • a first sub-output network corresponding to the main amplifier of the Doherty amplifier and an auxiliary amplifier of the Doherty amplifier are set.
  • the first sub-output network includes a first series circuit composed of a first inductor and a first transmission line in series
  • the second sub-output network includes a second inductor A second series circuit consisting of an amplifier and a second transmission line, the first series circuit and the second series circuit being configured such that the node impedance at the combining node is matched to the target of the main amplifier and the auxiliary amplifier Load impedance, so that the Doherty amplifier can work efficiently from low power to high power, and then realize the deeper back-off power (that is, a larger back-off power range) and wider back-off power of the load modulation of the Doherty amplifier Working bandwidth.
  • the first series circuit composed of a first inductor and a first transmission line in series
  • the second sub-output network includes a second inductor A second series circuit consisting of an amplifier
  • Fig. 1A schematically shows an exemplary principle diagram of a Doherty amplifier in the related art
  • FIG. 1B schematically shows an exemplary circuit structure diagram of a matching network for a Doherty amplifier in the related art
  • Fig. 2 schematically shows an exemplary schematic diagram of an improved Doherty amplifier in the related art
  • Figure 3 schematically illustrates an exemplary schematic diagram of an output network for a Doherty amplifier according to some embodiments of the present application
  • FIG. 4A schematically shows an exemplary schematic diagram of the output network in FIG. 3 implementing load modulation at low power according to some embodiments of the present application;
  • FIG. 4B schematically shows an exemplary schematic diagram of the output network in FIG. 3 implementing load modulation at high power according to some embodiments of the present application;
  • Fig. 5 schematically shows an exemplary schematic diagram of a combined matching network according to some embodiments of the present application
  • Fig. 6 schematically shows an exemplary schematic diagram of a combination matching network according to other embodiments of the present application.
  • Fig. 7 schematically shows an exemplary schematic diagram of a combining matching network according to other embodiments of the present application.
  • FIG. 8A schematically shows an exemplary circuit structure diagram of a Doherty amplifier according to some embodiments of the present application
  • FIG. 8B schematically shows an exemplary circuit structure diagram of a Doherty amplifier according to other embodiments of the present application.
  • FIG. 8C schematically shows an exemplary circuit structure diagram of a Doherty amplifier according to other embodiments of the present application.
  • FIG. 9 schematically shows an exemplary circuit structure diagram of a first inductor or a second inductor according to some embodiments of the present application.
  • FIG. 10A schematically shows an exemplary performance diagram of a Doherty amplifier according to some embodiments of the present application
  • FIG. 10B schematically shows an exemplary performance diagram of a Doherty amplifier according to other embodiments of the present application.
  • Fig. 11 schematically shows an exemplary principle diagram of a Doherty amplifier according to yet another embodiment of the present application.
  • Fig. 12 schematically shows a flowchart of a method of designing a Doherty amplifier according to some embodiments of the present application.
  • Fig. 13A schematically shows an example diagram of values of characteristic impedances of the first transmission line and the second transmission line according to some embodiments of the present application
  • Fig. 13B schematically shows an example diagram of values of electrical angles of the first transmission line and the second transmission line according to some embodiments of the present application
  • FIG. 13C schematically shows an example diagram of the relationship between the first characteristic impedance of the first transmission line and the first inductance value of the first inductor according to some embodiments of the present application;
  • Fig. 13D schematically shows an example diagram of the relationship between the second characteristic impedance of the second transmission line and the second inductance value of the second inductor according to some embodiments of the present application.
  • FIG. 1A schematically shows an exemplary schematic diagram 110 of a Doherty amplifier in the related art.
  • the Doherty amplifier includes two amplifiers (the main amplifier and the auxiliary amplifier).
  • the phase of the signal (that is, the input signal of the main amplifier and the auxiliary amplifier) is determined to meet the working requirements of the load pulling of the Doherty amplifier.
  • the output side of the Doherty amplifier includes four sub-networks: 1) The main circuit matching network is responsible for providing the DC bias voltage V DD1 and matching the optimal load Z opt, M for the main amplifier; 2) The auxiliary circuit matching network is responsible for providing the auxiliary amplifier with DC bias voltage V DD2 and matching optimal load Z opt, A ; 3) combined matching network, responsible for matching the load of the RF output end of the amplifier to the combined point impedance; 4) quarter-wavelength transmission line TL OUT , responsible for Implement Doherty load pull (load modulation).
  • V DD1 and V DD2 are the drain DC bias voltages of the main amplifier and auxiliary amplifier respectively, and C M and C A are DC blocking capacitors.
  • the main amplifier works in class B or AB
  • the auxiliary amplifier works in class C.
  • the two amplifiers do not work alternately, but the main amplifier works all the time, and the auxiliary amplifier starts to work when the input power reaches the set peak value.
  • the quarter-wavelength transmission line in the output path of the main amplifier can play a role of phase compensation, so that the output signal in the output path of the main amplifier and the output signal in the output path of the auxiliary amplifier have the same phase at the combining point C.
  • the matching network usually includes multi-section transmission lines, capacitors, and inductors. These schemes increase the Doherty amplifier overall complexity and circuit size.
  • MIMO multiple-input multiple-output
  • the RF front-end system of the MIMO system includes multiple (for example, dozens or even hundreds) of RF link units, which has great impact on
  • the miniaturization design of the power amplifier in the radio frequency link unit puts forward higher and higher requirements, but the traditional scheme is complicated, uses many components, and has a large circuit size, which is difficult to meet the design requirements of the miniaturized amplifier.
  • the communication bandwidth is increasing exponentially.
  • the communication bandwidth has reached 500MHz or even higher, which poses a high challenge to the working bandwidth of the power amplifier.
  • the load modulation of the Doherty amplifier is realized by the quarter-wavelength transmission line TL OUT , and this structure has only a narrow operating bandwidth (often less than 200MHz), so this architecture is far from meeting the bandwidth of today's systems job requirements.
  • Fig. 2 schematically shows an exemplary principle diagram of an improved Doherty amplifier in the related art.
  • this improved Doherty amplifier includes a broadband power divider, a phase shifter, a carrier amplifier, a peak amplifier, a peak compensation line, and a step impedance combiner, where the carrier amplifier includes sequentially connected Carrier input matching network, carrier transistor and broadband multi-mode matching network; peak amplifier includes sequentially connected peak input matching network, peak transistor and broadband single-mode matching network; broadband power divider receives input power and connects phase shifter and The peak input matching network; the phase shifter is connected to the carrier input matching network; the broadband single-mode matching network is connected to the peak compensation line; and the step impedance combiner is respectively connected to the broadband multi-mode matching network and the peak compensation line for power output.
  • the carrier amplifier includes sequentially connected Carrier input matching network, carrier transistor and broadband multi-mode matching network
  • peak amplifier includes sequentially connected peak input matching network, peak transistor and broadband single-mode matching network
  • broadband power divider receives input power and connect
  • the matching network of the improved Doherty amplifier shown in Figure 2 can optimize the bandwidth, efficiency, fallback power range and other indicators of the Doherty amplifier, but these existing solutions require a large number of components to replace the traditional Doherty
  • the matching network of the amplifier will cause a further increase in the size of the amplifier circuit, making it difficult to realize the miniaturization and integrated design of the power amplifier.
  • Fig. 3 schematically shows an exemplary schematic diagram of an output network 310 for a Doherty amplifier according to some embodiments of the present application.
  • the output network 310 includes a first sub-output network 311 corresponding to the main amplifier of the Doherty amplifier, a second sub-output network 312 corresponding to the auxiliary amplifier of the Doherty amplifier, a combination node 313 and a combination matching network 314, wherein the output of the first sub-output network 311 and the output of the second sub-output network 312 are connected to the combination node 313, and the combining matching network 314 is configured to connect the combination node to the RF output of the Doherty amplifier described above.
  • the first sub-output network 311 includes a first series circuit composed of the first inductor L P1 and the first transmission line TL Main in series
  • the second sub-output network 312 includes a second inductor L P2 and the second transmission line A second series circuit consisting of TL Aux
  • the first series circuit is configured to be connected between the output of the main amplifier and the combining node 313, and the second series circuit is configured to be connected to the auxiliary amplifier
  • the first series circuit and the second series circuit are configured such that the node impedance Z combine at the combination node 313 is matched to the target load of the main amplifier and the auxiliary amplifier impedance.
  • Z combine is the equivalent impedance seen from the combination node 313 to the combination matching network 314, which can be regarded as the combination of the voltage U TC at the node 313 and the current I flowing into the combination matching network 314 in some cases.
  • TC ratio the equivalent impedance seen from the combination node 313 to the combination matching network 314.
  • the above-mentioned first series circuit forms the first sub-output network 311
  • the above-mentioned second series circuit forms the second sub-output network, but this does not exclude the first sub-output network and
  • the second sub-output network includes instances of other elements.
  • the first sub-output network 311 may also include other circuit devices other than the first series circuit, such as capacitors for isolating DC; similarly, the second sub-output network 312 may also include Other circuit devices other than the second series circuit, such as capacitors for isolating DC.
  • the combination node 313 indicates the common connection point of the first sub-output network 311, the second sub-output network 312 and the combination matching network 314.
  • the combination node 313 may be the first sub-output network 311, the second sub-output network 312 and the combined matching network 314 are electrically common contacts, the combination node 313 can also be the electrical node of the output end of the first sub-output network 311, the combination node 313 can also be the electrical node of the output end of the second sub-output network 312, or even a combined Node 313 may be an electrical node at the input of combining matching network 314 .
  • the auxiliary amplifier is not turned on, so it can be equivalent to an open circuit state.
  • the branch where the second sub-output network 312 is located (hereinafter referred to as the auxiliary circuit) provides the auxiliary circuit impedance at the combination node 313.
  • Z off which is connected in parallel with the node impedance Z combine at one end of the branch where the first sub-output network 311 is located (hereinafter referred to as the main branch).
  • the first series circuit (including the first inductor L P1 and the first transmission line TL Main ) can convert the parallel impedance Z off //Z combine of the auxiliary path impedance Z off and the node impedance Z combine into the The target load impedance (Z opt, BO in FIG. 4A ) of the main amplifier at the back-off power.
  • the target load impedance indicates the best power matching impedance of the amplifier at a specific power level, that is, the load impedance that enables the amplifier to achieve the highest efficiency at a specific power level.
  • the target load impedance depends on the parameters of the amplifier itself and the actual power level, and it can be obtained through theoretical calculation or experimental measurement.
  • the first series circuit converts the parallel impedance Z off //Z combine into the target load impedance Z opt, BO of the main amplifier under the back-off power, so that the main amplifier can still efficiently operate under the back-off power Work.
  • the first series circuit (including the first inductor L P1 and the first transmission line TL Main ) can convert the combined equivalent impedance (1+I T2 /I T1 )*Z combine of the main circuit into Target load impedance of the main amplifier at saturation power (Z opt,M in FIG. 4B ).
  • the second series circuit (including the second inductor L P2 and the second transmission line TL Aux ) can convert the combined equivalent impedance (1+I T1 /I T2 )*Z combine of the auxiliary circuit into Target load impedance at power (Z opt, A in FIG. 4B ).
  • the first series circuit and the second series circuit convert the combined equivalent impedance of the main circuit and the combined equivalent impedance of the auxiliary circuit into corresponding target values of the main amplifier and the auxiliary amplifier under saturated power
  • the load impedance enables both the main amplifier and the auxiliary amplifier to work efficiently at saturated power.
  • the "combining equivalent impedance” mentioned here indicates the equivalent impedance seen to the combining node (ie, combining node 313 ) on a certain path.
  • the combined equivalent impedance of the main circuit is the ratio of the output terminal voltage U T1 of the main circuit to the output current I T1 of the main circuit
  • the equivalent impedance of the combined circuit of the auxiliary circuit is the output terminal voltage of the auxiliary circuit
  • the first inductor L P1 and the second inductor L P2 can be implemented in various forms (such as bonding wires).
  • the main amplifier and the auxiliary amplifier may include, but are not limited to, power transistors based on, for example, VDMOS, LDMOS or GaN, with different transistor technologies providing different performance advantages in terms of output power, gain and performance.
  • the type of transistor can be selected according to requirements such as frequency, bandwidth, and cost.
  • the main amplifier and the auxiliary amplifier may be the same type of power transistor (such as a GaN-based power transistor), and the parameters of the transistor used as the main amplifier and the transistor used as the auxiliary amplifier and The dimensions can be exactly the same.
  • the transistors used as the main amplifier and the transistors used as the auxiliary amplifier differ in at least one of transistor type, parameter, and size.
  • the main amplifier or the auxiliary amplifier may include a plurality of transistors. The specific implementation manners of the main amplifier and the auxiliary amplifier are not specifically limited herein.
  • the node impedance Z combine at the combining node 313 can be matched to the target load impedance of the main and auxiliary amplifiers of the Doherty amplifier at different power levels,
  • the main amplifier can still work efficiently at the back-off power, and both the main amplifier and the auxiliary amplifier can work efficiently at saturated power, that is, make the Doherty amplifier operate at different power levels All can work efficiently.
  • the number of components contained in the output network 310 is greatly reduced, the structure of the output network 310 is simplified, and the size of related circuits is reduced, which can meet the needs of miniaturized amplifiers. design needs.
  • the Doherty amplifier can be operated with high efficiency and has Larger working bandwidth and deeper backoff power (that is, larger backoff power range).
  • At least one of the first transmission line and the second transmission line includes only microstrip lines.
  • Microstrip line is a planar transmission line most used in hybrid microwave integrated circuits and monolithic microwave integrated circuits. It is a strip wire (signal line) and is isolated from the ground by a dielectric. Factors affecting the characteristic impedance of the microstrip line include the thickness and width of the microstrip line, the distance from the formation and the dielectric constant of the dielectric, etc. The length of the microstrip line can correspond to the electrical angle of the microstrip line.
  • the first transmission line and the second transmission line may be realized by using a microstrip line.
  • dimensional parameters such as length and width of the microstrip line can be configured based on the characteristic impedance and electrical angle of the first transmission line and the second transmission line.
  • a transmission line that meets the requirements of characteristic parameters can be obtained, so that the Doherty amplifier can have a smaller circuit size, higher working efficiency, larger The working bandwidth and deeper back-off power (that is, a larger back-off power range).
  • microstrip lines can be realized by using substrates with high dielectric constants to further reduce the size of related circuits.
  • At least one of the first transmission line and the second transmission line may comprise a stripline, a coplanar waveguide, or a substrate integrated waveguide.
  • a stripline is a high-frequency transmission conductor placed between a dielectric between two parallel ground planes (or power planes). Stripline has the advantages of small size, light weight, wide frequency band, high quality factor, simple process, and low cost, and is suitable for making high-performance (broadband, high quality factor, high isolation) passive components.
  • a coplanar waveguide (CPW) is formed by fabricating a central conductor strip on one surface of a dielectric substrate, and fabricating conductor planes on both sides of the central conductor strip. Stripline circuits have less loss.
  • Substrate integrated waveguide utilizes metal vias to realize the field propagation mode of the waveguide on the dielectric substrate, which has the advantages of low dropout, low radiation, and high quality factor.
  • at least one of the first transmission line and the second transmission line may consist of only one of a stripline, a coplanar waveguide, or a substrate-integrated waveguide.
  • FIG. 5 schematically shows an exemplary schematic diagram of a combining matching network 514 according to some embodiments of the present application.
  • the combining matching network is configured such that the node impedance presents a complex impedance
  • the combined matching network 514 includes a third transmission line 514A, a fourth transmission line 514B and a first capacitor C 1 , the third transmission line 514A is connected between the combining node 513 and the output end of the combining matching network 514, and the fourth The transmission line 514B is connected between the output terminal of the combination matching network 514 and the DC voltage terminal V DD , one terminal of the first capacitor C 1 is connected to the DC voltage terminal V DD , and the other terminal of the first capacitor C 1 is grounded, wherein the DC voltage terminal V DD is configured to provide a DC bias voltage to the main amplifier and the auxiliary amplifier via the fourth transmission line 514B, the third transmission line 514A, the first sub-output network 511 and the second sub-output network 512 .
  • the third transmission line 514A and the fourth transmission line 514B may be implemented by microstrip lines.
  • the node impedance Z combine at the combined node 513 can be adjusted by setting the characteristic parameters of the third transmission line 514A, the fourth transmission line 514B, and the first capacitor C1 , thereby helping to realize the aforementioned impedance matching to optimize the items of the Doherty amplifier Performance metrics (see above for details regarding Figures 4A and 4B).
  • the first capacitor C1 can prevent the radio frequency signal from entering the DC power supply line through the fourth transmission line 514B, and can reduce or even avoid the loss of radio frequency power in the combining matching network 514 .
  • each of the main amplifier and the auxiliary amplifier has a corresponding DC bias circuit (see V DD1 and V DD2 in Fig. 1A ), but in the technical solution of this embodiment of the present application, the main amplifier
  • the DC bias circuit is shared with the auxiliary amplifier, and the DC bias circuit can be integrated in the matching network 514, that is, the DC voltage terminal V DD passes through the fourth transmission line 514B, the third transmission line 514A, the first sub-output network 511 and
  • the second sub-output network 512 provides a DC bias voltage to the main and auxiliary amplifiers, which helps to further reduce the circuit size of the Doherty amplifier.
  • FIG. 6 schematically shows an exemplary schematic diagram of a combining matching network 614 according to other embodiments of the present application.
  • the combination matching network 614 includes a fifth transmission line 614A, a sixth transmission line 614B, a seventh transmission line 614C and a second capacitor C 2 , and the fifth transmission line 614A is connected to the combination node 613 and the output end of the combination matching network 614
  • the sixth transmission line 614B is connected between the combined node 613 and the DC voltage terminal V DD
  • one end of the seventh transmission line 614C is connected to the output end of the combining matching network 614
  • the other end of the seventh transmission line 614C is floating
  • the second One end of the capacitor C2 is connected to the DC voltage terminal V DD
  • the other end of the second capacitor is grounded
  • the DC voltage terminal V DD is configured to: via the sixth transmission line 614B, the first sub-output network 611 and the second sub-output network 612 Provides DC bias voltage to
  • the fifth transmission line 614A, the sixth transmission line 614B, and the seventh transmission line 614C can be implemented by microstrip lines .
  • the node impedance Z combine at the combined node 613 can be adjusted by setting the characteristic parameters of the fifth transmission line 614A, the sixth transmission line 614B, the seventh transmission line 614C and the second capacitor C2 , thereby helping to achieve the aforementioned impedance matching to optimize the multihertz Various performance indicators of the pedicle amplifier (see the above descriptions of FIG. 4A and FIG. 4B for details).
  • the sixth transmission line 614B connected to the DC voltage terminal V DD is closer to the combination node. 613, which can further reduce the baseband impedance of the Doherty amplifier and enhance the linearity of the Doherty amplifier under wideband signals. In addition, it also helps to improve the friendliness of digital pre-distortion (that is, for those with higher peak-to-average power Compared with the modulated signal with a larger bandwidth, the output signal processed by the digital pre-distortion technology has extremely small nonlinear distortion).
  • the second capacitor C2 can prevent the radio frequency signal from entering the DC power supply line through the sixth transmission line 614B, and can reduce or even avoid the loss of radio frequency power in the combining matching network 614 .
  • the main and auxiliary amplifiers each have a corresponding DC bias circuit (see V DD1 and V DD2 in Figure 1A), whereas in this embodiment, the main and auxiliary amplifiers share a DC bias circuit, and the DC bias circuit can be integrated in the combination matching network 614 provided by the present application, that is: the DC voltage terminal V DD is connected via the sixth transmission line 614B, the first sub-output network 611 and the second sub-output network 612 A DC bias voltage is provided to the main and auxiliary amplifiers, which helps to further reduce the circuit size of the Doherty amplifier.
  • FIG. 7 schematically shows an exemplary principle diagram of a combining matching network 714 according to some other embodiments of the present application.
  • the combined matching network 714 includes a third inductor L P3 , a fourth inductor L P4 and a third capacitor C 3 , wherein the third inductor L P3 and the third capacitor C 3 are connected in series at DC voltage Between terminal V DD and ground, the combination node 713 is connected to the connection point between the third inductor L P3 and the third capacitor C3 , and the fourth inductor L P4 is connected between the third inductor L P3 and the third capacitor Between the connection point between C 3 and the output terminal of the combining matching network 714, wherein the DC voltage terminal V DD is configured to: via the third inductor L P3 , the first sub-output network 711 and the second sub-output network 712 Provides DC bias voltage to the main and auxiliary amplifiers.
  • the node impedance Z combine at the combined node 713 can be adjusted by setting the characteristic parameters (inductance value, capacitance value) of the third inductor L P3 , the fourth inductor L P4 and the third capacitor C 3 , so that It is helpful to realize the aforementioned impedance matching to optimize various performance indicators of the Doherty amplifier (see the above description for FIG. 4A and FIG. 4B for details).
  • the third capacitor C 3 can prevent the radio frequency signal from entering the DC power supply line, and can reduce or even avoid the loss of radio frequency power in the combining matching network 714 .
  • the main and auxiliary amplifiers each have their respective DC bias circuits (see V DD1 and V DD2 in Figure 1A), whereas in this application, the main and auxiliary amplifiers share a DC bias circuit. setting circuit, and the DC bias circuit can be integrated in the combined matching network 714 provided in this application, that is, the DC voltage terminal V DD passes through the third inductor L P3 , the first sub-output network 711 and the second sub-output network
  • the 712 provides DC bias voltage to the main and auxiliary amplifiers, which helps to further reduce the circuit size of the Doherty amplifier.
  • DC bias circuits are integrated in the combined matching network, but this is not necessary, and the number and number of DC bias circuits can be adjusted according to actual applications. Its location in the Doherty amplifier circuit. Exemplarily, when the configuration parameters of the main amplifier and the auxiliary amplifier are different (for example, when they are not a type of transistor), corresponding DC bias circuits may be respectively set for the main amplifier and the auxiliary amplifier.
  • the combining matching network described above with respect to FIGS. 5 , 6 and 7 further includes an output capacitor connected between the output of the combining matching network and the Doherty amplifier between the radio frequency output terminals of the Doherty amplifier and is configured to block the direct current signal of the direct current voltage terminal from being transmitted to the radio frequency output terminal of the Doherty amplifier.
  • the output capacitor With the output capacitor, the DC signal from the DC voltage terminal will not be transmitted to the RF output terminal of the Doherty amplifier, thereby protecting sensitive RF components (loads) from the influence of DC.
  • the Doherty amplifier includes a main amplifier, an auxiliary amplifier, and any one of the aforementioned output networks according to the present application, the output network is configured to receive the a first amplified signal at the output of the main amplifier and a second amplified signal at the output of the auxiliary amplifier such that the first amplified signal and the second amplified signal are combined at the combining node to be provided to the Doherty RF output of the amplifier. Since the Doherty amplifier includes the output network according to the foregoing embodiments of the present application, the Doherty amplifier has the advantages brought by the corresponding output network.
  • the output network of the Doherty amplifier includes the combination matching network 514 described in FIG. 5, it can be adjusted by setting the characteristic parameters of the third transmission line 514A, the fourth transmission line 514B, and the first capacitor C1
  • the node impedance Z combine at the node 513 is combined to help achieve the aforementioned impedance matching to optimize various performance indicators of the Doherty amplifier (see the above descriptions in relation to FIG. 4A and FIG. 4B for details).
  • the first capacitor C1 can prevent the radio frequency signal from entering the power supply line through the fourth transmission line 514B, and can reduce or even avoid the loss of radio frequency power in the combining matching network 514 .
  • the main amplifier and the auxiliary amplifier can share the DC bias circuit integrated in the combining matching network 514, so that the circuit size of the Doherty amplifier can be further reduced.
  • a Doherty amplifier based on this circuit structure can be referred to the Doherty amplifier 810 described below with respect to FIG. 8A .
  • FIG. 8A schematically shows an exemplary layout of some components in a Doherty amplifier 810 according to some embodiments of the present application.
  • the Doherty amplifier 810 is a two-way Doherty amplifier formed based on LDMOS or GaN process transistors and matching elements on the peripheral printed circuit board 800A.
  • the Doherty amplifier 810 includes a carrier signal input path that provides a carrier signal to a main amplifier to generate the first amplified signal, and a peak signal input path that provides a peak signal to the auxiliary amplifier to generate the second amplified signal, wherein
  • the Doherty amplifier 810 includes a phase delay element 813 located in at least one of the carrier signal input path and the peak signal input path, and the phase delay element is configured to provide A phase difference is formed between the peak signals to the auxiliary amplifiers, the phase difference being less than 90 degrees.
  • the Doherty amplifier 810 includes a packaged main amplifier chip 814A and an auxiliary amplifier chip 814B, the phase delay element 813 can be implemented in the form of a microstrip line, and the Doherty amplifier 810 also includes a power divider 812 , which is electrically connected to the radio frequency signal input end 811 of the Doherty amplifier 810 .
  • the first sub-output network is implemented as a series circuit of the first inductor L P1 and the first microstrip line 815A
  • the second sub-output network is implemented as a series circuit of the second inductor L P2 and the second microstrip line 815B.
  • the combination matching network includes a microstrip line 816A, a microstrip line 816B and a surface mount SMD capacitor 817, which respectively correspond to the third transmission line 514A, the fourth transmission line 514B and the first capacitor C 1 described above with respect to FIG. 5 , and they The connection relationship among them is consistent with that described above with respect to FIG. 5 , and will not be repeated here.
  • 818 represents a DC voltage terminal for receiving a DC voltage signal
  • the surface mount SMD capacitor 816C is a DC blocking capacitor.
  • the RF signal output of Doherty amplifier 810 is shown as 819 .
  • the specific implementation manner of the phase delay element 813 is not limited herein, and the phase delay element 813 includes but is not limited to a microstrip line.
  • the phase delay element is shown as being located in the input path of the peaking amplifier 814B, alternatively, the phase delay element may also be provided in the input path of the main amplifier, or between the input path of the main amplifier and the auxiliary amplifier 814B.
  • a phase delay element is also provided in the input path of the amplifier.
  • those skilled in the art may implement a phase difference of less than 90 degrees between the carrier signal provided to the main amplifier and the peak signal provided to the auxiliary amplifier in different ways.
  • the aforementioned combining matching network is configured such that the node impedance presents a complex impedance.
  • the phase delay element 813 makes a phase difference less than 90 degrees formed between the carrier signal provided to the main amplifier and the peak signal provided to the auxiliary amplifier, which can further improve the ability of the main amplifier and the auxiliary amplifier to present complex impedance at the node impedance. work efficiency in the situation.
  • FIG. 8B schematically shows an exemplary circuit structure diagram of a Doherty amplifier 820 according to other embodiments of the present application. Similar to the Doherty amplifier 810 described above with respect to FIG. 8A, as shown in FIG. Lou Doherty Amplifier.
  • the Doherty amplifier 820 includes a carrier signal input path that provides a carrier signal to a main amplifier to generate the first amplified signal, and a peak signal input path that provides a peak signal to the auxiliary amplifier to generate the second amplified signal, wherein
  • the Doherty amplifier 820 includes a phase delay element located in at least one of the carrier signal input path and the peak signal input path (for example, a microstrip line 823 located in the peak signal input path as shown in FIG. 8B ) , the phase delay element is configured to form a phase difference between the carrier signal supplied to the main amplifier and the peak signal supplied to the auxiliary amplifier, the phase difference being less than 90 degrees.
  • the main amplifier and the first inductor shown as inductor 8241 in FIG.
  • the first sub-output network includes a microstrip line 825A connected in series with an inductor 8241 located in the package where the main amplifier is located
  • the second sub-output network includes a microstrip line 825B connected in series with an inductor 8241 located in Another inductor in the same package as the auxiliary amplifier.
  • the combined matching network includes a microstrip line 826A, a microstrip line 826B, a microstrip line 826C, and a surface-mounted SMD capacitor 827, which correspond to the fifth transmission line 614A, the sixth transmission line 614B, and the seventh transmission line described above in relation to FIG. 6, respectively.
  • 828 represents a DC voltage terminal
  • the surface mount SMD capacitor 826D is a DC blocking capacitor.
  • the RF input and RF output of the Doherty amplifier 820 are 821 and 829, respectively.
  • the microstrip line 826B connected to the DC voltage terminal 828 is closer to the combination node, which can further reduce the baseband impedance of the Doherty amplifier and enhance the linearity of the Doherty amplifier under broadband signals.
  • the main amplifier 824A and the auxiliary amplifier 824B are packaged together with corresponding inductors, this further improves the integration of components and further reduces the circuit size of the Doherty amplifier 820 .
  • FIG. 8C schematically shows an exemplary circuit structure diagram of a Doherty amplifier 830 according to other embodiments of the present application.
  • a Doherty amplifier 830 is formed on an LGA substrate.
  • the Doherty amplifier 830 is a monolithic microwave integrated circuit (MMIC) based on LDMOS or GaN process, packaged in an LGA substrate package 800C.
  • MMIC monolithic microwave integrated circuit
  • the main difference between the Doherty amplifier 830 and the Doherty amplifier in FIG. 8A and FIG. 8B is that the circuit components on the printed circuit board are all integrated on the LGA substrate to further increase the integration level.
  • both the main amplifier 834A and the auxiliary amplifier 834B are unpackaged bare cores (only containing parasitic capacitance), and the outputs of the main amplifier 834A and the auxiliary amplifier 834B are respectively connected to the microstrip lines 835A and 835B through bonding wires 837A and 837B.
  • the bonding lines 837A and 837B respectively correspond to the first inductor L P1 and the first inductor L P2 in the first series circuit and the second series circuit described in the above embodiments.
  • the microstrip lines 835A and 835B respectively correspond to the first transmission line and the second transmission line in the first sub-output network and the second sub-output network described in the above embodiments.
  • the combined matching network is composed of an inductor 839A, a capacitor 839C and an inductor 839B, which respectively correspond to the third inductor L P3 , the fourth inductor L P4 and the third capacitor C 3 described above with respect to FIG. 7 .
  • These capacitors can be implemented by metal-oxide-metal capacitors, fringe capacitors, or surface-mounted SMD capacitors.
  • the third inductor and the fourth inductor can be implemented by bonding wires, and the bonding wires are also connected to the drain through the pin pad 842. Pole DC voltage terminal. Pin pads 831 and 841 represent the radio frequency signal input terminal and the radio frequency signal output terminal of the Doherty amplifier respectively.
  • the first inductor L P1 and the first inductor L P2 can be implemented by bonding wires.
  • FIG. 9 schematically shows the first inductor L P1 according to some embodiments of the present application.
  • An exemplary circuit structure diagram of the first inductor L P2 At least one of the first inductor and the second inductor may include a plurality of bonding wires.
  • 913 is a transistor (main amplifier or auxiliary amplifier) QFN package tube shell
  • 914 is a transistor chip bare core
  • 915 is a gate bonding pad, which is connected to the input pin of the chip through a bonding wire 917 918
  • 916 are drain bonding pads, which are connected to the output pin 920 of the chip through a plurality of bonding wires 919 .
  • each of the bonding wires 919 can be connected in parallel, and its equivalent inductance can be easily adjusted by adjusting parameters such as the number, length, and height of the bonding wires 919 to achieve the desired
  • the inductance values of the first inductor L P1 and the first inductor L P2 can help to optimize various performance indicators of the amplifier.
  • first inductor and the second inductor is not limited to bonding wires, and in other embodiments, the above-mentioned first inductor and the second inductor can also be implemented in the form of a microstrip line. , this paper does not impose any special restrictions on the specific forms of the first inductor and the second inductor.
  • FIGS. 10A and 10B schematically show performance examples of Doherty amplifiers obtained through simulation experiments according to some embodiments of the present application.
  • the central operating frequency of the Doherty amplifier is 2 GHz
  • the total output power is 16 W
  • the output capacitance (the drain parasitic capacitance of the transistor) of the main amplifier and the auxiliary amplifier is 1.02 pF
  • the inductor has an inductance value of 0.25pF.
  • the characteristic impedance of the first transmission line is 53 Ohm, and the electrical angle is 44.7°
  • the characteristic impedance of the second transmission line is 37.5 Ohm, and the electrical angle is 80.9°.
  • the combined matching network makes the node impedance Z combine present a complex impedance (14.23-j5.89) Ohm.
  • the electrical angle of the phase delay element is 37.76°.
  • FIG. 10A corresponds to the Doherty amplifier 820 shown in FIG. 8B
  • FIG. 10B corresponds to the Doherty amplifier 830 shown in FIG. 8C.
  • the curve 1011 indicates the change of the efficiency of the Doherty amplifier 820 with the output power
  • the curve 1012 indicates the change of the gain of the Doherty amplifier 820 with the output power, which can be It can be seen that the Doherty amplifier 820 can obtain a saturated output power (1013) exceeding 42dBm, and at the same time realize high-efficiency operation under 10dB power backoff (1014), that is, the backoff power range of the Doherty amplifier 820 is about 10dB.
  • curve 1021 indicates the change of the efficiency of the Doherty amplifier 830 with the output power
  • curve 1022 indicates the change of the gain of the Doherty amplifier 830 with the output power
  • the Doherty amplifier 830 can obtain a saturated output power (1023) exceeding 40dBm, and at the same time realize high-efficiency operation under 10dB power backoff (1024), that is, the backoff power range of the Doherty amplifier 830 Around 10dB.
  • both the main amplifier and the auxiliary amplifier include transistors, the first characteristic impedance Z Main of the first transmission line, the first electrical angle ⁇ Main and the second transmission line
  • the second characteristic impedance Z Aux and the second electrical angle ⁇ Aux are respectively:
  • ⁇ IN represents the phase difference less than 90 degrees between the carrier signal supplied to the main amplifier and the peak signal supplied to the auxiliary amplifier (the phase difference is greater than 0 degrees)
  • ⁇ is the center operating frequency of the Doherty amplifier
  • R opt is The optimal working load of the transistor
  • L P1 represents the first inductance value of the first inductor
  • L P2 represents the second inductance value of the second inductor
  • C DS is the drain parasitic capacitance of the transistor
  • ⁇ represents that the auxiliary amplifier is turned on
  • the power level of , x is a constant.
  • ⁇ representing the power level at which the auxiliary amplifier is turned on is relative to the maximum power value, so in some embodiments, ⁇ can be regarded as a ratio of the power at which the auxiliary amplifier is turned on to the maximum power.
  • the constant x, the inductance values of the first inductor and the second inductor can affect the first characteristic impedance Z Main of the first transmission line, the first electrical angle ⁇ Main and the second characteristic impedance of the second transmission line Z Aux and the second electrical angle ⁇ Aux , thereby affecting the size parameters of the first transmission line and the second transmission line, by selecting the appropriate constant x, the inductance values of the first inductor and the second inductor, the first inductor suitable for manufacturing can be implemented.
  • the "optimum operating load” mentioned in this article refers to the load impedance that allows the amplifier (main or auxiliary amplifier) to achieve the highest efficiency at a specific power level, but this load impedance does not take into account the parasitic parameters of the transistor (for example, drain parasitic capacitance C DS ), or the above-mentioned R opt is the optimum working load of the transistor after removing the parasitic parameters, therefore, the optimum working load is usually a real number.
  • the phase difference ⁇ IN in formulas 1-4 satisfies: Where ⁇ is greater than 0 and less than 0.5, where 1 ⁇ x ⁇ 10.
  • the node impedance Z combine at the combined node satisfies the following formula:
  • a combining matching network with an appropriate structure can be designed.
  • the combination matching network described above with reference to FIG. 5 to FIG. 8C is only an example of the combination matching network, but this does not constitute a limitation on the combination matching network.
  • Based on the node impedance Z combine various forms can be designed and implemented. The specific structure of the combination matching network.
  • FIG. 11 schematically shows an exemplary schematic diagram of a Doherty amplifier 1100 according to another embodiment of the present application.
  • the Doherty amplifier 1100 includes a plurality of auxiliary amplifiers (auxiliary amplifier A and auxiliary amplifier B shown in FIG.
  • the output network 1110 includes a plurality of first auxiliary amplifiers corresponding to the auxiliary amplifier A and auxiliary amplifier B respectively
  • Two sub-output networks (second sub-output networks 1112A, 1112B as shown in Figure 11)
  • the first sub-output network 1111 is configured to receive the first amplified signal of the output of the main amplifier
  • the second sub-output networks 1112A, 1112B are respectively configured to receive the second amplified signals output by the auxiliary amplifiers A, B such that the first amplified signal and the second amplified signal output by each auxiliary amplifier are combined at the combining node 1213 to be provided to the Doherty amplifier 1100 RF output.
  • the Doherty amplifier 11 includes two auxiliary amplifiers, this does not constitute a limitation on the structure of the Doherty amplifier, and the Doherty amplifier may include more auxiliary amplifiers (for example, Three, four or more auxiliary amplifiers), that is, the Doherty amplifier may be a multi-channel Doherty amplifier including multiple amplification paths.
  • the multi-channel Doherty amplifier including the output network described in the above-mentioned embodiments of the present application can provide a larger operating bandwidth and deeper back-off power, which will not be repeated here.
  • FIG. 12 schematically A flowchart 1200 is shown of a method of designing a Doherty amplifier according to some embodiments of the present application. As shown in Figure 12, the method includes the following steps:
  • Step 1210 select transistors for the main amplifier and the auxiliary amplifier.
  • the selection of transistors can consider various design requirements, such as power, cost, size, etc., and reference can be made to the description of different types of transistors above, which is not limited herein.
  • the transistor used for the amplifier is determined, its optimal operating load R opt is also basically determined; step 1220, determining the target back-off power range of the Doherty amplifier, and back-off power range according to the target , the first inductance value of the first inductor, the second inductance value of the second inductor, the drain parasitic capacitance of the transistor, the central operating frequency of the Doherty amplifier, and the optimum operating load are determined
  • the embodiment of the present application proposes a method for designing a Doherty amplifier, starting from the desired target backoff power range, and aiming at simplifying the structure of the output network of the Doherty amplifier, which can realize the extension of the Doherty amplifier backoff.
  • the coordination and unification of the depowering range and the simplified circuit structure of the Doherty amplifier can be obtained.
  • the Doherty amplifier can also realize the power conversion from low power to high power Efficient operation within the range, with deeper back-off power and wider operating bandwidth.
  • the first inductance value of the first inductor, the second inductance value of the second inductor, the drain parasitic capacitance of the transistor determine the first characteristic impedance and the first electrical angle of the first transmission line, and the second characteristic impedance and the second electrical angle of the second transmission line include:
  • the first characteristic impedance Z Main and the first electrical angle ⁇ Main of the first transmission line, and the second characteristic impedance Z Aux and the second electrical angle ⁇ Aux of the second transmission line are respectively calculated by the following formulas:
  • ⁇ IN represents the phase difference
  • ⁇ is the center operating frequency of the Doherty amplifier
  • R opt is the optimum operating load of the transistor
  • L P1 represents the first inductance value of the first inductor
  • L P2 represents the second inductance value of the second inductor
  • C DS is the drain parasitic capacitance of the transistor
  • ⁇ represents the power level coefficient for enabling the auxiliary amplifier to work
  • x is a constant.
  • the first characteristic impedance of the first transmission line, the first electrical angle, the second characteristic impedance of the second transmission line, the second electrical angle, the optimal working load, the first The first inductance value of the inductor, the second inductance value of the second inductor and the target backoff power range determine the node impedance at the combined node includes determining the node impedance Zcombine at the combined node by the following formula :
  • the constant x, the first inductance value of the first inductor, and the second inductor value of the second inductor have flexibility in the design of specific parameters of the first transmission line and the second transmission line in the output network. positive practical significance.
  • the first characteristic impedance Z Main of the first transmission line, the first electrical angle ⁇ Main , the second characteristic impedance Z Aux of the second transmission line and the second electrical angle ⁇ Aux can be obtained. value.
  • FIG. 13A and FIG. 13B schematically show example graphs 1310 and 1320 of characteristic impedances and electrical angles of the first transmission line and the second transmission line according to some embodiments of the present application, respectively.
  • the constant x The choice of can be used to adjust the characteristic impedance of the transmission line within the manufacturable range (30 ⁇ 100Ohm), and at the same time, the electrical angle of the transmission line can be adjusted by the constant x to achieve a smaller circuit size (that is, a smaller electrical angle corresponds to a smaller size of the transmission line).
  • FIG. 13C schematically illustrates an example graph 1330 of a relationship between a first characteristic impedance of a first transmission line and a first inductance value of a first inductor according to some embodiments of the present application.
  • optimum operating load R opt 60Ohm
  • fallback power range 9dB
  • C DS 1pF
  • x 2.5"
  • R opt 60 Ohm corresponds to a power amplifier with small and medium power
  • the main circuit does not include the first inductor described in the embodiment of the present application, even if the parasitic inductance of the transistor itself in the main amplifier ( ⁇ 0.5pF) is considered, the first transmission line of the first transmission line
  • a characteristic impedance Z main will be much larger than 100 Ohm, which is difficult to realize in the specific implementation of the first transmission line.
  • FIG. 13D schematically illustrates an example graph 1340 of the relationship between the second characteristic impedance of the second transmission line and the second inductance value of the second inductor according to some embodiments of the present application.
  • the constant x, the first inductor, and the second inductor can provide a greater degree of freedom for the design of the first transmission line and the second transmission line in the output network, and at the same time, it can also provide a convenient way for designing the first transmission line, the second The processing and production of the second transmission line provides guarantee.

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Abstract

本申请实施例提供了一种用于多赫蒂放大器的输出网络、多赫蒂放大器和设计多赫蒂放大器的方法。上述输出网络包括：第一子输出网络、第二子输出网络、组合节点和合路匹配网络，第一子输出网络的输出和第二子输出网络的输出均连接至组合节点，合路匹配网络被配置成将组合节点连接至多赫蒂放大器的射频输出端。第一子输出网络包括由第一电感器和第一传输线串联组成的第一串联电路，第二子输出网络包括由第二电感器和第二传输线组成的第二串联电路，第一串联电路连接在主放大器的输出端和组合节点之间，第二串联电路连接在辅放大器的输出端和组合节点之间，第一串联电路和第二串联电路被配置成使得组合节点处的节点阻抗匹配至主放大器和辅放大器的目标负载阻抗。

Description

多赫蒂放大器及其输出网络、多赫蒂放大器的设计方法 技术领域
本申请涉及无线通信领域，具体地，涉及一种用于多赫蒂放大器的输出网络、包括该输出网络的多赫蒂放大器和一种设计多赫蒂放大器的方法。
背景技术
随着无线通信技术的发展，无线通信系统所需的通信带宽不断增长，无线通信系统采用的调制信号也越来越复杂。为了满足对无线通信系统的带宽、效率、体积等方面的要求，在无线通信网络的射频前端系统中，对功率放大器(PA)的效率、回退功率范围、工作带宽、尺寸等方面提出了越来越高的要求。
在相关技术中，可以在无线通信系统(包括基站、广播和移动终端等)的射频前端中使用多赫蒂放大器来提高无线通信系统的效率，但是由于射频前端系统包含的射频链路单元(包括功率放大器和天线等)的数量不断增长，而多赫蒂放大器使用的元器件较多、电路尺寸较大，因此难以满足小型化放大器的设计需求。另外，由于多赫蒂放大器的负载调制是由四分之一波长传输线来实现的，这种结构导致多赫蒂放大器的工作带宽较窄并且高效率的回退功率范围较小。因此，无线通信系统难以通过传统的多赫蒂放大器来满足在带宽、效率、体积等方面越来越高的要求。目前，存在一些通过改进多赫蒂放大器的负载调制网络来增加带宽的方法，但是往往使得多赫蒂放大器的尺寸增加，从而导致难以在放大器的效率、带宽、回退功率范围和电路尺寸之间达到较好的平衡。
发明内容
有鉴于此，本申请提供了一种用于多赫蒂放大器的输出网络、包括该输出网络的多赫蒂放大器和设计多赫蒂放大器的方法，以缓解、减轻、甚至消除上述问题。
本申请的实施例提供了一种用于多赫蒂放大器的输出网络，所述多赫蒂放大器包括主放大器和辅放大器，所述输出网络包括：与所述 主放大器对应的第一子输出网络、与所述辅放大器对应的第二子输出网络、组合节点和合路匹配网络。所述第一子输出网络的输出端和所述第二子输出网络的输出端均连接至所述组合节点，所述合路匹配网络被配置成将所述组合节点连接至所述多赫蒂放大器的射频输出端，所述第一子输出网络包括由第一电感器和第一传输线串联组成的第一串联电路，所述第二子输出网络包括由第二电感器和第二传输线组成的第二串联电路，所述第一串联电路连接在所述主放大器的输出端和所述组合节点之间，所述第二串联电路连接在所述辅放大器的输出端和所述组合节点之间，所述第一串联电路和所述第二串联电路被配置成使得所述组合节点处的节点阻抗匹配至所述主放大器和所述辅放大器的目标负载阻抗。
根据本申请的一些实施例，所述第一传输线和所述第二传输线中的至少一个仅包括微带线。
根据本申请的一些实施例，所述合路匹配网络包括第三传输线、第四传输线和第一电容器，所述第三传输线连接在所述组合节点和所述合路匹配网络的输出端之间，所述第四传输线连接在所述合路匹配网络的输出端和直流电压端之间，所述第一电容器的一端连接至所述直流电压端，所述第一电容器的另一端接地，其中所述直流电压端被配置成经由所述第四传输线、所述第三传输线、所述第一子输出网络和所述第二子输出网络向所述主放大器和辅放大器提供直流偏置电压。
根据本申请的一些实施例，所述合路匹配网络包括第五传输线、第六传输线、第七传输线和第二电容器，所述第五传输线连接在所述组合节点和所述合路匹配网络的输出端之间，所述第六传输线连接在所述组合节点和直流电压端之间，所述第七传输线的一端连接至所述合路匹配网络的输出端，所述第七传输线的另一端浮接，所述第二电容器的一端连接至直流电压端，所述第二电容器的另一端接地，其中所述直流电压端被配置成经由所述第六传输线、所述第一子输出网络和所述第二子输出网络向所述主放大器和辅放大器提供直流偏置电压。
根据本申请的一些实施例，所述合路匹配网络包括第三电感器、第四电感器和第三电容器，其中所述第三电感器和所述第三电容器串 联连接在直流电压端和接地端之间，所述组合节点连接至所述第三电感器和所述第三电容器之间的连接点，所述第四电感器连接在所述第三电感器和所述第三电容器之间的所述连接点与所述合路匹配网络的输出端之间，其中所述直流电压端被配置成经由所述第三电感器、所述第一子输出网络和所述第二子输出网络向所述主放大器和辅放大器提供直流偏置电压。
根据本申请的一些实施例，其中所述合路匹配网络还包括输出电容器，所述输出电容器连接在所述合路匹配网络的输出端和所述多赫蒂放大器的射频输出端之间并且被配置成阻断所述直流电压端的直流信号传输到所述多赫蒂放大器的射频输出端。
根据本申请的一些实施例，所述合路匹配网络被配置成使得所述节点阻抗呈现复数阻抗。
根据本申请的一些实施例，所述第一电感器和所述第二电感器中的至少一个包括多条键合线。
根据本申请的一些实施例，所述第一电感器和所述第二电感器中的至少一个包括微带线。
根据本申请的一些实施例，所述第一传输线和所述第二传输线中的至少一个包括带状线、共面波导或基片集成波导。
本申请的另一实施例提供了一种多赫蒂放大器，包括：主放大器；辅放大器；以及根据前述实施例中任一实施例所述的输出网络，所述输出网络被配置成接收所述主放大器的输出的第一放大信号和所述辅放大器输出的第二放大信号，使得所述第一放大信号和所述第二放大信号在所述组合节点处组合以提供给所述多赫蒂放大器的射频输出端。
根据本申请的一些实施例，所述多赫蒂放大器包括向所述主放大器提供载波信号以生成所述第一放大信号的载波信号输入路径、以及向所述辅放大器提供峰值信号以生成所述第二放大信号的峰值信号输入路径，所述多赫蒂放大器包括位于所述载波信号输入路径和所述峰值信号输入路径中的至少一个的相位延迟元件，所述相位延迟元件被配置成在提供给所述主放大器的载波信号和提供给所述辅放大器的峰值信号之间形成相位差，所述相位差小于90度。
根据本申请的一些实施例，所述主放大器和所述辅放大器均包括 晶体管，第一传输线的第一特性阻抗Z Main、第一电角度θ Main、所述第二传输线的第二特性阻抗Z Aux和第二电角度θ Aux分别为：
Figure PCTCN2021140419-appb-000001
Figure PCTCN2021140419-appb-000002
Figure PCTCN2021140419-appb-000003
Figure PCTCN2021140419-appb-000004
其中θ IN表示所述相位差，ω是所述多赫蒂放大器的中心工作频率，R opt是所述晶体管的最佳工作负载，L P1表示所述第一电感器的第一电感值，L P2表示所述第二电感器的第二电感值，C DS是晶体管的漏极寄生电容，α表示使得所述辅放大器开启工作的功率水平，x是常数。
根据本申请的一些实施例，所述相位差θ IN为
Figure PCTCN2021140419-appb-000005
其中α大于0小于0.5，其中1≤x≤10。
根据本申请的一些实施例，所述组合节点处的节点阻抗Z combine满足以下公式：
Figure PCTCN2021140419-appb-000006
Figure PCTCN2021140419-appb-000007
根据本申请的一些实施例，所述多赫蒂放大器包括多个所述辅放大器，所述输出网络包括分别与所述多个辅放大器一一对应的多个所述第二子输出网络，所述第一子输出网络被配置成接收所述主放大器的输出的第一放大信号，每个第二子输出网络被配置成接收所述多个辅放大器中相应的辅放大器输出的第二放大信号，使得所述第一放大信号和每个辅放大器输出的第二放大信号在所述组合节点处进行组合以提供给所述多赫蒂放大器的射频输出端。
本申请的又一实施例提供了一种设计多赫蒂放大器的方法，所述多赫蒂放大器包括主放大器、至少一个辅放大器、以及如前述实施例 所述的输出网络，其中所述方法包括：选取用于所述主放大器和辅放大器的晶体管；确定所述多赫蒂放大器的目标回退功率范围，并根据所述目标回退功率范围、所述第一电感器的第一电感值、所述第二电感器的第二电感值、所述晶体管的漏极寄生电容、所述多赫蒂放大器的中心工作频率和最佳工作负载确定所述第一传输线的第一特性阻抗和第一电角度、以及所述第二传输线的第二特性阻抗和第二电角度；以及根据所述中心工作频率、所述第一传输线的第一特性阻抗、第一电角度、所述第二传输线的第二特性阻抗、第二电角度、所述最佳工作负载、所述第一电感器的第一电感值、所述第二电感器的第二电感值和所述目标回退功率范围确定所述组合节点处的节点阻抗。
根据本申请的一些实施例，其中根据所述目标回退功率范围、所述第一电感器的第一电感值、所述第二电感器的第二电感值、所述晶体管的漏极寄生电容、所述多赫蒂放大器的中心工作频率和最佳工作负载确定所述第一传输线的第一特性阻抗和第一电角度、以及所述第二传输线的第二特性阻抗和第二电角度包括：通过以下公式分别计算所述第一传输线的第一特性阻抗Z Main和第一电角度θ Main、以及所述第二传输线的第二特性阻抗Z Aux和第二电角度θ Aux：
Figure PCTCN2021140419-appb-000008
Figure PCTCN2021140419-appb-000009
Figure PCTCN2021140419-appb-000010
Figure PCTCN2021140419-appb-000011
其中θ IN表示所述相位差，ω是所述多赫蒂放大器的中心工作频率，R opt是所述晶体管的最佳工作负载，L P1表示所述第一电感器的第一电感值，L P2表示所述第二电感器的第二电感值，C DS是晶体管的漏极寄生电容，α表示使得所述辅放大器开启工作的功率水平系数，x是常数，
其中根据所述中心工作频率、所述第一传输线的第一特性阻抗、第一电角度、所述第二传输线的第二特性阻抗、第二电角度、所述最佳工作负载、所述第一电感器的第一电感值、所述第二电感器的第二 电感值和所述目标回退功率范围确定所述组合节点处的节点阻抗包括通过如下公式确定所述组合节点处的节点阻抗Z combine：
Figure PCTCN2021140419-appb-000012
Figure PCTCN2021140419-appb-000013
其中所述目标回退功率范围为
Figure PCTCN2021140419-appb-000014
在根据本申请的一些实施例的用于多赫蒂放大器的输出网络中，设置了与所述多赫蒂放大器的主放大器对应的第一子输出网络、与所述多赫蒂放大器的辅放大器对应的第二子输出网络、组合节点和合路匹配网络，第一子输出网络包括由第一电感器和第一传输线串联组成的第一串联电路，所述第二子输出网络包括由第二电感器和第二传输线组成的第二串联电路，所述第一串联电路和所述第二串联电路被配置成使得所述组合节点处的节点阻抗匹配至所述主放大器和所述辅放大器的目标负载阻抗，从而使得多赫蒂放大器从低功率到高功率均能高效工作，进而实现了多赫蒂放大器的负载调制的更深的回退功率(即更大的回退功率范围)和更宽的工作带宽。另一方面，所述第一串联电路和所述第二串联电路包含较少的元器件数目，从而简化了第一子输出网络和第二子输出网络的结构，有利于实现多赫蒂放大器的小型化设计。
根据在下文中所描述的实施例，本申请的这些和其他方面将是清楚明白的，并且将参考在下文中所描述的实施例而被阐明。
附图说明
在下面结合附图对于示例性实施例的描述中，本申请的技术方案更多细节、特征和优点被公开，在附图中：
图1A示意性示出了相关技术中的多赫蒂放大器的示例性原理图；
图1B示意性示出了相关技术中的用于多赫蒂放大器的匹配网络的示例性电路结构图；
图2示意性示出了相关技术中的一种改进的多赫蒂放大器的示例性原理图；
图3示意性示出了根据本申请的一些实施例的用于多赫蒂放大器的输出网络的示例性原理图；
图4A示意性示出了根据本申请的一些实施例的图3中的输出网络在低功率下实现负载调制的示例性原理图；
图4B示意性示出了根据本申请的一些实施例的图3中的输出网络在高功率下实现负载调制的示例性原理图；
图5示意性示出了根据本申请的一些实施例的合路匹配网络的示例性原理图；
图6示意性示出了根据本申请的另一些实施例的合路匹配网络的示例性原理图；
图7示意性示出了根据本申请的另一些实施例的合路匹配网络的示例性原理图；
图8A示意性示出了根据本申请的一些实施例的多赫蒂放大器的示例性电路结构图；
图8B示意性示出了根据本申请的另一些实施例的多赫蒂放大器的示例性电路结构图；
图8C示意性示出了根据本申请的另一些实施例的多赫蒂放大器的示例性电路结构图；
图9示意性示出了根据本申请的一些实施例的第一电感器或第二电感器的示例性电路结构图；
图10A示意性示出了根据本申请的一些实施例的多赫蒂放大器的性能示例图；
图10B示意性示出了根据本申请的另一些实施例的多赫蒂放大器的性能示例图；
图11示意性示出了根据本申请的又一实施例的多赫蒂放大器的示例性原理图；
图12示意性示出了根据本申请的一些实施例的设计多赫蒂放大器的方法的流程图。
图13A示意性示出了根据本申请的一些实施例的第一传输线和第二传输线的特性阻抗的取值示例图；
图13B示意性示出了根据本申请的一些实施例的第一传输线和第二传输线的电角度的取值示例图；
图13C示意性示出了根据本申请的一些实施例的第一传输线的第一特性阻抗和第一电感器的第一电感值的关系的示例图；
图13D示意性示出了根据本申请的一些实施例的第二传输线的第二特性阻抗和第二电感器的第二电感值的关系的示例图。
具体实施方式
下面将参照附图更详细地描述本申请的若干个实施例以便使得本领域技术人员能够实现本申请的技术方案。本申请的技术方案可以体现为许多不同的形式和目的，并且不应局限于本文所阐述的实施例。提供这些实施例是为了使得本申请的技术方案清楚完整，但所述实施例并不限定本申请的保护范围。
除非另有定义，本文中使用的所有术语(包括技术术语和科学术语)具有与本申请所属领域的普通技术人员所通常理解的相同含义。将进一步理解的是，诸如那些在通常使用的字典中定义的之类的术语应当被解释为具有与其在相关领域和/或本说明书上下文中的含义相一致的含义，并且将不在理想化或过于正式的意义上进行解释，除非本文中明确地如此定义。
图1A示意性示出了相关技术中的多赫蒂放大器的示例性原理图110。如图1A所示，多赫蒂放大器包括两个放大器(主放大器和辅放大器)，主放大器和辅放大器分别接入功率分配器的两个输出端口，另外TLIN负责调整从功率分配器输出的两路信号(即主放大器和辅放大器的输入信号)的相位，以满足多赫蒂放大器负载牵引的工作需求。多赫蒂放大器输出侧包括四个子网络：1)主路匹配网络，负责为主放大器提供直流偏置电压V DD1以及匹配最优负载Z opt，M；2)辅路匹配网络，负责为辅放大器提供直流偏置电压V DD2以及匹配最优负载Z opt，A；3)合路匹配网络，负责将放大器的射频输出端负载匹配成合路点阻抗；4)四分之一波长传输线TL OUT，，负责实现多赫蒂负载牵引(负载调制)。V DD1和V DD2分别为主放大器和辅放大器的漏极直流偏置电压，C M和C A为隔直电容。其中，主放大器工作在B类或者AB类，辅放大器工作在C类。两个放大器不是轮流工作，而是主放大器一直工作，当输入功率达到设定的峰值时辅放大器开始工作。主放大器输出路径中的四分之一波长传输线可以起到相位补偿的作用，使得主放大器输 出路径中的输出信号和辅放大器输出路径中的输出信号在合路点C处相位相同。
在相关技术中，存在实现上述的主路匹配网络和辅路匹配网络的多种方案，如图1B所示，该匹配网络通常包括多节传输线、电容器、电感器，这些方案增加了多赫蒂放大器的整体复杂度和电路尺寸。随着通信技术的不断发展，多输入多输出(MIMO)系统得到越来越广泛的应用，MIMO系统的射频前端系统包含多个(例如，几十甚至上百个)射频链路单元，这对射频链路单元中的功率放大器的小型化设计提出了越来越高的要求，而传统方案复杂度高、使用元器件多、电路尺寸大，难以满足小型化放大器的设计需求。
另一方面，电路元器件的增多给功率放大器集成化设计带来更多问题，不仅设计难度加大，整体电路尺寸增大，芯片成本提高，而且电路的损耗也变得更大，功放的效率也会降低，这导致高效、节能、低成本的系统设计变得更加困难。
另外，随着通信系统的不断迭代，通信带宽在成倍的增长，例如，在5G场景下通信带宽已经达到500MHz甚至更高，这对功率放大器的工作带宽提出了很高的挑战。在图1A中，多赫蒂放大器的负载调制是由四分之一波长传输线TL OUT实现的，而该结构只有较窄的工作带宽(往往小于200MHz)，因此这种架构远不能满足如今系统宽带工作的要求。
图2示意性示出了相关技术中的一种改进的多赫蒂放大器的示例性原理图。如图2所示，这种改进的多赫蒂放大器包括宽频功率分配器、相移器、载波放大器、峰值放大器、峰值补偿线和阶跃阻抗合路器，其中，载波放大器包括顺次连接的载波输入匹配网络、载波晶体管和宽频多模式匹配网络；峰值放大器包括顺次连接的峰值输入匹配网络、峰值晶体管和宽频单模式匹配网络；宽频功率分配器接收输入的功率并分别连接相移器和峰值输入匹配网络；相移器连接至载波输入匹配网络；宽频单模式匹配网络连接至峰值补偿线；并且阶跃阻抗合路器分别连接宽频多模式匹配网络和峰值补偿线进行功率输出。图2所示的改进的多赫蒂放大器的匹配网络可以优化多赫蒂放大器的带宽、效率、回退功率范围等指标，但这些现有方案需要过大量的元器件来替换传统的多赫蒂放大器的匹配网络，这会造成放大器电路尺寸 进一步增大的问题，难以实现功率放大器的小型化、集成化设计。
图3示意性示出了根据本申请的一些实施例的用于多赫蒂放大器的输出网络310的示例性原理图。
如图3所示，输出网络310包括与多赫蒂放大器的主放大器对应的第一子输出网络311、与多赫蒂放大器的辅放大器对应的第二子输出网络312、组合节点313和合路匹配网络314，其中所述第一子输出网络311的输出端和所述第二子输出网络312的输出端均连接至组合节点313，合路匹配网络314被配置成将所述组合节点连接至所述多赫蒂放大器的射频输出端。
示例性地，第一子输出网络311包括由第一电感器L P1和第一传输线TL Main串联组成的第一串联电路，第二子输出网络312包括由第二电感器L P2和第二传输线TL Aux组成的第二串联电路，其中所述第一串联电路被配置成连接在所述主放大器的输出端和组合节点313之间，所述第二串联电路被配置成连接在所述辅放大器的输出端和组合节点313之间，所述第一串联电路和所述第二串联电路被配置成使得组合节点313处的节点阻抗Z combine匹配至所述主放大器和所述辅放大器的目标负载阻抗。如图3所示，Z combine为从组合节点313向合路匹配网络314看去的等效阻抗，在一些情形下可视为组合节点313处电压U TC与流入合路匹配网络314的电流I TC之比。
在图3所示的实施例中，上述的第一串联电路形成了第一子输出网络311，上述的第二串联电路形成了第二子输出网络，但这并不排除第一子输出网络和第二子输出网络包括其他元件的情形。例如，在其他实施例中，第一子输出网络311还可以包括所述第一串联电路之外的其他电路器件，例如用于隔离直流的电容器；同样地，第二子输出网络312还可以包括所述第二串联电路之外的其他电路器件，例如用于隔离直流的电容器。另外，组合节点313指示第一子输出网络311、第二子输出网络312和合路匹配网络314的公共连接点，示例性地，组合节点313可以是第一子输出网络311、第二子输出网络312和合路匹配网络314在电气上的公共接点，组合节点313也可以是第一子输出网络311输出端的电气节点，组合节点313还可以是第二子输出网络312的输出端的电气节点，甚至组合节点313可以是合路匹配网络314的输入端的电气节点。
具体地，下面结合图4A和图4B来阐明输出网络的阻抗匹配过程。
如图4A所示，在低功率下，辅放大器未开启，因此可以将其等效为开路状态，此时第二子输出网络312所在支路(以下简称为辅路)在组合节点313提供辅路阻抗Z off，其与节点阻抗Z combine并联接在第一子输出网络311所在支路(以下简称为主路)的一端。在回退功率下，所述第一串联电路(包括第一电感器L P1和第一传输线TL Main)可以将辅路阻抗Z off和节点阻抗Z combine的并联阻抗Z off//Z combine转换为所述主放大器在回退功率下的目标负载阻抗(图4A中的Z opt，BO)。对于主放大器或辅放大器(通常被实施为晶体管)而言，其目标负载阻抗指示特定功率水平下放大器的最佳功率匹配阻抗，即能够使得放大器在特定功率水平下效率达到最高值的负载阻抗。目标负载阻抗取决于放大器本身的参数和实际的功率水平，其可以通过理论计算的方式得到，也可以通过实验测定的方法得到。所述第一串联电路通过将并联阻抗Z off//Z combine转换为所述主放大器在回退功率下的目标负载阻抗Z opt，BO，可以使得主放大器在回退功率下仍然能够高效率地工作。
如图4B所示，在高功率下辅放大器开启，流过辅路的电流为I T2，流过主路的电流为I T1，根据基尔霍夫电压定律和基尔霍夫电流定律，可以得到此时主路的合路等效阻抗为(1+I T2/I T1)*Z combine，辅路的合路等效阻抗为(1+I T1/I T2)*Z combine，因此电流I T2可以动态地调制主路的合路等效阻抗和辅路的合路等效阻抗。在饱和功率下，所述第一串联电路(包括第一电感器L P1和第一传输线TL Main)可以将主路的合路等效阻抗(1+I T2/I T1)*Z combine转换为所述主放大器在饱和功率下的目标负载阻抗(图4B中的Z opt，M)。所述第二串联电路(包括第二电感器L P2和第二传输线TL Aux)可以将辅路的合路等效阻抗(1+I T1/I T2)*Z combine转换为所述辅放大器在饱和功率下的目标负载阻抗(图4B中的Z opt，A)。所述第一串联电路和所述第二串联电路分别通过将主路的合路等效阻抗和辅路的合路等效阻抗转换为所述主放大器和所述辅放大器在饱和功率下的对应目标负载阻抗，可以使得主放大器和辅放大器在饱和功率下均能够高效率地工作。
这里所提到的“合路等效阻抗”指示在某一路径上向合路节点(即组合节点313)看去的等效阻抗。示例性地，如图4B所示，主路的合路等效阻抗即为主路输出端电压U T1与主路输出电流I T1之比，辅路的 合路等效阻抗即为辅路输出端电压U T2与辅路输出电流I T2之比。第一电感器L P1和第二电感器L P2可以通过多种形式来实现(例如键合线)。
所述主放大器和所述辅放大器可以包括且不限于例如基于VDMOS、LDMOS或GaN的功率晶体管，不同的晶体管技术在输出功率、增益和性能方面提供不同的性能优势。例如，可以根据频率、带宽、成本等要求来选取晶体管的类型。根据本申请的一些实施例，所述主放大器和所述辅放大器可以是相同类型的功率晶体管(如基于GaN的功率晶体管)，且用作主放大器的晶体管和用作辅放大器的晶体管的参数和尺寸可以完全相同。在其他实施例中，用作主放大器的晶体管和用作辅放大器的晶体管至少在晶体管类型、参数和尺寸等方面中的一个方面存在差异。根据本申请的另外的实施例，主放大器或辅放大器可包括多个晶体管。本文对主放大器和辅放大器的具体实施方式不作具体限制。
通过在多赫蒂放大器中使用图3所示的输出网络310，可以在不同功率水平下均将组合节点313处的节点阻抗Z combine匹配至多赫蒂放大器的主放大器和辅放大器的目标负载阻抗，使得所述主放大器在回退功率下仍然能够高效率地工作，并且使得所述主放大器和所述辅放大器在饱和功率下均能够高效率地工作，即，使得多赫蒂放大器在不同功率水平下均能够高效率地工作。另外，相较于传统多赫蒂放大器中的输出网络，输出网络310所包含的元器件的数量大大减少，输出网络310的结构得以简化，减小了相关电路的尺寸，可以满足小型化放大器的设计需求。此外，如将在下文中进一步描述的，通过合理设置所述第一串联电路和所述第二串联电路中的电感器与传输线的特征参数，可以使得多赫蒂放大器在高效率工作的同时，具备较大的工作带宽和更深的回退功率(即更大的回退功率范围)。
在一些实施例中，所述第一传输线和所述第二传输线中的至少一个仅包括微带线。微带线是目前混合微波集成电路和单片微波集成电路使用最多的一种平面型传输线，它是一根带状导线(信号线)，与地层之间用一种电介质隔离开。影响微带线的特性阻抗的因素包括微带线的厚度、宽度、与地层的距离以及电介质的介电常数等，微带线的长度可以对应于微带线的电角度。示例性地，可以用微带线来实现所述第一传输线和所述第二传输线。相应地，可以基于第一传输线和 所述第二传输线的特性阻抗和电角度来配置微带线的长度、宽度等尺寸参数。通过使用微带线来实现所述第一传输线和所述第二传输线，可以获取满足特征参数要求的传输线，从而可以使得多赫蒂放大器具有较小的电路尺寸、较高的工作效率、较大的工作带宽和更深的回退功率(即更大的回退功率范围)。特别地，可以通过采用选取高介电常数的基材来实现微带线，以进一步减少相关电路的尺寸。
在其他实施例中，第一传输线和第二传输线中的至少一个可以包括带状线、共面波导或基片集成波导。带状线是置于两个平行的接地平面(或电源平面)之间的电介质之间的高频传输导线。带状线具有体积小、重量轻、频带宽、品质因数高、工艺简单、成本低廉等优点，适于制作高性能(宽频带、高品质因数、高隔离度)无源元件。共面波导(CPW)通过在介质基片的一个面上制作出中心导体带、并在紧邻中心导体带的两侧制作出导体平面而构成，在毫米波频段，共面波导比微带线和带状线电路的损耗更小。基片集成波导(SIW)利用金属通孔在介质基片上实现波导的场传播模式，具有低差损、低辐射、高品质因数等优点。在一些实施例中，所述第一传输线和所述第二传输线中的至少一个可以仅由带状线、共面波导或基片集成波导中的一个构成。
图5示意性示出了根据本申请的一些实施例的合路匹配网络514的示例性原理图。根据本申请的一些实施例，合路匹配网络被配置成使得节点阻抗呈现复数阻抗
如图5所示，合路匹配网络514包括第三传输线514A、第四传输线514B和第一电容器C 1，第三传输线514A连接在组合节点513和合路匹配网络514的输出端之间，第四传输线514B连接在合路匹配网络514的输出端和直流电压端V DD之间，第一电容器C 1的一端连接至直流电压端V DD，第一电容器C 1的另一端接地，其中直流电压端V DD被配置成：经由第四传输线514B、第三传输线514A、第一子输出网络511和第二子输出网络512向主放大器和辅放大器提供直流偏置电压。
示例性地，第三传输线514A、第四传输线514B可以由微带线来实现。可以通过设置第三传输线514A、第四传输线514B、第一电容器C 1的特征参数来调整组合节点513处的节点阻抗Z combine，从而有助于实现前述阻抗匹配以优化多赫蒂放大器的各项性能指标(详见上文关 于图4A和图4B描述的内容)。此外，第一电容器C 1可以阻止射频信号经由第四传输线514B进入直流供电线路中，并且能够减少甚至避免射频功率在合路匹配网络514中的损失。在传统的多赫蒂放大器中，主放大器和辅放大器各自都具有相应的直流偏置电路(参见图1A中的V DD1和V DD2)，而在本申请该实施例的技术方案中，主放大器和辅放大器共用直流偏置电路，并且该直流偏置电路可以集成在合路匹配网络514中，即：直流电压端V DD经由第四传输线514B、第三传输线514A、第一子输出网络511和第二子输出网络512向主放大器和辅放大器提供直流偏置电压，这有助于进一步减小多赫蒂放大器的电路尺寸。
图6示意性示出了根据本申请的另一些实施例的合路匹配网络614的示例性原理图。如图6所示，合路匹配网络614包括第五传输线614A、第六传输线614B、第七传输线614C和第二电容器C 2，第五传输线614A连接在组合节点613和合路匹配网络614的输出端之间，第六传输线614B连接在组合节点613和直流电压端V DD之间，第七传输线614C的一端连接至合路匹配网络614的输出端，第七传输线614C的另一端浮接，第二电容器C 2的一端连接至直流电压端V DD，第二电容器的另一端接地，其中直流电压端V DD被配置成：经由第六传输线614B、第一子输出网络611和第二子输出网络612向主放大器和辅放大器提供直流偏置电压。
示例性地，类似于上文关于图5所描述，在根据本申请的实施例的合路匹配网络614中，第五传输线614A、第六传输线614B、第七传输线614C可以由微带线来实现。可以通过设置第五传输线614A、第六传输线614B、第七传输线614C和第二电容器C 2的特征参数来调整组合节点613处的节点阻抗Z combine，从而有助于实现前述阻抗匹配以优化多赫蒂放大器的各项性能指标(详见上文关于图4A和图4B描述的内容)。特别地，与图5中第三传输线514A、第四传输线514B和组合节点513的相对位置相比，在图6的实施例中，与直流电压端V DD连接的第六传输线614B更靠近组合节点613，这可以进一步降低多赫蒂放大器的基带阻抗并且增强多赫蒂放大器在宽带信号下的线性度，此外，还有助于提高数字预失真友好度(即，对具有较高的峰均功率比和较大的带宽的调制信号，经数字预失真技术处理后的输出信号具有极小的非线性失真)。
此外，第二电容器C 2可以阻止射频信号经由第六传输线614B进入直流供电线路中，并且能够减少甚至避免射频功率在合路匹配网络614中的损失。在传统的多赫蒂放大器中，主放大器和辅放大器各自都具有相应的直流偏置电路(参见图1A中的V DD1和V DD2)，而在该实施例中，主放大器和辅放大器共用直流偏置电路，并且该直流偏置电路可以集成在本申请提供的合路匹配网络614中，即：直流电压端V DD经由第六传输线614B、第一子输出网络611和第二子输出网络612向主放大器和辅放大器提供直流偏置电压，这有助于进一步减小多赫蒂放大器的电路尺寸。
图7示意性示出了根据本申请的又一些实施例的合路匹配网络714的示例性原理图。如图7所示，合路匹配网络714包括第三电感器L P3、第四电感器L P4和第三电容器C 3，其中第三电感器L P3和第三电容器C 3串联连接在直流电压端V DD和接地端之间，组合节点713连接至第三电感器L P3和第三电容器C 3之间的连接点，第四电感器L P4连接在第三电感器L P3和第三电容器C 3之间的连接点与合路匹配网络714的输出端之间，其中直流电压端V DD被配置成：经由第三电感器L P3、第一子输出网络711和第二子输出网络712向主放大器和辅放大器提供直流偏置电压。
示例性地，可以通过设置第三电感器L P3、第四电感器L P4和第三电容器C 3的特征参数(电感值、电容值)来调整组合节点713处的节点阻抗Z combine，从而有助于实现前述阻抗匹配以优化多赫蒂放大器的各项性能指标(详见上文关于图4A和图4B描述的内容)。此外，第三电容器C 3可以阻止射频信号进入直流供电线路中，并且能够减少甚至避免射频功率在合路匹配网络714中的损失。在传统的多赫蒂放大器中，主放大器和辅放大器各自都具有相应的直流偏置电路(参见图1A中的V DD1和V DD2)，而在本申请中，主放大器和辅放大器共用直流偏置电路，并且该直流偏置电路可以集成在本申请提供的合路匹配网络714中，即：直流电压端V DD经由第三电感器L P3、第一子输出网络711和第二子输出网络712向主放大器和辅放大器提供直流偏置电压，这有助于进一步减小多赫蒂放大器的电路尺寸。
在上文关于图5、图6和图7描述的实施例中，合路匹配网络中均集成了直流偏置电路，但这不是必须的，可以根据实际应用来调整直 流偏置电路的数量和其在多赫蒂放大器电路中的位置。示例性地，当主放大器和辅放大器的配置参数不相同时(例如，当它们不是一种类型的晶体管时)，可以为主放大器和辅放大器分别设置对应的直流偏置电路。
在一些实施例中，上文关于图5、图6和图7描述的合路匹配网络还包括输出电容器，所述输出电容器连接在所述合路匹配网络的输出端和所述多赫蒂放大器的射频输出端之间并且被配置成阻断所述直流电压端的直流信号传输到所述多赫蒂放大器的射频输出端。利用所述输出电容器，来自所述直流电压端的直流信号不会被传输到所述多赫蒂放大器的射频输出端，从而可以保护敏感的射频元件(负载)免受直流电的影响。
本申请的另外的实施例提供了一种多赫蒂放大器，该多赫蒂放大器包括主放大器、辅放大器、以及前述根据本申请的任一种输出网络，所述输出网络被配置成接收所述主放大器的输出的第一放大信号和所述辅放大器输出的第二放大信号，使得所述第一放大信号和所述第二放大信号在所述组合节点处组合以提供给所述多赫蒂放大器的射频输出端。由于所述多赫蒂放大器包括根据本申请前述实施例的输出网络，因此所述多赫蒂放大器具有相应的输出网络带来的优点。
示例性地，在所述多赫蒂放大器的输出网络包括关于图5描述的合路匹配网络514时，可以通过设置第三传输线514A、第四传输线514B、第一电容器C 1的特征参数来调整组合节点513处的节点阻抗Z combine，从而有助于实现前述阻抗匹配以优化多赫蒂放大器的各项性能指标(详见上文关于图4A和图4B描述的内容)。此外，如上文所述，第一电容器C 1可以阻止射频信号经由第四传输线514B进入供电线路中，并且能够减少甚至避免射频功率在合路匹配网络514中的损失。另外，在这种情况下，主放大器和辅放大器可以共用集成在合路匹配网络514中的直流偏置电路，从而可以进一步减小所述多赫蒂放大器的电路尺寸。基于这种电路结构的一种多赫蒂放大器可以参见下文关于图8A所描述的多赫蒂放大器810。
图8A示意性示出了根据本申请的一些实施例的多赫蒂放大器810的中的部分元件的示例性布局图。多赫蒂放大器810是基于LDMOS或GaN工艺晶体管、配合外围的印刷电路板800A上的匹配元件而形 成的两路多赫蒂放大器。多赫蒂放大器810包括向主放大器提供载波信号以生成所述第一放大信号的载波信号输入路径、以及向所述辅放大器提供峰值信号以生成所述第二放大信号的峰值信号输入路径，其中多赫蒂放大器810包括位于所述载波信号输入路径和所述峰值信号输入路径中的至少一个的相位延迟元件813，所述相位延迟元件被配置成在提供给所述主放大器的载波信号和提供给所述辅放大器的峰值信号之间形成相位差，所述相位差小于90度。
在该实施例中，多赫蒂放大器810包括已封装的主放大器芯片814A和辅放大器芯片814B，相位延迟元件813可以被实施为微带线的形式，多赫蒂放大器810还包括功率分配器812，其与多赫蒂放大器810的射频信号输入端811电连接。第一子输出网络被实施为第一电感器L P1和第一微带线815A的串联电路，第二子输出网络被实施为第二电感器L P2和第二微带线815B的串联电路。合路匹配网络包括微带线816A、微带线816B和表贴SMD电容817，它们分别对应于上文关于图5描述的第三传输线514A、第四传输线514B和第一电容器C 1，并且它们之间的连接关系与上文关于图5描述的一致，在此不再赘述。818表示直流电压端，用于接收直流电压信号，表贴SMD电容816C为隔直电容。多赫蒂放大器810的射频信号输出端被示出为819。本文对相位延迟元件813的具体实施方式不作限制，相位延迟元件813包括但不限于微带线。虽然在图8A中，相位延迟元件被示出为位于峰值放大器814B的输入路径中，替代性地，也可以在主放大器的输入路径中设置相位延迟元件，或者，在主放大器的输入路径和辅放大器的输入路径中同时设置相位延迟元件。换言之，本领域技术人员可以通过不同的方式来实现提供给所述主放大器的载波信号和提供给所述辅放大器的峰值信号之间小于90度的相位差。
如前所述，根据本申请的一些实施例，前述的合路匹配网络被配置成使得所述节点阻抗呈现复数阻抗。相位延迟元件813使得提供给所述主放大器的载波信号和提供给所述辅放大器的峰值信号之间形成小于90度的相位差，这可以进一步提升主放大器和辅放大器在节点阻抗呈现复数阻抗的情形中的工作效率。
图8B示意性示出了根据本申请的另一些实施例的多赫蒂放大器820的示例性电路结构图。类似于上文关于图8A所描述的多赫蒂放大 器810，如图8B所示，多赫蒂放大器820是基于LDMOS或GaN工艺晶体管、配合外围的印刷电路板800B上的匹配元件而形成的两路多赫蒂放大器。多赫蒂放大器820包括向主放大器提供载波信号以生成所述第一放大信号的载波信号输入路径、以及向所述辅放大器提供峰值信号以生成所述第二放大信号的峰值信号输入路径，其中多赫蒂放大器820包括位于所述载波信号输入路径和所述峰值信号输入路径中的至少一个的相位延迟元件(例如，如图8B中示出的位于峰值信号输入路径中的微带线823)，所述相位延迟元件被配置成在提供给所述主放大器的载波信号和提供给所述辅放大器的峰值信号之间形成相位差，所述相位差小于90度。
与上文关于图8A所描述的多赫蒂放大器810不同，在多赫蒂放大器820中，主放大器和第一电感(如图8B中的电感8241所示)位于同一封装体824A中，辅放大器和第二电感位于同一封装体824B中第一子输出网络包括微带线825A和与其串联的位于主放大器所在的封装体内的电感8241，第二子输出网络包括微带线825B和与其串联的位于辅放大器所在的封装体内的另一电感。合路匹配网络包括微带线826A、微带线826B、微带线826C和表贴SMD电容827，它们分别对应于上文关于图6描述的第五传输线614A、第六传输线614B、第七传输线614C和第二电容器C 2。828表示直流电压端，表贴SMD电容826D为隔直电容。多赫蒂放大器820的射频输入端和射频输出端分别为821和829。与直流电压端828连接的微带线826B更靠近组合节点，这可以进一步降低多赫蒂放大器的基带阻抗并且增强多赫蒂放大器在宽带信号下的线性度。此外，由于主放大器824A和辅放大器824B分别和对应的电感器封装在一起，这进一步提高了元器件的集成度，进一步减小多赫蒂放大器820的电路尺寸。
图8C示意性示出了根据本申请的另一些实施例的多赫蒂放大器830的示例性电路结构图。如图8C所示，多赫蒂放大器830被形成于LGA基板上。多赫蒂放大器830是一个基于LDMOS或GaN工艺的单片微波集成电路(MMIC)，封装在一个LGA基板封装800C内。多赫蒂放大器830与图8A和图8B中的多赫蒂放大器的主要区别在于印刷电路板上的电路元器件均被集成到LGA基板上，以进一步提高集成度。其中，主放大器834A和辅放大器834B均为未封装的裸芯(只包 含寄生电容)，主放大器834A和辅放大器834B的输出分别通过键合线837A和837B连接到微带线835A和835B，键合线837A和837B分别对应于上文实施例中描述的第一串联电路和第二串联电路中的第一电感器L P1和第一电感器L P2。微带线835A和835B分别对应于上文实施例中描述的第一子输出网络和第二子输出网络中的第一传输线和第二传输线。836A和836B为裸芯上的输出键合焊盘，微带线833，835A和835B可以通过采用高介电常数的基材实现，以减少整体电路面积尺寸。合路匹配网络则由电感839A、电容839C和电感839B组成，它们分别对应于上文关于图7描述的第三电感器L P3、第四电感器L P4和第三电容器C 3。这些电容可以通过金属-氧化物-金属电容、边缘电容或者表贴SMD电容实现，第三电感器和第四电感器则可以由键合线实现，键合线还通过引脚焊盘842连接漏极直流电压端。引脚焊盘831和841分别表示多赫蒂放大器的射频信号输入端和射频信号输出端。
在本申请的上述实施例中，第一电感器L P1、第一电感器L P2可以由键合线实现，图9示意性示出了根据本申请的一些实施例的第一电感器L P1、第一电感器L P2的示例性电路结构图。上述第一电感器和上述第二电感器中的至少一个可包括多条键合线。
如图9所示，913为晶体管(主放大器或辅放大器)QFN封装管壳，914为晶体管芯片裸芯，915为栅极键合焊盘，其通过键合线917连接到芯片的输入引脚918，并且916为漏极键合焊盘，其通过多条键合线919连接到芯片的输出引脚920。在一些实施例中，这些键合线919中的各条键合线彼此可以并联连接，通过调整键合线919的数量、长度、高度等参数可以方便地调整其等效电感值，以实现预期的第一电感器L P1、第一电感器L P2的电感值，进而有助于优化放大器的各项性能指标。
当然，第一电感器和第二电感器的具体实施方式并不局限于键合线，在其他实施例中，也可以采用微带线的方式来实现上述的第一电感器和第二电感器，本文不对第一电感器和第二电感器的具体形式做任何的特殊限制。
图10A和10B示意性示出了通过仿真实验获得根据本申请的一些实施例的多赫蒂放大器的性能示例图。在该实施例中，多赫蒂放大器的中心工作频率是2GHz，总输出功率为16W，主放大器和辅放大器 的输出电容(晶体管的漏极寄生电容)为1.02pF，第一电感器和第二电感器的电感值为0.25pF。第一传输线的特性阻抗为53Ohm，电角度为44.7°，第二传输线的特性阻抗为37.5Ohm，电角度为80.9°。合路匹配网络使得节点阻抗Z combine呈现复数阻抗(14.23-j5.89)Ohm。相位延迟元件的电角度为37.76°。图10A对应于图8B所示的多赫蒂放大器820，图10B对应于图8C所示的多赫蒂放大器830。
如图10A所示，在1800MHz到2170MHz工作频率之间，曲线1011指示多赫蒂放大器820的效率随输出功率的变化情况，曲线1012指示多赫蒂放大器820的增益随输出功率的变化情况，可以看出，多赫蒂放大器820能够获得超过42dBm的饱和输出功率(1013)，同时实现10dB功率回退(1014)下的高效率工作，即多赫蒂放大器820的回退功率范围在10dB左右。
如图10B所示，在1820MHz到2155MHz工作频率之间，曲线1021指示多赫蒂放大器830的效率随输出功率的变化情况，曲线1022指示多赫蒂放大器830的增益随输出功率的变化情况，由于多赫蒂放大器830采用的LGA基板和元器件产生相对更大的损耗，因此图10B示出的效率比图10A略有降低(但多赫蒂放大器830具有更高的集成度和更小的电路尺寸)。从图10B可以看出，多赫蒂放大器830能够获得超过40dBm的饱和输出功率(1023)，同时实现10dB功率回退(1024)下的高效率工作，即多赫蒂放大器830的回退功率范围在10dB左右。
根据本申请的实施例，在以上描述的多赫蒂放大器的实施例中，主放大器和辅放大器均包括晶体管，第一传输线的第一特性阻抗Z Main、第一电角度θ Main以及第二传输线的第二特性阻抗Z Aux和第二电角度θ Aux分别为：
Figure PCTCN2021140419-appb-000015
Figure PCTCN2021140419-appb-000016
Figure PCTCN2021140419-appb-000017
Figure PCTCN2021140419-appb-000018
其中θ IN表示提供给主放大器的载波信号和提供给辅放大器的峰值信号之间小于90度的相位差(该相位差大于0度)，ω是多赫蒂放大器的中心工作频率，R opt是晶体管的最佳工作负载，L P1表示第一电感器的第一电感值，L P2表示第二电感器的第二电感值，C DS是晶体管的漏极寄生电容，α表示使得辅放大器开启工作的功率水平，x是常数。表示使得辅放大器开启工作的功率水平的α是相对于最大功率值而言，因此在一些实施例中，α可以被视作使得辅放大器开启工作的功率与最大功率的比值。由以上公式可以看出，常数x、第一电感器和第二电感器的电感值可影响第一传输线的第一特性阻抗Z Main、第一电角度θ Main以及第二传输线的第二特性阻抗Z Aux和第二电角度θ Aux，由此影响第一传输线、第二传输线的尺寸参数，通过选择合适的常数x、第一电感器和第二电感器的电感值可以实施适于制造的第一传输线、第二传输线。本文提到的“最佳工作负载”指的是让放大器(主放大器或辅放大器)在特定功率水平下达到最高效率的负载阻抗，但是该负载阻抗并未考虑晶体管的寄生参数(例如，漏极寄生电容C DS)，或者说，上述的R opt是晶体管去寄生参数后的最佳工作负载，因此，最佳工作负载通常是一个实数。
在根据本申请的一些实施例中，式1-4中的相位差θ IN满足：
Figure PCTCN2021140419-appb-000019
其中α大于0小于0.5，其中1≤x≤10。
在根据本申请的一些实施例中，组合节点处的节点阻抗Z combine满足以下公式：
Figure PCTCN2021140419-appb-000020
Figure PCTCN2021140419-appb-000021
在获得节点阻抗Z combine的基础上，可以设计适当结构的合路匹配网络。以上参照图5至图8C描述的合路匹配网络的具体仅仅是合路匹配网络的示例，但这并不构成对合路匹配网络的限制，基于节点阻抗 Z combine，可以设计和实现多种形式的合路匹配网络的具体结构。
图11示意性示出了根据本申请的另外的实施例的多赫蒂放大器1100的示例性原理图。如图11所示，多赫蒂放大器1100包括多个辅放大器(如图11所示的辅放大器A、辅放大器B)，输出网络1110包括分别与辅放大器A、辅放大器B对应的多个第二子输出网络(如图11所示的第二子输出网络1112A、1112B)，第一子输出网络1111被配置成接收主放大器的输出的第一放大信号，第二子输出网络1112A、1112B分别被配置成接收辅放大器A、辅放大器B输出的第二放大信号，使得第一放大信号和每个辅放大器输出的第二放大信号在组合节点1213处进行组合以提供给多赫蒂放大器1100的射频输出端。需要说明的是，虽然图11示出的多赫蒂放大器1100包括两个辅放大器，但这不构成对多赫蒂放大器的结构的限制，多赫蒂放大器可以包括更多的辅放大器(例如，三个、四个或更多个辅放大器)，即多赫蒂放大器可以是包括多个放大路径的多路多赫蒂放大器。包括本申请上述实施例所述的输出网络的多路多赫蒂放大器能够提供更大的工作带宽和更深的回退功率，在此不再赘述。
本申请的另外的实施例提供了一种设计多赫蒂放大器的方法，所述多赫蒂放大器包括主放大器、至少一个辅放大器、以及上文关于图3描述的输出网络310，图12示意性示出了根据本申请的一些实施例的设计多赫蒂放大器的方法的流程图1200。如图12所示，所述方法包括以下步骤：
步骤1210、选取用于主放大器和辅放大器的晶体管。晶体管的选取可以考虑多方面的设计需求，例如功率、成本、尺寸等，可以参考上文对不同类型晶体管的描述，本文对此不作限定。在确定了用于放大器的晶体管的情况下，其最佳工作负载R opt也基本得以确定；步骤1220、确定所述多赫蒂放大器的目标回退功率范围，并根据所述目标回退功率范围、所述第一电感器的第一电感值、所述第二电感器的第二电感值、所述晶体管的漏极寄生电容、所述多赫蒂放大器的中心工作频率和最佳工作负载确定所述第一传输线的第一特性阻抗和第一电角度、以及所述第二传输线的第二特性阻抗和第二电角度；步骤1230，根据所述中心工作频率、所述第一传输线的第一特性阻抗、第一电角度、所述第二传输线的第二特性阻抗、第二电角度、所述最佳工作负 载、所述第一电感器的第一电感值、所述第二电感器的第二电感值和所述目标回退功率范围确定所述组合节点处的节点阻抗。
因此，本申请的实施例提出设计多赫蒂放大器的方法以期望的目标回退功率范围为出发点，并以简化多赫蒂放大器的输出网络的结构为目标，能够实现延展多赫蒂放大器的回退功率范围和简化多赫蒂放大器的电路结构的协调统一。换言之，利用本申请的实施例提出的设计多赫蒂放大器的方法，可以获得结构更加紧凑、电路结构得以简化的多赫蒂放大器，另外，该多赫蒂放大器还能够实现从低功率到高功率范围内的高效工作，具有更深的回退功率和更宽的工作带宽。
根据本申请的一些实施例，根据所述目标回退功率范围、所述第一电感器的第一电感值、所述第二电感器的第二电感值、所述晶体管的漏极寄生电容、所述多赫蒂放大器的中心工作频率和最佳工作负载确定所述第一传输线的第一特性阻抗和第一电角度、以及所述第二传输线的第二特性阻抗和第二电角度包括：通过以下公式分别计算所述第一传输线的第一特性阻抗Z Main和第一电角度θ Main、以及所述第二传输线的第二特性阻抗Z Aux和第二电角度θ Aux：
Figure PCTCN2021140419-appb-000022
Figure PCTCN2021140419-appb-000023
Figure PCTCN2021140419-appb-000024
Figure PCTCN2021140419-appb-000025
θ IN表示所述相位差，ω是所述多赫蒂放大器的中心工作频率，R opt是所述晶体管的最佳工作负载，L P1表示所述第一电感器的第一电感值，L P2表示所述第二电感器的第二电感值，C DS是晶体管的漏极寄生电容，α表示使得所述辅放大器开启工作的功率水平系数，x是常数。根据所述中心工作频率、所述第一传输线的第一特性阻抗、第一电角度、所述第二传输线的第二特性阻抗、第二电角度、所述最佳工作负载、所述第一电感器的第一电感值、所述第二电感器的第二电感值和所述目标回退功率范围确定所述组合节点处的节点阻抗包括通过如下公式确 定所述组合节点处的节点阻抗Zcombine：
Figure PCTCN2021140419-appb-000026
Figure PCTCN2021140419-appb-000027
其中所述目标回退功率范围为
Figure PCTCN2021140419-appb-000028
能够理解到的是，常数x、第一电感器的第一电感值、第二电感器的第二电感器值对于输出网络中的第一传输线和第二传输线的具体参数的设计的灵活度具有积极的现实意义。通过选取不同值的常数x，可以获得第一传输线的第一特性阻抗Z Main、第一电角度θ Main、所述第二传输线的第二特性阻抗Z Aux和第二电角度θ Aux的不同的值。图13A和图13B分别示意性示出了根据本申请的一些实施例的第一传输线和第二传输线的特性阻抗和电角度的取值示例图1310、1320。以设计案例“中心工作频率2GHz，最佳工作负载R opt＝60Ohm，回退功率范围＝9dB，L p1＝L p2＝0.3nH，晶体管的漏极寄生电容C DS＝1pF”为例，常数x的选择可以用来调整传输线的特性阻抗在可加工制作的范围内(30～100Ohm)，同时通过常数x可以调整传输线的电角度以实现较小的电路尺寸(即较小的电角度对应较小的传输线的尺寸)。
图13C示意性示出了根据本申请的一些实施例的第一传输线的第一特性阻抗和第一电感器的第一电感值的关系的示例图1330。以设计案例“中心工作频率2GHz，最佳工作负载R opt＝60Ohm，回退功率范围＝9dB，L p1＝L p2＝0.3nH，C DS＝1pF，x＝2.5”为例(其中R opt＝60Ohm对应于中小功率的功率放大器)，主路如果不包括本申请实施例所述的第一电感器，即使考虑到主放大器中晶体管自身的寄生电感(＜0.5pF)，则第一传输线的第一特性阻抗Z main将远大于100Ohm，这在第一传输线的具体实施中难以实现。如图13C所示，通过增大L p1，可以降低Z main，从而有助于实现满足设计需求的传输线的特性阻抗。图13D示意性示出了根据本申请的一些实施例的第二传输线的第二特性阻抗和第二电感器的第二电感值的关系的示例图1340。以设计案例“中心工作频率2GHz，最佳工作负载R opt＝10Ohm，回退功率范围＝9dB， L p1＝L p2＝0.3nH，C DS＝1pF，x＝2.5”为例(其中R opt＝10Ohm对应于大功率的功放设计场景)，在辅路如果不设置第二电感器，即使考虑辅放大器晶体管自身的寄生电感(＜0.5pF)，则Z Aux将小于10Ohm，这在实际的第二传输线设计和制作中同样难以实现。如图13D所示，通过增大L p2，可以增加Z Aux，从而有助于实现满足设计需求的第二传输线的特性阻抗。
因此，利用常数x、第一电感器和第二电感器，可以为输出网络中第一传输线和第二传输线的设计提供较大的自由度，同时，也能够为设计出便于第一传输线、第二传输线的加工制作提供保证。
将理解的是，尽管第一、第二、第三等术语在本文中可以用来描述各种设备、元件、部件或部分，但是这些设备、元件、部件或部分不应当由这些术语限制。这些术语仅用来将一个设备、元件、部件或部分与另一个设备、元件、部件或部分相区分。本文提到的“连接”包括“直接连接”或“间接连接”。
尽管已经结合一些实施例描述了本申请，但是其不旨在被限于在本文中所阐述的特定形式。相反，本申请的范围仅由所附权利要求来限制。附加地，尽管单独的特征可以被包括在不同的权利要求中，但是这些可以可能地被有利地组合，并且包括在不同权利要求中不暗示特征的组合不是可行的和/或有利的。特征在权利要求中的次序不暗示特征必须以其工作的任何特定次序。此外，在权利要求中，词“包括”不排除其他元件，并且术语“一”或“一个”不排除多个。权利要求中的附图标记仅作为明确的例子被提供，不应该被解释为以任何方式限制权利要求的范围。

Claims (18)

  1. 一种用于多赫蒂放大器的输出网络，所述多赫蒂放大器包括主放大器和辅放大器，所述输出网络包括：与所述主放大器对应的第一子输出网络、与所述辅放大器对应的第二子输出网络、组合节点和合路匹配网络，
    其中所述第一子输出网络的输出端和所述第二子输出网络的输出端均连接至所述组合节点，所述合路匹配网络被配置成将所述组合节点连接至所述多赫蒂放大器的射频输出端，
    其中所述第一子输出网络包括由第一电感器和第一传输线串联组成的第一串联电路，所述第二子输出网络包括由第二电感器和第二传输线组成的第二串联电路，
    其中所述第一串联电路连接在所述主放大器的输出端和所述组合节点之间，所述第二串联电路连接在所述辅放大器的输出端和所述组合节点之间，所述第一串联电路和所述第二串联电路被配置成使得所述组合节点处的节点阻抗匹配至所述主放大器和所述辅放大器的目标负载阻抗。
  2. 根据权利要求1所述的输出网络，其中所述第一传输线和所述第二传输线中的至少一个仅包括微带线。
  3. 根据权利要求1所述的输出网络，其中所述合路匹配网络包括第三传输线、第四传输线和第一电容器，所述第三传输线连接在所述组合节点和所述合路匹配网络的输出端之间，所述第四传输线连接在所述合路匹配网络的输出端和直流电压端之间，所述第一电容器的一端连接至所述直流电压端，所述第一电容器的另一端接地，其中所述直流电压端被配置成经由所述第四传输线、所述第三传输线、所述第一子输出网络和所述第二子输出网络向所述主放大器和辅放大器提供直流偏置电压。
  4. 根据权利要求1所述的输出网络，其中所述合路匹配网络包括第五传输线、第六传输线、第七传输线和第二电容器，所述第五传输线连接在所述组合节点和所述合路匹配网络的输出端之间，所述第六传输线连接在所述组合节点和直流电压端之间，所述第七传输线的一端连接至所述合路匹配网络的输出端，所述第七传输线的另一端浮接， 所述第二电容器的一端连接至直流电压端，所述第二电容器的另一端接地，其中所述直流电压端被配置成经由所述第六传输线、所述第一子输出网络和所述第二子输出网络向所述主放大器和辅放大器提供直流偏置电压。
  5. 根据权利要求1所述的输出网络，其中所述合路匹配网络包括第三电感器、第四电感器和第三电容器，其中所述第三电感器和所述第三电容器串联连接在直流电压端和接地端之间，所述组合节点连接至所述第三电感器和所述第三电容器之间的连接点，所述第四电感器连接在所述第三电感器和所述第三电容器之间的所述连接点与所述合路匹配网络的输出端之间，其中所述直流电压端被配置成经由所述第三电感器、所述第一子输出网络和所述第二子输出网络向所述主放大器和辅放大器提供直流偏置电压。
  6. 根据权利要求3至5中任一项所述的输出网络，其中所述合路匹配网络还包括输出电容器，所述输出电容器连接在所述合路匹配网络的输出端和所述多赫蒂放大器的射频输出端之间并且被配置成阻断所述直流电压端的直流信号传输到所述多赫蒂放大器的射频输出端。
  7. 根据权利要求1所述的输出网络，其中所述合路匹配网络被配置成使得所述节点阻抗呈现复数阻抗。
  8. 根据权利要求1所述的输出网络，其中所述第一电感器和所述第二电感器中的至少一个包括多条键合线。
  9. 根据权利要求1所述的输出网络，其中所述第一电感器和所述第二电感器中的至少一个包括微带线。
  10. 根据权利要求1所述的输出网络，其中所述第一传输线和所述第二传输线中的至少一个包括带状线、共面波导或基片集成波导。
  11. 一种多赫蒂放大器，包括：
    主放大器；
    辅放大器；以及
    根据权利要求1-10中任一项所述的输出网络，
    其中所述输出网络被配置成接收所述主放大器的输出的第一放大信号和所述辅放大器输出的第二放大信号，使得所述第一放大信号和所述第二放大信号在所述组合节点处组合以提供给所述多赫蒂放大器的射频输出端。
  12. 根据权利要求11所述的多赫蒂放大器，其中所述多赫蒂放大器包括向所述主放大器提供载波信号以生成所述第一放大信号的载波信号输入路径、以及向所述辅放大器提供峰值信号以生成所述第二放大信号的峰值信号输入路径，
    其中所述多赫蒂放大器包括位于所述载波信号输入路径和所述峰值信号输入路径中的至少一个的相位延迟元件，所述相位延迟元件被配置成在提供给所述主放大器的载波信号和提供给所述辅放大器的峰值信号之间形成相位差，所述相位差小于90度。
  13. 根据权利要求12所述的多赫蒂放大器，其中所述主放大器和所述辅放大器均包括晶体管，第一传输线的第一特性阻抗Z Main、第一电角度θ Main、所述第二传输线的第二特性阻抗Z Aux和第二电角度θ Aux分别为：
    Figure PCTCN2021140419-appb-100001
    Figure PCTCN2021140419-appb-100002
    Figure PCTCN2021140419-appb-100003
    Figure PCTCN2021140419-appb-100004
    其中θ IN表示所述相位差，ω是所述多赫蒂放大器的中心工作频率，R opt是所述晶体管的最佳工作负载，L P1表示所述第一电感器的第一电感值，L P2表示所述第二电感器的第二电感值，C DS是晶体管的漏极寄生电容，α表示使得所述辅放大器开启工作的功率水平，x是常数。
  14. 根据权利要求13所述的多赫蒂放大器，其中所述相位差θ IN为
    Figure PCTCN2021140419-appb-100005
    其中α大于0小于0.5，其中1≤x≤10。
  15. 根据权利要求14所述的多赫蒂放大器，其中所述组合节点处的节点阻抗Z combine满足以下公式：
    Figure PCTCN2021140419-appb-100006
    Figure PCTCN2021140419-appb-100007
  16. 根据权利要求11所述的多赫蒂放大器，其中所述多赫蒂放大器包括多个所述辅放大器，所述输出网络包括分别与所述多个辅放大器一一对应的多个所述第二子输出网络，所述第一子输出网络被配置成接收所述主放大器的输出的第一放大信号，每个第二子输出网络被配置成接收所述多个辅放大器中相应的辅放大器输出的第二放大信号，使得所述第一放大信号和每个辅放大器输出的第二放大信号在所述组合节点处进行组合以提供给所述多赫蒂放大器的射频输出端。
  17. 一种设计多赫蒂放大器的方法，所述多赫蒂放大器包括主放大器、至少一个辅放大器、以及如权利要求1所述的输出网络，其中所述方法包括：
    选取用于所述主放大器和辅放大器的晶体管；
    确定所述多赫蒂放大器的目标回退功率范围，并根据所述目标回退功率范围、所述第一电感器的第一电感值、所述第二电感器的第二电感值、所述晶体管的漏极寄生电容、所述多赫蒂放大器的中心工作频率和最佳工作负载确定所述第一传输线的第一特性阻抗和第一电角度、以及所述第二传输线的第二特性阻抗和第二电角度；以及
    根据所述中心工作频率、所述第一传输线的第一特性阻抗、第一电角度、所述第二传输线的第二特性阻抗、第二电角度、所述最佳工作负载、所述第一电感器的第一电感值、所述第二电感器的第二电感值和所述目标回退功率范围确定所述组合节点处的节点阻抗。
  18. 根据权利要求17所述的方法，其中根据所述目标回退功率范围、所述第一电感器的第一电感值、所述第二电感器的第二电感值、所述晶体管的漏极寄生电容、所述多赫蒂放大器的中心工作频率和最佳工作负载确定所述第一传输线的第一特性阻抗和第一电角度、以及所述第二传输线的第二特性阻抗和第二电角度包括：通过以下公式分别计算所述第一传输线的第一特性阻抗Z Main和第一电角度θ Main、以及所述第二传输线的第二特性阻抗Z Aux和第二电角度θ Aux：
    Figure PCTCN2021140419-appb-100008
    Figure PCTCN2021140419-appb-100009
    Figure PCTCN2021140419-appb-100010
    Figure PCTCN2021140419-appb-100011
    其中θ IN表示所述相位差，ω是所述多赫蒂放大器的中心工作频率，R opt是所述晶体管的最佳工作负载，L P1表示所述第一电感器的第一电感值，L P2表示所述第二电感器的第二电感值，C DS是晶体管的漏极寄生电容，α表示使得所述辅放大器开启工作的功率水平系数，x是常数，
    其中根据所述中心工作频率、所述第一传输线的第一特性阻抗、第一电角度、所述第二传输线的第二特性阻抗、第二电角度、所述最佳工作负载、所述第一电感器的第一电感值、所述第二电感器的第二电感值和所述目标回退功率范围确定所述组合节点处的节点阻抗包括通过如下公式确定所述组合节点处的节点阻抗Z combine：
    Figure PCTCN2021140419-appb-100012
    Figure PCTCN2021140419-appb-100013
    其中所述目标回退功率范围为
    Figure PCTCN2021140419-appb-100014
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