WO2023109927A1 - 像素单元及图像传感器 - Google Patents

像素单元及图像传感器 Download PDF

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Publication number
WO2023109927A1
WO2023109927A1 PCT/CN2022/139440 CN2022139440W WO2023109927A1 WO 2023109927 A1 WO2023109927 A1 WO 2023109927A1 CN 2022139440 W CN2022139440 W CN 2022139440W WO 2023109927 A1 WO2023109927 A1 WO 2023109927A1
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Prior art keywords
transistor
transfer
photodiode
capacitor
pixel unit
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PCT/CN2022/139440
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English (en)
French (fr)
Inventor
曾夕
温建新
周阳
王玮
Original Assignee
上海集成电路装备材料产业创新中心有限公司
上海集成电路研发中心有限公司
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Publication of WO2023109927A1 publication Critical patent/WO2023109927A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/148—Charge coupled imagers
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/50—Control of the SSIS exposure
    • H04N25/57—Control of the dynamic range
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/50—Control of the SSIS exposure
    • H04N25/57—Control of the dynamic range
    • H04N25/59—Control of the dynamic range by controlling the amount of charge storable in the pixel, e.g. modification of the charge conversion ratio of the floating node capacitance
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
    • H04N25/77—Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components

Definitions

  • the present invention relates to the technical field of image sensors, in particular to a pixel unit and an image sensor.
  • CMOS image sensors have the advantages of high integration and low power consumption, and are widely used in electronics, monitoring, navigation, transportation and other fields.
  • the requirements for the performance of CMOS image sensors are also getting higher and higher.
  • CMOS image sensors are required to collect as true and complete image information as possible in various driving environments and scenarios.
  • the dynamic range of the CMOS image sensor is required to be large enough.
  • intelligent driving needs to adjust the driving mode according to the electronic devices in the driving environment, such as traffic lights, etc., and such electronic devices are usually LED lights, and the signals of LED lights are periodic modulation signals.
  • the automotive CMOS image sensor must be able to suppress LED flicker.
  • the charge of the second photodiode diffuses to the first photodiode, thereby affecting the signal of the first photodiode and affecting the image quality.
  • the object of the present invention is to provide a pixel unit and an image sensor, which can avoid the influence of the second photodiode on the first photodiode, thereby improving the image quality.
  • the pixel unit of the present invention is characterized in that it includes:
  • a first transfer unit configured to transfer the charge of the first photodiode to the first node
  • the second transfer unit is configured to transfer the charge within the saturation range of the second photodiode to the first node, and transfer the charge outside the saturation range of the second photodiode to the second node or a fixed potential;
  • a conversion gain adjustment transistor for controlling conversion gain to the second photodiode by opening or closing a path between the first node and the second node;
  • a reset transistor connected to the first transmission unit, for resetting the pixel unit
  • an output unit configured to amplify and output the voltage at the first node.
  • the beneficial effect of the pixel unit is that: the second transfer unit is used to transfer the charges within the saturation range of the second photodiode to the first node, and transfer the charges outside the saturation range of the second photodiode to the first node.
  • Two nodes or a fixed potential thereby avoiding adverse effects caused by charge diffusion of the second photodiode to the first photodiode, improving image quality, and realizing high dynamic range while suppressing LED flicker.
  • the first transmission unit includes a first transmission transistor, a first terminal of the first transmission transistor is connected to the cathode of the first photodiode, an anode of the first photodiode is grounded, and the first terminal of the first transmission transistor is connected to the cathode of the first photodiode.
  • a second end of a transfer transistor is connected to the first end of the reset transistor, and the second end of the reset transistor is connected to a power supply voltage.
  • the second transmission unit includes a second transmission transistor and a third transmission transistor, the first terminal of the second transmission transistor and the first terminal of the third transmission transistor are both connected to the second photodiode
  • the cathode of the second photodiode is connected to the ground
  • the second end of the second transfer transistor is connected to the output unit
  • the second end of the third transfer transistor unit is connected to the second node, or Connect to a fixed potential.
  • the first end of the conversion gain adjustment transistor is the second node
  • the second end of the conversion gain adjustment transistor is the first node
  • the first end of the conversion gain adjustment transistor is connected to the connected to the second end of the first transfer transistor
  • the second end of the conversion gain adjustment transistor is connected to the second end of the second transfer transistor.
  • the first end of the conversion gain adjustment transistor is the second node
  • the second end of the conversion gain adjustment transistor is the first node
  • the second end of the conversion gain adjustment transistor is connected to the The second end of the first transfer transistor is connected to the second end of the second transfer transistor, and when the second end of the third transfer transistor unit is connected to a fixed potential, the first end of the conversion gain adjustment transistor is suspended.
  • the first transmission unit further includes a fourth transmission transistor, the first terminal of the fourth transmission transistor is connected to the cathode of the first photodiode, the anode of the first photodiode is grounded, and the The second end of the fourth pass transistor is connected to the first end of the first pass transistor.
  • the beneficial effect is that it can prevent the charge of the second photodiode from diffusing to the first photodiode, thereby avoiding the influence of large pixels on small pixels and improving image quality.
  • the pixel unit further includes a first capacitor, one end of the first capacitor is connected to the first end of the conversion gain adjustment transistor, and the other end of the first capacitor is connected to a fixed potential or a timing signal.
  • the beneficial effect is that the low conversion gain of the second photodiode can be reduced, and the dynamic range of the pixel unit can be expanded.
  • the pixel unit further includes a second capacitor, one end of the second capacitor is connected to the second end of the fourth transfer transistor, and the other end of the second capacitor is connected to another fixed potential or timing signal .
  • the beneficial effect is that the full well charge of the first photodiode can be enlarged, thereby expanding the dynamic range of the pixel unit.
  • the pixel unit further includes a first capacitor and a second capacitor, one end of the first capacitor is connected to the first end of the conversion gain adjustment transistor, and the other end of the first capacitor is connected to a fixed potential or Timing signal, one end of the second capacitor is connected to the second end of the fourth transfer transistor, the other end of the second capacitor is connected to another fixed potential or timing signal, and the capacitance of the first capacitor is less than The capacitance of the second capacitor.
  • the beneficial effect is that the low conversion gain of the second photodiode can be reduced, and the full well charge of the first photodiode can be enlarged, thereby expanding the dynamic range of the pixel unit.
  • the output unit includes an amplifying transistor and a selection transistor, the first end of the amplifying transistor is connected to a power supply voltage, the gate of the amplifying transistor is connected to the second end of the second transmission transistor, and the amplifying The second end of the transistor is connected to the first end of the selection transistor, and the second end of the selection transistor is used to output the voltage amplified by the amplification transistor.
  • the pixel unit further includes a driving circuit, the driving circuit is connected to the gate of the first transfer transistor, the gate of the second transfer transistor, the gate of the third transfer transistor, the A gate of the reset transistor is connected to a gate of the selection transistor to drive the first pass transistor, the second pass transistor, the third pass transistor, the reset transistor, and the select transistor.
  • the driving circuit is further connected to the gate of the fourth transfer transistor to drive the fourth transfer transistor.
  • the present invention also provides an image sensor, comprising a pixel array formed by at least one pixel unit.
  • the beneficial effect of the image sensor is that: a pixel array composed of at least one pixel unit is included, the pixel unit includes a second transfer unit, and the second transfer unit is used to transfer the charge within the saturation range of the second photodiode to The first node transmits the charge outside the saturation range of the second photodiode to the second node or a fixed potential, thereby preventing the charge of the second photodiode from diffusing to the first photodiode and causing adverse effects, Improve image quality and enable high dynamic range while suppressing LED flicker.
  • FIG. 1 is a circuit diagram of a pixel unit in a first embodiment of the present invention
  • FIG. 2 is a circuit diagram of a pixel unit in a second embodiment of the present invention.
  • FIG. 3 is a circuit diagram of a pixel unit in a third embodiment of the present invention.
  • FIG. 4 is a circuit diagram of a pixel unit in a fourth embodiment of the present invention.
  • FIG. 5 is a circuit diagram of a pixel unit in a fifth embodiment of the present invention.
  • FIG. 6 is a circuit diagram of a pixel unit in a sixth embodiment of the present invention.
  • FIG. 7 is a circuit diagram of a pixel unit in a seventh embodiment of the present invention.
  • FIG. 8 is a circuit diagram of a pixel unit in an eighth embodiment of the present invention.
  • FIG. 9 is a circuit diagram of a pixel unit in a ninth embodiment of the present invention.
  • FIG. 10 is a circuit diagram of a pixel unit in a tenth embodiment of the present invention.
  • FIG. 11 is a circuit diagram of a pixel unit in an eleventh embodiment of the present invention.
  • Fig. 12 is a circuit diagram of a pixel unit in a twelfth embodiment of the present invention.
  • FIG. 13 is a circuit diagram of a pixel unit in a thirteenth embodiment of the present invention.
  • FIG. 14 is a circuit diagram of a pixel unit in a fourteenth embodiment of the present invention.
  • Fig. 15 is a circuit diagram of a pixel unit in a fifteenth embodiment of the present invention.
  • Fig. 16 is a circuit diagram of a pixel unit in a sixteenth embodiment of the present invention.
  • Fig. 17 is a circuit diagram of a pixel unit in a seventeenth embodiment of the present invention.
  • Fig. 18 is a circuit diagram of a pixel unit in an eighteenth embodiment of the present invention.
  • FIG. 19 is a timing diagram of a pixel unit in some embodiments of the present invention.
  • Fig. 20 is a schematic diagram of charge transfer of a circuit in the prior art
  • Fig. 21 is a schematic diagram of charge transfer of circuits shown in Fig. 1, Fig. 2, Fig. 5, Fig. 8, Fig. 10, Fig. 11, Fig. 14 and Fig. 17 of the present invention;
  • FIG. 22 is a schematic diagram of charge transfer in the circuits shown in FIG. 3 , FIG. 4 , FIG. 6 , FIG. 7 , FIG. 9 , FIG. 12 , FIG. 13 , FIG. 15 , FIG. 16 and FIG. 18 of the present invention.
  • an embodiment of the present invention provides an image sensor, which includes a pixel array composed of at least one pixel unit.
  • the pixel unit includes a first photodiode, a second photodiode, a first transmission unit, a second transmission unit, a conversion gain adjustment transistor, a reset transistor and an output unit.
  • the sensitivity of the first photodiode is lower than a predetermined sensitivity; the sensitivity of the second photodiode is higher than the predetermined sensitivity; the first transfer unit is used to transfer the charge of the first photodiode transfer to the first node; the second transfer unit is used to transfer the charge within the saturation range of the second photodiode to the first node, and transfer the charge outside the saturation range of the second photodiode to the second node or a fixed potential; the conversion gain adjustment transistor is used to control the conversion gain to the second photodiode by opening or closing the path between the first node and the second node; the reset transistor connected to the first transmission unit, for resetting the pixel unit; the output unit is used for amplifying and outputting the voltage at the first node.
  • the saturation range mentioned here refers to the charge saturation range of the first node. Therefore, the second transfer unit transfers the charges within the charge saturation range of the first node in the second photodiode to the first node, and transfers the charges outside the charge saturation range of the first node in the second photodiode to Second node or fixed potential.
  • the fixed potential is greater than the ground potential and less than or equal to the power potential.
  • the first transfer unit includes a first transfer transistor, the first terminal of the first transfer transistor is connected to the cathode of the first photodiode, the anode of the first photodiode is grounded, and the The second end of the first transfer transistor is connected to the first end of the reset transistor, and the second end of the reset transistor is connected to a power supply voltage.
  • the second transmission unit includes a second transmission transistor and a third transmission transistor, the first terminal of the second transmission transistor and the first terminal of the third transmission transistor are both connected to the second photoelectric
  • the cathode of the diode is connected, the anode of the second photodiode is connected to the ground, the second end of the second transfer transistor is connected to the output unit, and the second end of the third transfer transistor unit is connected to the second node Or connect to a fixed potential.
  • the first end of the conversion gain adjustment transistor is the second node
  • the second end of the conversion gain adjustment transistor is the first node
  • the first end of the conversion gain adjustment transistor is connected to The second end of the first transfer transistor is connected
  • the second end of the conversion gain adjustment transistor is connected with the second end of the second transfer transistor.
  • the first end of the conversion gain adjustment transistor is the second node
  • the second end of the conversion gain adjustment transistor is the first node
  • the second end of the conversion gain adjustment transistor is connected to the second node.
  • the second end of the first transfer transistor is connected to the second end of the second transfer transistor, and when the second end of the third transfer transistor unit is connected to a fixed potential, the first end of the conversion gain adjustment transistor is suspended .
  • the first transfer unit further includes a fourth transfer transistor, the first end of the fourth transfer transistor is connected to the cathode of the first photodiode, the anode of the first photodiode is grounded, and the The second end of the fourth pass transistor is connected to the first end of the first pass transistor.
  • the output unit includes an amplifying transistor and a selection transistor, the first terminal of the amplifying transistor is connected to a power supply voltage, the gate of the amplifying transistor is connected to the second terminal of the second transmission transistor, and the The second end of the amplifying transistor is connected to the first end of the selection transistor, and the second end of the selection transistor is used to output the voltage amplified by the amplifying transistor.
  • the pixel unit further includes a driving circuit, the driving circuit is connected to the gate of the first transfer transistor, the gate of the second transfer transistor, the gate of the third transfer transistor, A gate of the reset transistor is connected to a gate of the selection transistor to drive the first transfer transistor, the second transfer transistor, the third transfer transistor, the reset transistor, and the selection transistor.
  • the driving circuit is further connected to the gate of the fourth transfer transistor to drive the fourth transfer transistor.
  • the pixel unit further includes a first capacitor, one end of the first capacitor is connected to the first end of the conversion gain adjustment transistor, and the other end of the first capacitor is connected to a fixed potential or a timing signal .
  • the pixel unit further includes a second capacitor, one end of the second capacitor is connected to the second end of the fourth transfer transistor, and the other end of the second capacitor is connected to another fixed potential or timing signals.
  • the pixel unit further includes a first capacitor and a second capacitor, one end of the first capacitor is connected to the first end of the conversion gain adjustment transistor, and the other end of the first capacitor connected to a fixed potential or a timing signal, one end of the second capacitor is connected to the second end of the fourth transfer transistor, the other end of the second capacitor is connected to another fixed potential or a timing signal, and the first capacitor The capacitance of is smaller than the capacitance of the second capacitor.
  • the first terminal of any transistor is the source or the drain
  • the second terminal of any transistor is the source or the drain
  • the first terminal and the second terminal of the same transistor cannot both be the source or the drain pole.
  • the selection transistor is an NMOS transistor or a PMOS transistor, and it only needs to be able to realize corresponding functions.
  • FIG. 1 is a circuit diagram of a pixel unit in the first embodiment of the present invention.
  • the pixel unit 100 includes a first photodiode 101 , a second photodiode 102 , a first transmission unit 103 , a second transmission unit 104 , a conversion gain adjustment transistor 105 , an output unit 106 and a reset transistor 107 .
  • the sensitivity of the first photodiode 101 is lower than a predetermined sensitivity
  • the sensitivity of the second photodiode 102 is higher than a predetermined sensitivity.
  • the first transfer unit 103 includes a first transfer transistor 1031
  • the second transfer unit 104 includes a second transfer transistor 1041 and a third transfer transistor 1042
  • the output unit 106 includes an amplification transistor 1061 and a selection transistor 1062
  • the The first transfer transistor 1031, the second transfer transistor 1041, the third transfer transistor 1042, the conversion gain adjustment transistor 105, the reset transistor 107, the amplification transistor 1061 and the selection transistor 1062 are all NMOS tube or PMOS tube.
  • the anode of the first photodiode 101 and the anode of the second photodiode 102 are grounded, the cathode of the first photodiode 101 is connected to the source of the first transfer transistor 1031, the The drain of the first transmission transistor 1031 is connected to the second node 109 , and the gate of the first transmission transistor 1031 is used for receiving the first transmission control signal TXS1 .
  • the cathode of the second photodiode 102 is connected to the source of the second transfer transistor 1041 and the source of the third transfer transistor 1042, and the drain of the second transfer transistor 1041 is connected to the source of the second transfer transistor 1041.
  • the first node 108 is connected, the gate of the second transmission transistor 1041 is used to receive the second transmission control signal TXL1, the drain of the third transmission transistor 1042 is connected to the second node 109, and the third transmission transistor 1042 is connected to the second node 109.
  • the gate of 1042 is used for receiving the third transmission control signal TXL2.
  • the drain of the reset transistor 107 is connected to a power source, the source of the reset transistor 107 is connected to the second node 109 , and the gate of the reset transistor 107 is used to receive a reset control signal RX.
  • the drain of the conversion gain adjustment transistor 105 is connected to the second node 109, the source of the conversion gain adjustment transistor 105 is connected to the first node 108, the conversion gain adjustment transistor 105
  • the gate is used for receiving the conversion gain adjustment control signal LCG.
  • the drain of the amplifier transistor 1061 is connected to the power supply, the source of the amplifier transistor 1061 is connected to the drain of the selection transistor 1062, and the gate of the amplifier transistor 1061 is connected to the first node 108 , the source of the selection transistor 1062 is used as the output terminal of the output unit 106, and the gate of the selection transistor 1062 is used to receive the selection control signal SEL.
  • FIG. 2 is a circuit diagram of a pixel unit in a second embodiment of the present invention.
  • the first transfer unit 103 further includes a fourth transfer transistor 1032, the cathode of the first photodiode 101 is connected to the source of the fourth transfer transistor 1032, and the fourth The drain of the transmission transistor 1032 is connected to the source of the first transmission transistor 1031 , and the gate of the fourth transmission transistor 1032 is used to receive the fourth transmission control signal TXS2 .
  • FIG. 3 is a circuit diagram of a pixel unit in a third embodiment of the present invention.
  • the difference between Fig. 3 and Fig. 1 is that: the source of the third transfer transistor 1042 is connected to the working voltage.
  • FIG. 4 is a circuit diagram of a pixel unit in a fourth embodiment of the present invention. The difference between FIG. 4 and FIG. 2 is that: the source of the third transfer transistor 1042 is connected to the working voltage.
  • FIG. 5 is a circuit diagram of a pixel unit in a fifth embodiment of the present invention.
  • the difference between FIG. 5 and FIG. 1 is that: the pixel unit 100 further includes a first capacitor 1091, one end of the first capacitor 1091 is connected to the second node 109, and the other end of the first capacitor 1091 is connected to a fixed potential or timing signals.
  • FIG. 6 is a circuit diagram of a pixel unit in a sixth embodiment of the present invention. The difference between FIG. 6 and FIG. 3 is that: the pixel unit 100 further includes a first capacitor 1091, one end of the first capacitor 1091 is connected to the second node 109, and the other end of the first capacitor 1091 is connected to a fixed potential or timing signals.
  • FIG. 7 is a circuit diagram of a pixel unit in a seventh embodiment of the present invention.
  • the difference between FIG. 7 and FIG. 4 is that: the pixel unit 100 further includes a first capacitor 1091, one end of the first capacitor 1091 is connected to the second node 109, and the other end of the first capacitor 1091 is connected to a fixed potential or timing signals.
  • FIG. 8 is a circuit diagram of a pixel unit in an eighth embodiment of the present invention.
  • the pixel unit 100 further includes a first capacitor 1091 and a second capacitor 10321, one end of the first capacitor 1091 is connected to the second node 109, and the first capacitor 1091 The other end is connected to a fixed potential or a timing signal, one end of the second capacitor 10321 is connected to the drain of the fourth transmission transistor 1032 , and the other end of the second capacitor 10321 is connected to another fixed potential or a timing signal.
  • FIG. 9 is a circuit diagram of a pixel unit in a ninth embodiment of the present invention.
  • the pixel unit 100 further includes a first capacitor 1091 and a second capacitor 10321, one end of the first capacitor 1091 is connected to the second node 109, and the first capacitor 1091 The other end is connected to a fixed potential or a timing signal, one end of the second capacitor 10321 is connected to the drain of the fourth transmission transistor 1032 , and the other end of the second capacitor 10321 is connected to another fixed potential or a timing signal.
  • Fig. 10 is a circuit diagram of a pixel unit in a tenth embodiment of the present invention.
  • the pixel unit 100 includes a first photodiode 101, a second photodiode 102, a first transmission unit 103, a second transmission unit 104, a conversion gain adjustment transistor 105, an output unit 106 and a reset transistor 107
  • the The first transfer unit 103 includes a first transfer transistor 1031
  • the second transfer unit 104 includes a second transfer transistor 1041 and a third transfer transistor 1042
  • the output unit 106 includes an amplification transistor 1061 and a selection transistor 1062
  • the first The transfer transistor 1031, the second transfer transistor 1041, the third transfer transistor 1042, the conversion gain adjustment transistor 105, the reset transistor 107, the amplification transistor 1061 and the selection transistor 1062 are all NMOS transistors or PMOS tube.
  • the anode of the first photodiode 101 and the anode of the second photodiode 102 are grounded, the cathode of the first photodiode 101 is connected to the source of the first transfer transistor 1031, the The drain of the first transmission transistor 1031 is connected to the first node 108 , and the gate of the first transmission transistor 1031 is used for receiving the first transmission control signal TXS1 .
  • the cathode of the second photodiode 102 is connected to the source of the second transfer transistor 1041 and the source of the third transfer transistor 1042, and the drain of the second transfer transistor 1041 is connected to the source of the second transfer transistor 1041.
  • the first node 108 is connected, the gate of the second transmission transistor 1041 is used to receive the second transmission control signal TXL1, the drain of the third transmission transistor 1042 is connected to the second node 109, the third transmission The gate of the transistor 1042 is used for receiving the third transmission control signal TXL2.
  • the drain of the reset transistor 107 is connected to a power supply, the source of the reset transistor 107 is connected to the first node 108 , and the gate of the reset transistor 107 is used to receive a reset control signal RX.
  • the drain of the conversion gain adjustment transistor 105 is connected to the first node 108, the source of the conversion gain adjustment transistor 105 is connected to the second node 109, and the conversion gain adjustment transistor 105
  • the gate is used for receiving the conversion gain adjustment control signal LCG.
  • the drain of the amplification transistor 1061 is connected to a power supply, the source of the amplification transistor 1061 is connected to the drain of the selection transistor 1062, and the gate of the amplification transistor 1061 is connected to the first node 108, The source of the selection transistor 1062 is used as the output terminal of the output unit 106 , and the gate of the selection transistor 1062 is used to receive the selection control signal SEL.
  • Fig. 11 is a circuit diagram of a pixel unit in an eleventh embodiment of the present invention.
  • the first transfer unit 103 further includes a fourth transfer transistor 1032, the cathode of the first photodiode 101 is connected to the source of the fourth transfer transistor 1032, and the fourth The drain of the transmission transistor 1032 is connected to the source of the first transmission transistor 1031 , and the gate of the fourth transmission transistor 1032 is used to receive the fourth transmission control signal TXS2 .
  • Fig. 12 is a circuit diagram of a pixel unit in a twelfth embodiment of the present invention. The difference between FIG. 12 and FIG. 10 is that: the source of the third transfer transistor 1042 is connected to the working voltage, and the source of the conversion gain adjustment transistor 105 is suspended.
  • FIG. 13 is a circuit diagram of a pixel unit in a thirteenth embodiment of the present invention. The difference between FIG. 13 and FIG. 11 is that: the source of the third transfer transistor 1042 is connected to the working voltage, and the source of the conversion gain adjustment transistor 105 is suspended.
  • FIG. 14 is a circuit diagram of a pixel unit in a fourteenth embodiment of the present invention.
  • the pixel unit 100 further includes a first capacitor 1091, one end of the first capacitor 1091 is connected to the second node 109, and the other end of the first capacitor 1091 is connected to a fixed potential or timing signals.
  • Fig. 15 is a circuit diagram of a pixel unit in a fifteenth embodiment of the present invention. The difference between FIG. 15 and FIG. 12 is that: the pixel unit 100 further includes a first capacitor 1091, one end of the first capacitor 1091 is connected to the second node 109, and the other end of the first capacitor 1091 is connected to a fixed potential or timing signals.
  • Fig. 16 is a circuit diagram of a pixel unit in a sixteenth embodiment of the present invention. The difference between FIG. 16 and FIG. 13 is that the pixel unit 100 further includes a first capacitor 1091, one end of the first capacitor 1091 is connected to the second node 109, and the other end of the first capacitor 1091 is connected to a fixed potential or timing signals.
  • Fig. 17 is a circuit diagram of a pixel unit in a seventeenth embodiment of the present invention.
  • the pixel unit 100 further includes a first capacitor 1091 and a second capacitor 10321, one end of the first capacitor 1091 is connected to the second node 109, and the first capacitor 1091 The other end is connected to a fixed potential or a timing signal, one end of the second capacitor 10321 is connected to the drain of the fourth transmission transistor 1032 , and the other end of the second capacitor 10321 is connected to another fixed potential or a timing signal.
  • Fig. 18 is a circuit diagram of a pixel unit in an eighteenth embodiment of the present invention. The difference between FIG. 18 and FIG. 13 is that: the pixel unit 100 further includes a first capacitor 1091 and a second capacitor 10321, one end of the first capacitor 1091 is connected to the second node 109, and the first capacitor 1091 The other end is connected to a fixed potential or a timing signal, one end of the second capacitor 10321 is connected to the drain of the fourth transmission transistor 1032 , and the other end of the second capacitor 10321 is connected to another fixed potential or a timing signal.
  • Fig. 19 is a timing diagram of a pixel unit in some embodiments of the present invention.
  • the driving method of the pixel unit comprises the following steps:
  • Step 1 Referring to Figure 2 and Figure 19, the reset control signal RX, the first transmission control signal TXS1, the second transmission control signal TXL1, the third transmission control signal TXL2, the fourth transmission control Both the signal TXS2 and the conversion gain adjustment control signal LCG are at high potential to reset the pixel unit signal 100 .
  • Step 2 Referring to FIG. 2 and FIG. 19 , the first transmission control signal TXS1 and the fourth transmission control signal TXS2 both change from high potential to low potential, and the first photodiode 101 starts to expose.
  • Step 3 Referring to FIG. 2 and FIG. 19, both the second transmission control signal TXL1 and the third transmission control signal TXL2 are changed from high potential to low potential, and the second transmission transistor 1041 and the third transmission transistor 1042 are all turned off, and the second photodiode 102 starts to expose.
  • Step 4 Referring to FIG. 2 and FIG. 19, the reset control signal RX changes from a high potential to a low potential, and the selection control signal SEL changes from a low level to a high potential to output the low level of the second photodiode 102.
  • Step 5 Referring to FIG. 2 and FIG. 19, the conversion gain adjustment control signal LCG changes from a high potential to a low potential, and the selection control signal SEL changes from a low potential to a high potential to output the output of the second photodiode 102.
  • the high-gain reset signal Vrst2 and then the selection control signal SEL changes from a high potential to a low potential.
  • Step 6 Referring to FIG. 2 and FIG. 19, the second transmission control signal TXL1 changes from a low potential to a high potential for a period of time and then changes from a high potential to a low potential, and then the selection control signal SEL changes from a low potential to a high potential , to output the high-gain pixel signal Vsig2 of the second photodiode 102, and then the selection control signal SEL changes from a high potential to a low potential.
  • Step 7 Referring to FIG. 2 and FIG. 19, the conversion gain adjustment control signal LCG changes from a low potential to a high potential, and then the second transmission control signal TXL1 changes from a low potential to a high potential and then changes from a high potential to a high potential after a period of time. low potential, and then the selection control signal SEL changes from a low potential to a high potential to output the low-gain pixel signal Vsigl of the second photodiode 102, and then the selection control signal SEL changes from a high potential to a low potential .
  • Step 8 Referring to FIG. 2 and FIG. 19, the reset control signal RX changes from a low potential to a high potential, and the third transmission control signal TXL2 changes from a low potential to a high potential, so as to connect the first node 108 and the The second node 109 is reset, and then the reset control signal RX changes from high potential to low potential, the third transmission control signal TXL2 changes from high potential to low potential, and the selection control signal SEL changes from low potential to high potential to output the reset signal Vrst3 of the first photodiode 102, and then the selection control signal SEL changes from a high potential to a low potential.
  • Step 9 Referring to FIG. 2 and FIG. 19, the first transmission control signal TXS1 changes from a low potential to a high potential, and at the same time, the fourth transmission control signal TXS2 changes from a low potential to a high potential and then to a low potential, the The selection control signal SEL changes from a low potential to a high potential to output the pixel signal Vsig3 of the first photodiode 102 , and then the selection control signal SEL changes from a high potential to a low potential.
  • Step ten Referring to Figure 2 and Figure 19, the reset control signal RX, the first transmission control signal TXS1, the second transmission control signal TXL1, the third transmission control signal TXL2, the fourth transmission control signal Both the signal TXS2 and the conversion gain adjustment control signal LCG are at high potential, and the pixel unit 100 is reset to prepare for the next exposure.
  • FIG. 20 is a schematic diagram of charge transfer in a circuit in the prior art. Referring to FIG. 20 , the charges 1021 outside the saturation range of the high-sensitivity photodiode LP in the prior art will overflow into the low-sensitivity photodiode SP, thereby affecting the low-sensitivity photodiode SP.
  • FIG. 21 is a schematic diagram of charge transfer in the circuits shown in FIG. 1 , FIG. 2 , FIG. 5 , FIG. 8 , FIG. 10 , FIG. 11 , FIG. 14 and FIG. 17 of the present invention. 21, the charge 1021 outside the saturation range of the second photodiode 102 can be released to the second node 109 through the third transfer transistor 1042, thereby avoiding the saturation range of the second photodiode 102 External charges overflow to the first photodiode 101 and cause adverse effects.
  • FIG. 22 is a schematic diagram of charge transfer in the circuits shown in FIG. 3 , FIG. 4 , FIG. 6 , FIG. 7 , FIG. 9 , FIG. 12 , FIG. 13 , FIG. 15 , FIG. 16 and FIG. 18 of the present invention.
  • the charge 1021 outside the saturation range of the second photodiode 102 can be released to the power supply VP through the third transfer transistor 1042, thereby avoiding the charge 1021 outside the saturation range of the second photodiode 102 overflow to the first photodiode 101 and cause adverse effects.

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Abstract

本发明提供一种像素单元及图像传感器，所述像素单元包括第一光电二极管、第二光电二极管、第一传输单元、第二传输单元、转换增益调节晶体管、复位晶体管、输出单元，第一传输单元，用于将所述第一光电二极管的电荷传输到第一节点，第二传输单元用于将所述第二光电二极管的饱和范围内的电荷传输到第一节点，并将所述第二光电二极管的饱和范围外的电荷传输到所述第二节点或电源，由此避免所述第二光电二极管的电荷向所述第一光电二极管扩散而造成不良影响，提高图像质量。

Description

像素单元及图像传感器
交叉引用
本申请要求2021年12月17日提交的申请号为202111553669.X的中国专利申请的优先权。上述申请的内容以引用方式被包含于此。
技术领域
本发明涉及图像传感器技术领域，尤其涉及一种像素单元及图像传感器。
技术背景
CMOS图像传感器具有高集成度及低功耗等优点，在电子、监控、导航、交通等领域的应用越来越广泛。但随着技术不断发展，对CMOS图像传感器的性能的要求也越来越高。
作为智能驾驶的信息采集来源，车载CMOS图像传感器在各种驾驶环境和场景下均要求能采集到尽可能真实完整的图像信息。为了实现隧道和夜间图像信号的捕捉，要求CMOS图像传感器的动态范围足够大。与此同时，智能驾驶需要根据驾驶环境中的电子设备比如交通信号灯等调整驾驶模式，而这样的电子设备通常是LED灯，LED灯的信号为周期调制信号，为了采集到完整的电子交通信号，要求车载CMOS图像传感器必须能实现LED闪烁抑制。但现有技术中存在第二光电二极管的电荷向第一光电二极管扩散的技术问题，从而使得第一光电二极管的信号受到影响，影响图像质量。
因此，有必要提供一种新型的像素单元及图像传感器以解决现有技术中存在的上述问题。
发明概要
本本发明的目的在于提供一种像素单元及图像传感器，避免第二光电二 极管对第一光电二极管的影响，从而提高图像质量。
为实现上述目的，本发明的所述像素单元，其特征在于，包括：
第一光电二极管，灵敏度低于预定灵敏度；
第二光电二极管，灵敏度高于所述预定灵敏度；
第一传输单元，用于将所述第一光电二极管的电荷传输到第一节点；
第二传输单元，用于将所述第二光电二极管的饱和范围内的电荷传输到第一节点，将所述第二光电二极管的饱和范围外的电荷传输到第二节点或固定电位；
转换增益调节晶体管，用于通过打开或关断所述第一节点和所述第二节点之间的通路来控制对所述第二光电二极管的转换增益；
复位晶体管，与所述第一传输单元连接，用于将所述像素单元复位；以及
输出单元，用于放大所述第一节点处的电压并输出。
所述像素单元的有益效果在于：第二传输单元用于将所述第二光电二极管的饱和范围内的电荷传输到第一节点，将所述第二光电二极管的饱和范围外的电荷传输到第二节点或固定电位，由此避免所述第二光电二极管的电荷向所述第一光电二极管扩散而造成不良影响，提高图像质量，并且能够实现高动态范围的同时实现LED闪烁抑制。
可选地，所述第一传输单元包括第一传输晶体管，所述第一传输晶体管的第一端与所述第一光电二极管的阴极连接，所述第一光电二极管的阳极接地，所述第一传输晶体管的第二端与所述复位晶体管的第一端连接，所述复位晶体管的第二端接电源电压。其有益效果在于：能够避免所述第二光电二 极管的电荷向所述第一光电二极管扩散，从而避免大像素对小像素的影响，提高图像质量。
可选地，所述第二传输单元包括第二传输晶体管和第三传输晶体管，所述第二传输晶体管的第一端和所述第三传输晶体管的第一端均与所述第二光电二极管的阴极连接，所述第二光电二极管的阳极接地，所述第二传输晶体管的第二端与所述输出单元连接，所述第三传输晶体管单元的第二端与所述第二节点连接或接固定电位。其有益效果在于：能够避免所述第二光电二极管的电荷向所述第一光电二极管扩散，从而避免大像素对小像素的影响，提高图像质量。
可选地，所述转换增益调节晶体管的第一端为所述第二节点，所述转换增益调节晶体管的第二端为所述第一节点，所述转换增益调节晶体管的第一端与所述第一传输晶体管的第二端连接，所述转换增益调节晶体管的第二端与所述第二传输晶体管的第二端连接。
可选地，所述转换增益调节晶体管的第一端为所述第二节点，所述转换增益调节晶体管的第二端为所述第一节点，所述转换增益调节晶体管第二端与所述第一传输晶体管的第二端和所述第二传输晶体管的第二端连接，当所述第三传输晶体管单元的第二端接固定电位时，所述转换增益调节晶体管的第一端悬空。
可选地，所述第一传输单元还包括第四传输晶体管，所述第四传输晶体管的第一端与所述第一光电二极管的阴极连接，所述第一光电二极管的阳极接地，所述第四传输晶体管的第二端与所述第一传输晶体管的第一端连接。其有益效果在于：能够避免所述第二光电二极管的电荷向所述第一光电二极 管扩散，从而避免大像素对小像素的影响，提高图像质量。
可选地，所述像素单元还包括第一电容，所述第一电容的一端与所述转换增益调节晶体管的第一端连接，所述第一电容的另一端接固定电位或时序信号。其有益效果在于：能够降低所述第二光电二极管的低转化增益，扩大所述像素单元的动态范围。
可选地，所述像素单元还包括第二电容，所述第二电容的一端与所述第四传输晶体管的第二端连接，所述第二电容的另一端接另一固定电位或时序信号。其有益效果在于：能够扩大所述第一光电二极管的满阱电荷，进而扩大所述像素单元的动态范围。
可选地，所述像素单元还包括第一电容和第二电容，所述第一电容的一端与所述转换增益调节晶体管的第一端连接，所述第一电容的另一端接固定电位或时序信号，所述第二电容的一端与所述第四传输晶体管的第二端连接，所述第二电容的另一端接另一固定电位或时序信号，且所述第一电容的电容量小于所述第二电容的电容量。其有益效果在于：能够降低所述第二光电二极管的低转化增益，并且能够扩大所述第一光电二极管的满阱电荷，进而扩大所述像素单元的动态范围。
可选地，所述输出单元包括放大晶体管和选择晶体管，所述放大晶体管的第一端接电源电压，所述放大晶体管的栅极与所述第二传输晶体管的第二端连接，所述放大晶体管的第二端与所述选择晶体管的第一端连接，所述选择晶体管的第二端用于输出所述放大晶体管放大的电压。
可选地，所述像素单元还包括驱动电路，所述驱动电路与所述第一传输晶体管的栅极、所述第二传输晶体管的栅极、所述第三传输晶体管的栅极、 所述复位晶体管的栅极和所述选择晶体管的栅极连接，以驱动所述第一传输晶体管、所述第二传输晶体管、所述第三传输晶体管、所述复位晶体管和所述选择晶体管。
可选地，所述驱动电路还与所述第四传输晶体管的栅极连接，以驱动所述第四传输晶体管。
本发明还提供了一种图像传感器，包括至少一个所述像素单元构成的像素阵列。
所述图像传感器的有益效果在于：包括至少一个所述像素单元构成的像素阵列，像素单元包括第二传输单元，第二传输单元用于将所述第二光电二极管的饱和范围内的电荷传输到第一节点，将所述第二光电二极管的饱和范围外的电荷传输到第二节点或固定电位，由此避免所述第二光电二极管的电荷向所述第一光电二极管扩散而造成不良影响，提高图像质量，并且能够实现高动态范围的同时实现LED闪烁抑制。
附图说明
图1为本发明第一种实施例中像素单元的电路图；
图2为本发明第二种实施例中像素单元的电路图；
图3为本发明第三种实施例中像素单元的电路图；
图4为本发明第四种实施例中像素单元的电路图；
图5为本发明第五种实施例中像素单元的电路图；
图6为本发明第六种实施例中像素单元的电路图；
图7为本发明第七种实施例中像素单元的电路图；
图8为本发明第八种实施例中像素单元的电路图；
图9为本发明第九种实施例中像素单元的电路图；
图10为本发明第十种实施例中像素单元的电路图；
图11为本发明第十一种实施例中像素单元的电路图；
图12为本发明第十二种实施例中像素单元的电路图；
图13为本发明第十三种实施例中像素单元的电路图；
图14为本发明第十四种实施例中像素单元的电路图；
图15为本发明第十五种实施例中像素单元的电路图；
图16为本发明第十六种实施例中像素单元的电路图；
图17为本发明第十七种实施例中像素单元的电路图；
图18为本发明第十八种实施例中像素单元的电路图；
图19为本发明一些实施例中像素单元的时序图；
图20为现有技术中电路的电荷转移示意图；
图21为本发明图1、图2、图5、图8、图10、图11、图14以及图17所示电路的电荷转移示意图；
图22为本发明图3、图4、图6、图7、图9、图12、图13、图15、图16以及图18所示电路的电荷转移示意图。
发明内容
为使本发明的目的、技术方案和优点更加清楚，下面将结合本发明的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本发明的一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。除非另外定义，此处使用的技术术语或者科学术语应当为本发明所属领域内具有一般技能的人士所理解的通常意 义。本文中使用的“包括”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。
针对现有技术存在的问题，本发明的实施例提供了一种图像传感器，包括至少一个像素单元构成的像素阵列。
一些实施例中，所述像素单元包括第一光电二极管、第二光电二极管、第一传输单元、第二传输单元、转换增益调节晶体管、复位晶体管和输出单元。
一些实施例中，所述第一光电二极管的灵敏度低于预定灵敏度；所述第二光电二极管的灵敏度高于所述预定灵敏度；所述第一传输单元用于将所述第一光电二极管的电荷传输到第一节点；所述第二传输单元用于将所述第二光电二极管的饱和范围内的电荷传输到第一节点，将所述第二光电二极管的饱和范围外的电荷传输到第二节点或固定电位；所述转换增益调节晶体管用于通过打开或关断所述第一节点和所述第二节点之间的通路来控制对所述第二光电二极管的转换增益；所述复位晶体管与所述第一传输单元连接，用于将所述像素单元复位；所述输出单元用于放大所述第一节点处的电压并输出。需要说明的是，这里所说的饱和范围指的是第一节点的电荷饱和范围。因此，第二传输单元将第二光电二极管中的、第一节点的电荷饱和范围内的电荷传输到第一节点，将第二光电二极管中的、第一节点的电荷饱和范围外的电荷传输到第二节点或固定电位。
一些实施例中，所述固定电位大于接地电位，且小于或等于电源电位。
一些实施例中，所述第一传输单元包括第一传输晶体管，所述第一传输晶体管的第一端与所述第一光电二极管的阴极连接，所述第一光电二极管的阳极接地，所述第一传输晶体管的第二端与所述复位晶体管的第一端连接，所述复位晶体管的第二端接电源电压。
一些实施例中，所述第二传输单元包括第二传输晶体管和第三传输晶体管，所述第二传输晶体管的第一端和所述第三传输晶体管的第一端均与所述 第二光电二极管的阴极连接，所述第二光电二极管的阳极接地，所述第二传输晶体管的第二端与所述输出单元连接，所述第三传输晶体管单元的第二端与所述第二节点连接或接固定电位。
一些实施例中，所述转换增益调节晶体管的第一端为所述第二节点，所述转换增益调节晶体管的第二端为所述第一节点，所述转换增益调节晶体管的第一端与所述第一传输晶体管的第二端连接，所述转换增益调节晶体管的第二端与所述第二传输晶体管的第二端连接。
一些实施例中，所述转换增益调节晶体管的第一端为所述第二节点，所述转换增益调节晶体管的第二端为所述第一节点，所述转换增益调节晶体管第二端与所述第一传输晶体管的第二端和所述第二传输晶体管的第二端连接，当所述第三传输晶体管单元的第二端接固定电位时，所述转换增益调节晶体管的第一端悬空。
一些实施例中，所述第一传输单元还包括第四传输晶体管，所述第四传输晶体管的第一端与所述第一光电二极管的阴极连接，所述第一光电二极管的阳极接地，所述第四传输晶体管的第二端与所述第一传输晶体管的第一端连接。
一些实施例中，所述输出单元包括放大晶体管和选择晶体管，所述放大晶体管的第一端接电源电压，所述放大晶体管的栅极与所述第二传输晶体管的第二端连接，所述放大晶体管的第二端与所述选择晶体管的第一端连接，所述选择晶体管的第二端用于输出所述放大晶体管放大的电压。
一些实施例中，所述的像素单元还包括驱动电路，所述驱动电路与所述第一传输晶体管的栅极、所述第二传输晶体管的栅极、所述第三传输晶体管的栅极、所述复位晶体管的栅极和所述选择晶体管的栅极连接，以驱动所述第一传输晶体管、所述第二传输晶体管、所述第三传输晶体管、所述复位晶体管和所述选择晶体管。
一些可选实施例中，所述驱动电路还与所述第四传输晶体管的栅极连接，以驱动所述第四传输晶体管。
一些实施例中，所述的像素单元还包括第一电容，所述第一电容的一端与所述转换增益调节晶体管的第一端连接，所述第一电容的另一端接固定电位或时序信号。
一些可选实施例中，所述的像素单元还包括第二电容，所述第二电容的一端与所述第四传输晶体管的第二端连接，所述第二电容的另一端接另一固定电位或时序信号。
一些可选实施例中，所述的像素单元还包括第一电容和第二电容，所述第一电容的一端与所述转换增益调节晶体管的第一端连接，所述第一电容的另一端接固定电位或时序信号，所述第二电容的一端与所述第四传输晶体管的第二端连接，所述第二电容的另一端接另一固定电位或时序信号，且所述第一电容的电容量小于所述第二电容的电容量。
本申请中任意一个晶体管的第一端为源极或漏极，任意一个晶体管的第二端为源极或漏极，且同一个晶体管的第一端和第二端不能同为源极或漏极。
一些实施例中，所述第一传输晶体管、所述第二传输晶体管、所述第三传输晶体管、所述第四传输晶体管、所述转换增益调节晶体管、所述复位晶体管、所述放大晶体管和所述选择晶体管为NMOS管或PMOS管，能够实现相应的功能即可。
图1为本发明第一种实施例中像素单元的电路图。参照图1，所述像素单元100包括第一光电二极管101、第二光电二极管102、第一传输单元103、第二传输单元104、转换增益调节晶体管105、输出单元106以及复位晶体管107。所述第一光电二极管101的灵敏度低于预定灵敏度，所述第二光电二极管102的灵敏度高于预定灵敏度。所述第一传输单元103包括第一传输晶体管1031，所述第二传输单元104包括第二传输晶体管1041和第三传输晶体管1042，所述输出单元106包括放大晶体管1061和选择晶体管1062，所述第一传输晶体管1031、所述第二传输晶体管1041、所述第三传输晶体管1042、所述转换增益调节晶体管105、所述复位晶体管107、所述放大晶 体管1061和所述选择晶体管1062均为NMOS管或PMOS管。
参照图1，所述第一光电二极管101的阳极和所述第二光电二极管102的阳极均接地，所述第一光电二极管101的阴极与所述第一传输晶体管1031的源极连接，所述第一传输晶体管1031的漏极与所述第二节点109连接，所述第一传输晶体管1031的栅极用于接收第一传输控制信号TXS1。
参照图1，所述第二光电二极管102的阴极与所述第二传输晶体管1041的源极和所述第三传输晶体管1042的源极连接，所述第二传输晶体管1041的漏极与所述第一节点108连接，所述第二传输晶体管1041的栅极用于接收第二传输控制信号TXL1，所述第三传输晶体管1042的漏极连接所述第二节点109，所述第三传输晶体管1042的栅极用于接收第三传输控制信号TXL2。
参照图1，所述复位晶体管107的漏极接电源，所述复位晶体管107的源极与所述第二节点109连接，所述复位晶体管107的栅极用于接收复位控制信号RX。
参照图1，所述转换增益调节晶体管105的漏极与所述第二节点109连接，所述转换增益调节晶体管105的源极与所述第一节点108连接，所述转换增益调节晶体管105的栅极用于接收转换增益调节控制信号LCG。
参照图1，所述放大晶体管1061的漏极连接电源，所述放大晶体管1061的源极与所述选择晶体管1062的漏极连接，所述放大晶体管1061的栅极与所述第一节点108连接，所述选择晶体管1062的源极作为所述输出单元106的输出端，所述选择晶体管1062的栅极用于接收选择控制信号SEL。
图2为本发明第二种实施例中像素单元的电路图。图2与图1的区别在于：所述第一传输单元103还包括第四传输晶体管1032，所述第一光电二极管101的阴极与所述第四传输晶体管1032的源极连接，所述第四传输晶体管1032的漏极与所述第一传输晶体管1031的源极连接，所述第四传输晶体管1032的栅极用于接收第四传输控制信号TXS2。
图3为本发明第三种实施例中像素单元的电路图。图3与图1的区别在 于：所述第三传输晶体管1042的源极接工作电压。
图4为本发明第四种实施例中像素单元的电路图。图4与图2的区别在于：所述第三传输晶体管1042的源极接工作电压。
图5为本发明第五种实施例中像素单元的电路图。图5与图1的区别在于：所述像素单元100还包括第一电容1091，所述第一电容1091的一端与所述第二节点109连接，所述第一电容1091的另一端接固定电位或时序信号。
图6为本发明第六种实施例中像素单元的电路图。图6与图3的区别在于：所述像素单元100还包括第一电容1091，所述第一电容1091的一端与所述第二节点109连接，所述第一电容1091的另一端接固定电位或时序信号。
图7为本发明第七种实施例中像素单元的电路图。图7与图4的区别在于：所述像素单元100还包括第一电容1091，所述第一电容1091的一端与所述第二节点109连接，所述第一电容1091的另一端接固定电位或时序信号。
图8为本发明第八种实施例中像素单元的电路图。图8与图2的区别在于：所述像素单元100还包括第一电容1091和第二电容10321，所述第一电容1091的一端与所述第二节点109连接，所述第一电容1091的另一端接固定电位或时序信号，所述第二电容10321的一端与所述第四传输晶体管1032的漏极连接，所述第二电容10321的另一端接另一固定电位或时序信号。
图9为本发明第九种实施例中像素单元的电路图。图9与图4的区别在于：所述像素单元100还包括第一电容1091和第二电容10321，所述第一电容1091的一端与所述第二节点109连接，所述第一电容1091的另一端接固定电位或时序信号，所述第二电容10321的一端与所述第四传输晶体管1032的漏极连接，所述第二电容10321的另一端接另一固定电位或时序信号。
图10为本发明第十种实施例中像素单元的电路图。参照图10，所述像素单元100包括第一光电二极管101、第二光电二极管102、第一传输单元 103、第二传输单元104、转换增益调节晶体管105、输出单元106以及复位晶体管107，所述第一传输单元103包括第一传输晶体管1031，所述第二传输单元104包括第二传输晶体管1041和第三传输晶体管1042，所述输出单元106包括放大晶体管1061和选择晶体管1062，所述第一传输晶体管1031、所述第二传输晶体管1041、所述第三传输晶体管1042、所述转换增益调节晶体管105、所述复位晶体管107、所述放大晶体管1061和所述选择晶体管1062均为NMOS管或PMOS管。
参照图10，所述第一光电二极管101的阳极和所述第二光电二极管102的阳极均接地，所述第一光电二极管101的阴极与所述第一传输晶体管1031的源极连接，所述第一传输晶体管1031的漏极与所述第一节点108连接，所述第一传输晶体管1031的栅极用于接收第一传输控制信号TXS1。
参照图10，所述第二光电二极管102的阴极与所述第二传输晶体管1041的源极和所述第三传输晶体管1042的源极连接，所述第二传输晶体管1041的漏极与所述第一节点108连接，所述第二传输晶体管1041的栅极用于接收第二传输控制信号TXL1，所述第三传输晶体管1042的漏极与所述第二节点109连接，所述第三传输晶体管1042的栅极用于接收第三传输控制信号TXL2。
参照图10，所述复位晶体管107的漏极接电源，所述复位晶体管107的源极与所述第一节点108连接，所述复位晶体管107的栅极用于接收复位控制信号RX。
参照图10，所述转换增益调节晶体管105的漏极与所述第一节点108连接，所述转换增益调节晶体管105的源极与所述第二节点109连接，所述转换增益调节晶体管105的栅极用于接收转换增益调节控制信号LCG。
参照图10，所述放大晶体管1061漏极连接电源，所述放大晶体管1061的源极与所述选择晶体管1062的漏极连接，所述放大晶体管1061的栅极与所述第一节点108连接，所述选择晶体管1062的源极作为所述输出单元106的输出端，所述选择晶体管1062的栅极用于接收选择控制信号SEL。
图11为本发明第十一种实施例中像素单元的电路图。图11与图10的区别在于：所述第一传输单元103还包括第四传输晶体管1032，所述第一光电二极管101的阴极与所述第四传输晶体管1032的源极连接，所述第四传输晶体管1032的漏极与所述第一传输晶体管1031的源极连接，所述第四传输晶体管1032的栅极用于接收第四传输控制信号TXS2。
图12为本发明第十二种实施例中像素单元的电路图。图12与图10的区别在于：所述第三传输晶体管1042的源极接工作电压，所述转换增益调节晶体管105的源极悬空。
图13为本发明第十三种实施例中像素单元的电路图。图13与图11的区别在于：所述第三传输晶体管1042的源极接工作电压，所述转换增益调节晶体管105的源极悬空。
图14为本发明第十四种实施例中像素单元的电路图。图14与图10的区别在于：所述像素单元100还包括第一电容1091，所述第一电容1091的一端与所述第二节点109连接，所述第一电容1091的另一端接固定电位或时序信号。
图15为本发明第十五种实施例中像素单元的电路图。图15与图12的区别在于：所述像素单元100还包括第一电容1091，所述第一电容1091的一端与所述第二节点109连接，所述第一电容1091的另一端接固定电位或时序信号。
图16为本发明第十六种实施例中像素单元的电路图。图16与图13的区别在于：所述像素单元100还包括第一电容1091，所述第一电容1091的一端与所述第二节点109连接，所述第一电容1091的另一端接固定电位或时序信号。
图17为本发明第十七种实施例中像素单元的电路图。图17与图11的区别在于：所述像素单元100还包括第一电容1091和第二电容10321，所述第一电容1091的一端与所述第二节点109连接，所述第一电容1091的另一端接固定电位或时序信号，所述第二电容10321的一端与所述第四传输晶体 管1032的漏极连接，所述第二电容10321的另一端接另一固定电位或时序信号。
图18为本发明第十八种实施例中像素单元的电路图。图18与图13的区别在于：所述像素单元100还包括第一电容1091和第二电容10321，所述第一电容1091的一端与所述第二节点109连接，所述第一电容1091的另一端接固定电位或时序信号，所述第二电容10321的一端与所述第四传输晶体管1032的漏极连接，所述第二电容10321的另一端接另一固定电位或时序信号。
图19本发明一些实施例中像素单元的时序图。所述像素单元的驱动方法包括以下步骤：
步骤一：参照图2和图19，所述复位控制信号RX、所述第一传输控制信号TXS1、所述第二传输控制信号TXL1、所述第三传输控制信号TXL2、所述第四传输控制信号TXS2、所述转换增益调节控制信号LCG均为高电位，以将所述像素单元信号100复位。
步骤二：参照图2和图19，所述第一传输控制信号TXS1和所述第四传输控制信号TXS2均由高电位转为低电位，所述第一光电二极管101开始曝光。
步骤三：参照图2和图19，所述第二传输控制信号TXL1和所述第三传输控制信号TXL2均由高电位转为低电位，所述第二传输晶体管1041和所述第三传输晶体管1042均关断，所述第二光电二极管102开始曝光。
步骤四：参照图2和图19，所述复位控制信号RX由高电位变为低电位，所述选择控制信号SEL由低电平变为高电位，以输出所述第二光电二极管102的低增益复位信号Vrstl，然后所述选择控制信号SEL由高电位变为低电位。
步骤五：参照图2和图19，所述转换增益调节控制信号LCG由高电位变为低电位，所述选择控制信号SEL由低电位变为高电位，以输出所述第二光电二极管102的高增益复位信号Vrst2，然后所述选择控制信号SEL由高电 位变为低电位。
步骤六：参照图2和图19，所述第二传输控制信号TXL1由低电位变为高电位一段时间后由高电位变为低电位，然后所述选择控制信号SEL由低电位变为高电位，以输出所述第二光电二极管102的高增益像素信号Vsig2，然后所述选择控制信号SEL由高电位变为低电位。
步骤七：参照图2和图19，所述转换增益调节控制信号LCG由低电位变为高电位，然后所述第二传输控制信号TXL1由低电位变为高电位一段时间后由高电位变为低电位，再然后所述选择控制信号SEL由低电位变为高电位，以输出所述第二光电二极管102的低增益像素信号Vsigl，再然后所述选择控制信号SEL有高电位变为低电位。
步骤八：参照图2和图19，所述复位控制信号RX由低电位变为高电位，所述第三传输控制信号TXL2由低电位变为高电位，以将所述第一节点108和所述第二节点109复位，然后所述复位控制信号RX由高电位变为低电位，所述第三传输控制信号TXL2由高电位变为低电位，所述选择控制信号SEL由低电位变为高电位，以输出所述第一光电二极管102的复位信号Vrst3，然后所述选择控制信号SEL由高电位变为低电位。
步骤九：参照图2和图19，所述第一传输控制信号TXS1由低电位变为高电位，同时所述第四传输控制信号TXS2由低电位变为高电位然后变为低电位，所述选择控制信号SEL由低电位变为高电位，以输出所述第一光电二极管102的像素信号Vsig3，然后所述选择控制信号SEL由高电位变为低电位。
步骤十：参照图2和图19，所述复位控制信号RX、所述第一传输控制信号TXS1、所述第二传输控制信号TXL1、所述第三传输控制信号TXL2、所述第四传输控制信号TXS2、所述转换增益调节控制信号LCG均为高电位，所述像素单元100复位，以为下次曝光做准备。
所述第二光电二极管102的低增益曝光信号为Vpix1＝Vrst1-Vsig1；所述第二光电二极管102的高增益曝光信号为Vpix2＝Vrst2-Vsig2；所述第一 光电二极管101的曝光信号为Vpix3＝Vrst3-Vsig3。
图20为现有技术中电路的电荷转移示意图。参照图20，现有技术中高灵敏度的光电二极管LP的饱和范围外的电荷1021会溢出到低灵敏度的光电二极管SP内，从而对低灵敏度的光电二极管SP造成影响。
图21为本发明图1、图2、图5、图8、图10、图11、图14以及图17所示电路的电荷转移示意图。参照图21，通过所述第三传输晶体管1042能够将所述第二光电二极管102的饱和范围外的电荷1021释放到所述第二节点109，由此避免所述第二光电二极管102的饱和范围外的电荷溢出到所述第一光电二极管101而造成不良影响。
图22为本发明图3、图4、图6、图7、图9、图12、图13、图15、图16以及图18所示电路的电荷转移示意图。参照图22，通过所述第三传输晶体管1042能够将所述第二光电二极管102的饱和范围外的电荷1021释放到电源VP，由此避免所述第二光电二极管102的饱和范围外的电荷1021溢出到所述第一光电二极管101而造成不良影响。
虽然在上文中详细说明了本发明的实施方式，但是对于本领域的技术人员来说显而易见的是，能够对这些实施方式进行各种修改和变化。但是，应理解，这种修改和变化都属于权利要求书中所述的本发明的范围和精神之内。而且，在此说明的本发明可有其它的实施方式，并且可通过多种方式实施或实现。

Claims (19)

  1. 一种像素单元，其特征在于，包括：
    第一光电二极管，灵敏度低于预定灵敏度；
    第二光电二极管，灵敏度高于所述预定灵敏度；
    第一传输单元，用于将所述第一光电二极管的电荷传输到第一节点；
    第二传输单元，用于将所述第二光电二极管的饱和范围内的电荷传输到第一节点，并将所述第二光电二极管的饱和范围外的电荷传输到第二节点或固定电位；
    转换增益调节晶体管，用于通过打开或关断所述第一节点和所述第二节点之间的通路来控制所述第二光电二极管的转换增益；
    复位晶体管，与所述第一传输单元连接，用于将所述像素单元复位；以及
    输出单元，用于放大所述第一节点处的电压并输出。
  2. 根据权利要求1所述的像素单元，其特征在于，所述第一传输单元包括第一传输晶体管，所述第一传输晶体管的第一端与所述第一光电二极管的阴极连接，所述第一光电二极管的阳极接地，所述第一传输晶体管的第二端与所述复位晶体管的第一端连接，所述复位晶体管的第二端接电源电压。
  3. 根据权利要求2所述的像素单元，其特征在于，所述第二传输单元包括第二传输晶体管和第三传输晶体管，所述第二传输晶体管的第一端和所述第三传输晶体管的第一端均与所述第二光电二极管的阴极连接，所述第二光电二极管的阳极接地，所述第二传输晶体管的第二端与所述输出单元连接，所述第三传输晶体管单元的第二端与所述第二节点连接或接固定电位。
  4. 根据权利要求3所述的像素单元，其特征在于，所述输出单元包括 放大晶体管和选择晶体管，所述放大晶体管的第一端接电源电压，所述放大晶体管的栅极与所述第二传输晶体管的第二端连接，所述放大晶体管的第二端与所述选择晶体管的第一端连接，所述选择晶体管的第二端用于输出所述放大晶体管放大的电压。
  5. 根据权利要求3所述的像素单元，其特征在于，所述转换增益调节晶体管的第一端为所述第二节点，所述转换增益调节晶体管的第二端为所述第一节点，所述转换增益调节晶体管的第一端与所述第一传输晶体管的第二端连接，所述转换增益调节晶体管的第二端与所述第二传输晶体管的第二端连接。
  6. 根据权利要求5所述的像素单元，其特征在于，还包括第一电容，所述第一电容的一端与所述转换增益调节晶体管的第一端连接，所述第一电容的另一端接固定电位或时序信号。
  7. 根据权利要求5所述的像素单元，其特征在于，所述第一传输单元还包括第四传输晶体管，所述第四传输晶体管的第一端与所述第一光电二极管的阴极连接，所述第一光电二极管的阳极接地，所述第四传输晶体管的第二端与所述第一传输晶体管的第一端连接。
  8. 根据权利要求5所述的像素单元，其特征在于，所述输出单元包括放大晶体管和选择晶体管，所述放大晶体管的第一端接电源电压，所述放大晶体管的栅极与所述第二传输晶体管的第二端连接，所述放大晶体管的第二端与所述选择晶体管的第一端连接，所述选择晶体管的第二端用于输出所述放大晶体管放大的电压。
  9. 根据权利要求3所述的像素单元，其特征在于，所述转换增益调节晶体管的第一端为所述第二节点，所述转换增益调节晶体管的第二端为所述第一节点，所述转换增益调节晶体管第二端与所述第一传输晶体管的第二端和所述第二传输晶体管的第二端连接，当所述第三传输晶体管单元的第二端 接固定电位时，所述转换增益调节晶体管的第一端悬空。
  10. 根据权利要求9所述的像素单元，其特征在于，还包括第一电容，所述第一电容的一端与所述转换增益调节晶体管的第一端连接，所述第一电容的另一端接固定电位或时序信号。
  11. 根据权利要求9所述的像素单元，其特征在于，所述输出单元包括放大晶体管和选择晶体管，所述放大晶体管的第一端接电源电压，所述放大晶体管的栅极与所述第二传输晶体管的第二端连接，所述放大晶体管的第二端与所述选择晶体管的第一端连接，所述选择晶体管的第二端用于输出所述放大晶体管放大的电压。
  12. 根据权利要求11所述的像素单元，其特征在于，还包括驱动电路，所述驱动电路与所述第一传输晶体管的栅极、所述第二传输晶体管的栅极、所述第三传输晶体管的栅极、所述复位晶体管的栅极和所述选择晶体管的栅极连接，以驱动所述第一传输晶体管、所述第二传输晶体管、所述第三传输晶体管、所述复位晶体管和所述选择晶体管。
  13. 根据权利要求9所述的像素单元，其特征在于，所述第一传输单元还包括第四传输晶体管，所述第四传输晶体管的第一端与所述第一光电二极管的阴极连接，所述第一光电二极管的阳极接地，所述第四传输晶体管的第二端与所述第一传输晶体管的第一端连接。
  14. 根据权利要求13所述的像素单元，其特征在于，还包括第一电容，所述第一电容的一端与所述转换增益调节晶体管的第一端连接，所述第一电容的另一端接固定电位或时序信号。
  15. 根据权利要求13所述的像素单元，其特征在于，还包括第二电容，所述第二电容的一端与所述第四传输晶体管的第二端连接，所述第二电容的另一端接另一固定电位或时序信号。
  16. 根据权利要求13所述的像素单元，其特征在于，还包括第一电容 和第二电容，所述第一电容的一端与所述转换增益调节晶体管的第一端连接，所述第一电容的另一端接固定电位或时序信号，所述第二电容的一端与所述第四传输晶体管的第二端连接，所述第二电容的另一端接另一固定电位或时序信号，且所述第一电容的电容量小于所述第二电容的电容量。
  17. 根据权利要求13所述的像素单元，其特征在于，所述输出单元包括放大晶体管和选择晶体管，所述放大晶体管的第一端接电源电压，所述放大晶体管的栅极与所述第二传输晶体管的第二端连接，所述放大晶体管的第二端与所述选择晶体管的第一端连接，所述选择晶体管的第二端用于输出所述放大晶体管放大的电压。
  18. 根据权利要求17所述的像素单元，其特征在于，还包括驱动电路，所述驱动电路与所述第一传输晶体管的栅极、所述第二传输晶体管的栅极、所述第三传输晶体管的栅极、所述第四传输晶体管的栅极、所述复位晶体管的栅极和所述选择晶体管的栅极连接，以驱动所述第一传输晶体管、所述第二传输晶体管、所述第三传输晶体管、所述第四传输晶体管、所述复位晶体管和所述选择晶体管。
  19. 一种图像传感器，其特征在于，包括至少一个如权利要求1～18任意一项所述的像素单元构成的像素阵列。
PCT/CN2022/139440 2021-12-17 2022-12-16 像素单元及图像传感器 WO2023109927A1 (zh)

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Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102098456A (zh) * 2009-12-15 2011-06-15 株式会社东芝 可扩大动态范围的固体摄像装置
CN107895729A (zh) * 2016-10-04 2018-04-10 豪威科技股份有限公司 减少照明诱发的闪烁的图像传感器像素和成像系统
CN108282621A (zh) * 2018-03-01 2018-07-13 上海晔芯电子科技有限公司 降低led光源闪烁影响的图像传感器像素结构及成像系统
CN109638027A (zh) * 2017-10-06 2019-04-16 豪威科技股份有限公司 图像传感器、减少发光二极管闪烁的方法及成像系统
CN111971952A (zh) * 2018-04-04 2020-11-20 索尼半导体解决方案公司 固态摄像元件和摄像装置
CN113206963A (zh) * 2020-01-30 2021-08-03 半导体元件工业有限责任公司 具有多个光电二极管的高动态范围成像像素

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102098456A (zh) * 2009-12-15 2011-06-15 株式会社东芝 可扩大动态范围的固体摄像装置
CN107895729A (zh) * 2016-10-04 2018-04-10 豪威科技股份有限公司 减少照明诱发的闪烁的图像传感器像素和成像系统
CN109638027A (zh) * 2017-10-06 2019-04-16 豪威科技股份有限公司 图像传感器、减少发光二极管闪烁的方法及成像系统
CN108282621A (zh) * 2018-03-01 2018-07-13 上海晔芯电子科技有限公司 降低led光源闪烁影响的图像传感器像素结构及成像系统
CN111971952A (zh) * 2018-04-04 2020-11-20 索尼半导体解决方案公司 固态摄像元件和摄像装置
CN113206963A (zh) * 2020-01-30 2021-08-03 半导体元件工业有限责任公司 具有多个光电二极管的高动态范围成像像素

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