WO2023109266A1

WO2023109266A1 - Chip packaging structure and photoelectric apparatus thereof

Info

Publication number: WO2023109266A1
Application number: PCT/CN2022/124162
Authority: WO
Inventors: 汤宁峰
Original assignee: 中兴通讯股份有限公司
Priority date: 2021-12-15
Filing date: 2022-10-09
Publication date: 2023-06-22
Also published as: CN116266587A

Abstract

Disclosed in the present application are a chip packaging structure and a photoelectric apparatus thereof. The chip packaging structure comprises: a CPA substrate (100), wherein the CPA substrate (100) is provided with a first through hole (110); a CPO (200), wherein the CPO (200) is packaged on a first surface of the CPA substrate (100); and an ASIC chip (300), wherein the ASIC chip (300) is packaged on a second surface of the CPA substrate (100), the first surface is located on an opposite side of the second surface, and the ASIC chip (300) is electrically connected to the CPO (200) by means of the first through hole (110).

Description

Chip Packaging Structure and Its Optoelectronic Devices

Cross References to Related Applications

This application is based on a Chinese patent application with application number 202111532291.5 and a filing date of December 15, 2021, and claims the priority of this Chinese patent application. The entire content of this Chinese patent application is hereby incorporated by reference into this application.

technical field

The present application relates to but not limited to the field of integrated chips, and in particular relates to a chip packaging structure and an optoelectronic device thereof.

Background technique

The serializer/deserializer (SERializer/DESerializer, SerDes) technology can effectively improve the serial communication rate, and has been widely used in Switch chips and router chips. As the rate of SerDes continues to increase, the conflict between signal integrity and power consumption becomes more and more obvious. The emergence of Co-Packaged Optics (CPO) solves this problem well.

In optoelectronic equipment, CPO is usually packaged with Application Specific Integrated Circuit (ASIC) chips into Co-Packaged Assemble (CPA). However, in the current packaging structure of CPA, ASIC chip and CPO packaging On the same side of the CPA substrate, in order to realize the transmission of SerDes, it is necessary to set up an electrical link in the CPA substrate, which leads to a longer transmission link of electrical signals, which will be unfavorable to the direct drive of the CPO and the overall power consumption of the CPA. Influence.

Contents of the invention

The following is an overview of the topics described in detail in this article. This summary is not intended to limit the scope of the claims.

Embodiments of the present application provide a chip packaging structure and an optoelectronic device thereof.

In the first aspect, the embodiment of the present application provides a chip packaging structure, including: a co-mounted component CPA substrate, the CPA substrate is provided with a first through hole; a photoelectric co-mounted optical module CPO, the CPO is packaged in the CPA The first surface of the substrate; the ASIC chip, the ASIC chip is packaged on the second surface of the CPA substrate, wherein the first surface is located on the opposite side of the second surface, and the ASIC chip passes through the first The vias are electrically connected to the CPO.

In a second aspect, an embodiment of the present application provides an optoelectronic device, including the chip packaging structure as described in the first aspect.

Additional features and advantages of the application will be set forth in the description which follows, and, in part, will be obvious from the description, or may be learned by practice of the application. The objectives and other advantages of the application will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.

Description of drawings

The accompanying drawings are used to provide a further understanding of the technical solution of the present application, and constitute a part of the specification, and are used together with the embodiments of the present application to explain the technical solution of the present application, and do not constitute a limitation to the technical solution of the present application.

Figure 1 is a schematic structural diagram of the existing CPO and ASIC chips packaged on the same side of the CPA substrate;

FIG. 2 is a schematic cross-sectional view of a chip packaging structure provided by an embodiment of the present application;

FIG. 3 is a schematic cross-sectional view of a chip packaging structure provided in Embodiment 1 of the present application;

FIG. 4 is an exploded view of the chip package structure provided in Embodiment 1 of the present application;

FIG. 5 is a schematic cross-sectional view of a chip packaging structure provided in Embodiment 2 of the present application;

FIG. 6 is an exploded view of the chip package structure provided by Embodiment 2 of the present application.

Detailed ways

In order to make the purpose, technical solution and advantages of the present application clearer, the present application will be described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described here are only used to explain the technical solution of the present application, and are not intended to limit the technical solution of the present application.

It should be noted that although the functional modules are divided in the schematic diagram of the device, and the logical sequence is shown in the flowchart, in some cases, it can be executed in a different order than the module division in the device or the flowchart in the flowchart. steps shown or described. The terms "first", "second" and the like in the specification, claims or the above-mentioned drawings are used to distinguish similar objects, and not necessarily used to describe a specific order or sequential order.

The present application discloses a chip packaging structure and an optoelectronic device thereof. The chip packaging structure includes: a CPA substrate, the CPA substrate is provided with a first through hole; a CPO, the CPO is packaged on the first surface of the CPA substrate; an ASIC chip, the ASIC chip is packaged on the second surface of the CPA substrate, wherein the first surface is located on the opposite side of the second surface, and the ASIC chip is connected to the CPO circuit through the first through hole connect. According to the solution provided by the embodiment of the present application, the ASIC chip and the CPO are respectively arranged on opposite sides of the CPA substrate, so that the ASIC chip can be directly electrically connected to the CPO through the first through hole of the CPA substrate, effectively reducing the gap between the ASIC chip and the CPO. The length of the transmission link between them improves the electrical signal transmission performance of the CPA.

Referring to Fig. 1, Fig. 1 is a schematic structural diagram of the existing CPO and ASIC chip packaged on the same side of the CPA substrate. In this package structure, both the ASIC chip and the CPO are packaged on the same side of the CPA substrate. The transmission of the SerDes between the two needs to set up an electrical link channel in the CPA substrate. The transmission link of the electrical signal is long, resulting in high transmission power consumption, poor signal integrity, and difficult implementation of CPO direct drive.

In order to overcome the defects of the existing CPA packaging structure, the embodiments of the present application will be described below with reference to the accompanying drawings.

Referring to Figure 2, the present application provides a chip packaging structure, including:

CPA substrate 100, the CPA substrate 100 is provided with a first through hole 110;

CPO200, CPO200 is packaged on the first surface of the CPA substrate 100;

The ASIC chip 300 , the ASIC chip 300 is packaged on the second surface of the CPA substrate 100 , wherein the first surface is located on the opposite side of the second surface, and the ASIC chip 300 is electrically connected to the CPO 200 through the first through hole 110 .

It is worth noting that in this embodiment, the CPO200 and the ASIC chip 300 are no longer packaged on the same side of the CPA substrate 100, but the ASIC chip 300 and the CPO200 are respectively arranged on opposite sides of the CPA substrate 100, effectively reducing the ASIC The length of the transmission link between the chip and the CPO200 improves the electrical signal transmission performance of the CPA.

It is worth noting that those skilled in the art know how to realize the electrical connection between the CPO200 and the ASIC chip 300 through the first through hole 110, for example, the inner wall of the first through hole 110 is plated with a conductive material, and the first through hole 110 is set For the via holes, the CPO solder balls 261 and the ASIC chip solder balls 310 are respectively welded on both sides of the via holes. It is also possible that the electrical links connected to the CPO 200 and the ASIC chip 300 respectively pass through the first through holes 110, not many here. Do limited.

It should be noted that the ASIC chip in the embodiment of the present application may be a Switch chip or a Graphics Processing Unit (GPU), which is not limited here.

Various embodiments of the chip packaging structure will be described below through two embodiments.

Embodiment one:

In order to facilitate the description of this embodiment, the present embodiment takes the CPO200 packaged on the front side of the CPA substrate 100 and the ASIC chip 300 packaged on the back side of the CPA substrate 100 as an example for description, which does not limit the CPO200 or the ASIC chip 300 packaged on the CPA substrate 100 The specific location, the technical solution of this embodiment is also applicable to the situation where the CPO 200 is packaged on the reverse side of the CPA substrate 100 and the ASIC chip 300 is packaged on the front side of the CPA substrate 100 .

3 and 4, CPO200 is packaged on CPA substrate 100 through CPO connector 210, one side of CPO connector 210 is packaged with CPO200, and the other side of CPO connector 210 is connected to first through hole 110 of CPA substrate 100 , it can be understood that the detachable connection between the CPO200 and the CPO connector 210 facilitates the replacement and maintenance of the CPO200 with a relatively high loss rate. Of course, if it is necessary for actual needs, as shown in FIG. 5 , the CPO 200 may be directly welded to the CPA substrate 100 , which does not limit the connection method between the CPO 200 and the CPA substrate 100 .

It should be noted that, with reference to FIG. 3 , the CPO connector 210 is generally larger in size, therefore, multiple CPO 200 can be packaged under the condition that the number of CPO connector 210 interfaces and the layout space allow, so as to realize the maximization of the CPO connector 210 interface For example, as shown in FIG. 3 , four CPO200s are arranged in a square shape at the CPO connector 210 to make the capacity density of the CPO200 more compact. Those skilled in the art have the motivation to adjust the specific number and layout of the CPO200 according to actual needs. Here Not much to limit.

It should be noted that the number and connection positions of CPO200 depend on the SerDes signal transmission path with ASIC chip 300. For example, in this embodiment, the SerDes of ASIC chip 300 is designed in the middle of the chip. Therefore, in order to realize the connection between CPO200 and To minimize the transmission path between the ASIC chips 300 , it is necessary to align the CPO 200 with the middle of the ASIC chip 300 , so as to realize the transmission of the SerDes through the first through hole 110 . Of course, as shown in FIG. 3 , in this case of CPO200, a larger CPO connector 210 can be covered on the CPA substrate 100 and positioned on the opposite side of the ASIC chip 300, and then the CPO200 can be connected to the CPA connector by adjusting the CPO200. 210, the CPO200 and the ASIC chip 300 are connected through the first through hole 110, and the full-coverage alignment method can make more alignment points between the CPO200 and the ASIC chip 300, and the ASIC chip 300 can design more SerDes areas. Large, can improve the design flexibility of the ASIC chip 300 .

It is worth noting that when the SerDes of the ASIC chip 300 is designed around the chip, the CPO200 can also be laid out in the manner shown in FIG. One through hole 110 is sufficient for connection. Of course, in the case of using CPO200 and ASIC chip 300 to align around, CPO200 is not arranged side by side, so CPO connector 210 can also be omitted, and CPO200 can be soldered directly to CPA substrate 100. In this case, the size of CPO200 Not limited by the CPO connector 210 , the design size of the CPO200 can be appropriately increased if the size of the CPA substrate 100 allows, which is beneficial to improving the design flexibility of the CPO200 and reducing the design difficulty of the CPO200 .

In addition, with reference to FIG. 3 and FIG. 4 , in order to realize the heat dissipation of the CPO and the ASIC chip, the chip packaging structure of this embodiment is also provided with a first heat sink 410 and a second heat sink 420 , and the first heat sink 410 is arranged on the top of the CPO200 side, the second heat sink 420 is disposed on the lower side of the ASIC chip 300 .

It should be noted that the first radiator 410 and the second radiator 420 can be liquid-cooled radiators or air-cooled radiators; liquid-cooled radiators are small in size and easy to install, while air-cooled Compared with the liquid cooling radiator, the air duct design is more troublesome to install. It can be understood that those skilled in the art can choose the specific type of the first radiator 410 or the second radiator according to the actual heat dissipation space, and can also be immersed Type cooling, not limited here.

It should be noted that the number of the first heat sink 410 or the second heat sink 420 can be arbitrary. For example, referring to FIG. To achieve heat dissipation, those skilled in the art have the motivation to select the specific number of the first heat sink 410 or the second heat sink 420 according to actual needs, and there is no limitation here.

In addition, referring to FIG. 3 and FIG. 4 , the chip packaging structure of this embodiment is further provided with a line card main board 500, and the line card main board 500 is connected to the CPA substrate 100 through at least two line card connectors 510, thereby realizing the ASIC chip 300. Power supply, clock supply and connection of control signals.

Referring to FIG. 3 and FIG. 4 , the reverse side of the CPA substrate 100 forms a first space between the line card connector 510 and the line card main board 500. The first space can provide a setting space for the ASIC chip 300 and the second heat sink 420. It is worth noting that It is worth noting that this embodiment does not limit the specific height of the line card connector 510. Those skilled in the art have the motivation to adjust the specific height of the line card connector 510 according to the volume of the heat sink. For example, referring to FIGS. 3 and 4, if Considering the use of an air-cooled heat sink to dissipate heat from the ASIC chip 300, it is necessary to consider the design of the air duct and select a line card connector 510 with a relatively high height for adaptation. However, in this embodiment, a liquid-cooled heat dissipation method is used to realize the heat dissipation of the ASIC chip 300. There is no need to consider the design of the air duct, and the height of the line card connector 510 can be appropriately reduced, which is not limited here.

Embodiment two:

In order to facilitate the description of this embodiment, this embodiment takes CPO200 packaged on the reverse side of the CPA substrate 100 and the ASIC chip 300 packaged on the front side of the CPA substrate 100 as an example for description. This is not to limit the CPO200 or ASIC chip 300 packaged on the CPA substrate 100. The specific location, the technical solution of this embodiment is also applicable to the situation where the CPO 200 is packaged on the front side of the CPA substrate 100 and the ASIC chip 300 is packaged on the back side of the CPA substrate 100 .

The chip packaging structure of this embodiment is similar to that of Embodiment 1, mainly having the following differences:

Referring to FIG. 6, in this embodiment, the SerDes of the ASIC chip 300 is designed around the chip. In order to minimize the transmission path between the CPO200 and the ASIC chip 300, the CPO200 is aligned with the edge area of the ASIC chip 300, so that the CPO200 It is connected with the ASIC chip 300 through the first through hole 110 .

It is worth noting that when the SerDes of the ASIC chip 300 is designed in the middle of the chip, CPO200 can also be laid out in the manner shown in FIG. The hole 110 can be connected.

It is worth noting that referring to FIG. 5 , the CPO200 in this embodiment is directly welded to the CPA substrate 100. It can be understood that the welding method is compared with the CPO connector 210 shown in FIG. 4 to achieve the CPO200 and the CPA substrate 100 The packaging method can reduce insertion loss and cost, which does not limit the connection method between CPO200 and CPA substrate 100. As shown in Figure 3, CPO200 is packaged on CPA substrate 100 through CPO connector 210. Technicians can choose according to the actual situation.

It is worth noting that this embodiment does not limit the specific number and specific size of CPO200. For example, referring to FIG. , those skilled in the art have the motivation to adjust the specific number and layout of the CPO 200 according to actual needs, which are not limited here.

With reference to Fig. 5, in the present embodiment, CPO200 comprises EIC220, PIC230, pigtail 240 and optical fiber connector 250, and EIC220 is electrically connected with ASIC chip 300, and PIC230 is coupled with pigtail 240, and pigtail 240 is connected away from one end of described PIC230 Fiber optic connector 250.

It is worth noting that this embodiment does not limit the connection method between EIC220 and ASIC chip 300, and the specific method of packaging PIC230 on CPO200. As shown in FIG. 5, EIC220 is soldered to CPO substrate 260 through EIC solder balls 221. The CPO substrate 260 is soldered to the CPA substrate 100 through the CPO solder balls 261. Since the ASIC chip 300 is packaged on the CPA substrate 100 through the ASIC chip solder balls 310, the EIC solder balls 221 pass through the second through hole 262 in the CPO substrate 260 and the CPA substrate 100. The first through hole 110 of the ASIC chip is aligned and electrically connected with the ASIC chip solder ball 310, thereby realizing the connection between the EIC220 and the ASIC chip 300; the PIC230 is packaged on the CPO substrate 260 through the PIC solder ball 231, and the specific solder balls connected to each other can be Selection is based on actual needs. This embodiment only describes the connection relationship between two chips. The specific selection of solder balls is not within the scope of this embodiment, and will not be repeated in the future.

It is worth noting that since the CPO 200 of this embodiment is packaged on the reverse side of the CPA substrate 100, four line card connectors 510 are arranged at intervals around the line card main board 500, and channels are formed between every two line card connectors 510, which is convenient Fan-out of CPO200 pigtail 240.

It should be noted that this embodiment does not limit the specific number of line card connectors 510 , and those skilled in the art are motivated to make adjustments according to actual needs.

In addition to the above differences, other parts of the chip package structure of this embodiment can refer to the description of Embodiment 1, and for the sake of brevity, details are not repeated here.

In addition, the present application also provides an optoelectronic device (not shown in the figure), including the chip packaging structure described in any one of the above embodiments.

It should be noted that the optoelectronic device in this embodiment may be a switch, a router, an artificial intelligence (AI) device, a Compute Express Link (CXL) product, etc., which involve photoelectric conversion and use SerDes technology to achieve high-speed The transfer device is fine.

It should be noted that after applying any one of the chip packaging structures in the first to second embodiments above to the optoelectronic device, since the ASIC chip 300 and the CPO 200 are respectively arranged on opposite sides of the CPA substrate 100, the ASIC chip 300 can It is directly electrically connected to the CPO200 through the first through hole 110 of the CPA substrate 100, effectively reducing the length of the transmission link between the ASIC chip 300 and the CPO200, and improving the electrical signal transmission performance of the CPA, thereby making the computing speed or switching speed of the optoelectronic device There has been a significant improvement.

The above is a specific description of the preferred implementation of the application, but the application is not limited to the above-mentioned implementation, and those skilled in the art can also make various equivalent deformations or replacements without violating the essence of the application. Equivalent modifications or replacements are all within the scope defined by the claims of the present application.

Claims

A chip packaging structure, comprising:

A co-mounted component CPA substrate, the CPA substrate is provided with a first through hole;

A photoelectric co-mounted optical module CPO, the CPO is packaged on the first surface of the CPA substrate;

An application specific integrated circuit ASIC chip, the ASIC chip is packaged on the second surface of the CPA substrate, wherein the first surface is located on the opposite side of the second surface, and the ASIC chip is connected to the second surface through the first through hole The CPO is electrically connected.
The chip packaging structure according to claim 1, further comprising:

A CPO connector, wherein the CPO is encapsulated on one side of the CPO connector, and the other side of the CPO connector is connected to the first through hole.
The chip packaging structure according to claim 2, wherein,

The CPO connector encapsulates at least two of the CPOs.
The chip packaging structure according to claim 1, further comprising:

A first heat sink, the first heat sink is disposed on a side of the CPO away from the CPA substrate.
The chip packaging structure according to claim 4, further comprising:

A second heat sink, the second heat sink is disposed on a side of the ASIC chip away from the CPA substrate.
The chip packaging structure according to claim 5, wherein,

The first radiator and the second radiator are air-cooled radiators or liquid-cooled radiators.
The chip packaging structure according to claim 1, further comprising:

A line card main board, where the line card main board is connected to the CPA substrate through at least two line card connectors.
The chip packaging structure according to claim 1, wherein the CPO comprises an electrical chip (EIC), and the EIC is electrically connected to the ASIC chip.
The chip packaging structure according to claim 1, wherein the CPO comprises an optical chip PIC, the PIC is coupled with a pigtail, and an end of the pigtail far away from the PIC is connected with an optical fiber connector.
An optoelectronic device, comprising the chip package structure according to any one of claims 1-9.