WO2023108874A1 - 一种半导体结构及其制造方法 - Google Patents

一种半导体结构及其制造方法 Download PDF

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Publication number
WO2023108874A1
WO2023108874A1 PCT/CN2022/076160 CN2022076160W WO2023108874A1 WO 2023108874 A1 WO2023108874 A1 WO 2023108874A1 CN 2022076160 W CN2022076160 W CN 2022076160W WO 2023108874 A1 WO2023108874 A1 WO 2023108874A1
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layer
silicon
substrate
present disclosure
interconnection
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PCT/CN2022/076160
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English (en)
French (fr)
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张志伟
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长鑫存储技术有限公司
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Priority to US17/854,181 priority Critical patent/US20230187316A1/en
Publication of WO2023108874A1 publication Critical patent/WO2023108874A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures

Definitions

  • Embodiments of the present disclosure relate to the technical field of semiconductor manufacturing, and in particular, to a semiconductor structure and a manufacturing method thereof.
  • TSV Through Silicon Via
  • the current method for forming through-silicon vias mainly includes: forming a through hole perpendicular to the silicon substrate on the first surface of the silicon substrate; forming an insulating layer on the sidewall and bottom of the through hole; Filling with a conductive material; performing chemical mechanical polishing (Chemical Mechanical Polishing, CMP) on the second surface of the silicon substrate opposite to the first surface, until a through hole filled with a conductive material is exposed, that is, a through-silicon via is formed .
  • CMP chemical mechanical polishing
  • the embodiments of the present disclosure provide a semiconductor structure and a manufacturing method thereof to solve at least one technical problem existing in the prior art.
  • an embodiment of the present disclosure provides a method for manufacturing a semiconductor structure, including:
  • the underlying silicon of the substrate is pretreated to expose the conductive pillars to form through-silicon vias; wherein, the underlying silicon is used to block metal pollutants generated by the pretreatment.
  • the pretreatment includes grinding treatment.
  • the grain size of the bottom silicon is smaller than the grain size of the top silicon.
  • the thickness of the top silicon layer is greater than the thickness of the bottom silicon layer.
  • the substrate further includes a buried oxide layer between the bottom silicon and the top silicon; the forming penetrates through the device layer and the top silicon and extends into the bottom layer Through-silicon vias, including:
  • a through hole is formed through the device layer, the top silicon layer and the buried oxide layer in sequence, and extends into the bottom silicon layer.
  • the formation of the via holes that sequentially penetrate through the device layer, the top silicon layer, and the buried oxide layer and extend into the bottom silicon layer includes:
  • the diameter of the part of the through hole located in the buried oxide layer is greater than or equal to the diameter of the part of the through hole located in the top layer of silicon;
  • the pore diameter of the part of the through hole located in the underlying silicon is greater than or equal to the pore diameter of the part of the through hole located in the buried oxide layer.
  • the device layer includes transistor devices and capacitive devices.
  • the method before the pretreatment of the underlying silicon of the substrate, the method further includes:
  • the interconnection layer includes an interconnection via hole and an interconnection metal layer.
  • the method before the pretreatment of the underlying silicon of the substrate, the method further includes:
  • a bump structure is formed in the groove, and the bump structure is electrically connected to the interconnection layer.
  • an embodiment of the present disclosure provides a semiconductor structure, including:
  • a substrate comprising top silicon and bottom silicon
  • the through-silicon vias are disposed inside the substrate and penetrate through the substrate and the device layer.
  • the grain size of the bottom silicon is smaller than the grain size of the top silicon.
  • the substrate further includes a buried oxide layer between the bottom silicon and the top silicon.
  • the device layer includes transistor devices and capacitive devices.
  • interconnection layer is located on the device layer, and the interconnection layer is electrically connected to the through-silicon via;
  • the interconnection layer includes an interconnection via hole and an interconnection metal layer.
  • the bump structure is electrically connected to the interconnection layer.
  • the TSVs are filled with conductive materials.
  • the through-silicon vias are disposed inside the substrate and penetrate through the substrate and the device layer, including:
  • the diameter of the portion of the TSV located in the buried oxide layer is greater than or equal to the pore diameter of the portion of the TSV located in the top layer of silicon;
  • the diameter of the portion of the TSV located in the underlying silicon is greater than or equal to the diameter of the portion of the TSV located in the buried oxide layer.
  • An embodiment of the present disclosure provides a semiconductor structure and a manufacturing method thereof.
  • the method includes: providing a substrate, the substrate including a top silicon layer and a bottom layer silicon; forming a device layer on the top silicon layer of the substrate; forming a device layer penetrating through the device layer. and the top layer of silicon and extend into the via holes of the bottom silicon; filling the via holes to form conductive pillars; pre-processing the bottom silicon of the substrate to expose the conductive pillars to form through silicon vias ; Wherein, the underlying silicon is used to block metal pollutants produced by pretreatment.
  • the bottom-layer silicon is pretreated to expose the conductive pillars.
  • the underlying silicon blocks the contamination of the top layer of silicon (i.e., the silicon substrate) by the metal material produced by the pretreatment, and there is no need to set up an additional protective layer to prevent the contamination of the metal material to the silicon substrate, thereby simplifying the exposure of the back hole of the through-silicon via.
  • FIG. 1A is a schematic cross-sectional structure diagram of a semiconductor structure provided by an embodiment of the present disclosure after forming through-silicon vias;
  • FIG. 1B is a schematic cross-sectional structure diagram of a semiconductor structure exposing the end of a TSV provided by an embodiment of the present disclosure
  • 1C is a schematic cross-sectional view of a semiconductor structure after forming an oxide layer and a silicon nitride layer according to an embodiment of the present disclosure
  • 1D is a schematic cross-sectional structural view of a semiconductor structure exposing a conductive layer in a through-silicon via provided by an embodiment of the present disclosure
  • FIG. 2 is an optional schematic flowchart of a method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure
  • FIG. 3A is a schematic cross-sectional structure diagram of a substrate provided by an embodiment of the present disclosure.
  • 3B is a schematic cross-sectional structure diagram of a semiconductor structure after forming a device layer according to an embodiment of the present disclosure
  • FIG. 3C is a schematic cross-sectional structure diagram of a semiconductor structure after via holes are formed according to an embodiment of the present disclosure
  • 3D is a schematic cross-sectional structure diagram of a semiconductor structure after an isolation layer is formed in a through hole provided by an embodiment of the present disclosure
  • 3E is a schematic cross-sectional structure diagram of a semiconductor structure after forming conductive pillars provided by an embodiment of the present disclosure
  • 3F is a schematic cross-sectional structure diagram of a semiconductor structure after forming an interconnection metal layer according to an embodiment of the present disclosure
  • 3G is a schematic cross-sectional structure diagram of a semiconductor structure after forming grooves provided by an embodiment of the present disclosure
  • 3H is a schematic cross-sectional structure diagram of a semiconductor structure after forming a bump structure provided by an embodiment of the present disclosure
  • FIG. 3I is a schematic cross-sectional structure diagram after flipping the semiconductor structure forming the bump structure provided by an embodiment of the present disclosure
  • 3J is a schematic cross-sectional structure diagram of a semiconductor structure exposing conductive pillars provided by an embodiment of the present disclosure
  • FIG. 4A is a schematic cross-sectional structure diagram of another substrate provided by an embodiment of the present disclosure.
  • 4B is a schematic cross-sectional structure diagram of another semiconductor structure after forming a device layer according to an embodiment of the present disclosure
  • FIG. 4C is a schematic cross-sectional structure diagram of another semiconductor structure after via holes are formed according to an embodiment of the present disclosure
  • FIG. 4D is a schematic cross-sectional structure diagram of another semiconductor structure after forming an isolation layer in a through hole according to an embodiment of the present disclosure
  • 4E is a schematic cross-sectional structure diagram of another semiconductor structure after forming conductive pillars according to an embodiment of the present disclosure
  • 4F is a schematic cross-sectional structure diagram of another semiconductor structure after forming an interconnection metal layer according to an embodiment of the present disclosure
  • FIG. 4G is a schematic cross-sectional structure diagram of another semiconductor structure after forming grooves according to an embodiment of the present disclosure.
  • 4H is a schematic cross-sectional structure diagram of another semiconductor structure after forming a bump structure provided by an embodiment of the present disclosure
  • FIG. 4I is another schematic cross-sectional structure diagram after flipping the semiconductor structure forming the bump structure provided by an embodiment of the present disclosure
  • 4J is a schematic cross-sectional structure diagram of another semiconductor structure exposing conductive pillars provided by an embodiment of the present disclosure
  • FIG. 5A is a schematic cross-sectional structure diagram of through holes located in the bottom silicon and the top silicon provided by an embodiment of the present disclosure
  • 5B is a schematic cross-sectional structure diagram of a through hole located in the underlying silicon, the buried oxide layer, and the top silicon provided by an embodiment of the present disclosure
  • the figure includes: 101-silicon substrate; 101a-first surface; 101b-second surface; 102-through-silicon via; 103-isolation layer; 104-conductive layer; 105-oxidation layer; 106-silicon nitride layer; 301, 401-bottom silicon; 402-buried oxide layer; 303, 403-top silicon; 304, 404-device layer; 305, 405-semiconductor device; 306, 406-through hole; 307, 407-isolation layer; 308, 408-conductive column; 309, 409-top metal layer; 310, 410-insulation layer; 311, 411-passivation layer; 312, 412-groove; 313, 413-bump structure; 414-bonding layer; 415 -Substrate; 416-Metal contamination; S 1 -The distance of the end of the exposed TSV in the direction perpendicular to the silicon substrate; W 1 , W 1' -The diameter of the part of the through hole located
  • the current method of forming TSV mainly includes: forming a through hole perpendicular to the silicon substrate on the front surface of the silicon substrate; forming an insulating layer on the sidewall and bottom of the through hole; The backside of the silicon substrate is subjected to chemical mechanical polishing until the through holes filled with conductive materials are exposed, that is, through silicon vias are formed.
  • the conductive material filled in the through hole such as copper, is likely to contaminate the silicon substrate. Therefore, how to improve the hole exposure technology on the back side of TSVs and reduce the contamination of metal materials to the silicon substrate is an urgent problem to be solved.
  • FIG. 1A is a schematic cross-sectional structure diagram of a semiconductor structure after forming TSVs according to an embodiment of the present disclosure.
  • the TSV 102 extends from the first surface 101 a of the silicon substrate 101 into the silicon substrate 101 , and the TSV 102 does not penetrate the silicon substrate 101 .
  • the direction in which the through-silicon hole 102 is formed by etching is perpendicular to the silicon substrate 101.
  • an isolation material is deposited on the sidewall and bottom of the through-silicon hole to form an isolation layer 103;
  • a conductive material is deposited in the hole 102 to form a conductive layer 104 .
  • the silicon substrate 101 has a first surface 101a, and a second surface 101b opposite to the first surface 101a.
  • the first surface may be the front side of the silicon substrate, and the second surface may be the back side of the silicon substrate.
  • the deposition of the isolation layer and the conductive layer in the TSV can be achieved by one or more deposition processes.
  • the deposition process includes but not limited to Physical Vapor Deposition (Physical Vapor Deposition, PVD), Chemical Vapor Deposition (Chemical Vapor Deposition, CVD), Atomic Layer Deposition (Atomic Layer Deposition, ALD) or any combination thereof.
  • the isolation layer may include an oxide layer, for example, a silicon dioxide layer; the conductive layer may include a metal layer, for example, a copper layer.
  • FIG. 1B is a schematic cross-sectional structure diagram of a semiconductor structure exposing ends of TSVs provided by an embodiment of the present disclosure.
  • the back side of the silicon substrate is thinned (backside grinding), to expose the end of the through-silicon hole or from the second surface 101b of the silicon substrate. , etch the silicon substrate 101 to expose the ends of the TSVs.
  • the backside of the silicon substrate is thinned, and the thinned thickness of the silicon substrate is about 20 ⁇ m. Referring to FIG. 1B here, after thinning the backside of the silicon substrate, the ends of the TSVs are exposed.
  • the silicon substrate may also be dry-etched from the second surface of the silicon substrate to expose the ends of the through-silicon vias.
  • the distance of the exposed end of the TSV in a direction perpendicular to the silicon substrate may be about 6.5 ⁇ m.
  • FIG. 1C is a schematic cross-sectional view of a semiconductor structure after forming an oxide layer and a silicon nitride layer according to an embodiment of the present disclosure.
  • an oxide layer 105 is deposited on the second surface of the silicon substrate 101 to cover the second surface of the silicon substrate 101 and the ends of the TSVs.
  • a silicon nitride layer 106 is deposited on the oxide layer 105 , and the silicon nitride layer 106 completely covers the oxide layer 105 .
  • forming an oxide layer on the second surface of the silicon substrate and forming a silicon nitride layer on the oxide layer may be achieved by one or more deposition processes.
  • the deposition process includes but not limited to physical vapor deposition, chemical vapor deposition, atomic layer deposition or any combination thereof.
  • the thickness of the oxide layer formed to cover the second surface of the silicon substrate and the ends of the TSVs is about 1.85 ⁇ m.
  • the thickness of the silicon nitride layer covering the oxide layer is about 0.3 ⁇ m.
  • FIG. 1D is a schematic cross-sectional structure diagram of a semiconductor structure exposing a conductive layer in a TSV according to an embodiment of the present disclosure.
  • chemical mechanical polishing is used to remove the isolation layer 103 at the end of the TSV to expose the conductive layer 104 at the end of the TSV.
  • the oxide layer and the silicon nitride layer covering the end of the TSV can be used as a protection layer to isolate material contamination of the conductive layer, such as metal contamination, generated by grinding on the surface of the silicon nitride layer or the oxide layer.
  • an embodiment of the present disclosure provides a method for manufacturing a semiconductor structure.
  • the bottom-layer silicon is pretreated to expose the conductive pillars.
  • the underlying silicon can also be used to block metal pollutants generated by pretreatment.
  • FIG. 2 is a schematic flowchart of an optional method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure. As shown in FIG. 2, the method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure includes:
  • Step S201 providing a substrate, the substrate comprising top-layer silicon and bottom-layer silicon;
  • Step S202 forming a device layer on the top silicon layer of the substrate
  • Step S203 forming a via hole penetrating through the device layer and the top silicon and extending into the bottom silicon;
  • Step S204 filling the through hole to form a conductive column
  • Step S205 performing pretreatment on the underlying silicon of the substrate to expose the conductive pillars to form through-silicon vias; wherein the underlying silicon is used to block metal pollutants generated by the pretreatment.
  • FIG. 3A is a schematic cross-sectional structure diagram of a substrate provided by an embodiment of the present disclosure. As shown in FIG. 3A , the substrate includes bottom silicon 301 and top silicon 303 .
  • the thickness of the top silicon layer is greater than the thickness of the bottom silicon layer.
  • the underlying silicon is used to block metal pollutants generated by the pretreatment.
  • the bottom silicon can act as a protective layer to isolate the metal contamination from the pretreatment from the top silicon. Therefore, the thickness of the bottom layer of silicon may be smaller than the thickness of the top layer of silicon. Thereafter, the underlying silicon may also be removed.
  • the grain size of the bottom silicon is smaller than the grain size of the top silicon.
  • the underlying silicon is provided to block metal contamination from pretreatment. Therefore, if the grain size of the bottom silicon is set to be smaller than that of the top silicon, the grains of the bottom silicon will be arranged more densely, and the bottom silicon will have a better effect of blocking metal pollutants, which can effectively prevent metal pollutants from being embedded in the in the underlying silicon.
  • FIG. 3B is a schematic cross-sectional structure diagram of a semiconductor structure after forming a device layer according to an embodiment of the present disclosure.
  • a device layer 304 is formed on the top silicon layer 303 , and a semiconductor device 305 is included in the device layer 304 .
  • the embodiment of the present disclosure does not illustrate the specific structure of the device layer, but only schematically shows that there is a semiconductor device in the layer, and the thickness ratio between the device layer and other material layers is not considered to be an important aspect of the present disclosure. The limitation of the thickness of the device layer.
  • the device layer includes transistor devices and capacitive devices.
  • the device layer includes a dielectric layer and transistor devices and capacitor devices formed in the dielectric layer.
  • semiconductor devices formed within the device layer may include transistor devices and capacitor devices.
  • the transistor device may include one or more Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs).
  • MOSFETs Metal-Oxide-Semiconductor Field-Effect Transistors
  • Transistors may include planar transistors, non-planar transistors, or a combination of both.
  • the planar transistor may include a bipolar junction transistor (Bipolar Junction Transistor, BJT), a heterojunction bipolar transistor (Heterojunction Bipolar Transistor, HBT) or a high electron mobility transistor (High Electron Mobility Transistor, HEMT).
  • surround- or full-ring gate transistors e.g., nanoribbon and nanowire transistors.
  • the process of forming a semiconductor device in an embodiment of the present disclosure involves a front end of line (FEOL) in a semiconductor manufacturing process.
  • FEOL front end of line
  • FIG. 3C is a schematic cross-sectional structure diagram of a semiconductor structure after via holes are formed according to an embodiment of the present disclosure.
  • a via 306 is formed through the device layer 304 and the top silicon 303 and extends into the bottom silicon 301 .
  • Embodiments of the present disclosure may use wet etching, dry etching, or a combination thereof to etch the device layer, top silicon, and bottom silicon to form via holes.
  • a patterned photoresist layer can be formed on the device layer, and the device layer, top silicon and bottom silicon are sequentially etched using the patterned photoresist layer to form a through-device layer and top silicon and extend into vias in the bottom silicon. After the via holes are formed, the photoresist may be removed, ie photoresist strip (PR strip).
  • PR strip photoresist strip
  • the formation of the via hole penetrating the device layer and the top silicon layer and extending into the bottom silicon layer includes: the diameter of the portion of the via hole located in the bottom silicon layer is greater than or equal to that of the via hole located in the bottom silicon layer. Partial pore diameter in the top silicon.
  • the etching process parameters for example, prolong the etching time, so that the aperture diameter of the part of the through hole located in the bottom silicon layer is greater than or equal to the aperture diameter of the part of the via hole located in the top layer silicon.
  • the size of the portion of the conductive pillars located in the bottom layer of silicon is greater than or equal to the size of the portion of the conductive pillars located in the top layer of silicon.
  • FIG. 3C shows that the diameter of the portion of the via located in the bottom silicon is equal to the diameter of the portion of the via located in the top silicon.
  • FIG. 5A is a schematic cross-sectional structure diagram of a through hole located in the bottom silicon and the top silicon according to an embodiment of the present disclosure.
  • FIG. 5A shows that the diameter W 1 of the portion of the via located in the bottom silicon is greater than the diameter W 3 of the portion of the via located in the top silicon.
  • the size of the portion of the conductive pillars located in the bottom silicon layer is greater than or equal to the size of the portion of the conductive pillars located in the top layer of silicon.
  • FIG. 3D is a schematic cross-sectional structure diagram of a semiconductor structure after an isolation layer is formed in a via hole according to an embodiment of the present disclosure. As shown in FIG. 3D , an isolation layer 307 is deposited on the sidewall and bottom of the via hole.
  • the deposition and formation of the isolation layer in the through hole may be achieved by one or more deposition processes.
  • the deposition process includes but not limited to physical vapor deposition, chemical vapor deposition, atomic layer deposition or any combination thereof.
  • a liner deposition source (liner deposition) can also be used to deposit and form the isolation layer in the through hole.
  • FIG. 3E is a schematic cross-sectional structure diagram of a semiconductor structure after forming conductive pillars according to an embodiment of the present disclosure. As shown in FIG. 3E , the conductive material is continuously filled into the via hole to form a conductive column 308 .
  • methods including but not limited to vacuum evaporation, sputtering plating, and ion plating may be used to deposit and form the conductive pillars in the through holes.
  • chemical mechanical polishing can also be used to remove excess conductive material, so that the upper surface of the conductive pillars is flush with the upper surface of the device layer.
  • the conductive material forming the conductive column may include but not limited to metal material.
  • the material forming the conductive pillar is, for example, copper.
  • FIG. 3F is a schematic cross-sectional structure diagram of a semiconductor structure after forming an interconnection metal layer according to an embodiment of the present disclosure.
  • an interconnection layer (not shown in the figure) is formed on the device layer 304, and the interconnection layer is electrically connected to the conductive column;
  • the interconnection layer includes interconnection vias (via) and Interconnect metal layer (metal);
  • the interconnect metal layer includes a top metal layer 309 , the interconnect layer is electrically connected to the semiconductor device 305 , and the top metal layer 309 is electrically connected to the conductive pillar.
  • a dielectric layer is deposited on the device layer, and then a patterned photoresist layer is formed on the dielectric layer, and the patterned photoresist layer is used to etch the dielectric layer to form a top layer
  • the metal layer is patterned and filled with material to form the top metal layer 309 .
  • the material of the dielectric layer may be silicon dioxide.
  • a metal material layer is deposited on the device layer, and then a patterned photoresist layer is formed on the metal material layer, and the patterned photoresist layer is used to treat the metal material layer is etched to form the top metal layer.
  • FIG. 3G is a schematic cross-sectional structure diagram of a semiconductor structure after grooves are formed according to an embodiment of the present disclosure.
  • an insulating layer 310 and a passivation layer 311 covering the interconnection layer are formed, and the passivation layer 311 and the insulating layer 310 are etched to form a groove 312 exposing the top metal layer 309 .
  • the material forming the insulating layer may be silicon dioxide.
  • the material deposited to form a passivation layer may include but not limited to silicon nitride.
  • FIG. 3H is a schematic cross-sectional structure diagram of a semiconductor structure after the bump structure is formed according to an embodiment of the present disclosure.
  • a passivation layer 311 covers the upper surface of the insulating layer 310 , and a conductive material is deposited in the groove to form a bump structure 313 , and the bump structure 313 is electrically connected to the top metal layer 309 .
  • the conductive material deposited to form the bump structure may include, but not limited to, a metal material.
  • the conductive material forming the bump structure may be copper.
  • FIG. 3I is a schematic cross-sectional structure diagram after the semiconductor structure forming the bump structure is turned over according to an embodiment of the present disclosure. As shown in FIG. 3I , the wafer on which the bump structure has been formed is flipped over.
  • FIG. 3J is a schematic cross-sectional structure diagram of a semiconductor structure exposing conductive pillars according to an embodiment of the present disclosure.
  • the underlying silicon 301 is pretreated to remove the isolation layer 307 at the end of the conductive pillar 308 to expose the conductive pillar 308 .
  • the pretreatment may include, but not limited to, chemical mechanical polishing treatment.
  • the bottom silicon can be used as a protective layer to isolate the metal contamination generated by the pretreatment from the top silicon.
  • the manufacturing method of the semiconductor structure provided by the embodiments of the present disclosure by setting the top-layer silicon and the bottom-layer silicon, after forming the conductive pillars penetrating the top-layer silicon and extending into the bottom-layer silicon, the bottom-layer silicon is pre-treated to expose the conductive pillars, without adding additional With advanced process steps, the metal pollutants produced by pretreatment can be blocked by using the bottom silicon, effectively preventing the metal pollutants from polluting the top silicon.
  • the manufacturing method of the semiconductor structure provided by the embodiments of the present disclosure can reduce the pollution of the silicon substrate (top-layer silicon) by metal pollutants while reducing the difficulty and cost of the process.
  • FIG. 4A is a schematic cross-sectional structure diagram of another substrate provided by an embodiment of the present disclosure.
  • the substrate includes bottom silicon 401 and top silicon 403 , and a buried oxide layer 402 between the bottom silicon 401 and top silicon 403 .
  • the base may include Silicon-On-Insulator (SOI), that is, a layer of oxide material is disposed between two layers of silicon material.
  • SOI Silicon-On-Insulator
  • the use of SOI in semiconductor devices has many advantages, such as: reducing parasitic capacitance, increasing operating speed; reducing power consumption; eliminating latch-up effects; suppressing pulse current interference in the substrate, reducing the occurrence of soft errors; Silicon process compatible, can reduce 13% to 20% of the process.
  • N-type metal-oxide-semiconductor N-Metal-Oxide-Semiconductor, NMOS
  • P-type metal-oxide-semiconductor P-Metal-Oxide-Semiconductor, PMOS
  • substrate The parasitic capacitance between varies linearly with the doping concentration of the substrate. As the size of semiconductor devices continues to decrease, in order to reduce the short channel effect, the doping concentration of the substrate must be increased appropriately, and the capacitance of the source-drain junction increases accordingly, and the parasitic between the source-drain junction and the channel blocking region The capacitance increases accordingly.
  • the parasitic capacitance between the source-drain junction and the substrate is the buried insulator capacitance, which is proportional to the dielectric constant of the buried oxide layer, and the dielectric constant of silicon dioxide in the buried oxide layer is only one-third of that of silicon one.
  • the thickness of the buried oxide layer does not need to be scaled down, and the parasitic capacitance will not increase. Therefore, using SOI in semiconductor devices can reduce parasitic capacitance, increase operating speed, and reduce power consumption.
  • each device is surrounded by an oxide layer, completely isolated from surrounding devices, and latch-up effect is eliminated. Therefore, using SOI in a semiconductor device, since there is no current path to the substrate, the longitudinal path of the latch-up effect is cut off, and the latch-up effect can be eliminated.
  • the SOI device when a device structure with the same performance is realized on SOI and bulk silicon materials, the SOI device does not require additional process steps for manufacturing an isolation structure. Therefore, using SOI in a semiconductor device can simplify the manufacturing process.
  • the underlying silicon and the buried oxide layer are used to block metal pollutants generated by the pretreatment.
  • the bottom silicon and the buried oxide layer can serve as a protective layer to isolate the metal contamination generated by the pretreatment from the top silicon.
  • the manufacturing method of the semiconductor structure provided by the embodiment of the present disclosure can directly use SOI as the substrate of the semiconductor structure, which can reduce the difficulty of the technology of revealing the back hole, simplify the process of the technology of revealing the back hole and reduce the cost of the technology of revealing the back hole. While reducing the cost, the pollution of the conductive material to the substrate is reduced.
  • FIG. 4B is a schematic cross-sectional structure diagram of another semiconductor structure after the device layer is formed according to an embodiment of the present disclosure.
  • a device layer 404 is formed on the top silicon layer 403 , and a semiconductor device 405 is included in the device layer 404 .
  • the embodiment of the present disclosure does not illustrate the specific structure of the device layer, but only schematically shows that there is a semiconductor device in the layer, and the thickness ratio between the device layer and other material layers is not considered to be an important aspect of the present disclosure. The limitation of the thickness of the device layer.
  • the device layer includes transistor devices and capacitive devices.
  • the device layer includes a dielectric layer and transistor devices and capacitor devices formed in the dielectric layer.
  • FIG. 4C is a schematic cross-sectional structure diagram of another semiconductor structure after via holes are formed according to an embodiment of the present disclosure. As shown in FIG. 4C , a via hole 406 penetrating through the device layer 404 , the top silicon layer 403 and the buried oxide layer 402 and extending into the bottom silicon layer 401 is formed.
  • the forming a via hole that sequentially passes through the device layer, the top silicon layer, and the buried oxide layer, and extends into the bottom silicon layer includes: the via hole is located on the The pore diameter of the part in the buried oxide layer is greater than or equal to the pore diameter of the part of the through hole located in the top silicon layer; The diameter of the middle part.
  • the etching process parameters can be used, for example, prolonging the etching time, so that the aperture of the via hole located in the buried oxide layer is greater than or equal to the aperture of the via hole located in the top silicon layer, and the via hole located in the bottom silicon layer.
  • the diameter of the hole is greater than or equal to that of the portion of the through hole located in the buried oxide layer.
  • FIG. 5B is a schematic cross-sectional structure diagram of a through hole located in the bottom silicon layer, the buried oxide layer and the top silicon layer according to an embodiment of the present disclosure.
  • Figure 5B shows that the aperture W 2 of the part of the through hole located in the buried oxide layer is larger than the aperture W 3 ' of the part of the via hole located in the top silicon layer, and the aperture W 1 ' of the part of the via hole located in the bottom silicon layer is larger than that of the via hole located in the buried oxide layer.
  • FIG. 4D is a schematic cross-sectional structure diagram of another semiconductor structure after an isolation layer is formed in the via hole according to an embodiment of the present disclosure. As shown in FIG. 4D , an isolation layer 407 is deposited on the sidewall and bottom of the via hole.
  • FIG. 4E is a schematic cross-sectional structure diagram of another semiconductor structure after forming conductive pillars according to an embodiment of the present disclosure. As shown in FIG. 4E , the conductive material is continuously filled into the via holes to form conductive pillars 408 .
  • FIG. 4F is a schematic cross-sectional structure diagram of another semiconductor structure after forming an interconnection metal layer according to an embodiment of the present disclosure.
  • an interconnection layer (not shown in the figure) is formed on the device layer 404, and the interconnection layer is electrically connected to the conductive column; the interconnection layer includes interconnection vias and interconnection metal layer; the interconnect metal layer includes a top metal layer 409, the interconnect layer is electrically connected to the semiconductor device 405, and the top metal layer 409 is electrically connected to the conductive pillar.
  • FIG. 4G is a schematic cross-sectional structure diagram of another semiconductor structure after forming grooves according to an embodiment of the present disclosure.
  • an insulating layer 410 and a passivation layer 411 covering the interconnection layer are formed, and the passivation layer 411 and the insulating layer 410 are etched to form a groove 412 exposing the top metal layer 409 .
  • FIG. 4H is a schematic cross-sectional structure diagram of another semiconductor structure after the bump structure is formed according to an embodiment of the present disclosure.
  • a passivation layer 411 covers the upper surface of the insulating layer 410 , and a conductive material is deposited in the groove to form a bump structure 413 , and the bump structure 413 is electrically connected to the top metal layer 409 .
  • FIG. 4I is another schematic cross-sectional structure diagram after flipping the semiconductor structure forming the bump structure according to an embodiment of the present disclosure. As shown in FIG. 4I , the wafer on which the bump structure 413 has been formed is turned over.
  • FIG. 4J is a schematic cross-sectional structure diagram of another semiconductor structure exposing conductive pillars according to an embodiment of the present disclosure.
  • a bonding layer 414 covering the bump structure 413 is formed on the passivation layer 411, the semiconductor structure is bonded to the substrate 415 through the bonding layer 414, and the underlying silicon 401 is pretreated to expose the conductive Column 408.
  • the pretreatment may include, but not limited to, chemical mechanical polishing treatment.
  • the substrate (carrier) only provides support for the semiconductor structure, so as to facilitate the subsequent pretreatment of the underlying silicon.
  • the bottom silicon 401 and the buried oxide layer 402 can be used as a protective layer to separate the metal contamination 416 generated by the pretreatment from the top silicon 403. leave.
  • the manufacturing method of the semiconductor structure provided by the embodiment of the present disclosure can directly use SOI as the substrate of the semiconductor structure, which can not only reduce the difficulty of the backside hole exposure technology, simplify the process of the backside hole exposure technology, and reduce the cost of the backside hole exposure technology.
  • the cost can also reduce the contamination of the substrate by the conductive material.
  • an embodiment of the present disclosure also provides a semiconductor structure, including:
  • a substrate comprising a top layer of silicon 303 and a bottom layer of silicon 301;
  • the device layer 304 is located on the top layer silicon 303 of the substrate;
  • the through-silicon vias are disposed inside the substrate and penetrate through the substrate and the device layer 304 .
  • the underlying silicon 301 of the substrate is pretreated to expose the conductive pillars 308 to form TSVs.
  • the bottom silicon is pretreated to expose the conductive pillars, so that the bottom silicon can be used to block the pollution of the top silicon (ie, the silicon substrate) by the metal material produced by the pretreatment, and there is no need to set an additional protective layer for blocking the metal material from contaminating the top layer of silicon. Contamination of the silicon substrate, so as to achieve the purpose of simplifying the process steps of the hole exposure technology on the back side of the through-silicon via.
  • the grain size of the bottom silicon is smaller than the grain size of the top silicon.
  • the grain size of the bottom silicon is set to be smaller than that of the top silicon, the grains of the bottom silicon will be arranged more densely, so the bottom silicon will have a better effect of blocking metal pollutants, and can effectively prevent metal pollutants from being embedded in the bottom silicon, thereby protecting the top silicon from contamination by metallic materials.
  • the substrate further includes a buried oxide layer between the bottom silicon and the top silicon.
  • the underlying silicon and buried oxide layers are used to block metal contaminants generated by pretreatment.
  • the bottom silicon and the buried oxide layer can act as a protective layer to isolate the metal contamination generated by the pretreatment from the top silicon, thereby protecting the top silicon from contamination by metal materials.
  • the device layer includes transistor devices and capacitive devices.
  • it further includes: an interconnection layer located on the device layer, and the interconnection layer is electrically connected to the TSV; wherein the interconnection layer includes Interconnect vias and interconnect metal layers.
  • it also includes: a passivation layer and a bump structure formed in the passivation layer, the passivation layer is located on the interconnection layer; wherein, the bump structure and The interconnect layers are electrically connected.
  • the TSVs are filled with conductive materials.
  • the through-silicon vias are disposed inside the substrate and penetrate through the substrate and the device layer, including:
  • the diameter of the portion of the TSV located in the buried oxide layer is greater than or equal to the pore diameter of the portion of the TSV located in the top layer of silicon;
  • the diameter of the portion of the TSV located in the underlying silicon is greater than or equal to the diameter of the portion of the TSV located in the buried oxide layer.
  • the pore diameter of the TSV located in the buried oxide layer is greater than or equal to the pore diameter of the TSV located in the top silicon layer, and the pore diameter of the TSV located in the bottom silicon layer is greater than or equal to that of the TSV located in the buried oxide layer. aperture. Enlarging the part size of the through-silicon via in the underlying silicon can increase the contact area of the electrical connection between the conductive pillar and other semiconductor devices, so as to improve the effect of the electrical connection.
  • An embodiment of the present disclosure provides a semiconductor structure and a manufacturing method thereof.
  • the method includes: providing a substrate, the substrate including a top silicon layer and a bottom layer silicon; forming a device layer on the top silicon layer of the substrate; forming a device layer penetrating through the device layer. and the top layer of silicon and extending into the through hole of the bottom silicon; filling the through hole to form a conductive column to form a through silicon via; preprocessing the bottom silicon of the substrate to expose the conductive column; wherein , the underlying silicon is used to block metal pollutants generated by pretreatment.
  • the bottom-layer silicon is pretreated to expose the conductive pillars.
  • the underlying silicon blocks the contamination of the top layer of silicon (i.e., the silicon substrate) by the metal material produced by the pretreatment, and there is no need to set up an additional protective layer to prevent the contamination of the metal material to the silicon substrate, thereby simplifying the exposure of the back hole of the through-silicon via.
  • the bottom-layer silicon is pretreated to expose the conductive pillars.
  • the underlying silicon blocks the contamination of the top layer of silicon (i.e., the silicon substrate) by the metal material produced by the pretreatment, and there is no need to set up an additional protective layer to prevent the contamination of the metal material to the silicon substrate, thereby simplifying the exposure of the back hole of the through-silicon via.

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Abstract

本公开提供一种半导体结构及其制造方法，所述方法包括：提供基底，基底包括顶层硅和底层硅；在基底的顶层硅形成器件层；形成贯穿器件层和顶层硅并延伸进入底层硅的通孔；对通孔进行填充以形成导电柱；对基底的底层硅进行预处理，以暴露出导电柱形成硅通孔；其中，底层硅用于阻挡预处理产生的金属污染物。

Description

一种半导体结构及其制造方法
相关申请的交叉引用
本公开基于申请号为202111537812.6、申请日为2021年12月15日、发明名称为“一种半导体结构及其制造方法”的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此引入本公开作为参考。
技术领域
本公开实施例涉及半导体制造技术领域，尤其涉及一种半导体结构及其制造方法。
背景技术
穿硅通孔(Through Silicon Via，TSV)是一种贯穿硅基材的导体结构，其主要用于互连集成电路芯片。目前形成穿硅通孔的方法主要包括：在硅衬底的第一表面形成垂直于所述硅衬底的通孔；在所述通孔的侧壁和底部形成绝缘层；向所述通孔内填充导电材料；对所述硅衬底的与第一表面相对的第二表面进行化学机械研磨(Chemical Mechanical Polishing，CMP)，直至暴露出填充导电材料的通孔，即，形成穿硅通孔。
因此，如何改善穿硅通孔的背面孔洞显露(Backside Via Reveal，BVR)技术是目前亟待解决的问题。
发明内容
有鉴于此，本公开实施例为解决现有技术中存在的至少一个技术问题而提供一种半导体结构及其制造方法。
为达到上述目的，本公开的技术方案是这样实现的：
第一方面，本公开实施例提供一种半导体结构的制造方法，包括：
提供基底，所述基底包括顶层硅和底层硅；
在所述基底的顶层硅形成器件层；
形成贯穿所述器件层和所述顶层硅并延伸进入所述底层硅的通孔；
对所述通孔进行填充以形成导电柱；
对所述基底的底层硅进行预处理，以暴露出所述导电柱形成硅通孔；其中，所述底层硅用于阻挡预处理产生的金属污染物。
在本公开的一些实施例中，所述预处理包括研磨处理。
在本公开的一些实施例中，所述底层硅的晶粒尺寸小于所述顶层硅的晶粒尺寸。
在本公开的一些实施例中，所述顶层硅的厚度大于所述底层硅的厚度。
在本公开的一些实施例中，所述基底还包括位于所述底层硅和所述顶层硅之间的埋氧层；所述形成贯穿所述器件层和所述顶层硅并延伸进入所述底层硅的通孔，包括：
形成依次贯穿所述器件层、所述顶层硅和所述埋氧层，并延伸进入所述底层硅的通孔。
在本公开的一些实施例中，所述形成依次贯穿所述器件层、所述顶层硅和所述埋氧层，并延伸进入所述底层硅的通孔，包括：
所述通孔位于所述埋氧层中部分的孔径大于或等于所述通孔位于所述顶层硅中部分的孔径；
所述通孔位于所述底层硅中部分的孔径大于或等于所述通孔位于所述埋氧层中部分的孔径。
在本公开的一些实施例中，所述器件层包括晶体管器件和电容器件。
在本公开的一些实施例中，所述对所述基底的底层硅进行预处理之前，所述方法还包括：
在所述器件层上形成互连层，所述互连层与所述导电柱电连接；
其中，所述互连层包括互连通孔和互连金属层。
在本公开的一些实施例中，所述对所述基底的底层硅进行预处理之前，所述方法还包括：
形成覆盖所述互连层的钝化层，刻蚀所述钝化层以形成暴露所述互连层的凹槽；
在所述凹槽内形成凸点结构，所述凸点结构与所述互连层电连接。
第二方面，本公开实施例提供一种半导体结构，包括：
基底，所述基底包括顶层硅和底层硅；
器件层，所述器件层位于所述基底的顶层硅上；
硅通孔，所述硅通孔设置在所述基底内部，且贯穿所述基底及所述器件层。
在本公开的一些实施例中，所述底层硅的晶粒尺寸小于所述顶层硅的晶粒尺寸。
在本公开的一些实施例中，所述基底还包括位于所述底层硅和所述顶层硅之间的埋氧层。
在本公开的一些实施例中，所述器件层包括晶体管器件和电容器件。
在本公开的一些实施例中，还包括：
互连层，所述互连层位于所述器件层上，所述互连层与所述硅通孔电连接；
其中，所述互连层包括互连通孔和互连金属层。
在本公开的一些实施例中，还包括：
钝化层及形成在所述钝化层内的凸点结构，所述钝化层位于所述互连层上；
其中，所述凸点结构与所述互连层电连接。
在本公开的一些实施例中，所述硅通孔内填充有导电材料。
在本公开的一些实施例中，所述硅通孔设置在所述基底内部，且贯穿所述基底及所述器件层，包括：
所述硅通孔位于所述埋氧层中部分的孔径大于或等于所述硅通孔位于所述顶层硅中部分的孔径；
所述硅通孔位于所述底层硅中部分的孔径大于或等于所述硅通孔位于所述埋氧层中部分的孔径。
本公开实施例提供了一种半导体结构及其制造方法，所述方法包括：提供基底，所述基底包括顶层硅和底层硅；在所述基底的顶层硅形成器件层；形成贯穿所述器件层和所述顶层硅并延伸进入所述底层硅的通孔；对所述通孔进行填充以形成导电柱；对所述基底的底层硅进行预处理，以暴露出所述导电柱形成硅通孔；其中，所述底层硅用于阻挡预处理产生的金属污染物。本公开实施例提供的半导体结构的制造方法中，通过设置顶层硅和底层硅，在形成贯穿顶层硅并延伸进入底层硅的导电柱后，对底层硅进行预处理暴露出导电柱，如此能够利用底层硅阻挡预处理产生的金属材料对顶层硅(即，硅衬底)的污染，无需设置额外的保护层用于阻挡金属材料对硅衬底的污染，从而达到简化 硅通孔的背面孔洞显露技术的工艺步骤的目的。
附图说明
图1A为本公开实施例提供的形成硅通孔之后的半导体结构的剖面结构示意图；
图1B为本公开实施例提供的暴露出硅通孔末端的半导体结构的剖面结构示意图；
图1C为本公开实施例提供的形成氧化层和氮化硅层之后的半导体结构的剖面结构示意图；
图1D为本公开实施例提供的暴露出硅通孔内导电层的半导体结构的剖面结构示意图；
图2为本公开实施例提供的半导体结构的制造方法的一种可选的流程示意图；
图3A为本公开实施例提供的一种基底的剖面结构示意图；
图3B为本公开实施例提供的一种形成器件层之后的半导体结构的剖面结构示意图；
图3C为本公开实施例提供的一种形成通孔之后的半导体结构的剖面结构示意图；
图3D为本公开实施例提供的一种在通孔内形成隔离层之后的半导体结构的剖面结构示意图；
图3E为本公开实施例提供的一种形成导电柱之后的半导体结构的剖面结构示意图；
图3F为本公开实施例提供的一种形成互连金属层之后的半导体结构的剖面结构示意图；
图3G为本公开实施例提供的一种形成凹槽之后的半导体结构的剖面结构示意图；
图3H为本公开实施例提供的一种形成凸点结构之后的半导体结构的剖面结构示意图；
图3I为本公开实施例提供的一种将形成凸点结构的半导体结构翻转之后的剖面结构示意图；
图3J为本公开实施例提供的一种暴露出导电柱的半导体结构的剖面结构示意图；
图4A为本公开实施例提供的另一种基底的剖面结构示意图；
图4B为本公开实施例提供的另一种形成器件层之后的半导体结构的剖面结构示意图；
图4C为本公开实施例提供的另一种形成通孔之后的半导体结构的剖面结构示意图；
图4D为本公开实施例提供的另一种在通孔内形成隔离层之后的半导体结构的剖面结构示意图；
图4E为本公开实施例提供的另一种形成导电柱之后的半导体结构的剖面结构示意图；
图4F为本公开实施例提供的另一种形成互连金属层之后的半导体结构的剖面结构示意图；
图4G为本公开实施例提供的另一种形成凹槽之后的半导体结构的剖面结构示意图；
图4H为本公开实施例提供的另一种形成凸点结构之后的半导体结构的剖面结构示意图；
图4I为本公开实施例提供的另一种将形成凸点结构的半导体结构翻转之后的剖面结构示意图；
图4J为本公开实施例提供的另一种暴露出导电柱的半导体结构的剖面结构示意图；
图5A为本公开实施例提供的通孔位于底层硅和顶层硅内的剖面结构示意图；
图5B为本公开实施例提供的通孔位于底层硅、埋氧层和顶层硅内的剖面结构示意图；
图中包括：101-硅衬底；101a-第一表面；101b-第二表面；102-硅通孔；103-隔离层；104-导电层；105-氧化层；106-氮化硅层；301、401-底层硅；402-埋氧层；303、403-顶层硅；304、404-器件层；305、405-半导体器件；306、406-通孔；307、407-隔离层；308、408-导电柱；309、409-顶层金属层；310、410-绝缘层；311、411-钝化层；312、412-凹槽；313、413-凸点结构；414-键合层；415-基板；416-金属污染物；S 1-暴露出的硅通孔末端在垂直于硅衬底方向上的距离；W 1、W 1’-通孔位于底层硅中部分的孔径；W 2-通孔位于埋氧层中部分的孔径；W 3、W 3’-通孔位于顶层硅中部分的孔径。
具体实施方式
下面将结合本公开实施方式及附图，对本公开实施方式中的技术方案进行清楚、完整地描述，显然，所描述的实施方式仅仅是本公开的一部分实施方式，而不是全部的实施方式。基于本公开中的实施方式，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施方式，都属于本公开保护的范围。
在下文的描述中，给出了大量具体的细节以便提供对本公开更为彻底的理解。然而，对于本领域技术人员而言显而易见的是，本公开可以无需一个或多个这些细节而得以实施。在其他的例子中，为了避免与本公开发生混淆，对于本领域公知的一些技术特征未进行描述；即，这里不描述实际实施例的全部特征，不详细描述公知的功能和结构。
在附图中，为了清楚，层、区、元件的尺寸以及其相对尺寸可能被夸大。自始至终相同附图标记表示相同的元件。
应当明白，当元件或层被称为“在……上”、“与……相邻”、“连接到”或“耦合到”其它元件或层时，其可以直接地在其它元件或层上、与之相邻、连接或耦合到其它元件或层，或者可以存在居间的元件或层。相反，当元件被称为“直接在……上”、“与……直接相邻”、“直接连接到”或“直接耦合到”其它元件或层时，则不存在居间的元件或层。应当明白，尽管可使用术语第一、第二、第三等描述各种元件、部件、区、层和/或部分，这些元件、部件、区、层和/或部分不应当被这些术语限制。这些术语仅仅用来区分一个元件、部件、区、层或部分与另一个元件、部件、区、层或部分。因此，在不脱离本公开教导之下，下面讨论的第一元件、部件、区、层或部分可表示为第二元件、部件、区、层或部分。而当讨论的第二元件、部件、区、层或部分时，并不表明本公开必然存在第一元件、部件、区、层或部分。
空间关系术语例如“在……下”、“在……下面”、“下面的”、“在……之下”、“在……之上”、“上面的”等，在这里可为了方便描述而被使用从而描述图中所示的一个元件或特征与其它元件或特征的关系。应当明白，除了图中所示的取向以外，空间关系术语意图还包括使用和操作中的器件的不同取向。例如，如果附图中的器件翻转，然后，描述为“在其它元件下面”或“在其之下”或“在其下”元件或特征将取向为在其它元件或特征“上”。因此，示例性术语“在……下面”和“在……下”可包括上和下两个取向。器件可以另外地取向(旋转90度或其它取向)并且在此使用的空间描述语相应地被解释。
在此使用的术语的目的仅在于描述具体实施例并且不作为本公开的限制。在此使用时，单数形式的“一”、“一个”和“所述/该”也意图包括复数形式，除非上下文清楚指出另外的方式。还应明白术语“组成”和/或“包括”，当在该说明书中使用时，确定所述特征、整数、步骤、操作、元件和/或部件的存在，但不排除一个或更多其它的特征、整数、步骤、操作、元件、部件和/或组的存在或添加。在此使用时，术语“和/或”包括相关所列项目的任何及所有组合。
为了彻底理解本公开，将在下列的描述中提出详细的步骤以及详细的结构，以便阐释本公开的技术方案。本公开的较佳实施例详细描述如下，然而除了这些详细描述外，本公开还可以具有其他实施方式。
如前所述，目前形成穿硅通孔的方法主要包括：在硅衬底的正面形成垂直于所述硅衬底的通孔；在所述通孔的侧壁和底部形成绝缘层；对所述硅衬底的背面进行化学机械研磨，直至暴露出填充导电材料的通孔，即，形成穿硅通孔。
这里，对所述硅衬底的背面进行研磨以暴露出填充导电材料的通孔的过程中，通孔内填充的导电材料，例如，铜，极可能会污染硅衬底。因此，如何改善穿硅通孔的背面孔洞显露技术，以及减少金属材料对硅衬底的污染是目前亟待解决的问题。
参考图1A，图1A为本公开实施例提供的形成硅通孔之后的半导体结构的剖面结构示意图。如图1A所示，硅通孔102由硅衬底101的第一表面101a延伸进入硅衬底101内，硅通孔102未贯穿硅衬底101。刻蚀形成硅通孔102的方向垂直于硅衬底101，刻蚀形成硅通孔102后，在硅通孔内的侧壁和底部沉积隔离材料，以形成隔离层103；然后，向硅通孔102内沉积导电材料，以形成导电层104。这里，硅衬底101具有第一表面101a，以及与第一表面101a相对的第二表面101b。具体而言，第一表面可为硅衬底的正面，第二表面可为硅衬底的背面。
在本公开的一些实施例中，在硅通孔内沉积形成隔离层和导电层，可以通过一种或多种沉积工艺来实现。其中，沉积工艺包括但不限于物理气相沉积(Physical Vapor Deposition，PVD)、化学气相沉积(Chemical Vapor Deposition，CVD)、原子层沉积(Atomic Layer Deposition，ALD)或者其任何组合。
在本公开的一些实施例中，隔离层可以包括氧化物层，例如，二氧化硅层；导电层可以包括金属层，例如，铜层。
参考图1B，图1B为本公开实施例提供的暴露出硅通孔末端的半导体结构的剖面结构示意图。从硅衬底的第二表面101b，沿垂直于硅衬底101的方向，对硅衬底进行背面减薄(backside grinding)，以暴露出硅通孔末端或者从硅衬底的第二表面101b，对硅衬底101进行刻蚀，以暴露出硅通孔末端。
在本公开的一个具体实施例中，对硅衬底进行背面减薄，硅衬底的减薄厚度约为20μm。这里可以参考图1B，对硅衬底进行背面减薄后，暴露出硅通孔末端。
在本公开的一个具体实施例中，还可以从硅衬底的第二表面，对硅衬底进行干法刻蚀，以暴露出硅通孔末端。这里，暴露出的硅通孔末端在垂直于硅衬底方向上的距离可以约为6.5μm。这里可以参考图1B，对硅衬底进行干法刻蚀后，暴露出硅通孔末端，暴露出的硅通孔末端在垂直于硅衬底方向上的距离S 1，S 1可约为6.5μm。
参考图1C，图1C为本公开实施例提供的形成氧化层和氮化硅层之后的半导体结构的剖面结构示意图。如图1C所示，在硅衬底101的第二表面沉积形成氧化层105，氧化层105覆盖硅衬底101的第二表面和硅通孔末端。在氧化层105上沉积形成氮化硅层106，氮化硅层106完全覆盖氧化层105。
在本公开的一些实施例中，在硅衬底的第二表面形成氧化层，和在氧化层上形成氮化硅层，可以通过一种或多种沉积工艺来实现。其中，沉积工艺包括但不限于物理气相沉积、化学气相沉积、原子层沉积或者其任何组合。
在本公开的一个具体实施例中，形成覆盖硅衬底的第二表面和硅通孔末端的氧化层的厚度约为1.85μm。
在本公开的一个具体实施例中，形成覆盖氧化层的氮化硅层的厚度约为0.3μm。
参考图1D，图1D为本公开实施例提供的暴露出硅通孔内导电层的半导体结构的剖面结构示意图。如图1D所示，从硅衬底101的第二表面，使用化学机械研磨去除硅通 孔末端的隔离层103，以暴露出硅通孔末端的导电层104。
上述技术方案中，通过在硅通孔的末端依次形成氧化层和氮化硅层，能够有效地改善后续使用化学机械研磨以暴露出硅通孔末端的导电层的过程中，导电层的材料对硅衬底的污染。这里，覆盖硅通孔末端的氧化层和氮化硅层可以作为保护层，将研磨产生的导电层的材料污染物，例如，金属污染物，隔离在氮化硅层或者氧化层的表面上。
然而，上述硅通孔的背面孔洞显露的技术方案中，需要在形成硅通孔后，增加额外的工艺步骤以形成氧化层和氮化硅层作为保护层。因此，该技术方案增加了硅通孔的背面孔洞显露技术的工艺难度、增加了工艺成本以及将工艺制程复杂化。
有鉴于此，本公开实施例提供一种半导体结构的制造方法，通过设置顶层硅和底层硅，在形成贯穿顶层硅并延伸进入底层硅的导电柱后，对底层硅进行预处理暴露出导电柱，在减小工艺难度和降低工艺成本的同时，还能够利用底层硅阻挡预处理产生的金属污染物。
参考图2，图2为本公开实施例提供的半导体结构的制造方法的一种可选的流程示意图。如图2所示，本公开实施例提供的半导体结构的制造方法，所述方法包括：
步骤S201、提供基底，所述基底包括顶层硅和底层硅；
步骤S202、在所述基底的顶层硅形成器件层；
步骤S203、形成贯穿所述器件层和所述顶层硅并延伸进入所述底层硅的通孔；
步骤S204、对所述通孔进行填充以形成导电柱；
步骤S205、对所述基底的底层硅进行预处理，以暴露出所述导电柱形成硅通孔；其中，所述底层硅用于阻挡预处理产生的金属污染物。
接下来对本公开实施例提供的半导体结构的制造方法进行进一步地详细说明。
参考图3A，图3A为本公开实施例提供的一种基底的剖面结构示意图。如图3A所示，基底包括底层硅301和顶层硅303。
在本公开的一些实施例中，所述顶层硅的厚度大于所述底层硅的厚度。
这里，对底层硅进行预处理以暴露出导电柱的过程中，设置底层硅用于阻挡预处理产生的金属污染物。在对底层硅进行预处理暴露出导电柱之后，底层硅可以作为保护层，将预处理产生的金属污染物与顶层硅之间隔离开。因此，底层硅的厚度可以小于顶层硅的厚度。此后，也可以去除底层硅。
在本公开的一些实施例中，所述底层硅的晶粒尺寸小于所述顶层硅的晶粒尺寸。
如前所述，设置底层硅用于阻挡预处理产生的金属污染物。因此，设置底层硅的晶粒尺寸小于顶层硅的晶粒尺寸，底层硅的晶粒排列会更加致密，那么底层硅用于阻挡金属污染物的效果更好，能够有效地避免金属污染物嵌入到底层硅中。
参考图3B，图3B为本公开实施例提供的一种形成器件层之后的半导体结构的剖面结构示意图。如图3B所示，在顶层硅303上形成器件层304，器件层304中包括有半导体器件305。需要说明的是，本公开实施例中并未示意出器件层的具体结构，仅示意性的示意出该层中具有半导体器件，且该器件层与其他材料层的厚度比例也不视为对本公开中器件层厚度的限定。
在本公开的一些实施例中，所述器件层包括晶体管器件和电容器件。器件层包括介质层和形成在介质层中的晶体管器件和电容器件。
这里，在器件层内形成的半导体器件可以包括晶体管器件和电容器件。晶体管器件可以包括一个或者多个金属氧化物半导体场效应晶体管(Metal-Oxide-Semiconductor Field-Effect Transistor，MOSFET)。晶体管可以包括平面晶体管、非平面晶体管或者二者的组合。平面晶体管可以包括双极结型晶体管(Bipolar Junction Transistor，BJT)、异质结双极晶体管(Heterojunction Bipolar Transistor，HBT)或者高电子迁移率晶体管(High  Electron Mobility Transistor，HEMT)。非平面晶体管可以包括鳍式场效应晶体管(Fin Field-Effect Transistor，FinFET)(例如，双栅极晶体管或者三栅极晶体管)、以及环绕或者全环栅极晶体管(例如，纳米带和纳米线晶体管)。
本公开实施例中形成半导体器件的过程涉及半导体制造工艺中的前段制程(front end of line，FEOL)。
参考图3C，图3C为本公开实施例提供的一种形成通孔之后的半导体结构的剖面结构示意图。如图3C所示，形成贯穿器件层304和顶层硅303并延伸进入底层硅301的通孔306。
本公开实施例可以使用湿法刻蚀、干法刻蚀或者其组合对器件层、顶层硅和底层硅进行刻蚀以形成通孔。
本公开实施例中，可以在器件层上形成图案化的光刻胶层，使用图案化的光刻胶层依次对器件层、顶层硅和底层硅进行刻蚀(etch)，以形成贯穿器件层和顶层硅并延伸进入底层硅的通孔。在形成通孔之后，可以去除光刻胶，即光刻胶剥离(photoresist strip，PR strip)。
在本公开的一些实施例中，所述形成贯穿器件层和顶层硅并延伸进入底层硅的通孔，包括：所述通孔位于所述底层硅中部分的孔径大于或等于所述通孔位于所述顶层硅中部分的孔径。
这里，可以通过刻蚀的工艺参数，例如，延长刻蚀时间，使得通孔位于底层硅中部分的孔径大于或等于通孔位于顶层硅中部分的孔径。这样对通孔进行填充形成导电柱之后，导电柱位于底层硅中部分的尺寸大于或等于导电柱位于顶层硅中部分的尺寸。对底层硅进行预处理暴露出导电柱之后，位于底层硅中部分导电柱将用于实现电连接。因此，增大导电柱位于底层硅中的部分尺寸，能够增大导电柱与其他半导体器件之间的电连接的接触面积，以改善电连接的效果。
仍参考图3C，图3C示出的通孔位于底层硅中部分的孔径等于通孔位于顶层硅中部分的孔径。参考图5A，图5A为本公开实施例提供的通孔位于底层硅和顶层硅内的剖面结构示意图。图5A示出的通孔位于底层硅中部分的孔径W 1大于通孔位于顶层硅中部分的孔径W 3。如此对通孔填充形成导电柱之后，导电柱位于底层硅中部分的尺寸大于或等于导电柱位于顶层硅中部分的尺寸。
参考图3D，图3D为本公开实施例提供的一种在通孔内形成隔离层之后的半导体结构的剖面结构示意图。如图3D所示，在通孔的侧壁和底部沉积形成隔离层307。
本公开实施例中，在通孔内沉积形成隔离层，可以通过一种或多种沉积工艺来实现。其中，沉积工艺包括但不限于物理气相沉积、化学气相沉积、原子层沉积或者其任何组合。本公开实施例中，还可以使用线型沉积源(liner deposition)，在通孔内沉积形成隔离层。
参考图3E，图3E为本公开实施例提供的一种形成导电柱之后的半导体结构的剖面结构示意图。如图3E所示，向通孔内继续填充导电材料，以形成导电柱308。
本公开实施例中，可以使用包括但不限于真空蒸镀、溅射镀膜(sputtering plating)、离子镀等方法，在通孔内沉积形成导电柱。在形成导电柱之后，还可以使用化学机械研磨，去除多余的导电材料，使得导电柱的上表面与器件层的上表面齐平。
本公开实施例中，形成导电柱的导电材料可以包括但不限于金属材料。在本公开的一实施例中，形成导电柱的材料例如为铜。
参考图3F，图3F为本公开实施例提供的一种形成互连金属层之后的半导体结构的剖面结构示意图。如图3F所示，在器件层304上形成互连层(图中未示出)，所述互连层与所述导电柱电连接；所述互连层包括互连通孔(via)和互连金属层(metal)；互连 金属层包括顶层金属层309，互连层与半导体器件305电连接，且顶层金属层309与导电柱电连接。
本公开一些实施例中，在器件层上沉积形成介质层，进而在介质层上形成图案化的光刻胶层，使用所述图案化的光刻胶层对介质层进行刻蚀，以形成顶层金属层的图案，填充进行材料，形成顶层金属层309。这里，介质层的材料可以为二氧化硅。
本公开另一些实施例中，在器件层上沉积形成金属材料层，进而在所述金属材料层上形成图案化的光刻胶层，使用所述图案化的光刻胶层对所述金属材料层进行刻蚀，以形成顶层金属层。
参考图3G，图3G为本公开实施例提供的一种形成凹槽之后的半导体结构的剖面结构示意图。如图3G所示，形成覆盖互连层的绝缘层310和钝化层311，对钝化层311和绝缘层310进行刻蚀，以形成暴露出顶层金属层309的凹槽312。
在本公开的一些实施例中，形成绝缘层的材料可以为二氧化硅。
在本公开的一些实施例中，沉积形成钝化层(passivation layer，PAS layer)的材料可以包括但不限于氮化硅。
参考图3H，图3H为本公开实施例提供的一种形成凸点结构之后的半导体结构的剖面结构示意图。如图3H所示，钝化层311覆盖绝缘层310的上表面，在凹槽内沉积导电材料以形成凸点结构313，凸点结构313与顶层金属层309电连接。
在本公开的一些实施例中，沉积形成凸点结构的导电材料可以包括但不限于金属材料。例如，形成凸点结构的导电材料可以为铜。
参考图3I，图3I为本公开实施例提供的一种将形成凸点结构的半导体结构翻转之后的剖面结构示意图。如图3I所示，将已经形成凸点结构的晶圆翻转(wafer flip)过来。
参考图3J，图3J为本公开实施例提供的一种暴露出导电柱的半导体结构的剖面结构示意图。如图3J所示，对底层硅301进行预处理，去除导电柱308末端的隔离层307，以暴露出导电柱308。当然，在预处理以去除隔离层的过程中，不可避免地会去除部分导电柱的材料。这里，预处理可以包括但不限于化学机械研磨处理。
这里，在对底层硅进行预处理暴露出导电柱之后，底层硅可以作为保护层，将预处理产生的金属污染物与顶层硅之间隔离开。
本公开实施例提供的半导体结构的制造方法中，通过设置顶层硅和底层硅，在形成贯穿顶层硅并延伸进入底层硅的导电柱后，对底层硅进行预处理暴露出导电柱，无需增加额外的工艺步骤，利用底层硅即可阻挡预处理产生的金属污染物，有效防止金属污染物对顶层硅的污染。本公开实施例提供的半导体结构的制造方法，在减小工艺难度和降低工艺成本的同时，还能够减小金属污染物对硅衬底(顶层硅)的污染。
接下来对本公开另一实施例提供的半导体结构的制造方法进行进一步地详细说明。
参考图4A，图4A为本公开实施例提供的另一种基底的剖面结构示意图。如图4A所示，基底包括底层硅401和顶层硅403，以及位于底层硅401和顶层硅403之间的埋氧层402。
这里，基底可以包括绝缘体衬底上的硅(Silicon-On-Insulator，SOI)，即在两层硅材料之间设置一层氧化材料层。在半导体器件中使用SOI具有多种优势，例如包括：减小寄生电容，提高运行速度；降低功耗；消除闩锁效应；抑制基底中脉冲电流干扰，减小软错误的发生；以及与现有的硅工艺兼容，可减少13％至20％的工序。
具体地，N型金属-氧化物-半导体(N-Metal-Oxide-Semiconductor，NMOS)和P型金属-氧化物-半导体(P-Metal-Oxide-Semiconductor，PMOS)的源漏扩散区与衬底之间的寄生电容随着衬底的掺杂浓度线性变化。随着半导体器件的尺寸不断减小，为了减小短沟道效应，衬底的掺杂浓度必须适当提高，源漏结电容随之增大，源漏结和沟道阻断 区之间的寄生电容随之增加。寄生电容增加不仅会降低电路运行速度，还会增加电路的功耗。在SOI中，源漏结与衬底之间的寄生电容是隐埋的绝缘体电容，该电容正比于埋氧层的介电常数，埋氧层二氧化硅的介电常数仅为硅的三分之一。而且随着半导体器件的尺寸不断减小，埋氧层的厚度不需要按比例缩小，寄生电容不会增加。因此，在半导体器件中使用SOI能够减小寄生电容、提高运行速度以及降低功耗。
具体地，在SOI中，各器件均被氧化层包围，完全与周围的器件隔离，消除了闩锁效应。因此，在半导体器件中使用SOI，由于没有到衬底的电流通道，闩锁效应的纵向通路被切断，能够消除闩锁效应。
具体地，在SOI和体硅材料上实现相同性能的器件结构时，SOI器件不需要额外的制造隔离结构的工艺步骤。因此，在半导体器件中使用SOI，能够简化制造工艺。
这里，对底层硅进行预处理以暴露出导电柱的过程中，设置底层硅和埋氧层用于阻挡预处理产生的金属污染物。在对底层硅进行预处理暴露出导电柱之后，底层硅和埋氧层可以作为保护层，将预处理产生的金属污染物与顶层硅之间隔离开。
因此，本公开实施例提供的半导体结构的制造方法，能够直接使用SOI作为半导体结构的衬底，可以在减小背面孔洞显露技术的难度、简化背面孔洞显露技术的工序和降低背面孔洞显露技术的成本的同时，减小导电材料对衬底的污染。
参考图4B，图4B为本公开实施例提供的另一种形成器件层之后的半导体结构的剖面结构示意图。如图4B所示，在顶层硅403上形成器件层404，器件层404中包括有半导体器件405。需要说明的是，本公开实施例中并未示意出器件层的具体结构，仅示意性的示意出该层中具有半导体器件，且该器件层与其他材料层的厚度比例也不视为对本公开中器件层厚度的限定。
在本公开的一些实施例中，所述器件层包括晶体管器件和电容器件。器件层包括介质层和形成在介质层中的晶体管器件和电容器件。
参考图4C，图4C为本公开实施例提供的另一种形成通孔之后的半导体结构的剖面结构示意图。如图4C所示，形成贯穿器件层404、顶层硅403和埋氧层402，并延伸进入底层硅401的通孔406。
在本公开的一些实施例中，所述形成依次贯穿所述器件层、所述顶层硅和所述埋氧层，并延伸进入所述底层硅的通孔，包括：所述通孔位于所述埋氧层中部分的孔径大于或等于所述通孔位于所述顶层硅中部分的孔径；所述通孔位于所述底层硅中部分的孔径大于或等于所述通孔位于所述埋氧层中部分的孔径。
这里，可以通过刻蚀的工艺参数，例如，延长刻蚀时间，使得通孔位于埋氧层中部分的孔径大于或等于通孔位于顶层硅中部分的孔径，且通孔位于底层硅中部分的孔径大于或等于通孔位于埋氧层中部分的孔径。这样对通孔进行填充形成导电柱之后，导电柱位于底层硅中部分的尺寸大于或等于导电柱位于顶层硅中部分的尺寸。对底层硅进行预处理暴露出导电柱之后，位于底层硅中部分导电柱将用于实现电连接。因此，增大导电柱位于底层硅中的部分尺寸，能够增大导电柱与其他半导体器件之间的电连接的接触面积，以改善电连接的效果。
仍参考图4C，图4C示出的通孔位于埋氧层中部分的孔径等于通孔位于顶层硅中部分的孔径；通孔位于底层硅中部分的孔径等于通孔位于埋氧层中部分的孔径。参考图5B，图5B为本公开实施例提供的通孔位于底层硅、埋氧层和顶层硅内的剖面结构示意图。图5B示出的通孔位于埋氧层中部分的孔径W 2大于通孔位于顶层硅中部分的孔径W 3’，通孔位于底层硅中部分的孔径W 1’大于通孔位于埋氧层中部分的孔径W 2。如此对通孔填充形成导电柱之后，导电柱位于底层硅中部分的尺寸大于导电柱位于顶层硅中部分的尺寸。
参考图4D，图4D为本公开实施例提供的另一种在通孔内形成隔离层之后的半导体结构的剖面结构示意图。如图4D所示，在通孔的侧壁和底部沉积形成隔离层407。
参考图4E，图4E为本公开实施例提供的另一种形成导电柱之后的半导体结构的剖面结构示意图。如图4E所示，向通孔内继续填充导电材料，以形成导电柱408。
参考图4F，图4F为本公开实施例提供的另一种形成互连金属层之后的半导体结构的剖面结构示意图。如图4F所示，在器件层404上形成互连层(图中未示出)，所述互连层与所述导电柱电连接；所述互连层包括互连通孔和互连金属层；互连金属层包括顶层金属层409，互连层与半导体器件405电连接，且顶层金属层409与导电柱电连接。
参考图4G，图4G为本公开实施例提供的另一种形成凹槽之后的半导体结构的剖面结构示意图。如图4G所示，形成覆盖互连层的绝缘层410和钝化层411，对钝化层411和绝缘层410进行刻蚀，以形成暴露出顶层金属层409的凹槽412。
参考图4H，图4H为本公开实施例提供的另一种形成凸点结构之后的半导体结构的剖面结构示意图。如图4H所示，钝化层411覆盖绝缘层410的上表面，在凹槽内沉积导电材料以形成凸点结构413，凸点结构413与顶层金属层409电连接。
参考图4I，图4I为本公开实施例提供的另一种将形成凸点结构的半导体结构翻转之后的剖面结构示意图。如图4I所示，将已经形成凸点结构413的晶圆翻转过来。
参考图4J，图4J为本公开实施例提供的另一种暴露出导电柱的半导体结构的剖面结构示意图。如图4J所示，在钝化层411上形成覆盖凸点结构413的键合层414，半导体结构通过键合层414与基板415进行键合，对底层硅401进行预处理，以暴露出导电柱408。当然，在预处理以去除隔离层的过程中，不可避免地会去除部分导电柱的材料。这里，预处理可以包括但不限于化学机械研磨处理。其中，基板(carrier)仅仅为半导体结构提供支撑作用，以便于后续对底层硅进行预处理。
这里，仍参考图4J，在对底层硅401进行预处理暴露出导电柱408之后，底层硅401和埋氧层402可以作为保护层，将预处理产生的金属污染物416与顶层硅403之间隔离开。
因此，本公开实施例提供的半导体结构的制造方法，能够直接使用SOI作为半导体结构的衬底，不仅可以减小背面孔洞显露技术的难度、简化背面孔洞显露技术的工序和降低背面孔洞显露技术的成本，还可以减小导电材料对衬底的污染。
仍参考图3J，本公开实施例还提供一种半导体结构，包括：
基底，所述基底包括顶层硅303和底层硅301；
器件层304，器件层304位于所述基底的顶层硅303上；
硅通孔，所述硅通孔设置在所述基底内部，且贯穿所述基底及器件层304。
这里，形成导电柱308之后，对所述基底的底层硅301进行预处理，以暴露出导电柱308形成硅通孔。
这里，对底层硅进行预处理暴露出导电柱，如此能够利用底层硅阻挡预处理产生的金属材料对顶层硅(即，硅衬底)的污染，无需设置额外的保护层用于阻挡金属材料对硅衬底的污染，从而达到简化硅通孔的背面孔洞显露技术的工艺步骤目的。
在本公开的一些实施例中，所述底层硅的晶粒尺寸小于所述顶层硅的晶粒尺寸。
这里，设置底层硅的晶粒尺寸小于顶层硅的晶粒尺寸，底层硅的晶粒排列会更加致密，那么底层硅用于阻挡金属污染物的效果更好，能够有效地避免金属污染物嵌入到底层硅中，从而保护顶层硅免受金属材料的污染。
在本公开的一些实施例中，所述基底还包括位于所述底层硅和所述顶层硅之间的埋氧层。
这里，设置底层硅和埋氧层用于阻挡预处理产生的金属污染物。在对底层硅进行预 处理暴露出导电柱之后，底层硅和埋氧层可以作为保护层，将预处理产生的金属污染物与顶层硅之间隔离开，从而保护顶层硅免受金属材料的污染。
在本公开的一些实施例中，所述器件层包括晶体管器件和电容器件。
在本公开的一些实施例中，还包括：互连层，所述互连层位于所述器件层上，所述互连层与所述硅通孔电连接；其中，所述互连层包括互连通孔和互连金属层。
在本公开的一些实施例中，还包括：钝化层及形成在所述钝化层内的凸点结构，所述钝化层位于所述互连层上；其中，所述凸点结构与所述互连层电连接。
在本公开的一些实施例中，所述硅通孔内填充有导电材料。
在本公开的一些实施例中，所述硅通孔设置在所述基底内部，且贯穿所述基底及所述器件层，包括：
所述硅通孔位于所述埋氧层中部分的孔径大于或等于所述硅通孔位于所述顶层硅中部分的孔径；
所述硅通孔位于所述底层硅中部分的孔径大于或等于所述硅通孔位于所述埋氧层中部分的孔径。
这里，硅通孔位于埋氧层中部分的孔径大于或等于硅通孔位于顶层硅中部分的孔径，硅通孔位于底层硅中部分的孔径大于或等于硅通孔位于埋氧层中部分的孔径。如此增大硅通孔位于底层硅中的部分尺寸，能够增大导电柱与其他半导体器件之间的电连接的接触面积，以改善电连接的效果。
本公开实施例提供了一种半导体结构及其制造方法，所述方法包括：提供基底，所述基底包括顶层硅和底层硅；在所述基底的顶层硅形成器件层；形成贯穿所述器件层和顶层硅并延伸进入所述底层硅的通孔；对所述通孔进行填充以形成导电柱形成硅通孔；对所述基底的底层硅进行预处理，以暴露出所述导电柱；其中，所述底层硅用于阻挡预处理产生的金属污染物。本公开实施例提供的半导体结构的制造方法中，通过设置顶层硅和底层硅，在形成贯穿顶层硅并延伸进入底层硅的导电柱后，对底层硅进行预处理暴露出导电柱，如此能够利用底层硅阻挡预处理产生的金属材料对顶层硅(即，硅衬底)的污染，无需设置额外的保护层用于阻挡金属材料对硅衬底的污染，从而达到简化硅通孔的背面孔洞显露技术的工艺步骤的目的。
应理解，说明书通篇中提到的“一个实施例”或“一实施例”意味着与实施例有关的特定特征、结构或特性包括在本公开的至少一个实施例中。因此，在整个说明书各处出现的“在一个实施例中”或“在一实施例中”未必一定指相同的实施例。此外，这些特定的特征、结构或特性可以任意适合的方式结合在一个或多个实施例中。应理解，在本公开的各种实施例中，上述各过程的序号的大小并不意味着执行顺序的先后，各过程的执行顺序应以其功能和内在逻辑确定，而不应对本公开实施例的实施过程构成任何限定。上述本公开实施例序号仅仅为了描述，不代表实施例的优劣。
以上所述仅为本公开的优选实施方式，并非因此限制本公开的专利范围，凡是在本公开的发明构思下，利用本公开说明书及附图内容所作的等效结构变换，或直接/间接运用在其他相关的技术领域均包括在本公开的专利保护范围内。
工业实用性
本公开实施例提供的半导体结构的制造方法中，通过设置顶层硅和底层硅，在形成贯穿顶层硅并延伸进入底层硅的导电柱后，对底层硅进行预处理暴露出导电柱，如此能够利用底层硅阻挡预处理产生的金属材料对顶层硅(即，硅衬底)的污染，无需设置额外的保护层用于阻挡金属材料对硅衬底的污染，从而达到简化硅通孔的背面孔洞显露技 术的工艺步骤的目的。

Claims (17)

  1. 一种半导体结构的制造方法，包括：
    提供基底，所述基底包括顶层硅和底层硅；
    在所述基底的顶层硅形成器件层；
    形成贯穿所述器件层和所述顶层硅并延伸进入所述底层硅的通孔；
    对所述通孔进行填充以形成导电柱；
    对所述基底的底层硅进行预处理，以暴露出所述导电柱形成硅通孔；其中，所述底层硅用于阻挡预处理产生的金属污染物。
  2. 如权利要求1所述的制造方法，其中，所述预处理包括研磨处理。
  3. 如权利要求1所述的制造方法，其中，所述底层硅的晶粒尺寸小于所述顶层硅的晶粒尺寸。
  4. 如权利要求1所述的制造方法，其中，所述顶层硅的厚度大于所述底层硅的厚度。
  5. 如权利要求1所述的制造方法，其中，所述基底还包括位于所述底层硅和所述顶层硅之间的埋氧层；所述形成贯穿所述器件层和所述顶层硅并延伸进入所述底层硅的通孔，包括：
    形成依次贯穿所述器件层、所述顶层硅和所述埋氧层，并延伸进入所述底层硅的通孔。
  6. 如权利要求5所述的制造方法，其中，所述形成依次贯穿所述器件层、所述顶层硅和所述埋氧层，并延伸进入所述底层硅的通孔，包括：
    所述通孔位于所述埋氧层中部分的孔径大于或等于所述通孔位于所述顶层硅中部分的孔径；
    所述通孔位于所述底层硅中部分的孔径大于或等于所述通孔位于所述埋氧层中部分的孔径。
  7. 如权利要求1所述的制造方法，其中，所述器件层包括晶体管器件和电容器件。
  8. 如权利要求1所述的制造方法，其中，所述对所述基底的底层硅进行预处理之前，所述方法还包括：
    在所述器件层上形成互连层，所述互连层与所述导电柱电连接；
    其中，所述互连层包括互连通孔和互连金属层。
  9. 如权利要求8所述的制造方法，其中，所述对所述基底的底层硅进行预处理之前，所述方法还包括：
    形成覆盖所述互连层的钝化层，刻蚀所述钝化层以形成暴露所述互连层的凹槽；
    在所述凹槽内形成凸点结构，所述凸点结构与所述互连层电连接。
  10. 一种半导体结构，包括：
    基底，所述基底包括顶层硅和底层硅；
    器件层，所述器件层位于所述基底的顶层硅上；
    硅通孔，所述硅通孔设置在所述基底内部，且贯穿所述基底及所述器件层。
  11. 如权利要求10所述的半导体结构，其中，所述底层硅的晶粒尺寸小于所述顶层硅的晶粒尺寸。
  12. 如权利要求10所述的半导体结构，其中，
    所述基底还包括位于所述底层硅和所述顶层硅之间的埋氧层。
  13. 如权利要求10所述的半导体结构，其中，所述器件层包括晶体管器件和电容 器件。
  14. 如权利要求10所述的半导体结构，其中，还包括：
    互连层，所述互连层位于所述器件层上，所述互连层与所述硅通孔电连接；
    其中，所述互连层包括互连通孔和互连金属层。
  15. 如权利要求14所述的半导体结构，其中，还包括：
    钝化层及形成在所述钝化层内的凸点结构，所述钝化层位于所述互连层上；
    其中，所述凸点结构与所述互连层电连接。
  16. 如权利要求10所述的半导体结构，其中，所述硅通孔内填充有导电材料。
  17. 如权利要求12所述的半导体结构，其中，所述硅通孔设置在所述基底内部，且贯穿所述基底及所述器件层，包括：
    所述硅通孔位于所述埋氧层中部分的孔径大于或等于所述硅通孔位于所述顶层硅中部分的孔径；
    所述硅通孔位于所述底层硅中部分的孔径大于或等于所述硅通孔位于所述埋氧层中部分的孔径。
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