WO2023108829A1 - 一种测试头掉电前信息收集设备及其收集方法 - Google Patents

一种测试头掉电前信息收集设备及其收集方法 Download PDF

Info

Publication number
WO2023108829A1
WO2023108829A1 PCT/CN2021/143488 CN2021143488W WO2023108829A1 WO 2023108829 A1 WO2023108829 A1 WO 2023108829A1 CN 2021143488 W CN2021143488 W CN 2021143488W WO 2023108829 A1 WO2023108829 A1 WO 2023108829A1
Authority
WO
WIPO (PCT)
Prior art keywords
test
module
interrupt
voltage threshold
cpu
Prior art date
Application number
PCT/CN2021/143488
Other languages
English (en)
French (fr)
Inventor
徐波波
Original Assignee
上海御渡半导体科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 上海御渡半导体科技有限公司 filed Critical 上海御渡半导体科技有限公司
Publication of WO2023108829A1 publication Critical patent/WO2023108829A1/zh

Links

Images

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/26—Testing of individual semiconductor devices

Definitions

  • the invention relates to the field of semiconductor automatic test equipment (Automatic Test Equipment, referred to as ATE), in particular to an information collection device and a collection method thereof before a test head is powered off.
  • ATE Automatic Test Equipment
  • a test head is directly connected to a wafer under test or a chip under test. Whether it is a wafer/chip under test or a test head, the cost is relatively expensive.
  • FIG. 1 is a schematic diagram of a test head structure of a semiconductor automatic test equipment in the prior art.
  • N boards board 1, board 2... board N
  • DUT Device Under Test
  • each single board includes a central processing module CPU, a test module, a storage module and a hard disk (HDD).
  • the central processing module controls the test module to test the DUT of the customer's device under test, and sends the test result back to the corresponding board, and stores it through the storage module.
  • the semiconductor automatic test equipment During the test, if the test head encounters some abnormal conditions or environmental faults, etc., usually the semiconductor automatic test equipment will be powered off urgently. Although the emergency power-off of semiconductor automatic test equipment is an occasional event with a small probability, such an emergency will cause the ATE test to be interrupted forcibly, and the test results and data before power-off cannot be effectively saved.
  • the purpose of the present invention is to provide a device and method for collecting information before the test head is powered off according to the present invention, which can collect all kinds of information before the test head is powered off, and effectively save it, so that the next test recovery can continue use.
  • a device for collecting information before a test head is powered off comprising:
  • each said single board includes power supply, power failure detection module, interrupt module, central processing module CPU, test module and storage module; all the test modules are connected to the customer's device under test DUT;
  • each of the power-off detection modules receives and detects whether the respective power supply voltage is lower than the first voltage threshold, and if so, the power-off detection module sends a power-off indication signal To the interrupt module, the interrupt module sends an interrupt signal to the central processing module CPU of the N single boards (single board 1, single board 2 ...
  • each The central processing module CPU controls the corresponding test module to test the customer's device under test CPU, and sends the test result back to the corresponding test module, and stores it through the storage module; wherein the first voltage The threshold is greater than a second voltage threshold, the second voltage threshold is a voltage value for stopping the testing of the test module, and is greater than zero.
  • test modules are connected to the CPU of the customer's device under test through a backplane.
  • a method for collecting information before a test head is powered off, using the above-mentioned device for collecting information before a test head is powered off which includes:
  • Step S1 Connect N boards (board 1, board 2... board N) located in different slots to the customer's device under test DUT; wherein, each board includes a power supply, a power-down detection module, Interrupt module, central processing module CPU, test module and storage module;
  • Step S2 Each central processing module CPU controls the corresponding test module to test the customer's device under test DUT, and sends the test result back to the corresponding test module, and stores it through the storage module;
  • Step S3 Each of the power-down detection modules receives and detects whether the voltage signal of the power supply is lower than the first voltage threshold, and when the detection result of one of the power-down detection modules is yes, perform step S4; if not , execute step S2:
  • Step S4 the power-off detection module sends a power-off indication signal to the interrupt module, and simultaneously notifies the interrupt modules of other slots, and the interrupt module reports and sends interrupt signals to the central processing module CPUs located in different slots;
  • the central processing module CPU of the single board notifies the test module to interrupt the test, save the current test progress and test results when the voltage signal of the power supply is lower than the second voltage threshold, and store the current test progress and test results in the ;
  • the first voltage threshold is greater than the second voltage threshold
  • the second voltage threshold is a voltage value that stops the test module from testing, and is greater than zero.
  • the information collection device and method for collecting information before the test head is powered off provided by the present invention can realize early detection of equipment power-off, and collect the test progress and test progress of all current resources before the equipment is completely powered off. As a result, the test can be resumed from the power-off point after the fault is removed and the power is turned on again, which not only improves the test efficiency of the device, but also protects the performance of the DUT of the customer's device under test from being affected by the fault.
  • Fig. 1 shows the schematic diagram of the test head structure of the semiconductor automatic test equipment in the prior art
  • Fig. 2 shows the schematic diagram of a preferred embodiment of the information collection device before the power failure of the test head of the present invention
  • Fig. 3 shows the schematic flow chart of the method for collecting information before the test head is powered off in the present invention
  • Fig. 4 shows the schematic diagram of a preferred embodiment of the information collection method before the test head of the present invention is powered off
  • the present invention monitors the power supply of N boards (single board 1 , single board 2 ...single board N ) located in different slots based on a specific detection circuit; At the moment when the information collection device starts to lose power before the test head loses power, it outputs a power-down indication signal to notify the downstream modules.
  • the key to the design of the power-off detection circuit is to detect in advance, the time point when the power-off indication is output, and the information collection device is actually powered off before the test head is powered off. There needs to be enough time to satisfy the downstream modules to complete the relevant operations. Therefore, the present invention can solve the problems that the relevant test information cannot be collected effectively, and the waste of resources and low efficiency are caused.
  • FIG. 1 is a schematic diagram of the device for collecting information before the test head is powered off according to the present invention.
  • the information collection device before the test head is powered off includes N single boards (single board 1 , single board 2 ... single board N ) located in different slots, and each said single board includes a power supply, a power-down Detection module, interrupt module, central processing module CPU, test module and storage module; all the test modules are connected to the customer's device under test DUT.
  • all the test modules interface with the customer's device under test (DUT) through a backplane.
  • the power supply is the power supply for the information collection device before the test head is powered off, usually a fixed DC voltage value V1.
  • the power-down detection circuit and the interrupt module are connected in series between the power supply and the central processing unit.
  • the module CPU is mainly used to detect and discover whether the single board or the DUT of the customer's device under test is powered off in advance.
  • each of the power-down detection modules in N single boards receives and detects whether the voltage signal of the power supply is lower than The first voltage threshold V2 (wherein, V2 is smaller than V1).
  • V2 the voltage threshold
  • the information collection device can still work before the test head is powered off, until the voltage of the power supply is lower than the second voltage threshold V3, the test The information collection device stops working before the head is powered off.
  • the information collection device before the test head is powered off can use the time period when the voltage of the power supply gradually drops from the first voltage threshold V2 to the second voltage threshold V3, that is, before the test head is powered off, Start collecting test information in advance and save it effectively so that it can continue to be used after the next test recovery.
  • the power-off detection module sends a power-off indication signal to the interruption module, and the interruption module detects the power-off indication signal.
  • the interrupt module reports and sends an interrupt signal to the central processing module CPU of the N single boards (single board 1 , single board 2 ... single board N ); the central processing module CPU of each single board Notify the test module to interrupt the test, save the current test progress and test results when the voltage signal of the power supply is lower than the second voltage threshold, and store the current test progress and test results in the said test module.
  • the interruptions of all the slots of the single boards are in an "AND" logical relationship, and any interruption generated will be reported to the central processing of N single boards (single board 1 , single board 2 ...single board N )
  • the module CPU that is, the interrupt modules between different boards will report and receive interrupts to each other, and will also directly report interrupts to the central processing module CPU.
  • each of the central processing modules CPU controls the corresponding test module to test the customer's device under test DUT, and sends the test result back to the corresponding The test module described above is stored through the storage module.
  • the central processing module CPU is mainly responsible for the management of the entire board and the control of the test module.
  • the test module directly drives the test resources and interfaces with the customer's DUT through the backplane.
  • the central processing module CPU receives the interrupt reported by the interrupt module, immediately notifies the test module to save the current test progress and test results, and interrupts the test to prepare for powering off the test device.
  • the storage module receives the test data and test results fed back by the test module, and writes them into the non-volatile storage medium in real time.
  • a sata hard disk can be used.
  • FIG. 3 is a schematic flowchart of the method for collecting information before the test head is powered off in the present invention.
  • the information collection method may include the following steps:
  • Step S1 Connect N boards (single board 1 , board 2 ... single board N ) located in different slots to the customer's device under test DUT; wherein, each board includes a power supply, a power-down detection module, Interrupt module, central processing module CPU, test module and storage module;
  • Step S2 each central processing module CPU controls the corresponding test module to test the customer's device under test DUT, and sends the test result back to the corresponding test module, and stores it through the storage module;
  • Step S3 Each of the power-down detection modules receives and detects whether the voltage signal of the power supply is lower than the first voltage threshold, and when the detection result of one of the power-down detection modules is yes, perform step S4; if not , execute step S2:
  • Step S4 the power-off detection module sends a power-off indication signal to the interrupt module, and simultaneously notifies the interrupt modules of other slots, and the interrupt module reports and sends interrupt signals to the central processing module CPUs located in different slots;
  • the central processing module CPU of the single board notifies the test module to interrupt the test, save the current test progress and test results when the voltage signal of the power supply is lower than the second voltage threshold, and store the current test progress and test results in the ;
  • the first voltage threshold is greater than the second voltage threshold
  • the second voltage threshold is a voltage value that stops the test module from testing, and is greater than zero.
  • FIG. 4 is a schematic diagram of a preferred embodiment of the method for collecting information before the test head is powered off according to the present invention. As shown in Figure 4, the process is mainly to explain that after a certain board detects a power failure and before it is completely powered off, it coordinates with other modules to complete the collection of various types of information, so that the next time the environment is restored. Test again to improve test efficiency.
  • the central processing module CPU of each single board notifies the test module to stop the test and test the node;
  • the storage module saves the test data and test results to the local hard disk.

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Tests Of Electronic Circuits (AREA)

Abstract

一种测试头掉电前信息收集装置及其收集方法，收集装置包括不同槽位的N块单板，每块单板包括供电电源、掉电检测模块、中断模块、CPU、测试模块和存储模块；所有测试模块接DUT；当检测时，每个掉电检测模块接收并检测各自的供电电源电压是否低于第一电压阈值，如果是，发送断电指示信号给N块单板的中断模块和CPU；每块单板中的CPU通知测试模块中断测试，在供电电源的电压信号低于第二电压阈值前保存当前测试进度和测试结果，并存储当前测试进度和测试结果；如果不是，每个CPU控制相应的测试模块对DUT进行测试，并将测试结果发送回相应的测试模块，并通过存储模块存储；其中，第一电压阈值大于第二电压阈值。

Description

一种测试头掉电前信息收集设备及其收集方法
交叉引用
本申请要求2021年12月13日提交的申请号为CN 202111515522.1的中国专利申请的优先权。上述申请的内容以引用方式被包含于此。
技术领域
本发明涉及半导体自动测试设备(Automatic Test Equipment，简称ATE)领域，尤其涉及一种测试头掉电前信息收集设备及其收集方法。
技术背景
随着集成电路的复杂度的提高，其测试的复杂度也随之提高，甚至一些器件的测试成本甚至占到了芯片成本的大部分。大规模集成电路会要求几百次的电压和电流和时序的测试，以及百万次的功能测试步骤以保证器件的完全正确。因此，半导体自动测试设备(ATE)应运而生。
通常，在ATE测试机中，测试头直接与被测晶圆(wafer)或被测芯片连接。无论是wafer/被测芯片，还是测试头，造价都比较昂贵。
请参阅图1，图1所示为现有技术中的半导体自动测试设备的测试头架构示意图。如图1所示，N块单板(单板1、单板2…单板N)通过背板与客户被测设备(Device Under Test，DUT)相连。
其中，每一块单板包括中央处理模块CPU、测试模块、存储模块和硬盘(HDD)。中央处理模块控制测试模块对客户被测设备DUT进行测试，并将测试结果发送回相应的单板，并通过存储模块存储。
在测试的过程中，如果测试头遇到一些异常情况或环境故障等，通常半导体自动测试设备会被紧急下电。虽然，半导体自动测试设备紧急下电是偶 发的小概率事件，但是，这种突发事件会导致ATE测试被强迫中断，并且使掉电之前的测试结果和数据无法得到有效的保存。
尤其是大规模批量量产阶段，如果大量的被测晶圆和被测芯片测试都没有完成，数据无法得到有效的统计。当后续环境恢复之后，工作人员还需要从头开始检测和测试，造成资源浪费且影响测试效率。
发明概要
本发明的目的在于，提供一种本发明测试头掉电前信息收集设备及其收集方法，其可以在测试头掉电之前，收集好各类信息，并有效保存，便于下次测试恢复可以继续使用。
为实现上述目的，本发明的技术方案如下：
一种测试头掉电前信息收集装置，其包括：
位于不同槽位的N块单板(单板1、单板2…单板N)，每块所述单板包括供电电源、掉电检测模块、中断模块、中央处理模块CPU、测试模块和存储模块；所有所述测试模块接客户被测设备DUT；
当所述测试头处于检测过程中，每个所述掉电检测模块接收并检测各自的所述供电电源电压是否低于第一电压阈值，如果是，所述掉电检测模块发送断电指示信号给所述中断模块，所述中断模块发送中断信号给所述N块单板(单板1、单板2…单板N)的中央处理模块CPU；每块所述单板的中央处理模块CPU通知各自的所述测试模块中断测试，在所述供电电源的电压信号低于第二电压阈值前保存当前测试进度和测试结果，并在所述存储当前测试进度和测试结果；如果不是，每个所述中央处理模块CPU控制相应的所述测试模块对所述客户被测设备CPU进行测试，并将测试结果发送回相 应的所述测试模块，并通过存储模块存储；其中，所述第一电压阈值大于第二电压阈值，所述第二电压阈值为使所述测试模块停止测试的电压值，且大于零。
进一步地，所有所述测试模块通过背板与所述客户被测设备CPU对接。
为实现上述目的，本发明又一技术方案如下：
一种测试头掉电前信息收集方法，采用上述的测试头掉电前信息收集装置，其包括：
步骤S1：将位于不同槽位的N块单板(单板1、单板2…单板N)接客户被测设备DUT；其中，每块所述单板包括供电电源、掉电检测模块、中断模块、中央处理模块CPU、测试模块和存储模块；
步骤S2：每个所述中央处理模块CPU控制相应的所述测试模块对所述客户被测设备DUT进行测试，并将测试结果发送回相应的所述测试模块，并通过存储模块存储；
步骤S3：每个所述掉电检测模块接收并检测所述供电电源的电压信号是否低于第一电压阈值，当某个所述掉电检测模块的检测结果为是，执行步骤S4；如果不是，执行步骤S2：
步骤S4：所述掉电检测模块发送断电指示信号给所述中断模块，同时通知其它槽位的中断模块，所述中断模块上报发送中断信号给位于不同槽位的中央处理模块CPU；每块所述单板的中央处理模块CPU通知所述测试模块中断测试，在所述供电电源的电压信号低于第二电压阈值保存当前测试进度和测试结果，并在所述存储当前测试进度和测试结果；其中，所述第一电压阈值大于第二电压阈值，所述第二电压阈值为使所述测试模块停止测试的 电压值，且大于零。
从上述技术方案可以看出，本发明提供的测试头掉电前信息收集设备及其收集方法，其可以实现提前检测设备掉电，在设备完全下电之前，收集当前所有资源的测试进度和测试结果，以便排除故障后再次上电之后，可以从断电点恢复测试，不仅提高了设备的测试效率，且保护客户被测设备DUT的性能不受故障的影响。
附图说明
图1所示为现有技术中的半导体自动测试设备的测试头架构示意图
图2所示为本发明测试头掉电前信息收集装置一较佳实施例的示意图
图3所示为本发明测试头掉电前信息收集方法的流程示意图
图4所示为本发明测试头掉电前信息收集方法一较佳实施例的示意图
发明内容
下面结合附图1-4，对本发明的具体实施方式作进一步的详细说明。
需要说明的是，在测试头突然掉电的情况下，本发明基于特定的检测电路，监控位于不同槽位的N块单板(单板 1、单板 2…单板 N)的供电电源；在测试头掉电前信息收集装置开始掉电的瞬间，输出掉电指示信号，通知下游模块。掉电检测电路的设计关键在于提前检测，输出掉电指示的时间点，到测试头掉电前信息收集装置真正掉电完成，需要有足够的时间，以满足下游模块完成相关的操作。因此，本发明可以解决相关测试信息无法有效收集，以及造成资源的浪费和效率低下的问题。
请参阅图1，图1所示为本发明测试头掉电前信息收集装置的示意图。 如图1所示，测试头掉电前信息收集装置包括位于不同槽位的N块单板(单板 1、单板 2…单板 N)，每块所述单板包括供电电源、掉电检测模块、中断模块、中央处理模块CPU、测试模块和存储模块；所有所述测试模块接客户被测设备DUT。较佳地，所有所述测试模块通过背板与所述客户被测设备(DUT)对接。
具体地，供电电源为测试头掉电前信息收集装置的供电，通常为一个固定的直流电压值V1，与现有技术不同的是，掉电检测电路和中断模块串接在供电电源和中央处理模块CPU之间主要用于提前检测和发现单板或客户被测设备DUT是否掉电。
当所述测试头处于检测过程中，N块单板(单板 1、单板 2…单板 N)中的每个所述掉电检测模块接收并检测所述供电电源的电压信号是否低于第一电压阈值V2(其中，V2小于V1)。此时，虽然所述供电电源的电压已低于第一电压阈值V2，但测试头掉电前信息收集装置还是可以工作的，直到所述供电电源的电压，低于第二电压阈值V3，测试头掉电前信息收集装置才停止工作。
在本发明的实施例中，测试头掉电前信息收集装置可以利用所述供电电源的电压从第一电压阈值V2逐渐掉到第二电压阈值V3的时间段，即在测试头掉电之前，提前开始收集测试信息，并有效保存，便于下次测试恢复可以继续使用。
具体地，当所述供电电源电压小于第一电压阈值V2的瞬间，所述掉电检测模块发送断电指示信号给所述中断模块，中断模块检测掉电指示信号。一旦接收到之后，所述中断模块上报发送中断信号给所述N块单板(单板 1、 单板 2…单板 N)的中央处理模块CPU；每块所述单板的中央处理模块CPU通知所述测试模块中断测试，在所述供电电源的电压信号低于第二电压阈值保存当前测试进度和测试结果，并在所述存储当前测试进度和测试结果。
在本发明的实施例中，所有单板槽位的中断是“与”逻辑关系，产生任意一个中断，都会上报给N块单板(单板 1、单板 2…单板 N)的中央处理模块CPU，即不同单板之间的中断模块会互相上报和接收中断，也会直接上报中断给中央处理模块CPU。
如果所述供电电源电压一直不小于第一电压阈值V2，每个所述中央处理模块CPU控制相应的所述测试模块对所述客户被测设备DUT进行测试，并将测试结果发送回相应的所述测试模块，并通过存储模块存储。
中央处理模块CPU主要负责整个单板的管理以及对测试模块的控制。测试模块则直接驱动测试资源，通过背板与客户被测设备DUT对接。中央处理模块CPU接收中断模块上报的中断，立刻通知测试模块保存当前测试进度和测试结果，并中断测试，为测试装置下电做好准备。
存储模块接收测试模块反馈的测试数据和测试结果，并实时地将其写入非易失性存储介质中。例如，可以采用sata硬盘。
请参阅图3，图3所示为本发明测试头掉电前信息收集方法的流程示意图。如图3所示，该信息收集方法可以包括如下步骤：
步骤S1：将位于不同槽位的N块单板(单板 1、单板 2…单板 N)接客户被测设备DUT；其中，每块所述单板包括供电电源、掉电检测模块、中断模块、中央处理模块CPU、测试模块和存储模块；
步骤S2：每个所述中央处理模块CPU控制相应的所述测试模块对所述 客户被测设备DUT进行测试，并将测试结果发送回相应的所述测试模块，并通过存储模块存储；
步骤S3：每个所述掉电检测模块接收并检测所述供电电源的电压信号是否低于第一电压阈值，当某个所述掉电检测模块的检测结果为是，执行步骤S4；如果不是，执行步骤S2：
步骤S4：所述掉电检测模块发送断电指示信号给所述中断模块，同时通知其它槽位的中断模块，所述中断模块上报发送中断信号给位于不同槽位的中央处理模块CPU；每块所述单板的中央处理模块CPU通知所述测试模块中断测试，在所述供电电源的电压信号低于第二电压阈值保存当前测试进度和测试结果，并在所述存储当前测试进度和测试结果；其中，所述第一电压阈值大于第二电压阈值，所述第二电压阈值为使所述测试模块停止测试的电压值，且大于零。
请参阅图4，图4所示为本发明测试头掉电前信息收集方法一较佳实施例的示意图。如图4所示，该流程主要是说明某一个单板在检测到掉电后，且在完全掉电之前，协调其它各个模块，去完成对各类信息的收集，以便下次环境恢复之后的再次测试，提高测试效率。
下面以单板1为例进行说明，具体操作步骤如下：
首先，对单板1进行正常的掉电检测，如果检测到掉电，中断模块产生掉电中断并通知位于其它槽位的单板；
第二，每一个单板的中央处理模块CPU通知测试模块停止测试并测试节点；
第三，所有测试模块停止驱动所有测试资源，汇总各自单板上的测试数 据和测试结果；
第四，存储模块将测试数据和测试结果保存到本地硬盘。
以上所述的仅为本发明的优选实施例，所述实施例并非用以限制本发明的专利保护范围，因此凡是运用本发明的说明书及附图内容所作的等同结构变化，同理均应包含在本发明的保护范围内。

Claims (3)

  1. 一种测试头掉电前信息收集装置，其特征在于，包括：
    位于不同槽位的N块单板(单板 1、单板 2…单板 N)，每块所述单板包括供电电源、掉电检测模块、中断模块、中央处理模块(CPU)、测试模块和存储模块；所有所述测试模块接客户被测设备(DUT)；
    当所述测试头处于检测过程中，每个所述掉电检测模块接收并检测各自的所述供电电源电压是否低于第一电压阈值，如果是，所述掉电检测模块发送断电指示信号给所述中断模块，所述中断模块发送中断信号给所述N块单板(单板 1、单板 2…单板 N)的中央处理模块(CPU)；每块所述单板的中央处理模块(CPU)通知各自的所述测试模块中断测试，在所述供电电源的电压信号低于第二电压阈值前保存当前测试进度和测试结果，并在所述存储当前测试进度和测试结果；如果不是，每个所述中央处理模块(CPU)控制相应的所述测试模块对所述客户被测设备(DUT)进行测试，并将测试结果发送回相应的所述测试模块，并通过存储模块存储；其中，所述第一电压阈值大于第二电压阈值，所述第二电压阈值为使所述测试模块停止测试的电压值，且大于零。
  2. 根据权利要求1所述的测试头掉电前信息收集方法，其特征在于，所有所述测试模块通过背板与所述客户被测设备(DUT)对接。
  3. 一种测试头掉电前信息收集方法，其采用权利要求1-2任意一个所述的测试头掉电前信息收集装置，其特征在于，包括：
    步骤S1：将位于不同槽位的N块单板(单板 1、单板 2…单板 N)接客户被测设备(DUT)；其中，每块所述单板包括供电电源、掉电检测模块、 中断模块、中央处理模块(CPU)、测试模块和存储模块；
    步骤S2：每个所述中央处理模块(CPU)控制相应的所述测试模块对所述客户被测设备(DUT)进行测试，并将测试结果发送回相应的所述测试模块，并通过存储模块存储；
    步骤S3：每个所述掉电检测模块接收并检测所述供电电源的电压信号是否低于第一电压阈值，当某个所述掉电检测模块的检测结果为是，执行步骤S4；如果不是，执行步骤S2：
    步骤S4：所述掉电检测模块发送断电指示信号给所述中断模块，同时通知其它槽位的中断模块，所述中断模块上报发送中断信号给位于不同槽位的中央处理模块(CPU)；每块所述单板的中央处理模块(CPU)通知所述测试模块中断测试，在所述供电电源的电压信号低于第二电压阈值保存当前测试进度和测试结果，并在所述存储当前测试进度和测试结果；其中，所述第一电压阈值大于第二电压阈值，所述第二电压阈值为使所述测试模块停止测试的电压值，且大于零。
PCT/CN2021/143488 2021-12-13 2021-12-31 一种测试头掉电前信息收集设备及其收集方法 WO2023108829A1 (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202111515522.1A CN114487744A (zh) 2021-12-13 2021-12-13 一种测试头掉电前信息收集设备及其收集方法
CN202111515522.1 2021-12-13

Publications (1)

Publication Number Publication Date
WO2023108829A1 true WO2023108829A1 (zh) 2023-06-22

Family

ID=81493114

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2021/143488 WO2023108829A1 (zh) 2021-12-13 2021-12-31 一种测试头掉电前信息收集设备及其收集方法

Country Status (2)

Country Link
CN (1) CN114487744A (zh)
WO (1) WO2023108829A1 (zh)

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102033826A (zh) * 2010-12-03 2011-04-27 创新科存储技术有限公司 内存掉电数据保护的装置和方法
CN102403987A (zh) * 2010-09-14 2012-04-04 三星半导体(中国)研究开发有限公司 在低压下实现数据断电保持的电路和方法
WO2017054487A1 (zh) * 2015-09-30 2017-04-06 中兴通讯股份有限公司 一种掉电保护的方法、装置和电子设备
CN109782888A (zh) * 2018-12-29 2019-05-21 京信通信系统（中国）有限公司 Dram数据的掉电保护电路、电子设备和方法
CN112269463A (zh) * 2020-11-02 2021-01-26 珠海格力电器股份有限公司 一种掉电保护电路、方法及电能表
CN112562764A (zh) * 2020-12-15 2021-03-26 上海维宏电子科技股份有限公司 嵌入式系统掉电保护的电路与方法
CN112946562A (zh) * 2021-02-07 2021-06-11 南方电网数字电网研究院有限公司 双芯智能电表的掉电保护方法、装置和双芯智能电表
WO2021189322A1 (zh) * 2020-03-25 2021-09-30 华为技术有限公司 一种芯片测试装置及测试方法

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102403987A (zh) * 2010-09-14 2012-04-04 三星半导体(中国)研究开发有限公司 在低压下实现数据断电保持的电路和方法
CN102033826A (zh) * 2010-12-03 2011-04-27 创新科存储技术有限公司 内存掉电数据保护的装置和方法
WO2017054487A1 (zh) * 2015-09-30 2017-04-06 中兴通讯股份有限公司 一种掉电保护的方法、装置和电子设备
CN109782888A (zh) * 2018-12-29 2019-05-21 京信通信系统（中国）有限公司 Dram数据的掉电保护电路、电子设备和方法
WO2021189322A1 (zh) * 2020-03-25 2021-09-30 华为技术有限公司 一种芯片测试装置及测试方法
CN112269463A (zh) * 2020-11-02 2021-01-26 珠海格力电器股份有限公司 一种掉电保护电路、方法及电能表
CN112562764A (zh) * 2020-12-15 2021-03-26 上海维宏电子科技股份有限公司 嵌入式系统掉电保护的电路与方法
CN112946562A (zh) * 2021-02-07 2021-06-11 南方电网数字电网研究院有限公司 双芯智能电表的掉电保护方法、装置和双芯智能电表

Also Published As

Publication number Publication date
CN114487744A (zh) 2022-05-13

Similar Documents

Publication Publication Date Title
CN101976217B (zh) 网络处理器异常检测方法及系统
JP6530774B2 (ja) ハードウェア障害回復システム
CN103455395B (zh) 一种硬盘故障的检测方法及装置
US6532552B1 (en) Method and system for performing problem determination procedures in hierarchically organized computer systems
US6012148A (en) Programmable error detect/mask utilizing bus history stack
US7519866B2 (en) Computer boot operation utilizing targeted boot diagnostics
US7461303B2 (en) Monitoring VRM-induced memory errors
US20080270827A1 (en) Recovering diagnostic data after out-of-band data capture failure
CN105259863A (zh) 一种plc温备份冗余方法及系统
CN104320308A (zh) 一种服务器异常检测的方法及装置
CN112114989B (zh) 一种服务器系统故障诊断设计方法
CN104283718B (zh) 网络设备及用于网络设备的硬件故障诊断方法
CN116049249A (zh) 报错信息处理方法、装置、系统、设备和存储介质
US20090138740A1 (en) Method and computer device capable of dealing with power fail
US20060184840A1 (en) Using timebase register for system checkstop in clock running environment in a distributed nodal environment
US20080288828A1 (en) structures for interrupt management in a processing environment
WO2023108829A1 (zh) 一种测试头掉电前信息收集设备及其收集方法
WO2021056913A1 (zh) 基于i2c通讯的故障定位方法、装置及系统
US8726102B2 (en) System and method for handling system failure
CN113742166A (zh) 一种服务器系统器件日志记录方法、装置及系统
CN111884830A (zh) 一种基于bmc保留故障现场的方法及装置
TWI823556B (zh) 記憶體異常檢測系統、主機板、電子裝置及異常檢測方法
CN112787305B (zh) Vlsi和soc的电压降管理
CN116107788B (zh) 一种i2c总线故障处理方法及装置
CN218122120U (zh) 一种主板故障的检测装置

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 21967958

Country of ref document: EP

Kind code of ref document: A1