WO2023108784A1 - 一种半导体器件及其制造方法 - Google Patents

一种半导体器件及其制造方法 Download PDF

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Publication number
WO2023108784A1
WO2023108784A1 PCT/CN2021/140812 CN2021140812W WO2023108784A1 WO 2023108784 A1 WO2023108784 A1 WO 2023108784A1 CN 2021140812 W CN2021140812 W CN 2021140812W WO 2023108784 A1 WO2023108784 A1 WO 2023108784A1
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Prior art keywords
layer
channel
electrode layer
dummy gate
opening
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PCT/CN2021/140812
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English (en)
French (fr)
Inventor
黄伟兴
朱慧珑
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Institute of Microelectronics of CAS
Beijing Superstring Academy of Memory Technology
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Institute of Microelectronics of CAS
Beijing Superstring Academy of Memory Technology
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Priority to US17/783,624 priority Critical patent/US12183807B2/en
Publication of WO2023108784A1 publication Critical patent/WO2023108784A1/zh
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/017—Manufacture or treatment using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/025—Manufacture or treatment of FETs having insulated gates [IGFET] of vertical IGFETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/63—Vertical IGFETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
    • H10D62/213—Channel regions of field-effect devices
    • H10D62/221—Channel regions of field-effect devices of FETs
    • H10D62/235—Channel regions of field-effect devices of FETs of IGFETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
    • H10D62/213—Channel regions of field-effect devices
    • H10D62/221—Channel regions of field-effect devices of FETs
    • H10D62/235—Channel regions of field-effect devices of FETs of IGFETs
    • H10D62/292—Non-planar channels of IGFETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H10D64/311—Gate electrodes for field-effect devices
    • H10D64/411—Gate electrodes for field-effect devices for FETs
    • H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
    • H10D12/211—Gated diodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/751—Insulated-gate field-effect transistors [IGFET] having composition variations in the channel regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/82—Heterojunctions
    • H10D62/822—Heterojunctions comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions

Definitions

  • the present application relates to the field of semiconductor devices, in particular to a semiconductor device and a manufacturing method thereof.
  • the flow direction of the channel current of the vertical semiconductor device is perpendicular to the plane of the substrate, which has the advantages of low power consumption, etc., and can increase and reduce the scale of the device or increase the integration density of the integrated circuit.
  • the purpose of the present application is to provide a semiconductor device and a manufacturing method thereof, so as to improve the performance of a semiconductor device with a vertical structure.
  • An embodiment of the present application provides a method for manufacturing a semiconductor device, including:
  • a first electrode layer, a semiconductor layer comprising at least germanium, and a second electrode layer are sequentially formed on one side of the substrate; the first electrode layer is one of a source layer or a drain layer, and the second electrode The layer is the other of the source layer or the drain layer;
  • Etching part of the semiconductor layer from the sidewall of the semiconductor layer to form an opening includes an arc, and the arc-shaped notch faces outward;
  • a channel layer is formed on the opening, the sidewall of the first electrode layer, and the sidewall of the second electrode layer, wherein the channel layer includes a first channel portion located in the opening and a a second channel portion within the opening, the first channel portion conforming to the opening;
  • Dielectric material is filled in the depression to form an isolation side wall.
  • the opening includes a first opening and a second opening, the first opening is located outside the second opening, the channel layer includes a first sub-channel layer and a second sub-channel layer, so The first sub-channel layer is located outside the second sub-channel layer;
  • Etching part of the semiconductor layer from the sidewall of the semiconductor layer to form an opening includes an arc
  • the arc-shaped notch facing the outside includes:
  • the forming a channel layer on the opening, the sidewall of the first electrode layer, and the sidewall of the second electrode layer includes:
  • first sub-channel layer epitaxially growing a first sub-channel layer on the first opening, the outer sidewall of the first electrode layer, and the outer sidewall of the second electrode layer;
  • Etching part of the semiconductor layer from the sidewall of the semiconductor layer to form an opening includes an arc
  • the arc-shaped notch facing the outside includes:
  • the forming a channel layer on the opening, the sidewall of the first electrode layer, and the sidewall of the second electrode layer includes:
  • a second sub-channel layer is epitaxially grown on the second opening, the inner sidewall of the first electrode layer, and the inner sidewall of the second electrode layer.
  • the dummy gate layer includes a first dummy gate layer and a second dummy gate layer, the first dummy gate layer is located outside the second dummy gate layer; the recess includes a first a depression and a second depression, the first depression being located outside the second depression;
  • the filling of the dummy gate layer in the first channel part includes:
  • the etching part of the dummy gate layer from the sidewall of the dummy gate layer includes:
  • the removal of the second channel part and the first channel part in contact with the upper and lower surfaces of the dummy gate layer forms a channel composed of the first electrode layer or the second electrode layer, the channel layer and The recess formed by the dummy gate layer includes:
  • the second channel part of the first sub-channel layer and the first channel part in contact with the upper and lower surfaces of the first dummy gate layer are removed by atomic layer etching, and the first electrode layer or the second channel part is formed. a first recess formed by the electrode layer, the first sub-channel layer and the first dummy gate layer;
  • the second channel portion of the second sub-channel layer and the first channel portion in contact with the upper and lower surfaces of the second dummy gate layer are removed by atomic layer etching to form the first electrode layer or the second dummy gate layer. a second recess formed by the electrode layer, the second sub-channel layer and the second dummy gate layer;
  • the filling the dielectric material in the depression to form the isolation side wall includes:
  • a dielectric material is deposited in the first recess and the second recess to form an isolation sidewall.
  • the method before etching the remaining semiconductor layer from the inner sidewall of the semiconductor layer by atomic layer etching, the method further includes:
  • the groove is surrounded by the first electrode layer, the semiconductor layer and the second electrode layer wall structure.
  • the method before etching part of the semiconductor layer from the sidewall of the semiconductor layer, the method further includes:
  • the top layer structure includes a crystalline silicon core area and a dielectric barrier surrounding the crystalline silicon core area, wherein the crystalline silicon core area corresponds to the said groove;
  • the wall structure composed of layers includes:
  • the method further includes:
  • the dummy gate layer is removed to form a gate in the first channel part.
  • the method before forming a gate in the first channel portion, the method further includes:
  • An interface layer and a high-K material layer are sequentially conformally formed in the first channel portion.
  • the material of the semiconductor layer including at least germanium is germanium or silicon germanium.
  • the dielectric material is a low-K material.
  • An embodiment of the present application provides a semiconductor device, including: a sequentially stacked substrate, a first electrode layer, a functional layer, and a second electrode layer; A trench to the substrate, the trench is surrounded by a wall structure composed of the first electrode layer, the functional layer and the second electrode layer;
  • the first electrode layer is located on one side of the substrate
  • the functional layer is located on the side of the first electrode layer away from the substrate, the functional layer includes a channel area, a gate area and an isolation spacer area, the channel area includes an arc-shaped area, and the arc
  • the notch in the shape faces outward, the two sides of the arc-shaped region are gate regions, and the isolation spacer regions are located above and below the gate region;
  • the second electrode layer is located on the side of the functional layer away from the substrate, the first electrode layer is one of a source layer or a drain layer, and the second electrode layer is a source layer or another in the drain layer.
  • An embodiment of the present application provides a method for manufacturing a semiconductor device.
  • a first electrode layer, a semiconductor layer including at least germanium, and a second electrode layer are sequentially formed on a substrate, and the first electrode layer is a source layer or a drain layer.
  • the second electrode layer is the other one of the source layer or the drain layer, and then a part of the semiconductor layer is etched from the sidewall of the semiconductor layer to form an opening, the opening includes an arc shape, and the arc-shaped gap faces outward, That is, the opening faces the outside, and then a channel layer is formed on the opening, the sidewall of the first electrode layer, and the sidewall of the second electrode layer, wherein the channel layer includes a first channel portion located in the opening and a channel portion except in the opening.
  • the second channel part, the first channel part conforms to the opening, that is, the first channel part also includes an arc, and the dummy gate layer is filled in the first channel part including the arc, and the obtained dummy gate layer
  • the sidewall is flush with the sidewall of the second channel part, and then the second channel part is used as a mask to etch part of the dummy gate layer from the sidewall of the dummy gate layer, so that the etched dummy gate layer
  • the sidewalls of the first electrode layer are flush with the sidewalls of the first electrode layer, and then the second channel part and the first channel part in contact with the upper and lower surfaces of the dummy gate layer are removed to form the first electrode layer or the second electrode layer, the trench
  • the recess formed by the channel layer and the dummy gate layer is filled with a dielectric material to form an isolation spacer, which can reduce the parasitic capacitance of the semiconductor device and optimize the performance of the semiconductor device.
  • FIG. 1 shows a flowchart of a method for manufacturing a semiconductor device provided by an embodiment of the present application
  • FIGS. 2 to 20 show schematic structural views of a semiconductor device manufactured according to the method for manufacturing a semiconductor device provided in an embodiment of the present application.
  • an embodiment of the present application provides a method for manufacturing a semiconductor device.
  • a first electrode layer, a semiconductor layer including at least germanium, and a second electrode layer are sequentially formed on a substrate, and the first electrode layer is a source layer or a drain layer.
  • One of the electrode layers, the second electrode layer is the other of the source layer or the drain layer, and then a part of the semiconductor layer is etched from the side wall of the semiconductor layer to form an opening, the opening includes arc-shaped, arc-shaped gaps towards the outside, that is, the opening faces the outside, and then a channel layer is formed on the opening, the sidewall of the first electrode layer, and the sidewall of the second electrode layer, wherein the channel layer includes a first channel part located in the opening and a channel layer except The second channel part in the opening, the first channel part conforms to the opening, that is, the first channel part also includes an arc, and the dummy gate layer is filled in the first channel part including the arc, and the obtained dummy gate
  • the sidewall of the electrode layer is flush with the sidewall of the second channel part, and then the second channel part is used as a mask to etch part of the dummy gate layer from the sidewall of the dummy gate layer, so that the etched dummy gate layer
  • the semiconductor device provided by the embodiment of the present application may be a storage device or a logic device, and the semiconductor device provided by the embodiment of the present application may be a transistor device with a vertical structure, such as a field effect transistor (Field Effect Transistor, FET) with a vertical structure, which may specifically be Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) or Tunneling Field-Effect Transistor (TFET).
  • FET Field Effect Transistor
  • MOSFET Metal-Oxide-Semiconductor Field-Effect Transistor
  • TFET Tunneling Field-Effect Transistor
  • FIG. 1 it is a flow chart of a method for manufacturing a semiconductor device provided by an embodiment of the present application. The method includes the following steps:
  • the first electrode layer 120 , the semiconductor layer 130 including at least germanium, and the second electrode layer 140 may be sequentially formed on one side surface of the substrate 110 .
  • the first electrode layer 120 , the semiconductor layer 130 including at least germanium, and the second electrode layer 140 may be formed by means of epitaxial growth.
  • the substrate 110 may be a semiconductor substrate, such as a silicon substrate. Before forming the first electrode layer 120 on one side surface of the substrate 110, the substrate 110 can also be doped to form a well layer. Referring to FIG. 2, the well layer is formed after doping the substrate 110. Yes, compared with the substrate 110 , the conductivity of the doped well layer is higher, and a good electrical contact can be formed with the first electrode layer 120 .
  • the doping can be N-type doping, the doping element is As or P, and the doping concentration is 1e17-2e19/cm 3 .
  • the doping can also be P-type doping, the doping element is B or In, and the doping concentration is 1e17-2e19/cm 3 .
  • a well layer may be formed on the silicon substrate by implanting dopant ions and performing an annealing process.
  • an N-type field effect transistor (Field Effect Transistor, FET) is implanted with P-type impurities to form a well layer
  • a P-type field effect transistor (Field Effect Transistor, FET) is implanted with N-type impurities to form a well layer.
  • the thickness of the first electrode layer 120 and the second electrode layer 140 is about 10-50 nanometers (nm).
  • the electrode layer 120 and the second electrode layer 140 are doped semiconductor layers, and the doping type of the first electrode layer 120 and the second electrode layer 140 is the same, which can be N-type doping or P-type doping. Since the first electrode layer 120 is one of the source layer or the drain layer, and the second electrode layer 140 is the other of the source layer or the drain layer, the first electrode layer 120 and the second electrode layer can be made The conductivity of the second electrode layer 140 is better, specifically, in-situ doping can be used for doping.
  • the first electrode layer 120 is a P-type doped silicon layer, the doping element is B or In, and the doping concentration is 1e18-1e21/cm 3 .
  • the second electrode layer 120 is a P-type doped silicon layer, the doping element is B or In, and the doping concentration is 1e18-1e21/cm 3 .
  • the first electrode layer 120 is an N-type doped silicon layer, the doping element is As or P, and the doping concentration is 1e18-1e21/cm 3 .
  • the second electrode layer 120 is an N-type doped silicon layer, the doping element is As or P, and the doping concentration is 1e18-1e21/cm 3 .
  • the semiconductor layer 130 including at least germanium may be epitaxially grown on the first electrode layer 120 .
  • the material of the semiconductor layer 130 includes at least germanium, such as germanium or silicon germanium.
  • the thickness of the semiconductor layer 130 may range from 10-100 nm.
  • the doping ratio of germanium is in the range of 10%-50%. If the doping ratio is too small, the opening of the C-type structure cannot be formed. If If the doping ratio is too high, lattice defects will increase, which may degrade the performance of the memory device.
  • the doping ratio of germanium remains unchanged.
  • the doping ratio of germanium first increases and then decreases, that is, the Ge composition in the middle region is greater than the Ge composition in the upper and lower regions. Since the Ge composition is high in the middle region and the Ge composition is low in the upper and lower regions, the etch rate of the high Ge composition is greater than the etching rate of the low Ge composition, so it is easier to form an opening including an arc through subsequent etching.
  • the second electrode layer 140 is epitaxially formed on the semiconductor layer 130, and then the etch stop layer 101 and the crystalline silicon layer 102 are sequentially formed on the second electrode layer 140. and the dielectric layer 103, as shown in FIG. 3 .
  • the etching stop layer 101 , the crystalline silicon layer 102 and the dielectric layer 103 can be formed by using a deposition process.
  • the etch barrier layer 101 covers the second electrode layer 140 for protecting the underlying second electrode layer 140, and can also serve as an etch barrier layer to avoid etching damage to the second electrode layer 140 when the second contact of the second electrode layer 140 is formed.
  • the second electrode layer 140 .
  • the material of the etch stop layer 101 may be silicon oxide, or silicon oxide with high crystal quality formed by a high temperature process, so as to improve the performance of the semiconductor device.
  • the etch stop layer 101 may have a thickness of 1-10 nm.
  • the etch stop layer 101 is also covered with a crystalline silicon layer 102, the material of the crystalline silicon layer 102 may be polycrystalline silicon or amorphous silicon, and the thickness may be 50-150 nanometers.
  • a dielectric layer 103 is also covered on the crystalline silicon layer 102 .
  • the dielectric layer 103 is used to isolate other film layers and the second electrode layer 140 when manufacturing the device, and can also be used to isolate the second contact after forming the second contact of the second electrode layer 140, so as to ensure that the second contact is only connected to the semiconductor
  • the second electrode layer 140 in the device forms an electrical connection.
  • the material of the dielectric layer 103 may be nitride, such as silicon nitride, and the thickness of the dielectric layer 103 may be 30-100 nanometers.
  • FIG. 4 is a schematic top view of the semiconductor device during the manufacturing process.
  • FIG. 5 is a schematic diagram of a semiconductor structure obtained by taking a cross-section along the AA' direction of the semiconductor device. After the etching is completed, remove the photoresist layer 104, retain the etched dielectric layer 103 and the crystalline silicon core region 1021, continue to deposit the dielectric layer material and then perform etching to form a dielectric barrier 105 surrounding the crystalline silicon core region 1021, Refer to Figure 6. That is to say, by processing the crystalline silicon layer 102 and the dielectric layer 103 , a top layer structure including a crystalline silicon core region 1021 and a dielectric barrier wall 105 surrounding the crystalline silicon core region 1021 is formed.
  • the dielectric barrier 105 is used as a mask to etch the etch stop layer 101 , the second electrode layer 140 , the semiconductor layer 130 , the first electrode layer 120 and part of the substrate 110 , as shown in FIG. 7 .
  • the dielectric material is deposited until covering all the semiconductor devices, and then a shallow trench isolation (shallow trench isolation, STI) layer 106 is formed by using a chemical mechanical polishing (CMP) process and an etching process, as shown in FIG. 8.
  • CMP chemical mechanical polishing
  • a shallow trench isolation (shallow trench isolation, STI) layer 106 is used to isolate the semiconductor device from other semiconductor devices that are simultaneously manufactured during integrated circuit manufacturing.
  • the dielectric material may be silicon oxide.
  • the etching process can be wet etching or dry etching.
  • the semiconductor layer 130 is used to form an opening, wherein the opening includes an arc shape, and the arc-shaped notch faces outward.
  • the openings include a first opening 1071 and a second opening 1072 , and the first opening 1071 is located outside the second opening 1072 .
  • a portion of the semiconductor layer 130 is etched from the outer sidewall of the semiconductor layer 130 to form an arc-shaped first opening 1071 , and the first opening 1071 includes an arc-shaped notch facing outward.
  • the first opening 1071 comprising an arc resembles a letter C.
  • the arc-shaped opening is conducive to the subsequent formation of an arc-shaped channel layer in the opening.
  • the channel layer has less leakage current and a longer channel length, which can improve the performance of the semiconductor device.
  • the width of the semiconductor layer 130 remaining after etching gradually decreases and then increases, that is, it presents a structure whose upper and lower widths are greater than the middle width, similar to the letter X structure.
  • atomic layer etching is used to etch the semiconductor layer 130 from the sidewall of the semiconductor layer 130 by 10-40 nm to form the C-type opening 1071 .
  • an etchant having a selectivity ratio to the first electrode layer 120 and the second electrode layer 140 is selected so that the first electrode layer 120 and the second electrode layer will not be damaged when the opening 1071 is formed by etching. 140.
  • the remaining semiconductor layer 130 is etched from the inner sidewall of the semiconductor layer 130 to form a second opening 1072 including an arc.
  • the arc included in the second opening 1072 is the same as the first
  • the arc included in the first opening 1071 is conformal, that is, the arc-shaped notch included in the second opening 1072 also faces outward, and the arc-shaped second opening 1072 also resembles a letter C.
  • the process of forming the second opening 1072 will be described in detail later after filling the channel layer and the dummy gate layer in the first opening 1071 .
  • a channel layer may be formed on the opening, the sidewall of the first electrode layer 120 and the sidewall of the second electrode layer 140, and the channel layer includes the first sub-groove The channel layer 1081 and the second sub-channel layer 1082, the first sub-channel layer 1081 is located outside the second sub-channel layer 1082.
  • the channel layer includes a first channel part located in the opening and a second channel part except in the opening, and the first channel part conforms to the opening.
  • the first sub-channel layer 1081 is epitaxially grown on the first opening 1071 , the outer sidewall of the first electrode layer 120 and the outer sidewall of the second electrode layer 140 .
  • the first sub-channel layer 1081 includes a first channel portion 1081-1 located in the first opening 1071 and a second channel portion 1081-2 except in the first opening 1071, the first channel portion 1081-1 It is conformal to the first opening 1071, that is, the first channel portion 1081-1 also includes an arc shape, and the arc-shaped notch faces outward.
  • the thickness of the channel layer can be 3-30nm, and the material of the channel layer can be silicon or silicon germanium.
  • the doping ratio range of germanium can be 10%-50%.
  • the second sub-channel layer 1082 is epitaxially grown on the second opening 1072 , the inner sidewall of the first electrode layer 120 and the inner sidewall of the second electrode layer 140 .
  • the second sub-channel layer 1082 includes a first channel portion 1082-1 located in the second opening 1072 and a second channel portion 1082-2 except in the second opening 1072, the first channel portion 1082-1 It is conformal to the second opening 1072 , that is, the first channel portion 1082 - 1 also includes an arc shape, and the arc-shaped notch faces outward.
  • the first channel part of the channel layer after filling the first channel part of the channel layer in the opening, the first channel part does not fill the opening, and the dummy gate layer can be continuously filled in the first channel part, and the dummy gate The sidewalls of the layer are flush with the sidewalls of the second channel portion.
  • the dummy gate layer includes a first dummy gate layer 1091 and a second dummy gate layer 1092 , and the first dummy gate layer 1091 is located outside the second dummy gate layer 1092 .
  • the first dummy gate layer 1091 is filled in the first channel portion 1081 - 1 of the first opening 1071 .
  • the first dummy gate layer 1092 is filled in the first channel portion 1082 - 1 of the second opening 1072 .
  • the material of the dummy gate layer may be deposited first, followed by etching, so that the sidewall of the dummy gate layer is flush with the sidewall of the second channel portion.
  • etching it is also necessary to select an etchant having a selective ratio to the channel layer, so that the channel layer will not be damaged during etching.
  • the material of the dummy gate layer may be oxynitride.
  • the first opening 1071 is etched from the outer sidewall of the channel layer, on the first opening 1071, the outer sidewall of the first electrode layer 120 and the outer sidewall of the second electrode layer 140 After epitaxially growing the first sub-channel layer 1081, and filling the first dummy gate layer 1091 in the first channel portion 1081-1 of the first sub-channel layer 1081, etching the dielectric barrier 105 and the crystalline silicon core region 1021, the etch stop layer 101, the first electrode layer 120, the semiconductor layer 130, the second electrode layer 140 and part of the substrate 110, forming the through dielectric barrier 105, the crystalline silicon core region 1021, the etch stop layer 101, the first The electrode layer 120, the semiconductor layer 130, and the trench 201 of the second electrode layer 140, the crystalline silicon core region 1021 corresponds to the trench 201, that is, the crystalline silicon core region 1021 defines the position of the trench 201, and the trench 201 is surrounded by dielectric barriers 105 , the wall structure 202
  • the groove 201 is the inside of the wall structure 202 , and oppositely, the wall structure 202 has an outside.
  • a first opening 1071 has been formed outside the wall structure 202 , and a first sub-channel layer 1081 and a first dummy gate layer 1091 are formed outside the wall structure 202 and inside the first opening 1071 .
  • the remaining semiconductor layer 130 is etched from the inner sidewall of the semiconductor layer 130 to form a second opening 1072 that includes an arc.
  • the arc that the second opening 1072 includes is the same as the first
  • the arc included in the opening 1071 is conformal, that is, the arc-shaped notch included in the second opening 1072 also faces outward, and the arc-shaped second opening 1072 is also similar to a letter C.
  • the channel layer and the dummy gate layer are filled in the first opening 1071 , and the trench 201 is obtained by etching.
  • the second sub-channel layer 1082 is epitaxially grown on the sidewall.
  • the second sub-channel layer 1082 includes a first channel portion 1082-1 located in the second opening 1072 and a second channel portion 1082-2 except in the second opening 1072, the first channel portion 1082-1 It is conformal to the second opening 1072 , that is, the first channel portion 1082 - 1 also includes an arc shape, and the arc-shaped notch faces outward.
  • the thickness of the first sub-channel layer 1081 and the second sub-channel layer 1082 can be 3-15nm, and the material can be silicon or silicon germanium.
  • the doping ratio of germanium can be in the range of 10%- 30%.
  • the first dummy gate layer 1092 is filled in the first channel portion 1082 - 1 of the second opening 1072 .
  • the material of the dummy gate layer may be oxynitride.
  • a dielectric material is deposited until it covers the entire semiconductor device, and then a shallow trench isolation (shallow trench isolation) is formed in the trench 201 using a chemical mechanical polishing (CMP) process and an etching process.
  • CMP chemical mechanical polishing
  • trench isolation, STI trench isolation, STI
  • the dielectric material may be silicon oxide.
  • the etching process can be wet etching or dry etching.
  • part of the dummy gate layer is etched from the sidewall of the dummy gate layer, so that after etching The sidewall of the dummy gate layer is flush with the sidewall of the first electrode layer.
  • part of the first dummy gate layer is etched using isotropy.
  • the gate layer 1091 and the second dummy gate layer 1092 so that the sidewall of the etched first dummy gate layer 1091 is flush with the outer sidewall of the first electrode layer 120 and the etched second dummy gate layer
  • the sidewalls of layer 1092 are flush with the inner sidewalls of first electrode layer 120 .
  • the second channel part of the channel layer and the first channel part of the channel layer in contact with the upper and lower surfaces of the dummy gate layer are removed, and part of the channel remains. layer, forming a recess formed by the first electrode layer 120 or the second electrode layer 140, the remaining part of the channel layer and the dummy gate layer.
  • the depressions include a first depression 2031 and a second depression 2032.
  • the first depression 2031 is located outside the second depression 2032, that is, the first depression 2031 is located outside the enclosure structure 202, and the second depression 2032 is located inside the enclosure structure 202. Referring to FIG. 17 Show.
  • atomic layer etching can be used to remove the second channel portion 1081-2 of the first sub-channel layer 1081 outside the wall structure 202 and the first channel portion 1081-1 in contact with the upper and lower surfaces of the first dummy gate layer 1091. , form the first recess 2031 formed by the first electrode layer 120 or the second electrode layer 140, the first sub-channel layer 1081 and the first dummy gate layer 1091, and at the same time use atomic layer etching to remove the first recess located inside the wall structure 202
  • the second channel portion 1082-2 of the second sub-channel layer 1082 and the first channel portion 1082-1 in contact with the upper and lower surfaces of the second dummy gate layer 1092 are formed by the first electrode layer 120 or the second electrode layer 140 , the second recess 2032 formed by the second sub-channel layer 1082 and the second dummy gate layer 1091 .
  • an etchant having a selectivity ratio to the first electrode layer 120 and the second electrode layer 140 is selected so that the first electrode layer 120 and the second electrode layer 140 will not be damaged when the part of the channel layer is removed by etching. electrode layer 140 .
  • a dielectric material is filled in the depression to form the isolation spacer 150 .
  • a dielectric material can be deposited and etched in the first recess 2031 and the second recess 2032 to form an isolation spacer 150 , the formed isolation spacer 150 can reduce the parasitic capacitance of the semiconductor device and optimize the performance of the semiconductor device.
  • the dielectric material can be a low-K material.
  • an etchant having a selectivity ratio to the first electrode layer 120, the second electrode layer 140 and other film layers is selected so that the first electrode layer will not be damaged when the isolation spacer 150 is formed by etching. 120, the second electrode layer 140 and other film layers.
  • the process flow of the method for forming the isolation sidewall in the embodiment of the present application is relatively simple, and the formed sidewall structure is controllable, which provides a strong foundation for improving the performance of the semiconductor device.
  • the dummy gate layer is removed, and then an interface layer (not shown) and a high-K material layer 160 are sequentially conformally formed in the first channel portion.
  • the interface layer is used to improve the interface quality and further improve the performance of the semiconductor device, and the material of the interface layer can be silicon oxide.
  • the high-K material layer 160 continue to form the gate 170 in the first channel portion, as shown in FIG. 19 .
  • the material of the gate 170 may be a material with better conductivity, such as TiN, TaN, W and so on.
  • the isolation layer 180 is finally formed.
  • the isolation layer 180 is located on the substrate 110 and surrounds the first electrode layer 120, the channel layer, the gate 170, the second electrode layer 140, and the etch stop layer 101. and dielectric barrier 105 and other film layers to isolate and protect devices.
  • the material of the isolation layer 180 may be a dielectric material with better insulation, such as silicon oxide.
  • a first contact 191, a second contact 192, and a gate contact 193 that penetrate the isolation layer 180 and are electrically connected to the first electrode layer 120, the second electrode layer 140, and the gate 170 are formed using a through-hole process, as shown in FIG. Show.
  • a first electrode layer, a semiconductor layer including at least germanium, and a second electrode layer are sequentially formed on a substrate, and the first electrode layer is a source layer or a drain layer.
  • One of the electrode layers, the second electrode layer is the other of the source layer or the drain layer, and then a part of the semiconductor layer is etched from the side wall of the semiconductor layer to form an opening, the opening includes arc-shaped, arc-shaped gaps towards the outside, that is, the opening faces the outside, and then a channel layer is formed on the opening, the sidewall of the first electrode layer, and the sidewall of the second electrode layer, wherein the channel layer includes a first channel part located in the opening and a channel layer except The second channel part in the opening, the first channel part conforms to the opening, that is, the first channel part also includes an arc, and the dummy gate layer is filled in the first channel part including the arc, and the obtained dummy gate
  • the sidewall of the electrode layer is flush with the sidewall of the second channel part, and then the second channel part is used as a mask to etch part of the dummy gate layer from the sidewall of the dummy gate layer, so that the etched dummy gate layer
  • an embodiment of the present application further provides a semiconductor device.
  • FIG. 20 it is a schematic structural diagram of a semiconductor device provided by an embodiment of the present application.
  • the semiconductor device provided by the embodiment of the present application includes a substrate 110, a first electrode layer 120, a functional layer, and a second electrode layer 140 stacked in sequence, passing through the first electrode layer 120, the functional layer, and the second electrode layer 140 to the substrate 110 groove, the groove is surrounded by a wall structure composed of the first electrode layer 120, the functional layer and the second electrode layer 140,
  • the first electrode layer 120 is located on one side of the substrate 110;
  • the functional layer is located on the side of the first electrode layer 120 away from the substrate 110.
  • the functional layer includes a channel region 108, a gate region 170 and an isolation spacer region 150.
  • the channel region 108 includes an arc-shaped region, and the arc-shaped gap faces On the outside, both sides of the arc-shaped region are gate regions 170, and the isolation spacer region 150 is located above and below the gate region 170;
  • the second electrode layer 140 is located on the side of the functional layer away from the substrate 110.
  • the first electrode layer 120 is one of the source layer or the drain layer
  • the second electrode layer 140 is one of the source layer or the drain layer. another.
  • the semiconductor device further includes an isolation layer 180 , a first contact 191 , a second contact 192 and a gate contact 193 , as shown in FIG. 20 .
  • the isolation layer 180 is located on the substrate 110 and surrounds the film layers such as the first electrode layer 120, the channel layer, the gate 170, the second electrode layer 140, the etch stop layer 101 and the dielectric barrier 105, so as to isolate and protect the device .
  • the first contact 191, the second contact 192, and the gate contact 193 penetrate the isolation layer 180 and are electrically connected to the first electrode layer 120, the second electrode layer 140, and the gate 170, respectively, so that the first electrode layer 120, the second electrode layer 140 and grid 170 electrical extraction.
  • the second electrode layer 140 is covered with an etching stopper layer 101 and a dielectric barrier 105 .
  • an interface layer (not shown) and a high-K material layer 160 are further included between the gate region 170 and the channel region 108 .
  • each embodiment in this specification is described in a progressive manner, the same and similar parts of each embodiment can be referred to each other, and each embodiment focuses on the differences from other embodiments.
  • the description is relatively simple, and for relevant parts, please refer to the part of the description of the structural embodiments.

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  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

本申请实施例提供了一种半导体器件及其制造方法，在衬底上依次形成第一电极层、半导体层和第二电极层，而后从半导体层的侧壁刻蚀部分半导体层，形成开口，之后在开口、第一电极层的侧壁和第二电极层的侧壁上形成沟道层，其中，沟道层包括位于开口内的第一沟道部分和除开口内的第二沟道部分，在第一沟道部分填充伪栅极层，之后以第二沟道部分为掩蔽，从伪栅极层的侧壁刻蚀部分伪栅极层，而后去除第二沟道部分和与伪栅极层上下表面接触的第一沟道部分，形成由第一电极层或第二电极层、沟道层和伪栅极层形成的凹陷，在凹陷内填充介质材料，形成隔离侧墙，形成的隔离侧墙能够降低半导体器件的寄生电容，优化半导体器件的性能。

Description

一种半导体器件及其制造方法
本申请要求于2021年12月15日提交中国国家知识产权局、申请号为CN202111535102.X、发明名称为“一种半导体器件及其制造方法”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及半导体器件领域，特别涉及一种半导体器件及其制造方法。
背景技术
随着半导体技术的快速发展，垂直结构的半导体器件受到广泛关注。垂直结构的半导体器件的沟道电流的流向垂直于衬底所在的平面，具有低功耗等优点，可以增加缩小器件规模或增加集成电路的集成密度。
但是随着计算机技术等其他技术的急速发展，对于高性能的垂直结构的半导体器件的需求也越来越大，因此，现在亟需高性能的半导体器件。
发明内容
有鉴于此，本申请的目的在于提供一种半导体器件及其制造方法，提高垂直结构的半导体器件的性能。
为实现上述目的，本申请有如下技术方案：
本申请实施例提供一种半导体器件的制造方法，包括：
在衬底的一侧上依次形成第一电极层、至少包括锗的半导体层和第二电极层；所述第一电极层为源极层或漏极层中的一种，所述第二电极层为源极层或漏极层中的另一种；
从所述半导体层的侧壁刻蚀部分所述半导体层，以形成开口，所述开口包括弧形，所述弧形的缺口朝向外侧；
在所述开口、所述第一电极层的侧壁和所述第二电极层的侧壁上形成沟道层，其中，沟道层包括位于所述开口内的第一沟道部分和除所述开口内的第二沟道部分，所述第一沟道部分与所述开口共形；
在所述第一沟道部分填充伪栅极层，所述伪栅极层的侧壁与所述第二沟道部分的侧壁齐平；
从所述伪栅极层的侧壁刻蚀部分所述伪栅极层，以使刻蚀后的伪栅极层的侧壁与所述第一电极层的侧壁齐平；
去除所述第二沟道部分和与所述伪栅极层上下表面接触的第一沟道部分，形成由所述第一电极层或所述第二电极层、所述沟道层和所述伪栅极层形成的凹陷；
在所述凹陷内填充介质材料，形成隔离侧墙。
可选地，所述开口包括第一开口和第二开口，所述第一开口位于所述第二开口外侧，所述沟道层包括第一子沟道层和第二子沟道层，所述第一子沟道层位于所述第二子沟道层 的外侧；
所述从所述半导体层的侧壁刻蚀部分所述半导体层，以形成开口，所述开口包括弧形，所述弧形的缺口朝向外侧包括：
从所述半导体层的外侧侧壁利用原子层蚀刻刻蚀部分所述半导体层，形成包括弧形的第一开口，所述第一开口包括的弧形的缺口朝向外侧；
所述在所述开口、所述第一电极层的侧壁和所述第二电极层的侧壁上形成沟道层包括：
在所述第一开口、所述第一电极层的外侧侧壁和所述第二电极层的外侧侧壁上外延生长第一子沟道层；
所述从所述半导体层的侧壁刻蚀部分所述半导体层，以形成开口，所述开口包括弧形，所述弧形的缺口朝向外侧包括：
从所述半导体层的内侧侧壁利用原子层蚀刻刻蚀剩余的所述半导体层，形成包括弧形的第二开口，所述第二开口包括的弧形与所述第一开口包括的弧形共形；
所述在所述开口、所述第一电极层的侧壁和所述第二电极层的侧壁上形成沟道层包括：
在所述第二开口、所述第一电极层的内侧侧壁和所述第二电极层的内侧侧壁上外延生长第二子沟道层。
可选地，所述伪栅极层包括第一伪栅极层和第二伪栅极层，所述第一伪栅极层位于所述第二伪栅极层外侧；所述凹陷包括第一凹陷和第二凹陷，所述第一凹陷位于所述第二凹陷外侧；
所述在所述第一沟道部分填充伪栅极层包括：
在所述第一开口的第一沟道部分填充所述第一伪栅极层，在所述第二开口的第一沟道部分填充所述第二伪栅极层；
所述从所述伪栅极层的侧壁刻蚀部分所述伪栅极层包括：
从所述第一伪栅极层的侧壁和所述第二伪栅极层的侧壁利用各向同性刻蚀部分所述第一伪栅极层和所述第二伪栅极层；
所述去除所述第二沟道部分和与所述伪栅极层上下表面接触的第一沟道部分，形成由所述第一电极层或所述第二电极层、所述沟道层和所述伪栅极层形成的凹陷包括：
利用原子层蚀刻去除所述第一子沟道层的第二沟道部分和与所述第一伪栅极层上下表面接触的第一沟道部分，形成由第一电极层或所述第二电极层、所述第一子沟道层和所述第一伪栅极层形成的第一凹陷；
利用原子层蚀刻去除所述第二子沟道层的第二沟道部分和与所述第二伪栅极层上下表面接触的第一沟道部分，形成由第一电极层或所述第二电极层、所述第二子沟道层和所述第二伪栅极层形成的第二凹陷；
所述在所述凹陷内填充介质材料，形成隔离侧墙包括：
在所述第一凹陷和所述第二凹陷内沉积介质材料，形成隔离侧墙。
可选地，从所述半导体层的内侧侧壁利用原子层蚀刻刻蚀剩余的所述半导体层之前，所述方法还包括：
形成贯穿所述第一电极层、所述半导体层和所述第二电极层的沟槽，所述沟槽的四周 具有所述第一电极层、所述半导体层和所述第二电极层构成的围墙结构。
可选地，在从所述半导体层的侧壁刻蚀部分所述半导体层之前，所述方法还包括：
在所述第二电极层上依次形成刻蚀阻挡层、晶硅层和介质层；
对所述晶硅层和所述介质层进行处理，形成顶层结构，所述顶层结构包括晶硅核心区域和包围所述晶硅核心区域的介质挡墙，其中，所述晶硅核心区域对应所述沟槽；
所述形成贯穿所述第一电极层、所述半导体层和所述第二电极层的沟槽，所述沟槽的四周具有所述第一电极层、所述半导体层和所述第二电极层构成的围墙结构包括：
形成贯穿所述介质挡墙、所述晶硅核心区域、所述刻蚀阻挡层、所述第一电极层、所述半导体层和所述第二电极层的沟槽，所述沟槽的四周具有所述介质挡墙、所述刻蚀阻挡层、所述第一电极层、所述半导体层和所述第二电极层构成的围墙结构。
可选地，在所述凹陷内填充介质材料，形成隔离侧墙之后，所述方法还包括：
去除所述伪栅极层，在所述第一沟道部分形成栅极。
可选地，在所述第一沟道部分形成栅极之前，所述方法还包括：
在所述第一沟道部分依次共形形成界面层和高K材料层。
可选地，所述至少包括锗的半导体层的材料为锗或硅锗。
可选地，所述介质材料为低K材料。
本申请实施例提供一种半导体器件，包括：依次层叠的衬底、第一电极层、功能层和第二电极层；贯穿所述第一电极层、所述功能层和所述第二电极层至所述衬底的沟槽，所述沟槽的四周具有所述第一电极层、所述功能层和所述第二电极层构成的围墙结构；
所述第一电极层，位于所述衬底的一侧；
所述功能层，位于所述第一电极层远离所述衬底的一侧，所述功能层包括沟道区、栅极区和隔离侧墙区，所述沟道区包括弧形区域，弧形的缺口朝向外侧，所述弧形区域两侧为栅极区，所述隔离侧墙区位于所述栅极区的上方和下方；
所述第二电极层，位于所述功能层远离所述衬底的一侧，所述第一电极层为源极层或漏极层中的一种，所述第二电极层为源极层或漏极层中的另一种。
本申请实施例提供了一种半导体器件的制造方法，在衬底上依次形成第一电极层、至少包括锗的半导体层和第二电极层，第一电极层为源极层或漏极层中的一种，第二电极层为源极层或漏极层中的另一种，而后从半导体层的侧壁刻蚀部分半导体层，形成开口，开口包括弧形，弧形的缺口朝向外侧，即开口朝向外侧，之后在开口、第一电极层的侧壁和第二电极层的侧壁上形成沟道层，其中，沟道层包括位于开口内的第一沟道部分和除开口内的第二沟道部分，第一沟道部分与开口共形，即第一沟道部分也包括弧形，在包括弧形的第一沟道部分填充伪栅极层，得到的伪栅极层的侧壁与第二沟道部分的侧壁齐平，之后以第二沟道部分为掩蔽，从伪栅极层的侧壁刻蚀部分伪栅极层，以使刻蚀后的伪栅极层的侧壁与第一电极层的侧壁齐平，而后去除第二沟道部分和与伪栅极层上下表面接触的第一沟道部分，形成由第一电极层或第二电极层、沟道层和伪栅极层形成的凹陷，在凹陷内填充介质材料，形成隔离侧墙，形成的隔离侧墙能够降低半导体器件的寄生电容，优化半导体器件的性能。
附图说明
为了更清楚地说明本申请实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其它的附图。
图1示出了本申请实施例提供的一种半导体器件的制造方法的流程图；
图2-图20示出了根据本申请实施例提供的半导体器件的制造方法制造的半导体器件的结构示意图。
具体实施方式
为使本申请的上述目的、特征和优点能够更加明显易懂，下面结合附图对本申请的具体实施方式做详细的说明。
在下面的描述中阐述了很多具体细节以便于充分理解本申请，但是本申请还可以采用其它不同于在此描述的其它方式来实施，本领域技术人员可以在不违背本申请内涵的情况下做类似推广，因此本申请不受下面公开的具体实施例的限制。
其次，本申请结合示意图进行详细描述，在详述本申请实施例时，为便于说明，表示器件结构的剖面图会不依一般比例作局部放大，而且所述示意图只是示例，其在此不应限制本申请保护的范围。此外，在实际制作中应包含长度、宽度及深度的三维空间尺寸。
目前，对于高性能的垂直结构的半导体器件的需求也越来越大，例如由于当前的垂直结构的半导体器件的寄生电容较高，影响器件的性能。因此，现在亟需高性能的半导体器件。
基于此，本申请实施例提供了一种半导体器件的制造方法，在衬底上依次形成第一电极层、至少包括锗的半导体层和第二电极层，第一电极层为源极层或漏极层中的一种，第二电极层为源极层或漏极层中的另一种，而后从半导体层的侧壁刻蚀部分半导体层，形成开口，开口包括弧形，弧形的缺口朝向外侧，即开口朝向外侧，之后在开口、第一电极层的侧壁和第二电极层的侧壁上形成沟道层，其中，沟道层包括位于开口内的第一沟道部分和除开口内的第二沟道部分，第一沟道部分与开口共形，即第一沟道部分也包括弧形，在包括弧形的第一沟道部分填充伪栅极层，得到的伪栅极层的侧壁与第二沟道部分的侧壁齐平，之后以第二沟道部分为掩蔽，从伪栅极层的侧壁刻蚀部分伪栅极层，以使刻蚀后的伪栅极层的侧壁与第一电极层的侧壁齐平，而后去除第二沟道部分和与伪栅极层上下表面接触的第一沟道部分，形成由第一电极层或第二电极层、沟道层和伪栅极层形成的凹陷，在凹陷内填充介质材料，形成隔离侧墙，形成的隔离侧墙能够降低半导体器件的寄生电容，优化半导体器件的性能。
为了更好地理解本申请的技术方案和技术效果，以下将结合附图对具体的实施例进行详细的描述。
本申请实施例提供的半导体器件可以为存储器件或逻辑器件，本申请实施例提供的半 导体器件可以为垂直结构的晶体管器件，例如垂直结构的场效应晶体管(Field Effect Transistor，FET)，具体可以是金属氧化物半导体场效应晶体管(Metal-Oxide-Semiconductor Field-Effect Transistor，MOSFET)或隧穿场效应晶体管(Tunneling Field-Effect Transistor，TFET)。
参考图1所示，为本申请实施例提供的一种半导体器件的制造方法的流程图，该方法包括以下步骤：
S101，在衬底110的一侧上依次形成第一电极层120、至少包括锗的半导体层130和第二电极层140，参考图2所示。
在本申请的实施例中，可以在衬底110的一侧表面上依次形成第一电极层120、至少包括锗的半导体层130和第二电极层140。具体的，可以利用外延生长的方式形成第一电极层120、至少包括锗的半导体层130和第二电极层140。
衬底110可以是半导体衬底，例如硅衬底。在衬底110的一侧表面上形成第一电极层120之前，还可以对衬底110进行掺杂，形成阱层，参考图2所示，阱层是对衬底110的进行掺杂后形成的，相较于衬底110，掺杂后的阱层的导电性更高，能够与第一电极层120形成良好的电接触。掺杂可以是N型掺杂，掺杂元素为As或P，掺杂浓度为1e17-2e19/cm 3。掺杂也可以是P型掺杂，掺杂元素为B或In，掺杂浓度为1e17-2e19/cm 3。具体可以是在硅衬底上通过注入掺杂离子并进行退火工艺形成阱层。
作为一种示例，N型场效应晶体管(Field Effect Transistor，FET)注入P型杂质形成阱层，P型场效应晶体管(Field Effect Transistor，FET)注入N型杂质形成阱层。
在本申请的实施例中，在外延生长形成第一电极层120和第二电极层140之后，第一电极层120和第二电极层140的厚度约为10-50纳米(nm)，第一电极层120和第二电极层140为掺杂的半导体层，第一电极层120和第二电极层140的掺杂类型相同，可以为N型掺杂，也可以为P型掺杂。由于第一电极层120为源极层或漏极层中的一种，第二电极层140为源极层或漏极层中的另一种，可以通过掺杂使得第一电极层120和第二电极层140的导电性能更好，具体可以利用原位掺杂进行掺杂。
作为一种示例，针对P型FET器件，第一电极层120为P型掺杂的硅层，掺杂元素为B或In，掺杂浓度为1e18-1e21/cm 3。第二电极层120为P型掺杂的硅层，掺杂元素为B或In，掺杂浓度为1e18-1e21/cm 3。
作为另一种示例，针对N型FET器件，第一电极层120为N型掺杂的硅层，掺杂元素为As或P，掺杂浓度为1e18-1e21/cm 3。第二电极层120为N型掺杂的硅层，掺杂元素为As或P，掺杂浓度为1e18-1e21/cm 3。
在本申请的实施例中，在外延生长形成第一电极层120之后，可以在第一电极层120上外延生长至少包括锗的半导体层130。半导体层130的材料至少包括锗，例如可以是锗或硅锗。半导体层130的厚度范围可以是10-100纳米。
作为一种可能的实现方式，若半导体层130的材料为硅锗SiGe时，锗的掺杂比例范围为10％-50％，若掺杂比例过小，则不能形成C型结构的开口，若掺杂比例过多，则晶格缺陷变多，可能会降低存储器件的性能。
作为一种示例，在垂直于衬底110的方向上，锗的掺杂比例不变。
作为另一种示例，在垂直于衬底110的方向上，锗的掺杂比例先增大后减小，即中部区域Ge组分大于上下区域Ge组分。由于中部区域Ge组分高，上下区域Ge组分低，Ge组分高的刻蚀速率大于Ge组分低的刻蚀速率，因而可以通过后续的刻蚀更容易形成包括弧形的开口。
在本申请的实施例中，在外延形成半导体层130之后，继续在半导体层130外延形成第二电极层140，而后在第二电极层140上继续依次形成刻蚀阻挡层101、晶硅层102和介质层103，参考图3所示。具体可以利用沉积工艺形成刻蚀阻挡层101、晶硅层102和介质层103。
刻蚀阻挡层101覆盖第二电极层140，用于保护其下的第二电极层140，还能作为刻蚀阻挡层，避免在形成第二电极层140的第二接触时，刻蚀损伤第二电极层140。刻蚀阻挡层101的材料可以是氧化硅，可以是利用高温工艺形成的结晶质量较高的氧化硅，以便提高半导体器件的性能。刻蚀阻挡层101的厚度可以是1-10纳米。
在刻蚀阻挡层101上还覆盖有晶硅层102，晶硅层102的材料可以是多晶硅或非晶硅，厚度可以是50-150纳米。
在晶硅层102上还覆盖有介质层103。介质层103用于在制造器件时，隔离其他膜层和第二电极层140，还能用于在形成第二电极层140的第二接触后，隔离第二接触，保证第二接触仅与半导体器件中的第二电极层140形成电连接。介质层103的材料可以是氮化物，例如氮化硅，介质层103的厚度可以是30-100纳米。
在本申请的实施例中，在衬底110上依次形成第一电极层120、半导体层130、第二电极层140、刻蚀阻挡层101、晶硅层102和介质层103之后，还可以在介质层103上形成图案化的光刻胶层104，图案化的光刻胶层104定义半导体器件的晶硅核心区域1021，参考图4，图4为半导体器件在制造过程中的俯视结构示意图。
而后利用图案化的光刻胶层104刻蚀介质层103和晶硅层102，参考图5所示。图5为沿着半导体器件的AA’方向进行截面获得的半导体结构示意图。在刻蚀完毕后，去除光刻胶层104，保留刻蚀后的介质层103和晶硅核心区域1021，继续沉积介质层材料而后进行刻蚀形成包围晶硅核心区域1021的介质挡墙105，参考图6所示。也就是说，通过对晶硅层102和介质层103进行处理，形成包括晶硅核心区域1021和包围晶硅核心区域1021的介质挡墙105的顶层结构。
在具体进行刻蚀形成介质挡墙105时，还需要选用对刻蚀阻挡层101具有选择比的刻蚀剂，以便在刻蚀时，不会损伤刻蚀阻挡层101。
而后以介质挡墙105为掩蔽，对刻蚀阻挡层101、第二电极层140、半导体层130、第一电极层120和部分衬底110进行刻蚀，参考图7所示。在刻蚀完毕后，沉积介质材料直至覆盖全部的半导体器件，而后使用化学机械研磨(Chemical Mechanical Polishing，CMP)工艺和刻蚀工艺形成浅沟槽隔离(shallow trench isolation，STI)层106，参考图8所示。浅沟槽隔离(shallow trench isolation，STI)层106用于隔离该半导体器件和在集成电路统一制造时同时制造形成的其他半导体器件。介质材料可以是氧化硅。刻蚀工艺可 以是湿法刻蚀或干法刻蚀。
S102，从所述半导体层130的侧壁刻蚀部分所述半导体层130，以形成开口，参考图8和图13所示。
在本申请的实施例中，在刻蚀完毕刻蚀阻挡层101、第二电极层140、半导体层130、第一电极层120和部分衬底110之后，从半导体层130的侧壁刻蚀部分半导体层130，以形成开口，其中，开口包括弧形，弧形的缺口朝向外侧。
在本申请的实施例中，开口包括第一开口1071和第二开口1072，第一开口1071位于第二开口1072外侧。
参考图8所示，从半导体层130的外侧侧壁刻蚀部分半导体层130，形成包括弧形的第一开口1071，第一开口1071包括的弧形的缺口朝向外侧。包括弧形的第一开口1071类似字母C。弧形开口有利于后续在该开口内形成具有弧形的沟道层，该沟道层漏电流较小并且沟道长度较长，能够提升半导体器件的性能。
在垂直于衬底110所在的方向上，刻蚀剩余的半导体层130宽度逐渐减小后增大，即呈现上下宽度大于中部宽度的结构，类似字母X结构。
当半导体层130的材料为硅锗或锗时，利用原子层刻蚀从半导体层130的侧壁刻蚀半导体层130，刻蚀10-40nm，形成C型开口1071。在具体进行刻蚀时，选用对第一电极层120和第二电极层140具有选择比的刻蚀剂，以便在刻蚀形成开口1071时，不会损伤第一电极层120和第二电极层140。
在本申请的实施例中，参考图13所示，从半导体层130的内侧侧壁刻蚀剩余的半导体层130，形成包括弧形的第二开口1072，第二开口1072包括的弧形与第一开口1071包括的弧形共形，即第二开口1072包括的弧形的缺口也朝向外侧，包括弧形的第二开口1072也类似字母C。形成第二开口1072的工艺在第一开口1071内填充沟道层和伪栅极层之后，会在后续详细介绍。
S103，在所述开口、所述第一电极层120的侧壁和所述第二电极层140的侧壁上形成沟道层，参考图9和图14所示。
在本申请的实施例中，在刻蚀得到开口之后，可以在开口、第一电极层120的侧壁和第二电极层140的侧壁上形成沟道层，沟道层包括第一子沟道层1081和第二子沟道层1082，第一子沟道层1081位于第二子沟道层1082的外侧。其中，沟道层包括位于开口内的第一沟道部分和除开口内的第二沟道部分，第一沟道部分与开口共形。
参考图9所示，在第一开口1071、第一电极层120的外侧侧壁和第二电极层140的外侧侧壁上外延生长第一子沟道层1081。其中，第一子沟道层1081包括位于第一开口1071内的第一沟道部分1081-1和除第一开口1071内的第二沟道部分1081-2，第一沟道部分1081-1与第一开口1071共形，即第一沟道部分1081-1也包括弧形，并且弧形的缺口朝向外侧。
沟道层的厚度可以是3-30nm，沟道层材料可以是硅或硅锗，当沟道层的材料为硅锗时，锗的掺杂比例范围可以是10％-50％。
参考图14所示，在第二开口1072、第一电极层120的内侧侧壁和第二电极层140的 内侧侧壁上外延生长第二子沟道层1082。其中，第二子沟道层1082包括位于第二开口1072内的第一沟道部分1082-1和除第二开口1072内的第二沟道部分1082-2，第一沟道部分1082-1与第二开口1072共形，即第一沟道部分1082-1也包括弧形，并且弧形的缺口朝向外侧。
S104，在所述第一沟道部分填充伪栅极层，参考图10和图15所示。
在本申请的实施例中，在开口内填充沟道层的第一沟道部分之后，第一沟道部分未填满开口，可以继续在第一沟道部分填充伪栅极层，伪栅极层的侧壁与第二沟道部分的侧壁齐平。伪栅极层包括第一伪栅极层1091和第二伪栅极层1092，第一伪栅极层1091位于第二伪栅极层1092外侧。
参考图10所示，在第一开口1071的第一沟道部分1081-1填充第一伪栅极层1091。参考图15所示，在第二开口1072的第一沟道部分1082-1填充第一伪栅极层1092。
具体填充伪栅极层时可以是先沉积伪栅极层材料，后续进行刻蚀，使得伪栅极层的侧壁与第二沟道部分的侧壁齐平。在具体进行刻蚀时，还需要选用对沟道层具有选择比的刻蚀剂，以便在刻蚀时，不会损伤沟道层。伪栅极层的材料可以是氮氧化物。
在本申请的实施例中，从沟道层的外侧侧壁刻蚀得到第一开口1071，在第一开口1071、第一电极层120的外侧侧壁和第二电极层140的外侧侧壁上外延生长第一子沟道层1081，并且在第一子沟道层1081的第一沟道部分1081-1内填充第一伪栅极层1091之后，刻蚀介质挡墙105、晶硅核心区域1021、刻蚀阻挡层101、第一电极层120、半导体层130、第二电极层140和部分衬底110，形成贯穿介质挡墙105、晶硅核心区域1021、刻蚀阻挡层101、第一电极层120、半导体层130和第二电极层140的沟槽201，晶硅核心区域1021对应沟槽201，即晶硅核心区域1021定义沟槽201的位置，沟槽201的四周具有介质挡墙105、刻蚀阻挡层101、第一电极层120、半导体层130和第二电极层140构成的围墙结构202，参考图11和图12所示。图11为半导体器件在制造过程中的俯视结构示意图，图12为沿着半导体器件的AA’方向进行截面获得的半导体结构示意图。
在本申请的实施例中，在刻蚀得到沟槽201，形成围墙结构202之后，沟槽201为围墙结构202的内侧，相对的，围墙结构202具有外侧。围墙结构202的外侧已经形成第一开口1071，并在围墙结构202的外侧和第一开口1071内形成有第一子沟道层1081和第一伪栅极层1091。
参考图13所示，在围墙结构202的内侧，从半导体层130的内侧侧壁刻蚀剩余的半导体层130，形成包括弧形的第二开口1072，第二开口1072包括的弧形与第一开口1071包括的弧形共形，即第二开口1072包括的弧形的缺口也朝向外侧，包括弧形的第二开口1072也类似字母C。形成第二开口1072的工艺在第一开口1071内填充沟道层和伪栅极层，并刻蚀得到沟槽201之后。
参考图14所示，与外延生长第一子沟道层1081的工艺相同，在围墙结构202的内侧，在第二开口1072、第一电极层120的内侧侧壁和第二电极层140的内侧侧壁上外延生长第二子沟道层1082。其中，第二子沟道层1082包括位于第二开口1072内的第一沟道部分1082-1和除第二开口1072内的第二沟道部分1082-2，第一沟道部分1082-1与第二开口 1072共形，即第一沟道部分1082-1也包括弧形，并且弧形的缺口朝向外侧。
第一子沟道层1081和第二子沟道层1082的厚度都可以是3-15nm，材料可以是硅或硅锗，当材料为硅锗时，锗的掺杂比例范围可以是10％-30％。
参考图15所示，在围墙结构202的内侧，在第二开口1072的第一沟道部分1082-1填充第一伪栅极层1092。伪栅极层的材料可以是氮氧化物。
在形成第一伪栅极层1092后，沉积介质材料直至覆盖全部的半导体器件，而后使用化学机械研磨(Chemical Mechanical Polishing，CMP)工艺和刻蚀工艺在沟槽201内形成浅沟槽隔离(shallow trench isolation，STI)层106，参考图16所示。介质材料可以是氧化硅。刻蚀工艺可以是湿法刻蚀或干法刻蚀。
S105，从所述伪栅极层的侧壁刻蚀部分所述伪栅极层，参考图16所示。
在本申请的实施例中，以围墙结构202的内侧和外侧的沟道层的第二沟道部分为掩蔽，从伪栅极层的侧壁刻蚀部分伪栅极层，以使刻蚀后的伪栅极层的侧壁与第一电极层的侧壁齐平。
参考图16所示，从位于围墙结构202外侧的第一伪栅极层1091的侧壁和位于围墙结构202内侧的第二伪栅极层1092的侧壁利用各向同性刻蚀部分第一伪栅极层1091和第二伪栅极层1092，使得刻蚀后的第一伪栅极层1091的侧壁与第一电极层120的外侧侧壁齐平以及刻蚀后的第二伪栅极层1092的侧壁与第一电极层120的内侧侧壁齐平。
S106，去除所述第二沟道部分和与所述伪栅极层上下表面接触的第一沟道部分，参考图17所示。
在本申请的实施例中，以伪栅极层为掩蔽，去除沟道层的第二沟道部分和与伪栅极层上下表面接触的沟道层的第一沟道部分，保留部分沟道层，形成由第一电极层120或第二电极层140、剩余的部分沟道层和伪栅极层形成的凹陷。
凹陷包括第一凹陷2031和第二凹陷2032，第一凹陷2031位于第二凹陷2032外侧，即第一凹陷2031位于围墙结构202的外侧，第二凹陷2032位于围墙结构202的内侧，参考图17所示。
具体可以利用原子层蚀刻去除位于围墙结构202外侧的第一子沟道层1081的第二沟道部分1081-2和与第一伪栅极层1091上下表面接触的第一沟道部分1081-1，形成由第一电极层120或第二电极层140、第一子沟道层1081和第一伪栅极层1091形成的第一凹陷2031，同时利用原子层蚀刻去除位于围墙结构202内侧的第二子沟道层1082的第二沟道部分1082-2和与第二伪栅极层1092上下表面接触的第一沟道部分1082-1，形成由第一电极层120或第二电极层140、第二子沟道层1082和第二伪栅极层1091形成的第二凹陷2032。
在具体进行刻蚀时，选用对第一电极层120和第二电极层140具有选择比的刻蚀剂，以便在刻蚀去除部分沟道层时，不会损伤第一电极层120和第二电极层140。
S107，在所述凹陷内填充介质材料，形成隔离侧墙150，参考图18所示。
在本申请的实施例中，在形成凹陷之后，在凹陷内填充介质材料，形成隔离侧墙150。具体可以在第一凹陷2031和第二凹陷2032内沉积介质材料并进行刻蚀，形成隔离侧墙150，形成的隔离侧墙150能够降低半导体器件的寄生电容，优化半导体器件的性能。介质材料 可以为低K材料。
在具体进行刻蚀时，选用对第一电极层120、第二电极层140和其他膜层具有选择比的刻蚀剂，以便在刻蚀形成隔离侧墙150时，不会损伤第一电极层120、第二电极层140和其他膜层。
由此可见，本申请实施例形成隔离侧墙的方法工艺流程较为简单，并且形成的侧墙结构可控，为提升半导体器件的性能提供了有力基础。
在本申请的实施例中，在形成隔离侧墙150之后，去除伪栅极层，而后在第一沟道部分依次共形形成界面层(图未示出)和高K材料层160。界面层用于改善界面质量，进一步提高半导体器件的性能，界面层的材料可以为氧化硅。在形成高K材料层160后，继续在第一沟道部分形成栅极170，参考图19所示。栅极170的材料可以是导电性较好的材料，例如TiN、TaN和W等。
在本申请的实施例中，最后形成隔离层180，隔离层180位于衬底110上，并且包围第一电极层120、沟道层、栅极170、第二电极层140、刻蚀阻挡层101和介质挡墙105等膜层，以隔离和保护器件。隔离层180的材料可以是绝缘性较好的介质材料，例如氧化硅。之后利用通孔工艺形成贯穿隔离层180并且分别与第一电极层120、第二电极层140和栅极170电连接的第一接触191、第二接触192和栅极接触193，参考图20所示。
综上所述，本申请实施例提供的半导体器件的制造方法，在衬底上依次形成第一电极层、至少包括锗的半导体层和第二电极层，第一电极层为源极层或漏极层中的一种，第二电极层为源极层或漏极层中的另一种，而后从半导体层的侧壁刻蚀部分半导体层，形成开口，开口包括弧形，弧形的缺口朝向外侧，即开口朝向外侧，之后在开口、第一电极层的侧壁和第二电极层的侧壁上形成沟道层，其中，沟道层包括位于开口内的第一沟道部分和除开口内的第二沟道部分，第一沟道部分与开口共形，即第一沟道部分也包括弧形，在包括弧形的第一沟道部分填充伪栅极层，得到的伪栅极层的侧壁与第二沟道部分的侧壁齐平，之后以第二沟道部分为掩蔽，从伪栅极层的侧壁刻蚀部分伪栅极层，以使刻蚀后的伪栅极层的侧壁与第一电极层的侧壁齐平，而后去除第二沟道部分和与伪栅极层上下表面接触的第一沟道部分，形成由第一电极层或第二电极层、沟道层和伪栅极层形成的凹陷，在凹陷内填充介质材料，形成隔离侧墙，形成的隔离侧墙能够降低半导体器件的寄生电容，优化半导体器件的性能。
基于以上实施例提供的半导体器件的制造方法，本申请实施例还提供了一种半导体器件。参考图20所示，为本申请实施例提供的一种半导体器件的结构示意图。
本申请实施例提供的半导体器件包括依次层叠的衬底110、第一电极层120、功能层和第二电极层140，贯穿第一电极层120、功能层和第二电极层140至衬底110的沟槽，沟槽的四周具有第一电极层120、功能层和第二电极层140构成的围墙结构，
第一电极层120，位于衬底110的一侧；
功能层，位于第一电极层120远离衬底110的一侧，功能层包括沟道区108、栅极区170和隔离侧墙区150，沟道区108包括弧形区域，弧形的缺口朝向外侧，弧形区域两侧为 栅极区170，隔离侧墙区150位于栅极区170的上方和下方；
第二电极层140，位于功能层远离衬底110的一侧，第一电极层120为源极层或漏极层中的一种，第二电极层140为源极层或漏极层中的另一种。
在本申请的实施例中，半导体器件还包括隔离层180、第一接触191、第二接触192和栅极接触193，参考图20所示。
隔离层180位于衬底110上，并且包围第一电极层120、沟道层、栅极170、第二电极层140、刻蚀阻挡层101和介质挡墙105等膜层，以隔离和保护器件。
第一接触191、第二接触192和栅极接触193贯穿隔离层180分别与第一电极层120、第二电极层140和栅极170电连接，以便进行第一电极层120、第二电极层140和栅极170的电引出。
在本申请的实施例中，第二电极层140上覆盖有刻蚀阻挡层101和介质挡墙105。
在本申请的实施例中，栅极区170和沟道区108之间还包括界面层(图未示出)和高K材料层160。
本说明书中的各个实施例均采用递进的方式描述，各个实施例之间相同相似的部分互相参见即可，每个实施例重点说明的都是与其他实施例的不同之处。尤其，对于方法实施例而言，由于其基本相似于结构实施例，所以描述得比较简单，相关之处参见结构实施例的部分说明即可。
上述各个附图对应的流程或结构的描述各有侧重，某个流程或结构中没有详述的部分，可以参见其他流程或结构的相关描述。
以上所述仅是本申请的优选实施方式，虽然本申请已以较佳实施例披露如上，然而并非用以限定本申请。任何熟悉本领域的技术人员，在不脱离本申请技术方案范围情况下，都可利用上述揭示的方法和技术内容对本申请技术方案做出许多可能的变动和修饰，或修改为等同变化的等效实施例。因此，凡是未脱离本申请技术方案的内容，依据本申请的技术实质对以上实施例所做的任何的简单修改、等同变化及修饰，均仍属于本申请技术方案保护的范围内。
本申请在上述各方面提供的实现方式的基础上，还可以进行进一步组合以提供更多实现方式。

Claims (10)

  1. 一种半导体器件的制造方法，其特征在于，包括：
    在衬底的一侧上依次形成第一电极层、至少包括锗的半导体层和第二电极层；所述第一电极层为源极层或漏极层中的一种，所述第二电极层为源极层或漏极层中的另一种；
    从所述半导体层的侧壁刻蚀部分所述半导体层，以形成开口，所述开口包括弧形，所述弧形的缺口朝向外侧；
    在所述开口、所述第一电极层的侧壁和所述第二电极层的侧壁上形成沟道层，其中，沟道层包括位于所述开口内的第一沟道部分和除所述开口内的第二沟道部分，所述第一沟道部分与所述开口共形；
    在所述第一沟道部分填充伪栅极层，所述伪栅极层的侧壁与所述第二沟道部分的侧壁齐平；
    从所述伪栅极层的侧壁刻蚀部分所述伪栅极层，以使刻蚀后的伪栅极层的侧壁与所述第一电极层的侧壁齐平；
    去除所述第二沟道部分和与所述伪栅极层上下表面接触的第一沟道部分，形成由所述第一电极层或所述第二电极层、所述沟道层和所述伪栅极层形成的凹陷；
    在所述凹陷内填充介质材料，形成隔离侧墙。
  2. 根据权利要求1所述的制造方法，其特征在于，所述开口包括第一开口和第二开口，所述第一开口位于所述第二开口外侧，所述沟道层包括第一子沟道层和第二子沟道层，所述第一子沟道层位于所述第二子沟道层的外侧；
    所述从所述半导体层的侧壁刻蚀部分所述半导体层，以形成开口，所述开口包括弧形，所述弧形的缺口朝向外侧包括：
    从所述半导体层的外侧侧壁利用原子层蚀刻刻蚀部分所述半导体层，形成包括弧形的第一开口，所述第一开口包括的弧形的缺口朝向外侧；
    所述在所述开口、所述第一电极层的侧壁和所述第二电极层的侧壁上形成沟道层包括：
    在所述第一开口、所述第一电极层的外侧侧壁和所述第二电极层的外侧侧壁上外延生长第一子沟道层；
    所述从所述半导体层的侧壁刻蚀部分所述半导体层，以形成开口，所述开口包括弧形，所述弧形的缺口朝向外侧包括：
    从所述半导体层的内侧侧壁利用原子层蚀刻刻蚀剩余的所述半导体层，形成包括弧形的第二开口，所述第二开口包括的弧形与所述第一开口包括的弧形共形；
    所述在所述开口、所述第一电极层的侧壁和所述第二电极层的侧壁上形成沟道层包括：
    在所述第二开口、所述第一电极层的内侧侧壁和所述第二电极层的内侧侧壁上外延生长第二子沟道层。
  3. 根据权利要求2所述的制造方法，其特征在于，所述伪栅极层包括第一伪栅极层和第二伪栅极层，所述第一伪栅极层位于所述第二伪栅极层外侧；所述凹陷包括第一凹陷和第二凹陷，所述第一凹陷位于所述第二凹陷外侧；
    所述在所述第一沟道部分填充伪栅极层包括：
    在所述第一开口的第一沟道部分填充所述第一伪栅极层，在所述第二开口的第一沟道部分填充所述第二伪栅极层；
    所述从所述伪栅极层的侧壁刻蚀部分所述伪栅极层包括：
    从所述第一伪栅极层的侧壁和所述第二伪栅极层的侧壁利用各向同性刻蚀部分所述第一伪栅极层和所述第二伪栅极层；
    所述去除所述第二沟道部分和与所述伪栅极层上下表面接触的第一沟道部分，形成由所述第一电极层或所述第二电极层、所述沟道层和所述伪栅极层形成的凹陷包括：
    利用原子层蚀刻去除所述第一子沟道层的第二沟道部分和与所述第一伪栅极层上下表面接触的第一沟道部分，形成由第一电极层或所述第二电极层、所述第一子沟道层和所述第一伪栅极层形成的第一凹陷；
    利用原子层蚀刻去除所述第二子沟道层的第二沟道部分和与所述第二伪栅极层上下表面接触的第一沟道部分，形成由第一电极层或所述第二电极层、所述第二子沟道层和所述第二伪栅极层形成的第二凹陷；
    所述在所述凹陷内填充介质材料，形成隔离侧墙包括：
    在所述第一凹陷和所述第二凹陷内沉积介质材料，形成隔离侧墙。
  4. 根据权利要求3所述的制造方法，其特征在于，从所述半导体层的内侧侧壁利用原子层蚀刻刻蚀剩余的所述半导体层之前，所述方法还包括：
    形成贯穿所述第一电极层、所述半导体层和所述第二电极层的沟槽，所述沟槽的四周具有所述第一电极层、所述半导体层和所述第二电极层构成的围墙结构。
  5. 根据权利要求4所述的制造方法，其特征在于，在从所述半导体层的侧壁刻蚀部分所述半导体层之前，所述方法还包括：
    在所述第二电极层上依次形成刻蚀阻挡层、晶硅层和介质层；
    对所述晶硅层和所述介质层进行处理，形成顶层结构，所述顶层结构包括晶硅核心区域和包围所述晶硅核心区域的介质挡墙，其中，所述晶硅核心区域对应所述沟槽；
    所述形成贯穿所述第一电极层、所述半导体层和所述第二电极层的沟槽，所述沟槽的四周具有所述第一电极层、所述半导体层和所述第二电极层构成的围墙结构包括：
    形成贯穿所述介质挡墙、所述晶硅核心区域、所述刻蚀阻挡层、所述第一电极层、所述半导体层和所述第二电极层的沟槽，所述沟槽的四周具有所述介质挡墙、所述刻蚀阻挡层、所述第一电极层、所述半导体层和所述第二电极层构成的围墙结构。
  6. 根据权利要求1所述的制造方法，其特征在于，在所述凹陷内填充介质材料，形成隔离侧墙之后，所述方法还包括：
    去除所述伪栅极层，在所述第一沟道部分形成栅极。
  7. 根据权利要求6所述的制造方法，其特征在于，在所述第一沟道部分形成栅极之前，所述方法还包括：
    在所述第一沟道部分依次共形形成界面层和高K材料层。
  8. 根据权利要求1-7任意一项所述的制造方法，其特征在于，所述至少包括锗的半导体层的材料为锗或硅锗。
  9. 根据权利要求1-7任意一项所述的制造方法，其特征在于，所述介质材料为低K材料。
  10. 一种半导体器件，其特征在于，包括：依次层叠的衬底、第一电极层、功能层和第二电极层；贯穿所述第一电极层、所述功能层和所述第二电极层至所述衬底的沟槽，所述沟槽的四周具有所述第一电极层、所述功能层和所述第二电极层构成的围墙结构；
    所述第一电极层，位于所述衬底的一侧；
    所述功能层，位于所述第一电极层远离所述衬底的一侧，所述功能层包括沟道区、栅极区和隔离侧墙区，所述沟道区包括弧形区域，弧形的缺口朝向外侧，所述弧形区域两侧为栅极区，所述隔离侧墙区位于所述栅极区的上方和下方；
    所述第二电极层，位于所述功能层远离所述衬底的一侧，所述第一电极层为源极层或漏极层中的一种，所述第二电极层为源极层或漏极层中的另一种。
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