WO2023104210A1 - 数据传输芯片及电子设备 - Google Patents

数据传输芯片及电子设备 Download PDF

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Publication number
WO2023104210A1
WO2023104210A1 PCT/CN2022/138258 CN2022138258W WO2023104210A1 WO 2023104210 A1 WO2023104210 A1 WO 2023104210A1 CN 2022138258 W CN2022138258 W CN 2022138258W WO 2023104210 A1 WO2023104210 A1 WO 2023104210A1
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Prior art keywords
data transmission
data
transmission chip
sampling
signals
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PCT/CN2022/138258
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English (en)
French (fr)
Inventor
牛元君
魏志煌
黄君利
居海强
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华为技术有限公司
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Publication of WO2023104210A1 publication Critical patent/WO2023104210A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163—Interprocessor communication
    • G06F15/17—Interprocessor communication using an input/output type connection, e.g. channel, I/O port
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Definitions

  • the present application relates to the field of electronic technology, in particular to a data transmission chip and electronic equipment.
  • electronic equipment generally includes multiple complex programmable logic devices (complex programmable logic devices, CPLDs), and different CPLDs generally communicate through multiple interfaces.
  • complex programmable logic devices complex programmable logic devices, CPLDs
  • CPLDs complex programmable logic devices
  • each interface in a CPLD needs to be connected to the corresponding interface in another CPLD through multiple signal lines, communication between CPLDs through multiple interfaces will result in a large number of signal lines between CPLDs, and the electronic equipment The structure is more complicated.
  • the present application provides a data transmission chip and an electronic device, which can solve the technical problem that the structure of the electronic device is complicated due to the large number of signal lines between the chips in the electronic device.
  • a data transmission chip in a first aspect, includes a high-speed serial interface and a low-speed interface; the low-speed interface is used to receive multiple first signals; the high-speed serial interface is used to receive multiple first signals Serially transmit to another data transmission chip in the form of data frames; wherein, the data transmission rate of the high-speed serial interface is higher than that of the low-speed interface.
  • the high-speed serial interface in the data transmission chip can serially transmit multiple first signals to another data transmission chip in the form of data frames, it can effectively reduce the number of signal lines that need to be arranged between the data transmission chips, Furthermore, the pin resource of the data transmission chip is saved, and the structure of the electronic device is simplified. Furthermore, since the data transmission rate of the high-speed serial interface is relatively high, the transmission efficiency of the multi-channel signal can be effectively ensured.
  • the data transmission chip may include one or more low-speed interfaces, and each low-speed interface may have multiple pins.
  • the multiple first signals mentioned above may be signals received by multiple different low-speed interfaces, or may be signals received by different pins of the same low-speed interface.
  • the high-speed serial interface is configured to generate a data frame based on data obtained by sampling multiple channels of first signals. Since the high-speed serial interface can carry data of multiple channels of first signals in one data frame, the transmission efficiency and flexibility of signals are effectively improved.
  • the high-speed serial interface is configured to perform parallel sampling on multiple channels of first signals based on the frequency of a clock signal of the data transmission chip.
  • the high-speed serial interface can perform parallel sampling on multiple first signals according to the first sampling frequency
  • the first sampling frequency can be less than or equal to the frequency of the clock signal of the data transmission chip, and can be K1 of the transmission frequency of the data frame times, K1 is an integer greater than 1.
  • the data sampled by the high-speed serial interface may include a plurality of first sampling sequences arranged in sequence according to the sampling time, and each first sampling sequence includes performing a multi-channel first signal sampling sequence. Multi-bit sampling value obtained by one parallel sampling.
  • the high-speed serial interface can synchronously send the data frame during the process of generating the data frame based on the sampled data, without waiting for each field of the data frame to be encapsulated before sending.
  • the data transmission efficiency is effectively improved.
  • the high-speed serial interface is also used to receive multiple second signals serially sent by another data transmission chip in the form of data frames, and transmit the multiple second signals to the low-speed interface.
  • the high-speed serial interface in the data transmission chip provided by the present application not only has the function of data transmission, but also has the function of data reception, that is, the high-speed serial interface can realize bidirectional transmission of data.
  • the data transmission chip may include multiple low-speed interfaces.
  • the data frame received by the high-speed serial interface also carries the identifier of each second signal, and the high-speed serial interface can distinguish each second signal based on the identifier, and divide each second signal The signal is transmitted to the corresponding low-speed interface.
  • the identifier of the second signal may also be referred to as a tag.
  • another data transmission chip may encapsulate the multiple channels of second signals in a data frame according to a pre-agreed fixed order, and after receiving the data frame, the high-speed serial interface may identify the multiple channels of signals according to the fixed order. the second signal, and send the multiple second signals to corresponding low-speed interfaces respectively.
  • the high-speed serial interface is also used to sample the data frame sent by another data transmission chip based on the frequency of the clock signal of the data transmission chip, and restore the multi-channel second frame based on the sampled data. Signal.
  • the high-speed serial interface can perform parallel sampling on multiple second signals according to the second sampling frequency
  • the second sampling frequency can be less than or equal to the frequency of the clock signal of the data transmission chip, or can be the clock signal of the data transmission chip 2 times the frequency.
  • the second sampling frequency may be K2 times the frequency of the clock signal of another data transmission chip, where K2 is an integer greater than 1. Since the second sampling frequency is an integer multiple of the frequency of the clock signal of another data transmission chip, it can ensure that the high-speed serial interface can accurately sample the data carried in the data frame.
  • the data obtained by sampling the data frame sent by another data transmission chip includes: a plurality of second sampling sequences arranged in order of sampling time, each second sampling sequence includes Multi-bit sampling values; the high-speed serial interface is also used to sequentially obtain one-bit sampling values from each second sampling sequence, and recover one second signal based on the sequentially obtained multi-bit sampling values.
  • the high-speed serial interface is used to sequentially obtain the j-th sampling value from each second sampling sequence according to the order in which the multiple second sampling sequences are arranged. , recover the j-th second signal based on the multi-bit sampling values obtained in sequence, where j is a positive integer, and j is not greater than the total number of multiple second signals.
  • the data transmission chip and another data transmission chip can be located on the same printed circuit board (printed circuit board, PCB); or, the data transmission chip and another data transmission chip can be located on different PCBs. . That is, in the solution provided by the present application, the high-speed serial interface in the data transmission chip can realize data communication within the board, and can also realize data communication between boards.
  • the data frame may include: a frame header, a plurality of data fields, and a gap field after each data field; wherein, the frame header includes consecutive N-bit first numerical values and M A second numerical value of 1 bit, a plurality of data fields are used to carry data obtained by sampling multiple first signals, and the length of each data field is W bits, the gap field includes a second numerical value of M bits, and N is greater than W A positive integer, M is a positive integer smaller than W.
  • the difference between N and W may be greater than or equal to 2, and the value of M may be 1.
  • the first value in the data frame may be 1, and the second value may be 0.
  • the data frame may further include: a check field positioned after multiple data fields, and a gap field positioned after the check field; the check field is used to carry a check bit, and the check field The length of the verification field is equal to the length of the data field.
  • the check bit carried by the check field is obtained after the high-speed serial interface uses a check algorithm to calculate the data carried by multiple data fields.
  • Another data transmission chip obtains the data carried in multiple data fields, and after obtaining the check bit carried by the check field, the check bit can be used to check the acquired data to ensure that the received data accuracy.
  • the second aspect provides a data transmission method, which is applied to the data transmission chip provided in the first aspect, and the method includes: receiving multiple first signals through a low-speed interface; converting the multiple first signals into data through a high-speed serial interface The data transmission rate of the high-speed serial interface is higher than the data transmission rate of the low-speed interface.
  • the method may further include: sampling multiple channels of first signals, and generating a data frame based on the sampled data.
  • the process of sampling the multiple first signals may include: performing parallel sampling on the multiple first signals based on a frequency of a clock signal of the data transmission chip.
  • the sampled data includes a plurality of first sampling sequences arranged in sequence according to the sampling time, and each first sampling sequence includes a parallel sampling of multiple first signals to obtain The multi-bit sampling value of .
  • the method may further include: receiving multiple second signals serially sent by another data transmission chip in the form of data frames through the high-speed serial interface, and transmitting the multiple second signals to Signals are routed to this low-speed interface.
  • the method may further include: sampling a data frame sent by another data transmission chip based on the frequency of the clock signal of the data transmission chip, and restoring the multiplex second frame based on the sampled data. Signal.
  • the data obtained by sampling the data frame sent by the other data transmission chip includes: a plurality of second sampling sequences arranged in sequence according to the sampling time, each second sampling sequence Including multi-bit sampling values; restoring the multi-channel second signal based on the data obtained by sampling includes: sequentially obtaining one bit sampling value from each second sampling sequence, and restoring one channel of second signal based on the sequentially obtained multi-bit sampling values Signal.
  • a data transmission chip in a third aspect, includes: a programmable logic circuit and/or program instructions, and the controller is used to implement the functions of the data transmission chip provided in the first aspect.
  • a data transmission chip in a fourth aspect, includes at least one module, and the at least one module can be used to implement the functions of the data transmission chip provided in the first aspect above.
  • a computer-readable storage medium where instructions are stored in the computer-readable storage medium, and the instructions are executed by a processing circuit to implement the data transmission method provided in the second aspect above.
  • a computer program product containing instructions is provided, and when the computer program product is run on a processing circuit, the processing circuit is made to execute the data transmission method provided in the second aspect above.
  • an electronic device in a seventh aspect, includes a data transmission chip, and the data transmission chip is used to realize the function of the data transmission chip provided in the first aspect.
  • the electronic device may include multiple data transmission chips, and high-speed serial interfaces of two data transmission chips may be connected through an electrical signal transmission medium.
  • the present application provides a data transmission chip and electronic equipment.
  • the low-speed interface of the data transmission chip is used to receive multiple first signals
  • the high-speed serial interface of the data transmission chip is used to serially transmit the multiple first signals to another Data transmission chip. Since multiple signals can be serially transmitted between the data transmission chips in the form of data frames, the number of signal lines required to be arranged between the data transmission chips can be effectively reduced, thereby simplifying the structure of the electronic device. Furthermore, since the data transmission rate of the high-speed serial interface is relatively high, the transmission efficiency of the multiple first signals can be effectively ensured.
  • FIG. 1 is a schematic structural diagram of an electronic device provided in an embodiment of the present application.
  • FIG. 2 is a schematic structural diagram of another electronic device provided by an embodiment of the present application.
  • FIG. 3 is a schematic diagram of a data structure of a data frame provided by an embodiment of the present application.
  • FIG. 4 is a schematic diagram of a partial structure of a data frame provided by an embodiment of the present application.
  • FIG. 5 is a schematic diagram of sampling a signal to generate a data frame according to an embodiment of the present application
  • FIG. 6 is a schematic diagram of a data transmission chip sending a data frame provided by an embodiment of the present application.
  • FIG. 7 is a schematic diagram of a data transmission chip receiving a data frame provided by an embodiment of the present application.
  • FIG. 8 is a schematic structural diagram of another electronic device provided by an embodiment of the present application.
  • FIG. 9 is a schematic diagram of a CPU sending a control instruction to a low-speed device through a data transmission chip provided by an embodiment of the present application.
  • FIG. 10 is a schematic diagram of a low-speed device sending an execution result to the CPU through a data transmission chip provided by the embodiment of the present application;
  • Fig. 11 is a schematic structural diagram of another electronic device provided by the embodiment of the present application.
  • Fig. 12 is a schematic diagram of a master control device sending a control command to a low-speed device through a data transmission chip provided by an embodiment of the present application;
  • Fig. 13 is a schematic diagram of a low-speed device sending an execution result to the main control device through a data transmission chip provided by the embodiment of the present application;
  • FIG. 14 is a schematic structural diagram of a data transmission chip provided by an embodiment of the present application.
  • the embodiment of the present application provides a data transmission chip. After the data transmission chip receives multiple signals through a low-speed interface, it can serialize the multiple signals in the form of data frames through a high-speed serial interface. Transfer to another data transfer chip. Therefore, while ensuring a high data transmission rate, the number of signal lines between data transmission chips can be effectively reduced.
  • Fig. 1 is a schematic structural diagram of an electronic device provided by an embodiment of the present application.
  • the electronic device may be a computing device such as a server, an edge device, or a personal computer (PC), or may be a mobile terminal such as a smart phone, or It can be a switching device such as a switch or a router.
  • the electronic device includes two data transmission chips 01a and 01b, and each data transmission chip has a high speed serial interface (high speed serial port, Hisport) and a low speed interface.
  • the high-speed serial interface 011a of the data transmission chip 01a and the high-speed serial interface 011b of the data transmission chip 01b can be connected through the electrical signal transmission medium 03, and can be serialized in the form of data frames through the electrical signal transmission medium 03. Transmits multiplexed signals for low-speed interfaces. That is, the high-speed serial interface in the data transmission chip can carry multiple signals of the low-speed interface in the form of data frames.
  • the high-speed serial interface 011a of the data transmission chip 01a is used to package the multiple first signals received by the low-speed interface 012a into a data frame, and serially transmit the data frame to the high-speed serial interface of the data transmission chip 01b.
  • Serial interface 011b is used to decapsulate (also referred to as decoding) the received data frame to recover the multiple first signals, and transmit the multiple first signals to the low-speed interface 012b.
  • both the high-speed serial interface 011a and the high-speed serial interface 011b may include connection ports (such as pins) for connecting to the electrical signal transmission medium 03, and logic circuits for processing data.
  • the high-speed serial interface 011a may include a logic circuit for packaging multiple channels of first signals into data frames
  • the high-speed serial interface 011b may include a logic circuit for decapsulating the data frames.
  • the data transmission rate of the high-speed serial interface in each data transmission chip is higher than the data transmission rate of the low-speed interface.
  • the data transfer rate of a high-speed serial interface can be 10 times that of a low-speed interface, or even higher.
  • the data transmission rate may refer to the number of bits (bits) of data transmitted per unit time, and the unit time may be 1 second.
  • the unit of the data transmission rate may be bits per second (bps).
  • the low-speed interface described in the embodiments of the present application is relative to the high-speed serial interface.
  • the low-speed interface in each data transmission chip may include one or more of the following interfaces: parallel input and output (input output, IO) interface, serial peripheral interface (serial peripheral interface, SPI), internal integrated circuit (inter - integrated circuit (IIC or I 2 C) interface, universal asynchronous receiver/transmitter (universal asynchronous receiver/transmitter, UART) interface and local bus (local bus, LBUS) interface, etc.
  • each data transmission chip may include one or more low-speed interfaces, each low-speed interface may be connected to a low-speed device, and each low-speed interface has multiple pins.
  • the multiple first signals received by the data transmission chip 01a may be signals from different low-speed devices received by different low-speed interfaces 012a, or may be different signals from a low-speed device received by different pins of a low-speed interface 012a. type of signal.
  • the data transmission chip 01a includes a plurality of IIC interfaces, and each IIC interface is connected to a sensor (such as a temperature sensor or a humidity sensor), then the multiple first signals may be received by a plurality of IIC interfaces from different sensors signal of.
  • a sensor such as a temperature sensor or a humidity sensor
  • the number of data transmission chips included in the electronic device provided in the embodiment of the present application may be greater than 2.
  • Each data transmission chip can have multiple high-speed serial interfaces, and can be connected to multiple other data transmission chips through the multiple high-speed serial interfaces.
  • each high-speed serial interface in any data transmission chip is connected to one or more low-speed interfaces, and different high-speed serial interfaces can be respectively connected to different low-speed interfaces.
  • the data transmission chip may be an application specific integrated circuit (application specific integrated circuit, ASIC), a programmable logic device (programmable logic device, PLD) or a processor.
  • the PLD may be a complex programmable logic device (complex programmable logic device, CPLD), a field programmable logic gate array (field programmable gate array, FPGA) or a general array logic (generic array logic, GAL), etc.
  • the processor may be a central processing unit (central processing unit, CPU), a network processing unit (network processing unit, NPU), or a data processing unit (data processing unit, DPU).
  • multiple signals can be serially transmitted in the form of data frames through the high-speed serial interface between the data transmission chips, so the number of signal lines that need to be set between the data transmission chips can be effectively reduced quantity. Furthermore, the number of pins occupied by signal lines between chips can be effectively reduced, saving pin resources of data transmission chips. Furthermore, since the transmission rate of the high-speed serial interface is relatively high, the transmission efficiency of the multi-channel signal can be effectively ensured.
  • each data transmission chip in the electronic device provided in the embodiment of the present application may have both a data sending function and a data receiving function.
  • the function of the data transmission chip in the electronic device will be introduced below by taking the data transmission chip 01a in the electronic device as the chip on the data sending side and taking the data transmission chip 01b as the chip on the data receiving side as an example.
  • the low-speed interface 012a in the data transmission chip 01a is used to receive multiple channels of first signals.
  • the high-speed serial interface 011a is used to serially send the multiple first signals to the data transmission chip 01b in the form of data frames. That is, the data transmission chip 01a can carry data of multiple channels of the first signal in a data frame, and send the data frame to the data transmission chip 01b in serial.
  • the high-speed serial interface 011b of the data transmission chip 01b is used to serially receive the multiple first signals sent by the data transmission chip 01a in the form of data frames, and transmit the multiple first signals to the low-speed interface 012b.
  • the high-speed serial interface 011b can respectively transmit multiple channels of first signals obtained from the data frame to different low-speed interfaces 012b, or can also be transmitted to multiple different pins of one low-speed interface 012a .
  • At least one low-speed interface 012b in the data transmission chip 01b may correspond to at least one low-speed interface 012a in the data transmission chip 01a, and each low-speed interface 012b and the corresponding low-speed interface 012a may be the same type of interface.
  • the data transmission chip 01b can transmit at least one channel of the first signal of each low-speed interface 012a in the received data frame to a corresponding low-speed interface 012b.
  • At least one low-speed interface 012a in the data transmission chip 01a includes: IIC interface, UART interface and SPI
  • at least one low-speed interface 012b in the data transmission chip 01b can also include IIC interface, UART interface and SPI.
  • the data transmission chip 01b can transmit at least one first signal from the IIC interface of the data transmission chip 01a in the data frame to the IIC interface in the data transmission chip 01b, and can transmit the data frame from the UART interface of the data transmission chip 01a At least one first signal from the data transmission chip 01b is transmitted to the UART interface in the data transmission chip 01b, and at least one first signal from the SPI of the data transmission chip 01a in the data frame can be transmitted to the SPI in the data transmission chip 01b.
  • the high-speed serial interface 011a of the data transmission chip 01a is used for sampling multiple first signals received by the low-speed interface 012a based on the frequency of the clock signal of the data transmission chip 01a, and based on the sampled data Generate a data frame.
  • the high-speed serial interface 011a can sample multiple first signals received by the low-speed interface 012a according to the first sampling frequency f1, and the first sampling frequency f1 can be equal to the frequency of the clock signal of the data transmission chip 01a, or can be 1/n of the frequency of the clock signal of the data transmission chip 01a, where n is an integer greater than 1.
  • the high-speed serial interface 011b of the data transmission chip 01b serially receives the data frame sent by the data transmission chip 01a, it can sample the data frame based on the frequency of the clock signal of the data transmission chip 01b to recover multiple first signals .
  • the high-speed serial interface 011b can sample the received data frame according to the second sampling frequency f2, and the second sampling frequency f2 can be equal to the frequency of the clock signal of the data transmission chip 01b, or can be the clock frequency of the data transmission chip 01b Twice the frequency of the signal, or 1/m of the frequency of the clock signal of the data transmission chip 01b, where m is an integer greater than 1.
  • the second sampling frequency f2 adopted by the high-speed serial interface 011b to sample the data frame needs to be greater than the data transmission rate of the data frame.
  • FIG. 3 is a schematic diagram of a data structure of a data frame provided by an embodiment of the present application.
  • the data frame sent by the high-speed serial interface 011a of the data transmission chip 01a may include: a frame header, multiple data fields, and a gap field after each data field.
  • the data transmission chip 01a can serially send multiple data frames through the high-speed serial interface 011a.
  • the frame header may include a continuous N-bit (bit) first value and an M-bit second value; the multiple data fields are used to carry data obtained by sampling multiple first signals, and each data The lengths of the fields are all W bits; the gap field includes a second value of M bits.
  • N is a positive integer greater than W
  • M is a positive integer smaller than W.
  • both the first number and the second value may be binary numbers.
  • the data obtained by sampling the multiple first signals carried in the multiple data fields is also a binary number. Since the frame header includes a first value of N bits and a second value of M bits, and N is an integer greater than W, it can be ensured that the content of any data field will not be repeated with the frame header, thereby ensuring that the data transmission chip 01b After receiving the data frame, the high-speed serial interface 011b can accurately distinguish the frame header and the data field in the data frame.
  • the first value may be 1, and the second value may be 0.
  • the frame header may include 1s of N consecutive bits and 0s of M bits.
  • the difference between N and W may be greater than or equal to 2.
  • the length M of the gap field can be set to be smaller than a preset value, the preset value is smaller than W, and the preset value can be based on business requirements, or data transmission delay or other parameters that affect performance set up.
  • the M can be set to 1.
  • the frame header may include consecutive 10-bit 1s and 1-bit 0s, that is, the length of the frame header is 11 bits.
  • the high-speed serial interface 011b of the data transmission chip 01b can accurately sample the data in the data field to recover the multi-channel first Signal, to ensure the reliability of signal transmission.
  • the frame format of the data frame in the embodiment of the present application can make the data transmission chip 01b not need to use a state machine to sample the data in the data field. data, thereby simplifying the circuit structure of the data transmission chip 01b, and lowering the requirement on the sampling frequency of the data transmission chip 01b.
  • the high-speed serial interface 011a of the data transmission chip 01a can send data frames at a relatively high data transmission rate, thereby effectively increasing the data transmission rate. Furthermore, since each data frame can carry multiple data fields, the amount of data that can be transmitted in a single data frame is effectively increased, thereby improving the efficiency of data transmission.
  • the data frame may further include: a check field located after multiple data fields, and a gap field located after the check field.
  • the check field is used to carry a check bit, and the length of the check field is equal to the length of the data field.
  • the check bit carried by the check field is obtained after the high-speed serial interface 011a of the data transmission chip 01a calculates the data carried by multiple data fields using a check algorithm.
  • the high-speed serial interface 011b of the data transmission chip 01b obtains the data carried in multiple data fields, and after obtaining the check bit carried by the check field, the check bit can be used to check the acquired data, so as to Ensure the accuracy of the data received.
  • the check algorithm used when the high-speed serial interface 011a calculates the check digit may include a cyclic redundancy check (cyclic redundancy check, CRC) algorithm, an exclusive OR algorithm, or an accumulation sum algorithm, etc.
  • CRC cyclic redundancy check
  • CRC exclusive OR algorithm
  • accumulation sum algorithm etc.
  • the key parameters of the data frame can be expressed as follows:
  • Frame header pattern frame_header_bitmap (ie frame header structure): ⁇ N'b1, M'b0 ⁇ ; wherein, N'b1 represents 1 of N bits, and M'b0 represents 0 of M bits.
  • the data transmission rate when the high-speed serial interface 011a sends a data frame, the number of data fields included in the data frame, and the length of each data field (also referred to as the bit width of the data field) are all It can be flexibly set according to the requirements of application scenarios.
  • the data transmission bandwidth and delay requirements can be set according to the transmission data requirements of different application scenarios.
  • the transmission data requirement includes at least one of transmission factors such as transmission rate, transmission delay, and the number of data to be transmitted each time.
  • the high-speed serial interface 011a can perform parallel sampling on multiple first signals based on the frequency of the clock signal of the data transmission chip 01a, and generate data frames based on the data obtained by parallel sampling.
  • the high-speed serial interface 011a can perform parallel sampling on multiple channels of first signals according to the first sampling frequency f1.
  • the first sampling frequency f1 may be K1 times the transmission frequency of the data frame, and K1 is an integer greater than 1.
  • the sampling frequency refers to the sampling times per unit time, and the unit time may be 1 second.
  • the transmission frequency of data frames refers to the number of data frames transmitted by the high-speed serial interface 011a per unit time. It can be understood that the high-speed serial interface 011a samples one channel of the first signal once to obtain a 1-bit sampling value, and the high-speed serial interface 011a performs a parallel sampling of the X-channel first signal to obtain a sample of X bits value, X is an integer greater than 1.
  • the data of multiple first signals can be simultaneously transmitted in one data frame, thereby effectively improving signal transmission Efficiency and flexibility of transmission.
  • the first sampling frequency f1 is K1 times the transmission frequency of the data frame, each channel of the first signal can be sampled at a higher sampling frequency, thereby ensuring less signal distortion and making the data transmission chip
  • the high-speed serial interface 011b in 01b can accurately recover the first signal.
  • the data carried by the multiple data fields may include: K1 first sampling sequences arranged in sequence according to the sampling time, and each first sampling sequence includes a pair of A multi-bit sampling value obtained by performing one parallel sampling of the multiple first signals.
  • the high-speed serial interface 011a may synchronously sample multiple channels of first signals in parallel during the process of receiving multiple channels of first signals at the low-speed interface 012a, and synchronously send data frames. That is, the high-speed serial interface 011a can synchronously send the data frame during the process of generating the data frame based on the sampled data, without waiting for each field of the data frame to be encapsulated before sending it. Thus, the data transmission efficiency is effectively improved.
  • each first sampling sequence a plurality of sampling values obtained by sampling each channel of first signals may be arranged in a pre-agreed fixed order.
  • the j-th sample value in each first sampling sequence is a sample value obtained by sampling the j-th channel of the first signal, where j is a positive integer not greater than X.
  • the high-speed serial interface 011b in the data transmission chip 01b it is convenient for the high-speed serial interface 011b in the data transmission chip 01b to accurately recover the first signals of each channel based on the fixed sequence after obtaining a plurality of sampled values from the data frame.
  • the high-speed serial interface 011b may sample the data frame based on the frequency of the clock signal of the data transmission chip 01b, and recover multiple first signals based on the sampled data.
  • the high-speed serial interface 011b can sample the received data frame according to the second sampling frequency f2, the second sampling frequency f2 is K2 times the frequency of the clock signal CLK1 of the data transmission chip 01a, K2 is an integer greater than 1, For example K2 may be equal to 4. Since the second sampling frequency f2 is K2 times the frequency of the clock signal CLK1 of the data transmission chip 01a, it can ensure that the data transmission chip 01b can accurately sample the data carried in each data field of the data frame.
  • the data transmission rate of the high-speed serial interface 011a can be twice the frequency of the clock signal CLK1, or can be less than or Equal to the frequency of the clock signal CLK1.
  • the data transmission rate of the high-speed serial interface 011a can be equal to the frequency of the clock signal CLK1.
  • the data transmission rate of the high-speed serial interface 011a can be equal to twice the frequency of the clock signal CLK1.
  • the data transmission rate of the high-speed serial interface 011a can be equal to 1 of the frequency of the clock signal CLK1 /K0 times.
  • K0 is an integer greater than 1.
  • the high-speed serial interface 011b of the data transmission chip 01b receives the data frame, it samples the data frame according to the frequency of the clock signal CLK2 of the data transmission chip 01b, that is, the second sampling frequency f2 is equal to the clock signal CLK2
  • the frequency of the clock signal CLK2 may be K2 times the frequency of the clock signal CLK1.
  • the high-speed serial interface 011b can sample the data frame once at each transition edge (for example, a rising edge or a falling edge) of the clock signal CLK2 of the data transmission chip 01b.
  • the frequency of the clock signal CLK2 that is, the second sampling frequency f2
  • the high-speed serial interface 011b can obtain K2 jump edges in every K2 jump edges of the clock signal CLK2
  • the sampling value sampled by the edge of the k-th jump is used as the data for recovering the first signal.
  • k is a positive integer not greater than K2.
  • the high-speed serial interface 011b can also adjust the value of k based on the sampled phase deviation of the frame header. For example, the high-speed serial interface 011b may adjust the value of k when detecting that the phase deviation of the frame header exceeds one clock cycle of the clock signal CLK2, so as to ensure the accuracy of the sampled data.
  • the high-speed serial interface 011b may also determine that the sampling of a data field has been completed after sampling the sampled value of the gap field G0 each time. Furthermore, the high-speed serial interface 011b can recover the first signal based on the sampled data in a data field.
  • the high-speed serial interface 011b can acquire the data sampled by the second hop edge among the 4 hop edges in every 4 hop edges of the clock signal CLK2. Sample values, and store the acquired sampled values in registers (such as shift registers). That is, the second sampling pulse in every 4 sampling pulses is an effective sampling pulse.
  • the high-speed serial interface 011b can generate a valid (valid) pulse after sampling the sampled value of the gap field G0, and based on the valid pulse, take out the sampled value stored in the register as data carried in a data field for further processing. recovery of the signal.
  • the high-speed serial interface 011a can transmit data frames based on the frequency of the local clock signal of the data transmission chip 01a
  • the high-speed serial interface 011b can transmit data frames based on the frequency of the local clock signal of the data transmission chip 01b.
  • the solution provided by the embodiment of the present application uses an asynchronous clock for data communication.
  • the high-speed serial interface may also be called a high-speed asynchronous serial interface.
  • the high-speed serial interface 011a does not need to separately transmit clock signals to the high-speed serial interface 011b, there is no need to set clock signal lines for transmitting clock signals between data transmission chips. As a result, the number of signal lines required to be provided between data transmission chips can be effectively reduced, and pin resources of the data transmission chips can be saved.
  • the frequency deviation tolerance refers to the maximum frequency deviation allowed by the frequencies of the local clock signals of the two data transmission chips.
  • the data obtained after the high-speed serial interface 011b samples the data frames may include: K1 arranged in sequence according to the sampling time A first sample sequence, each first sample sequence includes a multi-bit sample value.
  • the process for the high-speed serial interface 011b to restore multiple channels of first signals based on the sampled data may include:
  • the j-th sampling value is sequentially obtained from each first sampling sequence, based on the sequentially obtained K1 bit sampling value to restore the first signal of the jth channel.
  • j is a positive integer not greater than X.
  • the data transmission chip 01b includes multiple low-speed interfaces 012b.
  • the data field in the data frame received by the high-speed serial interface 011b may also carry an identifier of each channel of the first signal, and the high-speed serial interface 011b may further distinguish each channel of the first signal based on the identifier. signal, and transmit each channel of the first signal to the corresponding low-speed interface 012b.
  • the high-speed serial interface 011a may encapsulate the multiple channels of first signals in a data frame according to a pre-agreed fixed order, and after the high-speed serial interface 011b samples the data in the data frame, it may The multiple first signals are recovered and identified in a fixed order, and then the multiple first signals are respectively sent to the corresponding low-speed interface 012b.
  • the two data transmission chips 01a and 01b may be located on the same PCB in the electronic device.
  • the PCB may be a main board of an electronic device.
  • the electrical signal transmission medium 03 between the two data transmission chips 01a and 01b may be a metal wire on a PCB.
  • the PCB may also be referred to as a single board.
  • the PCB may be a server single board.
  • the electronic device may further include a main control device located on the main board.
  • the main control device may be a central processing unit (central processing unit, CPU) or a micro control unit (microcontroller unit, MCU), etc.
  • FIG. 8 is illustrated by taking a CPU as an example.
  • the main control device can be connected with the low-speed interface 012b of the data transmission chip 01b through a parallel bus. After the high-speed serial interface 011a of the data transmission chip 01a transmits the data frame to the data transmission chip 01b, the high-speed serial interface 011b of the data transmission chip 01b can sample the data in the data frame and store it in its internal register 013b. Afterwards, the low-speed interface 012b can transmit the data in the internal register 013b to the master device.
  • the data transmission chip 01b may include two sets of internal registers 013b, and each set of internal registers 013b may include one or more registers.
  • One set of internal registers 013b can store data inside the data transmission chip 01b, and the other set of internal registers 013b can be used to store data sent by the data transmission chip 01a. Since the main control device can access two sets of internal registers 013b through the parallel bus, not only the data in the data transmission chip 01b can be obtained, but also the data in the data transmission chip 01a can be obtained. Therefore, the main control device does not need to be connected to the data transmission chip 01a through a parallel bus, thereby effectively reducing the number of signal lines on the PCB.
  • the high-speed serial interface 011a of the data transmission chip 01a can also be connected to its internal internal register 013a.
  • the high-speed serial interface 011a in addition to serially transmitting multiple first signals received by the low-speed interface 012a to the data transmission chip 01b, the high-speed serial interface 011a can also serially transmit the data in the internal register 013a to the data transmission chip 01b.
  • the two data transmission chips 01a and 01b may be located on different PCBs in the electronic device.
  • the data transmission chip 01a is located on the single board 1 of the electronic device
  • the data transmission chip 01b is located on the single board 2 of the electronic device.
  • the electrical signal transmission medium 03 between the two data transmission chips 01a and 01b may be an electrical signal transmission line, such as a cable.
  • the electrical signal transmission medium 03 may be a backplane (also referred to as a backplane connector), and the PCBs where the two data transmission chips 01a and 01b are located are all plugged into the backplane and can communicate through the backplane. .
  • the electronic device may further include at least one low-speed device, and a main control device for controlling the at least one low-speed device, and the main control device may be a CPU or an MCU.
  • the main control device (such as CPU) may be located on the same PCB as the data transmission chip 01a, and be connected to at least one low-speed interface of the data transmission chip 01a.
  • the at least one low-speed device may be located on the same PCB as the data transmission chip 01b, and be connected to at least one low-speed interface of the data transmission chip 01a.
  • the low-speed devices connected to the IIC interface may include sensors (such as temperature sensors or humidity sensors) and electrically erasable programmable read only memory (electrically erasable programmable read only memory, EEPROM) and the like.
  • the low-speed devices connected with the UART interface may include MCU and so on.
  • Low-speed devices connected to SPI may include flash memory (FLASH) and the like.
  • the main control device can control multiple low-speed devices on different PCBs through the high-speed serial interface in the data transmission chip.
  • the number of signal lines between different PCBs in the electronic device is effectively reduced, and the structure of the electronic device is simplified.
  • Fig. 9 is a flow chart of a data transmission method provided by an embodiment of the present application.
  • Fig. 9 takes the CPU transmitting multiple first signals to multiple low-speed devices through the data transmission chips 01a and 01b as an example for illustration. As shown in Figure 9, the method includes:
  • Step S11 the CPU writes multiple channels of first signals into the data queue.
  • the multiple first signals may be control commands for controlling the multiple low-speed devices.
  • Step S12 the low-speed interface of the data transmission chip 01a reads the multiple channels of first signals.
  • Step S13 the high-speed serial interface 011a of the data transmission chip 01a generates a data frame based on the multiple first signals, and sends the data frame to the data transmission chip 01b in serial. That is, the high-speed serial interface 011a may encapsulate the multiple channels of first signals in the data field of the data frame.
  • Step S14 after receiving the data frame, the high-speed serial interface 011b of the data transmission chip 01b decodes the data frame to recover multiple channels of first signals.
  • Step S15 the high-speed serial interface 011b of the data transmission chip 01b dispatches multiple channels of first signals to different low-speed interfaces, so as to be transmitted from each low-speed interface to the corresponding low-speed device.
  • the high-speed serial interface 011b can dispatch the first signal to the controllers of different low-speed interfaces, and the controller of each low-speed interface can then transmit the first signal to the corresponding low-speed device through the low-speed interface.
  • the data transmission chip 01a is used as the chip on the data sending side
  • the data transmission chip 01b is used as the chip on the data receiving side as an example.
  • the data transmission chip 01b can also be used as a chip on the data sending side to serially transmit data frames to the data transmission chip 01a, that is, the high-speed serial interface 011a in the data transmission chip 01a can also have the high-speed serial interface described above.
  • the function of the row interface 011b, the high-speed serial interface 011b may also have the function of the above-mentioned high-speed serial interface 011a.
  • the high-speed serial interface 011a is also used to receive multiple second signals serially sent by the data transmission chip 01b in the form of data frames, and transmit the multiple second signals to the low-speed interface 012a.
  • the high-speed serial interface 011a can sample the data frame sent by the data transmission chip 01b based on the frequency of the clock signal of the data transmission chip 01a, and restore the multiple second signals based on the sampled data.
  • the data obtained by sampling the data frame sent by the data transmission chip 01a by the high-speed serial interface 011a may include: a plurality of second sampling sequences arranged in sequence according to the sampling time, and each second sampling sequence includes multi-bit sampling value.
  • the high-speed serial interface 011a is also used to sequentially obtain one-bit sampling values from each second sampling sequence, and recover one second signal based on the sequentially obtained multiple-bit sampling values.
  • FIG. 10 is a flow chart of another data transmission method provided by the embodiment of the present application.
  • FIG. 10 takes multiple low-speed devices transmitting multiple second signals to the CPU through the data transmission chips 01a and 01b as an example for illustration.
  • the method may include:
  • Step S21 the high-speed serial interface 011b of the data transmission chip 01b polls each low-speed interface 012b to obtain multiple channels of second signals.
  • each second signal may be a signal sent by a low-speed device to a low-speed interface 012b connected thereto.
  • the first signal in the embodiment shown in Fig. 9 is a control command
  • each low-speed device after each low-speed device receives the control command, it can perform corresponding operations in response to the control command, and send the corresponding low-speed signal to the data transmission chip 01b.
  • the interface 012b returns the execution result of the operation. That is, each channel of the second signal may be an execution result of feedback from a low-speed device.
  • Step S22 the high-speed serial interface 011b of the data transmission chip 01b generates a data frame based on the acquired multiple second signals, and sends the data frame to the data transmission chip 01a in serial. That is, the data transmission chip 01b may encapsulate the multiple second signals in the data field of the data frame, and send the data frame generated after the encapsulation to the data transmission chip 01a.
  • Step S23 after receiving the data frame, the high-speed serial interface 011a of the data transmission chip 01a decodes the data frame to recover multiple channels of second signals.
  • Step S24 the high-speed serial interface 011a of the data transmission chip 01a writes the multiple second signals into the data queue.
  • Step S25 the CPU reads the data queue through the low-speed interface 012a of the data transmission chip 01a to obtain the multiple second signals.
  • the type of the low-speed interface used to connect with the main control device in the data transmission chip 01a can be the same as the type of the low-speed interface used to connect with the low-speed device in the data transmission chip 01b .
  • the low-speed interfaces used in the data transmission chip 01a to connect with the main control device include: IIC interface, UART interface and SPI interface.
  • the low-speed interfaces used in the data transmission chip 01b for connecting with low-speed devices also include: IIC interface, UART interface and SPI interface.
  • the type of the low-speed interface used to connect with the main control device in the data transmission chip 01a, and the type of the low-speed interface used to connect with the low-speed device in the data transmission chip 01b can be different.
  • the low-speed interface connected to the main control device in the data transmission chip 01a can be an LBUS interface
  • the low-speed interface connected to the low-speed device in the data transmission chip 01b can include: IIC interface, UART interface and SPI interface.
  • the data transmission chip 01a may further include an LBUS interface, and the IIC interface, UART interface and SPI interface in the data transmission chip 01a may be connected to the CPU through the LBUS interface.
  • the main control device communicates with the low-speed devices connected to multiple IIC interfaces of the data transmission chip 01b through the LBUS interface of the data transmission chip 01a as an example.
  • the data transmission chip 01a in the single board 1 also includes an LBUS interface controller, which can write the control commands sent by the main control device to the LBUS interface into the LBUS sending queue.
  • the LBUS sending queue may be a first-in-first-out (first input first output, FIFO) queue, for example, the width (width) of the sending queue may be 64 bits, and the depth (depth) may be 512.
  • the high-speed serial interface scheduler in the data transmission chip 01a can read data from the LBUS sending queue, and write the read data (ie, control commands) into the sending buffer of the high-speed serial interface 011a.
  • the width of the sending buffer may be equal to the length of each data field in the data frame, for example, 8 bits; the depth of the sending buffer may be equal to the number of data fields included in the data frame, for example, 20.
  • the high-speed serial interface 011a can generate a data frame based on the data stored in its sending buffer, and send the data frame serially to the data transmission chip 01b in the single board 2 .
  • the data frame may include T data fields from D0 to DT, and a check field C0 after the T data fields. Assuming that the length W of each data field is 8 bits, and the length M of the gap field is 1 bit, then the length of the frame header of the data frame can be 11 bits, and includes consecutive 10-bit 1s and 1-bit 0s. A hexadecimal number can be represented as FFE.
  • the high-speed serial interface 011b of the data transmission chip 01b in the single board 2 receives the data frame, it can decode the data frame, and decode the data obtained after decoding (that is, the data carried in multiple data fields) control command) is stored in the receiving buffer of the high-speed serial interface 011b.
  • the high-speed serial interface scheduler in the data transmission chip 01b can read the control command from the receiving buffer, analyze the control command, and write it into the corresponding low-speed device through the IIC interface.
  • the IIC controller in the low-speed device can then write the received control commands into the command queue.
  • FIG. 13 is a flow chart of sending data from the data transmission chip 01 b in the board 2 to the data transmission chip 01 a in the board 1 .
  • the IIC controller can write the execution result of the operation into the result queue of the low-speed device.
  • the high-speed serial interface scheduler in the data transmission chip 01b can read the execution result from the result queue of the low-speed device through the IIC interface, and write the execution result to the sending buffer of the high-speed serial interface 011b.
  • the high-speed serial interface 011b can generate a data frame based on the data stored in its sending buffer, and send the data frame serially to the data transmission chip 01a in the single board 1 .
  • the high-speed serial interface 011a of the data transmission chip 01a in the single board 1 After the high-speed serial interface 011a of the data transmission chip 01a in the single board 1 receives the data frame, it can decode the data frame, and store the data obtained after decoding (that is, the execution results carried in multiple data fields) in the Receive buffer for high-speed serial interface 011a.
  • the high-speed serial interface scheduler in the data transmission chip 01a can read the execution result from the receiving buffer, and send the execution result to the master control device through the LBUS interface.
  • the high-speed serial interfaces of the data transmission chips are connected by signal wires (such as metal wires or cables), then for the scenario where the data transmission chip 01a sends data unidirectionally to the data transmission chip 01b, the two Only one signal line may be arranged between the high-speed serial interfaces of the data transmission chip.
  • signal wires such as metal wires or cables
  • the two Only one signal line may be arranged between the high-speed serial interfaces of the data transmission chip.
  • two signal lines can be set between the high-speed serial interfaces of the two data transmission chips, one of which is used for The data transmission chip 01a sends data frames to the data transmission chip 01b, and the other signal line is used for the data transmission chip 01b to send data frames to the data transmission chip 01a.
  • the signal lines between the high-speed serial interfaces may also be called high-speed serial buses, or Hisport buses.
  • FIG. 14 is a schematic structural diagram of a data transmission chip provided by an embodiment of the present application.
  • the data transmission chip includes at least one high-speed serial interface 011 and at least one low-speed interface 012 .
  • the data transmission chip includes at least one high-speed serial interface 011 and at least one low-speed interface 012 .
  • the data transmission chip includes at least one high-speed serial interface 011 and at least one low-speed interface 012 .
  • one high-speed serial interface 011 and a plurality of low-speed interfaces 012 are shown in FIG. 14 .
  • the high-speed serial interface 011 may include a connection port 0111 , and the connection port 0111 is used for connecting with the electrical signal transmission medium 03 .
  • the connection port 0111 can be a pin; if the electrical signal transmission medium 03 is a cable, the connection port 0111 can be a cable interface.
  • the high-speed serial interface 011 may also include:
  • the first sampling module 0112 is configured to sample multiple channels of first signals.
  • a framing module 0113 configured to generate a data frame based on the sampled data.
  • the first sampling module 0112 may perform parallel sampling on multiple channels of first signals based on the frequency of the clock signal of the data transmission chip 01a.
  • the data sampled by the first sampling module 0112 may include a plurality of first sampling sequences sequentially arranged in order of sampling time, and each first sampling sequence includes one parallel sampling of the multiple first signals to obtain The multi-bit sampling value of .
  • connection port 0111 is also used for the data frame sent serially by the data transmission chip 01b; as shown in Figure 14, the high-speed serial interface 011 can also include:
  • the second sampling module 0114 is configured to sample the data frames received by the connection port 0111 to obtain multiple channels of second signals.
  • the scheduling module 0115 is configured to transmit the multiple channels of second signals to the low-speed interface 012.
  • the scheduling module 0115 may be the high-speed serial interface scheduler described in the above embodiments.
  • the second sampling module 0114 is configured to sample the data frame based on the frequency of the clock signal of the data transmission chip 01a, and recover the multiple second signals based on the sampled data.
  • the data sampled by the second sampling module 0114 may include a plurality of second sampling sequences arranged in sequence according to sampling time, and each first sampling sequence includes a multi-bit sampling value.
  • the second sampling module 0114 can be used for:
  • a one-bit sampling value is sequentially obtained from each second sampling sequence, and one second signal is restored based on the sequentially obtained multiple-bit sampling values.
  • each module in the data transmission chip described above can be a circuit module, for example, can be implemented by a programmable logic circuit.
  • the embodiment of the present application provides a data transmission chip, the low-speed interface of the data transmission chip is used to receive multiple first signals, and the high-speed serial interface of the data transmission chip is used to receive the multiple first signals.
  • the signal is serially transmitted to another data transmission chip in the form of data frame. Since multiple signals can be serially transmitted between data transmission chips in the form of data frames, the number of signal lines that need to be set between data transmission chips can be effectively reduced, thereby simplifying the structure of electronic equipment. Furthermore, since the data transmission rate of the high-speed serial interface is relatively high, the transmission efficiency of the multiple first signals can be effectively ensured.
  • the embodiment of the present application also provides a data transmission chip, the data transmission chip includes a programmable logic circuit, and the data transmission chip is used to implement the functions of the data transmission chip described in the above embodiments.
  • the above-mentioned embodiments may be implemented in whole or in part by software, hardware, firmware or other arbitrary combinations.
  • the above-described embodiments may be implemented in whole or in part in the form of computer program products.
  • the computer program product includes one or more computer instructions.
  • the computer program instructions When the computer program instructions are loaded or executed on the computer, the processes or functions described in the embodiments of the present application according to the present invention will be generated in whole or in part.
  • the computer may be a general purpose computer, a special purpose computer, a computer network, or other programmable devices.
  • the computer instructions may be stored in or transmitted from one computer-readable storage medium to another computer-readable storage medium, for example, the computer instructions may be transmitted from a website, computer, server or data center Transmission to another website site, computer, server, or data center by wired (eg, coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (eg, infrared, wireless, microwave, etc.).
  • the computer-readable storage medium may be any available medium that can be accessed by a computer, or a data storage device such as a server or a data center that includes one or more sets of available media.
  • the available media may be magnetic media (eg, floppy disk, hard disk, magnetic tape), optical media (eg, DVD), or semiconductor media.
  • the semiconductor medium may be a solid state drive (SSD).

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Abstract

一种数据传输芯片及电子设备，属于电子技术领域。其中，数据传输芯片的低速接口用于接收多路第一信号，数据传输芯片的高速串行接口用于将该多路第一信号以数据帧的方式串行传输至另一个数据传输芯片。由于数据传输芯片之间能够通过数据帧的方式串行传输多路信号，因此可以有效减少数据传输芯片之间所需设置的信号线的数量，进而简化电子设备的结构。又由于该高速串行接口的数据传输速率较高，因此可以有效确保该多路第一信号的传输效率。

Description

数据传输芯片及电子设备
本申请要求于2021年12月10日提交中国专利局、申请号为202111509164.3、发明名称为“数据传输的方法”的中国专利申请的优先权，以及于2021年12月31日提交的申请号为202111665986.0、发明名称为“数据传输芯片及电子设备”的中国专利申请的优先权，前述两件专利申请的全部内容通过引用结合在本申请中。
技术领域
本申请涉及电子技术领域，特别涉及一种数据传输芯片及电子设备。
背景技术
随着电子设备性能的提升，电子设备中的芯片数量也不断增多。例如，电子设备中一般包括多个复杂可编程逻辑器件(complex programmable logic device，CPLD)，且不同CPLD之间一般通过多个接口通信。
由于CPLD中的每个接口均需通过多根信号线与另一CPLD中对应的接口连接，因此CPLD之间通过多个接口通信，会导致CPLD之间的信号线的数量较多，电子设备的结构较为复杂。
发明内容
本申请提供了一种数据传输芯片及电子设备，可以解决电子设备中芯片之间的信号线的数量较多，导致电子设备的结构较为复杂的技术问题。
第一方面，提供了一种数据传输芯片，该数据传输芯片包括高速串行接口和低速接口；该低速接口用于接收多路第一信号；该高速串行接口用于将多路第一信号以数据帧的方式串行传输至另一数据传输芯片；其中，高速串行接口的数据传输速率高于低速接口的数据传输速率。
由于数据传输芯片中的高速串行接口能够将多路第一信号以数据帧的方式串行传输至另一数据传输芯片，因此可以有效减少数据传输芯片之间所需设置的信号线的数量，进而节约了数据传输芯片的引脚资源，并简化了电子设备的结构。又由于该高速串行接口的数据传输速率较高，因此可以有效确保该多路信号的传输效率。
可以理解的是，该数据传输芯片可以包括一个或多个低速接口，每个低速接口可以具有多个引脚。上述多路第一信号可以是多个不同的低速接口接收到的信号，或者可以是同一个低速接口的不同引脚接收到的信号。
在一种可能的实现方式中，该高速串行接口，用于基于对多路第一信号进行采样得到的数据生成数据帧。由于高速串行接口能够在一个数据帧中携带多路第一信号的数据，因此有效提高了信号的传输效率和灵活性。
在另一种可能的实现方式中，该高速串行接口，用于基于数据传输芯片的时钟信号的频率对多路第一信号进行并行采样。
例如，高速串行接口可以按照第一采样频率对多路第一信号进行并行采样，该第一采样频率可以小于或等于数据传输芯片的时钟信号的频率，且可以是数据帧的传输频率的K1倍， K1为大于1的整数。通过将该第一采样频率设置的较高，可以确保第一信号的失真较少，进而使得另一数据传输芯片能够准确地恢复出第一信号。
在另一种可能的实现方式中，高速串行接口采样得到的数据可以包括按照采样时间的先后顺序依次排列的多个第一采样序列，每个第一采样序列包括对多路第一信号进行一次并行采样得到的多位采样值。
基于此，高速串行接口可以在基于采样得到的数据生成数据帧的过程中，同步发送该数据帧，而无需等待数据帧的各个字段均封装完成后再进行发送。由此，有效提高了数据的发送效率。
在另一种可能的实现方式中，该高速串行接口，还用于接收另一数据传输芯片以数据帧的方式串行发送的多路第二信号，并将多路第二信号传输至低速接口。
本申请提供的数据传输芯片中的高速串行接口既具有数据发送的功能，也具有数据接收的功能，即该高速串行接口能够实现数据的双向传输。
可选地，该数据传输芯片可以包括多个低速接口。作为一种可能的示例，高速串行接口接收到的数据帧中还携带有每一路第二信号的标识，该高速串行接口可以基于该标识区分各路第二信号，并将各路第二信号传输至对应的低速接口。其中，第二信号的标识也可以称为标签(tag)。
作为另一种可能的示例，另一数据传输芯片可以按照预先约定的固定顺序在数据帧中封装该多路第二信号，高速串行接口接收到数据帧后，可以根据该固定顺序识别多路第二信号，并将多路第二信号分别发送至对应的低速接口。
在另一种可能的实现方式中，高速串行接口，还用于基于数据传输芯片的时钟信号的频率对另一数据传输芯片发送的数据帧进行采样，基于采样得到的数据恢复多路第二信号。
例如，高速串行接口可以按照第二采样频率对多路第二信号进行并行采样，该第二采样频率可以小于或等于数据传输芯片的时钟信号的频率，或者，可以是数据传输芯片的时钟信号的频率的2倍。并且，该第二采样频率可以是另一数据传输芯片的时钟信号的频率的K2倍，K2为大于1的整数。由于第二采样频率是另一数据传输芯片的时钟信号的频率的整数倍，因此可以确保高速串行接口能够准确采样得到数据帧中携带的数据。
在另一种可能的实现方式中，对另一数据传输芯片发送的数据帧进行采样得到的数据包括：按照采样时间的先后顺序依次排列的多个第二采样序列，每个第二采样序列包括多位采样值；该高速串行接口，还用于依次从每个第二采样序列中获取一位采样值，基于按序获取到的多位采样值恢复一路第二信号。
例如，对于多路第二信号中的第j路第二信号，高速串行接口用于按照该多个第二采样序列的排列顺序，依次从每个第二采样序列中获取第j位采样值，基于按序获取到的多位采样值，恢复出第j路第二信号，其中j为正整数，且j不大于多路第二信号的总路数。
在另一种可能的实现方式中，数据传输芯片和另一数据传输芯片可以位于同一个印刷电路板(printed circuit board，PCB)；或者，数据传输芯片和另一数据传输芯片可以位于不同的PCB。也即，在本申请提供的方案中，数据传输芯片中的高速串行接口可以实现板内的数据通信，也可以实现板间的数据通信。
在另一种可能的实现方式中，该数据帧可以包括：帧头，多个数据字段，以及位于每个数据字段之后的一个间隙字段；其中，帧头包括连续的N位第一数值和M位第二数值，多个数据字段用于携带对多路第一信号进行采样得到的数据，且每个数据字段的长度均为W位，间隙字段包括M位第二数值，N为大于W的正整数，M为小于W的正整数。
基于上述数据帧的帧结构，可以确保另一数据传输芯片能够准确采样数据字段中的数据以恢复出多路第一信号，进而确保了信号传输的可靠性。
其中，N与W的差值可以大于或等于2，且M的取值可以为1。通过使N与W的差值大于或等于2，可以确保另一数据传输芯片能够区分数据帧中的帧头和数据字段，避免将数据字段误采样为帧头。通过将M设置为1，可以提高数据帧中有效净荷(即数据字段的长度)的占比，进而有效提高数据的传输效率。
可选地，该数据帧中的第一数值可以为1，第二数值可以为0。
在另一种可能的实现方式中，数据帧还可以包括：位于多个数据字段之后的校验字段，以及位于校验字段之后的一个间隙字段；校验字段用于携带校验位，且校验字段的长度等于数据字段的长度。
其中，该检验字段携带的校验位是高速串行接口采用校验算法对多个数据字段携带的数据进行计算后得到的。另一数据传输芯片获取到多个数据字段中携带的数据，并获取到校验字段携带的校验位之后，可以采用该校验位对获取到的数据进行校验，以确保接收到的数据的准确性。
第二方面，提供了一种数据传输方法，应用于第一方面提供的数据传输芯片，该方法包括：通过低速接口接收多路第一信号；通过高速串行接口将多路第一信号以数据帧的方式串行传输至另一数据传输芯片；其中，该高速串行接口的数据传输速率高于该低速接口的数据传输速率。
在一种可能的实现方式中，该方法还可以包括：对多路第一信号进行采样，并基于采样得到的数据生成数据帧。
在另一种可能的实现方式中，对多路第一信号进行采样的过程可以包括：基于该数据传输芯片的时钟信号的频率对该多路第一信号进行并行采样。
在另一种可能的实现方式中，该采样得到的数据包括按照采样时间的先后顺序依次排列的多个第一采样序列，每个第一采样序列包括对多路第一信号进行一次并行采样得到的多位采样值。
在另一种可能的实现方式中，该方法还可以包括：通过该高速串行接口接收另一数据传输芯片以数据帧的方式串行发送的多路第二信号，并将该多路第二信号传输至该低速接口。
在另一种可能的实现方式中，该方法还可以包括：基于该数据传输芯片的时钟信号的频率对另一数据传输芯片发送的数据帧进行采样，基于采样得到的数据恢复该多路第二信号。
在另一种可能的实现方式中，对该另一数据传输芯片发送的数据帧进行采样得到的数据包括：按照采样时间的先后顺序依次排列的多个第二采样序列，每个第二采样序列包括多位采样值；基于采样得到的数据恢复该多路第二信号，包括：依次从每个第二采样序列中获取一位采样值，基于按序获取到的多位采样值恢复一路第二信号。
第三方面，提供了一种数据传输芯片，该数据传输芯片包括：可编程逻辑电路和/或程序指令，该控制器用于实现上述第一方面所提供的数据传输芯片的功能。
第四方面，提供了一种数据传输芯片，该数据传输芯片包括至少一个模块，该至少一个模块可以用于实现上述第一方面所提供的数据传输芯片的功能。
第五方面，提供了一种计算机可读存储介质，该计算机可读存储介质中存储有指令，该指令由处理电路执行以实现上述第二方面所提供的数据传输方法。
第六方面，提供了一种包含指令的计算机程序产品，当该计算机程序产品在处理电路上运行时，使得处理电路执行上述第二方面所提供的数据传输方法。
第七方面，提供了一种电子设备，该电子设备包括数据传输芯片，该数据传输芯片用于实现上述第一方面所提供的数据传输芯片的功能。
在一种可能的实现方式中，该电子设备可以包括多个数据传输芯片，且两个数据传输芯片的高速串行接口之间可以通过电信号传输介质连接。
综上所述，本申请提供了一种数据传输芯片及电子设备。本申请提供的方案中，数据传输芯片的低速接口用于接收多路第一信号，数据传输芯片的高速串行接口用于将该多路第一信号以数据帧的方式串行传输至另一个数据传输芯片。由于数据传输芯片之间能够通过数据帧的方式串行传输多路信号，因此可以有效减少数据传输芯片之间所需设置的信号线的数量，进而简化电子设备的结构。又由于该高速串行接口的数据传输速率较高，因此可以有效确保该多路第一信号的传输效率。
本申请在上述各方面提供的实现方式的基础上，还可以进行进一步组合以提供更多实现方式。
附图说明
图1是本申请实施例提供的一种电子设备的结构示意图；
图2是本申请实施例提供的另一种电子设备的结构示意图；
图3是本申请实施例提供的一种数据帧的数据结构示意图；
图4是本申请实施例提供的一种数据帧的局部结构示意图；
图5是本申请实施例提供的一种对信号进行采样以生成数据帧的示意图；
图6是本申请实施例提供的一种数据传输芯片发送数据帧的示意图；
图7是本申请实施例提供的一种数据传输芯片接收数据帧的示意图；
图8是本申请实施例提供的又一种电子设备的结构示意图；
图9是本申请实施例提供的一种CPU通过数据传输芯片向低速器件发送控制指令的示意图；
图10是本申请实施例提供的一种低速器件通过数据传输芯片向CPU发送执行结果的示意图；
图11是本申请实施例提供的再一种电子设备的结构示意图；
图12是本申请实施例提供的一种主控器件通过数据传输芯片向低速器件发送控制指令的示意图；
图13是本申请实施例提供的一种低速器件通过数据传输芯片向主控器件发送执行结果的示意图；
图14是本申请实施例提供的一种数据传输芯片的结构示意图。
具体实施方式
为了解决上述技术问题，本申请实施例提供了一种数据传输芯片，该数据传输芯片通过低速接口接收到多路信号后，能够通过高速串行接口将该多路信号以数据帧的方式串行传输至另一数据传输芯片。由此，能够在确保较高的数据传输速率的同时，有效减少数据传输芯片之间的信号线的数量。
下面结合附图详细介绍本申请实施例提供的数据传输芯片及电子设备。
图1是本申请实施例提供的一种电子设备的结构示意图，该电子设备可以是服务器、边缘设备、个人电脑(personal computer，PC)等计算设备，或者可以是智能手机等可移动终端， 或者可以是交换机或路由器等交换设备。如图1所示，该电子设备包括两个数据传输芯片01a和01b，每个数据传输芯片均具有高速串行接口(high speed serial port，Hisport)和低速接口。
其中，数据传输芯片01a的高速串行接口011a与数据传输芯片01b的高速串行接口011b之间可以通过电信号传输介质03连接，并能够通过电信号传输介质03，以数据帧的方式串行传输低速接口的多路信号。也即是，数据传输芯片中的高速串行接口能够通过数据帧的方式，承载低速接口的多路信号。
以图1为例，数据传输芯片01a的高速串行接口011a用于将低速接口012a接收到的多路第一信号封装成数据帧，并将该数据帧串行传输至数据传输芯片01b的高速串行接口011b。高速串行接口011b用于对接收到的数据帧进行解封装(也称为解码)，以恢复出该多路第一信号，并将该多路第一信号传输至低速接口012b。
可以理解的是，高速串行接口011a和高速串行接口011b均可以包括用于连接电信号传输介质03的连接端口(例如引脚)，以及用于对数据进行处理的逻辑电路。例如，高速串行接口011a可以包括用于将多路第一信号封装成数据帧的逻辑电路，高速串行接口011b可以包括用于对数据帧进行解封装的逻辑电路。
在本申请实施例中，每个数据传输芯片中高速串行接口的数据传输速率均高于低速接口的数据传输速率。例如，高速串行接口的数据传输速率可以是低速接口的数据传输速率的10倍，甚至更高。该数据传输速率可以是指单位时间内传输的数据的位(bit)数，该单位时间可以为1秒，相应的，该数据传输速率的单位可以是比特每秒(bps)。
可以理解的是，本申请实施例中所述的低速接口是相对于该高速串行接口而言的。每个数据传输芯片中的低速接口可以包括下述接口中的一个或多个：并行输入输出(input output，IO)接口，串行外设接口(serial peripheral interface，SPI)，内部集成电路(inter-integrated circuit，IIC或I 2C)接口，通用异步收发传输器(universal asynchronous receiver/transmitter，UART)接口以及局部总线(local bus，LBUS)接口等。
在本申请实施例中，每个数据传输芯片均可以包括一个或多个低速接口，每个低速接口可以与一个低速器件连接，且每个低速接口具有多个引脚。数据传输芯片01a接收到的多路第一信号可以是不同的低速接口012a接收到的来自不同低速器件的信号，或者，可以是一个低速接口012a的不同引脚接收到的来自一个低速器件的不同类型的信号。
示例的，假设数据传输芯片01a包括多个IIC接口，每个IIC接口与一个传感器(如温度传感器或湿度传感器)连接，则该多路第一信号可以是多个IIC接口接收到的来自不同传感器的信号。
可选地，本申请实施例提供的电子设备中包括的数据传输芯片的个数可以大于2。每个数据传输芯片可以具有多个高速串行接口，且可以通过该多个高速串行接口与多个其他数据传输芯片连接。其中，任一数据传输芯片中的每个高速串行接口均与一个或多个低速接口连接，且不同高速串行接口可以分别连接不同低速接口。
在本申请实施例中，该数据传输芯片可以是专用集成电路(application specific integrated circuit，ASIC)、可编程逻辑器件(programmable logic device，PLD)或者处理器。该PLD可以是复杂可编程逻辑器件(complex programmable logic device，CPLD)，现场可编程逻辑门阵列(field programmable gate array，FPGA)或通用阵列逻辑(generic array logic，GAL)等。该处理器可以是中央处理器(central processing unit，CPU)、网络处理器(network processing unit，NPU)或数据处理器(data processing unit，DPU)等。
由于在本申请实施例提供的方案中，数据传输芯片之间能够通过高速串行接口，以数据 帧的方式串行传输多路信号，因此可以有效减少数据传输芯片之间所需设置的信号线的数量。进而，可以有效减少芯片之间的信号线所占用的引脚的数量，节约了数据传输芯片的引脚资源。又由于该高速串行接口的传输速率较高，因此可以有效确保该多路信号的传输效率。
可以理解的是，本申请实施例提供的电子设备中的每个数据传输芯片均可以既具有数据发送的功能，也具有数据接收的功能。下文以电子设备中的数据传输芯片01a为数据发送侧的芯片，并以数据传输芯片01b为数据接收侧的芯片为例，对该电子设备中的数据传输芯片的功能进行介绍。
参考图1，数据传输芯片01a中的低速接口012a用于接收多路第一信号。高速串行接口011a用于将该多路第一信号以数据帧的方式串行发送至数据传输芯片01b。也即，数据传输芯片01a能够在数据帧中携带多路第一信号的数据，并将该数据帧串行发送至数据传输芯片01b。
相应的，数据传输芯片01b的高速串行接口011b用于串行接收数据传输芯片01a以数据帧的方式发送的多路第一信号，并将多路第一信号传输至低速接口012b。
可以理解的是，高速串行接口011b能够将从数据帧中获取到的多路第一信号分别传输至不同的低速接口012b，或者，也可以传输至一个低速接口012a的多个不同的引脚。
可选地，数据传输芯片01b中的至少一个低速接口012b可以与数据传输芯片01a中的至少一个低速接口012a一一对应，每个低速接口012b与对应的低速接口012a可以为相同类型的接口。相应的，数据传输芯片01b能够将接收到的数据帧中每个低速接口012a的至少一路第一信号传输至对应的一个低速接口012b。
示例的，如图2所示，假设数据传输芯片01a中的至少一个低速接口012a包括：IIC接口，UART接口和SPI，则数据传输芯片01b中的至少一个低速接口012b也可以包括IIC接口，UART接口和SPI。并且，数据传输芯片01b能够将数据帧中来自数据传输芯片01a的IIC接口的至少一路第一信号传输至数据传输芯片01b中的IIC接口，并能够将数据帧中来自数据传输芯片01a的UART接口的至少一路第一信号传输至数据传输芯片01b中的UART接口，并还能够将数据帧中来自数据传输芯片01a的SPI的至少一路第一信号传输至数据传输芯片01b中的SPI。
在本申请实施例中，数据传输芯片01a的高速串行接口011a用于：基于数据传输芯片01a的时钟信号的频率对低速接口012a接收到多路第一信号进行采样，并基于采样得到的数据生成数据帧。例如，高速串行接口011a可以按照第一采样频率f1对低速接口012a接收到的多路第一信号进行采样，该第一采样频率f1可以等于数据传输芯片01a的时钟信号的频率，或者可以是数据传输芯片01a的时钟信号的频率的1/n，n为大于1的整数。
数据传输芯片01b的高速串行接口011b串行接收到数据传输芯片01a发送的数据帧后，能够基于数据传输芯片01b的时钟信号的频率对该数据帧进行采样，以恢复出多路第一信号。例如，高速串行接口011b可以按照第二采样频率f2对接收到的数据帧进行采样，该第二采样频率f2可以等于数据传输芯片01b的时钟信号的频率，或者可以是数据传输芯片01b的时钟信号的频率的2倍，又或者可以是数据传输芯片01b的时钟信号的频率的1/m，m为大于1的整数。并且，基于采样定理可知，高速串行接口011b对数据帧进行采样时所采用的第二采样频率f2需大于数据帧的数据传输速率。
图3是本申请实施例提供的一种数据帧的数据结构示意图。如图3所示，数据传输芯片01a的高速串行接口011a发送的数据帧可以包括：帧头，多个数据字段，以及位于每个数据字段之后的一个间隙字段。并且，从图3还可以看出，数据传输芯片01a可以通过高速串行 接口011a串行发送多个数据帧。
参考图4，该帧头可以包括连续的N位(bit)第一数值和M位第二数值；该多个数据字段用于携带对多路第一信号进行采样得到的数据，且每个数据字段的长度均为W位；该间隙字段包括M位第二数值。其中，N为大于W的正整数，M为小于W的正整数。
在本申请实施例中，该第一数字和第二数值可以均为二进制数。该多个数据字段携带的对多路第一信号进行采样得到的数据也为二进制数。由于帧头包括N位第一数值和M位第二数值，且N为大于W的整数，因此可以确保任一数据字段的内容均不会与该帧头重复，进而可以确保数据传输芯片01b的高速串行接口011b接收到数据帧后，能够准确地区分该数据帧中的帧头和数据字段。
示例的，如图4所示，该第一数值可以为1，第二数值可以为0。相应的，该帧头可以包括连续N个bit的1，以及M个bit的0。
可选地，为了确保高速串行接口011b区分帧头和数据字段的准确性，避免高速串行接口011b将数据字段误采样为帧头，该N与W的差值可以大于或等于2。并且，为了提高数据帧的数据传输效率，该间隙字段的长度M可以设置为小于预设值，该预设值小于W，预设值可以根据业务需求，或数据传输延迟或其他影响性能的参数设置。例如，参考图4，该M可以设置为1。相应的，若每个数据字段的长度W＝8，N与W的差值为2，则该帧头可以包括连续10bit的1，以及1bit的0，即帧头的长度为11bit。
基于本申请实施例中数据帧的帧头、数据字段和间隙字段的设置方式，一方面可以使得数据传输芯片01b的高速串行接口011b能够准确采样数据字段中的数据以恢复出多路第一信号，确保信号传输的可靠性。另一方面，相比于其他串行接口以逻辑低电平为数据传输的起始位，本申请实施例中的数据帧的帧格式可以使得数据传输芯片01b无需通过状态机来采样数据字段中的数据，进而简化了数据传输芯片01b的电路结构，且降低了对数据传输芯片01b的采样频率的要求。又由于对数据传输芯片01b的采样频率的要求较低，因此数据传输芯片01a的高速串行接口011a能够以较高的数据传输速率发送数据帧，从而有效提高了数据传输的速率。又由于每个数据帧中均能够携带多个数据字段，因此有效提高了单个数据帧能够传输的数据量，进而提高了数据的传输效率。
可选地，继续参考图3，该数据帧还可以包括：位于多个数据字段之后的校验字段，以及位于该校验字段之后的一个间隙字段。其中，该校验字段用于携带校验位，且该校验字段的长度等于数据字段的长度。
在本申请实施例中，该检验字段携带的校验位是数据传输芯片01a的高速串行接口011a采用校验算法对多个数据字段携带的数据进行计算后得到的。数据传输芯片01b的高速串行接口011b获取到多个数据字段中携带的数据，并获取到校验字段携带的校验位之后，可以采用该校验位对获取到的数据进行校验，以确保接收到的数据的准确性。
其中，高速串行接口011a计算该校验位时采用的校验算法可以包括循环冗余校验(cyclic redundancy check，CRC)算法，异或算法，或者累加和算法等。
假设高速串行接口011a发送的每个数据帧中包括的数据字段的个数为T，第一数值为1，第二数值为0，则数据帧的关键参数可以表示如下：
帧头图样frame_header_bitmap(即帧头结构)：{N′b1，M′b0}；其中，N′b1表示N个bit的1，M′b0表示M个bit的0。
帧长度frame_length：frame_length＝(W+M)×(T+2)+(N-W)；
有效净荷payload_length满足：payload_length＝(W×T)；
数据传输效率frame_efficiency(即数据帧中有效净荷的占比)：frame_efficiency＝payload_length/frame_length。
可以理解的是，高速串行接口011a发送数据帧时的数据传输速率，数据帧中所包括的数据字段的个数，以及每个数据字段的长度(也可以称为数据字段的位宽)均可以根据应用场景的需求灵活设置。例如，可以根据不同应用场景的传输数据需求对数据传输带宽和时延的要求进行设置。传输数据需求包括传输速率、传输时延、每次传输数据的个数等传输因素中至少一种。
可选地，为了提高数据的传输效率，高速串行接口011a能够基于数据传输芯片01a的时钟信号的频率，对多路第一信号进行并行采样，并基于并行采样得到的数据生成数据帧。例如，高速串行接口011a能够按照第一采样频率f1对多路第一信号进行并行采样，该第一采样频率f1可以为该数据帧的传输频率的K1倍，K1为大于1的整数。
其中，采样频率是指单位时间内的采样次数，该单位时间可以为1秒。数据帧的传输频率是指高速串行接口011a在单位时间内传输的数据帧的个数。可以理解的是，高速串行接口011a对一路第一信号进行一次采样，可以获取到1bit的采样值，高速串行接口011a对X路第一信号进行一次并行采样，可以获取到X bit的采样值，X为大于1的整数。
由于该第一采样频率f1为数据帧的传输频率的K1倍，因此在一个数据帧的传输时段内，高速串行接口011a能够对多路第一信号进行K1次并行采样。若一个数据帧的有效净荷为W×T，则一个数据帧中能够携带对X＝(W×T)/K1路第一信号进行K1次并行采样得到的多位采样值。
示例的，如图5所示，假设数据帧包括D0至D19共20个数据字段，每个数据字段的长度和校验字段C0的长度均为8bit，间隙字段的长度为1bit，帧头的长度为11bit。则数据帧的帧长度frame_length为200bit，有效净荷为160bit。若高速串行接口11a的数据传输速率为25兆比特每秒(Mbps)，则可以确定该数据帧的传输频率f0为：f0＝25Mbps/200bit＝125千赫兹(KHz)。
参考图5，若K1＝2，则该第一采样频率f1可以为250KHz，每个数据帧中能够携带对X＝80路第一信号进行2次并行采样得到的多位采样值。也即，在每个数据帧中，对于80路第一信号中的每一路第一信号，高速串行接口011a可以对该路第一信号进行2次采样，得到2位采样值。
若K1＝4，则该第一采样频率f1可以为500KHz，每个数据帧中能够携带对X＝40路第一信号进行4次并行采样得到的多位采样值。也即，在每个数据帧中，对于40路第一信号中的每一路第一信号，高速串行接口011a可以对该路第一信号进行4次采样，得到4位采样值。
若K1＝8，则第一采样频率f1可以为1MHz，每个数据帧中能够携带对X＝20路第一信号进行8次并行采样得到的多位采样值。也即，在每个数据帧中，对于20路第一信号中的每一路第一信号，高速串行接口011a可以对该路第一信号进行8次采样，得到8位采样值。
图5中还示出了某一路第一信号的原始波形，以及对该路第一信号分别进行4倍采样(即K1＝4)和8倍采样(即K1＝8)后得到的采样波形。基于图5所示的波形可以看出，第一采样频率f1越高，采样得到的信号波形越接近信号的原始波形。
本申请实施例提供的方法，通过采用第一采样频率f1对多路第一信号进行并行采样，一方面能够在一个数据帧中同时传输多路第一信号的数据，从而有效提高了信号的传输效率和传输的灵活性。另一方面，由于第一采样频率f1为数据帧的传输频率的K1倍，因此能够以较高的采样频率对每一路第一信号进行采样，由此可以确保信号失真较少，使得数据传输芯 片01b中的高速串行接口011b能够准确地恢复出第一信号。
可选地，高速串行接口011a发送的数据帧中，多个数据字段所携带的数据可以包括：按照采样时间的先后顺序依次排列的K1个第一采样序列，每个第一采样序列包括对该多路第一信号进行一次并行采样得到的多位采样值。
基于此，高速串行接口011a可以在低速接口012a接收多路第一信号的过程中，同步对该多路第一信号进行并行采样，并同步发送数据帧。也即是，高速串行接口011a可以在基于采样得到的数据生成数据帧的过程中，同步发送该数据帧，而无需等待数据帧的各个字段均封装完成后再发送。由此，有效提高了数据的发送效率。
示例的，假设数据帧包括D0至D19共20个数据字段，每个数据字段的长度为8bit。若K1＝4，则该20个数据字段可以携带4个第一采样序列，每个第一采样序列可以包括对40路第一信号进行一次并行采样得到的40bit的采样值。若K1＝8，则该20个数据字段可以携带8个第一采样序列，每个第一采样序列可以包括对20路第一信号进行一次并行采样得到的20bit的采样值。
可以理解的是，在每个第一采样序列中，对各路第一信号进行采样得到的多个采样值可以按照预先约定的固定顺序排列。例如，每个第一采样序列中的第j位采样值均为对第j路第一信号进行采样得到的采样值，其中，j为不大于X的正整数。由此，可以便于数据传输芯片01b中的高速串行接口011b在从数据帧中获取到多个采样值后，能够基于该固定顺序准确地恢复出各路第一信号。
下文对数据传输芯片01b中的高速串行接口011b接收到数据帧后，从数据帧中恢复多路第一信号的过程进行说明。
在本申请实施例中，高速串行接口011b接收到数据帧后，可以基于数据传输芯片01b的时钟信号的频率对数据帧进行采样，并基于采样得到的数据恢复出多路第一信号。例如，高速串行接口011b能够按照第二采样频率f2对接收到的数据帧进行采样，第二采样频率f2是数据传输芯片01a的时钟信号CLK1的频率的K2倍，K2为大于1的整数，例如K2可以等于4。由于第二采样频率f2是数据传输芯片01a的时钟信号CLK1的频率的K2倍，因此可以确保数据传输芯片01b能够准确采样得到数据帧的各个数据字段中携带的数据。
可以理解的是，高速串行接口011a基于数据传输芯片01a的时钟信号CLK1串行传输数据帧时，高速串行接口011a的数据传输速率可以是时钟信号CLK1的频率的2倍，或者可以小于或等于时钟信号CLK1的频率。
例如，如图6所示，假设高速串行接口011a在时钟信号CLK1的每个下降沿发送1bit数据，则高速串行接口011a的数据传输速率可以等于时钟信号CLK1的频率。或者，若高速串行接口011a在时钟信号CLK1的每个下降沿和每个上升沿均发送1bit数据，则高速串行接口011a的数据传输速率可以等于时钟信号CLK1的频率的2倍。又或者，若高速串行接口011a在时钟信号CLK1的每K0个下降沿(或每K0个上升沿)发送1bit数据，则高速串行接口011a的数据传输速率可以等于时钟信号CLK1的频率的1/K0倍。其中，K0为大于1的整数。
如图7所示，假设数据传输芯片01b的高速串行接口011b接收到数据帧后，按照数据传输芯片01b的时钟信号CLK2的频率对数据帧进行采样，即第二采样频率f2等于时钟信号CLK2的频率，则时钟信号CLK2的频率可以是时钟信号CLK1的频率的K2倍。例如，对比图6和图7可以看出，时钟信号CLK2的频率为时钟信号CLK1的频率的4倍，即K2＝4。
可以理解的是，高速串行接口011b可以在数据传输芯片01b的时钟信号CLK2的每个跳变沿(例如上升沿或下降沿)对数据帧进行一次采样。对于时钟信号CLK2的频率(即第二 采样频率f2)为时钟信号CLK1的频率的K2倍的场景，高速串行接口011b能够在时钟信号CLK2的每K2个跳边沿中，获取K2个跳边沿中第k个跳边沿采样到的采样值，并将第k个跳边沿采样到的采样值作为用于恢复第一信号的数据。其中，k为不大于K2的正整数。
并且，高速串行接口011b还可以基于采样到的帧头的相位偏差，调节k的取值。例如，高速串行接口011b可以在检测到帧头的相位偏差超过时钟信号CLK2的一个时钟周期时，对k的取值进行调整，以确保采样得到的数据的准确性。
可选地，高速串行接口011b还可以在每次采样到间隙字段G0的采样值后，确定已完成对一个数据字段的采样。进而，高速串行接口011b可以基于已采样到的一个数据字段中的数据，进行第一信号的恢复。
示例的，参考图7，假设K2＝4，k＝2，则高速串行接口011b可以在时钟信号CLK2的每4个跳边沿中，获取该4个跳边沿中第2个跳边沿采样到的采样值，并将获取到的采样值存储至寄存器(例如移位寄存器)。也即是，每4个采样脉冲中的第2个采样脉冲为有效的采样脉冲。
并且，高速串行接口011b可以在采样到间隙字段G0的采样值后，生成有效(valid)脉冲，并基于该有效脉冲将寄存器中已存储的采样值作为一个数据字段中携带的数据取出以进行信号的恢复。
基于上文描述可知，高速串行接口011a能够基于数据传输芯片01a的本地时钟信号的频率传输数据帧，高速串行接口011b能够基于数据传输芯片01b的本地时钟信号的频率对接收到的数据帧进行采样。也即是，本申请实施例提供的方案采用了异步时钟进行数据通信。相应的，该高速串行接口也可以称为高速异步串行接口。
相比于采用同步时钟进行数据通信，由于无需高速串行接口011a向高速串行接口011b单独传输时钟信号，因此数据传输芯片之间无需设置用于传输时钟信号的时钟信号线。由此，可以有效减少数据传输芯片之间所需设置的信号线的数量，节约数据传输芯片的引脚资源。
可以理解的是，若高速串行接口011b对数据帧进行采样时的第二采样频率f2是数据传输芯片01a的时钟信号CLK1的频率的K2倍，则数据传输芯片01a的时钟信号CLK1与数据传输芯片01b的时钟信号CLK2之间的频偏容忍度frequency_bias可以满足：frequency_bias＝1/(K2×frame_length)。其中，频偏容忍度是指两个数据传输芯片的本地时钟信号的频率所允许的最大频率偏差。
对于高速串行接口011a对多路第一信号进行并行采样后生成数据帧的场景，高速串行接口011b对数据帧进行采样后得到的数据的可以包括：按照采样时间的先后顺序依次排列的K1个第一采样序列，每个第一采样序列包括多位采样值。相应的，高速串行接口011b基于采样得到的数据恢复多路第一信号的过程可以包括：
对于该多路第一信号中的第j路第一信号，按照K1个第一采样序列的排列顺序，依次从每个第一采样序列中获取第j位采样值，基于按序获取到的K1位采样值，恢复出第j路第一信号。其中，若每个第一采样序列是高速串行接口011a对X路第一信号进行并行采样后得到的，则该j为不大于X的正整数。
可选地，对于该数据传输芯片01b包括多个低速接口012b的场景。在一种可能的示例中，高速串行接口011b接收到的数据帧中的数据字段还可以携带有每一路第一信号的标识，该高速串行接口011b进而可以基于该标识区分各路第一信号，并将各路第一信号传输至对应的低速接口012b。
在另一种可能的示例中，高速串行接口011a可以按照预先约定的固定顺序在数据帧中封 装该多路第一信号，高速串行接口011b采样得到数据帧中的数据后，可以根据该固定顺序恢复并识别多路第一信号，进而将该多路第一信号分别发送至对应的低速接口012b。
作为一种可选的实现方式，如图8所示，两个数据传输芯片01a和01b可以位于电子设备中的同一个PCB。例如，该PCB可以是电子设备的主板。相应的，两个数据传输芯片01a和01b之间的电信号传输介质03可以是PCB上的金属走线。其中，PCB也可以称为单板。例如，对于电子设备为服务器的场景，该PCB可以是服务器单板。
在该实现方式中，电子设备还可以包括位于主板上的主控器件。该主控器件可以是中央处理器(central processing unit，CPU)或微控制单元(microcontroller unit，MCU)等。图8以CPU为例进行示意。该主控器件可以通过并行总线与数据传输芯片01b的低速接口012b连接。数据传输芯片01a的高速串行接口011a将数据帧传输至数据传输芯片01b后，数据传输芯片01b的高速串行接口011b能够对数据帧中的数据进行采样后，存储至其内部寄存器013b。之后，低速接口012b可以将内部寄存器013b中的数据传输至主控器件。
从图8可以看出，数据传输芯片01b中可以包括两组内部寄存器013b，每组内部寄存器013b可以包括一个或多个寄存器。其中一组内部寄存器013b可以存储数据传输芯片01b内部的数据，另一组内部寄存器013b则可以用于存储数据传输芯片01a发送的数据。由于主控器件可以通过并行总线访问两组内部寄存器013b，因此不仅可以获取到数据传输芯片01b中的数据，还能够获取到数据传输芯片01a中的数据。由此，主控器件无需再通过并行总线与数据传输芯片01a连接，从而有效减少了PCB上的信号线的数量。
可选地，如图8所示，数据传输芯片01a的高速串行接口011a还能够与其内部的内部寄存器013a连接。相应的，高速串行接口011a除了可以将低速接口012a接收到的多路第一信号串行传输至数据传输芯片01b，还可以将内部寄存器013a中的数据串行传输至数据传输芯片01b。
作为另一种可选的实现方式，如图2所示，两个数据传输芯片01a和01b可以位于该电子设备中的不同的PCB。示例的，如图2所示，数据传输芯片01a位于电子设备的单板1上，数据传输芯片01b位于电子设备的单板2上。两个数据传输芯片01a和01b之间的电信号传输介质03可以是电信号传输线，例如可以是电缆。或者，电信号传输介质03可以是背板(也可以称为背板连接器)，两个数据传输芯片01a和01b所处的PCB均插装在该背板上，并可以通过该背板通信。
在该实现方式中，电子设备还可以包括至少一个低速器件，以及用于对该至少一个低速器件进行控制的主控器件，该主控器件可以是CPU或MCU等。如图2所示，该主控器件(如CPU)可以与数据传输芯片01a位于同一个PCB，并与数据传输芯片01a的至少一个低速接口连接。该至少一个低速器件可以与数据传输芯片01b位于同一个PCB，并与数据传输芯片01a的至少一个低速接口连接。
其中，与IIC接口连接的低速器件可以包括传感器(如温度传感器或湿度传感器)和带电可擦可编程只读存储器(electrically erasable programmable read only memory，EEPROM)等。与UART接口连接的低速器件可以包括MCU等。与SPI连接的低速器件可以包括闪存(FLASH)等。
基于上述连接方式，主控器件即可通过数据传输芯片中的高速串行接口实现对不同PCB上的多个低速器件的控制。由此，有效减少了电子设备中不同PCB之间的信号线的数量，简化了电子设备的结构。
图9是本申请实施例提供的一种数据传输方法的流程图，图9以CPU通过数据传输芯片 01a和01b向多个低速器件传输多路第一信号为例进行说明。如图9所示，该方法包括：
步骤S11、CPU向数据队列中写入多路第一信号。
其中，该多路第一信号可以是用于对该多个低速器件进行控制的控制命令。
步骤S12、数据传输芯片01a的低速接口读取该多路第一信号。
步骤S13、数据传输芯片01a的高速串行接口011a基于该多路第一信号生成数据帧，并将该数据帧串行发送至数据传输芯片01b。也即，高速串行接口011a可以在数据帧的数据字段中封装该多路第一信号。
步骤S14、数据传输芯片01b的高速串行接口011b接收到该数据帧后，对该数据帧进行解码以恢复出多路第一信号。
步骤S15、数据传输芯片01b的高速串行接口011b将多路第一信号调度至不同的低速接口，以便由各个低速接口传输至对应的低速器件。例如，高速串行接口011b可以将第一信号调度至不同低速接口的控制器，每个低速接口的控制器进而可以将第一信号通过低速接口传输至对应的低速器件。
上文均是以数据传输芯片01a作为数据发送侧的芯片，并以数据传输芯片01b作为数据接收侧的芯片为例进行的介绍。可以理解的是，数据传输芯片01b也可以作为数据发送侧的芯片向数据传输芯片01a串行传输数据帧，即数据传输芯片01a中的高速串行接口011a也可以具有上文所述的高速串行接口011b的功能，高速串行接口011b也可以具有上文所述的高速串行接口011a的功能。
例如，高速串行接口011a还用于接收数据传输芯片01b以数据帧的方式串行发送的多路第二信号，并将该多路第二信号传输至低速接口012a。
可选地，高速串行接口011a能够基于数据传输芯片01a的时钟信号的频率对数据传输芯片01b发送的数据帧进行采样，基于采样得到的数据恢复该多路第二信号。
其中，高速串行接口011a对数据传输芯片01a发送的数据帧进行采样得到的数据可以包括：按照采样时间的先后顺序依次排列的多个第二采样序列，每个第二采样序列包括多位采样值。相应的，该高速串行接口011a，还用于依次从每个第二采样序列中获取一位采样值，基于按序获取到的多位采样值恢复一路第二信号。
高速串行接口011a对接收到的数据帧进行采样以恢复多路第二信号的过程，可以参考上述实施例中关于高速串行接口011b恢复多路第一信号的相关描述，此处不再赘述。
图10是本申请实施例提供的另一种数据传输方法的流程图，图10以多个低速器件通过数据传输芯片01a和01b向CPU传输多路第二信号为例进行说明。如图10所示，该方法可以包括：
步骤S21、数据传输芯片01b的高速串行接口011b对各个低速接口012b进行轮询以获取多路第二信号。
在本申请实施例中，每一路第二信号可以是一个低速器件发送至其所连接的一个低速接口012b的信号。例如，假设图9所示实施例中的第一信号为控制指令，则各个低速器件接收到控制指令后，可以响应于该控制指令，执行相应的操作，并向数据传输芯片01b中对应的低速接口012b返回操作的执行结果。也即，每一路第二信号可以是一个低速器件反馈的执行结果。
步骤S22，数据传输芯片01b的高速串行接口011b基于获取到的多路第二信号生成数据帧，并将该数据帧串行发送至数据传输芯片01a。也即，数据传输芯片01b可以在数据帧的数据字段中封装该多路第二信号，并将封装后生成的数据帧发送至数据传输芯片01a。
步骤S23、数据传输芯片01a的高速串行接口011a接收到该数据帧后，对该数据帧进行解码以恢复出多路第二信号。
步骤S24、数据传输芯片01a的高速串行接口011a将该多路第二信号写入数据队列。
步骤S25、CPU通过数据传输芯片01a的低速接口012a读取该数据队列，以获取该多路第二信号。
作为一种可能的示例，如图2所示，数据传输芯片01a中用于与主控器件连接的低速接口的类型，与数据传输芯片01b中用于与低速器件连接的低速接口的类型可以相同。例如，参考图2，数据传输芯片01a中用于与主控器件连接的低速接口包括：IIC接口、UART接口和SPI接口。相应的，数据传输芯片01b中用于与低速器件连接的低速接口也包括：IIC接口、UART接口和SPI接口。
作为另一种可能的示例，如图11所示，数据传输芯片01a中用于与主控器件连接的低速接口的类型，与数据传输芯片01b中用于与低速器件连接的低速接口的类型可以不同。例如，参考图11，数据传输芯片01a中与主控器件连接的低速接口可以是LBUS接口，数据传输芯片01b与低速器件连接的低速接口则可以包括：IIC接口、UART接口和SPI接口。
可选地，图2所示的示例中，数据传输芯片01a还可以包括LBUS接口，且该数据传输芯片01a中的IIC接口、UART接口和SPI接口可以通过该LBUS接口与CPU连接。
下文以主控器件通过数据传输芯片01a的LBUS接口与数据传输芯片01b的多个IIC接口所连接的低速器件进行通信为例进行介绍。
如图12所示，单板1中的数据传输芯片01a还包括LBUS接口控制器，该LBUS接口控制器能够将主控器件发送至LBUS接口的控制命令写入至LBUS发送队列。该LBUS发送队列可以是先进先出(first input first output，FIFO)队列，例如该发送队列的宽度(width)可以为64bit，深度(depth)可以为512。之后，数据传输芯片01a中的高速串行接口调度器可以从该LBUS发送队列中读取数据，并将读取到的数据(即控制命令)写入高速串行接口011a的发送缓存。该发送缓存的宽度可以等于数据帧中每个数据字段的长度，例如可以为8bit；该发送缓存的深度可以等于数据帧中所包括的数据字段的个数，例如可以为20。
高速串行接口011a可以基于其发送缓存中存储的数据生成数据帧，并将该数据帧串行发送至单板2中的数据传输芯片01b。参考图12，该数据帧可以包括D0至DT共T个数据字段，以及位于该T个数据字段之后的一个校验字段C0。假设每个数据字段的长度W均为8bit，间隙字段的长度M为1bit，则该数据帧的帧头的长度可以为11bit，且包括连续的10bit的1，以及1bit的0，该帧头用十六进制数可以表示为FFE。
继续参考图12，单板2中数据传输芯片01b的高速串行接口011b接收到数据帧后，可以对该数据帧进行解码，并将解码后获取到的数据(即多个数据字段中携带的控制命令)存储至高速串行接口011b的接收缓存。数据传输芯片01b中的高速串行接口调度器可以从接收缓存中读取该控制命令，对该控制命令进行解析后，通过IIC接口写入至对应的低速器件中。低速器件中的IIC控制器进而可以将接收到的控制命令写入命令队列。
图13是单板2中的数据传输芯片01b向单板1中的数据传输芯片01a发送数据的流程图。如图13所示，单板2中的低速器件基于接收到的控制命令执行操作后，IIC控制器可以将操作的执行结果写入低速器件的结果队列。数据传输芯片01b中的高速串行接口调度器可以通过IIC接口，从低速器件的结果队列中读取执行结果，并将执行结果写入至高速串行接口011b的发送缓存。之后，高速串行接口011b即可基于其发送缓存中存储的数据生成数据帧，并将该数据帧串行发送至单板1中的数据传输芯片01a。
单板1中数据传输芯片01a的高速串行接口011a接收到数据帧后，可以对该数据帧进行解码，并将解码后获取到的数据(即多个数据字段中携带的执行结果)存储至高速串行接口011a的接收缓存。数据传输芯片01a中的高速串行接口调度器可以从接收缓存中读取该执行结果，并将该执行结果通过LBUS接口发送至主控器件。
可以理解的是，若数据传输芯片的高速串行接口之间通过信号线(例如金属走线或电缆)连接，则对于数据传输芯片01a向数据传输芯片01b单向发送数据的场景，该两个数据传输芯片的高速串行接口之间可以仅设置一根信号线。对于数据传输芯片01a与数据传输芯片01b之间双向发送数据的场景，如图1所示，该两个数据传输芯片的高速串行接口之间可以设两根信号线，其中一根信号线用于数据传输芯片01a向数据传输芯片01b发送数据帧，另一根信号线用于数据传输芯片01b向数据传输芯片01a发送数据帧。可选地，该高速串行接口之间的信号线也可以称为高速串行总线，或者Hisport总线。
图14是本申请实施例提供的一种数据传输芯片的结构示意图，如图14所示，该数据传输芯片包括至少一个高速串行接口011和至少一个低速接口012。例如，图14中示出了一个高速串行接口011和多个低速接口012。
其中，高速串行接口011可以包括连接端口0111，连接端口0111用于与电信号传输介质03连接。例如，若电信号传输介质03为金属走线，则连接端口0111可以为引脚；若电信号传输介质03为电缆，则连接端口0111可以为电缆接口。
继续参考图14，高速串行接口011还可以包括：
第一采样模块0112，用于对多路第一信号进行采样。
组帧模块0113，用于基于采样得到的数据生成数据帧。
其中，第一采样模块0112可以基于数据传输芯片01a的时钟信号的频率对多路第一信号进行并行采样。
可选地，第一采样模块0112采样得到的数据可以包括按照采样时间的先后顺序依次排列的多个第一采样序列，每个第一采样序列包括对该多路第一信号进行一次并行采样得到的多位采样值。
可选地，连接端口0111还用于数据传输芯片01b串行发送的数据帧；如图14所示，高速串行接口011还可以包括：
第二采样模块0114，用于对连接端口0111接收到的数据帧进行采样，得到多路第二信号。
调度模块0115，用于将该多路第二信号传输至低速接口012。调度模块0115可以为上述实施例中所述的高速串行接口调度器。
可选地，第二采样模块0114，用于基于数据传输芯片01a的时钟信号的频率对该数据帧进行采样，基于采样得到的数据恢复该多路第二信号。
可选地，第二采样模块0114采样得到的数据可以包括按照采样时间的先后顺序依次排列的多个第二采样序列，每个第一采样序列包括多位采样值。第二采样模块0114可以用于：
依次从每个第二采样序列中获取一位采样值，基于按序获取到的多位采样值恢复一路第二信号。
可以理解的是，上文描述的数据传输芯片中的各个模块均可以为电路模块，例如均可以由可编程逻辑电路实现。
综上所述，本申请实施例提供了一种数据传输芯片，该数据传输芯片的低速接口用于接收多路第一信号，该数据传输芯片的高速串行接口用于将该多路第一信号以数据帧的方式串行传输至另一个数据传输芯片。由于数据传输芯片之间能够通过数据帧的方式串行传输多路 信号，因此可以有效减少数据传输芯片之间所需设置的信号线的数量，进而简化电子设备的结构。又由于该高速串行接口的数据传输速率较高，因此可以有效确保该多路第一信号的传输效率。
本申请实施例还提供了一种数据传输芯片，该数据传输芯片包括可编程逻辑电路，该数据传输芯片用于实现上述实施例中所述的数据传输芯片的功能。
上述实施例，可以全部或部分地通过软件、硬件、固件或其他任意组合来实现。当使用软件实现时，上述实施例可以全部或部分地以计算机程序产品的形式实现。所述计算机程序产品包括一个或多个计算机指令。在计算机上加载或执行所述计算机程序指令时，全部或部分地产生按照本发明本申请实施例所述的流程或功能。所述计算机可以为通用计算机、专用计算机、计算机网络、或者其他可编程装置。所述计算机指令可以存储在计算机可读存储介质中，或者从一个计算机可读存储介质向另一个计算机可读存储介质传输，例如，所述计算机指令可以从一个网站站点、计算机、服务器或数据中心通过有线(例如同轴电缆、光纤、数字用户线(DSL))或无线(例如红外、无线、微波等)方式向另一个网站站点、计算机、服务器或数据中心进行传输。所述计算机可读存储介质可以是计算机能够存取的任何可用介质或者是包含一个或多个可用介质集合的服务器、数据中心等数据存储设备。所述可用介质可以是磁性介质(例如，软盘、硬盘、磁带)、光介质(例如，DVD)、或者半导体介质。半导体介质可以是固态硬盘(solid state drive，SSD)。
本申请中术语“至少一个”的含义是指一个或多个，本申请中术语“多个”的含义是指两个或两个以上，例如，多个数据字段是指两个或两个以上的数据字段。
以上所述，仅为本申请的可选实施方式，但本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到各种等效的修改或替换，这些修改或替换都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以权利要求的保护范围为准。

Claims (13)

  1. 一种数据传输芯片，其特征在于，所述数据传输芯片包括高速串行接口和低速接口；
    所述低速接口，用于接收多路第一信号；
    所述高速串行接口，用于将所述多路第一信号以数据帧的方式串行传输至另一数据传输芯片；
    其中，所述高速串行接口的数据传输速率高于所述低速接口的数据传输速率。
  2. 根据权利要求1所述的数据传输芯片，其特征在于，
    所述高速串行接口，用于基于对所述多路第一信号进行采样得到的数据生成所述数据帧。
  3. 根据权利要求2所述的数据传输芯片，其特征在于，
    所述高速串行接口，用于基于所述数据传输芯片的时钟信号的频率对所述多路第一信号进行并行采样。
  4. 根据权利要求3所述的数据传输芯片，其特征在于，所述采样得到的数据包括按照采样时间的先后顺序依次排列的多个第一采样序列，每个所述第一采样序列包括对所述多路第一信号进行一次并行采样得到的多位采样值。
  5. 根据权利要求1至4任一所述的数据传输芯片，其特征在于，
    所述高速串行接口，还用于接收所述另一数据传输芯片以数据帧的方式串行发送的多路第二信号，并将所述多路第二信号传输至所述低速接口。
  6. 根据权利要求5所述的数据传输芯片，其特征在于，
    所述高速串行接口，还用于基于所述数据传输芯片的时钟信号的频率对所述另一数据传输芯片发送的数据帧进行采样，基于采样得到的数据恢复所述多路第二信号。
  7. 根据权利要求6所述的数据传输芯片，其特征在于，对所述另一数据传输芯片发送的数据帧进行采样得到的数据包括：按照采样时间的先后顺序依次排列的多个第二采样序列，每个所述第二采样序列包括多位采样值；
    所述高速串行接口，还用于依次从每个所述第二采样序列中获取一位采样值，基于按序获取到的多位采样值恢复一路第二信号。
  8. 根据权利要求1至7任一所述的数据传输芯片，其特征在于，所述数据传输芯片和所述另一数据传输芯片位于同一个印刷电路板PCB；
    或者，所述数据传输芯片和所述另一数据传输芯片位于不同的印刷电路板。
  9. 根据权利要求1至8任一所述的数据传输芯片，其特征在于，所述数据帧包括：帧头，多个数据字段，以及位于每个所述数据字段之后的一个间隙字段；
    其中，所述帧头包括连续的N位第一数值和M位第二数值，所述多个数据字段用于携带对所述多路第一信号进行采样得到的数据，且每个所述数据字段的长度均为W位，所述间隙 字段包括M位所述第二数值，所述N为大于所述W的正整数，所述M为小于所述W的正整数。
  10. 根据权利要求9所述的数据传输芯片，其特征在于，所述N与所述W的差值大于或等于2，所述M为1。
  11. 根据权利要求9或10所述的数据传输芯片，其特征在于，所述第一数值为1，所述第二数值为0。
  12. 根据权利要求9至11任一所述的数据传输芯片，其特征在于，所述数据帧还包括：位于所述多个数据字段之后的校验字段，以及位于所述校验字段之后的一个所述间隙字段；
    所述校验字段用于携带校验位，且所述校验字段的长度等于所述数据字段的长度。
  13. 一种电子设备，其特征在于，所述电子设备包括数据传输芯片，所述数据传输芯片用于实现如权利要求1至12任一所述的数据传输芯片的功能。
PCT/CN2022/138258 2021-12-10 2022-12-11 数据传输芯片及电子设备 WO2023104210A1 (zh)

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CN110049512A (zh) * 2019-04-22 2019-07-23 武汉虹信通信技术有限责任公司 一种前传网络数据处理装置及方法
CN112003816A (zh) * 2020-06-22 2020-11-27 武汉光迅科技股份有限公司 数据传输方法、装置、设备及存储介质

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