WO2023102698A1 - 晶体管装置及其制备方法、电子器件 - Google Patents

晶体管装置及其制备方法、电子器件 Download PDF

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WO2023102698A1
WO2023102698A1 PCT/CN2021/135847 CN2021135847W WO2023102698A1 WO 2023102698 A1 WO2023102698 A1 WO 2023102698A1 CN 2021135847 W CN2021135847 W CN 2021135847W WO 2023102698 A1 WO2023102698 A1 WO 2023102698A1
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electrode
layer
transistor device
dielectric layer
transistor
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PCT/CN2021/135847
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English (en)
French (fr)
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殷士辉
景蔚亮
黄凯亮
冯君校
王正波
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华为技术有限公司
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Priority to CN202180103907.9A priority Critical patent/CN118202472A/zh
Priority to PCT/CN2021/135847 priority patent/WO2023102698A1/zh
Publication of WO2023102698A1 publication Critical patent/WO2023102698A1/zh

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  • the present application relates to the technical field of semiconductors, in particular to a transistor device, a manufacturing method thereof, and an electronic device.
  • the reading speed of the gain-cell memory can be as low as nanoseconds. It adopts a two-transistor device structure, which can reduce the occupied area of the device unit, and can realize high-speed reading and writing and high-density integration.
  • Due to the leakage phenomenon inside the storage unit it needs to be refreshed at regular intervals to maintain the integrity of the data in practical applications, thus bringing relatively large dynamic power consumption.
  • Utilizing ultra-low leakage thin film transistors (thin film transistors, TFTs) as transistors in gain cell memory can reduce dynamic power consumption and improve the memory market.
  • the operating current of the read transistor in the gain unit memory is relatively small, which results in the limitation of the operating frequency of the read transistor.
  • the present application provides a transistor device, a preparation method thereof, and an electronic device.
  • the transistor device can adjust the channel width to increase the channel current, and when used as a read transistor to read data, the read speed can be improved.
  • the present application provides a transistor device, which can be applied to devices such as memories and meet the channel width requirements of such devices.
  • the transistor device specifically includes a substrate structure, an electrode structure is provided on the substrate structure, and the electrode structure includes at least two electrode layers alternately arranged in the first direction, and any two adjacent electrodes in the at least two electrode layers Layers are electrically isolated to prevent short-circuiting of the electrodes; the at least two electrode layers include at least one source and at least one drain, and when the number of sources is at least two, any two sources are electrically connected to form the entire The source of the transistor device, when the number of drains is at least two, any two drains are electrically connected to form the drain of the entire transistor device, so that when the transistor device is connected to an external device, a source interface and a drain interface.
  • the above-mentioned first direction is perpendicular to the substrate structure.
  • a first electrode is also arranged on the substrate structure.
  • a channel layer is also provided on the substrate structure, the channel layer is located between the first electrode and the electrode structure, the channel layer is in contact with any electrode layer, and the first electrode corresponds to at least part of the channel layer along the second direction,
  • the second direction is perpendicular to the first direction.
  • a channel can be formed between any adjacent source and drain, and the first electrode can regulate the concentration of carriers in the channel between any two electrode layers; when the first electrode is turned on, the first electrode can Drive the movement of electrons in the channel layer between any adjacent source and drain to form channel current.
  • the distance between the source and the drain along the first direction corresponds to the length of the channel, and the length of the surface of the source (or drain) in contact with the channel layer perpendicular to the first direction corresponds to the width of the channel.
  • the number of electrode layers is n
  • n-1 channels can be formed, and within the reasonable height range of the transistor device, increasing the electrode layer (that is, alternately increasing the source/drain) can increase the channel.
  • Quantity and then increase the effective channel width of the transistor device, on the basis of constant factors such as the atomic mobility of the transistor device, channel length, gate oxide thickness, etc., the size of the channel current can be increased.
  • the transistor device further includes an isolation dielectric layer, the isolation dielectric layer is generally arranged on the surface of the first electrode, and the isolation dielectric layer is located between the first electrode and the electrode structure, so that the first electrode and the electrode structure are electrically isolated, the first The electrode is electrically isolated from the channel layer; in some embodiments, an isolation dielectric layer is disposed between the first electrode and the channel layer.
  • the isolation dielectric layer is equivalent to a gate dielectric layer.
  • the transistor device may have different structural forms, and in one of the structures, along the second direction, the channel layer may be arranged outside the first electrode, and the electrode structure may be arranged outside the channel layer; equivalent to setting in the electrode structure
  • There is a first groove the first groove extends along the first direction, and the first groove communicates with the at least two electrode layers; the first electrode is arranged in the first groove, and the bottom surface and the side surface of the first groove are sequentially
  • a channel layer and an isolation dielectric layer are stacked, wherein the isolation dielectric layer is in contact with the first electrode, and the channel layer is in contact with any one of the electrode layers.
  • the projection of the channel layer on the substrate structure covers the projection on the substrate structure of the end of the first electrode facing the substrate structure.
  • the electrode structure forms a column shape
  • the channel layer may be disposed outside the electrode structure
  • the first electrode is disposed outside the channel layer.
  • the projection of the channel layer on the substrate structure covers the projection on the substrate structure of the end of the electrode structure remote from the substrate structure.
  • an insulating layer can be provided at the contact interface between each electrode layer and the channel layer, A metal-insulator-semiconductor structure may be formed at an interface where the electrode layer is in contact with the channel layer.
  • the thickness range of the insulating layer may be selected to be 0.1-2 nanometers (nanometer, nm).
  • the electrical isolation between any two adjacent electrode layers includes: disposing an electrode dielectric layer between any two adjacent electrode layers, so as to electrically isolate the two electrode layers.
  • the distance between any two adjacent electrode layers can be set to be the same.
  • each structure in the transistor device is as follows: the material of the electrode layer is titanium (titanium, Ti), gold (aurum, Au), tungsten (tungsten, W), aluminum (aluminum, Al), copper (cuprum, Cu) , ruthenium (ruthenium, Ru), molybdenum (molybdenum, Mo), silver (argentum, Ag), platinum (platinum, Pt), bismuth (bismuth, Bi), titanium nitride (titanium nitride, TiN), tungsten nitride ( tungsten nitride, WN), indium tin oxide (indium tin oxide, ITO) or indium zinc oxide (indium tin oxide, IZO) or a combination of one or more; the material of the first electrode is titanium, gold, tungsten, aluminum , copper, ruthenium, molybdenum, silver, platinum, titanium nitride, indium tin oxide or indium zinc oxide; the material of the first
  • the present application also provides a transistor device, which specifically includes a first electrode, a pocket structure, and a connection structure;
  • the pocket structure includes an inner structure layer and an outer structure layer, and the inner structure layer and the outer structure layer are nested inside and outside;
  • the structural layer includes a doped semiconductor material, and the inner structural layer forms a pocket for accommodating the above-mentioned first electrode;
  • the outer structural layer is wrapped outside the inner structural layer;
  • the outer structural layer is equivalent to the electrode structure, including the first electrodes stacked in sequence Layer, the first dielectric layer, the second electrode layer, the second dielectric layer and the third electrode layer, the first dielectric layer is used to isolate the first electrode layer and the second electrode layer, to prevent the first electrode layer and the second electrode layer from being short connected;
  • the second dielectric layer is used to isolate the second electrode layer and the third electrode layer to prevent the second electrode layer and the third electrode layer from being short-circuited;
  • the first electrode can be used as the gate of the transistor device
  • the inner structure layer can be used as the channel layer of the transistor device
  • the first electrode layer, the second electrode layer and the third electrode layer in the outer structure layer can be used as As the source and drain of the transistor device; wherein, the polarity of the first electrode layer and the third electrode layer are the same (the same as the source or the same as the drain), and the second electrode layer is the same as the first electrode layer and the third electrode layer. opposite (when the first electrode layer and the third electrode layer are the source, the second electrode layer is the drain; when the first electrode layer and the third electrode layer are the drain, the second electrode layer is the source).
  • the transistor device further includes an isolation dielectric layer disposed outside the first electrode, and the isolation dielectric layer is located between the first electrode and the inner structure layer.
  • the isolation dielectric layer here can be used as a gate dielectric layer of the transistor device to prevent the gate (that is, the first electrode) from being short-circuited with other electrodes.
  • Both the first dielectric layer and the second dielectric layer are electrode dielectric layers, and the materials of the first dielectric layer and the second dielectric layer can be the same.
  • the present application also provides a transistor device, which specifically includes an electrode structure, a pocket structure, and a connection structure;
  • the electrode structure includes a first electrode layer, a first dielectric layer, a second electrode layer, a second dielectric layer and The third electrode layer, the first dielectric layer is used to isolate the first electrode layer and the second electrode layer to prevent the first electrode layer and the second electrode layer from being short-circuited;
  • the second dielectric layer is used to isolate the second electrode layer and the third electrode layer layer, preventing the second electrode layer and the third electrode layer from being short-circuited;
  • the pocket structure includes an inner structure layer and an outer structure layer, and the inner structure layer and the outer structure layer are nested inside and outside;
  • the inner structure layer includes a doped semiconductor material,
  • the inner structure layer forms a pocket for accommodating the above-mentioned electrode structure;
  • the outer structure layer is wrapped outside the inner structure layer; wherein, the first electrode layer and the third electrode layer are electrically connected through a connection structure, and the connection structure can
  • the first electrode can be used as the gate of the transistor device
  • the inner structure layer can be used as the channel layer of the transistor device
  • the first electrode layer, the second electrode layer and the third electrode layer in the electrode structure can be used as The source and drain of the transistor device; wherein, the first electrode layer and the third electrode layer have the same polarity (the same as the source or the same as the drain), and the second electrode layer has the same polarity as the first electrode layer and the third electrode layer
  • the second electrode layer is the drain; when the first electrode layer and the third electrode layer are the drain, the second electrode layer is the source.
  • the transistor device further includes an isolation dielectric layer disposed on the surface of the first electrode facing the electrode structure (equivalent to the inner wall of the outer structure layer), and the isolation dielectric layer is located between the first electrode and the inner structure layer.
  • the isolation dielectric layer here can be used as the isolation dielectric layer of the transistor device to prevent the gate (that is, the first electrode) from being short-circuited with other electrodes.
  • Both the first dielectric layer and the second dielectric layer are electrode dielectric layers, and the materials of the first dielectric layer and the second dielectric layer can be the same.
  • the present application also provides an electronic device, taking a memory as an example, the electronic device includes a write transistor, a read transistor, a storage unit, a first write signal line, a second write signal line, a first read signal line, and a second Two read signal lines, wherein the read transistor is any one of the above-mentioned transistor devices; the first write signal line is connected to the first electrode of the write transistor, and the second write signal line is connected to the source of the write transistor; the first read signal line is connected to the source of the write transistor.
  • the source of the read transistor is connected, the second read signal line is connected with the drain of the read transistor; the drain of the write transistor is connected with the first electrode structure of the read transistor, and the storage unit is connected between the write transistor and the read transistor. Since the channel current can be increased by the transistor device used as a read transistor, the read delay can be reduced when reading data.
  • the present application also provides a method for preparing a transistor device, which can be used to prepare part of the above-mentioned transistor device, and the preparation method specifically includes:
  • electrode layers and electrode dielectric layers are arranged alternately on the substrate structure to form an electrode structure; there are at least two electrode layers, and the at least two electrode layers include at least one source electrode and at least one drain electrode arranged alternately pole, when there are at least two sources, any two sources are electrically connected, when there are at least two drains, any two drains are electrically connected;
  • a first electrode is formed in the second groove.
  • the formation of the first electrode in the second groove includes:
  • the first electrode is formed in the third groove.
  • the present application also provides a method for preparing a transistor device, which can be used to prepare another part of the above-mentioned transistor device.
  • the preparation method specifically includes:
  • electrode layers and electrode dielectric layers are arranged alternately on the substrate structure to form an electrode structure; there are at least two electrode layers, and the at least two electrode layers include at least one source electrode and at least one drain electrode arranged alternately pole, when there are at least two sources, any two sources are electrically connected, when there are at least two drains, any two drains are electrically connected;
  • a first electrode is formed outside the channel layer.
  • the isolation dielectric layer is disposed on the surface of the first electrode, and the isolation dielectric layer is located between the first electrode and the channel layer; the formation of the first electrode outside the channel layer includes:
  • the first electrode is formed outside the isolation dielectric layer.
  • FIG. 1a and FIG. 1b are schematic diagrams of circuit principles of a gain unit memory in the prior art
  • FIG. 2 is a schematic structural diagram of a transistor device provided in an embodiment of the present application.
  • FIG. 3 is a schematic cross-sectional structure diagram of a transistor device cut along plane A provided by an embodiment of the present application;
  • 4a to 4d are schematic cross-sectional structural views of the transistor device shown in FIG. 3 cut along plane B;
  • 5a to 5d are schematic cross-sectional structural diagrams of a transistor device cut along plane A according to an embodiment of the present application.
  • FIG. 6 is a schematic cross-sectional structure diagram of a transistor device cut along plane A according to an embodiment of the present application.
  • FIG. 7a to 7e are schematic cross-sectional structural views of the transistor device shown in FIG. 6 cut along plane B;
  • FIG. 8 is a schematic cross-sectional structure diagram of another transistor device cut along plane A according to an embodiment of the present application.
  • 9a to 9d are schematic cross-sectional structural diagrams of the transistor device shown in FIG. 8 cut along plane B;
  • FIG. 10 is a schematic cross-sectional structure diagram of a transistor device cut along plane A according to an embodiment of the present application.
  • FIG. 11a to 11e are schematic cross-sectional structural diagrams of the transistor device shown in FIG. 10 cut along plane B;
  • 12a to 12c are schematic structural diagrams of an isolation dielectric layer in a transistor device provided in an embodiment of the present application.
  • Fig. 13a is an electrical characterization diagram of the first electrode voltage and the channel current of the transistor device in the prior art
  • Fig. 13b is an electrical characterization diagram of the first electrode voltage and channel current of a transistor device provided in the embodiment of the present application;
  • FIG. 14 is a schematic diagram of the circuit principle of an electronic device provided in the embodiment of the present application.
  • FIG. 15 is a schematic diagram of a method for preparing a transistor device provided in an embodiment of the present application.
  • FIG. 16 is a schematic diagram of an electrode structure formed during the preparation of a transistor device provided in an embodiment of the present application.
  • 17a to 17c are schematic diagrams of structural changes of the transistor device shown in FIG. 3 during the fabrication process;
  • FIG. 18 is a schematic diagram of another method of manufacturing a transistor device provided in the embodiment of the present application.
  • 19a to 19c are schematic diagrams of structural changes of the transistor device shown in FIG. 8 during the fabrication process.
  • Icons 1-write transistor; 2-read transistor; 3-memory unit; 41-first write signal line; 42-second write signal line; 51-first read signal line; 52-second read signal line; 11 -substrate structure; 12-functional structure; 121-first electrode; 122-channel layer; 123-electrode structure; 1231-source; 1232-drain; 1233-dielectric layer; 124-isolating dielectric layer; Insulation.
  • vertical thin film transistors can achieve high-speed reading and writing and high-density integration.
  • the gain unit memory can use two vertical thin film transistors, because the conduction channel of the thin film transistor is selected from an amorphous metal oxide with extremely low leakage characteristics (such as indium gallium zinc oxide, indium gallium zinc oxide, IGZO) or other wide bandgap semiconductor materials can reduce dynamic power consumption and meet storage requirements.
  • amorphous metal oxide with extremely low leakage characteristics such as indium gallium zinc oxide, indium gallium zinc oxide, IGZO
  • memory cells can be applied to back end of line (BEOL) processes to achieve heterogeneous integration and stack integration, which can improve memory density.
  • BEOL back end of line
  • choosing a thin film transistor with a vertical structure can improve the area utilization rate, which is beneficial to the realization of a memory array with high integration density, so that the occupied area of each memory cell is close to 4F 2 (F refers to half of a byte distance), and this parameter is only One-third of static random-access memory (SRAM).
  • F refers to half of a byte distance
  • the gain unit memory includes a write transistor (write transistor, WTR), a read transistor (read transistor, RTR), and storage nodes (storage nodes, SN) connected between the write transistor and the read transistor;
  • WTR write transistor
  • RTR read transistor
  • storage nodes storage nodes
  • SN storage nodes
  • the write transistor is controlled by the write word line (WWL), and the potential of the write bit line (WBL) is transferred to the gate of the read transistor, so that the gate potential of the read transistor is the same as
  • the write bit line is synchronized to realize the writing of "0" and "1"; then, the write bit line controls the write transistor to turn off, and the gate potential of the read transistor is determined by the power stored in the node, because the leakage of the thin film transistor is higher than that of silicon
  • the transistor is much lower, and the current on the gate of the read transistor leaks through the write transistor is improved, which can increase the storage time of the memory.
  • Fig. 1b including a precharge transistor (precharge transistor, PTR), a signal readout transistor (sense transistor, STR) and a capacitor (capacitor, Cap) of at least one ferroelectric material connected between the precharge transistor and the read transistor;
  • precharge transistor precharge transistor, PTR
  • sense transistor sense transistor
  • Cap capacitor
  • the opening of the precharge transistor is controlled by the control line (control line, CL).
  • the read transistor or the signal readout transistor is a thin film transistor, and since the conductive channel material of the thin film transistor has a low mobility, its operating current is relatively small, so that the operating frequency of the read transistor or the signal readout transistor is limited.
  • the embodiment of the present application provides a transistor device and its preparation method, and an electronic device.
  • the transistor device is a thin film transistor, and its operating current can be increased by increasing the effective channel width of the transistor device.
  • the read delay can be reduced.
  • references to "one embodiment” or “some embodiments” or the like in this specification means that a particular feature, structure, or characteristic described in connection with the embodiment is included in one or more embodiments of the present application.
  • appearances of the phrases “in one embodiment,” “in some embodiments,” “in other embodiments,” “in other embodiments,” etc. in various places in this specification are not necessarily All refer to the same embodiment, but mean “one or more but not all embodiments” unless specifically stated otherwise.
  • the terms “including”, “comprising”, “having” and variations thereof mean “including but not limited to”, unless specifically stated otherwise.
  • an embodiment of the present application provides a transistor device, which can be used as a read transistor in a memory circuit, and can also be applied in logic, analog, radio frequency circuits and other scenarios that require different transistor width options.
  • the transistor device includes a substrate structure 11 and a functional structure 12 disposed on the substrate structure 11 (including but not limited to structures such as source, drain, and gate, for realizing transistor functions), it should be understood that the “Above the substrate structure 11 ” only illustrates the relative positional relationship, and does not limit the connection relationship between the functional structure 12 and the substrate structure 11 . That is, taking the structure of the entire transistor device as a reference, the substrate structure 11 is equivalent to being located at the bottom of the transistor.
  • the substrate structure 11 can be correspondingly arranged on the carrying surface for carrying the transistor device, and the functional structures 12 are all located on the substrate structure. 11 away from the side of the bearing surface.
  • the substrate structure 11 may be the base of the transistor device when it is used alone, and plays a supporting role.
  • the functional structure 12 of the transistor device except the substrate structure 11 can be directly stacked on the substrate of the semiconductor device to realize the function of the transistor, and the substrate of the semiconductor device can serve as the transistor device Substrate structure 11.
  • the substrate structure 11 refers to the structure prepared in the front-end process of the semiconductor device, and the preparation of the functional structure 12 of the transistor device except the substrate structure 11 can be realized in the back-end process of semiconductor device preparation.
  • the substrate structure 11 may specifically include one or a combination of elemental semiconductors, compound semiconductors, alloy semiconductors, or other materials, wherein the elemental semiconductors may include single crystal silicon, polycrystalline silicon, single crystal germanium (Ge), polycrystalline Crystalline germanium (polycrystalline germanium, poly-Ge), amorphous structure, etc.
  • compound semiconductors can include silicon carbide (silicon carbide, SiC), gallium arsenide (gallium arsenide, GaAs), gallium phosphide (gallium phosphide, GaP), phosphorus Indium phosphide (InP), indium arsenide (InAs), indium antimonide (InSb), etc.
  • Alloy semiconductors can include silicon-germanium (SiGe), aluminum indium arsenide (aluminum indium arsenide (AlInAs), aluminum gallium arsenide (aluminum gallium arsenide, AlGaAs), indium gallium arsenide (indium gallium arsenide, InGaAs), gallium indium phosphide (GaInP), gallium indium phosphide (gallium indium phosphide arsenide, GaInPAs) and so on.
  • SiGe silicon-germanium
  • AlInAs aluminum indium arsenide
  • AlGaAs aluminum gallium arsenide
  • AlGaAs aluminum gallium arsenide
  • indium gallium arsenide indium gallium arsenide
  • InGaAs gallium indium phosphide
  • GaInPAs gallium indium phosphide arsenide arsenide
  • the first direction Z, the second direction X, and the third direction Y are set to be perpendicular to each other.
  • the stacking direction of the substrate structure 11 and the functional structure 12 of the transistor device is the first direction Z, and the first direction Z perpendicular to the substrate structure 11.
  • the structure of the transistor device may be implemented in many ways.
  • the specific structure of the transistor device can be obtained by cutting the transistor device on the plane A perpendicular to the third direction Y and the plane B perpendicular to the first direction Z. Next, we will pass The specific diagrams introduce the transistor device.
  • FIG. 3 shows a schematic cross-sectional structure diagram of a transistor device cut by plane A, wherein the functional structure 12 specifically includes a first electrode 121 , a channel layer 122 , an electrode structure 123 , and an isolation dielectric layer 124 .
  • the first electrode 121 can be used as the gate of the transistor device.
  • the first electrode 121 is columnar and extends along the first direction Z. Specifically, the first electrode 121 can be a column, a prism or other irregular column, and its length direction is parallel. in the first direction Z.
  • the isolation dielectric layer 124 is equivalent to a gate dielectric layer.
  • a pedestal M parallel to the substrate structure 11 can also be formed at the end of the first electrode 121 away from the substrate structure 11, and the pedestal M can be parallel to the substrate structure 11.
  • the channel layer 122 includes a doped semiconductor material, and the doped atoms can provide carriers, which can be used to conduct electric current.
  • the electrode structure 123 specifically includes at least two electrode layers stacked in sequence along the first direction Z and an electrode dielectric layer located between any two electrode layers, specifically including a first electrode layer, a first dielectric layer, and a second electrode stacked in sequence.
  • the first dielectric layer is used to isolate the first electrode layer and the second electrode layer, to prevent the first electrode layer and the second electrode layer from short circuit;
  • the second dielectric layer is used to isolate the first electrode layer
  • the second electrode layer and the third electrode layer prevent the second electrode layer and the third electrode layer from being short-circuited;
  • the stacking direction here is equivalent to the first direction Z, and the stacking direction can be from the substrate structure 11 to the base M, or It may be directed from the base M to the substrate structure.
  • the electrodes of the first electrode layer and the third electrode layer have the same polarity (both source or drain), and the second electrode layer is opposite to the polarity of the first electrode layer and the third electrode layer (when the first electrode layer When the first electrode layer and the third electrode layer are source electrodes, the second electrode layer is a drain electrode; when the first electrode layer and the third electrode layer are drain electrodes, the second electrode layer is a source electrode).
  • the first electrode layer and the third electrode layer are set as two drain electrodes 1232
  • the second electrode layer is set as one source electrode 1231
  • both the first dielectric layer and the second dielectric layer are electrodes. Dielectric layer 1233 .
  • the first electrode 121 is columnar and extends along the first direction Z, and the channel layer 122 is along the circumferential outer surface of the first electrode 121 (that is, the outer surface of the first electrode 121 parallel to the first direction Z). surface); the electrode structure 123 is arranged along the circumferential outer surface of the channel layer 122 (that is, the channel layer 122 is parallel to the outer surface of the first square array Z); specifically, the channel layer 122 is arranged on the first electrode 121 The peripheral outer surface and the end surface of the first electrode 121 extending along the first direction Z, the channel layer 122 also covers the surface of the base M facing the substrate structure 11 .
  • the isolation dielectric layer 124 is disposed between the channel layer 122 , the first electrode 121 and the base M. As shown in FIG. The electrode structure 123 is disposed outside the channel layer 122 . An isolation dielectric layer 124 is provided on the surface of the first electrode 121, and the isolation dielectric layer 124 is located between the first electrode 121 and the channel layer 122 (it can also be regarded as the isolation dielectric layer 124 located between the first electrode 121 and the electrode structure 123 ), can electrically isolate the first electrode 121 from the electrode structure 123 .
  • the electrode structure 123 is equivalent to comprising a first electrode layer (drain electrode 1232), a first dielectric layer (electrode dielectric layer 1233), a second electrode layer (source electrode 1231), a second dielectric layer ( Electrode dielectric layer 1233), the third electrode layer (drain 1232), any two adjacent electrode layers are equivalent to achieving electrical isolation through the electrode dielectric layer 1233, preventing short-circuiting between two adjacent electrode layers.
  • the first electrode layer and the third electrode layer (corresponding to the two drain electrodes 1232 ) are electrically connected through a connection structure (such as a wire, not shown here).
  • an electrode dielectric layer 1233 is also disposed between the electrode layer closest to the base M and the channel layer 122 .
  • the channel layer 122 is in contact with any electrode layer, and two adjacent electrode layers (equivalent to a source electrode 1231 and a drain electrode 1232) can pass through the two electrodes driven by the first electrode 121.
  • the channel layer 122 between the layers realizes electron transmission to form a channel current, electrons flow in the channel layer 122 , and the structural parameters of the channel layer 122 will affect the magnitude of the current between the source and the drain.
  • the distance between two adjacent electrode layers (corresponding to a source 1231 and a drain 1232 ) is equivalent to the channel of the channel layer 122 between the two electrode layers. Length L.
  • the first electrode 121 corresponds to the channel layer 122 between any two electrode layers.
  • the first electrode layer and the third electrode layer in FIG. 3 can also be the source electrode 1231, and the second electrode layer corresponds to the drain electrode 1232, which is not limited here; and FIG. 3 is equivalent to showing the
  • the transistor device provided in the embodiment is the simplest structure. In specific applications, the number of electrode layers can be more according to the structure of the transistor device. It only needs to be electrically isolated, and the electrode layers of the same polarity are electrically connected.
  • any two sources 1231 are electrically connected to serve as the source of the transistor device; when the number of electrode layers used as the drain 1232 is greater than or equal to 2, any The two drains 1232 are electrically connected and can serve as the drain of the transistor device.
  • the source electrode 1231 and the drain electrode 1232 are used to directly refer to a certain electrode layer, and the dielectric layer 1233 is used to directly refer to a certain electrode dielectric layer.
  • Fig. 4a shows a schematic cross-sectional structure diagram of the transistor device in Fig. 2 cut by plane B, where plane B is perpendicular to the first direction Z and passes through one of the electrode layers.
  • the isolation dielectric layer 124 surrounds the first electrode 121
  • the channel layer 122 surrounds the isolation dielectric layer 124
  • the electrode structure 123 (shown here as Electrode layer) surrounds the channel layer 122
  • the cross section of the first electrode 121 can be circular
  • the cross section of the channel layer 122, the electrode structure 123, and the isolation dielectric layer 124 are all concentric circular rings.
  • the length of the line of intersection between the surface of the channel layer 122 in contact with the electrode layer and the surface perpendicular to the first direction Z is equivalent to the channel width W of the channel between two adjacent electrode layers.
  • the transistor device When the transistor device has n electrode layers, n is greater than or equal to 2, and there is a channel between every two electrode layers, the transistor device will have n-1 channels, which is equivalent to having n-1 channel widths W , the effective channel width W total of the entire transistor device ⁇ (n-1)W; along the first direction Z, within the reasonable size range of the transistor device, increasing the number of electrode layers can increase the effective channel width W total , It is beneficial to increase the current size of the transistor device.
  • the transistor device provided by the embodiment of the present application is viewed from the final structural form
  • the electrode structure 123 and the channel layer 122 are equivalent to forming a pocket structure with a storage space
  • the storage space has an opening
  • the opening faces the second
  • the base M of an electrode 121 has an accommodation space for accommodating the first electrode 121 .
  • the channel layer 122 is equivalent to the inner structural layer of the pocket structure
  • the electrode structure 123 is equivalent to the outer structural layer of the pocket structure
  • the electrode structure 123 is wrapped outside the channel layer 122 .
  • each electrode layer (such as the first electrode layer, the second electrode layer and the third electrode layer) and the electrode dielectric layer (such as the first dielectric layer and the second electrode layer) in the electrode structure 123
  • the second dielectric layer is circular and surrounds the outside of the channel layer 122 .
  • Fig. 4b shows another schematic cross-sectional structure diagram of the transistor device in Fig. 2 after being cut by the B surface, similar to the structure shown in Fig. 4a, the isolation dielectric layer 124 surrounds the first electrode 121, and the channel layer 122 surrounds the isolation dielectric Layer 124 , electrode structure 123 (shown here as an electrode layer) surrounds channel layer 122 .
  • the cross section of the first electrode 121 may be rectangular, and the cross sections of the isolation dielectric layer 124, the channel layer 122 and the electrode structure 123 are all square rings. It should be understood that the cross section of the first electrode 121 may also be other polygons (such as the hexagon shown in FIG. The shape of the electrode 121 corresponds to a polygonal ring. The cross-section of the first electrode 121 may also be other irregular shapes (for example, the quasi-parabolic shape shown in FIG. 121 shapes correspond to irregularly shaped rings.
  • the cross section of the isolation dielectric layer 124, the channel layer 122, and the electrode structure 123 may not correspond to the shape of the first electrode 121 (for example, the cross section of the first electrode 121 is circular, and the isolation dielectric layer 124 The cross section of the channel layer 122 and the cross section of the electrode structure 123 are square rings), which will not be repeated here.
  • FIG. 5a to 5d show schematic cross-sectional structures of other transistor devices cut by plane A.
  • FIG. 5 a the isolation dielectric layer 124 covers the surface of the first electrode 121 facing the channel layer 122 , and the isolation dielectric layer 124 electrically isolates the electrode structure 123 from the first electrode 121 .
  • the channel layer 122 is located outside the isolation dielectric layer 124 , and there are some intersections between the channel layer 122 and the electrode structure 123 .
  • the electrode structure 123 has a drain 1232 , a source 1231 , and a drain 1232 sequentially distributed along the first direction Z, and the crossing between the channel layer 122 and the electrode structure 123 means: the drain 1232 closest to the substrate structure 11
  • the source electrode 1231 is located outside the channel layer 122
  • the drain electrode 1232 closest to the base M is located between the isolation dielectric layer 124 and the channel layer 122 . Comparing the transistor device shown in FIG. 5b with the transistor device shown in FIG. 5a, the difference is that in FIG. The surfaces of the bottom structure 11 are located in the same plane. In the transistor device shown in FIG.
  • the isolation dielectric layer 124 covers the surface of the first electrode 121 facing the channel layer 122 , and the isolation dielectric layer 124 electrically isolates the electrode structure 123 from the first electrode 121 .
  • the channel layer 122 is located between the isolation dielectric layer 124 and the electrode structure 123. Specifically, the channel layer 122 is only provided on the circumferential outer surface of the first electrode 121, and does not cover the first electrode 121 toward the substrate along the first direction Z. end of the bottom structure 11. On the side of the end of the first electrode 121 facing the substrate structure 11 , the isolation dielectric layer 124 is in contact with the drain 1232 closest to the substrate structure 11 . In FIG.
  • an insulating layer 125 is provided between the electrode layer and the channel layer 122.
  • the insulating layer The existence of 125 can form a metal-insulator-semiconductor structure between the electrode layer and the channel layer 122 .
  • the thickness of the insulating layer 125 can be set at 0.1-2 nm.
  • the embodiment of the present application further provides a transistor device as shown in FIG. 6 .
  • the first electrode 121 in the transistor device is similar to the first electrode 121 in the transistor device shown in FIG. 3 , that is, the first electrode 121 is columnar and extends along the first direction Z.
  • a pedestal M is also provided at the end of the first electrode 121 away from the substrate structure 11 , and the pedestal M is parallel to the substrate structure 11 .
  • the channel layer 122 is arranged along the circumferential outer surface of the first electrode 121, but the channel layer 122 does not completely wrap the circumferential outer surface of the first electrode 121, and the electrode structure 123 is arranged along the circumferential outer surface of the channel layer 122, But the electrode structure 123 does not completely wrap the peripheral outer surface of the channel layer 122 .
  • the isolation dielectric layer 124 is disposed between the channel layer 122 and the first electrode 121 and between the channel layer 122 and the base M, and the isolation dielectric layer 124 can electrically isolate the first electrode 121 from the electrode structure 123 .
  • the electrode structure 123 includes at least two electrode layers arranged along the first direction Z, and any two adjacent electrode layers are electrically isolated by the electrode dielectric layer 1233 to prevent short-circuiting between two adjacent electrode layers.
  • the electrode structure 123 exemplarily includes three electrode layers (one source 1231 and two drains 1232 ), and the source 1231 is located between the two drains 1232 .
  • an electrode dielectric layer 1233 is also disposed between the electrode layer closest to the base M and the channel layer 122 .
  • the first electrode 121 corresponds to the channel layer 122 between any two electrode layers.
  • the transistor device shown in FIG. 6 is cut on the plane of B in FIG. 2 to obtain the schematic cross-sectional structure shown in FIG.
  • the electrode 121 , the channel layer 122 half surrounds the isolation dielectric layer 124 , and the electrode structure 123 (here shown as an electrode layer) half surrounds the channel layer 122 .
  • the length of the line of intersection between the surface of the channel layer 122 in contact with the electrode layer and the surface perpendicular to the first direction Z is equivalent to the channel width W of the channel between any two adjacent electrode layers.
  • FIG. 7b Based on the cross-sectional structure of another transistor device shown in FIG. 6 along the plane B-B, it can be referred to as shown in FIG. 7b. Similar to the structure shown in FIG. 7a, the isolation dielectric layer 124 half surrounds the first electrode 121, and the channel layer 122 half surrounds The dielectric layer 124 is isolated, and the electrode structure 123 (shown here as an electrode layer) semi-surrounds the channel layer 122 . The difference is that in this transistor device, the cross section of the first electrode 121 is rectangular, and the cross sections of the isolation dielectric layer 124 , the channel layer 122 and the electrode structure 123 are all half-rings in a zigzag shape.
  • the cross section of the first electrode 121 may also be other polygons (such as shown in FIG. half-ring of the line.
  • the cross-section of the first electrode 121 may also be other irregular shapes (for example, the fan-like shape shown in FIG. The shape corresponds to the irregularly shaped ring.
  • the cross section of the isolation dielectric layer 124 , the channel layer 122 and the electrode structure 123 may not correspond to the shape of the first electrode 121 , so details will not be repeated here.
  • the first electrode 121, the isolation dielectric layer 124, the channel layer 122 and the electrode structure 123 are arranged along the second direction X.
  • the structures of the first electrode 121 , the isolation dielectric layer 124 , the channel layer 122 , and the electrode structure 123 are relatively regular, and the extending direction of each layer is parallel to the third direction Y and the first direction Z.
  • the structures of the first electrode 121 , the isolation dielectric layer 124 , the channel layer 122 , and the electrode structure 123 may also be irregular, and will not be repeated here.
  • the transistor device shown in FIG. 6 is equivalent to one half of the structure in which the transistor device shown in FIG. 3 is divided in half along the first direction Z.
  • the transistor device shown in FIG. 7a is equivalent to the transistor device shown in FIG. 4a
  • the transistor device shown in Figure 7b is equivalent to one half of the structure after the transistor device shown in Figure 4b is divided in half perpendicular to the second direction X
  • the transistor device shown in Figure 7c The transistor device is equivalent to half of the structure of the transistor device shown in FIG. 4c after being divided into half by X perpendicular to the second direction
  • the transistor device shown in FIG. 7d is equivalent to the half structure of the transistor device shown in FIG. Half of the structures can be cross-referenced.
  • FIG. 8 shows a schematic cross-sectional structure diagram of another transistor device cut by plane A, wherein the functional structure 12 specifically includes a first electrode 121 , a channel layer 122 , an electrode structure 123 , and an isolation dielectric layer 124 .
  • the electrode structure 123 includes at least two electrode layers stacked sequentially along the first direction Z and an electrode dielectric layer 1233 located between any two electrode layers, specifically including the first electrode layer, the first dielectric layer stacked in sequence layer, the second electrode layer, the second dielectric layer and the third electrode layer, the first dielectric layer is used to isolate the first electrode layer and the second electrode layer, and prevent the first electrode layer and the second electrode layer from being short-circuited; the second dielectric layer The layer is used to isolate the second electrode layer and the third electrode layer to prevent the second electrode layer and the third electrode layer from being short-circuited; the stacking direction here is equivalent to the first direction Z, and the stacking direction can be directed from the substrate structure 11
  • the base M may also be a structure pointing from the base M
  • the electrodes of the first electrode layer and the third electrode layer have the same polarity (both source or drain), and the second electrode layer is opposite to the polarity of the first electrode layer and the third electrode layer (when the first electrode layer When the first electrode layer and the third electrode layer are source electrodes, the second electrode layer is a drain electrode; when the first electrode layer and the third electrode layer are drain electrodes, the second electrode layer is a source electrode).
  • the first electrode layer and the third electrode layer are set as two drain electrodes 1232
  • the second electrode layer is set as one source electrode 1231
  • both the first dielectric layer and the second dielectric layer are electrodes. Dielectric layer 1233 .
  • the channel layer 122 includes a doped semiconductor material, and the doped atoms can provide carriers, which can be used to conduct current.
  • the channel layer 122 is arranged on the outside of the electrode structure 123 to be in contact with any electrode layer .
  • the first electrode 121 is wrapped outside the channel layer 122 , and the isolation dielectric layer 124 is disposed between the first electrode 121 and the channel layer 122 .
  • the first electrode 121 can be used as the gate of the transistor device, and the first electrode 121 also has a base M parallel to the substrate structure 11 .
  • the electrode structure 123 is equivalent to comprising a first electrode layer (drain electrode 1232 ), a first dielectric layer (electrode dielectric layer 1233 ), a second electrode layer arranged along the first direction Z.
  • Layer (source electrode 1231), second dielectric layer (electrode dielectric layer 1233), third electrode layer (drain electrode 1232), any two adjacent electrode layers are equivalent to realizing electrical isolation through electrode dielectric layer 1233, preventing Short circuit between two adjacent electrode layers.
  • the first electrode layer and the third electrode layer (corresponding to the two drain electrodes 1232 ) are electrically connected through a connection structure (such as a wire, not shown here).
  • the channel layer 122 is in contact with any electrode layer, and two adjacent electrode layers (equivalent to a source electrode 1231 and a drain electrode 1232) can pass through the channel between the two electrode layers driven by the first electrode 121.
  • Layer 122 enables electron transport to form a channel current.
  • the distance between two adjacent electrode layers is equivalent to the channel length L of the channel between the two electrode layers .
  • the first electrode 121 corresponds to the channel layer 122 between any two electrode layers.
  • the first electrode layer and the third electrode layer in FIG. 8 can also be the source electrode 1231, and the second electrode layer corresponds to the drain electrode, which is not limited here; and FIG. 8 is equivalent to showing the embodiment of the present application
  • the example provides the simplest structure of the transistor device.
  • the number of electrode layers can be more, and it only needs to meet the requirement of passing through the electrode dielectric layer 1233 between any two electrode layers. It only needs to be electrically isolated, and the electrode layers of the same polarity are electrically connected.
  • any two sources 1231 are electrically connected to serve as the source of the transistor device; when the number of electrode layers used as the drain 1232 is greater than or equal to 2, any The two drains 1232 are electrically connected and can serve as the drain of the transistor device.
  • the source electrode 1231 and the drain electrode 1232 are hereinafter used to directly refer to a certain electrode layer. It should be understood that the transistor device can also adjust the structure of part of the electrode layer, electrode dielectric layer 1233, channel layer 122 and isolation dielectric layer 124 as required, as long as the corresponding relationship between the first electrode 121 and the electrode structure 123 is satisfied. .
  • Fig. 9a shows a schematic cross-sectional structure diagram of the transistor device in Fig. 8 cut by plane B, where plane B is perpendicular to the first direction Z and passes through one of the electrode layers.
  • the channel layer 122 surrounds the electrode structure 123 (shown here as an electrode layer), and the isolation dielectric layer 124 surrounds the channel layer 122.
  • An electrode 121 surrounds the isolation dielectric layer 124 .
  • the length of the line of intersection between the surface of the channel layer 122 in contact with the electrode layer and the surface perpendicular to the first direction Z is equivalent to the channel width W of the channel between any two adjacent electrode layers.
  • the transistor device When the transistor device has n electrode layers, n is greater than or equal to 2, and there is a channel between every two electrode layers, the transistor device will have n-1 channels, which is equivalent to the existence of n-1 channel widths W , the total effective channel width W of the entire transistor device is equivalent to (n-1) W; along the first direction Z, within the reasonable size range of the transistor device, increasing the number of electrode layers can increase the total effective channel width W, It is beneficial to increase the current magnitude of the transistor device.
  • the transistor device provided by the embodiment of the present application is viewed from the final structural form
  • the first electrode 121 and the channel layer 122 are equivalent to forming a pocket structure with a storage space
  • the storage space has an opening
  • the opening faces
  • the substrate structure 11 has an accommodating space for accommodating the electrode structure 123 .
  • the channel layer 122 is equivalent to the inner structural layer of the pocket structure
  • the first electrode 121 is equivalent to the outer structural layer of the pocket structure
  • the first electrode 121 is wrapped outside the channel layer 122 .
  • Fig. 9b shows another schematic cross-sectional structure diagram of the transistor device in Fig. 8 after being cut by the B surface, similar to the structure shown in Fig.
  • the channel layer 122 surrounds the electrode structure 123 (here shown as an electrode layer)
  • the isolation dielectric layer 124 surrounds the channel layer 122
  • the first electrode 121 surrounds the isolation dielectric layer 124 .
  • the cross section of the electrode structure 123 is rectangular, and the cross sections of the isolation dielectric layer 124 , the channel layer 122 and the first electrode 121 are all square rings.
  • the cross section of the electrode structure 123 may also be other polygons (such as the hexagon shown in FIG. 123 shapes corresponding to polygon rings.
  • the cross-section of the electrode structure 123 may also be other irregular shapes (such as the quasi-parabolic shape shown in FIG.
  • the shape corresponds to the irregularly shaped ring.
  • the cross section of the isolation dielectric layer 124, the channel layer 122, and the first electrode 121 do not correspond to the shape of the electrode structure 123 (for example, the cross section of the electrode structure 123 is circular.
  • the cross-sections of the isolation dielectric layer 124, the channel layer 122 and the first electrode 121 are square rings), which will not be repeated here.
  • the embodiments of the present application further provide a transistor device as shown in FIG. 10 .
  • the electrode structure 123 is similar to the electrode structure 123 in the transistor device shown in FIG. 8, including at least two electrode layers arranged along the first direction Z, and any two adjacent electrodes The electrical isolation between the layers is realized by the electrode dielectric layer 1233 to prevent short circuit between two adjacent electrode layers.
  • Other structures of the electrode structure 123 except the drain 1232 closest to the substrate structure 11 are columnar and extend along the first direction Z. Referring to FIG.
  • the channel layer 122 is arranged along the circumferential outer surface of the electrode structure 123 (that is, the outer surface of the electrode structure 123 parallel to the first direction Z), but the channel layer 122 does not wrap the circumferential outer surface of the electrode structure 123, the first electrode 121 is disposed along the circumferential outer surface of the channel layer 122 (ie, the outer surface of the channel layer 122 parallel to the first direction Z), but the first electrode 121 does not wrap the circumferential surface of the channel layer 122 .
  • the isolation dielectric layer 124 is disposed between the channel layer 122 and the first electrode 121 , and the isolation dielectric layer 124 can electrically isolate the first electrode 121 from the electrode structure 123 .
  • the first electrode 121 corresponds to the channel layer 122 between any two electrode layers.
  • the isolation dielectric layer 124 half surrounds the channel layer 122
  • the isolation dielectric layer 124 half surrounds the first electrode 121 .
  • the length of the line of intersection between the surface of the channel layer 122 in contact with the electrode layer and the surface perpendicular to the first direction Z is equivalent to the channel width W of the channel between any two adjacent electrode layers.
  • the isolation dielectric layer 124 half surrounds the channel layer 122
  • the isolation dielectric layer 124 half surrounds the first electrode 121 .
  • the cross section of the electrode structure 123 is rectangular, and the cross sections of the isolation dielectric layer 124 , the channel layer 122 and the first electrode 121 are all half-rings in a zigzag shape. It should be understood that the cross section of the electrode structure 123 may also be in other zigzag shapes (such as shown in FIG. half-ring of the line.
  • the cross-section of the electrode structure 123 may also be other irregular shapes (for example, the fan-like shape shown in FIG. Corresponding irregular shape ring. Certainly, the cross section of the isolation dielectric layer 124 , the channel layer 122 and the first electrode 121 may not correspond to the shape of the electrode structure 123 , which will not be repeated here.
  • the first electrode 121, the isolation dielectric layer 124, the channel layer 122 and the electrode structure 123 are arranged along the second direction.
  • the structures of the first electrode 121 , the isolation dielectric layer 124 , the channel layer 122 , and the electrode structure 123 are relatively regular, and the extending direction of each layer is parallel to the third direction Y and the first direction Z.
  • the structures of the first electrode 121 , the isolation dielectric layer 124 , the channel layer 122 , and the electrode structure 123 may also be irregular, and will not be repeated here.
  • the transistor device shown in FIG. 10 is equivalent to half of the structure of the transistor device shown in FIG.
  • Half of the structure of the transistor device shown in FIG. 9a is split in two directions X in half
  • the transistor device shown in FIG. 11b is equivalent to half of the structure of the transistor device shown in FIG. 9b perpendicular to the second direction X.
  • the transistor device shown is equivalent to one half of the transistor device shown in FIG. 9c after being divided in half perpendicular to the second direction X
  • the transistor device shown in FIG. 11d is equivalent to the half structure shown in FIG. 9b perpendicular to the second direction X.
  • Half of the structures behind the transistor device can be referred to each other.
  • Each structure 123 includes a plurality of electrode layers arranged along the first direction Z and electrically isolated from each other, and the other first electrodes 121 , channel layer 122 , isolation dielectric layer 124 and other parts are all for the purpose of realizing transistor functions.
  • the material of the electrode layer should be a conductive material, specifically a metal or other conductive compound, such as one of titanium, gold, tungsten, aluminum, copper, ruthenium, molybdenum, silver, platinum or bismuth or a combination of more, such as a combination of one or more of titanium nitride, tungsten nitride or indium tin oxide, any electrode layer can form an electrical contact with the channel layer 122 .
  • a conductive material specifically a metal or other conductive compound, such as one of titanium, gold, tungsten, aluminum, copper, ruthenium, molybdenum, silver, platinum or bismuth or a combination of more, such as a combination of one or more of titanium nitride, tungsten nitride or indium tin oxide, any electrode layer can form an electrical contact with the channel layer 122 .
  • the material of the first electrode 121 is also a conductive material, specifically metal or other conductive compounds, such as titanium, gold, tungsten, aluminum, copper, ruthenium, molybdenum, silver, platinum, titanium nitride, indium tin oxide or One or more combinations of indium zinc oxide; the material of the isolation dielectric layer 124 can be selected from silicon oxide, silicon nitride, aluminum oxide, hafnium oxide, zirconium dioxide, titanium dioxide, or yttrium oxide.
  • the combination can be material doping combination (as shown in Figure 12a, the second material is doped into the first material as the matrix), stacked layer combination (as shown in Figure 12b, the first One material and the second material are alternately stacked) or a combination of doping and stacking (as shown in Figure 12c, both the second material is doped into the first material as the matrix, and the first material and the second material are alternately stacked layer).
  • the material of the channel layer 122 can be one or more combinations of metal oxide, multi-component compound, graphene, molybdenum disulfide, and black phosphorus, such as silicon-based semiconductors such as silicon, polysilicon, and amorphous silicon, indium oxide, Zinc oxide, gallium oxide, indium tin oxide, titanium dioxide and other metal oxides.
  • the electrode dielectric layer 1233 and the isolation dielectric layer 124 may be made of the same material.
  • the distance between any two adjacent electrode layers can be set to be the same, and during the preparation of the electrode structure 123 of the transistor device, the same process can be used to prepare multilayer electrodes layer, which is beneficial to simplify the device fabrication process, and this structure is also conducive to the calculation of the parameters of the transistor device, that is, n electrode layers, equivalent to the transistor device can have n-1 channel widths, and the channel current is equivalent to doubling.
  • the transistor device shown in FIG. 3 has one source 1231 and two drains 1232 , and the distance between any two electrode layers is set to be the same, so that the transistor device can form a channel width twice.
  • the electrical characterization diagrams shown in Figure 13a and Figure 13b can be obtained by simulating the transistor device in the prior art and the transistor device provided in the embodiment of the present application, wherein the abscissas of the icons in Figure 13a and Figure 13b are The voltage of the first electrode, the unit is volt (V), and the ordinate is the channel current, the unit is ampere (A).
  • the channel current is positively correlated with the voltage of the first electrode, but with the increase of the voltage of the first electrode, the increase rate of the channel current is relatively slow, when the first electrode When the voltage reaches 2V, the channel current reaches around 0.000024A; while in the transistor device provided by the embodiment of the present application shown in Figure 13b, when the first electrode voltage gradually increases, the channel current increases significantly, and when the first electrode voltage reaches At 2V, the channel current can reach around 0.00005A, which is equivalent to twice the channel current in the prior art.
  • the transistor device provided by the present application can realize multiplication of working current under the condition that the original mobility, channel length, gate oxide thickness and other factors remain unchanged, and has the advantages of low cost, simple process, and the existing
  • the technical process has similar advantages, and the area in the horizontal direction (vertical to the height direction of the transistor device, ie, the first direction Z) is not increased, and the integration density is maintained.
  • the transistor device provided by the embodiment of the present application can obtain multiple equivalent channels by increasing the electrode layer (that is, alternately increasing the source/drain) without increasing the unit area of the device, thereby improving the overall
  • the effective channel width of the transistor device increases the output current of the device.
  • Applying the transistor device as a read transistor to a gain cell memory can improve read efficiency.
  • the transistor device can also be applied to logic, analog, radio frequency circuits and other scenarios that need to provide different transistor width options.
  • the embodiment of the present application also provides an electronic device as shown in Figure 14, the electronic device is an example of a memory, including a signal write transistor 1, a read transistor 2, a storage unit 3, a first write signal line 41, a second write signal line 42.
  • the read transistor 2 may be any transistor device provided in the above-mentioned embodiments.
  • the first write signal line 41 is connected to the first electrode of the signal write transistor 1
  • the second write signal line 42 is connected to the source of the write transistor 1
  • the first read signal line 51 is connected to the source of the read transistor 2 (or drain)
  • the second read signal line 52 is connected to the drain (or source) of the read transistor 2
  • the drain of the write transistor 1 is connected to the first electrode structure of the read transistor 2
  • the memory unit 3 is connected to the write transistor 1 and read transistor 2.
  • the write transistor 1 is controlled to be turned on through the first write signal line 41, and the potential of the second write signal line 42 is transmitted to the first electrode of the read transistor 2, so that the first electrode of the read transistor 2
  • the electrode potential is synchronized with the second write signal line 42 to realize the writing of "0" and "1”; then, the first write signal line 41 controls the write transistor 1 to close, and the first electrode potential of the read transistor 2 is stored in the memory cell 3 is determined by the power.
  • the work of "reading” it is only necessary to read the current change of the read transistor 2 or the voltage change of the second read signal line 52 to determine the storage state. Since the read transistor 2 has a larger current, the memory has a higher read rate when reading signals.
  • FIG. 3 and FIG. 8 there may be at least two structures of the transistor device, and for transistor devices with different structures, there may be different implementations of the fabrication methods thereof.
  • An embodiment of the present application provides a method for manufacturing a transistor device, which is used to prepare the transistor device shown in FIG. 3 .
  • the preparation method comprises:
  • Step S11 Alternately arrange electrode layers and electrode dielectric layers 1233 on the substrate structure 11 along the first direction Z to form the electrode structure 123, and obtain the structure shown in Figure 16; the number of electrode layers is at least two, the At least two electrode layers include at least one source electrode 1231 and at least one drain electrode 1232 arranged alternately, when there are at least two source electrodes 1231, any two source electrodes 1231 are electrically connected, when there are at least two drain electrodes 1232 , any two drains 1232 are electrically connected.
  • the electrode structure 123 is specifically realized by laying one electrode layer and one electrode dielectric layer 1233 sequentially.
  • the order in which the source electrode 1231 and the drain electrode 1232 are prepared is not limited, but they must be prepared alternately, and finally a channel is formed between adjacent source electrodes 1231 and drain electrodes 1232 .
  • any two source electrodes 1231 are electrically connected to form the source of the entire transistor device;
  • any two drain electrodes 1232 are electrically connected connected to form the drain of the entire transistor device.
  • any two sources 1231 can be realized through external wiring (equivalent to a connection structure), which is not shown here; similarly, the electrical connection between any two drains 1232 can be achieved through The external wiring (equivalent to the connection structure) is realized, which is not shown here.
  • Step S12 Etching the electrode structure 123 to form a first groove K1 extending along the first direction Z, and the first groove K1 communicates with each electrode layer to obtain a structure as shown in FIG. 17a;
  • Step S13 forming a channel layer 122 in the first groove K1 , and the channel layer 122 forms a second groove K2 to obtain a structure as shown in FIG. 17 b .
  • the structure formed by the electrode structure 123 and the channel layer 122 is equivalent to a pocket structure
  • the second groove K2 is equivalent to a receiving space of the pocket structure.
  • the channel layer 122 when the channel layer 122 is filled in the first groove K1, the channel layer 122 can be etched along the first direction Z to form the second groove K2; when the channel layer 122 is attached in the first groove K1 On the surface, the side of the channel layer 122 away from the inner surface of the first groove K1 may naturally form the second groove K2.
  • Step S14 Form the first electrode 121 in the second groove K2; specifically, the isolation dielectric layer 124 can be formed in the second groove K2 first, and the isolation dielectric layer 124 can be formed with the third groove K3, and the result shown in FIG. 17c is obtained.
  • structure shown when the isolation dielectric layer 124 is filled in the second groove K2, the isolation dielectric layer 124 can be etched along the first direction Z to form the third groove K3; when the isolation dielectric layer 124 is attached to the second groove K2 On the inner surface, the side of the isolation dielectric layer 124 away from the inner surface of the first groove K2 may naturally form the third groove K3.
  • the first electrode 121 is formed after the first electrode material is filled in the third groove K3 to obtain the structure shown in FIG. 3 .
  • the first electrode 121 also has a base M.
  • this method can also be used when fabricating the transistor device structures shown in FIG. 5c and FIG. 6 .
  • An embodiment of the present application provides a method for manufacturing a transistor device, which is used to prepare the transistor device shown in FIG. 8 .
  • the preparation method comprises:
  • the preparation method after the above step S1 specifically includes:
  • Step S21 Along the first direction Z, alternately arrange electrode layers and electrode dielectric layers 1233 on the substrate structure 11 to form the electrode structure 123, and obtain the structure shown in Figure 16; the number of electrode layers is at least two, the At least two electrode layers include at least one source electrode 1231 and at least one drain electrode 1232 arranged alternately, when there are at least two source electrodes 1231, any two source electrodes 1231 are electrically connected, when there are at least two drain electrodes 1232 , any two drains 1232 are electrically connected.
  • This step S21 is similar to the above step S11 and will not be repeated here.
  • Step S22 Form the channel layer 122 outside the electrode structure 123; specifically, the structure shown in FIG. 16 can be etched to form the structure shown in FIG.
  • the other structures outside are columnar, and then channel material is deposited on the outside of the electrode structure 123 to form a channel layer 122, and the structure shown in FIG. 19b is obtained, and the channel layer 122 is also columnar.
  • Step S23 Forming the first electrode 121 outside the channel layer 122; before forming the first electrode 121, first forming an isolation dielectric layer 124 outside the channel layer 122 to obtain the structure shown in FIG. 19c; The electrode material is deposited outside 124 to form the first electrode 121, and the structure shown in FIG. 8 is obtained.
  • this method can also be used when fabricating the transistor device structure shown in FIG. 10 .
  • the structures of part of the electrode layers, the electrode dielectric layer 1233 , the channel layer 122 and the isolation dielectric layer 124 can be adjusted as required, as long as the corresponding relationship between the first electrode 121 and the electrode structure 123 is satisfied.

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Abstract

本申请提供了一种晶体管装置及其制备方法、电子器件。该晶体管装置包括衬底结构以及设置于衬底结构上的沟道层、第一电极和电极结构；第一电极与电极结构隔离；电极结构包括沿第一方向排布的至少两个电极层，任意两个相邻的电极层之间电隔离，第一方向垂直于衬底结构；沿第一方向，至少两个电极层包括交替排布的至少一个源极和至少一个漏极；当源极和漏极均为至少两个，任意两个源极之间电连接，任意两个漏极之间电连接；沟道层位于第一电极与电极结构之间，且沟道层与任意一个电极层接触。该晶体管装置在不增加器件单元面积的基础上，通过增加电极层可以获得多个等效沟道，提高整个晶体管装置的有效沟道宽度以提高器件的输出电流。

Description

晶体管装置及其制备方法、电子器件 技术领域
本申请涉及半导体技术领域，尤其涉及到一种晶体管装置及其制备方法、电子器件。
背景技术
随着互联网技术和云计算技术的发展，信息时代正向大数据时代飞速转变，使得存储系统的需求不断提升，日益增长的信息量使存储芯片在整个集成电路产业市场中占据非常重要的地位。然而，根据摩尔定律，处理器和存储器之间的鸿沟越来越大，微处理器性能的增长速度远远超过了存储器性能的增长速度，最终导致存储器的存储密度及读写速度跟不上处理器的运算速度，最终影响系统的整体性能。
增益单元(gain-cell)存储器读取速度可低至纳秒级，其采用两个晶体管装置结构，可以减小器件单元的占用面积，可以实现高速读写以及高密度集成。但是由于其存储单元内部存在漏电现象，导致在实际应用中需要每隔一段时间进行刷新来保持数据的完整性，因此带来了较大的动态功耗。利用超低漏电的薄膜晶体管(thin film transistor，TFT)作为增益单元存储器中的晶体管，可以降低动态功耗，提高存储市场。但是，目前增益单元存储器中的读晶体管的工作电流比较小，导致读晶体管的工作频率受限。
发明内容
本申请提供了一种晶体管装置及其制备方法、电子器件，该晶体管装置可以调节沟道宽度以增大沟道电流，用作读晶体管读取数据时，可以提高读取速度。
第一方面，本申请提供了一种晶体管装置，该晶体管装置可以应用到诸如存储器之类的器件中，满足这类器件对沟道宽度的要求。该晶体管装置具体包括衬底结构，衬底结构上设置有电极结构，该电极结构包括在第一方向上交替排布的至少两个电极层，至少两个电极层中任意两个相邻的电极层之间电隔离，防止电极短接；该至少两个电极层包括至少一个源极和至少一个漏极，当源极的数量为至少两个，任意两个源极之间电连接以形成整个晶体管装置的源极，当漏极的数量为至少两个，任意两漏极之间电连接以形成整个晶体管装置的漏极，使得在晶体管装置与外部器件连接时，对外一个源极接口和一个漏极接口。上述第一方向垂直于衬底结构。衬底结构上还设置有第一电极。衬底结构上还设置有沟道层，沟道层位于第一电极与电极结构之间，沟道层与任意一个电极层接触，而第一电极沿第二方向与沟道层至少部分对应，此处的第二方向垂直于第一方向。任意一个相邻的源极和漏极之间可以形成一个沟道，第一电极可以调控任意两个电极层之间的沟道中载流子的浓度；当第一电极导通，第一电极可以驱动任意相邻的一个源极和一个漏极之间的沟道层内电子移动，形成沟道电流。源极和漏极沿第一方向的间距相当于沟道的长度，源极(或漏极)与沟道层接触的面垂直于第一方向的长度相当于沟道的宽度。对于整个晶体管装置，当电极层的数量为n个，可以形成n-1个沟道，在晶体管装置合理的高度范围内，增加电极层(即交替增加源极/漏极)可以增加沟道的数量，进而增加晶体管装置的有效沟道宽度，在晶体管装置原子迁移率、沟道长度、栅氧厚度等因素不变的基础上，可以增加沟道电流的大小。
其中，该晶体管装置还包括隔离介质层，隔离介质层一般设置于第一电极的表面，且隔离介质层位于第一电极与电极结构之间，以使第一电极与电极结构电隔离、第一电极与沟道层之间电隔离；在一些实施例中，隔离介质层设置于第一电极与沟道层之间。第一电极为栅极时，隔离介质层相当于栅介质层。
晶体管装置可能有不同的结构形式，在其中一种结构中，沿第二方向，沟道层可以设置于第一电极的外侧，电极结构可以设置在沟道层的外侧；相当于电极结构中设置有第一凹槽，第一凹槽沿第一方向延伸，第一凹槽连通上述至少两个电极层；第一电极设置在第一凹槽内，且在第一凹槽的底面与侧面依次层叠设置有沟道层和隔离介质层，其中隔离介质层与第一电极接触，沟道层与任意一个电极层接触。在这种结构中，可以设置沟道层在衬底结构上的投影覆盖第一电极朝向衬底结构的端部在衬底结构上的投影。
在另一种结构的晶体管装置中，沿第二方向，电极结构形成柱状，沟道层可以设置在电极结构的外侧，第一电极设置在沟道层的外侧。在这种结构中，可以设置沟道层在衬底结构上的投影覆盖电极结构远离衬底结构的端部在衬底结构上的投影。
在一些实施例中，为了避免源极(漏极)在与沟道层接触区域发生扩散，降低接触的费米钉扎效应，可以在每个电极层与沟道层的接触界面设置绝缘层，可以在电极层与沟道层接触的界面处形成金属-绝缘层-半导体结构。其中，绝缘层的厚度范围可以选择0.1-2纳米(nanometer，nm)。
该晶体管装置中，任意两个相邻的电极层之间电隔离包括：任意两个相邻的电极层之间设置电极介质层，以将两个电极层电学隔离。为了便于工艺制备以及电性能计算，可以将任意两个相邻的电极层之间的距离设置为相同。
该晶体管装置中各结构的材质选择如下：电极层的材质为钛(titanium，Ti)、金(aurum，Au)、钨(tungsten，W)、铝(aluminium，Al)、铜(cuprum，Cu)、钌(ruthenium，Ru)、钼(molybdenum，Mo)、银(argentum，Ag)、铂(platinum，Pt)、铋(bismuth，Bi)、氮化钛(titanium nitride，TiN)、氮化钨(tungsten nitride，WN)、氧化铟锡(indium tin oxide，ITO)或氧化铟锌(indium tin oxide，IZO)中的一种或多种的组合；第一电极的材质为钛、金、钨、铝、铜、钌、钼、银、铂、氮化钛、氧化铟锡或氧化铟锌中的一种或多种的组合；隔离介质层的材质为硅氧化物(silicon oxide，SiO x)、硅氮化物(silicon nitride，SiN x)、三氧化二铝(aluminium oxide，Al 2O 3)、二氧化铪(hafnium oxide，HfO 2)、二氧化锆(zirconium dioxide，ZrO 2)、二氧化钛(titanium dioxide，TiO 2)或三氧化二钇(yttrium oxide，Y 2O 3)中的一种或多种的组合，其组合方式可以是材料掺杂组合、叠层组合或掺杂与叠层的组合；沟道层的材质可以为金属氧化物、多元化合物、石墨烯、二硫化钼(molybdenum sulfide，MoS 2)、黑磷中的一种或多种的组合，例如硅(silicon，Si)、多晶硅(polycrystalline silicon，poly-Si)或非晶硅(amorphous-Si)等硅基半导体，氧化铟(indium oxide，In 2O 3)、氧化锌(zinc oxide，ZnO)、氧化镓(gallium oxide，Ga 2O 3)、氧化铟锡(indium tin oxide，ITO)或二氧化钛等金属氧化物。
第二方面，本申请还提供一种晶体管装置，具体包括第一电极、口袋结构和连接结构；其中的口袋结构包括内结构层和外结构层，内结构层和外结构层内外嵌套；内结构层包括经过掺杂的半导体材料，内结构层围成口袋，用于收容上述第一电极；外结构层包裹于内结构层外；外结构层相当于电极结构，包括依次堆叠的第一电极层、第一介质层、第二电极层、第二介质层和第三电极层，第一介质层用于隔离第一电极层和第二电极层，防止第 一电极层和第二电极层短接；第二介质层用于隔离第二电极层和第三电极层，防止第二电极层和第三电极层短接；第一电极层、第一介质层、第二电极层、第二介质层和第三电极层均为环状，缠绕在内结构外；其中，第一电极层和第三电极层通过连接结构电连接，连接结构可以具体为导线。该结构中，第一电极可以用作晶体管装置的栅极，内结构层可以用作晶体管装置的沟道层，外结构层中的第一电极层、第二电极层和第三电极层可以用作晶体管装置的源漏极；其中，第一电极层和第三电极层极性一致(同为源极或同为漏极)，第二电极层则与第一电极层、第三电极层极性相反(当第一电极层和第三电极层为源极时，第二电极层为漏极；当第一电极层和第三电极层为漏极时，第二电极层为源极)。
具体地，该晶体管装置还包括设置于第一电极外侧的隔离介质层，隔离介质层位于第一电极与内结构层之间。此处的隔离介质层可以用作晶体管装置的栅介质层，防止栅极(即第一电极)与其他电极短接。上述第一介质层和第二介质层均为电极介质层，第一介质层和第二介质层的材质可以相同。
第三方面，本申请还提供一种晶体管装置，具体包括电极结构、口袋结构和连接结构；电极结构包括依次堆叠的第一电极层、第一介质层、第二电极层、第二介质层和第三电极层，第一介质层用于隔离第一电极层和第二电极层，防止第一电极层和第二电极层短接；第二介质层用于隔离第二电极层和第三电极层，防止第二电极层和第三电极层短接；其中的口袋结构包括内结构层和外结构层，内结构层和外结构层内外嵌套；内结构层包括经过掺杂的半导体材料，内结构层围成口袋，用于收容上述电极结构；外结构层包裹于内结构层外；其中，第一电极层和第三电极层通过连接结构电连接，连接结构可以具体为导线。该结构中，第一电极可以用作晶体管装置的栅极，内结构层可以用作晶体管装置的沟道层，电极结构中的第一电极层、第二电极层和第三电极层可以用作晶体管装置的源漏极；其中，第一电极层和第三电极层极性一致(同为源极或同为漏极)，第二电极层则与第一电极层、第三电极层极性相反(当第一电极层和第三电极层为源极时，第二电极层为漏极；当第一电极层和第三电极层为漏极时，第二电极层为源极)。
具体地，该晶体管装置还包括设置于第一电极朝向电极结构表面(相当于外结构层的内壁)的隔离介质层，隔离介质层位于第一电极与内结构层之间。此处的隔离介质层可以用作晶体管装置的隔离介质层，防止栅极(即第一电极)与其他电极短接。上述第一介质层和第二介质层均为电极介质层，第一介质层和第二介质层的材质可以相同。第四方面，本申请还提供一种电子器件，以存储器为例，该电子器件包括写晶体管、读晶体管、存储单元、第一写信号线、第二写信号线、第一读信号线和第二读信号线，其中的读晶体管为上述任一种晶体管装置；第一写信号线与写晶体管的第一电极连接，第二写信号线与写晶体管的源极连接；第一读信号线与读晶体管的源极连接，第二读信号线与读晶体管的漏极连接；写晶体管的漏极与读晶体管的第一电极结构连接，且存储单元连接于写晶体管与所述读晶体管之间。由于用作读晶体管的晶体管装置可以增大沟道电流，在读取数据时可以降低读取延时。
第五方面，本申请还提供一种晶体管装置的制备方法，可以用来制备其中一部分上述晶体管装置，该制备方法具体包括：
沿第一方向，在衬底结构上依次交替设置电极层和电极介质层以形成电极结构；电极层为至少两个，该至少两个电极层包括交替排布的至少一个源极和至少一个漏极，当源极为至少两个，任意两个源极之间电连接，当漏极为至少两个，任意两个漏极之间电连接；
刻蚀电极结构以形成沿第一方向延伸的第一凹槽，第一凹槽连通各电极层；
在第一凹槽内形成沟道层，沟道层形成第二凹槽；
在第二凹槽内形成第一电极。
当该晶体管装置还包括隔离介质层，隔离介质层设置于第一电极的表面，且隔离介质层位于第一电极与沟道层之间；上述在第二凹槽内形成第一电极包括：
在第二凹槽内形成隔离介质层，隔离介质层形成第三凹槽；
在第三凹槽内形成所述第一电极。
本申请还提供一种晶体管装置的制备方法，可以用来制备其中另一部分上述晶体管装置，该制备方法具体包括：
沿第一方向，在衬底结构上依次交替设置电极层和电极介质层以形成电极结构；电极层为至少两个，该至少两个电极层包括交替排布的至少一个源极和至少一个漏极，当源极为至少两个，任意两个源极之间电连接，当漏极为至少两个，任意两个漏极之间电连接；
在电极结构外侧形成沟道层；
在沟道层的外侧形成第一电极。
当该晶体管装置还包括隔离介质层，隔离介质层设置于第一电极的表面，且隔离介质层位于第一电极与沟道层之间；上述在沟道层的外侧形成第一电极包括：
在所述沟道层外侧形成所述隔离介质层；
在所述隔离介质层的外侧形成所述第一电极。
附图说明
图1a和图1b为现有技术中的增益单元存储器的电路原理示意图；
图2为本申请实施例提供的一种晶体管装置的结构示意图；
图3为本申请实施例提供的一种晶体管装置沿A面剖切的剖面结构示意图；
图4a至图4d为图3所示晶体管装置沿B面剖切的剖面结构示意图；
图5a至图5d为本申请实施例提供的一种晶体管装置沿A面剖切的剖面结构示意图；
图6为本申请实施例提供的一种晶体管装置沿A面剖切的剖面结构示意图；
图7a至图7e为图6所示晶体管装置沿B面剖切的剖面结构示意图；
图8为本申请实施例提供的另一种晶体管装置沿A面剖切的剖面结构示意图；
图9a至图9d为图8所示晶体管装置沿B面剖切的剖面结构示意图；
图10为本申请实施例提供的一种晶体管装置沿A面剖切的剖面结构示意图；
图11a至图11e为图10所示晶体管装置沿B面剖切的剖面结构示意图；
图12a至图12c为本申请实施例提供的一种晶体管装置中的隔离介质层的结构示意图；
图13a为现有技术中晶体管装置的第一电极电压与沟道电流的电学表征图；
图13b为本申请实施例提供的一种晶体管装置的第一电极电压与沟道电流的电学表征图；
图14为本申请实施例提供的一种电子器件电路原理示意图；
图15为本申请实施例提供的一种晶体管装置的制备方法示意图；
图16为本申请实施例提供的一种晶体管装置制备过程中形成的电极结构示意图；
图17a至图17c为图3所示的晶体管装置在制备过程中的结构变化示意图；
图18为本申请实施例提供的另一种晶体管装置的制备方法示意图；
图19a至图19c为图8所示的晶体管装置在制备过程中的结构变化示意图。
图标：1-写晶体管；2-读晶体管；3-存储单元；41-第一写信号线；42-第二写信号线；51-第一读信号线；52-第二读信号线；11-衬底结构；12-功能结构；121-第一电极；122-沟道层；123-电极结构；1231-源极；1232-漏极；1233-介质层；124-隔离介质层；125-绝缘层。
具体实施方式
在应用薄膜晶体管的电子器件中，垂直结构的薄膜晶体管能够实现高速读写和高密度集成。以增益单元存储器为例，其可以采用两个垂直结构的薄膜晶体管，由于薄膜晶体管的导电沟道选择具有极低漏电特性的非晶金属氧化物(例如铟镓锌氧化物，indium gallium zinc oxid，IGZO)或者是其他宽禁带半导体材料，可以降低动态功耗，满足存储要求。同时，利用薄膜晶体管的工艺温度低、与传统的微电子工艺相兼容等优点可将存储单元应用于后道(back end of line，BEOL)工艺中，实现异质集成以及堆叠集成，可以提高存储密度。并且，选择垂直结构的薄膜晶体管可以提高面积利用率，有利于实现高集成密度的存储阵列，使每个存储单元的占用面积接近4F 2(F指一个字节距离的一半)，该参数仅为静态随机存取存储器(static random-access memory，SRAM)的三分之一。
图1a和图1b示出了两种增益单元存储器的电路原理。图1a中，增益单元存储器包括写晶体管(write transistor，WTR)、读晶体管(read transistor，RTR)以及连接于写晶体管与读晶体管之间的存储节点(storage nodes，SN)；在“写”的操作中，通过写字节线(write word line，WWL)控制写晶体管的开启，将写比特线(write bit line，WBL)的电位传递到读晶体管的栅极，使得读晶体管的栅极电位与写比特线同步以实现“0”和“1”的写入；然后，写字节线控制写晶体管关闭，读晶体管的栅极电位由存储在该节点的电量决定，由于薄膜晶体管的漏电比硅晶体管低很多，读晶体管栅极上的电流通过写晶体管发生泄露的情况得到改善，可以提高存储器的存储时长。在“读”的操作中，只需要读取读晶体管的电流变化或读比特线(read bit line，RBL)的电压变化即可判断存储状态。图1b中，包括预充晶体管(precharge transistor，PTR)、信号读出晶体管(sense transistor，STR)以及连接于预充晶体管和读晶体管之间的至少一个铁电材料的电容(capacitor，Cap)；在“写”的操作中，通过控制线(control line，CL)控制预充晶体管的开启，当写比特线写入“1”时，利用电容铁电材料的极化效应使得其内部电荷发生翻转，使得信号读出晶体管的栅极电势发生改变；在“读”的操作中，只需要读取信号读出晶体管的电流变化或读比特线电压变化即可判断存储状态。其中，读晶体管或信号读出晶体管均为薄膜晶体管，由于薄膜晶体管导电沟道材料具有较低的迁移率，其工作电流比较小，导致读晶体管或信号读出晶体管的工作频率受限。
为此，本申请实施例提供一种晶体管装置及其制备方法、电子器件，该晶体管装置是一种薄膜晶体管，可以通过增加晶体管装置的有效沟道宽度提高其工作电流，当该晶体管装置用于读取数据时，可以降低读取延时。
为了使本申请的目的、技术方案和优点更加清楚，下面将结合附图对本申请作进一步地详细描述。
以下实施例中所使用的术语只是为了描述特定实施例的目的，而并非旨在作为对本申请的限制。如在本申请的说明书和所附权利要求书中所使用的那样，单数表达形式“一个”、 “一种”、“所述”、“上述”、“该”和“这一”旨在也包括例如“一个或多个”这种表达形式，除非其上下文中明确地有相反指示。
在本说明书中描述的参考“一个实施例”或“一些实施例”等意味着在本申请的一个或多个实施例中包括结合该实施例描述的特定特征、结构或特点。由此，在本说明书中的不同之处出现的语句“在一个实施例中”、“在一些实施例中”、“在其他一些实施例中”、“在另外一些实施例中”等不是必然都参考相同的实施例，而是意味着“一个或多个但不是所有的实施例”，除非是以其他方式另外特别强调。术语“包括”、“包含”、“具有”及它们的变形都意味着“包括但不限于”，除非是以其他方式另外特别强调。
请参照图2，本申请实施例提供一种晶体管装置，该晶体管装置可以作为读晶体管应用到存储器电路中，还可以应用到逻辑、模拟、射频电路等需要提供不同晶体管宽度选择的场景中。该晶体管装置包括衬底结构11以及设置于衬底结构11之上的功能结构12(包括但不限于源极、漏极、栅极等结构，用于实现晶体管功能)，应当理解，此处的“衬底结构11之上”仅说明相对位置关系，并不限定功能结构12与衬底结构11的连接关系。即以整个晶体管装置的结构为参考，衬底结构11相当于位于晶体管的底部，在应用时衬底结构11可以对应设置于用于承载晶体管装置的承载面上，功能结构12均位于衬底结构11远离承载面的一侧。
衬底结构11可以为晶体管装置单独使用时的基底，起到承载支撑作用。当该晶体管装置为半导体器件的一部分，可以将该晶体管装置除衬底结构11之外的功能结构12直接堆叠到半导体器件的衬底上实现晶体管的功能，半导体器件的衬底可以充当该晶体管装置衬底结构11。此时，衬底结构11指的是半导体器件的前道工艺制备的结构，而该晶体管装置除衬底结构11之外功能结构12的制备可以在半导体器件制备的后道工艺中实现。
衬底结构11具体可以包括元素半导体、化合物半导体、合金半导体或其他材料中的一种或多种的组合，其中，元素半导体可以包括单晶硅、多晶硅、单晶锗(germanium，Ge)、多晶锗(polycrystalline germanium，poly-Ge)、非晶结构等，化合物半导体可以包括碳化硅(silicon carbide，SiC)、砷化镓(gallium arsenide，GaAs)、磷化镓(gallium phosphide，GaP)、磷化铟(indium phosphide，InP)、砷化铟(indium arsenide，InAs)、锑化铟(indium antimonide，InSb)等，合金半导体可以包括硅锗(silicon-germanium，SiGe)、砷化铝铟(aluminium indium arsenide，AlInAs)、砷化铝镓(aluminium gallium arsenide，AlGaAs)、砷化铟镓(indium gallium arsenide，InGaAs)、镓铟磷(gallium indium phosphide，GaInP)、磷砷化镓铟(gallium indium phosphide arsenide，GaInPAs)等。
在图2中，设定相互垂直的第一方向Z、第二方向X以及第三方向Y，晶体管装置的衬底结构11与功能结构12的堆叠方向即为第一方向Z，第一方向Z垂直于衬底结构11。晶体管装置的结构可能有多种实现方式，以垂直于第三方向Y的A面、垂直于第一方向Z的B面剖切该晶体管装置，可以得到该晶体管装置具体的结构，接下来将通过具体的图示对晶体管装置进行介绍。
图3示出了一种晶体管装置被A面剖切后的剖面结构示意图，其中功能结构12具体包括第一电极121、沟道层122、电极结构123、隔离介质层124。第一电极121可以作为该晶体管装置的栅极，第一电极121呈柱状且沿第一方向Z延伸，具体地，第一电极121可以是圆柱、棱柱或其他不规则的柱状，其长度方向平行于第一方向Z。隔离介质层124相当于栅介质层。在第一电极121远离衬底结构11的一端还可以形成与衬底结构11平行 的基座M，基座M可以平行于衬底结构11。沟道层122包括经过掺杂的半导体材料，掺杂的原子能够提供载流子，这些载流子可以用作传导电流。电极结构123具体包括沿第一方向Z依次堆叠的至少两个电极层以及位于任意两个电极层之间的电极介质层，具体包括依次堆叠的第一电极层、第一介质层、第二电极层、第二介质层以及第三电极层，第一介质层用于隔离第一电极层和第二电极层，防止第一电极层和第二电极层短接；第二介质层用于隔离第二电极层和第三电极层，防止第二电极层和第三电极层短接；此处的堆叠方向相当于第一方向Z，且堆叠方向可以为自衬底结构11指向基座M，也可以为自基座M指向衬底结构。其中，第一电极层和第三电极层的电极极性一致(同为源极或漏极)，第二电极层则与第一电极层、第三电极层极性相反(当第一电极层和第三电极层为源极时，第二电极层为漏极；当第一电极层和第三电极层为漏极时，第二电极层为源极)。根据图3所示，将第一电极层和第三电极层设定为两个漏极1232，将第二电极层设定为一个源极1231，第一介质层和第二介质层均为电极介质层1233。
请继续参照图3，设定第一电极121为柱状且沿第一方向Z延伸，沟道层122沿第一电极121的周向外表面(即第一电极121平行于第一方向Z的外表面)设置；电极结构123沿沟道层122的周向外表面(即沟道层122平行于第一方阵Z的外表面)设置；具体地，沟道层122设置于第一电极121的周向外表面以及第一电极121沿第一方向Z延伸的端面，沟道层122还覆盖基座M朝向衬底结构11的表面。隔离介质层124设置于沟道层122与第一电极121、基座M之间。电极结构123设置于沟道层122的外侧。在第一电极121的表面设置有隔离介质层124，隔离介质层124位于第一电极121与沟道层122之间(也可以看作隔离介质层124位于第一电极121与电极结构123之间)，可以将第一电极121与电极结构123电隔离。电极结构123相当于包括沿第一方向Z排布的第一电极层(漏极1232)、第一介质层(电极介质层1233)、第二电极层(源极1231)、第二介质层(电极介质层1233)、第三电极层(漏极1232)，任意两个相邻的电极层之间相当于通过电极介质层1233实现电隔离，防止两个相邻的电极层之间短接。其中，第一电极层和第三电极层(相当于两个漏极1232)之间通过连接结构(例如导线，此处未示出)电连接。其中，最靠近基座M的电极层与沟道层122之间也设置有电极介质层1233。在该晶体管装置中，沟道层122与任意一个电极层接触，两个相邻的电极层(相当于一个源极1231和一个漏极1232)在第一电极121驱动下可以通过该两个电极层之间的沟道层122实现电子传输以形成沟道电流，电子在沟道层122中流动，沟道层122的结构参数会对源漏极之间的电流大小产生影响。此处，沿第一方向Z，两个相邻的电极层(相当于一个源极1231和一个漏极1232)之间的距离，相当于该两个电极层之间沟道层122的沟道长度L。为了实现第一电极121对沟道层122的驱动，沿垂直于第一方向Z的第二方向X，第一电极121与任意两个电极层之间的沟道层122对应。
应当理解，图3中的第一电极层和第三电极层还可以为源极1231，第二电极层则对应为漏极1232，此处并不限定；且图3相当于示出了本申请实施例所提供的晶体管装置最简单的一种结构，在具体应用时，根据晶体管装置结构允许，电极层的数量还可以为更多个，只需要满足任意两个电极层之间通过介质层1233电隔离即可，且同极性的电极层电连接。当用作源极1231的电极层的数量大于等于2，任意两个源极1231之间电连接，可以充当晶体管装置的源极；当用作漏极1232的电极层的数量大于等于2，任意两个漏极1232之间电连接，可以充当晶体管装置的漏极。电极介质层为了方便描述，在下文中用源极1231 和漏极1232直接指代某一电极层，并用介质层1233直接指代某一电极介质层。图4a示出了图2中晶体管装置被B面剖切后的剖面结构示意图，B面垂直于第一方向Z且穿过其中一个电极层。如图4a所示，在第一电极121与沟道层122对应的范围内，隔离介质层124环绕第一电极121，沟道层122环绕隔离介质层124，电极结构123(此处示出为电极层)环绕沟道层122，第一电极121的截面可呈圆形，沟道层122的截面、电极结构123的截面、隔离介质层124的截面均呈同心圆环形。其中，沟道层122与电极层接触的面与垂直于第一方向Z的面的交线长度相当于两个相邻的电极层之间沟道的沟道宽度W。当晶体管装置具有n个电极层，n大于等于2，每两个电极层之间存在一个沟道，该晶体管装置将会存在n-1个沟道，相当于存在n-1个沟道宽度W，整个晶体管装置的有效沟道宽度W 总≈(n-1)W；沿第一方向Z，在晶体管装置合理的尺寸范围内，增加电极层的数量，可以增加有效沟道宽度W 总，有利于提高该晶体管装置的电流大小。
结合图3和图4a，本申请实施例所提供的晶体管装置从最终结构形态上看，电极结构123与沟道层122相当于形成一个具有收容空间的口袋结构，收容空间具有开口，开口朝向第一电极121的基座M，容纳空间用于收容第一电极121。沟道层122相当于口袋结构的内结构层，电极结构123相当于口袋结构的外结构层，电极结构123包裹于沟道层122外。且在图3和图4a所示的结构中，电极结构123中的各个电极层(例如第一电极层、第二电极层和第三电极层)以及电极介质层(例如第一介质层和第二介质层)为圆环形并环绕在沟道层122的外侧。图4b示出了图2中晶体管装置被B面剖切后的另一种剖面结构示意图，与图4a所示的结构类似，隔离介质层124环绕第一电极121，沟道层122环绕隔离介质层124，电极结构123(此处示出为电极层)环绕沟道层122。区别在于，该晶体管装置中，第一电极121的截面可为矩形，隔离介质层124的截面、沟道层122的截面以及电极结构123的截面均为方形环。应当理解，第一电极121的截面还可能是其他的多边形(例如图4c所示的六边形)，隔离介质层124的截面、沟道层122的截面以及电极结构123的截面为与第一电极121形状对应的多边形环。第一电极121的截面还可能是其他的不规则形状(例如图4d所示的类抛物线形)，隔离介质层124的截面、沟道层122的截面以及电极结构123的截面为与第一电极121形状对应的不规则形状环。当然，隔离介质层124的截面、沟道层122的截面以及电极结构123的截面还可以并不与第一电极121的形状对应(例如第一电极121的截面为圆形，而隔离介质层124的截面、沟道层122的截面以及电极结构123的截面为方形环)，此处不再赘述。
图5a至图5d示出了另几种晶体管装置被A面剖切后的剖面结构示意图。在图5a中所示的晶体管装置中，隔离介质层124覆盖于第一电极121朝向沟道层122的表面，隔离介质层124将电极结构123与第一电极121电隔离。沟道层122位于隔离介质层124的外侧，且沟道层122与电极结构123在结构上存在一些交叉。电极结构123具有沿第一方向Z依次分布的漏极1232、源极1231以及漏极1232，沟道层122与电极结构123结构上产生交叉指的是：最靠近衬底结构11的漏极1232与源极1231位于沟道层122的外侧，最靠近基座M的漏极1232位于隔离介质层124与沟道层122之间。将图5b中所示的晶体管装置与图5a所示的晶体管装置进行比较，区别在于：图5b中沟道层122靠近衬底结构11的端面，最靠近衬底结构11的漏极1232朝向衬底结构11的表面，二者位于同一平面内。在图5c中所示的晶体管装置中，隔离介质层124覆盖于第一电极121朝向沟道层122的表面，隔离介质层124将电极结构123与第一电极121电隔离。沟道层122位于隔离介质层 124与电极结构123之间，具体地，沟道层122仅设置于第一电极121的周向外表面，并未覆盖第一电极121沿第一方向Z朝向衬底结构11的端部。在第一电极121朝向衬底结构11的端部一侧，隔离介质层124与最靠近衬底结构11的漏极1232接触。在图5d中，为了避免电极层在与沟道层122接触的区域发生扩散，降低二者接触的费米钉扎效应，在电极层与沟道层122之间设置绝缘层125，该绝缘层125的存在可以使得电极层与沟道层122之间形成金属-绝缘层-半导体的结构。具体地，绝缘层125的厚度可以设定为0.1-2nm。
一些实施例中，本申请实施例还提供一种如图6所示的晶体管装置。该晶体管装置中的第一电极121与图3所示的晶体管装置中的第一电极121类似，即第一电极121呈柱状且沿第一方向Z延伸。在第一电极121远离衬底结构11的一端还设置有基座M，基座M平行于衬底结构11。沟道层122沿第一电极121的周向外表面设置，但是沟道层122并不完全包裹第一电极121的周向外表面，电极结构123沿沟道层122的周向外表面设置，但是电极结构123并不完全包裹沟道层122的周向外表面。隔离介质层124设置于沟道层122与第一电极121以及沟道层122与基座M之间，隔离介质层124可以将第一电极121与电极结构123电隔离。电极结构123包括沿第一方向Z排布的至少两个电极层，任意两个相邻的电极层之间通过电极介质层1233实现电隔离，防止两个相邻的电极层之间短接。
在图6中，电极结构123示例性地包括三个电极层(一个源极1231以及两个漏极1232)，源极1231位于两个漏极1232之间。其中，最靠近基座M的电极层与沟道层122之间也设置有电极介质层1233。为了实现第一电极121对沟道层122的驱动，沿垂直于第一方向Z的第二方向X，第一电极121与任意两个电极层之间的沟道层122对应。
以图2中B所在平面剖切图6所示的晶体管装置，得到图7a所示的剖面结构示意图，在第一电极121与沟道层122对应的范围内，隔离介质层124半环绕第一电极121，沟道层122半环绕隔离介质层124，电极结构123(此处示出为电极层)半环绕沟道层122。其中，沟道层122与电极层接触的面与垂直于第一方向Z的面的交线长度相当于任意两个相邻的电极层之间沟道的沟道宽度W。
基于图6所示的另一种晶体管装置沿B-B所在平面的剖面结构可以参照图7b所示，与图7a所示结构类似，隔离介质层124半环绕第一电极121，沟道层122半环绕隔离介质层124，电极结构123(此处示出为电极层)半环绕沟道层122。区别在于，该晶体管装置中，第一电极121的截面为矩形，隔离介质层124的截面、沟道层122的截面以及电极结构123的截面均为折线形半环。
应当理解，第一电极121的截面还可能是其他的多边形(例如图7c所示)，隔离介质层124的截面、沟道层122的截面以及电极结构123的截面为与第一电极121形状对应的折线形半环。第一电极121的截面还可能是其他的不规则形状(例如图7d所示的类扇形)，隔离介质层124的截面、沟道层122的截面以及电极结构123的截面为与第一电极121形状对应的不规则形状环。当然，隔离介质层124的截面、沟道层122的截面以及电极结构123的截面还可以不与第一电极121的形状对应，此处不再赘述。
基于图6所示的另一种晶体管装置沿B-B所在平面的剖面结构可以参照图7e所示，第一电极121、隔离介质层124、沟道层122以及电极结构123(此处以电极层示出)沿第二方向X排布。此处，第一电极121、隔离介质层124、沟道层122、电极结构123的结构较为规则，各层的延展方向平行于第三方向Y和第一方向Z。当然，第一电极121、隔离介质层124、沟道层122、电极结构123的结构还可以是不规则的，此处不再赘述。
需要说明的是，图6所示的晶体管装置相当于图3所示晶体管装置沿第一方向Z对半分割的其中一半结构，对应地，图7a所示的晶体管装置相当于图4a所示晶体管装置沿第一方向Z对半分割的其中的一半结构，图7b所示的晶体管装置相当于垂直于第二方向X对半分割图4b所示晶体管装置后的其中一半结构，图7c所示的晶体管装置相当于垂直于第二方向X对半分割图4c所示晶体管装置后的其中一半结构，图7d所示的晶体管装置相当于垂直于第二方向X对半分割图4d所示晶体管装置后的其中一半结构，可以互相参照。
图8示出了另一种晶体管装置被A面剖切后的剖面结构示意图，其中功能结构12具体包括第一电极121、沟道层122、电极结构123、隔离介质层124。该晶体管装置中，电极结构123包括沿第一方向Z依次堆叠的至少两个电极层以及位于任意两个电极层之间的电极介质层1233，具体包括依次堆叠的第一电极层、第一介质层、第二电极层、第二介质层以及第三电极层，第一介质层用于隔离第一电极层和第二电极层，防止第一电极层和第二电极层短接；第二介质层用于隔离第二电极层和第三电极层，防止第二电极层和第三电极层短接；此处的堆叠方向相当于第一方向Z，且堆叠方向可以为自衬底结构11指向基座M，也可以为自基座M指向衬底结构。其中，第一电极层和第三电极层的电极极性一致(同为源极或漏极)，第二电极层则与第一电极层、第三电极层极性相反(当第一电极层和第三电极层为源极时，第二电极层为漏极；当第一电极层和第三电极层为漏极时，第二电极层为源极)。根据图3所示，将第一电极层和第三电极层设定为两个漏极1232，将第二电极层设定为一个源极1231，第一介质层和第二介质层均为电极介质层1233。在图8中，电极结构123除最靠近衬底结构11的漏极1232之外的其他结构呈柱状且沿第一方向Z延伸。沟道层122包括经过掺杂的半导体材料，掺杂的原子能够提供载流子，这些载流子可以用作传导电流，沟道层122设置于电极结构123的外侧以与任意一个电极层接触。第一电极121包裹于沟道层122外侧，隔离介质层124设置于第一电极121与沟道层122之间。其中，第一电极121可以作为该晶体管装置的栅极，且第一电极121也具有平行于衬底结构11的基座M。
请继续参照图8，在该晶体管装置中，电极结构123相当于包括沿第一方向Z排布的第一电极层(漏极1232)、第一介质层(电极介质层1233)、第二电极层(源极1231)、第二介质层(电极介质层1233)、第三电极层(漏极1232)，任意两个相邻的电极层之间相当于通过电极介质层1233实现电隔离，防止两个相邻的电极层之间短接。其中，第一电极层和第三电极层(相当于两个漏极1232)之间通过连接结构(例如导线，此处未示出)电连接。沟道层122与任意一个电极层接触，两个相邻的电极层(相当于一个源极1231和一个漏极1232)在第一电极121驱动下可以通过该两个电极层之间的沟道层122实现电子传输以形成沟道电流。此处，沿第一方向Z，两个相邻的电极层(相当于一个源极1231和一个漏极1232)之间的距离，相当于该两个电极层之间沟道的沟道长度L。应当理解，为了实现第一电极121对沟道层122的驱动，沿垂直于第一方向Z的第二方向X，第一电极121与任意两个电极层之间的沟道层122对应。
应当理解，图8中的第一电极层和第三电极层还可以为源极1231，第二电极层则对应为漏极，此处并不限定；且图8相当于示出了本申请实施例所提供的晶体管装置最简单的一种结构，在具体应用时，根据晶体管装置结构允许，电极层的数量还可以为更多个，只需要满足任意两个电极层之间通过电极介质层1233电隔离即可，且同极性的电极层电连接。当用作源极1231的电极层的数量大于等于2，任意两个源极1231之间电连接，可以 充当晶体管装置的源极；当用作漏极1232的电极层的数量大于等于2，任意两个漏极1232之间电连接，可以充当晶体管装置的漏极。为了方便描述，在下文中用源极1231和漏极1232直接指代某一电极层。应当理解，该晶体管装置还可以根据需要调整部分电极层、电极介质层1233、沟道层122以及隔离介质层124的结构，只需要满足第一电极121与电极结构123之间的对应关系即可。
图9a示出了图8中晶体管装置被B面剖切后的剖面结构示意图，B面垂直于第一方向Z且穿过其中一个电极层。如图9a所示，在第一电极121与沟道层122对应的范围内，沟道层122环绕电极结构123(此处示出为电极层)，隔离介质层124环绕沟道层122，第一电极121环绕隔离介质层124。其中，沟道层122与电极层接触的面与垂直于第一方向Z的面的交线长度相当于任意两个相邻的电极层之间沟道的沟道宽度W。当晶体管装置具有n个电极层，n大于等于2，每两个电极层之间存在一个沟道，该晶体管装置将会存在n-1个沟道，相当于存在n-1个沟道宽度W，整个晶体管装置的有效沟道宽度W 总相当于(n-1)W；沿第一方向Z，在晶体管装置合理的尺寸范围内，增加电极层的数量，可以增加有效沟道宽度W 总，有利于提高该晶体管装置的电流大小。
结合图8和图9a，本申请实施例所提供的晶体管装置从最终结构形态上看，第一电极121与沟道层122相当于形成一个具有收容空间的口袋结构，收容空间具有开口，开口朝向衬底结构11，收容空间用于收容电极结构123。沟道层122相当于口袋结构的内结构层，第一电极121相当于口袋结构的外结构层，第一电极121包裹于沟道层122外。图9b示出了图8中晶体管装置被B面剖切后的另一种剖面结构示意图，与图9a所示的结构类似，沟道层122环绕电极结构123(此处示出为电极层)，隔离介质层124环绕沟道层122，第一电极121环绕隔离介质层124。区别在于，该晶体管装置中，电极结构123的截面为矩形，隔离介质层124的截面、沟道层122的截面以及第一电极121的截面均为方形环。应当理解，电极结构123的截面还可能是其他的多边形(例如图9c所示的六边形)，隔离介质层124的截面、沟道层122的截面以及第一电极121的截面为与电极结构123形状对应的多边形环。电极结构123的截面还可能是其他的不规则形状(例如图9d所示的类抛物线形)，隔离介质层124的截面、沟道层122的截面以及第一电极121的截面为与电极结构123形状对应的不规则形状环。当然，在一种可选的情况中，隔离介质层124的截面、沟道层122的截面以及第一电极121的截面并不与电极结构123的形状对应(例如电极结构123的截面为圆形，而隔离介质层124的截面、沟道层122的截面以及第一电极121的截面为方形环)，此处不再赘述。
一些实施例中，本申请实施例还提供一种如图10所示的晶体管装置。在图10所示的晶体管装置中，电极结构123与图8所示的晶体管装置中的电极结构123类似，包括沿第一方向Z排布的至少两个电极层，任意两个相邻的电极层之间通过电极介质层1233实现电隔离，防止两个相邻的电极层之间短接。电极结构123除最靠近衬底结构11的漏极1232之外的其他结构呈柱状且沿第一方向Z延伸。沟道层122沿电极结构123的周向外表面(即电极结构123平行于第一方向Z的外表面)设置，但是沟道层122并不包裹电极结构123的周向外表面，第一电极121沿沟道层122的周向外表面(即沟道层122平行于第一方向Z的外表面)设置，但是第一电极121并不包裹沟道层122的周面。隔离介质层124设置于沟道层122与第一电极121之间，隔离介质层124可以将第一电极121与电极结构123电隔离。为了实现第一电极121对沟道层122的驱动，沿垂直于第一方向Z的第二方向X， 第一电极121与任意两个电极层之间的沟道层122对应。
以图2中B所在平面剖切图10所示的晶体管装置，得到图11a所示的剖面结构示意图，在第一电极121与沟道层122对应的范围内，沟道层122半环绕电极结构123(此处示出为电极层)，隔离介质层124半环绕沟道层122，隔离介质层124半环绕第一电极121。其中，沟道层122与电极层接触的面与垂直于第一方向Z的面的交线长度相当于任意两个相邻的电极层之间沟道的沟道宽度W。
基于图10所示的另一种晶体管装置沿B-B所在平面的剖面结构可以参照图11b所示，与图11a所示结构类似，沟道层122半环绕电极结构123(此处示出为电极层)，隔离介质层124半环绕沟道层122，隔离介质层124半环绕第一电极121。区别在于，该晶体管装置中，电极结构123的截面为矩形，隔离介质层124的截面、沟道层122的截面以及第一电极121的截面均为折线形半环。应当理解，电极结构123的截面还可能是其他的折线形(例如图11c所示)，隔离介质层124的截面、沟道层122的截面以及第一电极121的截面为与电极结构123形状对应的折线形半环。电极结构123的截面还可能是其他的不规则形状(例如图11d所示的类扇形)，隔离介质层124的截面、沟道层122的截面以及第一电极121的截面为与电极结构123形状对应的不规则形状环。当然，隔离介质层124的截面、沟道层122的截面以及第一电极121的截面还可以不与电极结构123的形状对应，此处不再赘述。
基于图10所示的另一种晶体管装置沿B-B所在平面的剖面结构可以参照图11e所示，第一电极121、隔离介质层124、沟道层122以及电极结构123(此处以电极层示出)沿第二方向排布。此处，第一电极121、隔离介质层124、沟道层122、电极结构123的结构较为规则，各层的延展方向平行于第三方向Y和第一方向Z。当然，第一电极121、隔离介质层124、沟道层122、电极结构123的结构还可以是不规则的，此处不再赘述。
需要说明的是，图10所示的晶体管装置相当于垂直于第二方向X对半分割图8所示晶体管装置后的其中一半结构，对应地，图11a所示的晶体管装置相当于垂直于第二方向X对半分割图9a所示晶体管装置后的其中一半结构，图11b所示的晶体管装置相当于垂直于第二方向X对半分割图9b所示晶体管装置后的其中一半结构，图11c所示的晶体管装置相当于垂直于第二方向X对半分割图9c所示晶体管装置后的其中一半结构，图11d所示的晶体管装置相当于垂直于第二方向X对半分割图9b所示晶体管装置后的其中一半结构，可以互相参照。
应当理解，图3至图11e所示的剖面结构，都是对图2所示的晶体管装置的示例性说明，在具体实施中，功能结构12的各部分还可能有其他的变形，但是其电极结构123均包括多个沿第一方向Z排布且相互电隔离的电极层，其他的第一电极121、沟道层122、隔离介质层124以及其他部分都以实现晶体管功能为目的。
示例性地，电极层的材质应为导电性材料，具体为金属或其他具有导电功能的化合物，金属例如钛、金、钨、铝、铜、钌、钼、银、铂或铋中的一种或多种的组合，化合物例如氮化钛、氮化钨或氧化铟锡中的一种或多种的组合，任意一个电极层可以与沟道层122形成电学接触。
第一电极121的材质也为导电性材料，具体为金属或其他具有导电功能的化合物，例如钛、金、钨、铝、铜、钌、钼、银、铂、氮化钛、氧化铟锡或氧化铟锌中的一种或多种的组合；隔离介质层124的材质可以选择硅氧化物、硅氮化物、三氧化二铝、二氧化铪、 二氧化锆、二氧化钛或三氧化二钇中的一种或多种的组合，其组合方式可以是材料掺杂组合(如图12a所示的第二材料掺杂到作为基体的第一材料中)、叠层组合(如图12b所示的第一材料和第二材料交替叠层)或掺杂与叠层的组合(如图12c所示既有第二材料掺杂到作为基体的第一材料中，也有第一材料和第二材料交替叠层)。沟道层122的材质可以为金属氧化物、多元化合物、石墨烯、二硫化钼、黑磷中的一种或多种的组合，例如硅、多晶硅、非晶硅等硅基半导体，氧化铟、氧化锌、氧化镓、氧化铟锡、二氧化钛等金属氧化物。另外，电极介质层1233可以与隔离介质层124选择相同的材质。
在一些实施例中，沿第一方向Z，可以将任意两个相邻的电极层之间的距离设置为相同，在晶体管装置的电极结构123制备过程中，可以采用相同的工艺制备多层电极层，有利于简化器件制备工艺，这样的结构也有利于晶体管装置的参数计算，即n个电极层，相当于晶体管装置可以具有n-1个沟道宽度，沟道电流相当于倍增。
以图3所示的晶体管装置为例，其具有一个源极1231和两个漏极1232，任意两个电极层之间的距离设置为相同，使得该晶体管装置能够形成2倍的沟道宽度。对现有技术中的晶体管装置以及本申请实施例所提供的晶体管装置分别进行模拟仿真可以得到图13a和图13b所示的电学表征图，其中，图13a和图13b中图标的横坐标均为第一电极的电压，单位为伏特(V)，纵坐标为沟道电流，单位为安培(A)。如图13a所示，现有的一种晶体管装置中，沟道电流与第一电极电压为正相关，但是随第一电极电压的增大，沟道电流的提升速率较慢，当第一电极电压达到2V时，沟道电流达到0.000024A附近；而图13b所示的本申请实施例提供的晶体管装置中，当第一电极电压逐渐增大，沟道电流增幅明显，当第一电极电压达到2V时，沟道电流可以达到0.00005A附近，相当于现有技术中沟道电流的二倍。可见，相较于现有技术，本申请提供的晶体管装置在原有迁移率、沟道长度、栅氧厚度等因素不变的情况下可以实现倍增工作电流，具有成本低、工艺简单、与现有技术工艺类似的优点，且不增加水平方向(垂直于晶体管装置的高度方向，即第一方向Z)的面积，保持集成密度。
可以看出，本申请实施例所提供的晶体管装置，在不增加器件单元面积的基础上，通过增加电极层(即交替增加源极/漏极)可以获得多个等效沟道，从而提高整个晶体管装置的有效沟道宽度，提高器件的输出电流。将该晶体管装置作为读取晶体管应用到增益单元存储器中，可以提高读取效率。当然，该晶体管装置还可以应用到逻辑、模拟、射频电路等需要提供不同晶体管宽度选择的场景中。
本申请实施例还提供一种如图14所示的电子器件，该电子器件示例为存储器，包括信号写晶体管1、读晶体管2、存储单元3、第一写信号线41、第二写信号线42、第一读信号线51和第二读信号线52，读晶体管2可为上述实施例提供的任一种晶体管装置。
具体地，第一写信号线41与信号写晶体管1的第一电极连接，第二写信号线42与写晶体管1的源极连接；第一读信号线51与读晶体管2的源极(或漏极)，第二读信号线52与读晶体管2的漏极(或源极)连接；写晶体管1的漏极与读晶体管2的第一电极结构连接，且存储单元3连接于写晶体管1与读晶体管2之间。
该存储器在进行“写”的工作中，通过第一写信号线41控制写晶体管1开启，将第二写信号线42的电位传递到读晶体管2的第一电极，使得读晶体管2的第一电极电位与第二写信号线42同步以实现“0”和“1”的写入；然后，第一写信号线41控制写晶体管1关闭，读晶体管2的第一电极电位由存储在存储单元3的电量决定。在进行“读”的工 作中，只需要读取读晶体管2的电流变化或读第二读信号线52的电压变化即可判断存储状态。由于读晶体管2具有较大的电流，使得存储器在信号读取时具有较高的读取速率。
如图3和图8所示，晶体管装置的结构可能有至少两种，针对不同结构的晶体管装置，其制备方法可以有不同的实施方式。
本申请实施例提供一种晶体管装置的制备方法，用于制备图3所示的晶体管装置。如图15所示，该制备方法包括：
步骤S11：沿第一方向Z，在衬底结构11上依次交替设置电极层和电极介质层1233以形成电极结构123，得到如图16所示的结构；电极层的数量为至少两个，该至少两个电极层包括交替排布的至少一个源极1231和至少一个漏极1232，当源极1231为至少两个，任意两个源极1231之间电连接，当漏极1232为至少两个，任意两个漏极1232之间电连接。
其中，电极结构123具体是以一层电极层、一层电极介质层1233依次铺设的方式实现的。源极1231和漏极1232在制备时的先后顺序不做限定，但是二者必须是交替进行制备的，最终相邻的一个源极1231与一个漏极1232之间相当于形成一个沟道。当源极1231的数量大于等于两个，任意两个源极1231之间电连接，形成整个晶体管装置的源极；当漏极1232的数量大于等于两个，任意两个漏极1232之间电连接，形成整个晶体管装置的漏极。应当理解，任意两个源极1231之间的电连接可以通过外部走线(相当于连接结构)实现，此处未予示出；同理，任意两个漏极1232之间的电连接可以通过外部走线(相当于连接结构)实现，此处未予示出。
步骤S12：刻蚀电极结构123以形成沿第一方向Z延伸的第一凹槽K1，第一凹槽K1连通各电极层，得到如图17a所示的结构；
步骤S13：在第一凹槽K1内形成沟道层122，沟道层122形成第二凹槽K2，得到如图17b所示的结构。至此，电极结构123和沟道层122形成的结构相当于口袋结构，第二凹槽K2相当于口袋结构的收容空间。
其中，当沟道层122填充在第一凹槽K1内，可以沿第一方向Z蚀刻沟道层122以形成第二凹槽K2；当沟道层122贴附在第一凹槽K1的内表面，沟道层122背离第一凹槽K1内表面的一侧可以自然形成第二凹槽K2。
步骤S14：在第二凹槽K2内形成第一电极121；具体地，可以先第二凹槽K2内形成隔离介质层124，隔离介质层124可以形成有第三凹槽K3，得到图17c所示结构；当隔离介质层124填充在第二凹槽K2内，可以沿第一方向Z蚀刻隔离介质层124以形成第三凹槽K3；当隔离介质层124贴附在第二凹槽K2的内表面，隔离介质层124背离第一凹槽K2内表面的一侧可以自然形成第三凹槽K3。然后在第三凹槽K3内填充第一电极材料后形成第一电极121，得到如图3所示的结构。其中，第一电极121还具有基座M。
应当理解，在制备图5c和图6所示的晶体管装置结构时，也可以采用该方法。在制备图5a和图5b的结构时，则需要调整部分电极层、电极介质层1233、沟道层122以及隔离介质层124的结构，此处不再赘述，只需要满足第一电极121与电极结构123之间的对应关系即可。
本申请实施例提供一种晶体管装置的制备方法，用于制备图8所示的晶体管装置。如图18所示，该制备方法包括：
针对图8所示的晶体管结构，上述步骤S1之后的制备方法具体包括：
步骤S21：沿第一方向Z，在衬底结构11上依次交替设置电极层和电极介质层1233以形成电极结构123，得到如图16所示的结构；电极层的数量为至少两个，该至少两个电极层包括交替排布的至少一个源极1231和至少一个漏极1232，当源极1231为至少两个，任意两个源极1231之间电连接，当漏极1232为至少两个，任意两个漏极1232之间电连接。该步骤S21与上文中的步骤S11类似，此处不再赘述。
步骤S22：在电极结构123外侧形成沟道层122；具体可以对图16所示的结构进行刻蚀形成图19a所示的结构，使得电极结构123除最靠近衬底结构11的漏极1232之外的其他结构呈柱状，然后在电极结构123的外侧沉积沟道材料形成沟道层122，得到如图19b所示结构，沟道层122也呈柱状。
步骤S23：在沟道层122的外侧形成第一电极121；在形成第一电极121之前，先在沟道层122的外侧形成隔离介质层124，得到图19c所示结构；然后在隔离介质层124外侧沉积电极材料形成第一电极121，得到图8所示的结构。
应当理解，在制备图10所示的晶体管装置结构时，也可以采用该方法。并且，可以根据需要调整部分电极层、电极介质层1233、沟道层122以及隔离介质层124的结构，只需要满足第一电极121与电极结构123之间的对应关系即可。
以上，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以权利要求的保护范围为准。

Claims (23)

  1. 一种晶体管装置，其特征在于，包括：衬底结构以及设置于所述衬底结构上的沟道层、第一电极和电极结构；
    所述电极结构包括沿第一方向排布的至少两个电极层，任意两个相邻的所述电极层之间电隔离，所述第一方向垂直于所述衬底结构；沿所述第一方向，所述至少两个电极层包括交替排布的至少一个源极和至少一个漏极；当所述源极为至少两个，任意两个所述源极之间电连接；当所述漏极为至少两个，任意两个所述漏极之间电连接；
    所述沟道层位于所述第一电极与所述电极结构之间，且所述沟道层与任意一个所述电极层接触。
  2. 如权利要求1所述的晶体管装置，其特征在于，所述沟道层设置在所述第一电极的外侧，所述电极结构设置在所述沟道层的外侧。
  3. 如权利要求2所述的晶体管装置，其特征在于，所述沟道层在所述衬底结构上的投影覆盖所述第一电极朝向所述衬底结构的端部在所述衬底结构上的投影。
  4. 如权利要求1所述的晶体管装置，其特征在于，所述沟道层设置在所述电极结构的外侧，所述第一电极设置在所述沟道层的外侧。
  5. 如权利要求4所述的晶体管装置，其特征在于，所述沟道层在所述衬底结构上的投影覆盖所述电极结构远离所述衬底结构的端部在所述衬底结构上的投影。
  6. 如权利要求1-5中任一项所述的晶体管装置，其特征在于，还包括隔离介质层，所述隔离介质层设置于所述第一电极与所述沟道层之间。
  7. 如权利要求1-6中任一项所述的晶体管装置，其特征在于，每个所述电极层与所述沟道层的接触界面设置有绝缘层。
  8. 如权利要求7所述的晶体管装置，其特征在于，所述绝缘层的厚度为0.1-2纳米nm。
  9. 如权利要求1-7中任一项所述的晶体管装置，其特征在于，所述第一电极沿所述第一方向延伸。
  10. 如权利要求1-9中任一项所述的晶体管装置，其特征在于，沿所述第一方向，任意两个相邻的所述电极层之间的距离相同。
  11. 如权利要求1-10中任一项所述的晶体管装置，其特征在于，任意两个相邻的所述电极层之间电隔离包括：任意两个相邻的所述电极层之间设置有隔离介质层。
  12. 如权利要求1-11中任一项所述的晶体管装置，其特征在于，所述电极层的材质为钛、金、钨、铝、铜、钌、钼、银、铂、铋、氮化钛、氮化钨、氧化铟锡或氧化铟锌中的一种或多种的组合。
  13. 如权利要求1-12中任一项所述的晶体管装置，其特征在于，所述第一电极的材质为钛、金、钨、铝、铜、钌、钼、银、铂、氮化钛、氧化铟锡或氧化铟锌中的一种或多种的组合。
  14. 如权利要求1-13中任一项所述的晶体管装置，其特征在于，所述沟道层的材质为多元化合物、石墨烯、二硫化钼或黑磷中的一种或多种的组合。
  15. 一种晶体管装置，其特征在于，包括：
    第一电极；
    口袋结构，所述口袋结构包括内结构层和外结构层，所述内结构层包括经过掺杂的半 导体材料，所述内结构层围成口袋，用于收容所述第一电极；所述外结构层包裹于所述内结构层外；所述外结构层包括依次堆叠的第一电极层、第一介质层、第二电极层、第二介质层和第三电极层，所述第一电极层、第一介质层、第二电极层、第二介质层和第三电极层均为环状且环绕在所述内结构外；
    连接结构，用于电连接所述第一电极层和所述第三电极层。
  16. 如权利要求15所述的晶体管装置，其特征在于，所述第二电极和所述第四电极均为源极，所述第一电极层为漏极；或，
    所述第二电极和所述第四电极均为漏极，所述第三电极为源极。
  17. 如权利要求15或16所述的晶体管装置，其特征在于，还包括设置于所述第一电极外侧的隔离介质层，所述隔离介质层位于所述第一电极与所述内结构层之间。
  18. 如权利要求15-17中任一项所述的晶体管装置，其特征在于，所述第一介质层和所述第二介质层的材质相同。
  19. 一种电子器件，其特征在于，包括写晶体管、读晶体管、存储单元、第一写信号线、第二写信号线、第一读信号线和第二读信号线，所述读晶体管为权利要求1-14或权利要求15-18中任一项所述的晶体管装置；
    所述第一写信号线与所述写晶体管的第一电极连接，所述第二写信号线与所述写晶体管的源极连接；所述第一读信号线与所述读晶体管的源极连接，所述第二读信号线与所述读晶体管的漏极连接；
    所述写晶体管的漏极与所述读晶体管的第一电极连接，且所述存储单元连接于所述写晶体管与所述读晶体管之间。
  20. 一种晶体管装置的制备方法，其特征在于，包括：
    沿第一方向，在衬底结构上依次交替设置电极层和隔离介质层以形成电极结构；所述电极层为至少两个，所述至少两个电极层包括交替排布的至少一个源极和至少一个漏极；当所述源极为至少两个，任意两个所述源极之间电连接；当所述漏极为至少两个，任意两个所述漏极之间电连接；
    刻蚀所述电极结构以形成沿所述第一方向延伸的第一凹槽，所述第一凹槽连通各所述电极层；
    在所述第一凹槽内形成沟道层，所述沟道层形成第二凹槽；
    在所述第二凹槽内形成所述第一电极。
  21. 如权利要求20所述的晶体管装置的制备方法，其特征在于，所述晶体管装置还包括隔离介质层，所述隔离介质层设置于所述第一电极的表面，且所述隔离介质层位于所述第一电极与所述沟道层之间；所述在所述第二凹槽内形成所述第一电极包括：
    在所述第二凹槽内形成所述隔离介质层，所述隔离介质层形成第三凹槽；
    在所述第三凹槽内形成所述第一电极。
  22. 一种晶体管装置的制备方法，其特征在于，包括：
    沿第一方向，设置电极层和隔离介质层以形成电极结构；所述电极层为至少两个，所述至少两个电极层包括交替排布的至少一个源极和至少一个漏极；当所述源极为至少两个，任意两个所述源极之间电连接；当所述漏极为至少两个，任意两个所述漏极之间电连接；
    在所述电极结构外侧形成沟道层；
    在所述沟道层的外侧形成第一电极。
  23. 如权利要求22所述的晶体管装置的制备方法，其特征在于，所述晶体管装置还包括隔离介质层，所述隔离介质层设置于所述第一电极的表面，且所述隔离介质层位于所述第一电极与所述沟道层之间；所述在所述沟道层的表面形成所述第一电极包括：
    在所述沟道层外侧形成所述隔离介质层；
    在所述隔离介质层的外侧形成所述第一电极。
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