WO2023101097A1

WO2023101097A1 - Memory device capable of dynamically switching error correction and error detection in on-die error correction code

Info

Publication number: WO2023101097A1
Application number: PCT/KR2021/019871
Authority: WO
Inventors: 안정호; 박재현; 윤성민
Original assignee: 서울대학교산학협력단
Priority date: 2021-12-03
Filing date: 2021-12-24
Publication date: 2023-06-08
Also published as: KR20230083689A

Abstract

The present invention relates to a memory device, which dynamically switches error correction and error detection so that error correction and error detection can be selected according to circumstances. The present invention comprises: an error correction code encoder comprising a parity generation unit, which generates parity bits from data bits input from a memory control unit, so as to write, on a memory cell array, a codeword including the data bits and the parity bits; and an error correction code decoder comprising a syndrome generation unit, which reads the codeword including the data bits and the parity bits written on the cell array, and then computes the codeword to generate syndrome data, a syndrome decoding unit, which decodes the syndrome data generated by the syndrome generation unit so as to generate error location bits indicating the location of an error bit, an error correction unit, which generates correction bit data by comparing and computing respective bits per location of the data bits and the error location bits if the data bits from the memory cell array and the error location bits generated by the syndrome decoding unit are received, an error detection unit, which receives the syndrome data output from the syndrome generation unit, and then performs an OR calculation and outputs a digital signal "1" or a digital signal "0" as an calculation value, a PIM enable unit, which includes the digital signal "0" and the digital signal "1" so as to output either the digital signal "0' or the digital signal "1" while controlled by means of the memory control unit, and a PIM enable switch unit, which receives the data bits from the memory cell array, receives the correction bit data from the error correction unit, receives either the digital signal "0" or the digital signal "1" from the PIM enable unit so as to output the correction bit data output from the error correction unit if the digital signal "0" is received from the PIM enable unit and output the data bits if the digital signal "1" is received from the PIM enable unit.

Description

Dynamically switchable memory device between error correction and error detection in on-die error correction code

The present invention relates to an error correction code (ECC) that increases data reliability of a memory including DRAM (Dynamic Random Access Memory).

There are two types of semiconductors: memory semiconductors and system semiconductors. A memory semiconductor is a semiconductor used for storing information, and a system semiconductor is a semiconductor that interprets, calculates, and processes data.

Existing memory semiconductors and system semiconductors are separated, so there is a problem that a bottleneck occurs in the process of information passing between the two. These problems have recently become an obstacle to the growth of the rapidly growing big data processing industry and AI-related industries.

As a way to solve this problem, processing-in-memory technology has been proposed. Processing-in-Memory technology can solve the bottleneck between the processor and memory by reducing data transfer between the processor and memory by performing operations previously performed by the processor near or inside the memory. In addition, the processing-in-memory technology utilizes the large bandwidth inside the memory to perform calculations and demonstrates improved calculation performance. In addition, it shows the feature of reducing energy consumption by reducing the data transmission distance between the calculator and memory.

Accordingly, research and development on processing-in-memory technology, that is, processing-in-memory (PIM) technology, is actively progressing.

However, as an example of a problem that has occurred in the PIM (Processing-In-Memory) technology so far, since the operation is performed near the memory, the existing data error detection and correction performed on the processor side cannot be applied to the PIM technology. . In particular, on-die error correction code (On-die ECC) performed inside the memory chip can be applied to the PIM technology, but the applied on-die error correction code has lower error correction capability than the error correction code performed on the processor side. indicates a problem.

[Prior art literature] Republic of Korea Patent Publication No. 10-2021-0142213 (published date: 2020.12.22)

The present invention is a problem in which the error correction capability of the on-die error correction code is not high in processing many bits of errors due to the inability to detect errors of several bits in the processing-in-memory (PIM) technology that operates inside the memory chip. want to solve

The technical problem of the present invention is not limited to the above-mentioned problems, and other technical problems not mentioned will be clearly understood by those skilled in the art from the following description.

In order to achieve the above technical problem, a memory device capable of dynamically switching between error correction and error detection in the on-die error correction code of the present invention generates parity bits from data bits input from a memory control unit to generate data bits and parity data bits in a memory cell array. an error correction code encoder including a parity generator that writes a codeword including bits and a syndrome generator that reads data bits and codewords including parity bits written in the memory cell array, and generates syndrome data through operation; When the syndrome decoding unit decodes the syndrome data generated through the syndrome generation unit and generates error location bits indicating the location of error bits, and the data bits and error location bits generated by the syndrome decoding unit are received from the memory cell array, the data bit An error correcting unit that generates correcting bit data by comparing and operating each bit for each position of the error location bit, and after receiving the syndrome data output from the syndrome generating unit, a logical sum operation is performed, and a digital signal '1' or a digital signal as an operation value A PIM that outputs either a digital signal '0' or a digital signal '1', controlled by the memory control unit, including an error detector outputting a signal '0' and a digital signal '0' and a digital signal '1'. Receiving data bits through the enable unit and the memory cell array, receiving corrected bit data through the error correction unit, and receiving either digital signal '0' or digital signal '1' from the PIM enable unit, A PIM enable switch unit is provided which outputs correction bit data output from the error correction unit when the digital signal '0' is received from the PIM enable unit, and outputs data bits when the digital signal '1' is received from the PIM enable unit. It includes an error correcting code decoder.

Here, the syndrome generator may receive a codeword from the memory cell array when the memory performs a read operation. The syndrome generation unit includes a first parity module including a plurality of exclusive OR gates to read the data bits of the codeword and calculates a new parity bit, and a plurality of exclusive OR gates including parity bits received through the memory cell array and It may include a second parity module that receives parity bits output from the first parity module and executes an exclusive OR operation. In this case, the first parity module and the second parity module may include the same number of XOR gates.

Then, the syndrome decoding unit decodes the syndrome data input to the input side into a decimal number, outputs a digital signal '1' to the output terminal corresponding to the value of the decoded decimal number, and outputs a digital signal to the output terminal located at the remaining position. It can output '0'. The error correcting unit may include an exclusive OR gate for performing an exclusive OR operation by receiving a codeword at a first input terminal and receiving a digital signal output from a syndrome decoding unit at a second input terminal. The error detection unit may include a logical sum gate that outputs an error signal when any one digital signal '1' is input among the syndrome data input from the syndrome generation unit.

The present invention enables error correction and error detection to be dynamically switched in an on-die error correction code, thereby securing high reliability for error detection of multiple bits in PIM (Processing-In-memory) technology that operates inside a memory chip. make it possible In addition, error data is detected through a simplified path, so that detected error bits are later corrected and latency for error correction codes can be reduced.

In addition, the present invention is formed in a structure in which only the PIM enable unit and the PIM enable switch unit are added to the existing on-die ECC engine, so that the reusability of the existing on-die ECC engine can be increased.

1 is a block diagram of a memory device capable of dynamically switching between error correction and error detection in an on-die error correction code according to an embodiment of the present invention.

2 is a flowchart of a memory device capable of dynamically switching between error correction and error detection in an on-die error correction code according to an embodiment of the present invention.

3 is a structural diagram of a memory device capable of dynamically switching between error correction and error detection in an on-die error correction code according to an embodiment of the present invention.

4 and 5 are diagrams illustrating codewords used in a memory device capable of dynamically switching between error correction and error detection in an on-die error correction code according to an embodiment of the present invention.

6 to 14 are diagrams showing the states of the data bits of FIG. 3 expressed in binary and which data bits are received by the first parity module according to the states expressed in binary.

15 is a diagram showing an operating state of the syndrome generating unit of FIG. 7 .

16 to 18 are views showing which data bits are received by each XOR gate (#1 to #8) of the first parity module of FIG.

19 and 20 are diagrams showing an operating state of the syndrome generating unit of FIG. 3 .

21 and 22 are views showing an operating state of the syndrome decoding unit of FIG. 3 .

23 is a diagram showing an operating state of the error detection unit of FIG. 3 .

24 and 25 are diagrams illustrating an operating state of the PIM enable switch unit of FIG. 3 .

Advantages and features of the present invention and methods for achieving them will become clear with reference to the detailed description of the following embodiments in conjunction with the accompanying drawings.

However, the present invention is not limited to the embodiments disclosed below and may be implemented in a variety of different forms. Accordingly, only one embodiment among several embodiments has been described in the specific contents for carrying out the invention. The disclosed embodiments are intended to completely inform the scope of the invention to those skilled in the art to which the present invention belongs.

The definition of the invention is solely defined by the claims. Like reference numerals designate like elements throughout the specification.

The present invention relates to a memory device capable of dynamically switching between error correction and error detection in an on-die error correction code.

Hereinafter, a memory device capable of dynamically switching between error correction and error detection in an on-die error correction code according to an embodiment of the present invention will be described with reference to FIGS. 1 to 25 .

However, the present invention is described with reference to FIGS. 1 and 2 so that the description of a memory device capable of dynamically switching error correction and error detection in an on-die error correction code according to an embodiment of the present invention is concise and clear. explain in general. Hereinafter, components of the present invention will be described with reference to the description and FIG. 3 . And based on FIGS. 4 to 25, the operation of the components of the present invention will be described in detail.

1 is a flowchart of a memory device capable of dynamically switching between error correction and error detection in an on-die error correction code according to an embodiment of the present invention, and FIG. 2 is an on-die error correction code according to an embodiment of the present invention. It is a structural diagram of a memory device capable of dynamically switching error correction and error detection in

The present invention is a memory device 1 capable of dynamically switching between error correction and error detection by including a memory cell array and an on-die ECC engine.

The present invention can dynamically switch between error correction and error detection in an on-die error correction code, thereby increasing data reliability in processing-in-memory (PIM) technology that operates inside a memory chip. In addition, the present invention allows error data to be detected through a simplified path when switching to error detection, and the detected error data to be corrected later, so that error processing can be quickly processed in a memory device.

The memory device 1 interfaces with the memory controller A, and its operation can be generally controlled according to signals transmitted from the memory controller A. At this time, the memory controller A applies commands and addresses, controls the overall operation of the memory device, and enables the memory device to read or write data. That is, the memory control unit (A) allows the memory device to 'Read' data from the memory cell array (E) or 'Write' data to the memory cell array (E). In addition, the memory control unit (A) controls the PIM enable unit 250 through a Reserved for future use (RFU) command in the interface between the memory control unit and the memory (DRAM) or registers the PIM input in the mode register of the memory. By storing enable information, the PIM enable module 250 can control to read PIM enable information from a corresponding mode register. At this time, the memory control unit (A) controls the PIM enable unit 250 in this way so that a digital signal '1' or a digital signal '0' is output. At this time, the output digital signal is applied to the PIM enable switch unit 260.

As shown in FIG. 2, the present invention writes the code word D-1 while the on-die ECC engine, that is, the error correction code encoder 10 operates when the memory controller A writes in the memory. When the generated codeword (D-1) is written in the memory cell array (E) and read from the memory by the memory control unit (A), the error correction code decoder 20 operates while the memory cell After reading the codeword (D-2) written in the array (E), an error generated in the codeword can be detected while performing an operation by comparing the parity bit generated through the data bits with the read parity bit. Also, detected errors may be corrected.

Such a memory device 1 of the present invention may be an improved DRAM device from existing DRAM devices. For example, the memory device 1 of the present invention may be a DDR5 SDRAM (Double Data Rate Fifth Synchronous Dynamic Random Access Memory) device.

A memory device 1 capable of dynamically switching error correction and error detection in an on-die error correction code according to an embodiment of the present invention includes a memory cell array E, an error correction code encoder 10, and an error correction code. It includes a decoder 20 and the like as components. At this time, the memory cell array E may be a storage device used with the existing on-die ECC engine, and the present invention enables PIM included in the error correction code decoder 20 in the existing on-die ECC engine. Only the unit 250 and the PIM enable switch unit 260 may be formed in an additional structure. As described above, based on the structural feature in which only the PIM enable unit 250 and the PIM enable switch unit 260 are added, the present invention can increase the reusability of the existing on-die ECC engine.

Hereinafter, the components constituting the present invention will be described in detail with reference to FIGS. 2 and 3 described above.

3 is a structural diagram of a memory device 1 capable of dynamically switching between error correction and error detection in an on-die error correction code according to an embodiment of the present invention.

The memory cell array E stores data bits and parity bits generated by the error correction code encoder 10, and the error correction code decoder 20 uses the error correction code encoder 10 Data bit and parity bit stored or written by can be read. That is, the memory cell array E becomes a device capable of inputting and outputting data bits and parity bits.

As shown in FIG. 2, the error correction code encoder 10 generates a parity bit C from the data bit B-1 input from the memory controller A to form a memory cell array E , Cell Array) to write the codeword (D-1). The error correction code encoder 10 may include the parity generator 110 to generate parity bits C corresponding to the data bits based on the data bits received from the memory controller A. At this time, parity bits (C) can be P1, P2, P3, P4, P5, P6, P7, P8, and all of these parity bits (C) can be digital signals '0' or '1'. .

The error correcting code decoder 20 reads the codeword D-2 written in the memory cell array E, detects an error in the data read and written by the user, that is, an error in the codeword, and then in the PIM enable module Depending on the output digital signal, the detected error is corrected or the detected error is output as it is.

The error correction code decoder 20 includes a syndrome generator 210, a syndrome decoding unit 220, an error correction unit 230, an error detection unit 240, a PIM enable unit ( 250) and a PIM enable switch unit 260 as components. Components included in the error correcting code decoder 20 may be the most essential components of the present invention. Here, the syndrome generator 210 generates a parity bit (C) with a data bit read from the memory cell array (E) and compares the parity bit (C) with the parity bit read from the memory cell array (E). to generate syndrome data (G).

The syndrome generating unit 210 generates syndrome data G containing location information of a data error based on a code word to be read from the memory cell array E. As shown in FIG. 3, the syndrome generator 210 includes a first parity module 211 including a plurality of exclusive OR gates (#1XOR Gate to #16XOR Gate) and a plurality of exclusive OR gates (#9 to #16 ) may include a second parity module 212 including. Here, the first parity module 211 and the second parity module 212 may be composed of the same characteristics and the same number of XOR gates.

Such a syndrome generator 210 can read the data bit B-2 included in the code word D-2 through the first parity module 211, and can read the code word B-2 through the second parity module 212. Syndrome data (G) may be generated by receiving the parity bit (F) included in the word (D-2) and the parity bit (C) output from the first parity module 211. Then, the generated syndrome data may be applied to the syndrome decoding unit 220 .

The syndrome decoding unit 220 may decode the syndrome data G generated through the syndrome generating unit 210 to generate error location bits H. As an embodiment, the syndrome decoding unit 220 may generate an error location by performing one-hot encoding on the syndrome data and outputting only the number of bits corresponding to the size of the data. Here, one-hot encoding means enumerating categorical variables and displaying all items that are not applicable as 0 and applicable items as 1.

When the error correction unit 230 receives the data bit B-2 from the memory cell array E and the error location bit H generated by the syndrome decoding unit 220, the data bit B-2 and the error Correction bit data (I) is generated by comparing and calculating each bit for each position of the position bit (H). The error correction unit 230 includes a plurality of exclusive OR gates and performs an exclusive OR operation on the received digital signal.

The error correcting unit 230 receives the data bit B-2 received at the first input terminal of a plurality of exclusive OR gates, that is, the XOR gate, and the digital signal output from the syndrome decoding unit 220 at the second input terminal, thereby generating exclusive The logical sum operation is performed and the read data can be corrected based on the error location bit (H). For example, if the data bit is a digital signal '0' and the digital signal '0' output from the syndrome decoding unit 220, the digital signal '0' may be output by performing an exclusive OR operation on the data bit. Alternatively, if the data bit is a digital signal '1' and the digital signal '0' output from the syndrome decoding unit 220, the digital signal '1' may be output by performing an exclusive OR operation on the data bit.

The error detection unit 240 receives the syndrome data G output from the syndrome generator 210, performs a logical OR operation, and outputs a digital signal '1' or a digital signal '0' as an operation value. For example, the error detection unit 240 includes a logical sum gate 241, and when any one digital signal '1' is input among the syndrome data G input from the syndrome generator 210, the error detection signal, that is, an error signal can be output.

Through this, the error detector 240 performs a logical sum operation on the syndrome data G output from the syndrome generator 210, and if any one bit of the received syndrome data is 1, it can output a signal indicating that an error has occurred. .

The error detection unit 240 may detect that a maximum of two errors occur in a codeword according to a result of an OR reduction operation of syndrome data due to the characteristics of Hamming codes having a minimum Hamming distance of 3.

Here, OR reduction is to perform a OR operation on all bits. For example, This means that the 8 bits output from the second parity module 212 are subjected to a OR operation at the OR gate 241. And, the minimum hamming distance means the minimum number of bits that differ between codewords. If the minimum Hamming distance is 3, single-error correction and double-error detection may be possible.

Therefore, the error detection unit 240 may be used as a function of single-error correction or a function of double-error detection.

Through this, the present invention can operate in a mode of correcting error bits in data bits or in a mode of detecting error bits.

Since the PIM enable unit 250 stores digital signal '0' and digital signal '1', it is controlled by the memory control unit A and sent to the PIM enable switch unit 260 as digital signal '0' or digital signal '1'. ' can be output.

The PIM enable switch unit 260 may vary the signal applied to the memory controller A. The PIM enable switch unit 260 includes a multiplexer (MUX) corresponding to the number of data bits, and when the digital signal '0' is input from the PIM enable unit 250, the error correction unit 230 outputs the output. outputs the correcting bit data (I).

On the other hand, when the digital signal '1' is received from the PIM enable unit 250, the data bit B-2 is output as it is. As described above, the syndrome generator 210, the error correction unit 230, the error detection unit 240, the PIM enable unit 250, and the PIM enable switch unit 260 are limited to the digital devices shown in FIG. 3, It may be formed by being transformed into another semiconductor element within the range of exhibiting the above-mentioned characteristics.

Hereinafter, operations of the components of the present invention will be described in detail with reference to FIGS. 4 to 25 . 4 and 5 are diagrams illustrating codewords used in a memory device capable of dynamically switching between error correction and error detection in an on-die error correction code according to an embodiment of the present invention, and FIGS. 6 to 14 3 is a diagram showing which data bits are received by the first parity module according to the states expressed in binary and the states expressed in binary. 15 is a diagram showing an operating state of the syndrome generating unit of FIG. 7 . 16 to 18 are views showing which data bits are received by each XOR gate of the first parity module of FIG. 19 to 20 are diagrams showing operating states of the syndrome generating unit of FIG. 3 . 21 and 22 are diagrams showing operating states of the syndrome decoding unit of FIG. 3 . 23 is a diagram showing an operating state of the error detection unit of FIG. 3 . 24 and 25 are diagrams illustrating an operating state of the PIM enable switch unit of FIG. 3 .

The code word D-2 written in the memory cell array E becomes a code combining a message and extra information. For example, as shown in FIGS. 4 and 5, the codeword D-2 includes a first parity bit P1, a second parity bit P2, and first data. bit D1, third parity bit P3, second data bit D2 to fourth data bit D4, fourth parity bit P4, and fifth data bit D5 to eleventh. The data bit D11, the 5th parity bit P5, the 12th data bit D12 to the 26th data bit D26, the 6th parit bit P6, and the 27th data bit D27 to the 57th The data bit D57 and the 7th parit bit P7 and the 58th data bit D58 to the 127th data bit D127 and the 57th data bit D57 and the 8th parit bit P8 and the 129th It may be formed of a linear code including data bits D129 to 136th data bits D136. Here, data bits become messages, and parity bits can be redundant information. Here, the parity bit may be positioned at 2^n positions in the order of bits shown in FIG. 4 .

Therefore, for the parity bit, P1 is located in the order of number 1, which is the place of 2^0, P2 is located in the order of number 2, which is the place of 2^1, P3 is located in the order of number 4, which is the place of 2^2, and P4 is located in the order of number 2, which is the place of 2^2. P5 is located in the 8th order of 2^3 place, P5 is located in the 16th order of 2^4 place, P6 is located in the 32nd order of 2^5 place, P7 is located in the 64th order of 2^6 place position, and P8 is located at position 128, which is the position of 2^7.

The first exclusive OR gate (#1XOR Gate) to the eighth exclusive OR gate (#8XOR Gate) of the first parity module 211 are data bits as shown in FIGS. 6 to 14 in the memory cell array E, respectively. can be read. At this time, as shown in FIG. 15, each of the first exclusive OR gate (#1XOR Gate) to the eighth exclusive OR gate (#8XOR Gate) outputs '1' if the number of '1' is odd, and ' If the number of 1' is an even number, '0' can be output. For example, the first exclusive OR gate (#1XOR Gate) to the eighth exclusive OR gate (#8XOR Gate) of the first parity module 211 generate 136-bit data obtained by adding 8-bit parity bits to 128-bit data. When the codeword of is read, the first exclusive OR gate (#1XOR Gate) is D1, D2, D4, D5, D7, D9, D11, D12, D14, D16, D18, D20, D22, D24, D26, D27, D29, D31, D33, D35, D37, D39, D41, D43, D45, D47, D49, D51, D53, D55, D57, D58, D60, D62, D64, D66, D68, D70, D72, D74, D76, D78, D80, D82, D84, D86, D88, D90, D92, D94, D96, D98, D100, D102, D104, D106, D108, D110, D112, D114, D116, D118, D120, D121, D123, D125, D127 are read and 67 digital signals can be input.

The second exclusive OR gate (#2XOR Gate) is D1, D3, D4, D6, D7, D10, D11, D13, D14, D17, D18, D21, D22, D25, D26, D28, D29, D32, D33, D36, D37, D39, D40, D41, D44, D45, D48, D49, D52, D53, D56, D57, D59, D60, D63, D64, D67, D68, D71, D72, D75, D76, D79, D83, D84, D87, D88, D91, D92, D95, D96, D99, D100, D103, D104, D107, D108, D111, D112, D115, D116, D119, D120, D122, D123, D126, 67 digital signals can be input by reading D127.

The third exclusive OR gate (#3XOR Gate) is D2, D3, D4, D8, D9, D10, D11, D15, D16, D17, D18, D20, D22, D23, D24, D25, D23, D24, D25, D26, D30, D31, D32, D33, D38, D40, D41, D46, D47, D48, D49, D54, D55, D56, D57, D61, D62, D64, D69, D70, D71, D72, D77, D78, D79, D80, D85, D86, D87, D88, D93, D94, D95, D96, D101, D102, D103, D104, D109, D110, D111, D112, D117, D118, D119, D120, D124, D125, D126, 67 digital signals can be input by reading D127.

The fourth exclusive OR gate (#4XOR Gate) is D5, D6, D7, D8, D9, D10, D11, D19, D20, D21, D22, D23, D24, D26, D34, D35, D26, D34, D35, D36, D37, D38, D39, D40, D41, D50, D51, D52, D53, D54, D55, D56, D57, D65, D66, D67, D68, D69, D70, D71, D72, D81, D82, D83, D84, D85, D86, D87, D88, D97, D98, D99, D100, D101, D102, D103, D104, D113, D114, D115, D116, D117, D118, D119, D120, D128 are read and 63 digital signals are read. can be entered.

The fifth exclusive OR gate (#5XOR Gate) is D12, D13, D14, D15, D16, D17, D18, D19, D20, D21, D22, D23, D24, D25, D26, D42, D43, D44, D45, D46, D47, D48, D49, D50, D51, D52, D53, D54, D55, D56, D57, D73, D74, D75, D76, D77, D78, D79, D80, D81, D82, D83, D84, D85, D86, D87, D88, D105, D106, D107, D108, D109, D110, D111, D112, D113, D114, D115, D116, D117, D118, D119, D120 are read and 65 digital signals are read. can be entered.

The sixth exclusive OR gate (#6XOR Gate) is D27, D28, D29, D30, D31, D32, D33, D34, D35, D36, D37, D38, D39, D40, D41, D42, D42, D43, D44, D45, D46, D47, D48, D49, D50, D51, D52, D53, D54, D55, D56, D57, D89, D90, D91, D92, D93, D94, D95, D96, D97, D98, D99, D100, D101, D102, D103, D104, D105, D106, D107, D108, D109, D110, D111, D112, D113, D114, D115, D116, D117, D118, D119, D120 are read and 63 digital signals are read. can be entered.

The seventh exclusive OR gate (#7XOR Gate) is D5, D6, D7, D8, D9, D10, D11, D19, D20, D21, D22, D23, D24, D26, D34, D35, D26, D34, D35, D36, D37, D38, D39, D40, D41, D50, D51, D52, D53, D54, D55, D56, D57, D65, D66, D67, D68, D69, D70, D71, D72, D81, D82, D83, D84, D85, D86, D87, D88, D97, D98, D99, D100, D101, D102, D103, D104, D113, D114, D115, D116, D117, D118, D119, D120, D128 are read and 63 digital signals are read. can be entered.

The eighth exclusive OR gate (#8XOR Gate) is D12, D13, D14, D15, D16, D17, D18, D19, D20, D21, D22, D23, D24, D25, D26, D46, D47, D48, D49, D50, D51, D52, D53, D54, D55, D56, D57, D73, D74, D75, D76, D77, D78, D79, D80, D81, D82, D83, D84, D85, D86, D87, D88, D105, D106, D107, D108, D109, D110, D111, D112, D113, D114, D115, D116, D117, D118, D119, D120 are read and 59 digital signals can be input.

Here, the binary numbers of the digits of D1 to D128 are the same as the binary numbers of FIGS. 6 to 14 . And, in this specification, it is assumed that D1 to D128 all become digital signals '0' when no error occurs so that the description of the data bits can be concise and clear. And it is assumed that the error occurs only in one D1 and that the digital signal of D1 is from ‘0’ to ‘1’. As shown in FIG. 19, all of the first exclusive OR gate (#1XOR Gate) to the eighth exclusive OR gate (#8XOR Gate) may output a digital signal '1'.

As shown in (a) of FIG. ) to the eighth exclusive OR gate (#8XOR Gate) and the parity bit (F) read from the memory cell array (E), that is, the signal of the default input shown in the figure, the digital signal '0' can output Accordingly, signals output from the ninth exclusive OR gate (#9XOR Gate) to the sixteenth exclusive OR gate (#16XOR Gate) may output a digital signal '0 0 0 0 0 0 0 0'.

On the other hand, the ninth exclusive OR gate (#9XOR Gate) to the sixteenth exclusive OR gate (#16XOR Gate) of the second parity module 212 are the first exclusive OR gate (# 1XOR Gate) to the 8th exclusive OR gate (#8XOR Gate) and the parity bit (F) read from the memory cell array (E), that is, the default input signal shown in the figure is different from each other, digital Signal '1' can be output. Accordingly, signals output from the ninth exclusive OR gate (#9XOR Gate) to the sixteenth exclusive OR gate (#16XOR Gate) may output a digital signal '1 1 0 0 0 0 0 0'.

As shown in FIG. 21, when the syndrome decoding unit 220 receives the digital signal '0 0 0 0 0 0 0 1 1' from the second parity module 212, it converts the received binary number into a decimal number, '3' may be output, and a digital signal '1' may be output to the third output pod corresponding to the decimal number '3'. And when ‘1 0 0 0 1 0 0 0’ is received, a digital signal ‘1’ can be output to the 128th output pod based on the method of converting binary numbers to decimal numbers. That is, the syndrome decoding unit 220 decodes the syndrome data (G) input to the input side into a decimal number, outputs a digital signal '1' to the output terminal corresponding to the value of the decoded decimal number, and A digital signal '0' can be output to the output terminal at the position.

As shown in FIG. 22, the syndrome decoding unit 220 may apply a digital signal '1' or a digital signal '0' output to the error correcting unit 230.

As shown in FIG. 23, the error detection unit 240 performs a logical sum operation on the syndrome data G output from the syndrome generation unit 210, and if any one of the received syndrome data is 1, it generates a signal indicating that an error has occurred. can be printed out. The error detection unit 240 may detect that a maximum of two errors occur in a codeword according to a result of an OR reduction operation of syndrome data due to the characteristics of Hamming codes having a minimum Hamming distance of 3.

Each of the Y3-th exclusive OR gate (#Y3XOR Gate) to the Y3-th exclusive-OR gate (#Y136XOR Gate) of the error correction unit 230 performs syndrome decoding with data bits read from the memory cell array E, that is, D1 to D128. A signal output from the unit 220 may be received, an exclusive OR operation may be performed, and an erroneous data bit may be corrected and output. For example, as shown in (A) of FIG. 24, the error correcting unit 230 receives a signal '0' from the memory cell array E and the syndrome decoding unit 220 when D1 to D128 come in as normal signals. can receive Then, the received digital signal ‘0’ is subjected to an exclusive OR operation to obtain ‘0000 … 0000' can be output. On the other hand, as shown in (B) of FIG. 24, the error correcting unit 230, when D1 among D1 to D128 comes as an error signal, the Y1-th exclusive OR gate (#Y1XOR Gate) is a memory cell array ( E) Then, the digital signal '1' is received through the Y3 output port of the syndrome decoding unit 220.

The remaining Y5th exclusive OR gate (#Y5XOR Gate) to Y136th exclusive OR gate (#Y136XOR Gate) receive the digital signal '0' through the memory cell array E and the output port of the syndrome decoding unit 220. . At this time, the Y3th exclusive OR gate (#Y3XOR Gate) may perform an exclusive OR operation on the received signal and output a digital signal '0'. The Y5th exclusive OR gate (#Y5XOR Gate) to the Y136th exclusive OR gate (#Y136XOR Gate) also perform an exclusive OR operation on the received signal and output a digital signal '0'. Through this, the error correcting unit 230 receives the position signal to be corrected through the syndrome decoding unit 220, and the data bit with the error is '0000...'. Even if '0000' is entered, it is correctly '0000...'. 0001'.

At this time, the PIM enable switch unit 260, as shown in (A) of FIG. 25, receives correction bit data output from the error correction unit 230 when the digital signal '0' is input from the PIM enable unit 250. (I) '0000 ... 0000' is output. On the other hand, as shown in (B) of FIG. 25, the PIM enable switch unit 260 transmits the uncorrected data bit B-2 as it is when the digital signal '0' is received from the PIM enable unit 250. print out For example, ‘0000 … which is the data bit in error. 0000’ can be output as it is.

In the on-die error correction code of the present invention, in the memory device 1 capable of dynamically switching between error correction and error detection, when the PIM enable signal is a digital signal '0', the PIM enable switch unit 260 corrects data (Corrected data) is output, so it can be used as single-error correction in the same way as before. On the other hand, when the PIM enable signal is a digital signal '1', the PIM enable switch unit 260 outputs the input data as it is and outputs an error signal as it is, quickly detecting the error with only a simplified procedure, and then In this step, erroneous data is processed to be corrected, and the time of data processing can be shortened.

Through this, the memory device 1 capable of dynamically switching error correction and error detection in the on-die error correction code of the present invention includes a syndrome generator 210, a syndrome decoder 220, and an error correction unit in case of general DRAM Read. It is possible to solve the problem that it takes a long time to process the input data because correction data is output only when all of the steps 230 are passed.

In addition, the memory device 1 capable of dynamically switching between error correction and error detection in the on-die error correction code of the present invention simultaneously detects errors of several bits based on the characteristics of the error detection unit 240 shown in FIG. and can show high reliability for error detection of data bits being processed.

In addition, the present invention can be formed in a structure in which only the PIM enable unit 250 and the PIM enable switch unit are added to the existing on-die ECC engine, so that the existing DDR5 SDRAM (Double Data Rate Fifth Synchronous Dynamic Random Access Memory Synchronous Dynamic Random Access Memory), as well as memory to which on-die ECC is applied, and enhances the reusability of the existing on-die ECC engine.

Although the embodiments of the present invention have been described with reference to the accompanying drawings, those skilled in the art to which the present invention pertains can be implemented in other specific forms without changing the technical spirit or essential features of the present invention. you will be able to understand Therefore, it should be understood that the embodiments described above are illustrative in all respects and not restrictive.

[Description of code]

1: Dynamically switchable memory device for error correction and error detection in on-die error correction code

10: Error correction code encoder

110: parity generator

20: Error correction code decoder

210: syndrome generator

220: syndrome decoding unit

221: first parity module 212: second parity module

230: error correction unit

240: error detection unit

241: OR gate

250: PIM enable unit 260: PIM enable switch unit

A: memory control unit B-1, B-2: data bit

C, F: parity bit D-1, D-2: code word

E: memory cell array G: syndrome data

H: Error location bit I: Correction bit data

Claims

A parity bit (C) is generated from the data bit (B-1) input from the memory controller (A), and the memory cell array (E, Cell Array) includes the data bit (B-1) and the parity bit (C). An error correction code encoder (10, Error Correction Code encoder) including a parity generator 110 that writes a code word (D-1), and

Syndrome generation unit for generating syndrome data (G) by reading the code word (D-2) including the data bit (B-2) and parity bit (F) written in the memory cell array (E), and performing an operation ( 210) and a syndrome decoding unit 220 that decodes the syndrome data (G) generated through the syndrome generating unit 210 to generate error location bits (H) indicating the location of error bits;

When the data bit (B-2) and the error location bit (H) generated by the syndrome decoding unit 220 are received from the memory cell array (E), the positions of the data bit (B-2) and the error location bit (H) An error correcting unit 230 that generates corrected bit data (I) by comparing and calculating each bit of each star;

An error detection unit 240 that receives the syndrome data (G) output from the syndrome generator 210, performs a logical sum operation, and outputs a digital signal '1' or a digital signal '0' as an operation value;

A PIM enable unit 250 that includes digital signal '0' and digital signal '1' and is controlled by the memory controller A and outputs either digital signal '0' or digital signal '1';

The data bit (B-2) is received through the memory cell array (E), the corrected bit data (I) is received through the error correction unit 230, and the digital signal '0' is received from the PIM enable unit 250. Alternatively, when receiving any one of the digital signal '1' and receiving the digital signal '0' from the PIM enable unit 250, the corrected bit data (I) output from the error correcting unit 230 is output, and the PIM An on-die error including an error correction code decoder 20 equipped with a PIM enable switch unit 260 that outputs a data bit (B-2) when a digital signal '1' is received from the enable unit 250. A memory device capable of dynamically switching between error correction and error detection in correcting code.
The method of claim 1, wherein the syndrome generator 210,

A memory device capable of dynamically switching between error correction and error detection in an on-die error correction code, which receives a codeword (D-2) from a memory cell array (E) when the memory (1) performs a read operation.
The method of claim 2, wherein the syndrome generator 210,

A first parity module 211 including a plurality of exclusive OR gates (#1 to #8) to read the data bit (B-2) of the codeword (D-2) and calculate a new parity bit (C); ,

A parity bit (F) received through a memory cell array (E) including a plurality of exclusive OR gates (#9 to #16) and a parity bit (C) output from the first parity module 211 A memory device capable of dynamically switching between error correction and error detection in an on-die error correction code, including a second parity module 212 that receives and executes an exclusive OR operation.
According to claim 3,

A memory device capable of dynamically switching between error correction and error detection in an on-die error correction code, wherein the first parity module 211 and the second parity module 212 include the same number of XOR gates.
The method of claim 3, wherein the syndrome decoding unit 220,

After decoding the syndrome data (G) input to the input side into decimal numbers, the digital signal '1' is output to the output terminal corresponding to the value of the decoded decimal number, and the digital signal '0' is output to the output terminal located in the remaining position. A memory device capable of dynamically switching between error correction and error detection in an on-die error correction code, outputting '.
The method of claim 5, wherein the error correction unit 230,

The first input terminal receives the codeword (D-2),

A memory device capable of dynamically switching between error correction and error detection in an on-die error correction code, including an exclusive OR gate for receiving the digital signal output from the syndrome decoding unit 220 and performing an exclusive OR operation on the second input terminal. .
The method of claim 1, wherein the error detection unit 240,

Among the syndrome data (G) input from the syndrome generating unit 210, if any one digital signal '1' is input, an error signal is output in the on-die error correction code including the OR gate 241, which outputs an error signal. Dynamically switchable memory devices for correction and error detection.