CN116524992A - High-capacity high-speed solid-state memory capacity management system - Google Patents
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Abstract
The invention relates to the technical field of solid-state memories, in particular to a high-capacity high-speed solid-state memory capacity management system. The system comprises a flash memory chip, a front-end platform and a rear-end platform, wherein the flash memory chip contains a plurality of basic storage units, the front-end platform establishes a verification partition and a use partition by means of the basic storage units, and an operation basis is provided for the rear-end platform. According to the invention, an operation basis is provided for the post platform through the check partition and the use partition, the post platform checks the data stored in the use partition through the check code stored in the check partition, and errors existing in the data stored in the basic storage unit are timely found out through the check and error correction is performed, so that the stability of the data stored in the basic storage unit is improved.
Description
Technical Field
The invention relates to the technical field of solid-state memories, in particular to a high-capacity high-speed solid-state memory capacity management system.
Background
The solid state memory, namely a Solid State Disk (SSD), mainly adopts a FLASH chip as a storage medium, and the storage principle is as follows:
the solid state disk based on flash memory is a main category of the solid state disk, the internal structure is quite simple, the main body in the solid state disk is a PCB (printed circuit board), the most basic accessories on the PCB are a control chip, a cache chip (part of the low-end hard disk is not provided with the cache chip) and a chip for storing data.
The main control chip is the brain of the solid state disk, and has the functions of reasonably allocating the load of the data on each flash memory chip, and bearing the whole data transfer and connecting the flash memory chip and an external SATA interface.
The chip for storing data is composed of a plurality of basic storage units, the basic storage units store the data in a binary form, and the flash memory of the solid state disk has the problem of limited erasing times, which is also a short-lived problem for many people. Flash is completely erased once, called 1P/E, so the life of flash is in P/E units. The lifetime of a 34nm flash memory chip is about 5000P/E times, while the lifetime of 25nm is about 3000P/E times. With the improvement of SSD firmware algorithm, the new SSD can provide less unnecessary writing quantity. A120G solid state disk is written with 120G files to be calculated as a P/E. Normal use by average users, even if 50G is written every day, P/E is completed once every 2 days, 3000P/E can take 20 years.
Therefore, the problem of the service life of the solid state disk is not solved, but the number of basic storage units is large, so that few basic storage units are inevitably abnormal in the use process, the capacity of the solid state disk is not only influenced, but also the stability of stored data is lowered due to the fact that few basic storage units are abnormal.
Disclosure of Invention
The present invention is directed to a high-speed solid-state memory capacity management system for solving the above-mentioned problems.
In order to achieve the above object, a high-capacity high-speed solid-state memory capacity management system is provided, which comprises a flash memory chip, a front-end platform and a rear-end platform, wherein the flash memory chip contains a plurality of basic storage units, the front-end platform establishes a verification partition and a use partition by means of the basic storage units, and provides an operation basis for the rear-end platform;
and the rear platform checks the data stored in the using partition through the check code stored in the checking partition.
As a further improvement of the technical scheme, the front-end platform comprises a bad detection module and a capacity partition module, wherein the output end of the bad detection module is connected to the input end of the capacity partition module;
the bad inspection module is used for detecting the basic storage unit to obtain the damage condition of the basic storage unit;
and the input end of the capacity partition module receives the damage condition output by the bad detection module, and establishes a check partition and a use partition according to the damage condition.
As a further improvement of the technical scheme, the rear platform comprises a verification module, wherein the verification module generates a verification code for the data stored in the using partition and stores the verification code in the verification partition;
and in the process of later operation, the verification module verifies the data corresponding to the verification module by means of the verification code.
As a further improvement of the technical proposal, the use partition comprises a low-life area and a high-life area;
obtaining a stable basic storage unit and an unstable basic storage unit in the processes of bad inspection and verification;
the check partition and the high-life area are both formed by the stability basic storage units;
the low-longevity area is composed of an unstable base memory cell, which is formed from a check partition and a high-longevity area.
As a further improvement of the technical scheme, the rear platform comprises a prompt module, and the prompt module is connected with the visualization equipment;
after the bad check, prompting is carried out on the unstable basic storage unit by means of a visualization device.
As a further improvement of the technical scheme, the basic storage unit is a floating gate transistor, and the floating gate transistor comprises a substrate, a source electrode and a drain electrode;
a tunnel oxide layer, a floating gate layer, an oxide layer and a control grid are sequentially arranged on the substrate;
the source electrode and the drain electrode are connected to the substrate, and electrons flow from the source electrode to the drain electrode under the action of voltage;
the floating gate layer is surrounded by an insulating layer, and data is written into and erased from the floating gate transistor by charging and discharging electrons from the floating gate layer.
As a further improvement of the technical scheme, the data are checked by the check module by adopting a redundancy check code, and the generation steps of the redundancy check code are as follows:
s1.1, splicing a check code of R bits after a K-bit data code of data, wherein the whole coding length of the check code is N bits, and obtaining a generator polynomial G (x);
s1.2, representing the stored data by using a polynomial C (X), and shifting the C (X) left by R bits to obtain C (X) X2R;
s1.3, dividing C (x) x 2R by a remainder obtained by generating a polynomial G (x), and recognizing the remainder as a check code.
As a further improvement of the technical scheme, the verification module determines the data source while generating the verification code;
the verification module determines that the data needs to be stored in a low-life area/Gao Shouou according to the data source;
and the verification module is used for repairing the lossy data according to the data source assistance.
As a further improvement of the technical scheme, the use of the basic storage units in the low-life area adopts a mean-value balancing algorithm, and the algorithm comprises the following steps:
s2.1, determining a life average value of a basic storage unit in a low-life zone;
s2.2, preferentially using the basic storage units higher than the life average value.
As a further improvement of the technical scheme, the basic storage units higher than the life average value in the step S2.2 are homogenized again to obtain a secondary average value, and the basic storage units higher than the secondary average value are preferentially used;
the life average and the secondary average in the average balancing algorithm are determined each time the underlying storage unit in the low-life region is changed.
Compared with the prior art, the invention has the beneficial effects that:
1. in the high-capacity high-speed solid-state memory capacity management system, an operation basis is provided for a rear platform through a check partition and a use partition, the rear platform checks data stored in the use partition through check codes stored in the check partition, errors existing in the data stored in a basic storage unit are timely found through the check, and error correction is performed, so that the stability of the data stored in the basic storage unit is improved.
2. In the high-capacity high-speed solid-state memory capacity management system, bad check is performed before data is not written, namely, when the flash memory chip is used for the first time, a low-life area possibly does not exist in a using partition at the time, but a high-life area and a check partition are needed to be formed, the capacity obtained at the time is the real capacity of the flash memory chip, and then the capacity of the check partition is determined according to the real capacity, so that the problem that a plurality of reserved check partitions are damaged by a basic storage unit is not needed to be considered, the capacity of the check partition is more adaptive, and unnecessary capacity waste is avoided.
3. In the capacity management system of the high-capacity high-speed solid-state memory, source data of data, namely basic data, are stored in a high-life area, on one hand, the storage stability in the high-life area is high, and on the other hand, the frequency of basic data modification is relatively low, so that the number of times of erasing and writing basic storage units in the high-life area is relatively small, namely, the number of times of verification in the high-life area is reduced.
4. In the high-capacity high-speed solid-state memory capacity management system, edge data with higher modification frequency is stored in a low-life area, the number of modification times of the edge data is large, the modification amount is large, the probability of a plurality of simultaneously modified data in a basic storage unit is improved, the plurality of data can be modified by performing one-time erasing and writing, the number of back-and-forth erasing and writing is reduced, the service life of the basic storage unit is further prolonged, the verification in the low-life area is more compact, the stability of the basic storage unit in the low-life area is not high, the high-density verification can improve the stability of the data, the condition that one-time verification produces effects on the plurality of data can be also generated, and the verification efficiency is improved.
5. In the high-capacity high-speed solid-state memory capacity management system, after the first use of the bad check, the basic memory units of the check partition are periodically subjected to the bad check in the later period, so that the basic memory units, from which electrons easily run out in the bad check, are released, the safety of check codes can be ensured, and the capacities in the check partition are reasonably utilized.
Drawings
FIG. 1 is a block diagram of the internal modules of the front-end and rear-end platforms of the present invention;
FIG. 2 is a schematic diagram of a floating gate transistor according to the present invention;
FIG. 3 is a schematic diagram of the operation principle of the floating gate transistor of the present invention when writing data;
FIG. 4 is a schematic diagram of the operation principle of the floating gate transistor in the data erasing process of the present invention;
FIG. 5 is a flowchart illustrating a redundancy check code generation process according to the present invention;
FIG. 6 is a flowchart illustrating steps of a mean value balancing algorithm according to the present invention;
FIG. 7 is a schematic diagram of a use partition and check partition architecture of the present invention.
The meaning of each reference sign in the figure is:
100. a flash memory chip; 200. a front-end platform; 210. a bad detection module; 220. a capacity partitioning module; 300. a rear platform; 310. a verification module; 320. and a prompt module.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
The chip for storing data is composed of a plurality of basic storage units, the basic storage units store the data in a binary form, and the flash memory of the solid state disk has the problem of limited erasing times, which is also a short-lived problem for many people. Flash is completely erased once, called 1P/E, so the life of flash is in P/E units. The lifetime of a 34nm flash memory chip is about 5000P/E times, while the lifetime of 25nm is about 3000P/E times. With the improvement of SSD firmware algorithm, the new SSD can provide less unnecessary writing quantity. A120G solid state disk is written with 120G files to be calculated as a P/E. Normal use by average users, even if 50G is written every day, P/E is completed once every 2 days, 3000P/E can take 20 years.
Therefore, the problem of the service life of the solid state disk is not solved, but the number of basic storage units is large, so that few basic storage units are inevitably abnormal in the use process, the capacity of the solid state disk is not only influenced, but also the stability of stored data is lowered due to the fact that few basic storage units are abnormal.
To this end, the present invention provides a high-speed solid-state memory capacity management system with a large capacity, as shown in fig. 1, which includes a flash memory chip 100 (i.e., a chip for storing data), wherein the flash memory chip 100 includes a plurality of basic memory units, and the management system further includes a front platform 200 and a back platform 300, wherein the front platform 200 establishes a check partition and a use partition by means of the basic memory units, the check partition is a space reserved for checking, and the larger the space is reserved, the lower the code rate that can be supported by a check code is, the better the debug capability is, because the larger the code distance is, the stronger the error correction capability is, but the larger the data redundancy is, i.e., the code rate is low.
The operation basis is provided for the post platform 300 through the check partition and the use partition, the post platform 300 checks the data stored in the use partition through the check code stored in the check partition, and errors existing in the data stored in the basic storage unit are timely found through the check and error correction is performed, so that the stability of the data stored in the basic storage unit is improved.
In the first embodiment, the post platform 300 includes a verification module 310, where the verification module 310 generates a verification code for the data stored in the usage partition, and stores the verification code in the verification partition;
during the later operation, the verification module 310 verifies the data corresponding to the verification code by means of the verification code.
In addition, the front-end platform 200 includes a bad inspection module 210 and a capacity partition module 220, wherein an output end of the bad inspection module 210 is connected to an input end of the capacity partition module 220;
the bad inspection module 210 is configured to detect the basic storage unit to obtain a damage condition of the basic storage unit;
the input end of the capacity partition module 220 receives the damage condition output by the damage detection module 210, and establishes a check partition and a use partition according to the damage condition.
It should be noted that, in this embodiment, the basic memory cell is a floating gate transistor, and referring to fig. 2, the floating gate transistor includes a substrate, a source and a drain;
a tunnel oxide layer, a floating gate layer, an oxide layer and a control grid are sequentially arranged on the substrate;
the source electrode and the drain electrode are connected to the substrate, and electrons flow from the source electrode to the drain electrode under the action of voltage;
the floating gate layer is surrounded by the insulating layer, electrons are easy to enter and exit, and the floating gate transistor is subjected to data writing and erasing by charging and discharging electrons to the floating gate layer.
During writing operation, as shown in fig. 3, the upper control gate electrode is applied with a positive voltage Vpp to enable electrons to enter the floating gate layer through the insulating layer, and the erasing operation is opposite, as shown in fig. 4, electrons are sucked out of the floating gate layer by applying the substrate with the positive voltage Vpp;
if the written page is written before, the flash must be erased to remove electrons in the floating gate layer, the data is stored in 0 and 1 binary system, and according to the two states of the electrons in the floating gate, the 0 and 1 of the data can be represented, so that the data can be stored; the state with electrons is generally denoted as 0, and the state without electrons is denoted as 1.
When the data is used each time, the data is checked by the check module 310 by adopting the redundancy check code, because the data is likely to be modified in the use process, and the data needs to be erased and rewritten once, which is probably just a critical point of damage of the floating gate transistor, the possibility of abnormality of the data is relatively high, and the normal use of the data can be ensured, as shown in fig. 5, the generation steps of the redundancy check code are as follows:
s1.1, splicing the check code of R bits after the data code of K bits of the data, wherein the whole code length of the check code is N bits, therefore, the code is also called (N, K) code, for a given (N, K) code, a polynomial G (x) with the highest power of N-K=R can be proved to exist, the check code of K bits of information can be generated according to the G (x), and the G (x) is called a generating polynomial of the check code;
s1.2, representing the stored data by using a polynomial C (X), and shifting the C (X) left by R bits to obtain C (X) X2R; (C (x) x 2R) such that the right side of C (x) is free of R bits, which is the position of the check code;
s1.3, dividing C (x) x 2R by a remainder obtained by generating a polynomial G (x), and recognizing the remainder as a check code.
Wherein, the polynomial and binary number have direct corresponding relation: the highest power of X corresponds to the highest bit of the binary number, the following bits correspond to the powers of the polynomials, the power term corresponds to 1, and no power term corresponds to 0. It can be seen that: the highest power of X is R, and R+1 bits are converted into corresponding binary numbers.
The polynomial includes a generator polynomial G (X) and a data polynomial C (X).
If the generator polynomial is G (X) =x4+x3+x+1, it can be converted into binary number 11011.
The data code 101111 can be converted into a polynomial for data of C (X) =x5+x3+x2+x+1.
The generator polynomial is a contract between the receiver and the sender, i.e. a binary number, which remains unchanged throughout the transmission; at the sender, the data is modulo-2 divided by the polynomial using a generator polynomial to generate a check code. The error location is detected and determined by modulo-2 division of the received check code at the receiver using a generator polynomial.
It should be noted that the most significant bit and the least significant bit of the generator polynomial must be 1; when any bit of the data code is wrong, the remainder should be made to be not 0 after the polynomial is generated and divided; when errors occur in different bits, the remainder should be made different; the remainder is continued to be divided and the remainder is looped.
However, neither verification nor degradation of data stability is visible, which results in a situation that the user cannot grasp the data in time, and for this purpose, the back platform 300 further includes a prompt module 320, where the prompt module 320 is connected to the visualization device, so that the verified abnormal data is displayed to the user in a visual manner.
In the second embodiment, the data in the whole using partition is required to be checked, so that the space reserved by the checking partition for checking is definitely increased by large-batch checking, and the storage space in the checking partition cannot be used by a user, so that the capacity of the partition needs to be managed reasonably, as shown in fig. 7, the using partition is divided into a low-life area and a high-life area, and the checking partition and the high-life area are formed by a stability basic storage unit;
the low-life area is formed by an unstable basic storage unit, and the forming source of the low-life area is a check partition sum Gao Shouou;
whether the basic storage unit is stable or not is obtained in the processes of bad checking and checking, wherein:
the bad check is performed before the data is not written, that is, when the flash memory chip 100 is used for the first time, a low-life area may not exist in the partition when the flash memory chip 100 is used (because no damaged floating gate transistor is found in the bad check process), but a high-life area and a check partition need to be formed, the capacity obtained at this time is the real capacity of the flash memory chip 100, and then the capacity of the check partition is determined according to the real capacity, so that the problem that the base storage unit damages the multi-reserved check partition does not need to be considered, the capacity of the check partition is more adaptive, and unnecessary capacity waste is avoided.
Therefore, the bad check is only performed when the flash memory chip 100 is first used, and the verification process is used to determine whether the basic memory cell is damaged later, because the NAND Block has a limitation on the erasing frequency, and when the number exceeds the limit, the Block may not be used: the floating gate layer is not charged with electrons (writing failure), or the electrons in the floating gate layer can easily run out (bit flip, 0- > 1), or the electrons in the floating gate layer can not run out (erasing failure), namely, the damage which can be known by the check code is that only the electrons in the floating gate layer can easily run out, if the basic storage units in the other two cases are not used, the basic storage units are not classified into any subareas, the basic storage units which can easily run out of the floating gate layer are identified as the non-stable basic storage units, the normal basic storage units are the stable basic storage units, and the stable basic storage units also become the non-stable basic storage units along with the increase of the using times, so the forming sources of the low-service-life area are the check subareas and the high-service-life areas.
The data is divided into a high-life area and a low-life area for storage, the source data of the data, namely the basic data, are stored in the high-life area, on one hand, the storage stability in the high-life area is high, and on the other hand, the frequency of basic data modification is relatively low, so that the number of times of erasing and writing basic storage units in the high-life area is relatively small, namely the number of times of verification in the high-life area is reduced.
The method has the advantages that the edge data with higher modification frequency is stored in the low-life area, firstly, the number of modification times of the edge data is large, the modification amount is large, the probability of a plurality of simultaneously modified data in a basic storage unit is improved, the plurality of data can be modified by one-time erasing and writing, the number of times of back-and-forth erasing and writing is reduced, the service life of the basic storage unit is further prolonged, namely, the verification in the low-life area is more compact, the stability of the basic storage unit in the low-life area is not high, the high-density verification can improve the stability of the data, and the condition that one-time verification has an effect on a plurality of data can also occur, so that the verification efficiency is improved.
In addition, the rear platform 300 comprises a prompt module 320, wherein the prompt module 320 is connected with a visual device, and prompts for the non-stable basic storage unit by means of the visual device after the bad check.
In addition, considering that some data is important, such as data to be backed up, the verification module 310 determines the source of the data while generating the verification code;
the verification module 310 determines that the data needs to be stored in a low-life area/Gao Shouou according to the data source, and the data like backup is stored in a high-life area so as to improve the security of the backup data;
the verification module 310 assists in repairing the lossy data according to the data source, and when visual prompt is performed, the source of the lossy data can be determined to assist the user in correcting in time, preferably, the verification module 310 automatically traces the source to find the backup data, then corrects automatically, and if no backup exists, the user needs to correct.
Preferably, the use of basic memory cells in the low-life region employs a mean-balancing algorithm, as shown in FIG. 6, which comprises the following algorithm steps:
s2.1, determining a life average value of a basic storage unit in a low-life zone;
s2.2, preferentially using the basic storage units higher than the life average value, so as to avoid that one or more basic storage units are excessively used, and the basic storage units are damaged rapidly.
Preferably, in S2.2, the basic storage units higher than the life average value are homogenized again to obtain a secondary average value, and the basic storage units higher than the secondary average value are preferentially used, and the re-homogenization is that the life average value is lowered by the basic storage units with lower life, so that the basic storage units higher than the life average value are still quite large, and even though the basic storage units higher than the life average value are preferentially used, the basic storage units with higher life are not used, and thus the basic storage units with higher life are screened out by the secondary average value, the more homogenization times are, the more accurate the screening out is, and the workload is also improved;
preferably, the mean value of life and the secondary mean value in the mean value balancing algorithm are determined each time the basic storage unit in the low-life region is changed, because the mean value is calculated again more typically because a larger difference occurs in the mean value of life once the basic storage unit is increased or decreased.
In the third embodiment, after the first use of the bad check in the present embodiment, the basic storage unit of the check partition is periodically bad checked in the later period, so that the basic storage unit where electrons easily run out in the bad check is released, thus ensuring the security of the check code, and simultaneously rationalizing the capacity in the check partition.
The foregoing has shown and described the basic principles, principal features and advantages of the invention. It will be understood by those skilled in the art that the present invention is not limited to the above-described embodiments, and that the above-described embodiments and descriptions are only preferred embodiments of the present invention, and are not intended to limit the invention, and that various changes and modifications may be made therein without departing from the spirit and scope of the invention as claimed. The scope of the invention is defined by the appended claims and equivalents thereof.
Claims (7)
1. A high-speed solid-state memory capacity management system comprising a flash memory chip (100), said flash memory chip (100) containing a plurality of basic memory cells, characterized by: the system further comprises a front-end platform (200) and a rear-end platform (300), wherein the front-end platform (200) establishes a verification partition and a use partition by means of a basic storage unit, and provides an operation basis for the rear-end platform (300);
the rear platform (300) checks the data stored in the using partition through the check code stored in the checking partition;
the front-end platform (200) comprises a bad inspection module (210) and a capacity partition module (220), wherein the output end of the bad inspection module (210) is connected to the input end of the capacity partition module (220);
the bad inspection module (210) is used for detecting the basic storage unit to obtain the damage condition of the basic storage unit;
the input end of the capacity partition module (220) receives the damage condition output by the bad detection module (210), and a check partition and a use partition are established according to the damage condition;
the rear platform (300) comprises a verification module (310), wherein the verification module (310) generates a verification code for data stored in the using partition, and stores the verification code in the verification partition;
in the process of the later operation, the verification module (310) verifies the data corresponding to the verification module by means of the verification code;
the usage partition comprises a low-life area and a high-life area;
obtaining a stable basic storage unit and an unstable basic storage unit in the processes of bad inspection and verification;
the check partition and the high-life area are both formed by the stability basic storage units;
the low-longevity area is composed of an unstable base memory cell, which is formed from a check partition and a high-longevity area.
2. The high-capacity high-speed solid state memory capacity management system of claim 1, wherein: the rear platform (300) comprises a prompt module (320), and the prompt module (320) is connected with the visualization equipment;
after the bad check, prompting is carried out on the unstable basic storage unit by means of a visualization device.
3. The high-capacity high-speed solid state memory capacity management system of claim 1, wherein: the basic storage unit is a floating gate transistor, and the floating gate transistor comprises a substrate, a source electrode and a drain electrode;
a tunnel oxide layer, a floating gate layer, an oxide layer and a control grid are sequentially arranged on the substrate;
the source electrode and the drain electrode are connected to the substrate, and electrons flow from the source electrode to the drain electrode under the action of voltage;
the floating gate layer is surrounded by an insulating layer, and data is written into and erased from the floating gate transistor by charging and discharging electrons from the floating gate layer.
4. The high-capacity high-speed solid state memory capacity management system of claim 1, wherein: the verification module (310) adopts a redundancy check code to verify the data, and the generation steps of the redundancy check code are as follows:
s1.1, splicing a check code of R bits after a K-bit data code of data, wherein the whole coding length of the check code is N bits, and obtaining a generator polynomial G (x);
s1.2, representing the stored data by using a polynomial C (X), and shifting the C (X) left by R bits to obtain C (X) X2R;
s1.3, dividing C (x) x 2R by a remainder obtained by generating a polynomial G (x), and recognizing the remainder as a check code.
5. The high-capacity high-speed solid state memory capacity management system of claim 1, wherein: the verification module (310) determines a data source while generating a verification code;
the verification module (310) determines that the data needs to be stored in a low-life area/Gao Shouou according to the data source;
the verification module (310) assists in repairing the lossy data according to the source of the data.
6. The high-capacity high-speed solid state memory capacity management system of claim 5, wherein: the use of the basic storage units in the low-life area adopts a mean value balance algorithm, and the algorithm comprises the following steps:
s2.1, determining a life average value of a basic storage unit in a low-life zone;
s2.2, preferentially using the basic storage units higher than the life average value.
7. The high-capacity high-speed solid state memory capacity management system of claim 6, wherein: homogenizing the basic storage units higher than the service life average value in the step S2.2 again to obtain a secondary average value, and preferentially using the basic storage units higher than the secondary average value;
the life average and the secondary average in the average balancing algorithm are determined each time the underlying storage unit in the low-life region is changed.
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