WO2023097580A1 - 集成电路的寿命预测方法、装置及计算机可读存储介质 - Google Patents

集成电路的寿命预测方法、装置及计算机可读存储介质 Download PDF

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WO2023097580A1
WO2023097580A1 PCT/CN2021/134872 CN2021134872W WO2023097580A1 WO 2023097580 A1 WO2023097580 A1 WO 2023097580A1 CN 2021134872 W CN2021134872 W CN 2021134872W WO 2023097580 A1 WO2023097580 A1 WO 2023097580A1
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integrated circuit
duration
lifetime
aging
tested
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PCT/CN2021/134872
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English (en)
French (fr)
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赛高乐
欧勇盛
段圣宇
王志扬
徐升
熊荣
刘超
江国来
郑雷雷
冯伟
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中国科学院深圳先进技术研究院
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Priority to PCT/CN2021/134872 priority Critical patent/WO2023097580A1/zh
Publication of WO2023097580A1 publication Critical patent/WO2023097580A1/zh

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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/20—Design optimisation, verification or simulation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2119/00—Details relating to the type or aim of the analysis or the optimisation
    • G06F2119/02—Reliability analysis or reliability optimisation; Failure analysis, e.g. worst case scenario performance, failure mode and effects analysis [FMEA]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2119/00—Details relating to the type or aim of the analysis or the optimisation
    • G06F2119/08—Thermal analysis or thermal optimisation

Definitions

  • the present application relates to the technical field of integrated circuits, in particular to a life prediction method, device and computer-readable storage medium for integrated circuits.
  • Integrated circuit applications are ubiquitous in life. In civil, commercial, military and other fields, integrated circuits are often key components to maintain the normal operation of various systems. As the market demand for high-performance chips has been greatly reduced in the production process of integrated circuits, the aging mechanism of integrated circuits has been significantly enhanced, and the service life of digital integrated circuits with a production process below 65nm has been significantly reduced. As a result, the durability of integrated circuits is facing severe challenges.
  • the life prediction results that do not take the actual operating conditions as a reference can only be used as a reference standard when optimizing the circuit, and cannot predict the life of specific equipment that requires it.
  • adding a temperature sensor and counting the running programs and data specifically for the life prediction of the circuit will greatly increase the manufacturing cost of the integrated circuit and waste huge computing resources. Therefore, it is impractical to use full real-time data to estimate the life of the circuit.
  • the present application mainly provides a method, device and computer-readable storage medium for life prediction of integrated circuits, which solves the problem of low accuracy of life prediction of integrated circuits in the prior art.
  • the first aspect of the present application provides a method for predicting the life of an integrated circuit, including: obtaining the estimated life of a reference integrated circuit, and obtaining a first duration corresponding to the reference integrated circuit in a set aging stage; Obtaining the second duration corresponding to the same aging stage of the integrated circuit under test; predicting the lifetime of the integrated circuit under test according to the estimated lifetime, the first duration, and the second duration; wherein, the The reference integrated circuit and the integrated circuit to be tested are integrated circuits of the same specification, the reference integrated circuit and the integrated circuit to be tested include multiple aging stages, and the multiple aging stages of the reference integrated circuit are the same as the Multiple aging stages of the integrated circuit to be tested correspond one to one, and the maximum power supply voltages corresponding to the aging stages are the same.
  • the second aspect of the present application provides an integrated circuit life prediction device, including: an acquisition module, used to obtain the estimated life of the reference integrated circuit, the first-order corresponding to the reference integrated circuit in the set aging stage A duration, and a second duration corresponding to the same aging stage of the integrated circuit to be tested; a lifetime prediction module, configured to predict the duration of the IC to be tested according to the estimated lifetime, the first duration, and the second duration Measuring the lifetime of integrated circuits.
  • the third aspect of the present application provides an integrated circuit life prediction device, including a processor and a memory coupled to each other; a computer program is stored in the memory, and the processor is used to execute the computer program In order to realize the integrated circuit lifetime prediction method provided in the first aspect above.
  • the fourth aspect of the present application provides a computer-readable storage medium, the computer-readable storage medium stores program data, and when the program data is executed by a processor, the integrated circuit provided by the above-mentioned first aspect is implemented. Life Prediction Methods.
  • the beneficial effects of the present application are: different from the situation of the prior art, the present application first obtains the estimated life of the reference integrated circuit, the first duration corresponding to the set aging stage of the reference integrated circuit, and obtains the integrated circuit to be tested in the same The second duration corresponding to the aging stage; then predict the life of the integrated circuit to be tested according to the estimated life, the first duration, and the second duration; wherein, the reference integrated circuit and the integrated circuit to be tested are integrated circuits of the same specification, and the reference integrated circuit
  • the circuit and the integrated circuit to be tested include multiple aging stages, and the multiple aging stages of the reference integrated circuit correspond to the multiple aging stages of the integrated circuit to be tested, and the maximum power supply voltages corresponding to the aging stages are the same.
  • the duration of the integrated circuit in the aging stage can reflect the actual operating conditions.
  • the life of the IC to be tested can be predicted by referring to the corresponding aging phase of the IC and the IC to be tested, and by referring to the estimated life of the IC. In this process, only a small amount of Real-time information effectively simplifies the life prediction process and improves the accuracy of prediction results.
  • FIG. 1 is a schematic diagram of soft errors occurring before and after aging of the integrated circuit provided by the present application
  • FIG. 2 is a schematic flow diagram of an embodiment of an integrated circuit lifetime prediction method provided by the present application.
  • Fig. 3 is a structural block diagram of the voltage regulation system provided by the present application.
  • Fig. 4 is a schematic diagram of the integrated circuit provided by the application to convert the power supply voltage mechanism under the voltage regulation system
  • Fig. 5 is a schematic diagram of supply voltage changes in different aging stages provided by the present application.
  • FIG. 6 is a schematic flow diagram of an embodiment of step S11 provided by the present application.
  • FIG. 7 is a schematic structural block diagram of an embodiment of an integrated circuit lifetime prediction device provided by the present application.
  • FIG. 8 is a schematic structural block diagram of another embodiment of an integrated circuit lifetime prediction device provided by the present application.
  • Fig. 9 is a schematic block diagram of an embodiment of a computer-readable storage medium provided by the present application.
  • first and second in this application are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly specifying the number of technical features shown. Thus, the features defined as “first” and “second” may explicitly or implicitly include at least one of these features. Furthermore, the terms “include” and “have”, as well as any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device comprising a series of steps or units is not limited to the listed steps or units, but optionally also includes unlisted steps or units, or optionally further includes For other steps or units inherent in these processes, methods, products or apparatuses.
  • FIG. 1 is a schematic diagram of soft errors caused by the aging effect of integrated circuits provided in this application.
  • the aging of the integrated circuit will cause the circuit propagation delay to increase.
  • the purpose of this application is to predict the time required for the propagation delay of integrated circuits to increase due to aging and cause the propagation delay to be greater than the system clock cycle. It is to predict the time required for the circuit to begin to fail due to soft errors due to the aging effect of the circuit after it has been used. , that is, integrated circuit lifetime prediction.
  • FIG. 2 is a schematic flow diagram of an embodiment of a method for predicting the lifetime of an integrated circuit provided in the present application. It should be noted that this embodiment is not limited to the flow sequence shown in FIG. 2 if substantially the same result is obtained. This embodiment includes the following steps:
  • Step S11 Obtain the estimated lifetime of the reference integrated circuit, and acquire the first duration corresponding to the set aging stage of the reference integrated circuit.
  • the reference integrated circuit and the integrated circuit to be tested are integrated circuits of the same specification
  • the reference integrated circuit and the integrated circuit to be tested include multiple aging stages, and the multiple aging stages of the reference integrated circuit and the multiple aging stages of the integrated circuit to be tested One-to-one correspondence, and the maximum supply voltage corresponding to the aging stage is the same.
  • both the reference integrated circuit and the integrated circuit under test are equipped with a voltage regulation system and soft error monitoring sensors, and multiple aging stages are obtained according to the adjustment of the maximum supply voltage by the voltage regulation system.
  • the life cycle of the circuit can be divided into aging stages using the period of maximum operating voltage.
  • the aging effect of the digital integrated circuit equipped with a voltage adjustment system will increase the propagation delay gradually, when the maximum voltage cannot satisfy the condition that the propagation delay is less than the system clock period , then increase the maximum supply voltage. Therefore, each maximum supply voltage can represent an aging stage.
  • 1, 2, 3, 4, 5 respectively represent different aging stages of 5 different maximum supply voltages (V1, V2, V3, V4, V5), and each aging stage of the integrated circuit corresponds to a duration.
  • the integrated circuit to be tested is the prediction object, and the ultimate purpose of this application is to predict the life of the integrated circuit to be tested.
  • Step S12 Obtain the second duration corresponding to the same aging stage of the integrated circuit under test.
  • the maximum supply voltage is the same as the maximum supply voltage of the set aging stage selected in step S11.
  • Step S13 Predict the lifetime of the integrated circuit to be tested according to the estimated lifetime, the first duration and the second duration.
  • the life of the integrated circuit to be tested can be obtained according to the relationship between the ratio of the estimated life to the life of the integrated circuit to be tested and the ratio of the first duration to the second duration.
  • the lifetime of the integrated circuit under test is calculated according to the following formula:
  • LifeTime est is the lifetime of the integrated circuit to be tested
  • LifeTime ref is the estimated lifetime
  • t est is the second duration
  • t ref is the first duration
  • the aging degree of integrated circuits is determined by the average temperature of the chip during operation, the input duty ratio of each component, the voltage difference between the gate and the source, the design size of the components, and the total operating time. Among them, only the component size and voltage are determined under the preset operating conditions, and the temperature, duty ratio, and operating time are mostly related to the environment and user habits.
  • the influence of integrated circuit NBTI aging effect on circuit propagation delay can be expressed by the following formula:
  • ⁇ D NBTI K ⁇ D 0 ⁇ n t n
  • ⁇ D NBTI represents the propagation delay increased due to NBTI
  • K is a constant at a specific system voltage and temperature
  • D 0 represents the propagation delay of the circuit at zero time without aging
  • ⁇ represents the duty ratio of a single original input
  • t Indicates the total running time of the integrated circuit
  • n is a constant (usually 0.16).
  • the voltage adjustment system adjusts the power supply voltage of the integrated circuit according to the actual operation of the integrated circuit, as shown in Figure 4. Therefore, the effective information that the voltage regulation system can provide is the voltage and the running time.
  • the parameters that determine the aging degree of the integrated circuit include the average temperature of the component operation, the duty cycle and the component design size.
  • This application uses the method of comparing with reference to integrated circuits, which can offset the uncertainty of other influencing factors. Specifically, due to the influence of process deviations during IC production, the propagation delays of two ICs with the same design will be different after production, and therefore, the safety margin reserved for the aging mechanism will also be different. Therefore, if we compare the propagation delays of two identical integrated circuits (C1 and C2) under different environments and usage habits due to NBTI:
  • Constant NBTI is the ratio of the safety margin between two integrated circuits, which is a fixed constant after production. In the same way, the propagation delay of the two circuits at time zero is also constant. In addition, the usage habits ( ⁇ ) and operating environment (K) of the same circuit itself are the same because the application scenario has not changed, namely:
  • K C1 and K C2 are the operating environment parameters of the two integrated circuits respectively, are the propagation delays of the two integrated circuits at time zero, are the customary parameters of the two integrated circuits, are the runtimes of the two integrated circuits, respectively.
  • the average temperature, duty cycle, and component design dimensions of the circuit can be calculated using the reference integrated circuit data with known lifetime, namely:
  • t C1 and t C2 are respectively the running time of two integrated circuits with the same specifications, and A is a constant. From this, it can be obtained that the time ratio of two same integrated circuits passing through the same aging stage is also a constant A, that is:
  • ⁇ t C1 and ⁇ t C2 are respectively the time lengths corresponding to the same aging stage of the two integrated circuits.
  • a reference integrated circuit with a known lifetime can be used for lifetime prediction.
  • FIG. 6 is a schematic block diagram of an embodiment of step S11 provided in the present application. It should be noted that this embodiment is not limited to the flow sequence shown in FIG. 6 if substantially the same result is achieved. This embodiment includes the following steps:
  • Step S111 Carry out an aging test on the reference integrated circuit, record the duration corresponding to each aging stage, and record the total working duration of the reference integrated circuit.
  • a reference integrated circuit is configured with a voltage adjustment system, and an aging test is performed to obtain multiple aging stages, and the duration and maximum supply voltage of each aging stage can be recorded.
  • Step S112 Select one of the aging stages as the set aging stage, use the duration corresponding to the set aging stage as the first duration, and use the total working hours as the estimated lifetime.
  • the selection of the set aging stage can be selected according to the preset voltage, specifically, the aging stage corresponding to the maximum power supply voltage and the preset voltage is selected as the preset aging stage, and the duration corresponding to the preset aging stage is used as the first duration. , and the total working hours are used as the estimated life expectancy.
  • an aging stage that is the same as the maximum power supply voltage of the set aging stage can be selected, and the duration of the aging stage is used as the second duration.
  • this application combines integrated circuit life prediction technology and voltage adjustment system, and uses the reference integrated circuit with the same known aging detailed data as the integrated circuit to be tested to operate at the same aging stage as the integrated circuit to be tested The life cycle of the integrated circuit is compared and analyzed, and then the life cycle of the integrated circuit can be accurately predicted through the limited real-time information provided by the voltage regulation system.
  • the present application greatly saves the manufacturing cost of the integrated circuit and reduces the occupation of computing resources.
  • the present application greatly reduces the cost and complexity in the process of building an integrated circuit aging prediction system.
  • FIG. 7 is a schematic structural block diagram of an embodiment of an integrated circuit lifetime prediction device according to the present application.
  • the integrated circuit life prediction device 100 includes an acquisition module 110 and a life prediction module 120, wherein the acquisition module 110 is used to obtain the estimated life of the reference integrated circuit, the first duration corresponding to the set aging stage of the reference integrated circuit, and the integrated circuit to be tested.
  • the second duration corresponding to the same aging stage of the circuit, the lifetime prediction module 120 is used to predict the lifetime of the integrated circuit under test according to the estimated lifetime, the first duration and the second duration.
  • the multiple aging stages are obtained according to the adjustment of the maximum supply voltage by the voltage adjustment system.
  • the integrated circuit life prediction device 100 may also include a test module (not shown in the figure), which is used to perform an aging test on the reference integrated circuit, record the time corresponding to each aging stage, and record the total working time of the reference integrated circuit, and obtain
  • the module 110 can also be used to select one of the aging stages as the set aging stage, obtain the events experienced in the set aging stage as the first duration, and obtain the total working hours as the estimated lifetime.
  • the lifetime prediction module 120 is further used to obtain the lifetime of the IC under test according to the ratio of the estimated lifetime to the lifetime of the IC under test, and the ratio of the first duration to the second duration.
  • FIG. 8 is a schematic structural block diagram of another embodiment of an integrated circuit lifetime prediction device of the present application.
  • the integrated circuit lifetime prediction device 200 includes a processor 210 and a memory 220 coupled to each other.
  • the computer program is stored in the memory 220, and the processor 210 is configured to execute the computer program to implement the integrated circuit lifetime prediction method described in the above embodiments.
  • the memory 220 can be used to store program data and modules, and the processor 210 executes various functional applications and data processing by running the program data and modules stored in the memory 220 .
  • the memory 220 may mainly include a program storage area and a data storage area, wherein the program storage area may store an operating system, an application program (such as a data processing function) required by at least one function, etc.;
  • the data created by the use of 200 (such as the life data of the reference integrated circuit, the maximum voltage of the reference integrated circuit at each aging stage and the corresponding duration data, the aging stage data of the integrated circuit to be tested, etc.) and the like.
  • the memory 220 may include a high-speed random access memory, and may also include a non-volatile memory, such as at least one magnetic disk storage device, flash memory device, or other volatile solid-state storage devices.
  • the memory 220 may further include a memory controller to provide the processor 210 with access to the memory 220 .
  • the disclosed methods and devices may be implemented in other ways.
  • the various embodiments of the integrated circuit life prediction device 200 described above are only illustrative.
  • the division of the modules or units is only a logical function division, and there may be other division methods in actual implementation.
  • several units or components may be combined or integrated into another system, or some features may be omitted, or not implemented.
  • the mutual coupling or direct coupling or communication connection shown or discussed may be through some interfaces, and the indirect coupling or communication connection of devices or units may be in electrical, mechanical or other forms.
  • the units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place, or may be distributed to multiple network units. Part or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.
  • each functional unit in each embodiment of the present application may be integrated into one processing unit, each unit may exist separately physically, or two or more units may be integrated into one unit.
  • the above-mentioned integrated units can be implemented in the form of hardware or in the form of software functional units.
  • the integrated unit is realized in the form of a software function unit and sold or used as an independent product, it can be stored in a computer-readable storage medium.
  • the technical solution of the present application is essentially or part of the contribution to the prior art or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium .
  • FIG. 9 is a schematic block diagram of the structure of an embodiment of a computer-readable storage medium of the present application.
  • the computer-readable storage medium 300 stores program data 310, and when the program data 310 is executed, each implementation of the above-mentioned integrated circuit life prediction method is realized. example steps.
  • the computer-readable storage medium 300 can be a U disk, a mobile hard disk, a read-only memory (ROM, Read-Only Memory), a random access memory (RAM, Random Access Memory), a magnetic disk or an optical disk, etc., which can store program codes. medium.

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Abstract

一种集成电路的寿命预测方法、装置及计算机可读存储介质。该方法包括：获取参照集成电路的预估寿命，以及获取参照集成电路在设定老化阶段对应的第一时长（S11）；获取待测集成电路在相同的老化阶段对应的第二时长（S12）；根据预估寿命、第一时长以及第二时长，预测待测集成电路的寿命（S13）；其中，参照集成电路与待测集成电路为同种规格的集成电路，参照集成电路和测集成电路包括多个老化阶段，参照集成电路的多个老化阶段与待测集成电路的多个老化阶段一一对应，且相对应老化阶段的最大供电电压相同。通过上述方式，本方法能够简化集成电路寿命预测方式，并提高预测结果的准确度。

Description

集成电路的寿命预测方法、装置及计算机可读存储介质 【技术领域】
本申请涉及集成电路技术领域，特别是涉及集成电路的寿命预测方法、装置及计算机可读存储介质。
【背景技术】
集成电路应用在生活中无处不在，在民用、商用、军事等领域，集成电路常常是维持各个系统正常工作的关键元件。集成电路生产工艺随着市场对高性能芯片的需求大幅降低，随之而来的是集成电路老化机制作用的明显增强，并在对65nm以下生产工艺的数字集成电路造成明显的使用寿命缩减，这导致集成电路耐用性面临着严峻的挑战。
现有的老化机制模型通过假设集成电路在特定使用情况下对其寿命进行预测，但电路实际的运行情况往往与预设情况有所不同。电路老化的速度由运行中的温度、空占比、电压、元件尺寸以及运行时长来决定。其中，运行温度和空占比与设备运行温度与其所处的环境、工作强度及应用领域有关，这些因素在设备投入应用前无法预估。
因此，不把实际运行状况作为参考的寿命预测结果只可作为在对电路优化时的参考标准，无法对有需求的具体设备进行寿命预测。然而，专门为电路的寿命预测加入温度传感器和对所运行的程序与数据进行统计将大大增加集成电路制造成本以及浪费巨大的计算资源。因此，运用全实时数据对电路的寿命进行预估是不切实际的。
【发明内容】
本申请主要提供一种集成电路的寿命预测方法、装置及计算机可读存储介质，解决了现有技术中集成电路寿命预测的准确度低的问题。
为解决上述技术问题，本申请第一方面提供了一种集成电路寿命预测方法，包括：获取参照集成电路的预估寿命，以及获取所述参照集成电路在设定老化阶段对应的第一时长；获取待测集成电路在相同的所述老化阶段对应的第二时长；根据所述预估寿命、所述第一时长以及所述 第二时长，预测所述待测集成电路的寿命；其中，所述参照集成电路与所述待测集成电路为同种规格的集成电路，所述参照集成电路和所述待测集成电路包括多个老化阶段，所述参照集成电路的多个老化阶段与所述待测集成电路的多个老化阶段一一对应，且相对应老化阶段的最大供电电压相同。
为解决上述技术问题，本申请第二方面提供了一种集成电路寿命预测装置，包括：获取模块，用于获取参照集成电路的预估寿命、所述参照集成电路在设定老化阶段对应的第一时长、以及待测集成电路在相同的所述老化阶段对应的第二时长；寿命预测模块，用于根据所述预估寿命、所述第一时长以及所述第二时长，预测所述待测集成电路的寿命。
为解决上述技术问题，本申请第三方面提供了一种集成电路寿命预测装置，包括相互耦接的处理器和存储器；所述存储器中存储有计算机程序，所述处理器用于执行所述计算机程序以实现上述第一方面提供的集成电路寿命预测方法。
为解决上述技术问题，本申请第四方面提供了一种计算机可读存储介质，计算机可读存储介质存储有程序数据，所述程序数据被处理器执行时，实现上述第一方面提供的集成电路寿命预测方法。
本申请的有益效果是：区别于现有技术的情况，本申请首先获取参照集成电路的预估寿命、参照集成电路在设定老化阶段对应的第一时长，以及获取待测集成电路在相同的老化阶段对应的第二时长；然后根据预估寿命、第一时长以及第二时长，预测待测集成电路的寿命；其中，参照集成电路与待测集成电路为同种规格的集成电路，参照集成电路和待测集成电路包括多个老化阶段，参照集成电路的多个老化阶段与待测集成电路的多个老化阶段一一对应，且相对应老化阶段的最大供电电压相同。由于参照集成电路和待测集成电路为同种规格的集成电路，集成电路在老化阶段的时长能够侧面反映出实际运行情况，参照集成电路和待测集成电路在同一老化阶段的时长与寿命之间存在着一定的关系，可以通过参照集成电路和待测集成电路相对应的老化阶段的时长，以及参照集成电路的预估寿命，预测待测集成电路的寿命，这个过程中，只用 到了少量的实时信息，有效简化寿命预测过程，并提高了预测结果的准确度。
【附图说明】
为了更清楚地说明本申请实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。其中：
图1是本申请提供的集成电路在老化前后出现软错误的示意图；
图2是本申请提供的集成电路寿命预测方法一实施例的流程示意框图；
图3是本申请提供的电压调整系统结构框图；
图4是本申请提供的集成电路在电压调整系统下转换供电电压机制的示意图；
图5是本申请提供的不同老化阶段的供电电压变化示意图；
图6是本申请提供的步骤S11一实施例的流程示意框图；
图7是本申请提供的集成电路寿命预测装置一实施例的结构示意框图；
图8是本申请提供的集成电路寿命预测装置另一实施例的结构示意框图；
图9是本申请提供的计算机可读存储介质一实施例的结构示意框图。
【具体实施方式】
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅是本申请的一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
本申请中的术语“第一”、“第二”仅用于描述目的，而不能理解 为指示或暗示相对重要性或者隐含指明所示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括至少一个该特征。此外，术语“包括”和“具有”以及他们任何形变，意图在于覆盖不排他的包含。例如包含了一系列步骤或单元的过程、方法、系统、产品或设备没有限定于已列出的步骤或单元，而是可选地还包括没有列出的步骤或单元，或可选地还包括对于这些过程、方法、产品或设备固有的其它步骤或单元。
在本文中提及“实施例”意味着，结合实施例描述的特定特征、结构或特性可以包含在本申请的至少一个实施例中。在说明书中的各个位置出现该短语不一定均是指相同的实施例，也不是与其它实施例互斥的独立的或备选的实施例。本领域技术人员显式地和隐式地理解是，本文所描述的实施例可以与其他实施例结合。
请参阅图1，图1是本申请提供的集成电路老化效应引发软错误的示意图。集成电路因老化将引起电路传播性延迟的增加，当电路传播性延迟大于系统时钟周期时，将导致电路中的寄存器的错误采样，而进一步导致该电路的失效。本申请旨在预测集成电路因老化而引起传播性延迟增长而导致传播性延迟大于系统时钟周期所需时间，是预测电路开始使用后因电路老化效应出现软错误而导致电路开始失效所需要的时间，即集成电路寿命预测。
请参阅图2，图2是本申请提供的集成电路寿命预测方法一实施例的流程示意框图。需注意的是，若有实质上相同的结果，本实施例并不以图2所示的流程顺序为限。本实施例包括以下步骤：
步骤S11：获取参照集成电路的预估寿命，以及获取参照集成电路在设定老化阶段对应的第一时长。
其中，参照集成电路与待测集成电路为同种规格的集成电路，参照集成电路和待测集成电路包括多个老化阶段，参照集成电路的多个老化阶段与待测集成电路的多个老化阶段一一对应，且相对应老化阶段的最大供电电压相同。
具体而言，参照集成电路和待测集成电路均配有电压调整系统和软 错误监测传感器，多个老化阶段则是根据电压调整系统对最大供电电压的调整而得到。
请参阅图3，在流水线式的数字集成电路中，两数据处理阶段电路中的关键路径装有软错误监测传感器，电压调整系统在系统出现软错误后利用提高供电电压缩短传播性延迟来避免软错误的发生，如图4所示。
因此，在配有电压调整系统的集成电路中，电路的生命周期可利用最大运行电压的时段分为多个老化阶段。如图5所示，配有电压调整系统的数字集成电路使用时间的延长，老化效应会使传播性延迟慢慢升高，当该最大电压下无法满足传播性延时小于系统时钟周期的条件时，则提高最大供电电压。故，每个最大供电电压皆可以代表一个老化阶段。图5中，①、②、③、④、⑤分别代表5个不同最大供电电压(V1、V2、V3、V4、V5)的不同老化阶段，集成电路的每个老化阶段均对应一时长。
待测集成电路即预测对象，本申请的最终目的是对待测集成电路进行寿命预测。
步骤S12：获取待测集成电路在相同的老化阶段对应的第二时长。
在相同的老化阶段，即，待测集成电路的老化阶段中，最大供电电压与步骤S11选择的设定老化阶段的最大供电电压相同的老化阶段。
步骤S13：根据预估寿命、第一时长以及第二时长，预测待测集成电路的寿命。
其中，可根据预估寿命与待测集成电路的寿命比值，与第一时长和第二时长的比值相等的关系，得出待测集成电路的寿命。
具体而言，根据下式计算待测集成电路的寿命：
Figure PCTCN2021134872-appb-000001
其中，LifeTime est为待测集成电路的寿命，LifeTime ref为预估寿命，t est为第二时长，t ref为第一时长。
具体而言，在集成电路的老化程度由芯片运行时的平均温度、各个零部件输入空占比、栅极与源极间的电压差、元件设计尺寸以及运行总时长来决定。其中，在预设的运行条件下只有元件尺寸与电压是确定的， 温度、空占比、运行时长多与环境及用户使用习惯有关。集成电路NBTI老化效应对电路传播延迟的影响可以用如下式子表示：
ΔD NBTI＝K·D 0α nt n
其中，ΔD NBTI表示因NBTI而增加的传播延迟，K为在特定系统电压及温度下的常数，D 0表示电路在零时刻未经老化时的传播延迟，α表示单一原件输入空占比，t表示集成电路的总运行时长，n为常数(通常为0.16)。由此可知，通过电压调整系统可提炼出的有效信息为集成电路的总运行时长t与根据电压变化的而变化的K。
电压调整系统根据集成电路实际运行情况，调整集成电路的供电电压，如图4所示。因此，电压调整系统可提供的有效信息为电压及运行时长。另外，决定集成电路老化程度的参数还有元件运行的平均温度、空占比及元件设计尺寸。
本申请使用参照集成电路对比的方法，可抵消其他影响因素的不确定性。具体而言，由于集成电路生产时工艺偏差的影响，两个相同设计的集成电路在生产之后的传播延迟会有所不同，因此，为老化机制而预留的安全余量亦有所不同。所以，若将两个在不同环境及使用习惯下的相同集成电路(C1和C2)因NBTI而增加的传播延迟比较则有：
Figure PCTCN2021134872-appb-000002
其中，Constant NBTI为两集成电路间安全余量之比，生产后即为固定常数。同理，两电路在零时刻的传播延迟相比亦为常数，另外，同一个电路本身的使用习惯(α)与运行环境(K)因应用场景没有改变而相同，即：
Figure PCTCN2021134872-appb-000003
Figure PCTCN2021134872-appb-000004
其中，K C1、K C2分别是两集成电路的运行环境参数，
Figure PCTCN2021134872-appb-000005
分别是两集成电路在零时刻的传播延迟，
Figure PCTCN2021134872-appb-000006
分别是两集成电路使用习惯参数，
Figure PCTCN2021134872-appb-000007
分别是两集成电路的运行时长。
因此，电路运行的平均温度、空占比、元件设计尺寸皆可运用已知寿命的参照集成电路数据进行推算，即：
Figure PCTCN2021134872-appb-000008
其中，t C1与t C2分别为两个规格相同的集成电路的运行时长，A为常数。由此可得，两同集成电路经过同一老化阶段的时间比意亦为常数A，即：
Figure PCTCN2021134872-appb-000009
其中，Δt C1、Δt C2分别是两集成电路在同一老化阶段对应的时长。
因此，对于寿命未知的待测集成电路，可利用已知寿命的参照集成电路进行寿命预测。
请参阅图6，图6是本申请提供的步骤S11一实施例的流程示意框图。需注意的是，若有实质上相同的结果，本实施例并不以图6所示的流程顺序为限。本实施例包括以下步骤：
步骤S111：对参照集成电路进行老化试验，记录每个老化阶段对应的时长，并记录参照集成电路的总工作时长。
具体而言，对参照集成电路配置电压调整系统，并进行老化试验，得到多个老化阶段，可记录每个老化阶段的时长和最大供电电压。
步骤S112：选择其中一个老化阶段作为设定老化阶段，以设定老化阶段对应的时长作为第一时长，并以总工作时长作为预估寿命。
其中，设定老化阶段的选择可根据预设的电压进行选择，具体是选择最大供电电压与预设电压相对应的老化阶段作为预设老化阶段，该预设老化阶段对应的时长作为第一时长，总工作时长则作为预估寿命。
对于第二时长的获取，则可在待测集成电路的老化阶段中，选定与设定老化阶段的最大供电电压相同的老化阶段，以该老化阶段的时长作为第二时长。
区别于现有技术，本申请将集成电路寿命预测技术和电压调整系统结合起来，利用与待测集成电路设计相同的已知老化详细数据的参照集成电路与待测集成电路在同一老化阶段的运行时长进行比较与分析，进而通过电压调整系统所提供的有限实时信息对集成电路的生命周期做出精确预测。相较于专门为集成电路的寿命预测加入温度传感器和对所运行的程序与数据进行统计的方式，本申请大大节省了集成电路制造成本，并降低了计算资源的占用。
因此，本申请在精准预测集成电路寿命的同时，大大减小了集成电路老化预测系统在搭建过程中的成本与复杂性。
请参阅图7，图7是本申请集成电路寿命预测装置一实施例的结构示意框图。集成电路寿命预测装置100包括获取模块110和寿命预测模块120，其中，获取模块110用于获取参照集成电路的预估寿命、参照集成电路在设定老化阶段对应的第一时长、以及待测集成电路在相同的老化阶段对应的第二时长，寿命预测模块120用于根据预估寿命、第一时长以及第二时长，预测待测集成电路的寿命。其中，多个老化阶段根据电压调整系统对最大供电电压的调整而得到。
其中，集成电路寿命预测装置100还可包括试验模块(图未示出)，用于对参照集成电路进行老化试验，记录每个老化阶段对应的时长，并记录参照集成电路的总工作时长，获取模块110还可用于选择其中一个老化阶段作为设定老化阶段，获取设定老化阶段经历的事件作为第一时长，并获取总工作时长作为预估寿命。
其中，寿命预测模块120还用于根据预估寿命与待测集成电路的寿命比值，与第一时长和第二时长的比值相等的关系，得出待测集成电路的寿命。
关于各模块处理执行的各步骤的具体方式请参照上述本申请集成电路寿命预测方法实施例的各步骤的描述，在此不再赘述。
请参阅图8，图8是本申请集成电路寿命预测装置另一实施例的结构示意框图。该集成电路寿命预测装置200包括相互耦接的处理器210和存储器220，存储器220中存储有计算机程序，处理器210用于执行计算机程序以实现上述各实施例所述的集成电路寿命预测方法。
关于处理执行的各步骤的描述请参照上述本申请集成电路寿命预测方法实施例的各步骤的描述，在此不再赘述。
存储器220可用于存储程序数据以及模块，处理器210通过运行存储在存储器220的程序数据以及模块，从而执行各种功能应用以及数据处理。存储器220可主要包括存储程序区和存储数据区，其中，存储程序区可存储操作系统、至少一个功能所需的应用程序(比如数据处理功能)等；存储数据区可存储根据集成电路寿命预测装置200的使用所创建的数据(比如参照集成电路的寿命数据、参照集成电路在各老化阶段的最大电压数及相应的时长数据、待测集成电路的老化阶段数据等)等。此外，存储器220可以包括高速随机存取存储器，还可以包括非易失性存储器，例如至少一个磁盘存储器件、闪存器件、或其他易失性固态存储器件。相应地，存储器220还可以包括存储器控制器，以提供处理器210对存储器220的访问。
在本申请的各实施例中，所揭露的方法、装置，可以通过其它的方式实现。例如，以上所描述的集成电路寿命预测装置200的各实施例仅仅是示意性的，例如，所述模块或单元的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，例如多个单元或组件可以结合或者可以集成到另一个系统，或一些特征可以忽略，或不执行。另一点，所显示或讨论的相互之间的耦合或直接耦合或通信连接可以是通过一些接口，装置或单元的间接耦合或通信连接，可以是电性，机械或其它的形式。
所述作为分离部件说明的单元可以是或者也可以不是物理上分开的，作为单元显示的部件可以是或者也可以不是物理单元，即可以位于一个地方，或者也可以分布到多个网络单元上。可以根据实际的需要选择其中的部分或者全部单元来实现本实施方式方案的目的。
另外，在本申请各个实施例中的各功能单元可以集成在一个处理单元中，也可以是各个单元单独物理存在，也可以两个或两个以上单元集成在一个单元中。上述集成的单元既可以采用硬件的形式实现，也可以采用软件功能单元的形式实现。
所述集成的单元如果以软件功能单元的形式实现并作为独立的产品销售或使用时，可以存储在一个计算机可读取存储介质中。基于这样的理解，本申请的技术方案本质上或者说对现有技术做出贡献的部分或者该技术方案的全部或部分可以以软件产品的形式体现出来，该计算机软件产品存储在一个存储介质中。
参阅图9，图9为本申请计算机可读存储介质一实施例的结构示意框图，计算机可读存储介质300存储有程序数据310，程序数据310被执行时实现如上述集成电路寿命预测方法各实施例的步骤。
关于处理执行的各步骤的描述请参照上述本申请集成电路寿命预测方法实施例的各步骤的描述，在此不再赘述。
计算机可读存储介质300可以是U盘、移动硬盘、只读存储器(ROM，Read-Only Memory)、随机存取存储器(RAM，Random Access Memory)、磁碟或者光盘等各种可以存储程序代码的介质。
以上所述仅为本申请的实施例，并非因此限制本申请的专利范围，凡是利用本申请说明书及附图内容所作的等效结构或等效流程变换，或直接或间接运用在其他相关的技术领域，均同理包括在本申请的专利保护范围内

Claims (10)

  1. 一种集成电路的寿命预测方法，其特征在于，所述方法包括：
    获取参照集成电路的预估寿命，以及获取所述参照集成电路在设定老化阶段对应的第一时长；
    获取待测集成电路在相同的所述老化阶段对应的第二时长；
    根据所述预估寿命、所述第一时长以及所述第二时长，预测所述待测集成电路的寿命；
    其中，所述参照集成电路与所述待测集成电路为同种规格的集成电路，所述参照集成电路和所述待测集成电路包括多个老化阶段，所述参照集成电路的多个老化阶段与所述待测集成电路的多个老化阶段一一对应，且相对应老化阶段的最大供电电压相同。
  2. 根据权利要求1所述的方法，其特征在于，所述获取参照集成电路的预估寿命，以及获取所述参照集成电路在设定老化阶段对应的第一时长，包括：
    对所述参照集成电路进行老化试验，记录每个老化阶段对应的时长，并记录所述参照集成电路的总工作时长；
    选择其中一个所述老化阶段作为所述设定老化阶段，以所述设定老化阶段对应的时长作为所述第一时长，并以所述总工作时长作为所述预估寿命。
  3. 根据权利要求1所述的方法，其特征在于，所述根据所述预估寿命、所述第一时长以及所述第二时长，预测所述待测集成电路的寿命，包括：
    根据所述预估寿命与所述待测集成电路的寿命比值，与所述第一时长和第二时长的比值相等的关系，得出所述待测集成电路的寿命。
  4. 根据权利要求3所述的方法，其特征在于，所述根据所述预估寿命与所述待测集成电路的寿命比值，与所述第一时长和第二时长的比值相等的关系，得出所述待测集成电路的寿命，包括：
    根据下式计算所述待测集成电路的寿命：
    Figure PCTCN2021134872-appb-100001
    其中，LifeTime est为所述待测集成电路的寿命，LifeTime ref为所述预估寿命，t est为所述第二时长，t ref为所述第一时长。
  5. 根据权利要求1所述的方法，其特征在于，所述多个老化阶段根据电压调整系统对所述最大供电电压的调整而形成。
  6. 一种集成电路寿命预测装置，其特征在于，所述装置包括：
    获取模块，用于获取参照集成电路的预估寿命、所述参照集成电路在设定老化阶段对应的第一时长、以及待测集成电路在相同的所述老化阶段对应的第二时长；
    寿命预测模块，用于根据所述预估寿命、所述第一时长以及所述第二时长，预测所述待测集成电路的寿命。
  7. 根据权利要求6所述的装置，其特征在于，所述装置还包括试验模块，用于对所述参照集成电路进行老化试验，记录每个老化阶段对应的时长，并记录所述参照集成电路的总工作时长；
    所述获取模块还用于选择其中一个所述老化阶段作为所述设定老化阶段，获取所述设定老化阶段经历的事件作为所述第一时长，并获取所述总工作时长作为所述预估寿命。
  8. 根据权利要求6所述的装置，其特征在于，所述寿命预测模块还用于根据所述预估寿命与所述待测集成电路的寿命比值，与所述第一时长和第二时长的比值相等的关系，得出所述待测集成电路的寿命。
  9. 一种集成电路寿命预测装置，其特征在于，所述集成电路寿命预测装置包括相互耦接的处理器和存储器；所述存储器中存储有计算机程序，所述处理器用于执行所述计算机程序以实现如权利要求1-5中任一项所述方法的步骤。
  10. 一种计算机可读存储介质，其特征在于，所述计算机可读存储介质存储有程序数据，所述程序数据被处理器执行时实现如权利要求1-5中任一项所述方法的步骤。
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